Merge branch 'u-boot-ti/master' into 'u-boot-arm/master'
authorAlbert ARIBAUD <albert.u.boot@aribaud.net>
Tue, 1 Jul 2014 13:11:18 +0000 (15:11 +0200)
committerAlbert ARIBAUD <albert.u.boot@aribaud.net>
Tue, 1 Jul 2014 13:11:18 +0000 (15:11 +0200)
442 files changed:
.gitignore
Makefile
README
arch/.gitignore
arch/arc/include/asm/config.h
arch/arm/cpu/arm720t/tegra-common/spl.c
arch/arm/cpu/arm926ejs/kirkwood/cpu.c
arch/arm/cpu/arm926ejs/orion5x/cpu.c
arch/arm/cpu/armv7/am33xx/board.c
arch/arm/cpu/armv7/at91/cpu.c
arch/arm/cpu/armv7/exynos/spl_boot.c
arch/arm/cpu/armv7/mx6/Makefile
arch/arm/cpu/armv7/mx6/ddr.c [new file with mode: 0644]
arch/arm/cpu/armv7/mx6/hab.c
arch/arm/cpu/armv7/omap-common/Makefile
arch/arm/cpu/armv7/omap-common/hwinit-common.c
arch/arm/cpu/armv7/omap-common/omap-cache.c [new file with mode: 0644]
arch/arm/cpu/armv7/omap3/board.c
arch/arm/cpu/armv7/zynq/u-boot.lds
arch/arm/dts/Makefile
arch/arm/dts/am335x-bone-common.dtsi [new file with mode: 0644]
arch/arm/dts/am335x-boneblack.dts [new file with mode: 0644]
arch/arm/dts/am33xx.dtsi [new file with mode: 0644]
arch/arm/dts/dt-bindings/gpio/gpio.h [new file with mode: 0644]
arch/arm/dts/dt-bindings/pinctrl/am33xx.h [new file with mode: 0644]
arch/arm/dts/dt-bindings/pinctrl/omap.h [new file with mode: 0644]
arch/arm/dts/include/dt-bindings [new symlink]
arch/arm/dts/tegra114.dtsi
arch/arm/dts/tegra124.dtsi
arch/arm/dts/tegra20.dtsi
arch/arm/dts/tegra30.dtsi
arch/arm/dts/tps65217.dtsi [new file with mode: 0644]
arch/arm/imx-common/Makefile
arch/arm/imx-common/cpu.c
arch/arm/imx-common/iomux-v3.c
arch/arm/imx-common/sata.c
arch/arm/imx-common/spl.c [new file with mode: 0644]
arch/arm/include/asm/arch-at91/spl.h [deleted file]
arch/arm/include/asm/arch-davinci/spl.h [deleted file]
arch/arm/include/asm/arch-mx35/spl.h [deleted file]
arch/arm/include/asm/arch-mx5/spl.h [deleted file]
arch/arm/include/asm/arch-mx6/hab.h
arch/arm/include/asm/arch-mx6/imx-regs.h
arch/arm/include/asm/arch-mx6/iomux.h
arch/arm/include/asm/arch-mx6/mx6-ddr.h
arch/arm/include/asm/arch-mx6/sys_proto.h
arch/arm/include/asm/arch-tegra114/spl.h [deleted file]
arch/arm/include/asm/arch-tegra124/spl.h [deleted file]
arch/arm/include/asm/arch-tegra20/spl.h [deleted file]
arch/arm/include/asm/arch-tegra30/spl.h [deleted file]
arch/arm/include/asm/atomic.h
arch/arm/include/asm/bitops.h
arch/arm/include/asm/imx-common/iomux-v3.h
arch/arm/include/asm/io.h
arch/arm/include/asm/proc-armv/processor.h
arch/arm/include/asm/processor.h
arch/arm/include/asm/ptrace.h
arch/arm/include/asm/spl.h
arch/arm/lib/board.c
arch/avr32/cpu/cache.c
arch/avr32/include/asm/arch-at32ap700x/cacheflush.h
arch/avr32/include/asm/dma-mapping.h
arch/avr32/lib/board.c
arch/m68k/cpu/mcf532x/cpu_init.c
arch/m68k/cpu/mcf5445x/cpu_init.c
arch/m68k/include/asm/io.h
arch/m68k/include/asm/posix_types.h
arch/m68k/lib/board.c
arch/m68k/lib/bootm.c
arch/microblaze/dts/include/dt-bindings [new symlink]
arch/microblaze/lib/bootm.c
arch/openrisc/cpu/start.S
arch/openrisc/include/asm/spr-defs.h
arch/powerpc/cpu/mpc8260/pci.c
arch/powerpc/cpu/mpc8260/start.S
arch/powerpc/cpu/mpc85xx/cmd_errata.c
arch/powerpc/cpu/mpc85xx/cpu_init.c
arch/powerpc/cpu/mpc85xx/fdt.c
arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c
arch/powerpc/cpu/mpc85xx/t1040_ids.c
arch/powerpc/cpu/mpc85xx/t2080_serdes.c
arch/powerpc/cpu/mpc85xx/t4240_serdes.c
arch/powerpc/cpu/ppc4xx/cpu.c
arch/powerpc/include/asm/config_mpc85xx.h
arch/powerpc/include/asm/fsl_law.h
arch/powerpc/include/asm/fsl_liodn.h
arch/powerpc/include/asm/immap_85xx.h
arch/powerpc/include/asm/processor.h
arch/powerpc/lib/board.c
arch/sandbox/cpu/os.c
arch/sandbox/dts/include/dt-bindings [new symlink]
arch/sandbox/include/asm/bitops.h
arch/sandbox/include/asm/gpio.h
arch/sandbox/include/asm/io.h
arch/sandbox/include/asm/system.h
arch/x86/config.mk
arch/x86/cpu/config.mk
arch/x86/dts/include/dt-bindings [new symlink]
board/Marvell/include/pci.h
board/abilis/tb100/Makefile [new file with mode: 0644]
board/abilis/tb100/tb100.c [new file with mode: 0644]
board/adder/Makefile [deleted file]
board/adder/adder.c [deleted file]
board/adder/u-boot.lds [deleted file]
board/ait/cam_enc_4xx/cam_enc_4xx.c
board/altera/common/sevenseg.c [deleted file]
board/altera/common/sevenseg.h [deleted file]
board/altera/nios2-generic/Makefile
board/amcc/yucca/cmd_yucca.c
board/astro/mcf5373l/fpga.c
board/astro/mcf5373l/mcf5373l.c
board/atmel/at91sam9261ek/at91sam9261ek.c
board/atmel/at91sam9263ek/at91sam9263ek.c
board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c
board/atmel/at91sam9rlek/at91sam9rlek.c
board/compulab/cm_t335/u-boot.lds
board/cray/L1/Makefile
board/denx/m53evk/m53evk.c
board/eltec/elppc/misc.c
board/eltec/mhpc/mhpc.c
board/ep8248/Makefile [deleted file]
board/ep8248/ep8248.c [deleted file]
board/etin/debris/Makefile [deleted file]
board/etin/debris/debris.c [deleted file]
board/etin/debris/flash.c [deleted file]
board/etin/debris/phantom.c [deleted file]
board/etin/kvme080/Makefile [deleted file]
board/etin/kvme080/kvme080.c [deleted file]
board/etin/kvme080/multiverse.c [deleted file]
board/etin/kvme080/multiverse.h [deleted file]
board/freescale/b4860qds/b4860qds.c
board/freescale/m5253demo/flash.c
board/freescale/mpc8260ads/Makefile [deleted file]
board/freescale/mpc8260ads/flash.c [deleted file]
board/freescale/mpc8260ads/mpc8260ads.c [deleted file]
board/freescale/mx28evk/README
board/freescale/mx31ads/u-boot.lds
board/freescale/mx6qsabreauto/mx6dl.cfg [new file with mode: 0644]
board/freescale/mx6sabresd/mx6sabresd.c
board/freescale/p1023rds/p1023rds.c
board/freescale/p1023rds/tlb.c
board/freescale/t208xqds/ddr.h
board/freescale/t208xqds/eth_t208xqds.c
board/freescale/t208xqds/t2080_rcw.cfg
board/freescale/t208xqds/t208xqds.c
board/freescale/t208xrdb/t2080_rcw.cfg
board/freescale/t4qds/eth.c
board/freescale/t4qds/t4240qds.c
board/freescale/t4qds/t4_rcw.cfg
board/freescale/t4rdb/eth.c
board/freescale/t4rdb/t4_rcw.cfg
board/gateworks/gw_ventana/Makefile
board/gateworks/gw_ventana/README
board/gateworks/gw_ventana/eeprom.c [new file with mode: 0644]
board/gateworks/gw_ventana/gw_ventana.c
board/gateworks/gw_ventana/gw_ventana.cfg
board/gateworks/gw_ventana/gw_ventana_spl.c [new file with mode: 0644]
board/gateworks/gw_ventana/ventana_eeprom.h
board/gdsys/405ex/io64.c
board/gdsys/p1022/controlcenterd-id.c
board/gdsys/p1022/controlcenterd.c
board/hidden_dragon/Makefile [deleted file]
board/hidden_dragon/README [deleted file]
board/hidden_dragon/flash.c [deleted file]
board/hidden_dragon/hidden_dragon.c [deleted file]
board/hymod/hymod.c
board/hymod/input.c
board/ispan/Makefile [deleted file]
board/ispan/ispan.c [deleted file]
board/keymile/common/common.c
board/keymile/common/ivm.c
board/matrix_vision/mvblm7/Makefile
board/matrix_vision/mvsmr/Makefile
board/mcc200/auto_update.c
board/pcs440ep/pcs440ep.c
board/psyent/common/AMDLV065D.c
board/quad100hd/Makefile [deleted file]
board/quad100hd/nand.c [deleted file]
board/quad100hd/quad100hd.c [deleted file]
board/rattler/Makefile [deleted file]
board/rattler/rattler.c [deleted file]
board/ronetix/pm9261/pm9261.c
board/ronetix/pm9263/pm9263.c
board/sheldon/simpc8313/Makefile [deleted file]
board/sheldon/simpc8313/README.simpc8313 [deleted file]
board/sheldon/simpc8313/sdram.c [deleted file]
board/sheldon/simpc8313/simpc8313.c [deleted file]
board/ti/am335x/u-boot.lds
board/ttcontrol/vision2/imximage_hynix.cfg
board/zpc1900/Makefile [deleted file]
board/zpc1900/zpc1900.c [deleted file]
boards.cfg
common/Makefile
common/autoboot.c [new file with mode: 0644]
common/board_r.c
common/bootm.c [new file with mode: 0644]
common/bootm_os.c [new file with mode: 0644]
common/bootretry.c [new file with mode: 0644]
common/cli.c [new file with mode: 0644]
common/cli_hush.c [moved from common/hush.c with 99% similarity]
common/cli_readline.c [new file with mode: 0644]
common/cli_simple.c [new file with mode: 0644]
common/cmd_bedbug.c
common/cmd_bootm.c
common/cmd_bootmenu.c
common/cmd_dcr.c
common/cmd_demo.c
common/cmd_disk.c
common/cmd_fat.c
common/cmd_fdc.c
common/cmd_fdt.c
common/cmd_fpga.c
common/cmd_gpio.c
common/cmd_i2c.c
common/cmd_iotrace.c [new file with mode: 0644]
common/cmd_itest.c
common/cmd_md5sum.c
common/cmd_mem.c
common/cmd_mmc.c
common/cmd_nand.c
common/cmd_nvedit.c
common/cmd_pci.c
common/cmd_sandbox.c
common/cmd_sha1sum.c
common/cmd_source.c
common/cmd_ximg.c
common/env_eeprom.c
common/env_embedded.c
common/fdt_support.c
common/hash.c
common/image-fdt.c
common/image-fit.c
common/image-sig.c
common/image.c
common/iotrace.c [new file with mode: 0644]
common/main.c
common/menu.c
common/usb_hub.c
common/xyzModem.c
disk/part.c
disk/part_dos.c
disk/part_efi.c
doc/README.fdt-control
doc/README.mxs
doc/README.scrapyard
doc/driver-model/README.txt
doc/uImage.FIT/beaglebone_vboot.txt [new file with mode: 0644]
doc/uImage.FIT/howto.txt
doc/uImage.FIT/signature.txt
drivers/block/dwc_ahsata.c
drivers/core/device.c
drivers/core/lists.c
drivers/core/root.c
drivers/core/uclass.c
drivers/crypto/ace_sha.c
drivers/ddr/fsl/ctrl_regs.c
drivers/ddr/fsl/interactive.c
drivers/demo/demo-shape.c
drivers/demo/demo-simple.c
drivers/demo/demo-uclass.c
drivers/dfu/dfu.c
drivers/fpga/altera.c
drivers/fpga/xilinx.c
drivers/gpio/gpio-uclass.c
drivers/gpio/sandbox.c
drivers/i2c/kona_i2c.c
drivers/misc/cros_ec_sandbox.c
drivers/mmc/kona_sdhci.c
drivers/mmc/mmc.c
drivers/mmc/rpmb.c
drivers/mtd/nand/Makefile
drivers/mtd/nand/mxs_nand_spl.c [new file with mode: 0644]
drivers/mtd/spi/sf_params.c
drivers/mtd/spi/sf_probe.c
drivers/net/macb.c
drivers/net/phy/phy.c
drivers/net/sh_eth.c
drivers/net/sh_eth.h
drivers/power/pmic/pmic_tps65090.c
drivers/serial/serial_mxc.c
drivers/spi/fsl_espi.c
drivers/spi/soft_spi.c
drivers/usb/gadget/ci_udc.c
drivers/usb/gadget/ci_udc.h
drivers/video/atmel_hlcdfb.c
dts/Makefile
fs/ext4/ext4_common.c
fs/ext4/ext4_write.c
fs/fat/fat_write.c
fs/jffs2/jffs2_1pass.c
include/asm-generic/global_data.h
include/asm-generic/gpio.h
include/autoboot.h [new file with mode: 0644]
include/bootm.h [new file with mode: 0644]
include/bootretry.h [new file with mode: 0644]
include/cli.h [new file with mode: 0644]
include/cli_hush.h [moved from include/hush.h with 93% similarity]
include/command.h
include/common.h
include/config_fallbacks.h
include/configs/Adder.h [deleted file]
include/configs/HIDDEN_DRAGON.h [deleted file]
include/configs/ISPAN.h [deleted file]
include/configs/MPC8260ADS.h [deleted file]
include/configs/MPC8315ERDB.h
include/configs/MPC8536DS.h
include/configs/MPC8569MDS.h
include/configs/MPC8572DS.h
include/configs/P1023RDS.h
include/configs/Rattler.h [deleted file]
include/configs/SIMPC8313.h [deleted file]
include/configs/T1040QDS.h
include/configs/T104xRDB.h
include/configs/T208xQDS.h
include/configs/ZPC1900.h [deleted file]
include/configs/am335x_evm.h
include/configs/atngw100mkii.h
include/configs/bcm28155_ap.h
include/configs/cm_t35.h
include/configs/debris.h [deleted file]
include/configs/embestmx6boards.h
include/configs/ep8248.h [deleted file]
include/configs/ethernut5.h
include/configs/gw_ventana.h
include/configs/ids8313.h
include/configs/imx6_spl.h [new file with mode: 0644]
include/configs/iocon.h
include/configs/kvme080.h [deleted file]
include/configs/m53evk.h
include/configs/mx28evk.h
include/configs/mx6_common.h
include/configs/mx6qsabreauto.h
include/configs/mx6sabresd.h
include/configs/quad100hd.h [deleted file]
include/configs/sandbox.h
include/configs/tb100.h [new file with mode: 0644]
include/configs/tegra-common.h
include/configs/ti_armv7_common.h
include/configs/zynq-common.h
include/dm-demo.h
include/dm.h
include/dm/device-internal.h
include/dm/device.h
include/dm/lists.h
include/dm/root.h
include/dm/test.h
include/dm/uclass-internal.h
include/dm/uclass.h
include/dt-bindings/gpio/gpio.h [new file with mode: 0644]
include/dt-bindings/gpio/tegra-gpio.h [new file with mode: 0644]
include/dt-bindings/interrupt-controller/arm-gic.h [new file with mode: 0644]
include/dt-bindings/interrupt-controller/irq.h [new file with mode: 0644]
include/fat.h
include/fdt_support.h
include/hash.h
include/image.h
include/iotrace.h [new file with mode: 0644]
include/mpc8260.h
include/part.h
include/power/pfuze100_pmic.h
include/tps6586x.h
include/u-boot/rsa-checksum.h [moved from include/rsa-checksum.h with 91% similarity]
include/u-boot/rsa.h [moved from include/rsa.h with 96% similarity]
include/u-boot/sha1.h [moved from include/sha1.h with 100% similarity]
include/u-boot/sha256.h [moved from include/sha256.h with 100% similarity]
lib/Makefile
lib/fdtdec.c
lib/fdtdec_common.c [new file with mode: 0644]
lib/libfdt/fdt_ro.c
lib/lzma/LzmaTools.c
lib/rsa/rsa-checksum.c
lib/rsa/rsa-sign.c
lib/rsa/rsa-verify.c
lib/sha1.c
lib/sha256.c
lib/tpm.c
mkconfig
nand_spl/board/freescale/mpc8315erdb/Makefile [deleted file]
nand_spl/board/freescale/mpc8315erdb/u-boot.lds [deleted file]
nand_spl/board/freescale/mpc8536ds/Makefile [deleted file]
nand_spl/board/freescale/mpc8536ds/nand_boot.c [deleted file]
nand_spl/board/freescale/mpc8569mds/Makefile [deleted file]
nand_spl/board/freescale/mpc8569mds/nand_boot.c [deleted file]
nand_spl/board/freescale/mpc8572ds/Makefile [deleted file]
nand_spl/board/freescale/mpc8572ds/nand_boot.c [deleted file]
nand_spl/board/freescale/p1023rds/Makefile [deleted file]
nand_spl/board/freescale/p1023rds/nand_boot.c [deleted file]
nand_spl/board/sheldon/simpc8313/Makefile [deleted file]
nand_spl/board/sheldon/simpc8313/config.mk [deleted file]
nand_spl/board/sheldon/simpc8313/u-boot.lds [deleted file]
nand_spl/nand_boot.c [deleted file]
nand_spl/nand_boot_fsl_elbc.c [deleted file]
net/net.c
scripts/Makefile.build
scripts/Makefile.host
scripts/Makefile.lib
scripts/Makefile.spl [moved from spl/Makefile with 100% similarity]
scripts/basic/fixdep.c
scripts/docproc.c
test/command_ut.c
test/dm/Makefile
test/dm/cmd_dm.c
test/dm/core.c
test/dm/gpio.c
test/dm/test-driver.c
test/dm/test-fdt.c
test/dm/test-main.c
test/dm/test-uclass.c
test/vboot/vboot_test.sh
tools/.gitignore
tools/Makefile
tools/crc32.c [deleted file]
tools/dumpimage.h
tools/env_embedded.c [deleted file]
tools/fdt.c [deleted file]
tools/fdt_ro.c [deleted file]
tools/fdt_rw.c [deleted file]
tools/fdt_strerror.c [deleted file]
tools/fdt_wip.c [deleted file]
tools/fdtdec.c [deleted file]
tools/fit_check_sign.c
tools/fit_common.c
tools/fit_common.h
tools/fit_image.c
tools/fit_info.c
tools/image-fit.c [deleted file]
tools/image-host.c
tools/image-sig.c [deleted file]
tools/image.c [deleted file]
tools/imagetool.h
tools/md5.c [deleted file]
tools/mkimage.h
tools/mxsimage.c
tools/pbl_crc32.c [new file with mode: 0644]
tools/pbl_crc32.h [new file with mode: 0644]
tools/pblimage.c
tools/rsa-checksum.c [deleted file]
tools/rsa-sign.c [deleted file]
tools/rsa-verify.c [deleted file]
tools/sha1.c [deleted file]
tools/sha256.c [deleted file]
tools/ubsha1.c

index a6b2d1c..2ddf57f 100644 (file)
@@ -20,7 +20,9 @@
 *.bin
 *.patch
 *.cfgtmp
-*.dts.tmp
+
+# host programs on Cygwin
+*.exe
 
 # Build tree
 /build-*
@@ -47,8 +49,7 @@
 /errlog
 /reloc_off
 
-/spl/*
-!/spl/Makefile
+/spl/
 /tpl/
 
 #
index 966fd14..e429212 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -8,7 +8,7 @@
 VERSION = 2014
 PATCHLEVEL = 07
 SUBLEVEL =
-EXTRAVERSION = -rc1
+EXTRAVERSION = -rc3
 NAME =
 
 # *DOCUMENTATION*
@@ -209,11 +209,6 @@ HOSTCXX      = g++
 HOSTCFLAGS   = -Wall -Wstrict-prototypes -O2 -fomit-frame-pointer
 HOSTCXXFLAGS = -O2
 
-ifeq ($(shell $(HOSTCC) -v 2>&1 | grep -c "clang version"), 1)
-HOSTCFLAGS  += -Wno-unused-value -Wno-unused-parameter \
-               -Wno-missing-field-initializers -fno-delete-null-pointer-checks
-endif
-
 ifeq ($(HOSTOS),cygwin)
 HOSTCFLAGS     += -ansi
 endif
@@ -249,18 +244,18 @@ endif
 KBUILD_MODULES :=
 KBUILD_BUILTIN := 1
 
-#      If we have only "make modules", don't compile built-in objects.
-#      When we're building modules with modversions, we need to consider
-#      the built-in objects during the descend as well, in order to
-#      make sure the checksums are up to date before we record them.
+# If we have only "make modules", don't compile built-in objects.
+# When we're building modules with modversions, we need to consider
+# the built-in objects during the descend as well, in order to
+# make sure the checksums are up to date before we record them.
 
 ifeq ($(MAKECMDGOALS),modules)
   KBUILD_BUILTIN := $(if $(CONFIG_MODVERSIONS),1)
 endif
 
-#      If we have "make <whatever> modules", compile modules
-#      in addition to whatever we do anyway.
-#      Just "make" or "make all" shall build modules as well
+# If we have "make <whatever> modules", compile modules
+# in addition to whatever we do anyway.
+# Just "make" or "make all" shall build modules as well
 
 # U-Boot does not need modules
 #ifneq ($(filter all _all modules,$(MAKECMDGOALS)),)
@@ -320,15 +315,6 @@ endif
 
 export quiet Q KBUILD_VERBOSE
 
-ifneq ($(CC),)
-ifeq ($(shell $(CC) -v 2>&1 | grep -c "clang version"), 1)
-COMPILER := clang
-else
-COMPILER := gcc
-endif
-export COMPILER
-endif
-
 # Look for make include files relative to root of kernel src
 MAKEFLAGS += --include-dir=$(srctree)
 
@@ -354,7 +340,7 @@ STRIP               = $(CROSS_COMPILE)strip
 OBJCOPY                = $(CROSS_COMPILE)objcopy
 OBJDUMP                = $(CROSS_COMPILE)objdump
 AWK            = awk
-RANLIB         = $(CROSS_COMPILE)RANLIB
+PERL           = perl
 DTC            = dtc
 CHECK          = sparse
 
@@ -376,8 +362,8 @@ export VERSION PATCHLEVEL SUBLEVEL UBOOTRELEASE UBOOTVERSION
 export ARCH CPU BOARD VENDOR SOC CPUDIR BOARDDIR
 export CONFIG_SHELL HOSTCC HOSTCFLAGS HOSTLDFLAGS CROSS_COMPILE AS LD CC
 export CPP AR NM LDR STRIP OBJCOPY OBJDUMP
-export MAKE AWK
-export DTC CHECK CHECKFLAGS
+export MAKE AWK PERL
+export HOSTCXX HOSTCXXFLAGS DTC CHECK CHECKFLAGS
 
 export KBUILD_CPPFLAGS NOSTDINC_FLAGS UBOOTINCLUDE OBJCOPYFLAGS LDFLAGS
 export KBUILD_CFLAGS KBUILD_AFLAGS
@@ -515,12 +501,6 @@ endif
 
 # If there is no specified link script, we look in a number of places for it
 ifndef LDSCRIPT
-       ifeq ($(CONFIG_NAND_U_BOOT),y)
-               LDSCRIPT := $(srctree)/board/$(BOARDDIR)/u-boot-nand.lds
-               ifeq ($(wildcard $(LDSCRIPT)),)
-                       LDSCRIPT := $(srctree)/$(CPUDIR)/u-boot-nand.lds
-               endif
-       endif
        ifeq ($(wildcard $(LDSCRIPT)),)
                LDSCRIPT := $(srctree)/board/$(BOARDDIR)/u-boot.lds
        endif
@@ -545,20 +525,6 @@ endif
 
 KBUILD_CFLAGS += $(call cc-option,-fno-stack-protector)
 
-ifeq ($(COMPILER),clang)
-KBUILD_CPPFLAGS += $(call cc-option,-Qunused-arguments,)
-KBUILD_CPPFLAGS += $(call cc-option,-Wno-unknown-warning-option,)
-KBUILD_CFLAGS += $(call cc-disable-warning, unused-variable)
-KBUILD_CFLAGS += $(call cc-disable-warning, format-invalid-specifier)
-KBUILD_CFLAGS += $(call cc-disable-warning, gnu)
-# Quiet clang warning: comparison of unsigned expression < 0 is always false
-KBUILD_CFLAGS += $(call cc-disable-warning, tautological-compare)
-# CLANG uses a _MergedGlobals as optimization, but this breaks modpost, as the
-# source of a reference will be _MergedGlobals and not on of the whitelisted names.
-# See modpost pattern 2
-KBUILD_CFLAGS += $(call cc-option, -mno-global-merge,)
-endif
-
 KBUILD_CFLAGS  += -g
 # $(KBUILD_AFLAGS) sets -g, which causes gcc to pass a suitable -g<format>
 # option to the assembler.
@@ -740,9 +706,8 @@ DO_STATIC_RELA =
 endif
 
 # Always append ALL so that arch config.mk's can add custom ones
-ALL-y += u-boot.srec u-boot.bin System.map
+ALL-y += u-boot.srec u-boot.bin System.map binary_size_check
 
-ALL-$(CONFIG_NAND_U_BOOT) += u-boot-nand.bin
 ALL-$(CONFIG_ONENAND_U_BOOT) += u-boot-onenand.bin
 ifeq ($(CONFIG_SPL_FSL_PBL),y)
 ALL-$(CONFIG_RAMBOOT_PBL) += u-boot-with-spl-pbl.bin
@@ -820,6 +785,18 @@ u-boot.hex u-boot.srec: u-boot FORCE
 
 OBJCOPYFLAGS_u-boot.bin := -O binary
 
+binary_size_check: u-boot.bin System.map FORCE
+       @file_size=`stat -c %s u-boot.bin` ; \
+       map_size=$(shell cat System.map | \
+               awk '/_image_copy_start/ {start = $$1} /_image_binary_end/ {end = $$1} END {if (start != "" && end != "") print strtonum("0x" end) - strtonum("0x" start)}'); \
+       if [ "" != "$$map_size" ]; then \
+               if test $$map_size -ne $$file_size; then \
+                       echo "System.map shows a binary size of $$map_size" >&2 ; \
+                       echo "  but u-boot.bin shows $$file_size" >&2 ; \
+                       exit 1; \
+               fi \
+       fi
+
 u-boot.bin: u-boot FORCE
        $(call if_changed,objcopy)
        $(call DO_STATIC_RELA,$<,$@,$(CONFIG_SYS_TEXT_BASE))
@@ -1148,33 +1125,16 @@ cmd_cpp_lds = $(CPP) -Wp,-MD,$(depfile) $(cpp_flags) $(LDPPFLAGS) -ansi \
 u-boot.lds: $(LDSCRIPT) prepare FORCE
        $(call if_changed_dep,cpp_lds)
 
-PHONY += nand_spl
-nand_spl: prepare
-       $(Q)$(MAKE) $(build)=nand_spl/board/$(BOARDDIR) all
-       @echo >&2
-       @echo >&2 "==================== WARNING ====================="
-       @echo >&2 "nand_spl will not be included in v2014.07 release."
-       @echo >&2 "Please switch over to SPL."
-       @echo >&2 "Otherwise, this board will be removed."
-       @echo >&2 "=================================================="
-       @echo >&2
-
-nand_spl/u-boot-spl-16k.bin: nand_spl
-       @:
-
-u-boot-nand.bin: nand_spl/u-boot-spl-16k.bin u-boot.bin FORCE
-       $(call if_changed,cat)
-
 spl/u-boot-spl.bin: spl/u-boot-spl
        @:
 spl/u-boot-spl: tools prepare
-       $(Q)$(MAKE) obj=spl -f $(srctree)/spl/Makefile all
+       $(Q)$(MAKE) obj=spl -f $(srctree)/scripts/Makefile.spl all
 
 spl/sunxi-spl.bin: spl/u-boot-spl
        @:
 
 tpl/u-boot-tpl.bin: tools prepare
-       $(Q)$(MAKE) obj=tpl -f $(srctree)/spl/Makefile all CONFIG_TPL_BUILD=y
+       $(Q)$(MAKE) obj=tpl -f $(srctree)/scripts/Makefile.spl all CONFIG_TPL_BUILD=y
 
 TAG_SUBDIRS := $(u-boot-dirs) include
 
@@ -1254,14 +1214,12 @@ CLEAN_FILES += u-boot.lds include/bmp_logo.h include/bmp_logo_data.h \
               include/tpl-autoconf.mk
 
 # Directories & files removed with 'make clobber'
-CLOBBER_DIRS  += $(patsubst %,spl/%, $(filter-out Makefile, \
-                $(shell ls -1 spl 2>/dev/null))) \
-                tpl
-CLOBBER_FILES += u-boot* MLO* SPL System.map nand_spl/u-boot*
+CLOBBER_DIRS  += spl tpl
+CLOBBER_FILES += u-boot* MLO* SPL System.map
 
 # Directories & files removed with 'make mrproper'
 MRPROPER_DIRS  += include/config include/generated          \
-                  .tmp_objdiff
+                 .tmp_objdiff
 MRPROPER_FILES += .config .config.old \
                  tags TAGS cscope* GPATH GTAGS GRTAGS GSYMS \
                  include/config.h include/config.mk
@@ -1290,8 +1248,6 @@ clean: $(clean-dirs)
                -o -name '*.symtypes' -o -name 'modules.order' \
                -o -name modules.builtin -o -name '.tmp_*.o.*' \
                -o -name '*.gcno' \) -type f -print | xargs rm -f
-       @find $(if $(KBUILD_EXTMOD), $(KBUILD_EXTMOD), .) $(RCS_FIND_IGNORE) \
-               -path './nand_spl/*' -type l -print | xargs rm -f
 
 # clobber
 #
diff --git a/README b/README
index a280435..fe5cacb 100644 (file)
--- a/README
+++ b/README
@@ -321,14 +321,6 @@ The following options need to be configured:
                                          the LCD display every second with
                                          a "rotator" |\-/|\-/
 
-- Board flavour: (if CONFIG_MPC8260ADS is defined)
-               CONFIG_ADSTYPE
-               Possible values are:
-                       CONFIG_SYS_8260ADS      - original MPC8260ADS
-                       CONFIG_SYS_8266ADS      - MPC8266ADS
-                       CONFIG_SYS_PQ2FADS      - PQ2FADS-ZU or PQ2FADS-VR
-                       CONFIG_SYS_8272ADS      - MPC8272ADS
-
 - Marvell Family Member
                CONFIG_SYS_MVFS         - define it if you want to enable
                                          multiple fs option at one time
@@ -1008,6 +1000,7 @@ The following options need to be configured:
                CONFIG_CMD_IMLS           List all images found in NOR flash
                CONFIG_CMD_IMLS_NAND    * List all images found in NAND flash
                CONFIG_CMD_IMMAP        * IMMR dump support
+               CONFIG_CMD_IOTRACE      * I/O tracing for debugging
                CONFIG_CMD_IMPORTENV    * import an environment
                CONFIG_CMD_INI          * import data from an ini file into the env
                CONFIG_CMD_IRQ          * irqinfo
@@ -1179,6 +1172,28 @@ The following options need to be configured:
                Note that if the GPIO device uses I2C, then the I2C interface
                must also be configured. See I2C Support, below.
 
+- I/O tracing:
+               When CONFIG_IO_TRACE is selected, U-Boot intercepts all I/O
+               accesses and can checksum them or write a list of them out
+               to memory. See the 'iotrace' command for details. This is
+               useful for testing device drivers since it can confirm that
+               the driver behaves the same way before and after a code
+               change. Currently this is supported on sandbox and arm. To
+               add support for your architecture, add '#include <iotrace.h>'
+               to the bottom of arch/<arch>/include/asm/io.h and test.
+
+               Example output from the 'iotrace stats' command is below.
+               Note that if the trace buffer is exhausted, the checksum will
+               still continue to operate.
+
+                       iotrace is enabled
+                       Start:  10000000        (buffer start address)
+                       Size:   00010000        (buffer size)
+                       Offset: 00000120        (current buffer offset)
+                       Output: 10000120        (start + offset)
+                       Count:  00000018        (number of trace records)
+                       CRC32:  9526fb66        (CRC32 of all trace records)
+
 - Timestamp Support:
 
                When CONFIG_TIMESTAMP is selected, the timestamp
@@ -1432,9 +1447,6 @@ The following options need to be configured:
                CONFIG_USB_EHCI_TXFIFO_THRESH enables setting of the
                txfilltuning field in the EHCI controller on reset.
 
-               CONFIG_USB_HUB_MIN_POWER_ON_DELAY defines the minimum
-               interval for usb hub power-on delay.(minimum 100msec)
-
 - USB Device:
                Define the below if you wish to use the USB console.
                Once firmware is rebuilt from a serial console issue the
@@ -1645,6 +1657,12 @@ CBFS (Coreboot Filesystem) support
                filesystem. Available commands are cbfsinit, cbfsinfo, cbfsls
                and cbfsload.
 
+- FAT(File Allocation Table) filesystem cluster size:
+               CONFIG_FS_FAT_MAX_CLUSTSIZE
+
+               Define the max cluster size for fat operations else
+               a default value of 65536 will be defined.
+
 - Keyboard Support:
                CONFIG_ISA_KEYBOARD
 
@@ -3202,6 +3220,19 @@ FIT uImage format:
  -150  common/cmd_nand.c       Incorrect FIT image format
   151  common/cmd_nand.c       FIT image format OK
 
+- legacy image format:
+               CONFIG_IMAGE_FORMAT_LEGACY
+               enables the legacy image format support in U-Boot.
+
+               Default:
+               enabled if CONFIG_FIT_SIGNATURE is not defined.
+
+               CONFIG_DISABLE_IMAGE_LEGACY
+               disable the legacy image format
+
+               This define is introduced, as the legacy image format is
+               enabled per default for backward compatibility.
+
 - FIT image support:
                CONFIG_FIT
                Enable support for the FIT uImage format.
@@ -3218,6 +3249,11 @@ FIT uImage format:
                using a hash signed and verified using RSA. See
                doc/uImage.FIT/signature.txt for more details.
 
+               WARNING: When relying on signed FIT images with required
+               signature check the legacy image format is default
+               disabled. If a board need legacy image format support
+               enable this through CONFIG_IMAGE_FORMAT_LEGACY
+
 - Standalone program support:
                CONFIG_STANDALONE_LOAD_ADDR
 
@@ -5295,6 +5331,11 @@ Information structure as we define in include/asm-<arch>/u-boot.h,
 and make sure that your definition of IMAP_ADDR uses the same value
 as your U-Boot configuration in CONFIG_SYS_IMMR.
 
+Note that U-Boot now has a driver model, a unified model for drivers.
+If you are adding a new driver, plumb it into driver model. If there
+is no uclass available, you are encouraged to create one. See
+doc/driver-model.
+
 
 Configuring the Linux kernel:
 -----------------------------
index a1fbe01..2714b86 100644 (file)
@@ -1,2 +1 @@
 /*/include/asm/arch
-/*/include/asm/proc
index 3d331cc..e5be078 100644 (file)
@@ -8,6 +8,7 @@
 #define __ASM_ARC_CONFIG_H_
 
 #define CONFIG_SYS_GENERIC_GLOBAL_DATA
+#define CONFIG_SYS_BOOT_RAMDISK_HIGH
 
 #define CONFIG_LMB
 
index 3479541..e0f9d5b 100644 (file)
@@ -15,7 +15,7 @@
 #include <asm/arch/tegra.h>
 #include <asm/arch-tegra/apb_misc.h>
 #include <asm/arch-tegra/board.h>
-#include <asm/arch/spl.h>
+#include <asm/spl.h>
 #include "cpu.h"
 
 void spl_board_init(void)
index d4711c0..da80240 100644 (file)
@@ -13,7 +13,6 @@
 #include <asm/io.h>
 #include <asm/arch/cpu.h>
 #include <asm/arch/kirkwood.h>
-#include <hush.h>
 
 #define BUFLEN 16
 
@@ -211,7 +210,7 @@ static void kw_sysrst_action(void)
 
        debug("Starting %s process...\n", __FUNCTION__);
        ret = run_command(s, 0);
-       if (ret < 0)
+       if (ret != 0)
                debug("Error.. %s failed\n", __FUNCTION__);
        else
                debug("%s process finished\n", __FUNCTION__);
index b55c5f0..f88db3b 100644 (file)
@@ -15,7 +15,6 @@
 #include <asm/io.h>
 #include <u-boot/md5.h>
 #include <asm/arch/cpu.h>
-#include <hush.h>
 
 #define BUFLEN 16
 
index 7fe049e..828d10b 100644 (file)
@@ -255,11 +255,3 @@ void s_init(void)
 #endif
 }
 #endif
-
-#ifndef CONFIG_SYS_DCACHE_OFF
-void enable_caches(void)
-{
-       /* Enable D-cache. I-cache is already enabled in start.S */
-       dcache_enable();
-}
-#endif /* !CONFIG_SYS_DCACHE_OFF */
index 2fbf60d..8d86f97 100644 (file)
@@ -61,6 +61,8 @@ int print_cpuinfo(void)
 
 void enable_caches(void)
 {
+       icache_enable();
+       dcache_enable();
 }
 
 unsigned int get_chip_id(void)
index ade45fd..7916630 100644 (file)
@@ -4,8 +4,8 @@
  * SPDX-License-Identifier:    GPL-2.0+
  */
 
-#include<common.h>
-#include<config.h>
+#include <common.h>
+#include <config.h>
 
 #include <asm/arch/clock.h>
 #include <asm/arch/clk.h>
index d7285fc..6dc9f8e 100644 (file)
@@ -8,4 +8,5 @@
 #
 
 obj-y  := soc.o clock.o
+obj-$(CONFIG_SPL_BUILD)             += ddr.o
 obj-$(CONFIG_SECURE_BOOT)    += hab.o
diff --git a/arch/arm/cpu/armv7/mx6/ddr.c b/arch/arm/cpu/armv7/mx6/ddr.c
new file mode 100644 (file)
index 0000000..0434211
--- /dev/null
@@ -0,0 +1,490 @@
+/*
+ * Copyright (C) 2014 Gateworks Corporation
+ * Author: Tim Harvey <tharvey@gateworks.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+#include <linux/types.h>
+#include <asm/arch/mx6-ddr.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/io.h>
+#include <asm/types.h>
+
+#if defined(CONFIG_MX6QDL) || defined(CONFIG_MX6Q) || defined(CONFIG_MX6D)
+/* Configure MX6DQ mmdc iomux */
+void mx6dq_dram_iocfg(unsigned width,
+                     const struct mx6dq_iomux_ddr_regs *ddr,
+                     const struct mx6dq_iomux_grp_regs *grp)
+{
+       volatile struct mx6dq_iomux_ddr_regs *mx6_ddr_iomux;
+       volatile struct mx6dq_iomux_grp_regs *mx6_grp_iomux;
+
+       mx6_ddr_iomux = (struct mx6dq_iomux_ddr_regs *)MX6DQ_IOM_DDR_BASE;
+       mx6_grp_iomux = (struct mx6dq_iomux_grp_regs *)MX6DQ_IOM_GRP_BASE;
+
+       /* DDR IO Type */
+       mx6_grp_iomux->grp_ddr_type = grp->grp_ddr_type;
+       mx6_grp_iomux->grp_ddrpke = grp->grp_ddrpke;
+
+       /* Clock */
+       mx6_ddr_iomux->dram_sdclk_0 = ddr->dram_sdclk_0;
+       mx6_ddr_iomux->dram_sdclk_1 = ddr->dram_sdclk_1;
+
+       /* Address */
+       mx6_ddr_iomux->dram_cas = ddr->dram_cas;
+       mx6_ddr_iomux->dram_ras = ddr->dram_ras;
+       mx6_grp_iomux->grp_addds = grp->grp_addds;
+
+       /* Control */
+       mx6_ddr_iomux->dram_reset = ddr->dram_reset;
+       mx6_ddr_iomux->dram_sdcke0 = ddr->dram_sdcke0;
+       mx6_ddr_iomux->dram_sdcke1 = ddr->dram_sdcke1;
+       mx6_ddr_iomux->dram_sdba2 = ddr->dram_sdba2;
+       mx6_ddr_iomux->dram_sdodt0 = ddr->dram_sdodt0;
+       mx6_ddr_iomux->dram_sdodt1 = ddr->dram_sdodt1;
+       mx6_grp_iomux->grp_ctlds = grp->grp_ctlds;
+
+       /* Data Strobes */
+       mx6_grp_iomux->grp_ddrmode_ctl = grp->grp_ddrmode_ctl;
+       mx6_ddr_iomux->dram_sdqs0 = ddr->dram_sdqs0;
+       mx6_ddr_iomux->dram_sdqs1 = ddr->dram_sdqs1;
+       if (width >= 32) {
+               mx6_ddr_iomux->dram_sdqs2 = ddr->dram_sdqs2;
+               mx6_ddr_iomux->dram_sdqs3 = ddr->dram_sdqs3;
+       }
+       if (width >= 64) {
+               mx6_ddr_iomux->dram_sdqs4 = ddr->dram_sdqs4;
+               mx6_ddr_iomux->dram_sdqs5 = ddr->dram_sdqs5;
+               mx6_ddr_iomux->dram_sdqs6 = ddr->dram_sdqs6;
+               mx6_ddr_iomux->dram_sdqs7 = ddr->dram_sdqs7;
+       }
+
+       /* Data */
+       mx6_grp_iomux->grp_ddrmode = grp->grp_ddrmode;
+       mx6_grp_iomux->grp_b0ds = grp->grp_b0ds;
+       mx6_grp_iomux->grp_b1ds = grp->grp_b1ds;
+       if (width >= 32) {
+               mx6_grp_iomux->grp_b2ds = grp->grp_b2ds;
+               mx6_grp_iomux->grp_b3ds = grp->grp_b3ds;
+       }
+       if (width >= 64) {
+               mx6_grp_iomux->grp_b4ds = grp->grp_b4ds;
+               mx6_grp_iomux->grp_b5ds = grp->grp_b5ds;
+               mx6_grp_iomux->grp_b6ds = grp->grp_b6ds;
+               mx6_grp_iomux->grp_b7ds = grp->grp_b7ds;
+       }
+       mx6_ddr_iomux->dram_dqm0 = ddr->dram_dqm0;
+       mx6_ddr_iomux->dram_dqm1 = ddr->dram_dqm1;
+       if (width >= 32) {
+               mx6_ddr_iomux->dram_dqm2 = ddr->dram_dqm2;
+               mx6_ddr_iomux->dram_dqm3 = ddr->dram_dqm3;
+       }
+       if (width >= 64) {
+               mx6_ddr_iomux->dram_dqm4 = ddr->dram_dqm4;
+               mx6_ddr_iomux->dram_dqm5 = ddr->dram_dqm5;
+               mx6_ddr_iomux->dram_dqm6 = ddr->dram_dqm6;
+               mx6_ddr_iomux->dram_dqm7 = ddr->dram_dqm7;
+       }
+}
+#endif
+
+#if defined(CONFIG_MX6QDL) || defined(CONFIG_MX6DL) || defined(CONFIG_MX6S)
+/* Configure MX6SDL mmdc iomux */
+void mx6sdl_dram_iocfg(unsigned width,
+                      const struct mx6sdl_iomux_ddr_regs *ddr,
+                      const struct mx6sdl_iomux_grp_regs *grp)
+{
+       volatile struct mx6sdl_iomux_ddr_regs *mx6_ddr_iomux;
+       volatile struct mx6sdl_iomux_grp_regs *mx6_grp_iomux;
+
+       mx6_ddr_iomux = (struct mx6sdl_iomux_ddr_regs *)MX6SDL_IOM_DDR_BASE;
+       mx6_grp_iomux = (struct mx6sdl_iomux_grp_regs *)MX6SDL_IOM_GRP_BASE;
+
+       /* DDR IO Type */
+       mx6_grp_iomux->grp_ddr_type = grp->grp_ddr_type;
+       mx6_grp_iomux->grp_ddrpke = grp->grp_ddrpke;
+
+       /* Clock */
+       mx6_ddr_iomux->dram_sdclk_0 = ddr->dram_sdclk_0;
+       mx6_ddr_iomux->dram_sdclk_1 = ddr->dram_sdclk_1;
+
+       /* Address */
+       mx6_ddr_iomux->dram_cas = ddr->dram_cas;
+       mx6_ddr_iomux->dram_ras = ddr->dram_ras;
+       mx6_grp_iomux->grp_addds = grp->grp_addds;
+
+       /* Control */
+       mx6_ddr_iomux->dram_reset = ddr->dram_reset;
+       mx6_ddr_iomux->dram_sdcke0 = ddr->dram_sdcke0;
+       mx6_ddr_iomux->dram_sdcke1 = ddr->dram_sdcke1;
+       mx6_ddr_iomux->dram_sdba2 = ddr->dram_sdba2;
+       mx6_ddr_iomux->dram_sdodt0 = ddr->dram_sdodt0;
+       mx6_ddr_iomux->dram_sdodt1 = ddr->dram_sdodt1;
+       mx6_grp_iomux->grp_ctlds = grp->grp_ctlds;
+
+       /* Data Strobes */
+       mx6_grp_iomux->grp_ddrmode_ctl = grp->grp_ddrmode_ctl;
+       mx6_ddr_iomux->dram_sdqs0 = ddr->dram_sdqs0;
+       mx6_ddr_iomux->dram_sdqs1 = ddr->dram_sdqs1;
+       if (width >= 32) {
+               mx6_ddr_iomux->dram_sdqs2 = ddr->dram_sdqs2;
+               mx6_ddr_iomux->dram_sdqs3 = ddr->dram_sdqs3;
+       }
+       if (width >= 64) {
+               mx6_ddr_iomux->dram_sdqs4 = ddr->dram_sdqs4;
+               mx6_ddr_iomux->dram_sdqs5 = ddr->dram_sdqs5;
+               mx6_ddr_iomux->dram_sdqs6 = ddr->dram_sdqs6;
+               mx6_ddr_iomux->dram_sdqs7 = ddr->dram_sdqs7;
+       }
+
+       /* Data */
+       mx6_grp_iomux->grp_ddrmode = grp->grp_ddrmode;
+       mx6_grp_iomux->grp_b0ds = grp->grp_b0ds;
+       mx6_grp_iomux->grp_b1ds = grp->grp_b1ds;
+       if (width >= 32) {
+               mx6_grp_iomux->grp_b2ds = grp->grp_b2ds;
+               mx6_grp_iomux->grp_b3ds = grp->grp_b3ds;
+       }
+       if (width >= 64) {
+               mx6_grp_iomux->grp_b4ds = grp->grp_b4ds;
+               mx6_grp_iomux->grp_b5ds = grp->grp_b5ds;
+               mx6_grp_iomux->grp_b6ds = grp->grp_b6ds;
+               mx6_grp_iomux->grp_b7ds = grp->grp_b7ds;
+       }
+       mx6_ddr_iomux->dram_dqm0 = ddr->dram_dqm0;
+       mx6_ddr_iomux->dram_dqm1 = ddr->dram_dqm1;
+       if (width >= 32) {
+               mx6_ddr_iomux->dram_dqm2 = ddr->dram_dqm2;
+               mx6_ddr_iomux->dram_dqm3 = ddr->dram_dqm3;
+       }
+       if (width >= 64) {
+               mx6_ddr_iomux->dram_dqm4 = ddr->dram_dqm4;
+               mx6_ddr_iomux->dram_dqm5 = ddr->dram_dqm5;
+               mx6_ddr_iomux->dram_dqm6 = ddr->dram_dqm6;
+               mx6_ddr_iomux->dram_dqm7 = ddr->dram_dqm7;
+       }
+}
+#endif
+
+/*
+ * Configure mx6 mmdc registers based on:
+ *  - board-specific memory configuration
+ *  - board-specific calibration data
+ *  - ddr3 chip details
+ *
+ * The various calculations here are derived from the Freescale
+ * i.Mx6DQSDL DDR3 Script Aid spreadsheet (DOC-94917) designed to generate MMDC
+ * configuration registers based on memory system and memory chip parameters.
+ *
+ * The defaults here are those which were specified in the spreadsheet.
+ * For details on each register, refer to the IMX6DQRM and/or IMX6SDLRM
+ * section titled MMDC initialization
+ */
+#define MR(val, ba, cmd, cs1) \
+       ((val << 16) | (1 << 15) | (cmd << 4) | (cs1 << 3) | ba)
+void mx6_dram_cfg(const struct mx6_ddr_sysinfo *i,
+                 const struct mx6_mmdc_calibration *c,
+                 const struct mx6_ddr3_cfg *m)
+{
+       volatile struct mmdc_p_regs *mmdc0;
+       volatile struct mmdc_p_regs *mmdc1;
+       u32 reg;
+       u8 tcke, tcksrx, tcksre, txpdll, taofpd, taonpd, trrd;
+       u8 todtlon, taxpd, tanpd, tcwl, txp, tfaw, tcl;
+       u8 todt_idle_off = 0x4; /* from DDR3 Script Aid spreadsheet */
+       u16 trcd, trc, tras, twr, tmrd, trtp, trp, twtr, trfc, txs, txpr;
+       u16 CS0_END;
+       u16 tdllk = 0x1ff; /* DLL locking time: 512 cycles (JEDEC DDR3) */
+       int clkper; /* clock period in picoseconds */
+       int clock; /* clock freq in mHz */
+       int cs;
+
+       mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
+       mmdc1 = (struct mmdc_p_regs *)MMDC_P1_BASE_ADDR;
+
+       /* MX6D/MX6Q: 1066 MHz memory clock, clkper = 1.894ns = 1894ps */
+       if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) {
+               clock = 528;
+               tcwl = 4;
+       }
+       /* MX6S/MX6DL: 800 MHz memory clock, clkper = 2.5ns = 2500ps */
+       else {
+               clock = 400;
+               tcwl = 3;
+       }
+       clkper = (1000*1000)/clock; /* ps */
+       todtlon = tcwl;
+       taxpd = tcwl;
+       tanpd = tcwl;
+       tcwl = tcwl;
+
+       switch (m->density) {
+       case 1: /* 1Gb per chip */
+               trfc = DIV_ROUND_UP(110000, clkper) - 1;
+               txs = DIV_ROUND_UP(120000, clkper) - 1;
+               break;
+       case 2: /* 2Gb per chip */
+               trfc = DIV_ROUND_UP(160000, clkper) - 1;
+               txs = DIV_ROUND_UP(170000, clkper) - 1;
+               break;
+       case 4: /* 4Gb per chip */
+               trfc = DIV_ROUND_UP(260000, clkper) - 1;
+               txs = DIV_ROUND_UP(270000, clkper) - 1;
+               break;
+       case 8: /* 8Gb per chip */
+               trfc = DIV_ROUND_UP(350000, clkper) - 1;
+               txs = DIV_ROUND_UP(360000, clkper) - 1;
+               break;
+       default:
+               /* invalid density */
+               printf("invalid chip density\n");
+               hang();
+               break;
+       }
+       txpr = txs;
+
+       switch (m->mem_speed) {
+       case 800:
+               txp = DIV_ROUND_UP(MAX(3*clkper, 7500), clkper) - 1;
+               tcke = DIV_ROUND_UP(MAX(3*clkper, 7500), clkper) - 1;
+               if (m->pagesz == 1) {
+                       tfaw = DIV_ROUND_UP(40000, clkper) - 1;
+                       trrd = DIV_ROUND_UP(MAX(4*clkper, 10000), clkper) - 1;
+               } else {
+                       tfaw = DIV_ROUND_UP(50000, clkper) - 1;
+                       trrd = DIV_ROUND_UP(MAX(4*clkper, 10000), clkper) - 1;
+               }
+               break;
+       case 1066:
+               txp = DIV_ROUND_UP(MAX(3*clkper, 7500), clkper) - 1;
+               tcke = DIV_ROUND_UP(MAX(3*clkper, 5625), clkper) - 1;
+               if (m->pagesz == 1) {
+                       tfaw = DIV_ROUND_UP(37500, clkper) - 1;
+                       trrd = DIV_ROUND_UP(MAX(4*clkper, 7500), clkper) - 1;
+               } else {
+                       tfaw = DIV_ROUND_UP(50000, clkper) - 1;
+                       trrd = DIV_ROUND_UP(MAX(4*clkper, 10000), clkper) - 1;
+               }
+               break;
+       case 1333:
+               txp = DIV_ROUND_UP(MAX(3*clkper, 6000), clkper) - 1;
+               tcke = DIV_ROUND_UP(MAX(3*clkper, 5625), clkper) - 1;
+               if (m->pagesz == 1) {
+                       tfaw = DIV_ROUND_UP(30000, clkper) - 1;
+                       trrd = DIV_ROUND_UP(MAX(4*clkper, 6000), clkper) - 1;
+               } else {
+                       tfaw = DIV_ROUND_UP(45000, clkper) - 1;
+                       trrd = DIV_ROUND_UP(MAX(4*clkper, 7500), clkper) - 1;
+               }
+               break;
+       case 1600:
+               txp = DIV_ROUND_UP(MAX(3*clkper, 6000), clkper) - 1;
+               tcke = DIV_ROUND_UP(MAX(3*clkper, 5000), clkper) - 1;
+               if (m->pagesz == 1) {
+                       tfaw = DIV_ROUND_UP(30000, clkper) - 1;
+                       trrd = DIV_ROUND_UP(MAX(4*clkper, 6000), clkper) - 1;
+               } else {
+                       tfaw = DIV_ROUND_UP(40000, clkper) - 1;
+                       trrd = DIV_ROUND_UP(MAX(4*clkper, 7500), clkper) - 1;
+               }
+               break;
+       default:
+               printf("invalid memory speed\n");
+               hang();
+               break;
+       }
+       txpdll = DIV_ROUND_UP(MAX(10*clkper, 24000), clkper) - 1;
+       tcl = DIV_ROUND_UP(m->trcd, clkper/10) - 3;
+       tcksre = DIV_ROUND_UP(MAX(5*clkper, 10000), clkper);
+       tcksrx = tcksre;
+       taonpd = DIV_ROUND_UP(2000, clkper) - 1;
+       taofpd = taonpd;
+       trp = DIV_ROUND_UP(m->trcd, clkper/10) - 1;
+       trcd = trp;
+       trc = DIV_ROUND_UP(m->trcmin, clkper/10) - 1;
+       tras = DIV_ROUND_UP(m->trasmin, clkper/10) - 1;
+       twr = DIV_ROUND_UP(15000, clkper) - 1;
+       tmrd = DIV_ROUND_UP(MAX(12*clkper, 15000), clkper) - 1;
+       twtr = ROUND(MAX(4*clkper, 7500)/clkper, 1) - 1;
+       trtp = twtr;
+       CS0_END = ((4*i->cs_density) <= 120) ? (4*i->cs_density)+7 : 127;
+       debug("density:%d Gb (%d Gb per chip)\n", i->cs_density, m->density);
+       debug("clock: %dMHz (%d ps)\n", clock, clkper);
+       debug("memspd:%d\n", m->mem_speed);
+       debug("tcke=%d\n", tcke);
+       debug("tcksrx=%d\n", tcksrx);
+       debug("tcksre=%d\n", tcksre);
+       debug("taofpd=%d\n", taofpd);
+       debug("taonpd=%d\n", taonpd);
+       debug("todtlon=%d\n", todtlon);
+       debug("tanpd=%d\n", tanpd);
+       debug("taxpd=%d\n", taxpd);
+       debug("trfc=%d\n", trfc);
+       debug("txs=%d\n", txs);
+       debug("txp=%d\n", txp);
+       debug("txpdll=%d\n", txpdll);
+       debug("tfaw=%d\n", tfaw);
+       debug("tcl=%d\n", tcl);
+       debug("trcd=%d\n", trcd);
+       debug("trp=%d\n", trp);
+       debug("trc=%d\n", trc);
+       debug("tras=%d\n", tras);
+       debug("twr=%d\n", twr);
+       debug("tmrd=%d\n", tmrd);
+       debug("tcwl=%d\n", tcwl);
+       debug("tdllk=%d\n", tdllk);
+       debug("trtp=%d\n", trtp);
+       debug("twtr=%d\n", twtr);
+       debug("trrd=%d\n", trrd);
+       debug("txpr=%d\n", txpr);
+       debug("CS0_END=%d\n", CS0_END);
+       debug("ncs=%d\n", i->ncs);
+       debug("Rtt_wr=%d\n", i->rtt_wr);
+       debug("Rtt_nom=%d\n", i->rtt_nom);
+       debug("SRT=%d\n", m->SRT);
+       debug("tcl=%d\n", tcl);
+       debug("twr=%d\n", twr);
+
+       /*
+        * board-specific configuration:
+        *  These values are determined empirically and vary per board layout
+        *  see:
+        *   appnote, ddr3 spreadsheet
+        */
+       mmdc0->mpwldectrl0 = c->p0_mpwldectrl0;
+       mmdc0->mpwldectrl1 = c->p0_mpwldectrl1;
+       mmdc0->mpdgctrl0 = c->p0_mpdgctrl0;
+       mmdc0->mpdgctrl1 = c->p0_mpdgctrl1;
+       mmdc0->mprddlctl = c->p0_mprddlctl;
+       mmdc0->mpwrdlctl = c->p0_mpwrdlctl;
+       if (i->dsize > 1) {
+               mmdc1->mpwldectrl0 = c->p1_mpwldectrl0;
+               mmdc1->mpwldectrl1 = c->p1_mpwldectrl1;
+               mmdc1->mpdgctrl0 = c->p1_mpdgctrl0;
+               mmdc1->mpdgctrl1 = c->p1_mpdgctrl1;
+               mmdc1->mprddlctl = c->p1_mprddlctl;
+               mmdc1->mpwrdlctl = c->p1_mpwrdlctl;
+       }
+
+       /* Read data DQ Byte0-3 delay */
+       mmdc0->mprddqby0dl = (u32)0x33333333;
+       mmdc0->mprddqby1dl = (u32)0x33333333;
+       if (i->dsize > 0) {
+               mmdc0->mprddqby2dl = (u32)0x33333333;
+               mmdc0->mprddqby3dl = (u32)0x33333333;
+       }
+       if (i->dsize > 1) {
+               mmdc1->mprddqby0dl = (u32)0x33333333;
+               mmdc1->mprddqby1dl = (u32)0x33333333;
+               mmdc1->mprddqby2dl = (u32)0x33333333;
+               mmdc1->mprddqby3dl = (u32)0x33333333;
+       }
+
+       /* MMDC Termination: rtt_nom:2 RZQ/2(120ohm), rtt_nom:1 RZQ/4(60ohm) */
+       reg = (i->rtt_nom == 2) ? 0x00011117 : 0x00022227;
+       mmdc0->mpodtctrl = reg;
+       if (i->dsize > 1)
+               mmdc1->mpodtctrl = reg;
+
+       /* complete calibration */
+       reg = (1 << 11); /* Force measurement on delay-lines */
+       mmdc0->mpmur0 = reg;
+       if (i->dsize > 1)
+               mmdc1->mpmur0 = reg;
+
+       /* Step 1: configuration request */
+       mmdc0->mdscr = (u32)(1 << 15); /* config request */
+
+       /* Step 2: Timing configuration */
+       reg = (trfc << 24) | (txs << 16) | (txp << 13) | (txpdll << 9) |
+             (tfaw << 4) | tcl;
+       mmdc0->mdcfg0 = reg;
+       reg = (trcd << 29) | (trp << 26) | (trc << 21) | (tras << 16) |
+             (1 << 15) |               /* trpa */
+             (twr << 9) | (tmrd << 5) | tcwl;
+       mmdc0->mdcfg1 = reg;
+       reg = (tdllk << 16) | (trtp << 6) | (twtr << 3) | trrd;
+       mmdc0->mdcfg2 = reg;
+       reg = (taofpd << 27) | (taonpd << 24) | (tanpd << 20) | (taxpd << 16) |
+             (todtlon << 12) | (todt_idle_off << 4);
+       mmdc0->mdotc = reg;
+       mmdc0->mdasp = CS0_END; /* CS addressing */
+
+       /* Step 3: Configure DDR type */
+       reg = (i->cs1_mirror << 19) | (i->walat << 16) | (i->bi_on << 12) |
+             (i->mif3_mode << 9) | (i->ralat << 6);
+       mmdc0->mdmisc = reg;
+
+       /* Step 4: Configure delay while leaving reset */
+       reg = (txpr << 16) | (i->sde_to_rst << 8) | (i->rst_to_cke << 0);
+       mmdc0->mdor = reg;
+
+       /* Step 5: Configure DDR physical parameters (density and burst len) */
+       reg = (m->rowaddr - 11) << 24 |         /* ROW */
+             (m->coladdr - 9) << 20 |          /* COL */
+             (1 << 19) |                       /* Burst Length = 8 for DDR3 */
+             (i->dsize << 16);                 /* DDR data bus size */
+       mmdc0->mdctl = reg;
+
+       /* Step 6: Perform ZQ calibration */
+       reg = (u32)0xa1390001; /* one-time HW ZQ calib */
+       mmdc0->mpzqhwctrl = reg;
+       if (i->dsize > 1)
+               mmdc1->mpzqhwctrl = reg;
+
+       /* Step 7: Enable MMDC with desired chip select */
+       reg = mmdc0->mdctl |
+             (1 << 31) |                       /* SDE_0 for CS0 */
+             ((i->ncs == 2) ? 1 : 0) << 30;    /* SDE_1 for CS1 */
+       mmdc0->mdctl = reg;
+
+       /* Step 8: Write Mode Registers to Init DDR3 devices */
+       for (cs = 0; cs < i->ncs; cs++) {
+               /* MR2 */
+               reg = (i->rtt_wr & 3) << 9 | (m->SRT & 1) << 7 |
+                     ((tcwl - 3) & 3) << 3;
+               mmdc0->mdscr = (u32)MR(reg, 2, 3, cs);
+               /* MR3 */
+               mmdc0->mdscr = (u32)MR(0, 3, 3, cs);
+               /* MR1 */
+               reg = ((i->rtt_nom & 1) ? 1 : 0) << 2 |
+                     ((i->rtt_nom & 2) ? 1 : 0) << 6;
+               mmdc0->mdscr = (u32)MR(reg, 1, 3, cs);
+               reg = ((tcl - 1) << 4) |        /* CAS */
+                     (1 << 8)   |              /* DLL Reset */
+                     ((twr - 3) << 9);         /* Write Recovery */
+               /* MR0 */
+               mmdc0->mdscr = (u32)MR(reg, 0, 3, cs);
+               /* ZQ calibration */
+               reg = (1 << 10);
+               mmdc0->mdscr = (u32)MR(reg, 0, 4, cs);
+       }
+
+       /* Step 10: Power down control and self-refresh */
+       reg = (tcke & 0x7) << 16 |
+             5            << 12 |  /* PWDT_1: 256 cycles */
+             5            <<  8 |  /* PWDT_0: 256 cycles */
+             1            <<  6 |  /* BOTH_CS_PD */
+             (tcksrx & 0x7) << 3 |
+             (tcksre & 0x7);
+       mmdc0->mdpdc = reg;
+       mmdc0->mapsr = (u32)0x00011006; /* ADOPT power down enabled */
+
+       /* Step 11: Configure ZQ calibration: one-time and periodic 1ms */
+       mmdc0->mpzqhwctrl = (u32)0xa1390003;
+       if (i->dsize > 1)
+               mmdc1->mpzqhwctrl = (u32)0xa1390003;
+
+       /* Step 12: Configure and activate periodic refresh */
+       reg = (1 << 14) |       /* REF_SEL: Periodic refresh cycles of 32kHz */
+             (7 << 11);        /* REFR: Refresh Rate - 8 refreshes */
+       mmdc0->mdref = reg;
+
+       /* Step 13: Deassert config request - init complete */
+       mmdc0->mdscr = (u32)0x00000000;
+
+       /* wait for auto-ZQ calibration to complete */
+       mdelay(1);
+}
index 5187775..f6810a6 100644 (file)
@@ -7,15 +7,69 @@
 #include <common.h>
 #include <asm/io.h>
 #include <asm/arch/hab.h>
+#include <asm/arch/sys_proto.h>
 
 /* -------- start of HAB API updates ------------*/
-#define hab_rvt_report_event ((hab_rvt_report_event_t *)HAB_RVT_REPORT_EVENT)
-#define hab_rvt_report_status ((hab_rvt_report_status_t *)HAB_RVT_REPORT_STATUS)
-#define hab_rvt_authenticate_image \
-       ((hab_rvt_authenticate_image_t *)HAB_RVT_AUTHENTICATE_IMAGE)
-#define hab_rvt_entry ((hab_rvt_entry_t *)HAB_RVT_ENTRY)
-#define hab_rvt_exit ((hab_rvt_exit_t *)HAB_RVT_EXIT)
-#define hab_rvt_clock_init HAB_RVT_CLOCK_INIT
+
+#define hab_rvt_report_event_p                                 \
+(                                                              \
+       ((is_cpu_type(MXC_CPU_MX6Q) ||                          \
+         is_cpu_type(MXC_CPU_MX6D)) &&                         \
+         (soc_rev() >= CHIP_REV_1_5)) ?                        \
+       ((hab_rvt_report_event_t *)HAB_RVT_REPORT_EVENT_NEW) :  \
+       (is_cpu_type(MXC_CPU_MX6DL) &&                          \
+        (soc_rev() >= CHIP_REV_1_2)) ?                         \
+       ((hab_rvt_report_event_t *)HAB_RVT_REPORT_EVENT_NEW) :  \
+       ((hab_rvt_report_event_t *)HAB_RVT_REPORT_EVENT)        \
+)
+
+#define hab_rvt_report_status_p                                        \
+(                                                              \
+       ((is_cpu_type(MXC_CPU_MX6Q) ||                          \
+         is_cpu_type(MXC_CPU_MX6D)) &&                         \
+         (soc_rev() >= CHIP_REV_1_5)) ?                        \
+       ((hab_rvt_report_status_t *)HAB_RVT_REPORT_STATUS_NEW) :\
+       (is_cpu_type(MXC_CPU_MX6DL) &&                          \
+        (soc_rev() >= CHIP_REV_1_2)) ?                         \
+       ((hab_rvt_report_status_t *)HAB_RVT_REPORT_STATUS_NEW) :\
+       ((hab_rvt_report_status_t *)HAB_RVT_REPORT_STATUS)      \
+)
+
+#define hab_rvt_authenticate_image_p                           \
+(                                                              \
+       ((is_cpu_type(MXC_CPU_MX6Q) ||                          \
+         is_cpu_type(MXC_CPU_MX6D)) &&                         \
+         (soc_rev() >= CHIP_REV_1_5)) ?                        \
+       ((hab_rvt_authenticate_image_t *)HAB_RVT_AUTHENTICATE_IMAGE_NEW) : \
+       (is_cpu_type(MXC_CPU_MX6DL) &&                          \
+        (soc_rev() >= CHIP_REV_1_2)) ?                         \
+       ((hab_rvt_authenticate_image_t *)HAB_RVT_AUTHENTICATE_IMAGE_NEW) : \
+       ((hab_rvt_authenticate_image_t *)HAB_RVT_AUTHENTICATE_IMAGE)    \
+)
+
+#define hab_rvt_entry_p                                                \
+(                                                              \
+       ((is_cpu_type(MXC_CPU_MX6Q) ||                          \
+         is_cpu_type(MXC_CPU_MX6D)) &&                         \
+         (soc_rev() >= CHIP_REV_1_5)) ?                        \
+       ((hab_rvt_entry_t *)HAB_RVT_ENTRY_NEW) :                \
+       (is_cpu_type(MXC_CPU_MX6DL) &&                          \
+        (soc_rev() >= CHIP_REV_1_2)) ?                         \
+       ((hab_rvt_entry_t *)HAB_RVT_ENTRY_NEW) :                \
+       ((hab_rvt_entry_t *)HAB_RVT_ENTRY)                      \
+)
+
+#define hab_rvt_exit_p                                         \
+(                                                              \
+       ((is_cpu_type(MXC_CPU_MX6Q) ||                          \
+         is_cpu_type(MXC_CPU_MX6D)) &&                         \
+         (soc_rev() >= CHIP_REV_1_5)) ?                        \
+       ((hab_rvt_exit_t *)HAB_RVT_EXIT_NEW) :                  \
+       (is_cpu_type(MXC_CPU_MX6DL) &&                          \
+        (soc_rev() >= CHIP_REV_1_2)) ?                         \
+       ((hab_rvt_exit_t *)HAB_RVT_EXIT_NEW) :                  \
+       ((hab_rvt_exit_t *)HAB_RVT_EXIT)                        \
+)
 
 bool is_hab_enabled(void)
 {
@@ -52,6 +106,11 @@ int get_hab_status(void)
        size_t bytes = sizeof(event_data); /* Event size in bytes */
        enum hab_config config = 0;
        enum hab_state state = 0;
+       hab_rvt_report_event_t *hab_rvt_report_event;
+       hab_rvt_report_status_t *hab_rvt_report_status;
+
+       hab_rvt_report_event = hab_rvt_report_event_p;
+       hab_rvt_report_status = hab_rvt_report_status_p;
 
        if (is_hab_enabled())
                puts("\nSecure boot enabled\n");
index 5f5132f..7695e16 100644 (file)
@@ -22,6 +22,10 @@ obj-y        += pipe3-phy.o
 obj-$(CONFIG_SCSI_AHCI_PLAT) += sata.o
 endif
 
+ifeq ($(CONFIG_SYS_DCACHE_OFF),)
+obj-y  += omap-cache.o
+endif
+
 ifeq ($(CONFIG_OMAP34XX),)
 obj-y  += boot-common.o
 obj-y  += lowlevel_init.o
index ba97d9e..5f50a19 100644 (file)
 #include <asm/emif.h>
 #include <asm/omap_common.h>
 #include <linux/compiler.h>
-#include <asm/cache.h>
 #include <asm/system.h>
 
-#define ARMV7_DCACHE_WRITEBACK  0xe
-#define        ARMV7_DOMAIN_CLIENT     1
-#define ARMV7_DOMAIN_MASK      (0x3 << 0)
-
 DECLARE_GLOBAL_DATA_PTR;
 
 void do_set_mux(u32 base, struct pad_conf_entry const *array, int size)
@@ -263,40 +258,3 @@ int print_cpuinfo(void)
        return 0;
 }
 #endif
-
-#ifndef CONFIG_SYS_DCACHE_OFF
-void enable_caches(void)
-{
-       /* Enable D-cache. I-cache is already enabled in start.S */
-       dcache_enable();
-}
-
-void dram_bank_mmu_setup(int bank)
-{
-       bd_t *bd = gd->bd;
-       int     i;
-
-       u32 start = bd->bi_dram[bank].start >> 20;
-       u32 size = bd->bi_dram[bank].size >> 20;
-       u32 end = start + size;
-
-       debug("%s: bank: %d\n", __func__, bank);
-       for (i = start; i < end; i++)
-               set_section_dcache(i, ARMV7_DCACHE_WRITEBACK);
-
-}
-
-void arm_init_domains(void)
-{
-       u32 reg;
-
-       reg = get_dacr();
-       /*
-       * Set DOMAIN to client access so that all permissions
-       * set in pagetables are validated by the mmu.
-       */
-       reg &= ~ARMV7_DOMAIN_MASK;
-       reg |= ARMV7_DOMAIN_CLIENT;
-       set_dacr(reg);
-}
-#endif
diff --git a/arch/arm/cpu/armv7/omap-common/omap-cache.c b/arch/arm/cpu/armv7/omap-common/omap-cache.c
new file mode 100644 (file)
index 0000000..579bebf
--- /dev/null
@@ -0,0 +1,56 @@
+/*
+ *
+ * Common functions for OMAP4/5 based boards
+ *
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ *
+ * Author :
+ *     Aneesh V        <aneesh@ti.com>
+ *     Steve Sakoman   <steve@sakoman.com>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/cache.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define ARMV7_DCACHE_WRITEBACK  0xe
+#define ARMV7_DOMAIN_CLIENT    1
+#define ARMV7_DOMAIN_MASK      (0x3 << 0)
+
+void enable_caches(void)
+{
+       /* Enable D-cache. I-cache is already enabled in start.S */
+       dcache_enable();
+}
+
+void dram_bank_mmu_setup(int bank)
+{
+       bd_t *bd = gd->bd;
+       int     i;
+
+       u32 start = bd->bi_dram[bank].start >> 20;
+       u32 size = bd->bi_dram[bank].size >> 20;
+       u32 end = start + size;
+
+       debug("%s: bank: %d\n", __func__, bank);
+       for (i = start; i < end; i++)
+               set_section_dcache(i, ARMV7_DCACHE_WRITEBACK);
+}
+
+void arm_init_domains(void)
+{
+       u32 reg;
+
+       reg = get_dacr();
+       /*
+       * Set DOMAIN to client access so that all permissions
+       * set in pagetables are validated by the mmu.
+       */
+       reg &= ~ARMV7_DOMAIN_MASK;
+       reg |= ARMV7_DOMAIN_CLIENT;
+       set_dacr(reg);
+}
index 2f9c939..667e77f 100644 (file)
@@ -478,11 +478,3 @@ void omap3_outer_cache_disable(void)
        omap3_update_aux_cr(0, 0x2);
 }
 #endif /* !CONFIG_SYS_L2CACHE_OFF */
-
-#ifndef CONFIG_SYS_DCACHE_OFF
-void enable_caches(void)
-{
-       /* Enable D-cache. I-cache is already enabled in start.S */
-       dcache_enable();
-}
-#endif /* !CONFIG_SYS_DCACHE_OFF */
index 69500a6..4dc9bb0 100644 (file)
@@ -18,6 +18,7 @@ SECTIONS
        .text :
        {
                *(.__image_copy_start)
+               *(.vectors)
                CPUDIR/start.o (.text*)
                *(.text*)
        }
index 5554615..61527a2 100644 (file)
@@ -31,6 +31,7 @@ dtb-$(CONFIG_ZYNQ) += zynq-zc702.dtb \
        zynq-zc770-xm010.dtb \
        zynq-zc770-xm012.dtb \
        zynq-zc770-xm013.dtb
+dtb-$(CONFIG_AM33XX) += am335x-boneblack.dtb
 
 targets += $(dtb-y)
 
diff --git a/arch/arm/dts/am335x-bone-common.dtsi b/arch/arm/dts/am335x-bone-common.dtsi
new file mode 100644 (file)
index 0000000..2f66ded
--- /dev/null
@@ -0,0 +1,262 @@
+/*
+ * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/ {
+       model = "TI AM335x BeagleBone";
+       compatible = "ti,am335x-bone", "ti,am33xx";
+
+       cpus {
+               cpu@0 {
+                       cpu0-supply = <&dcdc2_reg>;
+               };
+       };
+
+       memory {
+               device_type = "memory";
+               reg = <0x80000000 0x10000000>; /* 256 MB */
+       };
+
+       am33xx_pinmux: pinmux@44e10800 {
+               pinctrl-names = "default";
+               pinctrl-0 = <&clkout2_pin>;
+
+               user_leds_s0: user_leds_s0 {
+                       pinctrl-single,pins = <
+                               0x54 (PIN_OUTPUT_PULLDOWN | MUX_MODE7)  /* gpmc_a5.gpio1_21 */
+                               0x58 (PIN_OUTPUT_PULLUP | MUX_MODE7)    /* gpmc_a6.gpio1_22 */
+                               0x5c (PIN_OUTPUT_PULLDOWN | MUX_MODE7)  /* gpmc_a7.gpio1_23 */
+                               0x60 (PIN_OUTPUT_PULLUP | MUX_MODE7)    /* gpmc_a8.gpio1_24 */
+                       >;
+               };
+
+               i2c0_pins: pinmux_i2c0_pins {
+                       pinctrl-single,pins = <
+                               0x188 (PIN_INPUT_PULLUP | MUX_MODE0)    /* i2c0_sda.i2c0_sda */
+                               0x18c (PIN_INPUT_PULLUP | MUX_MODE0)    /* i2c0_scl.i2c0_scl */
+                       >;
+               };
+
+               uart0_pins: pinmux_uart0_pins {
+                       pinctrl-single,pins = <
+                               0x170 (PIN_INPUT_PULLUP | MUX_MODE0)    /* uart0_rxd.uart0_rxd */
+                               0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
+                       >;
+               };
+
+               clkout2_pin: pinmux_clkout2_pin {
+                       pinctrl-single,pins = <
+                               0x1b4 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr1.clkout2 */
+                       >;
+               };
+
+               cpsw_default: cpsw_default {
+                       pinctrl-single,pins = <
+                               /* Slave 1 */
+                               0x110 (PIN_INPUT_PULLUP | MUX_MODE0)    /* mii1_rxerr.mii1_rxerr */
+                               0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txen.mii1_txen */
+                               0x118 (PIN_INPUT_PULLUP | MUX_MODE0)    /* mii1_rxdv.mii1_rxdv */
+                               0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd3.mii1_txd3 */
+                               0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd2.mii1_txd2 */
+                               0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd1.mii1_txd1 */
+                               0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd0.mii1_txd0 */
+                               0x12c (PIN_INPUT_PULLUP | MUX_MODE0)    /* mii1_txclk.mii1_txclk */
+                               0x130 (PIN_INPUT_PULLUP | MUX_MODE0)    /* mii1_rxclk.mii1_rxclk */
+                               0x134 (PIN_INPUT_PULLUP | MUX_MODE0)    /* mii1_rxd3.mii1_rxd3 */
+                               0x138 (PIN_INPUT_PULLUP | MUX_MODE0)    /* mii1_rxd2.mii1_rxd2 */
+                               0x13c (PIN_INPUT_PULLUP | MUX_MODE0)    /* mii1_rxd1.mii1_rxd1 */
+                               0x140 (PIN_INPUT_PULLUP | MUX_MODE0)    /* mii1_rxd0.mii1_rxd0 */
+                       >;
+               };
+
+               cpsw_sleep: cpsw_sleep {
+                       pinctrl-single,pins = <
+                               /* Slave 1 reset value */
+                               0x110 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                               0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                               0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                               0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                               0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                               0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                               0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                               0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                               0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                               0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                               0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                               0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                               0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                       >;
+               };
+
+               davinci_mdio_default: davinci_mdio_default {
+                       pinctrl-single,pins = <
+                               /* MDIO */
+                               0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)    /* mdio_data.mdio_data */
+                               0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0)                   /* mdio_clk.mdio_clk */
+                       >;
+               };
+
+               davinci_mdio_sleep: davinci_mdio_sleep {
+                       pinctrl-single,pins = <
+                               /* MDIO reset value */
+                               0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                               0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                       >;
+               };
+       };
+
+       ocp {
+               uart0: serial@44e09000 {
+                       pinctrl-names = "default";
+                       pinctrl-0 = <&uart0_pins>;
+
+                       status = "okay";
+               };
+
+               musb: usb@47400000 {
+                       status = "okay";
+
+                       control@44e10000 {
+                               status = "okay";
+                       };
+
+                       usb-phy@47401300 {
+                               status = "okay";
+                       };
+
+                       usb-phy@47401b00 {
+                               status = "okay";
+                       };
+
+                       usb@47401000 {
+                               status = "okay";
+                       };
+
+                       usb@47401800 {
+                               status = "okay";
+                               dr_mode = "host";
+                       };
+
+                       dma-controller@07402000  {
+                               status = "okay";
+                       };
+               };
+
+               i2c0: i2c@44e0b000 {
+                       pinctrl-names = "default";
+                       pinctrl-0 = <&i2c0_pins>;
+
+                       status = "okay";
+                       clock-frequency = <400000>;
+
+                       tps: tps@24 {
+                               reg = <0x24>;
+                       };
+
+               };
+       };
+
+       leds {
+               pinctrl-names = "default";
+               pinctrl-0 = <&user_leds_s0>;
+
+               compatible = "gpio-leds";
+
+               led@2 {
+                       label = "beaglebone:green:heartbeat";
+                       gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>;
+                       linux,default-trigger = "heartbeat";
+                       default-state = "off";
+               };
+
+               led@3 {
+                       label = "beaglebone:green:mmc0";
+                       gpios = <&gpio1 22 GPIO_ACTIVE_HIGH>;
+                       linux,default-trigger = "mmc0";
+                       default-state = "off";
+               };
+
+               led@4 {
+                       label = "beaglebone:green:usr2";
+                       gpios = <&gpio1 23 GPIO_ACTIVE_HIGH>;
+                       default-state = "off";
+               };
+
+               led@5 {
+                       label = "beaglebone:green:usr3";
+                       gpios = <&gpio1 24 GPIO_ACTIVE_HIGH>;
+                       default-state = "off";
+               };
+       };
+};
+
+/include/ "tps65217.dtsi"
+
+&tps {
+       regulators {
+               dcdc1_reg: regulator@0 {
+                       regulator-always-on;
+               };
+
+               dcdc2_reg: regulator@1 {
+                       /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
+                       regulator-name = "vdd_mpu";
+                       regulator-min-microvolt = <925000>;
+                       regulator-max-microvolt = <1325000>;
+                       regulator-boot-on;
+                       regulator-always-on;
+               };
+
+               dcdc3_reg: regulator@2 {
+                       /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
+                       regulator-name = "vdd_core";
+                       regulator-min-microvolt = <925000>;
+                       regulator-max-microvolt = <1150000>;
+                       regulator-boot-on;
+                       regulator-always-on;
+               };
+
+               ldo1_reg: regulator@3 {
+                       regulator-always-on;
+               };
+
+               ldo2_reg: regulator@4 {
+                       regulator-always-on;
+               };
+
+               ldo3_reg: regulator@5 {
+                       regulator-always-on;
+               };
+
+               ldo4_reg: regulator@6 {
+                       regulator-always-on;
+               };
+       };
+};
+
+&cpsw_emac0 {
+       phy_id = <&davinci_mdio>, <0>;
+       phy-mode = "mii";
+};
+
+&cpsw_emac1 {
+       phy_id = <&davinci_mdio>, <1>;
+       phy-mode = "mii";
+};
+
+&mac {
+       pinctrl-names = "default", "sleep";
+       pinctrl-0 = <&cpsw_default>;
+       pinctrl-1 = <&cpsw_sleep>;
+
+};
+
+&davinci_mdio {
+       pinctrl-names = "default", "sleep";
+       pinctrl-0 = <&davinci_mdio_default>;
+       pinctrl-1 = <&davinci_mdio_sleep>;
+};
diff --git a/arch/arm/dts/am335x-boneblack.dts b/arch/arm/dts/am335x-boneblack.dts
new file mode 100644 (file)
index 0000000..197cadf
--- /dev/null
@@ -0,0 +1,17 @@
+/*
+ * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/dts-v1/;
+
+#include "am33xx.dtsi"
+#include "am335x-bone-common.dtsi"
+
+&ldo3_reg {
+       regulator-min-microvolt = <1800000>;
+       regulator-max-microvolt = <1800000>;
+       regulator-always-on;
+};
diff --git a/arch/arm/dts/am33xx.dtsi b/arch/arm/dts/am33xx.dtsi
new file mode 100644 (file)
index 0000000..f9c5da9
--- /dev/null
@@ -0,0 +1,649 @@
+/*
+ * Device Tree Source for AM33XX SoC
+ *
+ * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2.  This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/am33xx.h>
+
+#include "skeleton.dtsi"
+
+/ {
+       compatible = "ti,am33xx";
+       interrupt-parent = <&intc>;
+
+       aliases {
+               serial0 = &uart0;
+               serial1 = &uart1;
+               serial2 = &uart2;
+               serial3 = &uart3;
+               serial4 = &uart4;
+               serial5 = &uart5;
+               d_can0 = &dcan0;
+               d_can1 = &dcan1;
+               usb0 = &usb0;
+               usb1 = &usb1;
+               phy0 = &usb0_phy;
+               phy1 = &usb1_phy;
+       };
+
+       cpus {
+               #address-cells = <1>;
+               #size-cells = <0>;
+               cpu@0 {
+                       compatible = "arm,cortex-a8";
+                       device_type = "cpu";
+                       reg = <0>;
+
+                       /*
+                        * To consider voltage drop between PMIC and SoC,
+                        * tolerance value is reduced to 2% from 4% and
+                        * voltage value is increased as a precaution.
+                        */
+                       operating-points = <
+                               /* kHz    uV */
+                               720000  1285000
+                               600000  1225000
+                               500000  1125000
+                               275000  1125000
+                       >;
+                       voltage-tolerance = <2>; /* 2 percentage */
+                       clock-latency = <300000>; /* From omap-cpufreq driver */
+               };
+       };
+
+       /*
+        * The soc node represents the soc top level view. It is uses for IPs
+        * that are not memory mapped in the MPU view or for the MPU itself.
+        */
+       soc {
+               compatible = "ti,omap-infra";
+               mpu {
+                       compatible = "ti,omap3-mpu";
+                       ti,hwmods = "mpu";
+               };
+       };
+
+       am33xx_pinmux: pinmux@44e10800 {
+               compatible = "pinctrl-single";
+               reg = <0x44e10800 0x0238>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+               pinctrl-single,register-width = <32>;
+               pinctrl-single,function-mask = <0x7f>;
+       };
+
+       /*
+        * XXX: Use a flat representation of the AM33XX interconnect.
+        * The real AM33XX interconnect network is quite complex.Since
+        * that will not bring real advantage to represent that in DT
+        * for the moment, just use a fake OCP bus entry to represent
+        * the whole bus hierarchy.
+        */
+       ocp {
+               compatible = "simple-bus";
+               #address-cells = <1>;
+               #size-cells = <1>;
+               ranges;
+               ti,hwmods = "l3_main";
+
+               intc: interrupt-controller@48200000 {
+                       compatible = "ti,omap2-intc";
+                       interrupt-controller;
+                       #interrupt-cells = <1>;
+                       ti,intc-size = <128>;
+                       reg = <0x48200000 0x1000>;
+               };
+
+               gpio0: gpio@44e07000 {
+                       compatible = "ti,omap4-gpio";
+                       ti,hwmods = "gpio1";
+                       gpio-controller;
+                       #gpio-cells = <2>;
+                       interrupt-controller;
+                       #interrupt-cells = <1>;
+                       reg = <0x44e07000 0x1000>;
+                       interrupts = <96>;
+               };
+
+               gpio1: gpio@4804c000 {
+                       compatible = "ti,omap4-gpio";
+                       ti,hwmods = "gpio2";
+                       gpio-controller;
+                       #gpio-cells = <2>;
+                       interrupt-controller;
+                       #interrupt-cells = <1>;
+                       reg = <0x4804c000 0x1000>;
+                       interrupts = <98>;
+               };
+
+               gpio2: gpio@481ac000 {
+                       compatible = "ti,omap4-gpio";
+                       ti,hwmods = "gpio3";
+                       gpio-controller;
+                       #gpio-cells = <2>;
+                       interrupt-controller;
+                       #interrupt-cells = <1>;
+                       reg = <0x481ac000 0x1000>;
+                       interrupts = <32>;
+               };
+
+               gpio3: gpio@481ae000 {
+                       compatible = "ti,omap4-gpio";
+                       ti,hwmods = "gpio4";
+                       gpio-controller;
+                       #gpio-cells = <2>;
+                       interrupt-controller;
+                       #interrupt-cells = <1>;
+                       reg = <0x481ae000 0x1000>;
+                       interrupts = <62>;
+               };
+
+               uart0: serial@44e09000 {
+                       compatible = "ti,omap3-uart";
+                       ti,hwmods = "uart1";
+                       clock-frequency = <48000000>;
+                       reg = <0x44e09000 0x2000>;
+                       interrupts = <72>;
+                       status = "disabled";
+               };
+
+               uart1: serial@48022000 {
+                       compatible = "ti,omap3-uart";
+                       ti,hwmods = "uart2";
+                       clock-frequency = <48000000>;
+                       reg = <0x48022000 0x2000>;
+                       interrupts = <73>;
+                       status = "disabled";
+               };
+
+               uart2: serial@48024000 {
+                       compatible = "ti,omap3-uart";
+                       ti,hwmods = "uart3";
+                       clock-frequency = <48000000>;
+                       reg = <0x48024000 0x2000>;
+                       interrupts = <74>;
+                       status = "disabled";
+               };
+
+               uart3: serial@481a6000 {
+                       compatible = "ti,omap3-uart";
+                       ti,hwmods = "uart4";
+                       clock-frequency = <48000000>;
+                       reg = <0x481a6000 0x2000>;
+                       interrupts = <44>;
+                       status = "disabled";
+               };
+
+               uart4: serial@481a8000 {
+                       compatible = "ti,omap3-uart";
+                       ti,hwmods = "uart5";
+                       clock-frequency = <48000000>;
+                       reg = <0x481a8000 0x2000>;
+                       interrupts = <45>;
+                       status = "disabled";
+               };
+
+               uart5: serial@481aa000 {
+                       compatible = "ti,omap3-uart";
+                       ti,hwmods = "uart6";
+                       clock-frequency = <48000000>;
+                       reg = <0x481aa000 0x2000>;
+                       interrupts = <46>;
+                       status = "disabled";
+               };
+
+               i2c0: i2c@44e0b000 {
+                       compatible = "ti,omap4-i2c";
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       ti,hwmods = "i2c1";
+                       reg = <0x44e0b000 0x1000>;
+                       interrupts = <70>;
+                       status = "disabled";
+               };
+
+               i2c1: i2c@4802a000 {
+                       compatible = "ti,omap4-i2c";
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       ti,hwmods = "i2c2";
+                       reg = <0x4802a000 0x1000>;
+                       interrupts = <71>;
+                       status = "disabled";
+               };
+
+               i2c2: i2c@4819c000 {
+                       compatible = "ti,omap4-i2c";
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       ti,hwmods = "i2c3";
+                       reg = <0x4819c000 0x1000>;
+                       interrupts = <30>;
+                       status = "disabled";
+               };
+
+               wdt2: wdt@44e35000 {
+                       compatible = "ti,omap3-wdt";
+                       ti,hwmods = "wd_timer2";
+                       reg = <0x44e35000 0x1000>;
+                       interrupts = <91>;
+               };
+
+               dcan0: d_can@481cc000 {
+                       compatible = "bosch,d_can";
+                       ti,hwmods = "d_can0";
+                       reg = <0x481cc000 0x2000
+                               0x44e10644 0x4>;
+                       interrupts = <52>;
+                       status = "disabled";
+               };
+
+               dcan1: d_can@481d0000 {
+                       compatible = "bosch,d_can";
+                       ti,hwmods = "d_can1";
+                       reg = <0x481d0000 0x2000
+                               0x44e10644 0x4>;
+                       interrupts = <55>;
+                       status = "disabled";
+               };
+
+               timer1: timer@44e31000 {
+                       compatible = "ti,am335x-timer-1ms";
+                       reg = <0x44e31000 0x400>;
+                       interrupts = <67>;
+                       ti,hwmods = "timer1";
+                       ti,timer-alwon;
+               };
+
+               timer2: timer@48040000 {
+                       compatible = "ti,am335x-timer";
+                       reg = <0x48040000 0x400>;
+                       interrupts = <68>;
+                       ti,hwmods = "timer2";
+               };
+
+               timer3: timer@48042000 {
+                       compatible = "ti,am335x-timer";
+                       reg = <0x48042000 0x400>;
+                       interrupts = <69>;
+                       ti,hwmods = "timer3";
+               };
+
+               timer4: timer@48044000 {
+                       compatible = "ti,am335x-timer";
+                       reg = <0x48044000 0x400>;
+                       interrupts = <92>;
+                       ti,hwmods = "timer4";
+                       ti,timer-pwm;
+               };
+
+               timer5: timer@48046000 {
+                       compatible = "ti,am335x-timer";
+                       reg = <0x48046000 0x400>;
+                       interrupts = <93>;
+                       ti,hwmods = "timer5";
+                       ti,timer-pwm;
+               };
+
+               timer6: timer@48048000 {
+                       compatible = "ti,am335x-timer";
+                       reg = <0x48048000 0x400>;
+                       interrupts = <94>;
+                       ti,hwmods = "timer6";
+                       ti,timer-pwm;
+               };
+
+               timer7: timer@4804a000 {
+                       compatible = "ti,am335x-timer";
+                       reg = <0x4804a000 0x400>;
+                       interrupts = <95>;
+                       ti,hwmods = "timer7";
+                       ti,timer-pwm;
+               };
+
+               rtc@44e3e000 {
+                       compatible = "ti,da830-rtc";
+                       reg = <0x44e3e000 0x1000>;
+                       interrupts = <75
+                                     76>;
+                       ti,hwmods = "rtc";
+               };
+
+               spi0: spi@48030000 {
+                       compatible = "ti,omap4-mcspi";
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       reg = <0x48030000 0x400>;
+                       interrupts = <65>;
+                       ti,spi-num-cs = <2>;
+                       ti,hwmods = "spi0";
+                       status = "disabled";
+               };
+
+               spi1: spi@481a0000 {
+                       compatible = "ti,omap4-mcspi";
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       reg = <0x481a0000 0x400>;
+                       interrupts = <125>;
+                       ti,spi-num-cs = <2>;
+                       ti,hwmods = "spi1";
+                       status = "disabled";
+               };
+
+               usb: usb@47400000 {
+                       compatible = "ti,am33xx-usb";
+                       reg = <0x47400000 0x1000>;
+                       ranges;
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       ti,hwmods = "usb_otg_hs";
+                       status = "disabled";
+
+                       ctrl_mod: control@44e10000 {
+                               compatible = "ti,am335x-usb-ctrl-module";
+                               reg = <0x44e10620 0x10
+                                       0x44e10648 0x4>;
+                               reg-names = "phy_ctrl", "wakeup";
+                               status = "disabled";
+                       };
+
+                       usb0_phy: usb-phy@47401300 {
+                               compatible = "ti,am335x-usb-phy";
+                               reg = <0x47401300 0x100>;
+                               reg-names = "phy";
+                               status = "disabled";
+                               ti,ctrl_mod = <&ctrl_mod>;
+                       };
+
+                       usb0: usb@47401000 {
+                               compatible = "ti,musb-am33xx";
+                               status = "disabled";
+                               reg = <0x47401400 0x400
+                                       0x47401000 0x200>;
+                               reg-names = "mc", "control";
+
+                               interrupts = <18>;
+                               interrupt-names = "mc";
+                               dr_mode = "otg";
+                               mentor,multipoint = <1>;
+                               mentor,num-eps = <16>;
+                               mentor,ram-bits = <12>;
+                               mentor,power = <500>;
+                               phys = <&usb0_phy>;
+
+                               dmas = <&cppi41dma  0 0 &cppi41dma  1 0
+                                       &cppi41dma  2 0 &cppi41dma  3 0
+                                       &cppi41dma  4 0 &cppi41dma  5 0
+                                       &cppi41dma  6 0 &cppi41dma  7 0
+                                       &cppi41dma  8 0 &cppi41dma  9 0
+                                       &cppi41dma 10 0 &cppi41dma 11 0
+                                       &cppi41dma 12 0 &cppi41dma 13 0
+                                       &cppi41dma 14 0 &cppi41dma  0 1
+                                       &cppi41dma  1 1 &cppi41dma  2 1
+                                       &cppi41dma  3 1 &cppi41dma  4 1
+                                       &cppi41dma  5 1 &cppi41dma  6 1
+                                       &cppi41dma  7 1 &cppi41dma  8 1
+                                       &cppi41dma  9 1 &cppi41dma 10 1
+                                       &cppi41dma 11 1 &cppi41dma 12 1
+                                       &cppi41dma 13 1 &cppi41dma 14 1>;
+                               dma-names =
+                                       "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7",
+                                       "rx8", "rx9", "rx10", "rx11", "rx12", "rx13",
+                                       "rx14", "rx15",
+                                       "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7",
+                                       "tx8", "tx9", "tx10", "tx11", "tx12", "tx13",
+                                       "tx14", "tx15";
+                       };
+
+                       usb1_phy: usb-phy@47401b00 {
+                               compatible = "ti,am335x-usb-phy";
+                               reg = <0x47401b00 0x100>;
+                               reg-names = "phy";
+                               status = "disabled";
+                               ti,ctrl_mod = <&ctrl_mod>;
+                       };
+
+                       usb1: usb@47401800 {
+                               compatible = "ti,musb-am33xx";
+                               status = "disabled";
+                               reg = <0x47401c00 0x400
+                                       0x47401800 0x200>;
+                               reg-names = "mc", "control";
+                               interrupts = <19>;
+                               interrupt-names = "mc";
+                               dr_mode = "otg";
+                               mentor,multipoint = <1>;
+                               mentor,num-eps = <16>;
+                               mentor,ram-bits = <12>;
+                               mentor,power = <500>;
+                               phys = <&usb1_phy>;
+
+                               dmas = <&cppi41dma 15 0 &cppi41dma 16 0
+                                       &cppi41dma 17 0 &cppi41dma 18 0
+                                       &cppi41dma 19 0 &cppi41dma 20 0
+                                       &cppi41dma 21 0 &cppi41dma 22 0
+                                       &cppi41dma 23 0 &cppi41dma 24 0
+                                       &cppi41dma 25 0 &cppi41dma 26 0
+                                       &cppi41dma 27 0 &cppi41dma 28 0
+                                       &cppi41dma 29 0 &cppi41dma 15 1
+                                       &cppi41dma 16 1 &cppi41dma 17 1
+                                       &cppi41dma 18 1 &cppi41dma 19 1
+                                       &cppi41dma 20 1 &cppi41dma 21 1
+                                       &cppi41dma 22 1 &cppi41dma 23 1
+                                       &cppi41dma 24 1 &cppi41dma 25 1
+                                       &cppi41dma 26 1 &cppi41dma 27 1
+                                       &cppi41dma 28 1 &cppi41dma 29 1>;
+                               dma-names =
+                                       "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7",
+                                       "rx8", "rx9", "rx10", "rx11", "rx12", "rx13",
+                                       "rx14", "rx15",
+                                       "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7",
+                                       "tx8", "tx9", "tx10", "tx11", "tx12", "tx13",
+                                       "tx14", "tx15";
+                       };
+
+                       cppi41dma: dma-controller@07402000 {
+                               compatible = "ti,am3359-cppi41";
+                               reg =  <0x47400000 0x1000
+                                       0x47402000 0x1000
+                                       0x47403000 0x1000
+                                       0x47404000 0x4000>;
+                               reg-names = "glue", "controller", "scheduler", "queuemgr";
+                               interrupts = <17>;
+                               interrupt-names = "glue";
+                               #dma-cells = <2>;
+                               #dma-channels = <30>;
+                               #dma-requests = <256>;
+                               status = "disabled";
+                       };
+               };
+
+               epwmss0: epwmss@48300000 {
+                       compatible = "ti,am33xx-pwmss";
+                       reg = <0x48300000 0x10>;
+                       ti,hwmods = "epwmss0";
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       status = "disabled";
+                       ranges = <0x48300100 0x48300100 0x80   /* ECAP */
+                                 0x48300180 0x48300180 0x80   /* EQEP */
+                                 0x48300200 0x48300200 0x80>; /* EHRPWM */
+
+                       ecap0: ecap@48300100 {
+                               compatible = "ti,am33xx-ecap";
+                               #pwm-cells = <3>;
+                               reg = <0x48300100 0x80>;
+                               ti,hwmods = "ecap0";
+                               status = "disabled";
+                       };
+
+                       ehrpwm0: ehrpwm@48300200 {
+                               compatible = "ti,am33xx-ehrpwm";
+                               #pwm-cells = <3>;
+                               reg = <0x48300200 0x80>;
+                               ti,hwmods = "ehrpwm0";
+                               status = "disabled";
+                       };
+               };
+
+               epwmss1: epwmss@48302000 {
+                       compatible = "ti,am33xx-pwmss";
+                       reg = <0x48302000 0x10>;
+                       ti,hwmods = "epwmss1";
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       status = "disabled";
+                       ranges = <0x48302100 0x48302100 0x80   /* ECAP */
+                                 0x48302180 0x48302180 0x80   /* EQEP */
+                                 0x48302200 0x48302200 0x80>; /* EHRPWM */
+
+                       ecap1: ecap@48302100 {
+                               compatible = "ti,am33xx-ecap";
+                               #pwm-cells = <3>;
+                               reg = <0x48302100 0x80>;
+                               ti,hwmods = "ecap1";
+                               status = "disabled";
+                       };
+
+                       ehrpwm1: ehrpwm@48302200 {
+                               compatible = "ti,am33xx-ehrpwm";
+                               #pwm-cells = <3>;
+                               reg = <0x48302200 0x80>;
+                               ti,hwmods = "ehrpwm1";
+                               status = "disabled";
+                       };
+               };
+
+               epwmss2: epwmss@48304000 {
+                       compatible = "ti,am33xx-pwmss";
+                       reg = <0x48304000 0x10>;
+                       ti,hwmods = "epwmss2";
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       status = "disabled";
+                       ranges = <0x48304100 0x48304100 0x80   /* ECAP */
+                                 0x48304180 0x48304180 0x80   /* EQEP */
+                                 0x48304200 0x48304200 0x80>; /* EHRPWM */
+
+                       ecap2: ecap@48304100 {
+                               compatible = "ti,am33xx-ecap";
+                               #pwm-cells = <3>;
+                               reg = <0x48304100 0x80>;
+                               ti,hwmods = "ecap2";
+                               status = "disabled";
+                       };
+
+                       ehrpwm2: ehrpwm@48304200 {
+                               compatible = "ti,am33xx-ehrpwm";
+                               #pwm-cells = <3>;
+                               reg = <0x48304200 0x80>;
+                               ti,hwmods = "ehrpwm2";
+                               status = "disabled";
+                       };
+               };
+
+               mac: ethernet@4a100000 {
+                       compatible = "ti,cpsw";
+                       ti,hwmods = "cpgmac0";
+                       cpdma_channels = <8>;
+                       ale_entries = <1024>;
+                       bd_ram_size = <0x2000>;
+                       no_bd_ram = <0>;
+                       rx_descs = <64>;
+                       mac_control = <0x20>;
+                       slaves = <2>;
+                       active_slave = <0>;
+                       cpts_clock_mult = <0x80000000>;
+                       cpts_clock_shift = <29>;
+                       reg = <0x4a100000 0x800
+                              0x4a101200 0x100>;
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       interrupt-parent = <&intc>;
+                       /*
+                        * c0_rx_thresh_pend
+                        * c0_rx_pend
+                        * c0_tx_pend
+                        * c0_misc_pend
+                        */
+                       interrupts = <40 41 42 43>;
+                       ranges;
+
+                       davinci_mdio: mdio@4a101000 {
+                               compatible = "ti,davinci_mdio";
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                               ti,hwmods = "davinci_mdio";
+                               bus_freq = <1000000>;
+                               reg = <0x4a101000 0x100>;
+                       };
+
+                       cpsw_emac0: slave@4a100200 {
+                               /* Filled in by U-Boot */
+                               mac-address = [ 00 00 00 00 00 00 ];
+                       };
+
+                       cpsw_emac1: slave@4a100300 {
+                               /* Filled in by U-Boot */
+                               mac-address = [ 00 00 00 00 00 00 ];
+                       };
+               };
+
+               ocmcram: ocmcram@40300000 {
+                       compatible = "ti,am3352-ocmcram";
+                       reg = <0x40300000 0x10000>;
+                       ti,hwmods = "ocmcram";
+               };
+
+               wkup_m3: wkup_m3@44d00000 {
+                       compatible = "ti,am3353-wkup-m3";
+                       reg = <0x44d00000 0x4000        /* M3 UMEM */
+                              0x44d80000 0x2000>;      /* M3 DMEM */
+                       ti,hwmods = "wkup_m3";
+               };
+
+               elm: elm@48080000 {
+                       compatible = "ti,am3352-elm";
+                       reg = <0x48080000 0x2000>;
+                       interrupts = <4>;
+                       ti,hwmods = "elm";
+                       status = "disabled";
+               };
+
+               tscadc: tscadc@44e0d000 {
+                       compatible = "ti,am3359-tscadc";
+                       reg = <0x44e0d000 0x1000>;
+                       interrupt-parent = <&intc>;
+                       interrupts = <16>;
+                       ti,hwmods = "adc_tsc";
+                       status = "disabled";
+
+                       tsc {
+                               compatible = "ti,am3359-tsc";
+                       };
+                       am335x_adc: adc {
+                               #io-channel-cells = <1>;
+                               compatible = "ti,am3359-adc";
+                       };
+               };
+
+               gpmc: gpmc@50000000 {
+                       compatible = "ti,am3352-gpmc";
+                       ti,hwmods = "gpmc";
+                       reg = <0x50000000 0x2000>;
+                       interrupts = <100>;
+                       gpmc,num-cs = <7>;
+                       gpmc,num-waitpins = <2>;
+                       #address-cells = <2>;
+                       #size-cells = <1>;
+                       status = "disabled";
+               };
+       };
+};
diff --git a/arch/arm/dts/dt-bindings/gpio/gpio.h b/arch/arm/dts/dt-bindings/gpio/gpio.h
new file mode 100644 (file)
index 0000000..e6b1e0a
--- /dev/null
@@ -0,0 +1,15 @@
+/*
+ * This header provides constants for most GPIO bindings.
+ *
+ * Most GPIO bindings include a flags cell as part of the GPIO specifier.
+ * In most cases, the format of the flags cell uses the standard values
+ * defined in this header.
+ */
+
+#ifndef _DT_BINDINGS_GPIO_GPIO_H
+#define _DT_BINDINGS_GPIO_GPIO_H
+
+#define GPIO_ACTIVE_HIGH 0
+#define GPIO_ACTIVE_LOW 1
+
+#endif
diff --git a/arch/arm/dts/dt-bindings/pinctrl/am33xx.h b/arch/arm/dts/dt-bindings/pinctrl/am33xx.h
new file mode 100644 (file)
index 0000000..2fbc804
--- /dev/null
@@ -0,0 +1,42 @@
+/*
+ * This header provides constants specific to AM33XX pinctrl bindings.
+ */
+
+#ifndef _DT_BINDINGS_PINCTRL_AM33XX_H
+#define _DT_BINDINGS_PINCTRL_AM33XX_H
+
+#include <dt-bindings/pinctrl/omap.h>
+
+/* am33xx specific mux bit defines */
+#undef PULL_ENA
+#undef INPUT_EN
+
+#define PULL_DISABLE           (1 << 3)
+#define INPUT_EN               (1 << 5)
+#define SLEWCTRL_FAST          (1 << 6)
+
+/* update macro depending on INPUT_EN and PULL_ENA */
+#undef PIN_OUTPUT
+#undef PIN_OUTPUT_PULLUP
+#undef PIN_OUTPUT_PULLDOWN
+#undef PIN_INPUT
+#undef PIN_INPUT_PULLUP
+#undef PIN_INPUT_PULLDOWN
+
+#define PIN_OUTPUT             (PULL_DISABLE)
+#define PIN_OUTPUT_PULLUP      (PULL_UP)
+#define PIN_OUTPUT_PULLDOWN    0
+#define PIN_INPUT              (INPUT_EN | PULL_DISABLE)
+#define PIN_INPUT_PULLUP       (INPUT_EN | PULL_UP)
+#define PIN_INPUT_PULLDOWN     (INPUT_EN)
+
+/* undef non-existing modes */
+#undef PIN_OFF_NONE
+#undef PIN_OFF_OUTPUT_HIGH
+#undef PIN_OFF_OUTPUT_LOW
+#undef PIN_OFF_INPUT_PULLUP
+#undef PIN_OFF_INPUT_PULLDOWN
+#undef PIN_OFF_WAKEUPENABLE
+
+#endif
+
diff --git a/arch/arm/dts/dt-bindings/pinctrl/omap.h b/arch/arm/dts/dt-bindings/pinctrl/omap.h
new file mode 100644 (file)
index 0000000..edbd250
--- /dev/null
@@ -0,0 +1,55 @@
+/*
+ * This header provides constants for OMAP pinctrl bindings.
+ *
+ * Copyright (C) 2009 Nokia
+ * Copyright (C) 2009-2010 Texas Instruments
+ */
+
+#ifndef _DT_BINDINGS_PINCTRL_OMAP_H
+#define _DT_BINDINGS_PINCTRL_OMAP_H
+
+/* 34xx mux mode options for each pin. See TRM for options */
+#define MUX_MODE0      0
+#define MUX_MODE1      1
+#define MUX_MODE2      2
+#define MUX_MODE3      3
+#define MUX_MODE4      4
+#define MUX_MODE5      5
+#define MUX_MODE6      6
+#define MUX_MODE7      7
+
+/* 24xx/34xx mux bit defines */
+#define PULL_ENA               (1 << 3)
+#define PULL_UP                        (1 << 4)
+#define ALTELECTRICALSEL       (1 << 5)
+
+/* 34xx specific mux bit defines */
+#define INPUT_EN               (1 << 8)
+#define OFF_EN                 (1 << 9)
+#define OFFOUT_EN              (1 << 10)
+#define OFFOUT_VAL             (1 << 11)
+#define OFF_PULL_EN            (1 << 12)
+#define OFF_PULL_UP            (1 << 13)
+#define WAKEUP_EN              (1 << 14)
+
+/* 44xx specific mux bit defines */
+#define WAKEUP_EVENT           (1 << 15)
+
+/* Active pin states */
+#define PIN_OUTPUT             0
+#define PIN_OUTPUT_PULLUP      (PIN_OUTPUT | PULL_ENA | PULL_UP)
+#define PIN_OUTPUT_PULLDOWN    (PIN_OUTPUT | PULL_ENA)
+#define PIN_INPUT              INPUT_EN
+#define PIN_INPUT_PULLUP       (PULL_ENA | INPUT_EN | PULL_UP)
+#define PIN_INPUT_PULLDOWN     (PULL_ENA | INPUT_EN)
+
+/* Off mode states */
+#define PIN_OFF_NONE           0
+#define PIN_OFF_OUTPUT_HIGH    (OFF_EN | OFFOUT_EN | OFFOUT_VAL)
+#define PIN_OFF_OUTPUT_LOW     (OFF_EN | OFFOUT_EN)
+#define PIN_OFF_INPUT_PULLUP   (OFF_EN | OFF_PULL_EN | OFF_PULL_UP)
+#define PIN_OFF_INPUT_PULLDOWN (OFF_EN | OFF_PULL_EN)
+#define PIN_OFF_WAKEUPENABLE   WAKEUP_EN
+
+#endif
+
diff --git a/arch/arm/dts/include/dt-bindings b/arch/arm/dts/include/dt-bindings
new file mode 120000 (symlink)
index 0000000..0cecb3d
--- /dev/null
@@ -0,0 +1 @@
+../../../../include/dt-bindings
\ No newline at end of file
index f52fcf1..59434e0 100644 (file)
@@ -1,3 +1,6 @@
+#include <dt-bindings/gpio/tegra-gpio.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
 #include "skeleton.dtsi"
 
 / {
                              0 143 0x04>;
        };
 
-       gpio: gpio {
+       gpio: gpio@6000d000 {
                compatible = "nvidia,tegra114-gpio", "nvidia,tegra30-gpio";
                reg = <0x6000d000 0x1000>;
-               interrupts = <0 32 0x04
-                             0 33 0x04
-                             0 34 0x04
-                             0 35 0x04
-                             0 55 0x04
-                             0 87 0x04
-                             0 89 0x04
-                             0 125 0x04>;
+               interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
                #gpio-cells = <2>;
                gpio-controller;
                #interrupt-cells = <2>;
index 18a8b24..4561c5f 100644 (file)
@@ -1,3 +1,6 @@
+#include <dt-bindings/gpio/tegra-gpio.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
 #include "skeleton.dtsi"
 
 / {
        gpio: gpio@6000d000 {
                compatible = "nvidia,tegra124-gpio", "nvidia,tegra30-gpio";
                reg = <0x6000d000 0x1000>;
-               interrupts = <0 32 0x04
-                             0 33 0x04
-                             0 34 0x04
-                             0 35 0x04
-                             0 55 0x04
-                             0 87 0x04
-                             0 89 0x04
-                             0 125 0x04>;
+               interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
                #gpio-cells = <2>;
                gpio-controller;
                #interrupt-cells = <2>;
index 3805750..a524f6e 100644 (file)
@@ -1,3 +1,6 @@
+#include <dt-bindings/gpio/tegra-gpio.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
 #include "skeleton.dtsi"
 
 / {
 
        gpio: gpio@6000d000 {
                compatible = "nvidia,tegra20-gpio";
-               reg = < 0x6000d000 0x1000 >;
-               interrupts = < 64 65 66 67 87 119 121 >;
+               reg = <0x6000d000 0x1000>;
+               interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
                #gpio-cells = <2>;
                gpio-controller;
+               #interrupt-cells = <2>;
+               interrupt-controller;
        };
 
        pinmux: pinmux@70000000 {
index fee1c36..7be3791 100644 (file)
@@ -1,3 +1,6 @@
+#include <dt-bindings/gpio/tegra-gpio.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
 #include "skeleton.dtsi"
 
 / {
                clocks = <&tegra_car 34>;
        };
 
-       gpio: gpio {
+       gpio: gpio@6000d000 {
                compatible = "nvidia,tegra30-gpio";
                reg = <0x6000d000 0x1000>;
-               interrupts = <0 32 0x04
-                             0 33 0x04
-                             0 34 0x04
-                             0 35 0x04
-                             0 55 0x04
-                             0 87 0x04
-                             0 89 0x04
-                             0 125 0x04>;
+               interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
                #gpio-cells = <2>;
                gpio-controller;
                #interrupt-cells = <2>;
diff --git a/arch/arm/dts/tps65217.dtsi b/arch/arm/dts/tps65217.dtsi
new file mode 100644 (file)
index 0000000..a632724
--- /dev/null
@@ -0,0 +1,56 @@
+/*
+ * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/*
+ * Integrated Power Management Chip
+ * http://www.ti.com/lit/ds/symlink/tps65217.pdf
+ */
+
+&tps {
+       compatible = "ti,tps65217";
+
+       regulators {
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               dcdc1_reg: regulator@0 {
+                       reg = <0>;
+                       regulator-compatible = "dcdc1";
+               };
+
+               dcdc2_reg: regulator@1 {
+                       reg = <1>;
+                       regulator-compatible = "dcdc2";
+               };
+
+               dcdc3_reg: regulator@2 {
+                       reg = <2>;
+                       regulator-compatible = "dcdc3";
+               };
+
+               ldo1_reg: regulator@3 {
+                       reg = <3>;
+                       regulator-compatible = "ldo1";
+               };
+
+               ldo2_reg: regulator@4 {
+                       reg = <4>;
+                       regulator-compatible = "ldo2";
+               };
+
+               ldo3_reg: regulator@5 {
+                       reg = <5>;
+                       regulator-compatible = "ldo3";
+               };
+
+               ldo4_reg: regulator@6 {
+                       reg = <6>;
+                       regulator-compatible = "ldo4";
+               };
+       };
+};
index 0e71395..25a9d4c 100644 (file)
@@ -16,6 +16,7 @@ obj-$(CONFIG_SYS_I2C_MXC) += i2c-mxv7.o
 endif
 ifeq ($(SOC),$(filter $(SOC),mx6 mxs))
 obj-y  += misc.o
+obj-$(CONFIG_SPL_BUILD)        += spl.o
 endif
 ifeq ($(SOC),$(filter $(SOC),mx6))
 obj-$(CONFIG_CMD_SATA) += sata.o
@@ -33,10 +34,6 @@ $(IMX_CONFIG): %.cfgtmp: % FORCE
        $(Q)mkdir -p $(dir $@)
        $(call if_changed_dep,cpp_cfg)
 
-quiet_cmd_mkimage = MKIMAGE $@
-cmd_mkimage = $(objtree)/tools/mkimage $(MKIMAGEFLAGS_$(@F)) -d $< $@ \
-       $(if $(KBUILD_VERBOSE:1=), >/dev/null)
-
 MKIMAGEFLAGS_u-boot.imx = -n $(filter-out $< $(PHONY),$^) -T imximage \
        -e $(CONFIG_SYS_TEXT_BASE)
 
index a77c4de..5a09107 100644 (file)
@@ -58,6 +58,7 @@ char *get_reset_cause(void)
 static const unsigned char col_lookup[] = {9, 10, 11, 8, 12, 9, 9, 9};
 static const unsigned char bank_lookup[] = {3, 2};
 
+/* these MMDC registers are common to the IMX53 and IMX6 */
 struct esd_mmdc_regs {
        uint32_t        ctl;
        uint32_t        pdc;
@@ -66,15 +67,6 @@ struct esd_mmdc_regs {
        uint32_t        cfg1;
        uint32_t        cfg2;
        uint32_t        misc;
-       uint32_t        scr;
-       uint32_t        ref;
-       uint32_t        rsvd1;
-       uint32_t        rsvd2;
-       uint32_t        rwd;
-       uint32_t        or;
-       uint32_t        mrr;
-       uint32_t        cfg3lp;
-       uint32_t        mr4;
 };
 
 #define ESD_MMDC_CTL_GET_ROW(mdctl)    ((ctl >> 24) & 7)
@@ -83,6 +75,12 @@ struct esd_mmdc_regs {
 #define ESD_MMDC_CTL_GET_CS1(mdctl)    ((ctl >> 30) & 1)
 #define ESD_MMDC_MISC_GET_BANK(mdmisc) ((misc >> 5) & 1)
 
+/*
+ * imx_ddr_size - return size in bytes of DRAM according MMDC config
+ * The MMDC MDCTL register holds the number of bits for row, col, and data
+ * width and the MMDC MDMISC register holds the number of banks. Combine
+ * all these bits to determine the meme size the MMDC has been configured for
+ */
 unsigned imx_ddr_size(void)
 {
        struct esd_mmdc_regs *mem = (struct esd_mmdc_regs *)MEMCTL_BASE;
index 6e46ea8..22cd11a 100644 (file)
@@ -11,6 +11,9 @@
 #include <common.h>
 #include <asm/io.h>
 #include <asm/arch/imx-regs.h>
+#if !defined(CONFIG_MX25) && !defined(CONFIG_VF610)
+#include <asm/arch/sys_proto.h>
+#endif
 #include <asm/imx-common/iomux-v3.h>
 
 static void *base = (void *)IOMUXC_BASE_ADDR;
@@ -54,12 +57,23 @@ void imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad)
 #endif
 }
 
+/* configures a list of pads within declared with IOMUX_PADS macro */
 void imx_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t const *pad_list,
                                      unsigned count)
 {
        iomux_v3_cfg_t const *p = pad_list;
+       int stride;
        int i;
 
-       for (i = 0; i < count; i++)
-               imx_iomux_v3_setup_pad(*p++);
+#if defined(CONFIG_MX6QDL)
+       stride = 2;
+       if (!is_cpu_type(MXC_CPU_MX6Q) && !is_cpu_type(MXC_CPU_MX6D))
+               p += 1;
+#else
+       stride = 1;
+#endif
+       for (i = 0; i < count; i++) {
+               imx_iomux_v3_setup_pad(*p);
+               p += stride;
+       }
 }
index 2e69486..c10dd28 100644 (file)
@@ -8,13 +8,18 @@
 #include <asm/arch/iomux.h>
 #include <asm/io.h>
 #include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
 
 int setup_sata(void)
 {
        struct iomuxc_base_regs *const iomuxc_regs
                = (struct iomuxc_base_regs *)IOMUXC_BASE_ADDR;
+       int ret;
 
-       int ret = enable_sata_clock();
+       if (!is_cpu_type(MXC_CPU_MX6Q) && !is_cpu_type(MXC_CPU_MX6D))
+               return 1;
+
+       ret = enable_sata_clock();
        if (ret)
                return ret;
 
diff --git a/arch/arm/imx-common/spl.c b/arch/arm/imx-common/spl.c
new file mode 100644 (file)
index 0000000..9a02a64
--- /dev/null
@@ -0,0 +1,81 @@
+/*
+ * Copyright (C) 2014 Gateworks Corporation
+ * Copyright (C) 2011-2012 Freescale Semiconductor, Inc.
+ *
+ * Author: Tim Harvey <tharvey@gateworks.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/spl.h>
+#include <spl.h>
+
+#if defined(CONFIG_MX6)
+/* determine boot device from SRC_SBMR1 register (BOOT_CFG[4:1]) */
+u32 spl_boot_device(void)
+{
+       struct src *psrc = (struct src *)SRC_BASE_ADDR;
+       unsigned reg = readl(&psrc->sbmr1);
+
+       /* BOOT_CFG1[7:4] - see IMX6DQRM Table 8-8 */
+       switch ((reg & 0x000000FF) >> 4) {
+        /* EIM: See 8.5.1, Table 8-9 */
+       case 0x0:
+               /* BOOT_CFG1[3]: NOR/OneNAND Selection */
+               if ((reg & 0x00000008) >> 3)
+                       return BOOT_DEVICE_ONENAND;
+               else
+                       return BOOT_DEVICE_NOR;
+               break;
+       /* SATA: See 8.5.4, Table 8-20 */
+       case 0x2:
+               return BOOT_DEVICE_SATA;
+       /* Serial ROM: See 8.5.5.1, Table 8-22 */
+       case 0x3:
+               /* BOOT_CFG4[2:0] */
+               switch ((reg & 0x07000000) >> 24) {
+               case 0x0 ... 0x4:
+                       return BOOT_DEVICE_SPI;
+               case 0x5 ... 0x7:
+                       return BOOT_DEVICE_I2C;
+               }
+               break;
+       /* SD/eSD: 8.5.3, Table 8-15  */
+       case 0x4:
+       case 0x5:
+               return BOOT_DEVICE_MMC1;
+       /* MMC/eMMC: 8.5.3 */
+       case 0x6:
+       case 0x7:
+               return BOOT_DEVICE_MMC1;
+       /* NAND Flash: 8.5.2 */
+       case 0x8 ... 0xf:
+               return BOOT_DEVICE_NAND;
+       }
+       return BOOT_DEVICE_NONE;
+}
+#endif
+
+#if defined(CONFIG_SPL_MMC_SUPPORT)
+/* called from spl_mmc to see type of boot mode for storage (RAW or FAT) */
+u32 spl_boot_mode(void)
+{
+       switch (spl_boot_device()) {
+       /* for MMC return either RAW or FAT mode */
+       case BOOT_DEVICE_MMC1:
+       case BOOT_DEVICE_MMC2:
+#ifdef CONFIG_SPL_FAT_SUPPORT
+               return MMCSD_MODE_FAT;
+#else
+               return MMCSD_MODE_RAW;
+#endif
+               break;
+       default:
+               puts("spl: ERROR:  unsupported device\n");
+               hang();
+       }
+}
+#endif
diff --git a/arch/arm/include/asm/arch-at91/spl.h b/arch/arm/include/asm/arch-at91/spl.h
deleted file mode 100644 (file)
index d8a87da..0000000
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * Copyright (C) 2013 Atmel Corporation
- *                   Bo Shen <voice.shen@atmel.com>
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-#ifndef        _ASM_ARCH_SPL_H_
-#define        _ASM_ARCH_SPL_H_
-
-enum {
-       BOOT_DEVICE_NONE,
-#ifdef CONFIG_SYS_USE_MMC
-       BOOT_DEVICE_MMC1,
-       BOOT_DEVICE_MMC2,
-       BOOT_DEVICE_MMC2_2,
-#elif CONFIG_SYS_USE_NANDFLASH
-       BOOT_DEVICE_NAND,
-#elif CONFIG_SYS_USE_SERIALFLASH
-       BOOT_DEVICE_SPI,
-#endif
-};
-
-#endif
diff --git a/arch/arm/include/asm/arch-davinci/spl.h b/arch/arm/include/asm/arch-davinci/spl.h
deleted file mode 100644 (file)
index 5afe0d4..0000000
+++ /dev/null
@@ -1,16 +0,0 @@
-/*
- * (C) Copyright 2012
- * Texas Instruments, <www.ti.com>
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-#ifndef        _ASM_ARCH_SPL_H_
-#define        _ASM_ARCH_SPL_H_
-
-#define BOOT_DEVICE_NAND       1
-#define BOOT_DEVICE_SPI                2
-#define BOOT_DEVICE_MMC1       3
-#define BOOT_DEVICE_MMC2       4       /* dummy */
-#define BOOT_DEVICE_MMC2_2     5       /* dummy */
-
-#endif
diff --git a/arch/arm/include/asm/arch-mx35/spl.h b/arch/arm/include/asm/arch-mx35/spl.h
deleted file mode 100644 (file)
index d0efec2..0000000
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * (C) Copyright 2012
- * Texas Instruments, <www.ti.com>
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-#ifndef        _ASM_ARCH_SPL_H_
-#define        _ASM_ARCH_SPL_H_
-
-#define BOOT_DEVICE_NONE       0
-#define BOOT_DEVICE_XIP                1
-#define BOOT_DEVICE_XIPWAIT    2
-#define BOOT_DEVICE_NAND       3
-#define BOOT_DEVICE_ONENAND    4
-#define BOOT_DEVICE_MMC1       5
-#define BOOT_DEVICE_MMC2       6
-#define BOOT_DEVICE_MMC2_2     7
-#define BOOT_DEVICE_NOR                8
-#define BOOT_DEVICE_I2C                9
-#define BOOT_DEVICE_SPI                10
-
-#endif
diff --git a/arch/arm/include/asm/arch-mx5/spl.h b/arch/arm/include/asm/arch-mx5/spl.h
deleted file mode 100644 (file)
index 20c6cae..0000000
+++ /dev/null
@@ -1,13 +0,0 @@
-/*
- * Copyright (C) 2013 Marek Vasut <marex@denx.de>
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-#ifndef __ASM_ARCH_SPL_H__
-#define __ASM_ARCH_SPL_H__
-
-#define BOOT_DEVICE_NONE       0
-#define BOOT_DEVICE_NAND       1
-
-#endif /* __ASM_ARCH_SPL_H__ */
index d724f20..1f12695 100644 (file)
@@ -53,12 +53,17 @@ typedef void *hab_rvt_authenticate_image_t(uint8_t, ptrdiff_t,
                void **, size_t *, hab_loader_callback_f_t);
 typedef void hapi_clock_init_t(void);
 
-#define HAB_RVT_REPORT_EVENT (*(uint32_t *)0x000000B4)
-#define HAB_RVT_REPORT_STATUS (*(uint32_t *)0x000000B8)
-#define HAB_RVT_AUTHENTICATE_IMAGE (*(uint32_t *)0x000000A4)
-#define HAB_RVT_ENTRY (*(uint32_t *)0x00000098)
-#define HAB_RVT_EXIT (*(uint32_t *)0x0000009C)
-#define HAB_RVT_CLOCK_INIT ((hapi_clock_init_t *)0x0000024D)
+#define HAB_RVT_REPORT_EVENT                   (*(uint32_t *)0x000000B4)
+#define HAB_RVT_REPORT_STATUS                  (*(uint32_t *)0x000000B8)
+#define HAB_RVT_AUTHENTICATE_IMAGE             (*(uint32_t *)0x000000A4)
+#define HAB_RVT_ENTRY                          (*(uint32_t *)0x00000098)
+#define HAB_RVT_EXIT                           (*(uint32_t *)0x0000009C)
+
+#define HAB_RVT_REPORT_EVENT_NEW               (*(uint32_t *)0x000000B8)
+#define HAB_RVT_REPORT_STATUS_NEW              (*(uint32_t *)0x000000BC)
+#define HAB_RVT_AUTHENTICATE_IMAGE_NEW         (*(uint32_t *)0x000000A8)
+#define HAB_RVT_ENTRY_NEW                      (*(uint32_t *)0x0000009C)
+#define HAB_RVT_EXIT_NEW                       (*(uint32_t *)0x000000A0)
 
 #define HAB_CID_ROM 0 /**< ROM Caller ID */
 #define HAB_CID_UBOOT 1 /**< UBOOT Caller ID*/
index 1f19727..a69a753 100644 (file)
 #define IP2APB_USBPHY2_BASE_ADDR    (AIPS2_OFF_BASE_ADDR + 0x7C000)
 
 #define CHIP_REV_1_0                 0x10
+#define CHIP_REV_1_2                 0x12
+#define CHIP_REV_1_5                 0x15
 #define IRAM_SIZE                    0x00040000
 #define FEC_QUIRK_ENET_MAC
 
index f9ee0d9..6a4a632 100644 (file)
@@ -39,7 +39,7 @@
 #define IOMUXC_GPR12_LOS_LEVEL_MASK            (0x1f << 4)
 #define IOMUXC_GPR12_APPS_LTSSM_ENABLE         (1 << 10)
 #define IOMUXC_GPR12_DEVICE_TYPE_EP            (0x0 << 12)
-#define IOMUXC_GPR12_DEVICE_TYPE_RC            (0x2 << 12)
+#define IOMUXC_GPR12_DEVICE_TYPE_RC            (0x4 << 12)
 #define IOMUXC_GPR12_DEVICE_TYPE_MASK          (0xf << 12)
 
 /*
index 43d377a..d544d2e 100644 (file)
@@ -6,6 +6,7 @@
 #ifndef __ASM_ARCH_MX6_DDR_H__
 #define __ASM_ARCH_MX6_DDR_H__
 
+#ifndef CONFIG_SPL_BUILD
 #ifdef CONFIG_MX6Q
 #include "mx6q-ddr.h"
 #else
 #error "Please select cpu"
 #endif /* CONFIG_MX6DL or CONFIG_MX6S */
 #endif /* CONFIG_MX6Q */
+#else
+
+/* MMDC P0/P1 Registers */
+struct mmdc_p_regs {
+       u32 mdctl;
+       u32 mdpdc;
+       u32 mdotc;
+       u32 mdcfg0;
+       u32 mdcfg1;
+       u32 mdcfg2;
+       u32 mdmisc;
+       u32 mdscr;
+       u32 mdref;
+       u32 res1[2];
+       u32 mdrwd;
+       u32 mdor;
+       u32 res2[3];
+       u32 mdasp;
+       u32 res3[240];
+       u32 mapsr;
+       u32 res4[254];
+       u32 mpzqhwctrl;
+       u32 res5[2];
+       u32 mpwldectrl0;
+       u32 mpwldectrl1;
+       u32 res6;
+       u32 mpodtctrl;
+       u32 mprddqby0dl;
+       u32 mprddqby1dl;
+       u32 mprddqby2dl;
+       u32 mprddqby3dl;
+       u32 res7[4];
+       u32 mpdgctrl0;
+       u32 mpdgctrl1;
+       u32 res8;
+       u32 mprddlctl;
+       u32 res9;
+       u32 mpwrdlctl;
+       u32 res10[25];
+       u32 mpmur0;
+};
+
+/*
+ * MMDC iomux registers (pinctl/padctl) - (different for IMX6DQ vs IMX6SDL)
+ */
+#define MX6DQ_IOM_DDR_BASE      0x020e0500
+struct mx6dq_iomux_ddr_regs {
+       u32 res1[3];
+       u32 dram_sdqs5;
+       u32 dram_dqm5;
+       u32 dram_dqm4;
+       u32 dram_sdqs4;
+       u32 dram_sdqs3;
+       u32 dram_dqm3;
+       u32 dram_sdqs2;
+       u32 dram_dqm2;
+       u32 res2[16];
+       u32 dram_cas;
+       u32 res3[2];
+       u32 dram_ras;
+       u32 dram_reset;
+       u32 res4[2];
+       u32 dram_sdclk_0;
+       u32 dram_sdba2;
+       u32 dram_sdcke0;
+       u32 dram_sdclk_1;
+       u32 dram_sdcke1;
+       u32 dram_sdodt0;
+       u32 dram_sdodt1;
+       u32 res5;
+       u32 dram_sdqs0;
+       u32 dram_dqm0;
+       u32 dram_sdqs1;
+       u32 dram_dqm1;
+       u32 dram_sdqs6;
+       u32 dram_dqm6;
+       u32 dram_sdqs7;
+       u32 dram_dqm7;
+};
+
+#define MX6DQ_IOM_GRP_BASE      0x020e0700
+struct mx6dq_iomux_grp_regs {
+       u32 res1[18];
+       u32 grp_b7ds;
+       u32 grp_addds;
+       u32 grp_ddrmode_ctl;
+       u32 res2;
+       u32 grp_ddrpke;
+       u32 res3[6];
+       u32 grp_ddrmode;
+       u32 res4[3];
+       u32 grp_b0ds;
+       u32 grp_b1ds;
+       u32 grp_ctlds;
+       u32 res5;
+       u32 grp_b2ds;
+       u32 grp_ddr_type;
+       u32 grp_b3ds;
+       u32 grp_b4ds;
+       u32 grp_b5ds;
+       u32 grp_b6ds;
+};
+
+#define MX6SDL_IOM_DDR_BASE     0x020e0400
+struct mx6sdl_iomux_ddr_regs {
+       u32 res1[25];
+       u32 dram_cas;
+       u32 res2[2];
+       u32 dram_dqm0;
+       u32 dram_dqm1;
+       u32 dram_dqm2;
+       u32 dram_dqm3;
+       u32 dram_dqm4;
+       u32 dram_dqm5;
+       u32 dram_dqm6;
+       u32 dram_dqm7;
+       u32 dram_ras;
+       u32 dram_reset;
+       u32 res3[2];
+       u32 dram_sdba2;
+       u32 dram_sdcke0;
+       u32 dram_sdcke1;
+       u32 dram_sdclk_0;
+       u32 dram_sdclk_1;
+       u32 dram_sdodt0;
+       u32 dram_sdodt1;
+       u32 dram_sdqs0;
+       u32 dram_sdqs1;
+       u32 dram_sdqs2;
+       u32 dram_sdqs3;
+       u32 dram_sdqs4;
+       u32 dram_sdqs5;
+       u32 dram_sdqs6;
+       u32 dram_sdqs7;
+};
+
+#define MX6SDL_IOM_GRP_BASE     0x020e0700
+struct mx6sdl_iomux_grp_regs {
+       u32 res1[18];
+       u32 grp_b7ds;
+       u32 grp_addds;
+       u32 grp_ddrmode_ctl;
+       u32 grp_ddrpke;
+       u32 res2[2];
+       u32 grp_ddrmode;
+       u32 grp_b0ds;
+       u32 res3;
+       u32 grp_ctlds;
+       u32 grp_b1ds;
+       u32 grp_ddr_type;
+       u32 grp_b2ds;
+       u32 grp_b3ds;
+       u32 grp_b4ds;
+       u32 grp_b5ds;
+       u32 res4;
+       u32 grp_b6ds;
+};
+
+/* Device Information: Varies per DDR3 part number and speed grade */
+struct mx6_ddr3_cfg {
+       u16 mem_speed;  /* ie 1600 for DDR3-1600 (800,1066,1333,1600) */
+       u8 density;     /* chip density (Gb) (1,2,4,8) */
+       u8 width;       /* bus width (bits) (4,8,16) */
+       u8 banks;       /* number of banks */
+       u8 rowaddr;     /* row address bits (11-16)*/
+       u8 coladdr;     /* col address bits (9-12) */
+       u8 pagesz;      /* page size (K) (1-2) */
+       u16 trcd;       /* tRCD=tRP=CL (ns*100) */
+       u16 trcmin;     /* tRC min (ns*100) */
+       u16 trasmin;    /* tRAS min (ns*100) */
+       u8 SRT;         /* self-refresh temperature: 0=normal, 1=extended */
+};
+
+/* System Information: Varies per board design, layout, and term choices */
+struct mx6_ddr_sysinfo {
+       u8 dsize;       /* size of bus (in dwords: 0=16bit,1=32bit,2=64bit) */
+       u8 cs_density;  /* density per chip select (Gb) */
+       u8 ncs;         /* number chip selects used (1|2) */
+       char cs1_mirror;/* enable address mirror (0|1) */
+       char bi_on;     /* Bank interleaving enable */
+       u8 rtt_nom;     /* Rtt_Nom (DDR3_RTT_*) */
+       u8 rtt_wr;      /* Rtt_Wr (DDR3_RTT_*) */
+       u8 ralat;       /* Read Additional Latency (0-7) */
+       u8 walat;       /* Write Additional Latency (0-3) */
+       u8 mif3_mode;   /* Command prediction working mode */
+       u8 rst_to_cke;  /* Time from SDE enable to CKE rise */
+       u8 sde_to_rst;  /* Time from SDE enable until DDR reset# is high */
+};
+
+/*
+ * Board specific calibration:
+ *   This includes write leveling calibration values as well as DQS gating
+ *   and read/write delays. These values are board/layout/device specific.
+ *   Freescale recommends using the i.MX6 DDR Stress Test Tool V1.0.2
+ *   (DOC-96412) to determine these values over a range of boards and
+ *   temperatures.
+ */
+struct mx6_mmdc_calibration {
+       /* write leveling calibration */
+       u32 p0_mpwldectrl0;
+       u32 p0_mpwldectrl1;
+       u32 p1_mpwldectrl0;
+       u32 p1_mpwldectrl1;
+       /* read DQS gating */
+       u32 p0_mpdgctrl0;
+       u32 p0_mpdgctrl1;
+       u32 p1_mpdgctrl0;
+       u32 p1_mpdgctrl1;
+       /* read delay */
+       u32 p0_mprddlctl;
+       u32 p1_mprddlctl;
+       /* write delay */
+       u32 p0_mpwrdlctl;
+       u32 p1_mpwrdlctl;
+};
+
+/* configure iomux (pinctl/padctl) */
+void mx6dq_dram_iocfg(unsigned width,
+                     const struct mx6dq_iomux_ddr_regs *,
+                     const struct mx6dq_iomux_grp_regs *);
+void mx6sdl_dram_iocfg(unsigned width,
+                      const struct mx6sdl_iomux_ddr_regs *,
+                      const struct mx6sdl_iomux_grp_regs *);
+
+/* configure mx6 mmdc registers */
+void mx6_dram_cfg(const struct mx6_ddr_sysinfo *,
+                 const struct mx6_mmdc_calibration *,
+                 const struct mx6_ddr3_cfg *);
+
+#endif /* CONFIG_SPL_BUILD */
 
 #define MX6_MMDC_P0_MDCTL      0x021b0000
 #define MX6_MMDC_P0_MDPDC      0x021b0004
index 38851a1..42d30f5 100644 (file)
@@ -11,7 +11,9 @@
 #include <asm/imx-common/regs-common.h>
 #include "../arch-imx/cpu.h"
 
-#define is_soc_rev(rev)        ((get_cpu_rev() & 0xFF) - rev)
+#define soc_rev() (get_cpu_rev() & 0xFF)
+#define is_soc_rev(rev)        (soc_rev() - rev)
+
 u32 get_cpu_rev(void);
 
 /* returns MXC_CPU_ value */
diff --git a/arch/arm/include/asm/arch-tegra114/spl.h b/arch/arm/include/asm/arch-tegra114/spl.h
deleted file mode 100644 (file)
index ebb16fe..0000000
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * Copyright (c) 2010-2013, NVIDIA CORPORATION.  All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- */
-
-#ifndef        _ASM_ARCH_SPL_H_
-#define        _ASM_ARCH_SPL_H_
-
-#define BOOT_DEVICE_RAM         1
-
-#endif
diff --git a/arch/arm/include/asm/arch-tegra124/spl.h b/arch/arm/include/asm/arch-tegra124/spl.h
deleted file mode 100644 (file)
index e266395..0000000
+++ /dev/null
@@ -1,13 +0,0 @@
-/*
- * (C) Copyright 2010-2013
- * NVIDIA Corporation <www.nvidia.com>
- *
- * SPDX-License-Identifier:     GPL-2.0+
- */
-
-#ifndef _ASM_ARCH_SPL_H_
-#define _ASM_ARCH_SPL_H_
-
-#define BOOT_DEVICE_RAM 1
-
-#endif /* _ASM_ARCH_SPL_H_ */
diff --git a/arch/arm/include/asm/arch-tegra20/spl.h b/arch/arm/include/asm/arch-tegra20/spl.h
deleted file mode 100644 (file)
index 8953b00..0000000
+++ /dev/null
@@ -1,12 +0,0 @@
-/*
- * (C) Copyright 2012
- * NVIDIA Corporation <www.nvidia.com>
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-#ifndef        _ASM_ARCH_SPL_H_
-#define        _ASM_ARCH_SPL_H_
-
-#define BOOT_DEVICE_RAM         1
-
-#endif
diff --git a/arch/arm/include/asm/arch-tegra30/spl.h b/arch/arm/include/asm/arch-tegra30/spl.h
deleted file mode 100644 (file)
index 8953b00..0000000
+++ /dev/null
@@ -1,12 +0,0 @@
-/*
- * (C) Copyright 2012
- * NVIDIA Corporation <www.nvidia.com>
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-#ifndef        _ASM_ARCH_SPL_H_
-#define        _ASM_ARCH_SPL_H_
-
-#define BOOT_DEVICE_RAM         1
-
-#endif
index 1b22eeb..34c07fe 100644 (file)
@@ -25,7 +25,7 @@ typedef struct { volatile int counter; } atomic_t;
 #define ATOMIC_INIT(i) { (i) }
 
 #ifdef __KERNEL__
-#include <asm/proc/system.h>
+#include <asm/proc-armv/system.h>
 
 #define atomic_read(v) ((v)->counter)
 #define atomic_set(v,i)        (((v)->counter) = (i))
index 879e20e..597dafb 100644 (file)
@@ -17,7 +17,7 @@
 
 #ifdef __KERNEL__
 
-#include <asm/proc/system.h>
+#include <asm/proc-armv/system.h>
 
 #define smp_mb__before_clear_bit()     do { } while (0)
 #define smp_mb__after_clear_bit()      do { } while (0)
index ff45618..e91d4ac 100644 (file)
@@ -177,4 +177,29 @@ void imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad);
 void imx_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t const *pad_list,
                                     unsigned count);
 
+/* macros for declaring and using pinmux array */
+#if defined(CONFIG_MX6QDL)
+#define IOMUX_PADS(x) (MX6Q_##x), (MX6DL_##x)
+#define SETUP_IOMUX_PAD(def)                                   \
+if (is_cpu_type(MXC_CPU_MX6Q)) {                               \
+       imx_iomux_v3_setup_pad(MX6Q_##def);                     \
+} else {                                                       \
+       imx_iomux_v3_setup_pad(MX6DL_##def);                    \
+}
+#define SETUP_IOMUX_PADS(x)                                    \
+       imx_iomux_v3_setup_multiple_pads(x, ARRAY_SIZE(x)/2)
+#elif defined(CONFIG_MX6Q) || defined(CONFIG_MX6D)
+#define IOMUX_PADS(x) MX6Q_##x
+#define SETUP_IOMUX_PAD(def)                                   \
+       imx_iomux_v3_setup_pad(MX6Q_##def);
+#define SETUP_IOMUX_PADS(x)                                    \
+       imx_iomux_v3_setup_multiple_pads(x, ARRAY_SIZE(x))
+#else
+#define IOMUX_PADS(x) MX6DL_##x
+#define SETUP_IOMUX_PAD(def)                                   \
+       imx_iomux_v3_setup_pad(MX6DL_##def);
+#define SETUP_IOMUX_PADS(x)                                    \
+       imx_iomux_v3_setup_multiple_pads(x, ARRAY_SIZE(x))
+#endif
+
 #endif /* __MACH_IOMUX_V3_H__*/
index 6a1f05a..9f35fd6 100644 (file)
@@ -437,4 +437,7 @@ out:
 
 #endif /* __mem_isa */
 #endif /* __KERNEL__ */
+
+#include <iotrace.h>
+
 #endif /* __ASM_ARM_IO_H */
index 5bfab7f..532f207 100644 (file)
@@ -18,7 +18,7 @@
 #ifndef __ASM_PROC_PROCESSOR_H
 #define __ASM_PROC_PROCESSOR_H
 
-#include <asm/proc/domain.h>
+#include <asm/proc-armv/domain.h>
 
 #define KERNEL_STACK_SIZE      PAGE_SIZE
 
index 445d449..83481c6 100644 (file)
@@ -45,7 +45,7 @@ typedef unsigned long mm_segment_t;           /* domain register      */
 #if 0  /* XXX###XXX */
 #include <asm/arch/memory.h>
 #endif /* XXX###XXX */
-#include <asm/proc/processor.h>
+#include <asm/proc-armv/processor.h>
 #include <asm/types.h>
 
 union debug_insn {
index 73c9087..a836f6c 100644 (file)
@@ -11,7 +11,7 @@
 /* options set using PTRACE_SETOPTIONS */
 #define PTRACE_O_TRACESYSGOOD  0x00000001
 
-#include <asm/proc/ptrace.h>
+#include <asm/proc-armv/ptrace.h>
 
 #ifndef __ASSEMBLY__
 #define pc_pointer(v) \
index 90e5a9d..18a319d 100644 (file)
@@ -7,9 +7,29 @@
 #ifndef        _ASM_SPL_H_
 #define        _ASM_SPL_H_
 
+#if defined(CONFIG_OMAP) || defined(CONFIG_SOCFPGA) || defined(CONFIG_ZYNQ) \
+       || defined(CONFIG_EXYNOS4) || defined(CONFIG_EXYNOS5) \
+       || defined(CONFIG_EXYNOS4210)
 /* Platform-specific defines */
 #include <asm/arch/spl.h>
 
+#else
+enum {
+       BOOT_DEVICE_RAM,
+       BOOT_DEVICE_MMC1,
+       BOOT_DEVICE_MMC2,
+       BOOT_DEVICE_MMC2_2,
+       BOOT_DEVICE_NAND,
+       BOOT_DEVICE_ONENAND,
+       BOOT_DEVICE_NOR,
+       BOOT_DEVICE_UART,
+       BOOT_DEVICE_SPI,
+       BOOT_DEVICE_SATA,
+       BOOT_DEVICE_I2C,
+       BOOT_DEVICE_NONE
+};
+#endif
+
 /* Linker symbols. */
 extern char __bss_start[], __bss_end[];
 
index 9b473b5..76adaf3 100644 (file)
@@ -277,7 +277,7 @@ void board_init_f(ulong bootflag)
        gd->mon_len = (ulong)&__bss_end - (ulong)_start;
 #ifdef CONFIG_OF_EMBED
        /* Get a pointer to the FDT */
-       gd->fdt_blob = __dtb_db_begin;
+       gd->fdt_blob = __dtb_dt_begin;
 #elif defined CONFIG_OF_SEPARATE
        /* FDT is at end of image */
        gd->fdt_blob = &_end;
index ab0374e..b3ffc33 100644 (file)
@@ -24,31 +24,31 @@ void dcache_clean_range(volatile void *start, size_t size)
        sync_write_buffer();
 }
 
-void dcache_invalidate_range(volatile void *start, size_t size)
+void invalidate_dcache_range(unsigned long start, unsigned long stop)
 {
-       unsigned long v, begin, end, linesz;
+       unsigned long v, linesz;
 
        linesz = CONFIG_SYS_DCACHE_LINESZ;
 
        /* You asked for it, you got it */
-       begin = (unsigned long)start & ~(linesz - 1);
-       end = ((unsigned long)start + size + linesz - 1) & ~(linesz - 1);
+       start = start & ~(linesz - 1);
+       stop = (stop + linesz - 1) & ~(linesz - 1);
 
-       for (v = begin; v < end; v += linesz)
+       for (v = start; v < stop; v += linesz)
                dcache_invalidate_line((void *)v);
 }
 
-void dcache_flush_range(volatile void *start, size_t size)
+void flush_dcache_range(unsigned long start, unsigned long stop)
 {
-       unsigned long v, begin, end, linesz;
+       unsigned long v, linesz;
 
        linesz = CONFIG_SYS_DCACHE_LINESZ;
 
        /* You asked for it, you got it */
-       begin = (unsigned long)start & ~(linesz - 1);
-       end = ((unsigned long)start + size + linesz - 1) & ~(linesz - 1);
+       start = start & ~(linesz - 1);
+       stop = (stop + linesz - 1) & ~(linesz - 1);
 
-       for (v = begin; v < end; v += linesz)
+       for (v = start; v < stop; v += linesz)
                dcache_flush_line((void *)v);
 
        sync_write_buffer();
index 13d6d3a..e08cd9d 100644 (file)
@@ -49,9 +49,7 @@ static inline void icache_invalidate_line(volatile void *vaddr)
  * Applies the above functions on all lines that are touched by the
  * specified virtual address range.
  */
-void dcache_invalidate_range(volatile void *start, size_t len);
 void dcache_clean_range(volatile void *start, size_t len);
-void dcache_flush_range(volatile void *start, size_t len);
 void icache_invalidate_range(volatile void *start, size_t len);
 
 static inline void dcache_flush_unlocked(void)
index 95ea81f..dbdd2fe 100644 (file)
@@ -23,13 +23,15 @@ static inline unsigned long dma_map_single(volatile void *vaddr, size_t len,
 
        switch (dir) {
        case DMA_BIDIRECTIONAL:
-               dcache_flush_range(vaddr, len);
+               flush_dcache_range((unsigned long)vaddr,
+                                  (unsigned long)vaddr + len);
                break;
        case DMA_TO_DEVICE:
                dcache_clean_range(vaddr, len);
                break;
        case DMA_FROM_DEVICE:
-               dcache_invalidate_range(vaddr, len);
+               invalidate_dcache_range((unsigned long)vaddr,
+                                       (unsigned long)vaddr + len);
                break;
        default:
                /* This will cause a linker error */
index 7680102..bf0997f 100644 (file)
@@ -65,8 +65,8 @@ static void dma_alloc_init(void)
        printf("DMA: Using memory from 0x%08lx to 0x%08lx\n",
               dma_alloc_start, dma_alloc_end);
 
-       dcache_invalidate_range(cached(dma_alloc_start),
-                               dma_alloc_end - dma_alloc_start);
+       invalidate_dcache_range((unsigned long)cached(dma_alloc_start),
+                               dma_alloc_end);
 }
 
 void *dma_alloc_coherent(size_t len, unsigned long *handle)
index db7ded4..8d01f5f 100644 (file)
@@ -208,10 +208,10 @@ void cpu_init_f(void)
        scm2_t *scm2 = (scm2_t *) MMAP_SCM2;
        gpio_t *gpio = (gpio_t *) MMAP_GPIO;
        fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
+#ifndef CONFIG_WATCHDOG
        wdog_t *wdog = (wdog_t *) MMAP_WDOG;
 
        /* watchdog is enabled by default - disable the watchdog */
-#ifndef CONFIG_WATCHDOG
        out_be16(&wdog->cr, 0);
 #endif
 
index 9c324dc..b4a8eef 100644 (file)
@@ -364,9 +364,9 @@ void uart_port_conf(int port)
 int fecpin_setclear(struct eth_device *dev, int setclear)
 {
        gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+#ifdef CONFIG_MCF5445x
        struct fec_info_s *info = (struct fec_info_s *)dev->priv;
 
-#ifdef CONFIG_MCF5445x
        if (setclear) {
 #ifdef CONFIG_SYS_FEC_NO_SHARED_PHY
                if (info->iobase == CONFIG_SYS_FEC0_IOBASE)
index 5a87a9b..2d2a519 100644 (file)
 #define writew(b,addr)         ((*(volatile u16 *) (addr)) = (b))
 #define writel(b,addr)         ((*(volatile u32 *) (addr)) = (b))
 #else
-#define readw(addr)            in_le16((volatile u16 *)(addr))
-#define readl(addr)            in_le32((volatile u32 *)(addr))
-#define writew(b,addr)         out_le16((volatile u16 *)(addr),(b))
-#define writel(b,addr)         out_le32((volatile u32 *)(addr),(b))
+#define readw(addr)            in_be16((volatile u16 *)(addr))
+#define readl(addr)            in_be32((volatile u32 *)(addr))
+#define writew(b,addr)         out_be16((volatile u16 *)(addr),(b))
+#define writel(b,addr)         out_be32((volatile u32 *)(addr),(b))
 #endif
 
 /*
index 4fbc040..b97d267 100644 (file)
@@ -15,7 +15,7 @@ typedef long          __kernel_off_t;
 typedef int            __kernel_pid_t;
 typedef unsigned int   __kernel_uid_t;
 typedef unsigned int   __kernel_gid_t;
-typedef unsigned int   __kernel_size_t;
+typedef unsigned long  __kernel_size_t;
 typedef int            __kernel_ssize_t;
 typedef long           __kernel_ptrdiff_t;
 typedef long           __kernel_time_t;
index 318ca01..9caff73 100644 (file)
@@ -31,9 +31,6 @@
 #endif
 #include <net.h>
 #include <serial.h>
-#if defined(CONFIG_CMD_BEDBUG)
-#include <cmd_bedbug.h>
-#endif
 #ifdef CONFIG_SYS_ALLOC_DPRAM
 #include <commproc.h>
 #endif
@@ -602,11 +599,6 @@ void board_init_r (gd_t *id, ulong dest_addr)
        last_stage_init ();
 #endif
 
-#if defined(CONFIG_CMD_BEDBUG)
-       WATCHDOG_RESET ();
-       bedbug_init ();
-#endif
-
 #if defined(CONFIG_PRAM) || defined(CONFIG_LOGBUFFER)
        /*
         * Export available size of memory for Linux,
@@ -628,13 +620,6 @@ void board_init_r (gd_t *id, ulong dest_addr)
        }
 #endif
 
-#ifdef CONFIG_MODEM_SUPPORT
- {
-        extern int do_mdm_init;
-        do_mdm_init = gd->do_mdm_init;
- }
-#endif
-
 #ifdef CONFIG_WATCHDOG
        /* disable watchdog if environment is set */
        if ((s = getenv ("watchdog")) != NULL) {
index 804e01d..fa9c493 100644 (file)
@@ -50,11 +50,7 @@ void arch_lmb_reserve(struct lmb *lmb)
 
 int do_bootm_linux(int flag, int argc, char * const argv[], bootm_headers_t *images)
 {
-       ulong rd_len;
-       ulong initrd_start, initrd_end;
        int ret;
-
-       ulong cmd_start, cmd_end;
        bd_t  *kbd;
        void  (*kernel) (bd_t *, ulong, ulong, ulong, ulong);
        struct lmb *lmb = &images->lmb;
@@ -96,7 +92,8 @@ int do_bootm_linux(int flag, int argc, char * const argv[], bootm_headers_t *ima
         *   sp+16: Start of command line string
         *   sp+20: End   of command line string
         */
-       (*kernel) (kbd, initrd_start, initrd_end, cmd_start, cmd_end);
+       (*kernel)(kbd, images->initrd_start, images->initrd_end,
+                 images->cmdline_start, images->cmdline_end);
        /* does not return */
 error:
        return 1;
diff --git a/arch/microblaze/dts/include/dt-bindings b/arch/microblaze/dts/include/dt-bindings
new file mode 120000 (symlink)
index 0000000..0cecb3d
--- /dev/null
@@ -0,0 +1 @@
+../../../../include/dt-bindings
\ No newline at end of file
index d60b307..6977dd6 100644 (file)
@@ -58,7 +58,7 @@ int do_bootm_linux(int flag, int argc, char * const argv[],
        /* fixup the initrd now that we know where it should be */
        if (images->rd_start && images->rd_end && of_flat_tree)
                ret = fdt_initrd(of_flat_tree, images->rd_start,
-                                images->rd_end, 1);
+                                images->rd_end);
                if (ret)
                        return 1;
 
index c54b0cf..1ae3b75 100644 (file)
@@ -1,6 +1,7 @@
 /*
  * (C) Copyright 2011, Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
  * (C) Copyright 2011, Julius Baxter <julius@opencores.org>
+ * (C) Copyright 2014, Franck Jullien <franck.jullien@gmail.com>
  *
  * SPDX-License-Identifier:    GPL-2.0+
  */
@@ -40,9 +41,48 @@ __reset:
        l.ori   r3,r0,SPR_SR_SM
        l.mtspr r0,r3,SPR_SR
 
+       l.jal   _cur
+       l.nop
+_cur:
+       l.ori   r8, r9, 0               /* Get _cur current address */
+
+       l.movhi r3, hi(_cur)
+       l.ori   r3, r3, lo(_cur)
+       l.sfeq  r8, r3                  /* If we are running at the linked address */
+       l.bf    _no_vector_reloc        /* there is not need for relocation */
+        l.sub  r8, r8, r3
+
+       l.mfspr r4, r0, SPR_CPUCFGR
+       l.andi  r4, r4, SPR_CPUCFGR_EVBARP      /* Exception Vector Base Address Register present ? */
+       l.sfnei r4,0
+       l.bnf   _reloc_vectors
+       l.movhi r5, 0                   /* Destination */
+
+       l.mfspr r4, r0, SPR_EVBAR
+       l.add   r5, r5, r4
+
+_reloc_vectors:
+       /* Relocate vectors*/
+       l.movhi r5, 0                   /* Destination */
+       l.movhi r6, hi(__start)         /* Length */
+       l.ori   r6, r6, lo(__start)
+       l.ori   r3, r8, 0
+
+.L_relocvectors:
+       l.lwz   r7, 0(r3)
+       l.sw    0(r5), r7
+       l.addi  r5, r5, 4
+       l.sfeq  r5, r6
+       l.bnf   .L_relocvectors
+        l.addi r3, r3, 4
+
+_no_vector_reloc:
+
        /* Relocate u-boot */
-       l.movhi r3,hi(__start)          /* source start address */
+       l.movhi r3,hi(__start)          /* source start offset */
        l.ori   r3,r3,lo(__start)
+       l.add   r3,r8,r3
+
        l.movhi r4,hi(_stext)           /* dest start address */
        l.ori   r4,r4,lo(_stext)
        l.movhi r5,hi(__end)            /* dest end address */
@@ -56,19 +96,6 @@ __reset:
        l.bf    .L_reloc
         l.addi r4,r4,4                 /* delay slot */
 
-#ifdef CONFIG_SYS_RELOCATE_VECTORS
-       /* Relocate vectors from 0xf0000000 to 0x00000000 */
-       l.movhi r4, 0xf000 /* source */
-       l.movhi r5, 0      /* destination */
-       l.addi  r6, r5, CONFIG_SYS_VECTORS_LEN /* length */
-.L_relocvectors:
-       l.lwz   r7, 0(r4)
-       l.sw    0(r5), r7
-       l.addi  r5, r5, 4
-       l.sfeq  r5,r6
-       l.bnf   .L_relocvectors
-        l.addi r4,r4, 4
-#endif
        l.movhi r4,hi(_start)
        l.ori   r4,r4,lo(_start)
        l.jr    r4
index a863b3e..e30d210 100644 (file)
 #define SPR_ICCFGR     (SPRGROUP_SYS + 6)
 #define SPR_DCFGR      (SPRGROUP_SYS + 7)
 #define SPR_PCCFGR     (SPRGROUP_SYS + 8)
+#define SPR_VR2                (SPRGROUP_SYS + 9)
+#define SPR_AVR                (SPRGROUP_SYS + 10)
+#define SPR_EVBAR      (SPRGROUP_SYS + 11)
+#define SPR_AECR       (SPRGROUP_SYS + 12)
+#define SPR_AESR       (SPRGROUP_SYS + 13)
 #define SPR_NPC                (SPRGROUP_SYS + 16)
 #define SPR_SR         (SPRGROUP_SYS + 17)
 #define SPR_PPC                (SPRGROUP_SYS + 18)
 #define SPR_CPUCFGR_OF32S      0x00000080 /* ORFPX32 supported */
 #define SPR_CPUCFGR_OF64S      0x00000100 /* ORFPX64 supported */
 #define SPR_CPUCFGR_OV64S      0x00000200 /* ORVDX64 supported */
-#define SPR_CPUCFGR_RES                0xfffffc00 /* Reserved */
+#define SPR_CPUCFGR_ND         0x00000400 /* No delay slot */
+#define SPR_CPUCFGR_AVRP       0x00000800 /* Arch. Version Register present */
+#define SPR_CPUCFGR_EVBARP     0x00001000 /* Exception Vector Base Address Register (EVBAR) present */
+#define SPR_CPUCFGR_ISRP       0x00002000 /* Implementation-Specific Registers (ISR0-7) present */
+#define SPR_CPUCFGR_AECSRP     0x00004000 /* Arithmetic Exception Control Register (AECR) and */
+                                          /* Arithmetic Exception Status Register (AESR) presents */
+#define SPR_CPUCFGR_RES                0xffffc000 /* Reserved */
 
 /*
  * Bit definitions for the Debug configuration register and other
index 2c013bb..0a47fdc 100644 (file)
@@ -242,8 +242,6 @@ void pci_mpc8250_init (struct pci_controller *hose)
        immap->im_siu_conf.sc_siumcr =
                (immap->im_siu_conf.sc_siumcr & ~SIUMCR_LBPC11)
                | SIUMCR_LBPC01;
-#elif defined(CONFIG_ADSTYPE) && CONFIG_ADSTYPE == CONFIG_SYS_PQ2FADS
-/* nothing to do for this board here */
 #elif defined CONFIG_MPC8272
        immap->im_siu_conf.sc_siumcr = (immap->im_siu_conf.sc_siumcr &
                                  ~SIUMCR_BBD &
index 324f132..d7eaf13 100644 (file)
@@ -137,19 +137,6 @@ _hrcw_table:
 
        .globl  _start
 _start:
-#if defined(CONFIG_MPC8260ADS) && defined(CONFIG_SYS_DEFAULT_IMMR)
-       lis     r3, CONFIG_SYS_DEFAULT_IMMR@h
-       nop
-       lwz     r4, 0(r3)
-       nop
-       rlwinm  r4, r4, 0, 8, 5
-       nop
-       oris    r4, r4, 0x0200
-       nop
-       stw     r4, 0(r3)
-       nop
-#endif /* CONFIG_MPC8260ADS && CONFIG_SYS_DEFAULT_IMMR */
-
        mfmsr   r5                      /* save msr contents            */
 
 #if defined(CONFIG_COGENT)
index 3d37a76..3a04a89 100644 (file)
@@ -231,6 +231,9 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
        if ((SVR_MAJ(svr) == 1) || IS_SVR_REV(svr, 2, 0))
                puts("Work-around for Erratum NMG ETSEC129 enabled\n");
 #endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_A004508
+       puts("Work-around for Erratum A004508 enabled\n");
+#endif
 #ifdef CONFIG_SYS_FSL_ERRATUM_A004510
        puts("Work-around for Erratum A004510 enabled\n");
 #endif
@@ -266,6 +269,9 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 #ifdef CONFIG_SYS_FSL_ERRATUM_USB14
        puts("Work-around for Erratum USB14 enabled\n");
 #endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_A007186
+       puts("Work-around for Erratum A007186 enabled\n");
+#endif
 #ifdef CONFIG_SYS_FSL_ERRATUM_A006593
        puts("Work-around for Erratum A006593 enabled\n");
 #endif
index d6cf885..78316a6 100644 (file)
@@ -225,6 +225,32 @@ static void disable_cpc_sram(void)
 }
 #endif
 
+#if defined(T1040_TDM_QUIRK_CCSR_BASE)
+#ifdef CONFIG_POST
+#error POST memory test cannot be enabled with TDM
+#endif
+static void enable_tdm_law(void)
+{
+       int ret;
+       char buffer[HWCONFIG_BUFFER_SIZE] = {0};
+       int tdm_hwconfig_enabled = 0;
+
+       /*
+        * Extract hwconfig from environment since environment
+        * is not setup properly yet. Search for tdm entry in
+        * hwconfig.
+        */
+       ret = getenv_f("hwconfig", buffer, sizeof(buffer));
+       if (ret > 0) {
+               tdm_hwconfig_enabled = hwconfig_f("tdm", buffer);
+               /* If tdm is defined in hwconfig, set law for tdm workaround */
+               if (tdm_hwconfig_enabled)
+                       set_next_law(T1040_TDM_QUIRK_CCSR_BASE, LAW_SIZE_16M,
+                                    LAW_TRGT_IF_CCSR);
+       }
+}
+#endif
+
 static void enable_cpc(void)
 {
        int i;
@@ -729,6 +755,9 @@ skip_l2:
        disable_cpc_sram();
 #endif
        enable_cpc();
+#if defined(T1040_TDM_QUIRK_CCSR_BASE)
+       enable_tdm_law();
+#endif
 
 #ifndef CONFIG_SYS_FSL_NO_SERDES
        /* needs to be in ram since code uses global static vars */
index ed80a84..85dfa5b 100644 (file)
@@ -14,6 +14,7 @@
 #include <linux/ctype.h>
 #include <asm/io.h>
 #include <asm/fsl_portals.h>
+#include <hwconfig.h>
 #ifdef CONFIG_FSL_ESDHC
 #include <fsl_esdhc.h>
 #endif
@@ -35,6 +36,11 @@ void ft_fixup_cpu(void *blob, u64 memory_limit)
        u32 bootpg = determine_mp_bootpg(NULL);
        u32 id = get_my_id();
        const char *enable_method;
+#if defined(T1040_TDM_QUIRK_CCSR_BASE)
+       int ret;
+       int tdm_hwconfig_enabled = 0;
+       char buffer[HWCONFIG_BUFFER_SIZE] = {0};
+#endif
 
        off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
        while (off != -FDT_ERR_NOTFOUND) {
@@ -77,6 +83,26 @@ void ft_fixup_cpu(void *blob, u64 memory_limit)
                                "device_type", "cpu", 4);
        }
 
+#if defined(T1040_TDM_QUIRK_CCSR_BASE)
+#define        CONFIG_MEM_HOLE_16M     0x1000000
+       /*
+        * Extract hwconfig from environment.
+        * Search for tdm entry in hwconfig.
+        */
+       ret = getenv_f("hwconfig", buffer, sizeof(buffer));
+       if (ret > 0)
+               tdm_hwconfig_enabled = hwconfig_f("tdm", buffer);
+
+       /* Reserve the memory hole created by TDM LAW, so OSes dont use it */
+       if (tdm_hwconfig_enabled) {
+               off = fdt_add_mem_rsv(blob, T1040_TDM_QUIRK_CCSR_BASE,
+                                     CONFIG_MEM_HOLE_16M);
+               if (off < 0)
+                       printf("Failed  to reserve memory for tdm: %s\n",
+                              fdt_strerror(off));
+       }
+#endif
+
        /* Reserve the boot page so OSes dont use it */
        if ((u64)bootpg < memory_limit) {
                off = fdt_add_mem_rsv(blob, bootpg, (u64)4096);
index 70e09ea..d1fc76a 100644 (file)
@@ -147,12 +147,43 @@ int serdes_get_first_lane(u32 sd, enum srds_prtcl device)
        return -ENODEV;
 }
 
+#define BC3_SHIFT      9
+#define DC3_SHIFT      6
+#define FC3_SHIFT      0
+#define BC2_SHIFT      19
+#define DC2_SHIFT      16
+#define FC2_SHIFT      10
+#define BC1_SHIFT      29
+#define DC1_SHIFT      26
+#define FC1_SHIFT      20
+#define BC_MASK                0x1
+#define DC_MASK                0x7
+#define FC_MASK                0x3F
+
+#define FUSE_VAL_MASK          0x00000003
+#define FUSE_VAL_SHIFT         30
+#define CR0_DCBIAS_SHIFT       5
+#define CR1_FCAP_SHIFT         15
+#define CR1_BCAP_SHIFT         29
+#define FCAP_MASK              0x001F8000
+#define BCAP_MASK              0x20000000
+#define BCAP_OVD_MASK          0x10000000
+#define BYP_CAL_MASK           0x02000000
+
 u64 serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift)
 {
        ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
        u64 serdes_prtcl_map = 0;
        u32 cfg;
        int lane;
+#ifdef CONFIG_SYS_FSL_ERRATUM_A007186
+       struct ccsr_sfp_regs  __iomem *sfp_regs =
+                       (struct ccsr_sfp_regs __iomem *)(CONFIG_SYS_SFP_ADDR);
+       u32 pll_num, pll_status, bc, dc, fc, pll_cr_upd, pll_cr0, pll_cr1;
+       u32 bc_status, fc_status, dc_status, pll_sr2;
+       serdes_corenet_t  __iomem *srds_regs = (void *)sd_addr;
+       u32 sfp_spfr0, sel;
+#endif
 
        cfg = in_be32(&gur->rcwsr[4]) & sd_prctl_mask;
        /* Is serdes enabled at all? */
@@ -161,6 +192,123 @@ u64 serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift)
                return 0;
        }
 
+/* Erratum A-007186
+ * Freescale Scratch Pad Fuse Register n (SFP_FSPFR0)
+ * The workaround requires factory pre-set SerDes calibration values to be
+ * read from a fuse block(Freescale Scratch Pad Fuse Register SFP_FSPFR0)
+ * These values have been shown to work across the
+ * entire temperature range for all SerDes. These values are then written into
+ * the SerDes registers to calibrate the SerDes PLL.
+ *
+ * This workaround for the protocols and rates that only have the Ring VCO.
+ */
+#ifdef CONFIG_SYS_FSL_ERRATUM_A007186
+       sfp_spfr0 = in_be32(&sfp_regs->fsl_spfr0);
+       debug("A007186: sfp_spfr0= %x\n", sfp_spfr0);
+
+       sel = (sfp_spfr0 >> FUSE_VAL_SHIFT) & FUSE_VAL_MASK;
+
+       if (sel == 0x01 || sel == 0x02) {
+               for (pll_num = 0; pll_num < SRDS_MAX_BANK; pll_num++) {
+                       pll_status = in_be32(&srds_regs->bank[pll_num].pllcr0);
+                       debug("A007186: pll_num=%x pllcr0=%x\n",
+                             pll_num, pll_status);
+                       /* STEP 1 */
+                       /* Read factory pre-set SerDes calibration values
+                        * from fuse block(SFP scratch register-sfp_spfr0)
+                        */
+                       switch (pll_status & SRDS_PLLCR0_FRATE_SEL_MASK) {
+                       case SRDS_PLLCR0_FRATE_SEL_3_0:
+                       case SRDS_PLLCR0_FRATE_SEL_3_072:
+                               debug("A007186: 3.0/3.072 protocol rate\n");
+                               bc = (sfp_spfr0 >> BC1_SHIFT) & BC_MASK;
+                               dc = (sfp_spfr0 >> DC1_SHIFT) & DC_MASK;
+                               fc = (sfp_spfr0 >> FC1_SHIFT) & FC_MASK;
+                               break;
+                       case SRDS_PLLCR0_FRATE_SEL_3_125:
+                               debug("A007186: 3.125 protocol rate\n");
+                               bc = (sfp_spfr0 >> BC2_SHIFT) & BC_MASK;
+                               dc = (sfp_spfr0 >> DC2_SHIFT) & DC_MASK;
+                               fc = (sfp_spfr0 >> FC2_SHIFT) & FC_MASK;
+                               break;
+                       case SRDS_PLLCR0_FRATE_SEL_3_75:
+                               debug("A007186: 3.75 protocol rate\n");
+                               bc = (sfp_spfr0 >> BC1_SHIFT) & BC_MASK;
+                               dc = (sfp_spfr0 >> DC1_SHIFT) & DC_MASK;
+                               fc = (sfp_spfr0 >> FC1_SHIFT) & FC_MASK;
+                               break;
+                       default:
+                               continue;
+                       }
+
+                       /* STEP 2 */
+                       /* Write SRDSxPLLnCR1[11:16] = FC
+                        * Write SRDSxPLLnCR1[2] = BC
+                        */
+                       pll_cr1 = in_be32(&srds_regs->bank[pll_num].pllcr1);
+                       pll_cr_upd = (((bc << CR1_BCAP_SHIFT) & BCAP_MASK) |
+                                     ((fc << CR1_FCAP_SHIFT) & FCAP_MASK));
+                       out_be32(&srds_regs->bank[pll_num].pllcr1,
+                                (pll_cr_upd | pll_cr1));
+                       debug("A007186: pll_num=%x Updated PLLCR1=%x\n",
+                             pll_num, (pll_cr_upd | pll_cr1));
+                       /* Write SRDSxPLLnCR0[24:26] = DC
+                        */
+                       pll_cr0 = in_be32(&srds_regs->bank[pll_num].pllcr0);
+                       out_be32(&srds_regs->bank[pll_num].pllcr0,
+                                pll_cr0 | (dc << CR0_DCBIAS_SHIFT));
+                       debug("A007186: pll_num=%x, Updated PLLCR0=%x\n",
+                             pll_num, (pll_cr0 | (dc << CR0_DCBIAS_SHIFT)));
+                       /* Write SRDSxPLLnCR1[3] = 1
+                        * Write SRDSxPLLnCR1[6] = 1
+                        */
+                       pll_cr1 = in_be32(&srds_regs->bank[pll_num].pllcr1);
+                       pll_cr_upd = (BCAP_OVD_MASK | BYP_CAL_MASK);
+                       out_be32(&srds_regs->bank[pll_num].pllcr1,
+                                (pll_cr_upd | pll_cr1));
+                       debug("A007186: pll_num=%x Updated PLLCR1=%x\n",
+                             pll_num, (pll_cr_upd | pll_cr1));
+
+                       /* STEP 3 */
+                       /* Read the status Registers */
+                       /* Verify SRDSxPLLnSR2[8] = BC */
+                       pll_sr2 = in_be32(&srds_regs->bank[pll_num].pllsr2);
+                       debug("A007186: pll_num=%x pllsr2=%x\n",
+                             pll_num, pll_sr2);
+                       bc_status = (pll_sr2 >> 23) & BC_MASK;
+                       if (bc_status != bc)
+                               debug("BC mismatch\n");
+                       fc_status = (pll_sr2 >> 16) & FC_MASK;
+                       if (fc_status != fc)
+                               debug("FC mismatch\n");
+                       pll_cr0 = in_be32(&srds_regs->bank[pll_num].pllcr0);
+                       out_be32(&srds_regs->bank[pll_num].pllcr0, pll_cr0 |
+                                                               0x02000000);
+                       pll_sr2 = in_be32(&srds_regs->bank[pll_num].pllsr2);
+                       dc_status = (pll_sr2 >> 17) & DC_MASK;
+                       if (dc_status != dc)
+                               debug("DC mismatch\n");
+                       pll_cr0 = in_be32(&srds_regs->bank[pll_num].pllcr0);
+                       out_be32(&srds_regs->bank[pll_num].pllcr0, pll_cr0 &
+                                                               0xfdffffff);
+
+                       /* STEP 4 */
+                       /* Wait 750us to verify the PLL is locked
+                        * by checking SRDSxPLLnCR0[8] = 1.
+                        */
+                       udelay(750);
+                       pll_status = in_be32(&srds_regs->bank[pll_num].pllcr0);
+                       debug("A007186: pll_num=%x pllcr0=%x\n",
+                             pll_num, pll_status);
+
+                       if ((pll_status & SRDS_PLLCR0_PLL_LCK) == 0)
+                               printf("A007186 Serdes PLL not locked\n");
+                       else
+                               debug("A007186 Serdes PLL locked\n");
+               }
+       }
+#endif
+
        cfg >>= sd_prctl_shift;
        printf("Using SERDES%d Protocol: %d (0x%x)\n", sd + 1, cfg, cfg);
        if (!is_serdes_prtcl_valid(sd, cfg))
index 1034cd4..a5dfb81 100644 (file)
@@ -47,6 +47,7 @@ struct liodn_id_table liodn_tbl[] = {
 
        /* SET_NEXUS_LIODN(557), -- not yet implemented */
        SET_QE_LIODN(559),
+       SET_TDM_LIODN(560),
 };
 int liodn_tbl_sz = ARRAY_SIZE(liodn_tbl);
 
index 07e27de..7138bb4 100644 (file)
@@ -43,6 +43,10 @@ static const struct serdes_config serdes1_cfg_tbl[] = {
        {0x6C, {XFI_FM1_MAC9, XFI_FM1_MAC10,
                SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
                PCIE4, PCIE4, PCIE4, PCIE4} },
+       {0x1B, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10,
+               SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+               SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
+               SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
        {0x1C, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10,
                SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
                SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
@@ -59,18 +63,34 @@ static const struct serdes_config serdes1_cfg_tbl[] = {
                SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
                SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
                SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
+       {0x50, {XAUI_FM1_MAC9, XAUI_FM1_MAC9,
+               XAUI_FM1_MAC9, XAUI_FM1_MAC9,
+               PCIE4, SGMII_FM1_DTSEC4,
+               SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
        {0x51, {XAUI_FM1_MAC9, XAUI_FM1_MAC9,
                XAUI_FM1_MAC9, XAUI_FM1_MAC9,
                PCIE4, SGMII_FM1_DTSEC4,
                SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
+       {0x5E, {HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
+               HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
+               PCIE4, SGMII_FM1_DTSEC4,
+               SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
        {0x5F, {HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
                HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
                PCIE4, SGMII_FM1_DTSEC4,
                SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
+       {0x64, {HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
+               HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
+               PCIE4, SGMII_FM1_DTSEC4,
+               SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
        {0x65, {HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
                HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
                PCIE4, SGMII_FM1_DTSEC4,
                SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
+       {0x6A, {XFI_FM1_MAC9, XFI_FM1_MAC10,
+               XFI_FM1_MAC1, XFI_FM1_MAC2,
+               PCIE4, SGMII_FM1_DTSEC4,
+               SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
        {0x6B, {XFI_FM1_MAC9, XFI_FM1_MAC10,
                XFI_FM1_MAC1, XFI_FM1_MAC2,
                PCIE4, SGMII_FM1_DTSEC4,
@@ -115,6 +135,9 @@ static const struct serdes_config serdes1_cfg_tbl[] = {
        {0xD9, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1,
                SGMII_FM1_DTSEC2, PCIE4, SGMII_FM1_DTSEC4,
                SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
+       {0xD2, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1,
+               SGMII_FM1_DTSEC2, PCIE4, SGMII_FM1_DTSEC4,
+               SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
        {0xD3, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1,
                SGMII_FM1_DTSEC2, PCIE4, SGMII_FM1_DTSEC4,
                SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
@@ -127,8 +150,6 @@ static const struct serdes_config serdes1_cfg_tbl[] = {
        {0x66, {XFI_FM1_MAC9, XFI_FM1_MAC10,
                XFI_FM1_MAC1, XFI_FM1_MAC2,
                PCIE4, PCIE4, PCIE4, PCIE4} },
-
-#if defined(CONFIG_PPC_T2081)
        {0xAA, {PCIE3, PCIE3, PCIE3, PCIE3,
                PCIE4, PCIE4, PCIE4, PCIE4} },
        {0xCA, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1,
@@ -137,7 +158,6 @@ static const struct serdes_config serdes1_cfg_tbl[] = {
        {0x70, {XFI_FM1_MAC9, XFI_FM1_MAC10, SGMII_FM1_DTSEC1,
                SGMII_FM1_DTSEC2, PCIE4, SGMII_FM1_DTSEC4,
                SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
-#endif
        {}
 };
 
@@ -150,6 +170,7 @@ static const struct serdes_config serdes2_cfg_tbl[] = {
        {0x29, {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1} },
        {0x2D, {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1} },
        {0x15, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, SATA1, SATA2} },
+       {0x27, {PCIE1, PCIE1, PCIE1, PCIE1, NONE,  NONE,  SATA1, SATA2} },
        {0x18, {PCIE1, PCIE1, PCIE1, PCIE1, AURORA, AURORA, SATA1, SATA2} },
        {0x02, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1} },
        {0x36, {SRIO2, SRIO2, SRIO2, SRIO2, AURORA, AURORA, SATA1, SATA2} },
index 1f99a0a..74c4c81 100644 (file)
@@ -30,22 +30,41 @@ static const struct serdes_config serdes1_cfg_tbl[] = {
                HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
                HIGIG_FM1_MAC10, HIGIG_FM1_MAC10,
                HIGIG_FM1_MAC10, HIGIG_FM1_MAC10}},
+       {27, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
+               SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
+               SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+               SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4} },
        {28, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
                SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
                SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
                SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4}},
+       {35, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
+               SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
+               SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+               SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4} },
        {36, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
                SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
                SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
                SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4}},
+       {37, {NONE, NONE, QSGMII_FM1_B, NONE,
+               NONE, NONE, QSGMII_FM1_A, NONE} },
        {38, {NONE, NONE, QSGMII_FM1_B, NONE,
                NONE, NONE, QSGMII_FM1_A, NONE}},
+       {39, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
+               SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
+               NONE, NONE, QSGMII_FM1_A, NONE} },
        {40, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
                SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
                NONE, NONE, QSGMII_FM1_A, NONE}},
+       {45, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
+               SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
+               NONE, NONE, QSGMII_FM1_A, NONE} },
        {46, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
                SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
                NONE, NONE, QSGMII_FM1_A, NONE}},
+       {47, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
+               SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
+               NONE, NONE, QSGMII_FM1_A, NONE} },
        {48, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
                SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
                NONE, NONE, QSGMII_FM1_A, NONE}},
@@ -65,10 +84,18 @@ static const struct serdes_config serdes2_cfg_tbl[] = {
                HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
                HIGIG_FM2_MAC10, HIGIG_FM2_MAC10,
                HIGIG_FM2_MAC10, HIGIG_FM2_MAC10}},
+       {6, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
+               XAUI_FM2_MAC9, XAUI_FM2_MAC9,
+               SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+               SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
        {7, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
                XAUI_FM2_MAC9, XAUI_FM2_MAC9,
                SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
                SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
+       {12, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
+               XAUI_FM2_MAC9, XAUI_FM2_MAC9,
+               SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+               SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
        {13, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
                XAUI_FM2_MAC9, XAUI_FM2_MAC9,
                SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
@@ -77,10 +104,18 @@ static const struct serdes_config serdes2_cfg_tbl[] = {
                XAUI_FM2_MAC9, XAUI_FM2_MAC9,
                SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
                SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
+       {15, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+               HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+               SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+               SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
        {16, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
                HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
                SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
                SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
+       {21, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+               HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+               SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+               SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
        {22, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
                HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
                SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
@@ -89,6 +124,10 @@ static const struct serdes_config serdes2_cfg_tbl[] = {
                HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
                SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
                SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
+       {24, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+               HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+               SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+               SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
        {25, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
                HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
                SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
@@ -97,34 +136,66 @@ static const struct serdes_config serdes2_cfg_tbl[] = {
                HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
                SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
                SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
+       {27, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
+               SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
+               SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+               SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
        {28, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
                SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
                SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
                SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
+       {35, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
+               SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
+               SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+               SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
        {36, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
                SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
                SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
                SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
+       {37, {NONE, NONE, QSGMII_FM2_B, NONE,
+               NONE, NONE, QSGMII_FM2_A, NONE} },
        {38, {NONE, NONE, QSGMII_FM2_B, NONE,
                NONE, NONE, QSGMII_FM2_A, NONE} },
+       {39, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
+               SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
+               NONE, NONE, QSGMII_FM2_A, NONE} },
        {40, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
                SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
                NONE, NONE, QSGMII_FM2_A, NONE} },
+       {45, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
+               SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
+               NONE, NONE, QSGMII_FM2_A, NONE} },
        {46, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
                SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
                NONE, NONE, QSGMII_FM2_A, NONE} },
+       {47, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
+               SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
+               NONE, NONE, QSGMII_FM2_A, NONE} },
        {48, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
                SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
                NONE, NONE, QSGMII_FM2_A, NONE} },
+       {49, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
+               XAUI_FM2_MAC9, XAUI_FM2_MAC9,
+               NONE, NONE, QSGMII_FM2_A, NONE} },
        {50, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
                XAUI_FM2_MAC9, XAUI_FM2_MAC9,
                NONE, NONE, QSGMII_FM2_A, NONE} },
+       {51, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+               HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+               NONE, NONE, QSGMII_FM2_A, NONE} },
        {52, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
                HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
                NONE, NONE, QSGMII_FM2_A, NONE} },
+       {53, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+               HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+               NONE, NONE, QSGMII_FM2_A, NONE} },
        {54, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
                HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
                NONE, NONE, QSGMII_FM2_A, NONE} },
+       {55, {XFI_FM1_MAC9, XFI_FM1_MAC10,
+               XFI_FM2_MAC10, XFI_FM2_MAC9,
+               SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+               SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
        {56, {XFI_FM1_MAC9, XFI_FM1_MAC10,
                XFI_FM2_MAC10, XFI_FM2_MAC9,
                SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
@@ -137,22 +208,34 @@ static const struct serdes_config serdes2_cfg_tbl[] = {
 };
 static const struct serdes_config serdes3_cfg_tbl[] = {
        /* SerDes 3 */
+       {1, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1} },
        {2, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1}},
+       {3, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2} },
        {4, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2}},
+       {5, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1} },
        {6, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1}},
+       {7, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, NONE, NONE, NONE} },
        {8, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, NONE, NONE, NONE}},
        {9, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
                INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN}},
        {10, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
                INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN}},
+       {11, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
+               PCIE2, PCIE2, PCIE2, PCIE2} },
        {12, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
                PCIE2, PCIE2, PCIE2, PCIE2}},
+       {13, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
+               PCIE2, PCIE2, PCIE2, PCIE2} },
        {14, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
                PCIE2, PCIE2, PCIE2, PCIE2}},
+       {15, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
+               SRIO1, SRIO1, SRIO1, SRIO1} },
        {16, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
                SRIO1, SRIO1, SRIO1, SRIO1}},
        {17, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
                SRIO1, SRIO1, SRIO1, SRIO1}},
+       {18, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
+               SRIO1, SRIO1, SRIO1, SRIO1} },
        {19, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
                SRIO1, SRIO1, SRIO1, SRIO1}},
        {20, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
@@ -161,13 +244,21 @@ static const struct serdes_config serdes3_cfg_tbl[] = {
 };
 static const struct serdes_config serdes4_cfg_tbl[] = {
        /* SerDes 4 */
+       {1, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3} },
        {2, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3}},
+       {3, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, PCIE4, PCIE4} },
        {4, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, PCIE4, PCIE4}},
+       {5, {PCIE3, PCIE3, PCIE3, PCIE3, SRIO2, SRIO2, SRIO2, SRIO2} },
        {6, {PCIE3, PCIE3, PCIE3, PCIE3, SRIO2, SRIO2, SRIO2, SRIO2}},
+       {7, {PCIE3, PCIE3, PCIE3, PCIE3, SRIO2, SRIO2, SRIO2, SRIO2} },
        {8, {PCIE3, PCIE3, PCIE3, PCIE3, SRIO2, SRIO2, SRIO2, SRIO2}},
+       {9, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, SATA1, SATA2} },
        {10, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, SATA1, SATA2} },
+       {11, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, SATA1, SATA2} },
        {12, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, SATA1, SATA2} },
+       {13, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, SRIO2, SRIO2} },
        {14, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, SRIO2, SRIO2}},
+       {15, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, SRIO2, SRIO2} },
        {16, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, SRIO2, SRIO2}},
        {18, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, AURORA, AURORA}},
        {}
@@ -187,36 +278,66 @@ static const struct serdes_config serdes1_cfg_tbl[] = {
                HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
                HIGIG_FM1_MAC10, HIGIG_FM1_MAC10,
                HIGIG_FM1_MAC10, HIGIG_FM1_MAC10} },
+       {27, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
+               SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
+               SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+               SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4} },
        {28, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
                SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
                SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
                SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4} },
+       {35, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
+               SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
+               SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+               SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4} },
        {36, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
                SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
                SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
                SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4} },
+       {37, {NONE, NONE, QSGMII_FM1_B, NONE,
+               NONE, NONE, QSGMII_FM1_A, NONE} },
        {38, {NONE, NONE, QSGMII_FM1_B, NONE,
                NONE, NONE, QSGMII_FM1_A, NONE} },
        {}
 };
 static const struct serdes_config serdes2_cfg_tbl[] = {
        /* SerDes 2 */
+       {6, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
+               XAUI_FM2_MAC9, XAUI_FM2_MAC9,
+               SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+               SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
        {7, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
                XAUI_FM2_MAC9, XAUI_FM2_MAC9,
                SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
                SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
+       {12, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
+               XAUI_FM2_MAC9, XAUI_FM2_MAC9,
+               SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+               SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
        {13, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
                XAUI_FM2_MAC9, XAUI_FM2_MAC9,
                SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
                SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
+       {15, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+               HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+               SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+               SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
        {16, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
                HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
                SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
                SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
+       {21, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+               HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+               SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+               SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
        {22, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
                HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
                SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
                SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
+       {24, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+               HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+               SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+               SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
        {25, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
                HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
                SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
@@ -225,34 +346,66 @@ static const struct serdes_config serdes2_cfg_tbl[] = {
                HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
                SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
                NONE, NONE} },
+       {27, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
+               SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
+               SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+               SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
        {28, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
                SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
                SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
                SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
+       {35, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
+               SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
+               SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+               SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
        {36, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
                SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
                SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
                SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
+       {37, {NONE, NONE, QSGMII_FM2_B, NONE,
+               NONE, QSGMII_FM1_A, NONE, NONE} },
        {38, {NONE, NONE, QSGMII_FM2_B, NONE,
                NONE, QSGMII_FM1_A, NONE, NONE} },
+       {39, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
+               SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
+               NONE, QSGMII_FM1_A, NONE, NONE} },
        {40, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
                SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
                NONE, QSGMII_FM1_A, NONE, NONE} },
+       {45, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
+               SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
+               NONE, QSGMII_FM1_A, NONE, NONE} },
        {46, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
                SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
                NONE, QSGMII_FM1_A, NONE, NONE} },
+       {47, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
+               SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
+               NONE, QSGMII_FM1_A, NONE, NONE} },
        {48, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
                SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
                NONE, QSGMII_FM1_A, NONE, NONE} },
+       {49, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
+               XAUI_FM2_MAC9, XAUI_FM2_MAC9,
+               NONE, NONE, NONE, NONE} },
        {50, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
                XAUI_FM2_MAC9, XAUI_FM2_MAC9,
                NONE, NONE, NONE, NONE} },
+       {51, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+               HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+               NONE, NONE, NONE, NONE} },
        {52, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
                HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
                NONE, NONE, NONE, NONE} },
+       {53, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+               HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+               NONE, NONE, NONE, NONE} },
        {54, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
                HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
                NONE, NONE, NONE, NONE} },
+       {55, {NONE, XFI_FM1_MAC10,
+               XFI_FM2_MAC10, NONE,
+               SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+               SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
        {56, {NONE, XFI_FM1_MAC10,
                XFI_FM2_MAC10, NONE,