sunxi: Use CONFIG_MACH_SUN?I from Kconfig instead of CONFIG_SUN?I

Mostly automatic with:
    sed -i -e 's/CONFIG_\(SUN[45678]I\)/CONFIG_MACH_\1/g' $(git grep -l CONFIG_SUN[45678]I)
followed by removing the relevant #defines from include/configs/sun?i.h by
hand.

Signed-off-by: Ian Campbell <ijc@hellion.org.uk>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>

diff --git a/arch/arm/cpu/armv7/sunxi/Makefile b/arch/arm/cpu/armv7/sunxi/Makefile
index 24f1daee64766d1631122a65dcb13dcb88dbc8ea..82dbf764e438adc16c84d231cc910a875aa9e01a 100644 (file)
--- a/arch/arm/cpu/armv7/sunxi/Makefile
+++ b/arch/arm/cpu/armv7/sunxi/Makefile
@@ -11,13 +11,13 @@ obj-y       += timer.o
 obj-y  += board.o
 obj-y  += clock.o
 obj-y  += pinmux.o
-obj-$(CONFIG_SUN6I)    += prcm.o
-obj-$(CONFIG_SUN8I)    += prcm.o
-obj-$(CONFIG_SUN4I)    += clock_sun4i.o
-obj-$(CONFIG_SUN5I)    += clock_sun4i.o
-obj-$(CONFIG_SUN6I)    += clock_sun6i.o
-obj-$(CONFIG_SUN7I)    += clock_sun4i.o
-obj-$(CONFIG_SUN8I)    += clock_sun6i.o
+obj-$(CONFIG_MACH_SUN6I)       += prcm.o
+obj-$(CONFIG_MACH_SUN8I)       += prcm.o
+obj-$(CONFIG_MACH_SUN4I)       += clock_sun4i.o
+obj-$(CONFIG_MACH_SUN5I)       += clock_sun4i.o
+obj-$(CONFIG_MACH_SUN6I)       += clock_sun6i.o
+obj-$(CONFIG_MACH_SUN7I)       += clock_sun4i.o
+obj-$(CONFIG_MACH_SUN8I)       += clock_sun6i.o
 
 ifndef CONFIG_SPL_BUILD
 obj-y  += cpu_info.o
@@ -27,9 +27,9 @@ endif
 endif
 
 ifdef CONFIG_SPL_BUILD
-obj-$(CONFIG_SUN4I)    += dram.o
-obj-$(CONFIG_SUN5I)    += dram.o
-obj-$(CONFIG_SUN7I)    += dram.o
+obj-$(CONFIG_MACH_SUN4I)       += dram.o
+obj-$(CONFIG_MACH_SUN5I)       += dram.o
+obj-$(CONFIG_MACH_SUN7I)       += dram.o
 ifdef CONFIG_SPL_FEL
 obj-y  += start.o
 endif

diff --git a/arch/arm/cpu/armv7/sunxi/board.c b/arch/arm/cpu/armv7/sunxi/board.c
index 06eb6768e8f2b58ddbe1b2408157f8e4e89ccaab..6c812fc6e9ce351c4dddf910a978c5c3ffe442d9 100644 (file)
--- a/arch/arm/cpu/armv7/sunxi/board.c
+++ b/arch/arm/cpu/armv7/sunxi/board.c
@@ -51,7 +51,7 @@ u32 spl_boot_mode(void)
 int gpio_init(void)
 {
 #if CONFIG_CONS_INDEX == 1 && defined(CONFIG_UART0_PORT_F)
-#if defined(CONFIG_SUN4I) || defined(CONFIG_SUN7I)
+#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)
        /* disable GPB22,23 as uart0 tx,rx to avoid conflict */
        sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUNXI_GPIO_INPUT);
        sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUNXI_GPIO_INPUT);
@@ -59,23 +59,23 @@ int gpio_init(void)
        sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUNXI_GPF2_UART0_TX);
        sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUNXI_GPF4_UART0_RX);
        sunxi_gpio_set_pull(SUNXI_GPF(4), 1);
-#elif CONFIG_CONS_INDEX == 1 && (defined(CONFIG_SUN4I) || defined(CONFIG_SUN7I))
+#elif CONFIG_CONS_INDEX == 1 && (defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I))
        sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUN4I_GPB22_UART0_TX);
        sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUN4I_GPB23_UART0_RX);
        sunxi_gpio_set_pull(SUNXI_GPB(23), SUNXI_GPIO_PULL_UP);
-#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_SUN5I)
+#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN5I)
        sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN5I_GPB19_UART0_TX);
        sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN5I_GPB20_UART0_RX);
        sunxi_gpio_set_pull(SUNXI_GPB(20), SUNXI_GPIO_PULL_UP);
-#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_SUN6I)
+#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN6I)
        sunxi_gpio_set_cfgpin(SUNXI_GPH(20), SUN6I_GPH20_UART0_TX);
        sunxi_gpio_set_cfgpin(SUNXI_GPH(21), SUN6I_GPH21_UART0_RX);
        sunxi_gpio_set_pull(SUNXI_GPH(21), SUNXI_GPIO_PULL_UP);
-#elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_SUN5I)
+#elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_MACH_SUN5I)
        sunxi_gpio_set_cfgpin(SUNXI_GPG(3), SUN5I_GPG3_UART1_TX);
        sunxi_gpio_set_cfgpin(SUNXI_GPG(4), SUN5I_GPG4_UART1_RX);
        sunxi_gpio_set_pull(SUNXI_GPG(4), SUNXI_GPIO_PULL_UP);
-#elif CONFIG_CONS_INDEX == 5 && defined(CONFIG_SUN8I)
+#elif CONFIG_CONS_INDEX == 5 && defined(CONFIG_MACH_SUN8I)
        sunxi_gpio_set_cfgpin(SUNXI_GPL(2), SUN8I_GPL2_R_UART_TX);
        sunxi_gpio_set_cfgpin(SUNXI_GPL(3), SUN8I_GPL3_R_UART_RX);
        sunxi_gpio_set_pull(SUNXI_GPL(3), SUNXI_GPIO_PULL_UP);
@@ -88,7 +88,7 @@ int gpio_init(void)
 
 void reset_cpu(ulong addr)
 {
-#if defined(CONFIG_SUN4I) || defined(CONFIG_SUN5I) || defined(CONFIG_SUN7I)
+#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN5I) || defined(CONFIG_MACH_SUN7I)
        static const struct sunxi_wdog *wdog =
                 &((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog;
 
@@ -100,7 +100,7 @@ void reset_cpu(ulong addr)
                /* sun5i sometimes gets stuck without this */
                writel(WDT_MODE_RESET_EN | WDT_MODE_EN, &wdog->mode);
        }
-#else /* CONFIG_SUN6I || CONFIG_SUN8I || .. */
+#else /* CONFIG_MACH_SUN6I || CONFIG_MACH_SUN8I || .. */
        static const struct sunxi_wdog *wdog =
                 ((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog;
 
@@ -114,8 +114,8 @@ void reset_cpu(ulong addr)
 /* do some early init */
 void s_init(void)
 {
-#if !defined CONFIG_SPL_BUILD && (defined CONFIG_SUN7I || \
-               defined CONFIG_SUN6I || defined CONFIG_SUN8I)
+#if !defined CONFIG_SPL_BUILD && (defined CONFIG_MACH_SUN7I || \
+               defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I)
        /* Enable SMP mode for CPU0, by setting bit 6 of Auxiliary Ctl reg */
        asm volatile(
                "mrc p15, 0, r0, c1, c0, 1\n"

diff --git a/arch/arm/cpu/armv7/sunxi/clock_sun4i.c b/arch/arm/cpu/armv7/sunxi/clock_sun4i.c
index 4a0d64fb30e64db6b996d35e4134469a0ccfd385..a0e49d179feff469f212f479925bc6ab881b3585 100644 (file)
--- a/arch/arm/cpu/armv7/sunxi/clock_sun4i.c
+++ b/arch/arm/cpu/armv7/sunxi/clock_sun4i.c
@@ -35,7 +35,7 @@ void clock_init_safe(void)
               APB0_DIV_1 << APB0_DIV_SHIFT |
               CPU_CLK_SRC_PLL1 << CPU_CLK_SRC_SHIFT,
               &ccm->cpu_ahb_apb0_cfg);
-#ifdef CONFIG_SUN7I
+#ifdef CONFIG_MACH_SUN7I
        setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_DMA);
 #endif
        writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg);

diff --git a/arch/arm/cpu/armv7/sunxi/cpu_info.c b/arch/arm/cpu/armv7/sunxi/cpu_info.c
index 4f2a09cd2e28cbd69a498bab61c06341f4235473..41b9add297a2362732c360a6b51ec893735f06a7 100644 (file)
--- a/arch/arm/cpu/armv7/sunxi/cpu_info.c
+++ b/arch/arm/cpu/armv7/sunxi/cpu_info.c
@@ -13,9 +13,9 @@
 #ifdef CONFIG_DISPLAY_CPUINFO
 int print_cpuinfo(void)
 {
-#ifdef CONFIG_SUN4I
+#ifdef CONFIG_MACH_SUN4I
        puts("CPU:   Allwinner A10 (SUN4I)\n");
-#elif defined CONFIG_SUN5I
+#elif defined CONFIG_MACH_SUN5I
        u32 val = readl(SUNXI_SID_BASE + 0x08);
        switch ((val >> 12) & 0xf) {
        case 0: puts("CPU:   Allwinner A12 (SUN5I)\n"); break;
@@ -23,11 +23,11 @@ int print_cpuinfo(void)
        case 7: puts("CPU:   Allwinner A10s (SUN5I)\n"); break;
        default: puts("CPU:   Allwinner A1X (SUN5I)\n");
        }
-#elif defined CONFIG_SUN6I
+#elif defined CONFIG_MACH_SUN6I
        puts("CPU:   Allwinner A31 (SUN6I)\n");
-#elif defined CONFIG_SUN7I
+#elif defined CONFIG_MACH_SUN7I
        puts("CPU:   Allwinner A20 (SUN7I)\n");
-#elif defined CONFIG_SUN8I
+#elif defined CONFIG_MACH_SUN8I
        puts("CPU:   Allwinner A23 (SUN8I)\n");
 #else
 #warning Please update cpu_info.c with correct CPU information

diff --git a/arch/arm/cpu/armv7/sunxi/dram.c b/arch/arm/cpu/armv7/sunxi/dram.c
index 3cf3cbf19adb25fce553a4f88a8d35ca6909999a..dc9fdb930b6e5c51c2d7252f7b4511439c3f33a2 100644 (file)
--- a/arch/arm/cpu/armv7/sunxi/dram.c
+++ b/arch/arm/cpu/armv7/sunxi/dram.c
@@ -74,7 +74,7 @@ static void mctl_ddr3_reset(void)
        struct sunxi_dram_reg *dram =
                        (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
 
-#ifdef CONFIG_SUN4I
+#ifdef CONFIG_MACH_SUN4I
        struct sunxi_timer_reg *timer =
                        (struct sunxi_timer_reg *)SUNXI_TIMER_BASE;
        u32 reg_val;
@@ -113,7 +113,7 @@ static void mctl_set_drive(void)
 {
        struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
 
-#ifdef CONFIG_SUN7I
+#ifdef CONFIG_MACH_SUN7I
        clrsetbits_le32(&dram->mcr, DRAM_MCR_MODE_NORM(0x3) | (0x3 << 28),
 #else
        clrsetbits_le32(&dram->mcr, DRAM_MCR_MODE_NORM(0x3),
@@ -202,7 +202,7 @@ static void mctl_enable_dllx(u32 phase)
 }
 
 static u32 hpcr_value[32] = {
-#ifdef CONFIG_SUN5I
+#ifdef CONFIG_MACH_SUN5I
        0, 0, 0, 0,
        0, 0, 0, 0,
        0, 0, 0, 0,
@@ -212,7 +212,7 @@ static u32 hpcr_value[32] = {
        0x0301, 0x0301, 0x0301, 0x0301,
        0x0301, 0x0301, 0x0301, 0
 #endif
-#ifdef CONFIG_SUN4I
+#ifdef CONFIG_MACH_SUN4I
        0x0301, 0x0301, 0x0301, 0x0301,
        0x0301, 0x0301, 0, 0,
        0, 0, 0, 0,
@@ -222,7 +222,7 @@ static u32 hpcr_value[32] = {
        0x1035, 0x1031, 0x0731, 0x1035,
        0x1031, 0x0301, 0x0301, 0x0731
 #endif
-#ifdef CONFIG_SUN7I
+#ifdef CONFIG_MACH_SUN7I
        0x0301, 0x0301, 0x0301, 0x0301,
        0x0301, 0x0301, 0x0301, 0x0301,
        0, 0, 0, 0,
@@ -304,7 +304,7 @@ static void mctl_setup_dram_clock(u32 clk, u32 mbus_clk)
 
        setbits_le32(&ccm->pll5_cfg, CCM_PLL5_CTRL_DDR_CLK);
 
-#if defined(CONFIG_SUN4I) || defined(CONFIG_SUN7I)
+#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)
        /* reset GPS */
        clrbits_le32(&ccm->gps_clk_cfg, CCM_GPS_CTRL_RESET | CCM_GPS_CTRL_GATE);
        setbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_GPS);
@@ -318,7 +318,7 @@ static void mctl_setup_dram_clock(u32 clk, u32 mbus_clk)
 
        /* PLL5P and PLL6 are the potential clock sources for MBUS */
        pll6x_clk = clock_get_pll6() / 1000000;
-#ifdef CONFIG_SUN7I
+#ifdef CONFIG_MACH_SUN7I
        pll6x_clk *= 2; /* sun7i uses PLL6*2, sun5i uses just PLL6 */
 #endif
        pll5p_clk = clock_get_pll5p() / 1000000;
@@ -348,7 +348,7 @@ static void mctl_setup_dram_clock(u32 clk, u32 mbus_clk)
         * open DRAMC AHB & DLL register clock
         * close it first
         */
-#if defined(CONFIG_SUN5I) || defined(CONFIG_SUN7I)
+#if defined(CONFIG_MACH_SUN5I) || defined(CONFIG_MACH_SUN7I)
        clrbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_SDRAM | CCM_AHB_GATE_DLL);
 #else
        clrbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_SDRAM);
@@ -356,7 +356,7 @@ static void mctl_setup_dram_clock(u32 clk, u32 mbus_clk)
        udelay(22);
 
        /* then open it */
-#if defined(CONFIG_SUN5I) || defined(CONFIG_SUN7I)
+#if defined(CONFIG_MACH_SUN5I) || defined(CONFIG_MACH_SUN7I)
        setbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_SDRAM | CCM_AHB_GATE_DLL);
 #else
        setbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_SDRAM);
@@ -417,7 +417,7 @@ static int dramc_scan_readpipe(void)
 
 static void dramc_clock_output_en(u32 on)
 {
-#if defined(CONFIG_SUN5I) || defined(CONFIG_SUN7I)
+#if defined(CONFIG_MACH_SUN5I) || defined(CONFIG_MACH_SUN7I)
        struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
 
        if (on)
@@ -425,7 +425,7 @@ static void dramc_clock_output_en(u32 on)
        else
                clrbits_le32(&dram->mcr, DRAM_MCR_DCLK_OUT);
 #endif
-#ifdef CONFIG_SUN4I
+#ifdef CONFIG_MACH_SUN4I
        struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
        if (on)
                setbits_le32(&ccm->dram_clk_cfg, CCM_DRAM_CTRL_DCLK_OUT);
@@ -527,7 +527,7 @@ static void mctl_set_impedance(u32 zq, u32 odt_en)
        u32 reg_val;
        u32 zprog = zq & 0xFF, zdata = (zq >> 8) & 0xFFFFF;
 
-#ifndef CONFIG_SUN7I
+#ifndef CONFIG_MACH_SUN7I
        /* Appears that some kind of automatically initiated default
         * ZQ calibration is already in progress at this point on sun4i/sun5i
         * hardware, but not on sun7i. So it is reasonable to wait for its
@@ -539,7 +539,7 @@ static void mctl_set_impedance(u32 zq, u32 odt_en)
        if (!odt_en)
                return;
 
-#ifdef CONFIG_SUN7I
+#ifdef CONFIG_MACH_SUN7I
        /* Enabling ODT in SDR_IOCR on sun7i hardware results in a deadlock
         * unless bit 24 is set in SDR_ZQCR1. Not much is known about the
         * SDR_ZQCR1 register, but there are hints indicating that it might
@@ -597,7 +597,7 @@ static unsigned long dramc_init_helper(struct dram_para *para)
        /* dram clock off */
        dramc_clock_output_en(0);
 
-#ifdef CONFIG_SUN4I
+#ifdef CONFIG_MACH_SUN4I
        /* select dram controller 1 */
        writel(DRAM_CSEL_MAGIC, &dram->csel);
 #endif
@@ -654,7 +654,7 @@ static unsigned long dramc_init_helper(struct dram_para *para)
        writel(para->tpr2, &dram->tpr2);
 
        reg_val = DRAM_MR_BURST_LENGTH(0x0);
-#if (defined(CONFIG_SUN5I) || defined(CONFIG_SUN7I))
+#if (defined(CONFIG_MACH_SUN5I) || defined(CONFIG_MACH_SUN7I))
        reg_val |= DRAM_MR_POWER_DOWN;
 #endif
        reg_val |= DRAM_MR_CAS_LAT(para->cas - 4);
@@ -668,7 +668,7 @@ static unsigned long dramc_init_helper(struct dram_para *para)
        /* disable drift compensation and set passive DQS window mode */
        clrsetbits_le32(&dram->ccr, DRAM_CCR_DQS_DRIFT_COMP, DRAM_CCR_DQS_GATE);
 
-#ifdef CONFIG_SUN7I
+#ifdef CONFIG_MACH_SUN7I
        /* Command rate timing mode 2T & 1T */
        if (para->tpr4 & 0x1)
                setbits_le32(&dram->ccr, DRAM_CCR_COMMAND_RATE_1T);
@@ -718,7 +718,7 @@ unsigned long dramc_init(struct dram_para *para)
        /* try to autodetect the DRAM bus width and density */
        para->io_width  = 16;
        para->bus_width = 32;
-#if defined(CONFIG_SUN4I) || defined(CONFIG_SUN5I)
+#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN5I)
        /* only A0-A14 address lines on A10/A13, limiting max density to 4096 */
        para->density = 4096;
 #else

diff --git a/arch/arm/include/asm/arch-sunxi/clock.h b/arch/arm/include/asm/arch-sunxi/clock.h
index c562f621c22624ddf8589afb3e2cc3090eac8b1c..42382a8ae2ff365694bf7a37a1618733fbabaf73 100644 (file)
--- a/arch/arm/include/asm/arch-sunxi/clock.h
+++ b/arch/arm/include/asm/arch-sunxi/clock.h
@@ -15,7 +15,7 @@
 #define CLK_GATE_CLOSE                 0x0
 
 /* clock control module regs definition */
-#if defined(CONFIG_SUN6I) || defined(CONFIG_SUN8I)
+#if defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN8I)
 #include <asm/arch/clock_sun6i.h>
 #else
 #include <asm/arch/clock_sun4i.h>

diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h b/arch/arm/include/asm/arch-sunxi/gpio.h
index 7bb649950a982d19d9ea293352a35e82414e06ad..1527a6baad123554a4170e16c0e4c801134bc72f 100644 (file)
--- a/arch/arm/include/asm/arch-sunxi/gpio.h
+++ b/arch/arm/include/asm/arch-sunxi/gpio.h
@@ -155,7 +155,7 @@ enum sunxi_gpio_number {
 
 #define SUNXI_GPF2_SDC0                2
 
-#ifdef CONFIG_SUN8I
+#ifdef CONFIG_MACH_SUN8I
 #define SUNXI_GPF2_UART0_TX    3
 #define SUNXI_GPF4_UART0_RX    3
 #else

diff --git a/arch/arm/include/asm/arch-sunxi/mmc.h b/arch/arm/include/asm/arch-sunxi/mmc.h
index 8a216740a722e4471f4f39680634fe9db861b354..537f1455643cc5ffae3d998599f3b941d2244568 100644 (file)
--- a/arch/arm/include/asm/arch-sunxi/mmc.h
+++ b/arch/arm/include/asm/arch-sunxi/mmc.h
@@ -43,7 +43,7 @@ struct sunxi_mmc {
        u32 chda;               /* 0x90 */
        u32 cbda;               /* 0x94 */
        u32 res1[26];
-#if defined(CONFIG_SUN6I) || defined(CONFIG_SUN8I)
+#if defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN8I)
        u32 res2[64];
 #endif
        u32 fifo;               /* 0x100 (0x200 on sun6i) FIFO access address */

diff --git a/arch/arm/include/asm/arch-sunxi/timer.h b/arch/arm/include/asm/arch-sunxi/timer.h
index 03a0684c797a3c28179886a283ca2382d249b17b..9a5e488a38080f489494fd1f45a987c68142d1b6 100644 (file)
--- a/arch/arm/include/asm/arch-sunxi/timer.h
+++ b/arch/arm/include/asm/arch-sunxi/timer.h
@@ -67,7 +67,7 @@ struct sunxi_timer_reg {
        struct sunxi_timer timer[6];    /* We have 6 timers */
        u8 res2[16];
        struct sunxi_avs avs;
-#if defined(CONFIG_SUN4I) || defined(CONFIG_SUN5I) || defined(CONFIG_SUN7I)
+#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN5I) || defined(CONFIG_MACH_SUN7I)
        struct sunxi_wdog wdog; /* 0x90 */
        /* XXX the following is not accurate for sun5i/sun7i */
        struct sunxi_64cnt cnt64;       /* 0xa0 */
@@ -77,7 +77,7 @@ struct sunxi_timer_reg {
        struct sunxi_tgp tgp[4];
        u8 res5[8];
        u32 cpu_cfg;
-#else /* CONFIG_SUN6I || CONFIG_SUN8I || ... */
+#else /* CONFIG_MACH_SUN6I || CONFIG_MACH_SUN8I || ... */
        u8 res3[16];
        struct sunxi_wdog wdog[5];      /* We have 5 watchdogs */
 #endif

diff --git a/arch/arm/include/asm/arch-sunxi/watchdog.h b/arch/arm/include/asm/arch-sunxi/watchdog.h
index ccc8fa32c49df2244e7d6ff67b994824722ec3f4..8108be97bab08ec75128853ca07e4c65253d98f6 100644 (file)
--- a/arch/arm/include/asm/arch-sunxi/watchdog.h
+++ b/arch/arm/include/asm/arch-sunxi/watchdog.h
@@ -13,7 +13,7 @@
 #define WDT_CTRL_RESTART       (0x1 << 0)
 #define WDT_CTRL_KEY           (0x0a57 << 1)
 
-#if defined(CONFIG_SUN4I) || defined(CONFIG_SUN5I) || defined(CONFIG_SUN7I)
+#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN5I) || defined(CONFIG_MACH_SUN7I)
 
 #define WDT_MODE_EN            (0x1 << 0)
 #define WDT_MODE_RESET_EN      (0x1 << 1)

diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c
index 16592e3d7cf2454e00013181576dcb0ea437822e..f2fa12efa242ce8659d29577c8c63217b9818d6c 100644 (file)
--- a/drivers/mmc/sunxi_mmc.c
+++ b/drivers/mmc/sunxi_mmc.c
@@ -75,7 +75,7 @@ static int mmc_clk_io_on(int sdc_no)
        /* config ahb clock */
        setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MMC(sdc_no));
 
-#if defined(CONFIG_SUN6I) || defined(CONFIG_SUN8I)
+#if defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN8I)
        /* unassert reset */
        setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MMC(sdc_no));
 #endif
@@ -385,7 +385,7 @@ struct mmc *sunxi_mmc_init(int sdc_no)
        cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
        cfg->host_caps = MMC_MODE_4BIT;
        cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
-#if defined(CONFIG_SUN6I) || defined(CONFIG_SUN7I) || defined(CONFIG_SUN8I)
+#if defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN7I) || defined(CONFIG_MACH_SUN8I)
        cfg->host_caps |= MMC_MODE_HC;
 #endif
        cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;

diff --git a/drivers/usb/host/ehci-sunxi.c b/drivers/usb/host/ehci-sunxi.c
index 23617b7adc131a8770ba8715bccffc04e261eafa..d65e7985a7b3f9e97948ba35fe1804b848170607 100644 (file)
--- a/drivers/usb/host/ehci-sunxi.c
+++ b/drivers/usb/host/ehci-sunxi.c
@@ -105,7 +105,7 @@ static void sunxi_usb_phy_init(struct sunxi_ehci_hcd *sunxi_ehci)
        usb_phy_write(sunxi_ehci, 0x20, 0x14, 5);
 
        /* threshold adjustment disconnect */
-#ifdef CONFIG_SUN4I
+#ifdef CONFIG_MACH_SUN4I
        usb_phy_write(sunxi_ehci, 0x2a, 3, 2);
 #else
        usb_phy_write(sunxi_ehci, 0x2a, 2, 2);

diff --git a/include/configs/sun4i.h b/include/configs/sun4i.h
index d0191a32b1a6d99807cf75becf4821f2e6879cfd..e0ec52dcde7fb7c296c5a92acca7a5bc4ab062c4 100644 (file)
--- a/include/configs/sun4i.h
+++ b/include/configs/sun4i.h
@@ -11,7 +11,6 @@
 /*
  * A10 specific configuration
  */
-#define CONFIG_SUN4I           /* sun4i SoC generation */
 #define CONFIG_CLK_FULL_SPEED          1008000000
 
 #define CONFIG_SYS_PROMPT              "sun4i# "

diff --git a/include/configs/sun5i.h b/include/configs/sun5i.h
index 7b683e9c8908394e56072d545f873d0e5f798c6a..09f7533575c83518c43c040ecf944a787aab4fba 100644 (file)
--- a/include/configs/sun5i.h
+++ b/include/configs/sun5i.h
@@ -11,7 +11,6 @@
 /*
  * High Level Configuration Options
  */
-#define CONFIG_SUN5I           /* sun5i SoC generation */
 #define CONFIG_CLK_FULL_SPEED          1008000000
 
 #define CONFIG_SYS_PROMPT              "sun5i# "

diff --git a/include/configs/sun6i.h b/include/configs/sun6i.h
index 93a1d965ca4e680e27f24ff7fd8efac3f154faf6..b7144745c9204603ffc5be64c041e4c287f13220 100644 (file)
--- a/include/configs/sun6i.h
+++ b/include/configs/sun6i.h
@@ -14,7 +14,6 @@
 /*
  * A31 specific configuration
  */
-#define CONFIG_SUN6I           /* sun6i SoC generation */
 
 #define CONFIG_SYS_PROMPT              "sun6i# "
 

diff --git a/include/configs/sun7i.h b/include/configs/sun7i.h
index 966cbd8e83f6cb2659f64798cfeb502a1b5e6aa4..0193826a9dd404938f815487cb982a9f9ac01e8e 100644 (file)
--- a/include/configs/sun7i.h
+++ b/include/configs/sun7i.h
@@ -12,7 +12,6 @@
 /*
  * A20 specific configuration
  */
-#define CONFIG_SUN7I           /* sun7i SoC generation */
 #define CONFIG_CLK_FULL_SPEED          912000000
 
 #define CONFIG_SYS_PROMPT              "sun7i# "

diff --git a/include/configs/sun8i.h b/include/configs/sun8i.h
index 1c1a7cde5ec1762d6a1702ed5a295c17c4696459..6f1fc48cf02d08cbbfc5b13f857ad892512c6d4e 100644 (file)
--- a/include/configs/sun8i.h
+++ b/include/configs/sun8i.h
@@ -12,7 +12,6 @@
 /*
  * A23 specific configuration
  */
-#define CONFIG_SUN8I           /* sun8i SoC generation */
 #define CONFIG_SYS_PROMPT      "sun8i# "
 
 /*