static bd_t bdata __section(".data");
#endif
-/*
- * This delay function is intended to be used only in early stage of boot, where
- * clock are not set up yet. The timer used here is reset on every boot and
- * takes a few seconds to roll. The boot doesn't take that long, so to keep the
- * code simple, it doesn't take rolling into consideration.
- */
-/*
- * There's nothing to be taken into consideration for the rollover.
- * Two's complement arithmetic used correctly does all that's needed
- * automagically.
- */
-void early_delay(int delay)
-{
- struct mxs_digctl_regs *digctl_regs =
- (struct mxs_digctl_regs *)MXS_DIGCTL_BASE;
- u32 start = readl(&digctl_regs->hw_digctl_microseconds);
-
- while (readl(&digctl_regs->hw_digctl_microseconds) - start < delay);
-}
-
#define MUX_CONFIG_BOOTMODE_PAD (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL)
static const iomux_cfg_t iomux_boot[] = {
#if defined(CONFIG_SOC_MX23)
debug("SPL: Setting mx23 VDDMEM\n");
/* We must wait before and after disabling the current limiter! */
- early_delay(10000);
+ udelay(10000);
clrbits_le32(&power_regs->hw_power_vddmemctrl,
POWER_VDDMEMCTRL_ENABLE_ILIMIT);
- early_delay(10000);
+ udelay(10000);
}
for (;;) {
if (!(readl(MXS_EMI_BASE + 0x10) & (1 << 1)))
break;
- early_delay(1000);
+ udelay(1000);
}
/* Adjust EMI port priority. */
clrsetbits_le32(0x80020000, 0x1f << 16, 0x2);
- early_delay(20000);
+ udelay(20000);
setbits_le32(MXS_DRAM_BASE + 0x40, 1 << 19);
setbits_le32(MXS_DRAM_BASE + 0x40, 1 << 11);
void mxs_mem_init(void)
{
- early_delay(11000);
+ udelay(11000);
mxs_mem_init_clock();
*/
setbits_le32(&clkctrl_regs->hw_clkctrl_pll0ctrl0,
CLKCTRL_PLL0CTRL0_POWER);
- early_delay(100);
+ udelay(100);
/*
* TODO: Should the PLL0 FORCE_LOCK bit be set here followed be a
struct mxs_rtc_regs *rtc_regs = (void *)MXS_RTC_BASE;
while ((val = readl(&rtc_regs->hw_rtc_stat)) & mask) {
- early_delay(1);
+ udelay(1);
if (timeout-- < 0)
break;
}
writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
&power_regs->hw_power_5vctrl_clr);
- early_delay(500000);
+ udelay(500000);
volt = mxs_get_batt_volt();
if (!fixed_batt_supply) {
/* 5V to battery handoff ... FIXME */
setbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER);
- early_delay(30);
+ udelay(30);
clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER);
}
}
if (xfer) {
setbits_le32(&power_regs->hw_power_5vctrl,
POWER_5VCTRL_DCDC_XFER);
- early_delay(20);
+ udelay(20);
clrbits_le32(&power_regs->hw_power_5vctrl,
POWER_5VCTRL_DCDC_XFER);
POWER_DCDC4P2_ENABLE_DCDC);
}
- early_delay(25);
+ udelay(25);
clrsetbits_le32(&power_regs->hw_power_5vctrl,
POWER_5VCTRL_VBUSVALID_TRSH_MASK, vbus_thresh);
POWER_STS_DCDC_4P2_BO)) {
tmp = readl(&power_regs->hw_power_5vctrl);
tmp |= POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK;
- early_delay(100);
+ udelay(100);
writel(tmp, &power_regs->hw_power_5vctrl);
break;
} else {
tmp2 |= tmp <<
POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET;
writel(tmp2, &power_regs->hw_power_5vctrl);
- early_delay(100);
+ udelay(100);
}
}
}
mxs_power_init_dcdc_4p2_source();
writel(vdddctrl, &power_regs->hw_power_vdddctrl);
- early_delay(20);
+ udelay(20);
writel(vddactrl, &power_regs->hw_power_vddactrl);
- early_delay(20);
+ udelay(20);
writel(vddioctrl, &power_regs->hw_power_vddioctrl);
/*
/* 5V to battery handoff. */
setbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER);
- early_delay(30);
+ udelay(30);
clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER);
writel(POWER_CTRL_ENIRQ_DCDC4P2_BO, &power_regs->hw_power_ctrl_clr);
return;
}
- early_delay(1000);
+ udelay(1000);
if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
debug("SPL: 5V VDD good (after delay)\n");
mxs_boot_valid_5v();
if (powered_by_linreg ||
(readl(&power_regs->hw_power_sts) &
POWER_STS_VDD5V_GT_VDDIO)) {
- early_delay(500);
+ udelay(500);
} else {
while (!(readl(&power_regs->hw_power_sts) &
POWER_STS_DC_OK)) {
mxs_lradc_init();
mxs_lradc_enable_batt_measurement();
- early_delay(10);
+ udelay(10);
}
/**