# SPDX-License-Identifier: GPL-2.0+
#
- VERSION = 2013
- PATCHLEVEL = 10
+ VERSION = 2014
+ PATCHLEVEL = 01
SUBLEVEL =
- EXTRAVERSION =
+ EXTRAVERSION = -rc1
ifneq "$(SUBLEVEL)" ""
U_BOOT_VERSION = $(VERSION).$(PATCHLEVEL).$(SUBLEVEL)$(EXTRAVERSION)
else
# the object files are placed in the source directory.
#
- ifdef O
ifeq ("$(origin O)", "command line")
BUILD_DIR := $(O)
endif
- endif
# Call a source code checker (by default, "sparse") as part of the
# C compilation.
# The "examples" conditionally depend on U-Boot (say, when USE_PRIVATE_LIBGCC
# is "yes"), so compile examples after U-Boot is compiled.
SUBDIR_TOOLS = tools
- SUBDIR_EXAMPLES = examples/standalone examples/api
SUBDIRS = $(SUBDIR_TOOLS)
.PHONY : $(SUBDIRS) $(VERSION_FILE) $(TIMESTAMP_FILE)
sinclude $(obj)include/autoconf.mk.dep
sinclude $(obj)include/autoconf.mk
+ SUBDIR_EXAMPLES-y := examples/standalone
+ SUBDIR_EXAMPLES-$(CONFIG_API) += examples/api
ifndef CONFIG_SANDBOX
- SUBDIRS += $(SUBDIR_EXAMPLES)
+ SUBDIRS += $(SUBDIR_EXAMPLES-y)
endif
# load ARCH, BOARD, and CPU configuration
HAVE_VENDOR_COMMON_LIB = $(if $(wildcard board/$(VENDOR)/common/Makefile),y,n)
- LIBS-y += lib/libgeneric.o
- LIBS-y += lib/rsa/librsa.o
- LIBS-y += lib/lzma/liblzma.o
- LIBS-y += lib/lzo/liblzo.o
- LIBS-y += lib/zlib/libz.o
- LIBS-$(CONFIG_TIZEN) += lib/tizen/libtizen.o
- LIBS-$(HAVE_VENDOR_COMMON_LIB) += board/$(VENDOR)/common/lib$(VENDOR).o
- LIBS-y += $(CPUDIR)/lib$(CPU).o
+ LIBS-y += lib/
+ LIBS-$(HAVE_VENDOR_COMMON_LIB) += board/$(VENDOR)/common/
+ LIBS-y += $(CPUDIR)/
ifdef SOC
- LIBS-y += $(CPUDIR)/$(SOC)/lib$(SOC).o
- endif
- ifeq ($(CPU),ixp)
- LIBS-y += drivers/net/npe/libnpe.o
- endif
- LIBS-$(CONFIG_OF_EMBED) += dts/libdts.o
- LIBS-y += arch/$(ARCH)/lib/lib$(ARCH).o
- LIBS-y += fs/libfs.o \
- fs/fat/libfat.o
- LIBS-y += net/libnet.o
- LIBS-y += disk/libdisk.o
- LIBS-y += drivers/libdrivers.o
- LIBS-y += drivers/dma/libdma.o
- LIBS-y += drivers/gpio/libgpio.o
- LIBS-y += drivers/i2c/libi2c.o
- LIBS-y += drivers/input/libinput.o
- LIBS-y += drivers/mmc/libmmc.o
- LIBS-y += drivers/mtd/libmtd.o
- LIBS-y += drivers/mtd/nand/libnand.o
- LIBS-y += drivers/mtd/onenand/libonenand.o
- LIBS-y += drivers/mtd/ubi/libubi.o
- LIBS-y += drivers/mtd/spi/libspi_flash.o
- LIBS-y += drivers/net/libnet.o
- LIBS-y += drivers/net/phy/libphy.o
- LIBS-y += drivers/pci/libpci.o
- LIBS-y += drivers/power/libpower.o \
- drivers/power/fuel_gauge/libfuel_gauge.o \
- drivers/power/mfd/libmfd.o \
- drivers/power/pmic/libpmic.o \
- drivers/power/battery/libbattery.o
- LIBS-y += drivers/spi/libspi.o
- ifeq ($(CPU),mpc83xx)
- LIBS-y += drivers/qe/libqe.o
- LIBS-y += arch/powerpc/cpu/mpc8xxx/ddr/libddr.o
- LIBS-y += arch/powerpc/cpu/mpc8xxx/lib8xxx.o
- endif
- ifeq ($(CPU),mpc85xx)
- LIBS-y += drivers/qe/libqe.o
- LIBS-y += drivers/net/fm/libfm.o
- LIBS-y += arch/powerpc/cpu/mpc8xxx/ddr/libddr.o
- LIBS-y += arch/powerpc/cpu/mpc8xxx/lib8xxx.o
- endif
- ifeq ($(CPU),mpc86xx)
- LIBS-y += arch/powerpc/cpu/mpc8xxx/ddr/libddr.o
- LIBS-y += arch/powerpc/cpu/mpc8xxx/lib8xxx.o
- endif
- LIBS-y += drivers/serial/libserial.o
- LIBS-y += drivers/usb/eth/libusb_eth.o
- LIBS-y += drivers/usb/gadget/libusb_gadget.o
- LIBS-y += drivers/usb/host/libusb_host.o
- LIBS-y += drivers/usb/musb/libusb_musb.o
- LIBS-y += drivers/usb/musb-new/libusb_musb-new.o
- LIBS-y += drivers/usb/phy/libusb_phy.o
- LIBS-y += drivers/usb/ulpi/libusb_ulpi.o
- LIBS-y += common/libcommon.o
- LIBS-y += lib/libfdt/libfdt.o
- LIBS-y += api/libapi.o
- LIBS-y += post/libpost.o
- LIBS-y += test/libtest.o
+ LIBS-y += $(CPUDIR)/$(SOC)/
+ endif
+ LIBS-$(CONFIG_IXP4XX_NPE) += drivers/net/npe/
+ LIBS-$(CONFIG_OF_EMBED) += dts/
+ LIBS-y += arch/$(ARCH)/lib/
+ LIBS-y += fs/
+ LIBS-y += net/
+ LIBS-y += disk/
+ LIBS-y += drivers/
+ LIBS-y += drivers/dma/
+ LIBS-y += drivers/gpio/
+ LIBS-y += drivers/i2c/
+ LIBS-y += drivers/input/
+ LIBS-y += drivers/mmc/
+ LIBS-y += drivers/mtd/
+ LIBS-y += drivers/mtd/nand/
+ LIBS-y += drivers/mtd/onenand/
+ LIBS-y += drivers/mtd/ubi/
+ LIBS-y += drivers/mtd/spi/
+ LIBS-y += drivers/net/
+ LIBS-y += drivers/net/phy/
+ LIBS-y += drivers/pci/
+ LIBS-y += drivers/power/ \
+ drivers/power/fuel_gauge/ \
+ drivers/power/mfd/ \
+ drivers/power/pmic/ \
+ drivers/power/battery/
+ LIBS-y += drivers/spi/
+ LIBS-$(CONFIG_FMAN_ENET) += drivers/net/fm/
+ LIBS-$(CONFIG_SYS_FSL_DDR) += drivers/ddr/fsl/
+ LIBS-y += drivers/serial/
+ LIBS-y += drivers/usb/eth/
+ LIBS-y += drivers/usb/gadget/
+ LIBS-y += drivers/usb/host/
+ LIBS-y += drivers/usb/musb/
+ LIBS-y += drivers/usb/musb-new/
+ LIBS-y += drivers/usb/phy/
+ LIBS-y += drivers/usb/ulpi/
+ LIBS-y += common/
+ LIBS-y += lib/libfdt/
+ LIBS-$(CONFIG_API) += api/
+ LIBS-y += post/
+ LIBS-y += test/
ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx31 mx35 mxs vf610))
- LIBS-y += arch/$(ARCH)/imx-common/libimx-common.o
+ LIBS-y += arch/$(ARCH)/imx-common/
endif
- LIBS-$(CONFIG_ARM) += arch/arm/cpu/libcpu.o
+ LIBS-$(CONFIG_ARM) += arch/arm/cpu/
+ LIBS-$(CONFIG_PPC) += arch/powerpc/cpu/
+
+ LIBS-y += board/$(BOARDDIR)/
+ LIBS-y := $(patsubst %/, %/built-in.o, $(LIBS-y))
LIBS := $(addprefix $(obj),$(sort $(LIBS-y)))
.PHONY : $(LIBS)
- LIBBOARD = board/$(BOARDDIR)/lib$(BOARD).o
- LIBBOARD := $(addprefix $(obj),$(LIBBOARD))
-
# Add GCC lib
ifdef USE_PRIVATE_LIBGCC
ifeq ("$(USE_PRIVATE_LIBGCC)", "yes")
sed -ne 's/GNU ld version \([0-9][0-9]*\)\.\([0-9][0-9]*\).*/-DLD_MAJOR=\1 -DLD_MINOR=\2/p')
__OBJS := $(subst $(obj),,$(OBJS))
- __LIBS := $(subst $(obj),,$(LIBS)) $(subst $(obj),,$(LIBBOARD))
+ __LIBS := $(subst $(obj),,$(LIBS))
#########################################################################
#########################################################################
build := -f $(TOPDIR)/scripts/Makefile.build -C
- all: $(ALL-y) $(SUBDIR_EXAMPLES)
+ all: $(ALL-y) $(SUBDIR_EXAMPLES-y)
$(obj)u-boot.dtb: checkdtc $(obj)u-boot
$(MAKE) $(build) dts binary
$(OBJCOPY) ${OBJCFLAGS} -O ihex $< $@
$(obj)u-boot.srec: $(obj)u-boot
- $(OBJCOPY) -O srec $< $@
+ $(OBJCOPY) ${OBJCFLAGS} -O srec $< $@
$(obj)u-boot.bin: $(obj)u-boot
$(OBJCOPY) ${OBJCFLAGS} -O binary $< $@
endif
$(obj)u-boot: depend \
- $(SUBDIR_TOOLS) $(OBJS) $(LIBBOARD) $(LIBS) $(LDSCRIPT) $(obj)u-boot.lds
+ $(SUBDIR_TOOLS) $(OBJS) $(LIBS) $(LDSCRIPT) $(obj)u-boot.lds
$(GEN_UBOOT)
ifeq ($(CONFIG_KALLSYMS),y)
smap=`$(call SYSTEM_MAP,$(obj)u-boot) | \
$(LIBS): depend $(SUBDIR_TOOLS)
$(MAKE) $(build) $(dir $(subst $(obj),,$@))
- mv $(dir $@)built-in.o $@
-
- $(LIBBOARD): depend $(LIBS)
- $(MAKE) $(build) $(dir $(subst $(obj),,$@))
- mv $(dir $@)built-in.o $@
$(SUBDIRS): depend
$(MAKE) -C $@ all
- $(SUBDIR_EXAMPLES): $(obj)u-boot
+ $(SUBDIR_EXAMPLES-y): $(obj)u-boot
$(LDSCRIPT): depend
$(MAKE) -C $(dir $@) $(notdir $@)
$(obj)tpl/u-boot-tpl.bin: $(SUBDIR_TOOLS) depend
$(MAKE) -C spl all CONFIG_TPL_BUILD=y
- updater:
- $(MAKE) -C tools/updater all
-
# Explicitly make _depend in subdirs containing multiple targets to prevent
# parallel sub-makes creating .depend files simultaneously.
depend dep: $(TIMESTAMP_FILE) $(VERSION_FILE) \
grep -v '\(compiled\)\|\(\.o$$\)\|\( [aUw] \)\|\(\.\.ng$$\)\|\(LASH[RL]DI\)' | \
LC_ALL=C sort
$(obj)System.map: $(obj)u-boot
- @$(call SYSTEM_MAP,$<) > $(obj)System.map
+ @$(call SYSTEM_MAP,$<) > $@
checkthumb:
@if test $(call cc-version) -lt 0404; then \
all $(obj)u-boot.hex $(obj)u-boot.srec $(obj)u-boot.bin \
$(obj)u-boot.img $(obj)u-boot.dis $(obj)u-boot \
$(filter-out tools,$(SUBDIRS)) \
- updater depend dep tags ctags etags cscope $(obj)System.map:
+ depend dep tags ctags etags cscope $(obj)System.map:
@echo "System not configured - see README" >&2
@ exit 1
$(obj).boards.depend: boards.cfg
@awk '(NF && $$1 !~ /^#/) { print $$7 ": " $$7 "_config; $$(MAKE)" }' $< > $@
- #
- # Functions to generate common board directory names
- #
- lcname = $(shell echo $(1) | sed -e 's/\(.*\)_config/\L\1/')
- ucname = $(shell echo $(1) | sed -e 's/\(.*\)_config/\U\1/')
-
#########################################################################
#########################################################################
@rm -f $(obj)MLO MLO.byteswap
@rm -f $(obj)SPL
@rm -f $(obj)tools/xway-swap-bytes
- @rm -f $(obj)arch/powerpc/cpu/mpc824x/bedbug_603e.c
- @rm -f $(obj)arch/powerpc/cpu/mpc83xx/ddr-gen?.c
@rm -fr $(obj)include/asm/proc $(obj)include/asm/arch $(obj)include/asm
@rm -fr $(obj)include/generated
@[ ! -d $(obj)nand_spl ] || find $(obj)nand_spl -name "*" -type l -print | xargs rm -f
CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT
This value denotes start offset of DSP CCSR space.
- CONFIG_SYS_FSL_DDR_EMU
- Specify emulator support for DDR. Some DDR features such as
- deskew training are not available.
-
- Generic CPU options:
CONFIG_SYS_BIG_ENDIAN, CONFIG_SYS_LITTLE_ENDIAN
Defines the endianess of the CPU. Implementation of those
values is arch specific.
+ CONFIG_SYS_FSL_DDR
+ Freescale DDR driver in use. This type of DDR controller is
+ found in mpc83xx, mpc85xx, mpc86xx as well as some ARM core
+ SoCs.
+
+ CONFIG_SYS_FSL_DDR_ADDR
+ Freescale DDR memory-mapped register base.
+
+ CONFIG_SYS_FSL_DDR_EMU
+ Specify emulator support for DDR. Some DDR features such as
+ deskew training are not available.
+
+ CONFIG_SYS_FSL_DDRC_GEN1
+ Freescale DDR1 controller.
+
+ CONFIG_SYS_FSL_DDRC_GEN2
+ Freescale DDR2 controller.
+
+ CONFIG_SYS_FSL_DDRC_GEN3
+ Freescale DDR3 controller.
+
+ CONFIG_SYS_FSL_DDRC_ARM_GEN3
+ Freescale DDR3 controller for ARM-based SoCs.
+
+ CONFIG_SYS_FSL_DDR1
+ Board config to use DDR1. It can be enabled for SoCs with
+ Freescale DDR1 or DDR2 controllers, depending on the board
+ implemetation.
+
+ CONFIG_SYS_FSL_DDR2
+ Board config to use DDR2. It can be eanbeld for SoCs with
+ Freescale DDR2 or DDR3 controllers, depending on the board
+ implementation.
+
+ CONFIG_SYS_FSL_DDR3
+ Board config to use DDR3. It can be enabled for SoCs with
+ Freescale DDR3 controllers.
+
- Intel Monahans options:
CONFIG_SYS_MONAHANS_RUN_MODE_OSC_RATIO
as a convenience, when switching between booting from
RAM and NFS.
+- Bootcount:
+ CONFIG_BOOTCOUNT_LIMIT
+ Implements a mechanism for detecting a repeating reboot
+ cycle, see:
+ http://www.denx.de/wiki/view/DULG/UBootBootCountLimit
+
+ CONFIG_BOOTCOUNT_ENV
+ If no softreset save registers are found on the hardware
+ "bootcount" is stored in the environment. To prevent a
+ saveenv on all reboots, the environment variable
+ "upgrade_available" is used. If "upgrade_available" is
+ 0, "bootcount" is always 0, if "upgrade_available" is
+ 1 "bootcount" is incremented in the environment.
+ So the Userspace Applikation must set the "upgrade_available"
+ and "bootcount" variable to 0, if a boot was successfully.
+
- Pre-Boot Commands:
CONFIG_PREBOOT
kernel). Defining CONFIG_STATUS_LED enables this
feature in U-Boot.
+ Additional options:
+
+ CONFIG_GPIO_LED
+ The status LED can be connected to a GPIO pin.
+ In such cases, the gpio_led driver can be used as a
+ status LED backend implementation. Define CONFIG_GPIO_LED
+ to include the gpio_led driver in the U-Boot binary.
+
+ CONFIG_GPIO_LED_INVERTED_TABLE
+ Some GPIO connected LEDs may have inverted polarity in which
+ case the GPIO high value corresponds to LED off state and
+ GPIO low value corresponds to LED on state.
+ In such cases CONFIG_GPIO_LED_INVERTED_TABLE may be defined
+ with a list of GPIO LEDs that have inverted polarity.
+
- CAN Support: CONFIG_CAN_DRIVER
Defining CONFIG_CAN_DRIVER enables CAN driver support
- CONFIG_SYS_RCAR_I2C3_SPEED for for the speed channel 3
- CONFIF_SYS_RCAR_I2C_NUM_CONTROLLERS for number of i2c buses
+ - drivers/i2c/sh_i2c.c:
+ - activate this driver with CONFIG_SYS_I2C_SH
+ - This driver adds from 2 to 5 i2c buses
+
+ - CONFIG_SYS_I2C_SH_BASE0 for setting the register channel 0
+ - CONFIG_SYS_I2C_SH_SPEED0 for for the speed channel 0
+ - CONFIG_SYS_I2C_SH_BASE1 for setting the register channel 1
+ - CONFIG_SYS_I2C_SH_SPEED1 for for the speed channel 1
+ - CONFIG_SYS_I2C_SH_BASE2 for setting the register channel 2
+ - CONFIG_SYS_I2C_SH_SPEED2 for for the speed channel 2
+ - CONFIG_SYS_I2C_SH_BASE3 for setting the register channel 3
+ - CONFIG_SYS_I2C_SH_SPEED3 for for the speed channel 3
+ - CONFIG_SYS_I2C_SH_BASE4 for setting the register channel 4
+ - CONFIG_SYS_I2C_SH_SPEED4 for for the speed channel 4
+ - CONFIG_SYS_I2C_SH_BASE5 for setting the register channel 5
+ - CONFIG_SYS_I2C_SH_SPEED5 for for the speed channel 5
+ - CONFIF_SYS_I2C_SH_NUM_CONTROLLERS for nummber of i2c buses
+
+ - drivers/i2c/omap24xx_i2c.c
+ - activate this driver with CONFIG_SYS_I2C_OMAP24XX
+ - CONFIG_SYS_OMAP24_I2C_SPEED speed channel 0
+ - CONFIG_SYS_OMAP24_I2C_SLAVE slave addr channel 0
+ - CONFIG_SYS_OMAP24_I2C_SPEED1 speed channel 1
+ - CONFIG_SYS_OMAP24_I2C_SLAVE1 slave addr channel 1
+ - CONFIG_SYS_OMAP24_I2C_SPEED2 speed channel 2
+ - CONFIG_SYS_OMAP24_I2C_SLAVE2 slave addr channel 2
+ - CONFIG_SYS_OMAP24_I2C_SPEED3 speed channel 3
+ - CONFIG_SYS_OMAP24_I2C_SLAVE3 slave addr channel 3
+ - CONFIG_SYS_OMAP24_I2C_SPEED4 speed channel 4
+ - CONFIG_SYS_OMAP24_I2C_SLAVE4 slave addr channel 4
+
+ - drivers/i2c/zynq_i2c.c
+ - activate this driver with CONFIG_SYS_I2C_ZYNQ
+ - set CONFIG_SYS_I2C_ZYNQ_SPEED for speed setting
+ - set CONFIG_SYS_I2C_ZYNQ_SLAVE for slave addr
+
additional defines:
CONFIG_SYS_NUM_I2C_BUSES
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
Set for the SPL on PPC mpc8xxx targets, support for
- arch/powerpc/cpu/mpc8xxx/ddr/libddr.o in SPL binary.
+ drivers/ddr/fsl/libddr.o in SPL binary.
CONFIG_SPL_COMMON_INIT_DDR
Set for common ddr init with serial presence detect in
NOTE : currently only supported on AM335x platforms.
+- CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC:
+ Enables the RTC32K OSC on AM33xx based plattforms
+
Freescale QE/FMAN Firmware Support:
-----------------------------------
obj-y += abb.o
endif
- COBJS += pipe3-phy.o
+ifneq ($(CONFIG_OMAP54XX),)
++obj-y += pipe3-phy.o
+obj-$(CONFIG_SCSI_AHCI_PLAT) += sata.o
+endif
+
ifeq ($(CONFIG_OMAP34XX),)
obj-y += boot-common.o
obj-y += lowlevel_init.o
sr32(&prcm_base->iclken_per, 17, 1, 1);
#endif
- #ifdef CONFIG_DRIVER_OMAP34XX_I2C
+ #ifdef CONFIG_SYS_I2C_OMAP34XX
/* Turn on all 3 I2C clocks */
sr32(&prcm_base->fclken1_core, 15, 3, 0x7);
sr32(&prcm_base->iclken1_core, 15, 3, 0x7); /* I2C1,2,3 = on */
sr32(&prcm_base->fclken_cam, 0, 32, FCK_CAM_ON);
sr32(&prcm_base->iclken_cam, 0, 32, ICK_CAM_ON);
}
- sr32(&prcm_base->fclken_per, 0, 32, FCK_PER_ON);
- sr32(&prcm_base->iclken_per, 0, 32, ICK_PER_ON);
sdelay(1000);
}
# SPDX-License-Identifier: GPL-2.0+
#
-obj-y = lowlevel_init.o
-obj-y += cpu_info.o
+obj-y = cpu_info.o
obj-y += emac.o
obj-$(CONFIG_DISPLAY_BOARDINFO) += board.o
obj-$(CONFIG_GLOBAL_TIMER) += timer.o
-obj-$(CONFIG_R8A7740) += cpu_info-r8a7740.o
-obj-$(CONFIG_R8A7740) += pfc-r8a7740.o
-obj-$(CONFIG_SH73A0) += cpu_info-sh73a0.o
-obj-$(CONFIG_SH73A0) += pfc-sh73a0.o
+obj-$(CONFIG_R8A7740) += lowlevel_init.o cpu_info-r8a7740.o pfc-r8a7740.o
+obj-$(CONFIG_R8A7790) += lowlevel_init_ca15.o cpu_info-r8a7790.o pfc-r8a7790.o
+obj-$(CONFIG_R8A7791) += lowlevel_init_ca15.o cpu_info-r8a7791.o pfc-r8a7791.o
+obj-$(CONFIG_SH73A0) += lowlevel_init.o cpu_info-sh73a0.o pfc-sh73a0.o
- obj-$(CONFIG_TMU_TIMER) += sh_timer.o
-
- SRCS += $(obj)sh_timer.c
- # from arch/sh/lib/ directory
- $(obj)sh_timer.c:
- @rm -f $(obj)sh_timer.c
- ln -s $(SRCTREE)/arch/sh/lib/time.c $(obj)sh_timer.c
+ obj-$(CONFIG_TMU_TIMER) += ../../../../sh/lib/time.o
.text : {
*(.__image_copy_start)
arch/arm/cpu/ixp/start.o(.text*)
- net/libnet.o(.text*)
- board/actux1/libactux1.o(.text*)
- arch/arm/cpu/ixp/libixp.o(.text*)
- drivers/input/libinput.o(.text*)
+ net/built-in.o(.text*)
+ board/actux1/built-in.o(.text*)
+ arch/arm/cpu/ixp/built-in.o(.text*)
+ drivers/input/built-in.o(.text*)
. = env_offset;
common/env_embedded.o(.ppcenv)
KEEP(*(.__bss_end));
}
- /DISCARD/ : { *(.dynsym) }
- /DISCARD/ : { *(.dynstr*) }
- /DISCARD/ : { *(.dynamic*) }
- /DISCARD/ : { *(.plt*) }
- /DISCARD/ : { *(.interp*) }
- /DISCARD/ : { *(.gnu*) }
+ .dynsym _end : { *(.dynsym) }
+ .dynbss : { *(.dynbss) }
+ .dynstr : { *(.dynstr*) }
+ .dynamic : { *(.dynamic*) }
+ .hash : { *(.hash*) }
+ .plt : { *(.plt*) }
+ .interp : { *(.interp*) }
+ .gnu : { *(.gnu*) }
+ .ARM.exidx : { *(.ARM.exidx*) }
}
.text : {
*(.__image_copy_start)
arch/arm/cpu/ixp/start.o(.text*)
- net/libnet.o(.text*)
- board/actux2/libactux2.o(.text*)
- arch/arm/cpu/ixp/libixp.o(.text*)
- drivers/input/libinput.o(.text*)
+ net/built-in.o(.text*)
+ board/actux2/built-in.o(.text*)
+ arch/arm/cpu/ixp/built-in.o(.text*)
+ drivers/input/built-in.o(.text*)
. = env_offset;
common/env_embedded.o(.ppcenv)
KEEP(*(.__bss_end));
}
- /DISCARD/ : { *(.dynsym) }
- /DISCARD/ : { *(.dynstr*) }
- /DISCARD/ : { *(.dynamic*) }
- /DISCARD/ : { *(.plt*) }
- /DISCARD/ : { *(.interp*) }
- /DISCARD/ : { *(.gnu*) }
+ .dynsym _end : { *(.dynsym) }
+ .dynbss : { *(.dynbss) }
+ .dynstr : { *(.dynstr*) }
+ .dynamic : { *(.dynamic*) }
+ .hash : { *(.hash*) }
+ .plt : { *(.plt*) }
+ .interp : { *(.interp*) }
+ .gnu : { *(.gnu*) }
+ .ARM.exidx : { *(.ARM.exidx*) }
}
.text : {
*(.__image_copy_start)
arch/arm/cpu/ixp/start.o(.text*)
- net/libnet.o(.text*)
- board/actux3/libactux3.o(.text*)
- arch/arm/cpu/ixp/libixp.o(.text*)
- drivers/input/libinput.o(.text*)
+ net/built-in.o(.text*)
+ board/actux3/built-in.o(.text*)
+ arch/arm/cpu/ixp/built-in.o(.text*)
+ drivers/input/built-in.o(.text*)
. = env_offset;
common/env_embedded.o(.ppcenv)
KEEP(*(.__bss_end));
}
- /DISCARD/ : { *(.dynsym) }
- /DISCARD/ : { *(.dynstr*) }
- /DISCARD/ : { *(.dynamic*) }
- /DISCARD/ : { *(.plt*) }
- /DISCARD/ : { *(.interp*) }
- /DISCARD/ : { *(.gnu*) }
+ .dynsym _end : { *(.dynsym) }
+ .dynbss : { *(.dynbss) }
+ .dynstr : { *(.dynstr*) }
+ .dynamic : { *(.dynamic*) }
+ .hash : { *(.hash*) }
+ .plt : { *(.plt*) }
+ .interp : { *(.interp*) }
+ .gnu : { *(.gnu*) }
+ .ARM.exidx : { *(.ARM.exidx*) }
}
#include <micrel.h>
#include <net.h>
#include <netdev.h>
+#include <spl.h>
+#include <asm/arch/atmel_mpddrc.h>
+#include <asm/arch/at91_wdt.h>
#ifdef CONFIG_USB_GADGET_ATMEL_USBA
#include <asm/arch/atmel_usba_udc.h>
void lcd_show_board_info(void)
{
- ulong dram_size, nand_size;
+ ulong dram_size;
+ uint64_t nand_size;
int i;
char temp[32];
for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
nand_size += nand_info[i].size;
#endif
- lcd_printf("%ld MB SDRAM, %ld MB NAND\n",
+ lcd_printf("%ld MB SDRAM, %lld MB NAND\n",
dram_size >> 20, nand_size >> 20);
}
#endif /* CONFIG_LCD_INFO */
int board_early_init_f(void)
{
+ at91_periph_clk_enable(ATMEL_ID_PIOA);
+ at91_periph_clk_enable(ATMEL_ID_PIOB);
+ at91_periph_clk_enable(ATMEL_ID_PIOC);
+ at91_periph_clk_enable(ATMEL_ID_PIOD);
+ at91_periph_clk_enable(ATMEL_ID_PIOE);
+
at91_seriald_hw_init();
return 0;
}
}
#endif /* CONFIG_ATMEL_SPI */
+
+/* SPL */
+#ifdef CONFIG_SPL_BUILD
+void spl_board_init(void)
+{
+#ifdef CONFIG_SYS_USE_MMC
+ sama5d3xek_mci_hw_init();
+#endif
+}
+
+static void ddr2_conf(struct atmel_mpddr *ddr2)
+{
+ ddr2->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM);
+
+ ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
+ ATMEL_MPDDRC_CR_NR_ROW_14 |
+ ATMEL_MPDDRC_CR_CAS_DDR_CAS3 |
+ ATMEL_MPDDRC_CR_ENRDM_ON |
+ ATMEL_MPDDRC_CR_NB_8BANKS |
+ ATMEL_MPDDRC_CR_NDQS_DISABLED |
+ ATMEL_MPDDRC_CR_DECOD_INTERLEAVED |
+ ATMEL_MPDDRC_CR_UNAL_SUPPORTED);
+ /*
+ * As the DDR2-SDRAm device requires a refresh time is 7.8125us
+ * when DDR run at 133MHz, so it needs (7.8125us * 133MHz / 10^9) clocks
+ */
+ ddr2->rtr = 0x411;
+
+ ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |
+ 2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |
+ 2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET |
+ 8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET |
+ 2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET |
+ 2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET |
+ 2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET |
+ 2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET);
+
+ ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET |
+ 200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET |
+ 28 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET |
+ 26 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET);
+
+ ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET |
+ 2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET |
+ 2 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET |
+ 7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET |
+ 8 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET);
+}
+
+void mem_init(void)
+{
+ struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+ struct atmel_mpddr ddr2;
+
+ ddr2_conf(&ddr2);
+
+ /* enable MPDDR clock */
+ at91_periph_clk_enable(ATMEL_ID_MPDDRC);
+ writel(0x4, &pmc->scer);
+
+ /* DDRAM2 Controller initialize */
+ ddr2_init(ATMEL_BASE_DDRCS, &ddr2);
+}
+
+void at91_pmc_init(void)
+{
+ struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+ u32 tmp;
+
+ tmp = AT91_PMC_PLLAR_29 |
+ AT91_PMC_PLLXR_PLLCOUNT(0x3f) |
+ AT91_PMC_PLLXR_MUL(43) |
+ AT91_PMC_PLLXR_DIV(1);
+ at91_plla_init(tmp);
+
+ writel(0x3 << 8, &pmc->pllicpr);
+
+ tmp = AT91_PMC_MCKR_MDIV_4 |
+ AT91_PMC_MCKR_CSS_PLLA;
+ at91_mck_init(tmp);
+}
+#endif
--- /dev/null
- board/compulab/cm_t335/libcm_t335.o (.text*)
+/*
+ * Copyright (c) 2004-2008 Texas Instruments
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+ . = 0x00000000;
+
+ . = ALIGN(4);
+ .text :
+ {
+ *(.__image_copy_start)
+ CPUDIR/start.o (.text*)
++ board/compulab/cm_t335/built-in.o (.text*)
+ *(.text*)
+ }
+
+ . = ALIGN(4);
+ .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
+
+ . = ALIGN(4);
+ .data : {
+ *(.data*)
+ }
+
+ . = ALIGN(4);
+
+ . = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ KEEP(*(SORT(.u_boot_list*)));
+ }
+
+ . = ALIGN(4);
+
+ .image_copy_end :
+ {
+ *(.__image_copy_end)
+ }
+
+ .rel_dyn_start :
+ {
+ *(.__rel_dyn_start)
+ }
+
+ .rel.dyn : {
+ *(.rel*)
+ }
+
+ .rel_dyn_end :
+ {
+ *(.__rel_dyn_end)
+ }
+
+ _end = .;
+
+ /*
+ * Deprecated: this MMU section is used by pxa at present but
+ * should not be used by new boards/CPUs.
+ */
+ . = ALIGN(4096);
+ .mmutable : {
+ *(.mmutable)
+ }
+
+/*
+ * Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c
+ * __bss_base and __bss_limit are for linker only (overlay ordering)
+ */
+
+ .bss_start __rel_dyn_start (OVERLAY) : {
+ KEEP(*(.__bss_start));
+ __bss_base = .;
+ }
+
+ .bss __bss_base (OVERLAY) : {
+ *(.bss*)
+ . = ALIGN(4);
+ __bss_limit = .;
+ }
+
+ .bss_end __bss_limit (OVERLAY) : {
+ KEEP(*(.__bss_end));
+ }
+
+ /DISCARD/ : { *(.dynsym) }
+ /DISCARD/ : { *(.dynstr*) }
+ /DISCARD/ : { *(.dynamic*) }
+ /DISCARD/ : { *(.plt*) }
+ /DISCARD/ : { *(.interp*) }
+ /DISCARD/ : { *(.gnu*) }
+}
.text : {
*(.__image_copy_start)
arch/arm/cpu/ixp/start.o(.text*)
- net/libnet.o(.text*)
- board/dvlhost/libdvlhost.o(.text*)
- arch/arm/cpu/ixp/libixp.o(.text*)
- drivers/serial/libserial.o(.text*)
+ net/built-in.o(.text*)
+ board/dvlhost/built-in.o(.text*)
+ arch/arm/cpu/ixp/built-in.o(.text*)
+ drivers/serial/built-in.o(.text*)
. = env_offset;
common/env_embedded.o(.ppcenv)
KEEP(*(.__bss_end));
}
- /DISCARD/ : { *(.dynsym) }
- /DISCARD/ : { *(.dynstr*) }
- /DISCARD/ : { *(.dynamic*) }
- /DISCARD/ : { *(.plt*) }
- /DISCARD/ : { *(.interp*) }
- /DISCARD/ : { *(.gnu*) }
+ .dynsym _end : { *(.dynsym) }
+ .dynbss : { *(.dynbss) }
+ .dynstr : { *(.dynstr*) }
+ .dynamic : { *(.dynamic*) }
+ .hash : { *(.hash*) }
+ .plt : { *(.plt*) }
+ .interp : { *(.interp*) }
+ .gnu : { *(.gnu*) }
+ .ARM.exidx : { *(.ARM.exidx*) }
}
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- arch/arm/cpu/arm1136/start.o (.text*)
- board/freescale/mx31ads/libmx31ads.o (.text*)
- arch/arm/lib/libarm.o (.text*)
- net/libnet.o (.text*)
- drivers/mtd/libmtd.o (.text*)
+ arch/arm/cpu/arm1136/start.o (.text*)
+ board/freescale/mx31ads/built-in.o (.text*)
+ arch/arm/lib/built-in.o (.text*)
+ net/built-in.o (.text*)
+ drivers/mtd/built-in.o (.text*)
. = DEFINED(env_offset) ? env_offset : .;
common/env_embedded.o(.text*)
KEEP(*(.__bss_end));
}
- /DISCARD/ : { *(.bss*) }
- /DISCARD/ : { *(.dynsym) }
- /DISCARD/ : { *(.dynstr*) }
- /DISCARD/ : { *(.dynsym*) }
- /DISCARD/ : { *(.dynamic*) }
- /DISCARD/ : { *(.hash*) }
- /DISCARD/ : { *(.plt*) }
- /DISCARD/ : { *(.interp*) }
- /DISCARD/ : { *(.gnu*) }
+ .dynsym _end : { *(.dynsym) }
+ .dynbss : { *(.dynbss) }
+ .dynstr : { *(.dynstr*) }
+ .dynamic : { *(.dynamic*) }
+ .hash : { *(.hash*) }
+ .plt : { *(.plt*) }
+ .interp : { *(.interp*) }
+ .gnu : { *(.gnu*) }
+ .ARM.exidx : { *(.ARM.exidx*) }
}
return &dpll_ddr;
}
+#ifdef CONFIG_REV1
static const struct ddr_data ddr3_data = {
.datardsratio0 = MT41J256M8HX15E_RD_DQS,
.datawdsratio0 = MT41J256M8HX15E_WR_DQS,
.datafwsratio0 = MT41J256M8HX15E_PHY_FIFO_WE,
.datawrsratio0 = MT41J256M8HX15E_PHY_WR_DATA,
- .datadldiff0 = PHY_DLL_LOCK_DIFF,
};
static const struct cmd_control ddr3_cmd_ctrl_data = {
.cmd0csratio = MT41J256M8HX15E_RATIO,
- .cmd0dldiff = MT41J256M8HX15E_DLL_LOCK_DIFF,
.cmd0iclkout = MT41J256M8HX15E_INVERT_CLKOUT,
.cmd1csratio = MT41J256M8HX15E_RATIO,
- .cmd1dldiff = MT41J256M8HX15E_DLL_LOCK_DIFF,
.cmd1iclkout = MT41J256M8HX15E_INVERT_CLKOUT,
.cmd2csratio = MT41J256M8HX15E_RATIO,
- .cmd2dldiff = MT41J256M8HX15E_DLL_LOCK_DIFF,
.cmd2iclkout = MT41J256M8HX15E_INVERT_CLKOUT,
};
PHY_EN_DYN_PWRDN,
};
+void sdram_init(void)
+{
+ config_ddr(DDR_CLK_MHZ, MT41J256M8HX15E_IOCTRL_VALUE, &ddr3_data,
+ &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
+}
+#else
+static const struct ddr_data ddr3_data = {
+ .datardsratio0 = MT41K256M16HA125E_RD_DQS,
+ .datawdsratio0 = MT41K256M16HA125E_WR_DQS,
+ .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
+ .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
+};
+
+static const struct cmd_control ddr3_cmd_ctrl_data = {
+ .cmd0csratio = MT41K256M16HA125E_RATIO,
+ .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
+
+ .cmd1csratio = MT41K256M16HA125E_RATIO,
+ .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
+
+ .cmd2csratio = MT41K256M16HA125E_RATIO,
+ .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
+};
+
+static struct emif_regs ddr3_emif_reg_data = {
+ .sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
+ .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
+ .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
+ .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
+ .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
+ .zq_config = MT41K256M16HA125E_ZQ_CFG,
+ .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY |
+ PHY_EN_DYN_PWRDN,
+};
+
+void sdram_init(void)
+{
+ config_ddr(DDR_CLK_MHZ, MT41K256M16HA125E_IOCTRL_VALUE, &ddr3_data,
+ &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
+}
+#endif
+
void set_uart_mux_conf(void)
{
enable_uart0_pin_mux();
{
/* Initalize the board header */
enable_i2c0_pin_mux();
- i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+ i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
enable_board_pin_mux();
}
-
-void sdram_init(void)
-{
- config_ddr(DDR_CLK_MHZ, MT41J256M8HX15E_IOCTRL_VALUE, &ddr3_data,
- &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
-}
#endif
/*
*/
int board_init(void)
{
- i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+ i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
(MT47H128M16RT25E_PHY_WR_DATA<<20) |
(MT47H128M16RT25E_PHY_WR_DATA<<10) |
(MT47H128M16RT25E_PHY_WR_DATA<<0)),
- .datauserank0delay = MT47H128M16RT25E_PHY_RANK0_DELAY,
- .datadldiff0 = PHY_DLL_LOCK_DIFF,
};
static const struct cmd_control ddr2_cmd_ctrl_data = {
.cmd0csratio = MT47H128M16RT25E_RATIO,
- .cmd0dldiff = MT47H128M16RT25E_DLL_LOCK_DIFF,
.cmd0iclkout = MT47H128M16RT25E_INVERT_CLKOUT,
.cmd1csratio = MT47H128M16RT25E_RATIO,
- .cmd1dldiff = MT47H128M16RT25E_DLL_LOCK_DIFF,
.cmd1iclkout = MT47H128M16RT25E_INVERT_CLKOUT,
.cmd2csratio = MT47H128M16RT25E_RATIO,
- .cmd2dldiff = MT47H128M16RT25E_DLL_LOCK_DIFF,
.cmd2iclkout = MT47H128M16RT25E_INVERT_CLKOUT,
};
.datawdsratio0 = MT41J128MJT125_WR_DQS,
.datafwsratio0 = MT41J128MJT125_PHY_FIFO_WE,
.datawrsratio0 = MT41J128MJT125_PHY_WR_DATA,
- .datadldiff0 = PHY_DLL_LOCK_DIFF,
};
static const struct ddr_data ddr3_beagleblack_data = {
.datawdsratio0 = MT41K256M16HA125E_WR_DQS,
.datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
.datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
- .datadldiff0 = PHY_DLL_LOCK_DIFF,
};
static const struct ddr_data ddr3_evm_data = {
.datawdsratio0 = MT41J512M8RH125_WR_DQS,
.datafwsratio0 = MT41J512M8RH125_PHY_FIFO_WE,
.datawrsratio0 = MT41J512M8RH125_PHY_WR_DATA,
- .datadldiff0 = PHY_DLL_LOCK_DIFF,
};
static const struct cmd_control ddr3_cmd_ctrl_data = {
.cmd0csratio = MT41J128MJT125_RATIO,
- .cmd0dldiff = MT41J128MJT125_DLL_LOCK_DIFF,
.cmd0iclkout = MT41J128MJT125_INVERT_CLKOUT,
.cmd1csratio = MT41J128MJT125_RATIO,
- .cmd1dldiff = MT41J128MJT125_DLL_LOCK_DIFF,
.cmd1iclkout = MT41J128MJT125_INVERT_CLKOUT,
.cmd2csratio = MT41J128MJT125_RATIO,
- .cmd2dldiff = MT41J128MJT125_DLL_LOCK_DIFF,
.cmd2iclkout = MT41J128MJT125_INVERT_CLKOUT,
};
static const struct cmd_control ddr3_beagleblack_cmd_ctrl_data = {
.cmd0csratio = MT41K256M16HA125E_RATIO,
- .cmd0dldiff = MT41K256M16HA125E_DLL_LOCK_DIFF,
.cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
.cmd1csratio = MT41K256M16HA125E_RATIO,
- .cmd1dldiff = MT41K256M16HA125E_DLL_LOCK_DIFF,
.cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
.cmd2csratio = MT41K256M16HA125E_RATIO,
- .cmd2dldiff = MT41K256M16HA125E_DLL_LOCK_DIFF,
.cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
};
static const struct cmd_control ddr3_evm_cmd_ctrl_data = {
.cmd0csratio = MT41J512M8RH125_RATIO,
- .cmd0dldiff = MT41J512M8RH125_DLL_LOCK_DIFF,
.cmd0iclkout = MT41J512M8RH125_INVERT_CLKOUT,
.cmd1csratio = MT41J512M8RH125_RATIO,
- .cmd1dldiff = MT41J512M8RH125_DLL_LOCK_DIFF,
.cmd1iclkout = MT41J512M8RH125_INVERT_CLKOUT,
.cmd2csratio = MT41J512M8RH125_RATIO,
- .cmd2dldiff = MT41J512M8RH125_DLL_LOCK_DIFF,
.cmd2iclkout = MT41J512M8RH125_INVERT_CLKOUT,
};
struct am335x_baseboard_id header;
enable_i2c0_pin_mux();
- i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+ i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
if (read_eeprom(&header) < 0)
puts("Could not get board ID.\n");
*/
int board_init(void)
{
- #ifdef CONFIG_NOR
- const u32 gpmc_nor[GPMC_MAX_REG] = { STNOR_GPMC_CONFIG1,
- STNOR_GPMC_CONFIG2, STNOR_GPMC_CONFIG3, STNOR_GPMC_CONFIG4,
- STNOR_GPMC_CONFIG5, STNOR_GPMC_CONFIG6, STNOR_GPMC_CONFIG7 };
- #endif
-
#if defined(CONFIG_HW_WATCHDOG)
hw_watchdog_init();
#endif
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
-
+ #if defined(CONFIG_NOR) || defined(CONFIG_NAND)
gpmc_init();
-
- #ifdef CONFIG_NOR
- /* Reconfigure CS0 for NOR instead of NAND. */
- enable_gpmc_cs_config(gpmc_nor, &gpmc_cfg->cs[0],
- CONFIG_SYS_FLASH_BASE, GPMC_SIZE_16M);
#endif
-
return 0;
}
{
*(.__image_copy_start)
CPUDIR/start.o (.text*)
- board/ti/am335x/libam335x.o (.text*)
+ board/ti/am335x/built-in.o (.text*)
*(.text*)
}
KEEP(*(.__bss_end));
}
- /DISCARD/ : { *(.dynsym) }
- /DISCARD/ : { *(.dynstr*) }
- /DISCARD/ : { *(.dynamic*) }
- /DISCARD/ : { *(.plt*) }
- /DISCARD/ : { *(.interp*) }
- /DISCARD/ : { *(.gnu*) }
+ .dynsym _end : { *(.dynsym) }
+ .dynbss : { *(.dynbss) }
+ .dynstr : { *(.dynstr*) }
+ .dynamic : { *(.dynamic*) }
+ .hash : { *(.hash*) }
+ .plt : { *(.plt*) }
+ .interp : { *(.interp*) }
+ .gnu : { *(.gnu*) }
+ .ARM.exidx : { *(.ARM.exidx*) }
}
.text.0 :
{
arch/arm/cpu/pxa/start.o (.text*)
- board/vpac270/libvpac270.o (.text*)
- drivers/mtd/onenand/libonenand.o (.text*)
+ board/vpac270/built-in.o (.text*)
+ drivers/mtd/onenand/built-in.o (.text*)
}
__bss_end = .;
}
- /DISCARD/ : { *(.bss*) }
- /DISCARD/ : { *(.dynsym) }
- /DISCARD/ : { *(.dynstr*) }
- /DISCARD/ : { *(.dynsym*) }
- /DISCARD/ : { *(.dynamic*) }
- /DISCARD/ : { *(.hash*) }
- /DISCARD/ : { *(.plt*) }
- /DISCARD/ : { *(.interp*) }
- /DISCARD/ : { *(.gnu*) }
+ .dynsym _end : { *(.dynsym) }
+ .dynbss : { *(.dynbss) }
+ .dynstr : { *(.dynstr*) }
+ .dynamic : { *(.dynamic*) }
+ .hash : { *(.hash*) }
+ .plt : { *(.plt*) }
+ .interp : { *(.interp*) }
+ .gnu : { *(.gnu*) }
+ .ARM.exidx : { *(.ARM.exidx*) }
}
Active arm arm926ejs at91 calao tny_a9260 tny_a9260_nandflash tny_a9260:AT91SAM9260,SYS_USE_NANDFLASH Albin Tonnerre <albin.tonnerre@free-electrons.com>
Active arm arm926ejs at91 calao tny_a9260 tny_a9g20_eeprom tny_a9260:AT91SAM9G20,SYS_USE_EEPROM Albin Tonnerre <albin.tonnerre@free-electrons.com>
Active arm arm926ejs at91 calao tny_a9260 tny_a9g20_nandflash tny_a9260:AT91SAM9G20,SYS_USE_NANDFLASH Albin Tonnerre <albin.tonnerre@free-electrons.com>
+Active arm arm926ejs at91 calao usb_a9263 usb_a9263_dataflash usb_a9263:AT91SAM9263,SYS_USE_DATAFLASH Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
Active arm arm926ejs at91 egnite ethernut5 ethernut5 ethernut5:AT91SAM9XE egnite GmbH <info@egnite.de>
Active arm arm926ejs at91 emk top9000 top9000eval_xe top9000:EVAL9000 Reinhard Meyer <reinhard.meyer@emk-elektronik.de>
Active arm arm926ejs at91 emk top9000 top9000su_xe top9000:SU9000 Reinhard Meyer <reinhard.meyer@emk-elektronik.de>
Active arm arm926ejs at91 ronetix pm9g45 pm9g45 pm9g45:AT91SAM9G45 Ilko Iliev <iliev@ronetix.at>
Active arm arm926ejs at91 taskit stamp9g20 portuxg20 stamp9g20:AT91SAM9G20,PORTUXG20 Markus Hubig <mhubig@imko.de>
Active arm arm926ejs at91 taskit stamp9g20 stamp9g20 stamp9g20:AT91SAM9G20 Markus Hubig <mhubig@imko.de>
+Active arm arm926ejs at91 siemens taurus axm taurus:AT91SAM9G20,MACH_TYPE=2068,BOARD_AXM Heiko Schocher <hs@denx.de>
+Active arm arm926ejs at91 siemens corvus corvus corvus:AT91SAM9M10G45,SYS_USE_NANDFLASH Heiko Schocher <hs@denx.de>
+Active arm arm926ejs at91 siemens taurus taurus taurus:AT91SAM9G20,MACH_TYPE=2067,BOARD_TAURUS Heiko Schocher <hs@denx.de>
Active arm arm926ejs davinci ait cam_enc_4xx cam_enc_4xx cam_enc_4xx Heiko Schocher <hs@denx.de>
Active arm arm926ejs davinci Barix ipam390 ipam390 - Heiko Schocher <hs@denx.de>
Active arm arm926ejs davinci davinci da8xxevm da830evm - Nick Thompson <nick.thompson@gefanuc.com>
Active arm arm926ejs nomadik st nhk8815 nhk8815 - Nomadik Linux Team <STN_WMM_nomadik_linux@list.st.com>:Alessandro Rubini <rubini@unipv.it>
Active arm arm926ejs nomadik st nhk8815 nhk8815_onenand nhk8815:BOOT_ONENAND Nomadik Linux Team <STN_WMM_nomadik_linux@list.st.com>:Alessandro Rubini <rubini@unipv.it>
Active arm arm926ejs omap ti - omap5912osk - Rishi Bhattacharya <rishi@ti.com>
-Active arm arm926ejs omap ti omap730p2 omap730p2 omap730p2:CS3_BOOT Dave Peverley <dpeverley@mpc-data.co.uk>
-Active arm arm926ejs omap ti omap730p2 omap730p2_cs0boot omap730p2:CS0_BOOT Dave Peverley <dpeverley@mpc-data.co.uk>
-Active arm arm926ejs omap ti omap730p2 omap730p2_cs3boot omap730p2:CS3_BOOT Dave Peverley <dpeverley@mpc-data.co.uk>
Active arm arm926ejs orion5x LaCie - edminiv2 - Albert ARIBAUD <albert.u.boot@aribaud.net>
Active arm arm926ejs pantheon Marvell - dkb - Lei Wen <leiwen@marvell.com>
Active arm arm926ejs spear spear - x600 x600 Stefan Roese <sr@denx.de>
Active arm armv7 - armltd vexpress vexpress_ca15_tc2 - -
Active arm armv7 - armltd vexpress vexpress_ca5x2 - Matt Waddel <matt.waddel@linaro.org>
Active arm armv7 - armltd vexpress vexpress_ca9x4 - Matt Waddel <matt.waddel@linaro.org>
+Active arm armv7 am33xx compulab cm_t335 cm_t335 cm_t335 Igor Grinberg <grinberg@compulab.co.il>
Active arm armv7 am33xx isee igep0033 am335x_igep0033 - Enric Balletbo i Serra <eballetbo@iseebcn.com>
-Active arm armv7 am33xx phytec pcm051 pcm051 pcm051 Lars Poeschel <poeschel@lemonage.de>
+Active arm armv7 am33xx phytec pcm051 pcm051_rev1 pcm051:REV1 Lars Poeschel <poeschel@lemonage.de>
+Active arm armv7 am33xx phytec pcm051 pcm051_rev3 pcm051:REV3 Lars Poeschel <poeschel@lemonage.de>
Active arm armv7 am33xx siemens dxr2 dxr2 - Roger Meier <r.meier@siemens.com>
Active arm armv7 am33xx siemens pxm2 pxm2 - Roger Meier <r.meier@siemens.com>
Active arm armv7 am33xx siemens rut rut - Roger Meier <r.meier@siemens.com>
Active arm armv7 am33xx ti am335x am335x_evm_nor am335x_evm:SERIAL1,CONS_INDEX=1,NAND,NOR Tom Rini <trini@ti.com>
Active arm armv7 am33xx ti am335x am335x_evm_norboot am335x_evm:SERIAL1,CONS_INDEX=1,NOR,NOR_BOOT Tom Rini <trini@ti.com>
Active arm armv7 am33xx ti am335x am335x_evm_spiboot am335x_evm:SERIAL1,CONS_INDEX=1,SPI_BOOT Tom Rini <trini@ti.com>
-Active arm armv7 am33xx ti am335x am335x_evm_uart1 am335x_evm:SERIAL2,CONS_INDEX=1,NAND Tom Rini <trini@ti.com>
-Active arm armv7 am33xx ti am335x am335x_evm_uart2 am335x_evm:SERIAL3,CONS_INDEX=1,NAND Tom Rini <trini@ti.com>
-Active arm armv7 am33xx ti am335x am335x_evm_uart3 am335x_evm:SERIAL4,CONS_INDEX=1,NAND Tom Rini <trini@ti.com>
-Active arm armv7 am33xx ti am335x am335x_evm_uart4 am335x_evm:SERIAL5,CONS_INDEX=1,NAND Tom Rini <trini@ti.com>
-Active arm armv7 am33xx ti am335x am335x_evm_uart5 am335x_evm:SERIAL6,CONS_INDEX=1,NAND Tom Rini <trini@ti.com>
+Active arm armv7 am33xx ti am335x am335x_evm_uart1 am335x_evm:SERIAL2,CONS_INDEX=2,NAND Tom Rini <trini@ti.com>
+Active arm armv7 am33xx ti am335x am335x_evm_uart2 am335x_evm:SERIAL3,CONS_INDEX=3,NAND Tom Rini <trini@ti.com>
+Active arm armv7 am33xx ti am335x am335x_evm_uart3 am335x_evm:SERIAL4,CONS_INDEX=4,NAND Tom Rini <trini@ti.com>
+Active arm armv7 am33xx ti am335x am335x_evm_uart4 am335x_evm:SERIAL5,CONS_INDEX=5,NAND Tom Rini <trini@ti.com>
+Active arm armv7 am33xx ti am335x am335x_evm_uart5 am335x_evm:SERIAL6,CONS_INDEX=6,NAND Tom Rini <trini@ti.com>
Active arm armv7 am33xx ti am335x am335x_evm_usbspl am335x_evm:SERIAL1,CONS_INDEX=1,NAND,SPL_USBETH_SUPPORT Tom Rini <trini@ti.com>
Active arm armv7 am33xx ti am43xx am43xx_evm am43xx_evm:SERIAL1,CONS_INDEX=1 -
-Active arm armv7 am33xx ti ti814x ti814x_evm - Matt Porter <mporter@ti.com>
+Active arm armv7 am33xx ti ti814x ti814x_evm - Matt Porter <matt.porter@linaro.org>
Active arm armv7 am33xx ti ti816x ti816x_evm - -
Active arm armv7 at91 atmel sama5d3xek sama5d3xek_mmc sama5d3xek:SAMA5D3,SYS_USE_MMC Bo Shen <voice.shen@atmel.com>
Active arm armv7 at91 atmel sama5d3xek sama5d3xek_nandflash sama5d3xek:SAMA5D3,SYS_USE_NANDFLASH Bo Shen <voice.shen@atmel.com>
Active arm armv7 omap5 ti omap5_uevm omap5_uevm - -
Active arm armv7 rmobile atmark-techno armadillo-800eva armadillo-800eva - Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Active arm armv7 rmobile kmc kzm9g kzm9g - Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>:Tetsuyuki Kobayashi <koba@kmckk.co.jp>
+Active arm armv7 rmobile renesas lager lager - Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
+Active arm armv7 rmobile renesas lager lager_nor lager:NORFLASH Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
+Active arm armv7 rmobile renesas koelsch koelsch - Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
+Active arm armv7 rmobile renesas koelsch koelsch_nor koelsch:NORFLASH Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Active arm armv7 s5pc1xx samsung goni s5p_goni - Minkyu Kang <mk7.kang@samsung.com>
Active arm armv7 s5pc1xx samsung smdkc100 smdkc100 - Minkyu Kang <mk7.kang@samsung.com>
Active arm armv7 socfpga altera socfpga socfpga_cyclone5 - -
Active m68k mcf547x_8x - freescale m548xevb M5485GFE M5485EVB:SYS_BUSCLK=100000000,SYS_BOOTSZ=4,SYS_DRAMSZ=64 TsiChung Liew <Tsi-Chung.Liew@freescale.com>
Active m68k mcf547x_8x - freescale m548xevb M5485HFE M5485EVB:SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=16,SYS_VIDEO TsiChung Liew <Tsi-Chung.Liew@freescale.com>
Active microblaze microblaze - xilinx microblaze-generic microblaze-generic - Michal Simek <monstr@monstr.eu>
- Active mips mips32 - - qemu-malta qemu_malta qemu-malta:MIPS32,SYS_BIG_ENDIAN -
- Active mips mips32 - - qemu-malta qemu_maltael qemu-malta:MIPS32,SYS_LITTLE_ENDIAN -
Active mips mips32 - - qemu-mips qemu_mips qemu-mips:SYS_BIG_ENDIAN Vlad Lungu <vlad.lungu@windriver.com>
Active mips mips32 - - qemu-mips qemu_mipsel qemu-mips:SYS_LITTLE_ENDIAN -
+ Active mips mips32 - imgtec malta malta malta:MIPS32,SYS_BIG_ENDIAN Paul Burton <paul.burton@imgtec.com>
+ Active mips mips32 - imgtec malta maltael malta:MIPS32,SYS_LITTLE_ENDIAN Paul Burton <paul.burton@imgtec.com>
Active mips mips32 - micronas vct vct_platinum vct:VCT_PLATINUM -
Active mips mips32 - micronas vct vct_platinum_onenand vct:VCT_PLATINUM,VCT_ONENAND -
Active mips mips32 - micronas vct vct_platinum_onenand_small vct:VCT_PLATINUM,VCT_ONENAND,VCT_SMALL_IMAGE -
Active powerpc mpc824x - - linkstation linkstation_HGLAN linkstation:HGLAN=1 Guennadi Liakhovetski <g.liakhovetski@gmx.de>
Active powerpc mpc824x - - musenki MUSENKI - Jim Thompson <jim@musenki.com>
Active powerpc mpc824x - - mvblue MVBLUE - -
- Active powerpc mpc824x - - pn62 PN62 - Wolfgang Grandegger <wg@denx.de>
Active powerpc mpc824x - - sandpoint Sandpoint8240 - Wolfgang Denk <wd@denx.de>
Active powerpc mpc824x - - sandpoint Sandpoint8245 - Jim Thompson <jim@musenki.com>
Active powerpc mpc824x - etin - debris - Sangmoon Kim <dogoil@etinsys.com>
Active powerpc mpc85xx - freescale t4qds T4240QDS_SDCARD T4240QDS:PPC_T4240,RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000 -
Active powerpc mpc85xx - freescale t4qds T4240QDS_SPIFLASH T4240QDS:PPC_T4240,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000 -
Active powerpc mpc85xx - freescale t4qds T4240QDS_SRIO_PCIE_BOOT T4240QDS:PPC_T4240,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF80000 -
- Active powerpc mpc85xx - freescale t1040qds T1040QDS T1040QDS:PPC_T1040 Naveen Burmi <NaveenBurmi@freescale.com>
+ Active powerpc mpc85xx - freescale t1040qds T1040QDS T1040QDS:PPC_T1040 Poonam Aggrwal <poonam.aggrwal@freescale.com>
+ Active powerpc mpc85xx - freescale t104xrdb T1040RDB T1040RDB:PPC_T1040 Poonam Aggrwal <poonam.aggrwal@freescale.com>
+ Active powerpc mpc85xx - freescale t104xrdb T1042RDB_PI T1042RDB_PI:PPC_T1042 Poonam Aggrwal <poonam.aggrwal@freescale.com>
+ Active powerpc mpc85xx - freescale t2080qds T2080QDS T2080QDS:PPC_T2080
+ Active powerpc mpc85xx - freescale t2080qds T2080QDS_SDCARD T2080QDS:PPC_T2080,RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000
+ Active powerpc mpc85xx - freescale t2080qds T2080QDS_SPIFLASH T2080QDS:PPC_T2080,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000
+ Active powerpc mpc85xx - freescale t2080qds T2080QDS_NAND T2080QDS:PPC_T2080,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000
+ Active powerpc mpc85xx - freescale t2080qds T2080QDS_SRIO_PCIE_BOOT T2080QDS:PPC_T2080,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF80000
Active powerpc mpc85xx - gdsys p1022 controlcenterd_36BIT_SDCARD controlcenterd:36BIT,SDCARD Dirk Eibach <eibach@gdsys.de>
Active powerpc mpc85xx - gdsys p1022 controlcenterd_36BIT_SDCARD_DEVELOP controlcenterd:36BIT,SDCARD,DEVELOP Dirk Eibach <eibach@gdsys.de>
Active powerpc mpc85xx - gdsys p1022 controlcenterd_TRAILBLAZER controlcenterd:TRAILBLAZER,SPIFLASH Dirk Eibach <eibach@gdsys.de>
Board Arch CPU Commit Removed Last known maintainer/contact
=================================================================================================
-pdnb3 arm ixp - 2013-09-24 Stefan Roese <sr@denx.de>
-scpu arm ixp - 2013-09-24 Stefan Roese <sr@denx.de>
+omap730p2 arm arm926ejs - 2013-11-11
+ pn62 powerpc mpc824x - 2013-11-11 Wolfgang Grandegger <wg@grandegger.com>
+pdnb3 arm ixp 304db0b 2013-09-24 Stefan Roese <sr@denx.de>
+scpu arm ixp 304db0b 2013-09-24 Stefan Roese <sr@denx.de>
omap1510inn arm arm925t 0610a16 2013-09-23 Kshitij Gupta <kshitij@ti.com>
CANBT powerpc 405CR fb8f4fd 2013-08-07 Matthias Fuchs <matthias.fuchs@esd.eu>
Alaska8220 powerpc mpc8220 d6ed322 2013-05-11
PCIPPC2 powerpc MPC740/MPC750 7c9e89b 2013-02-07 Wolfgang Denk <wd@denx.de>
PCIPPC6 powerpc MPC740/MPC750 - - Wolfgang Denk <wd@denx.de>
omap2420h4 arm omap24xx - 2013-06-04 Richard Woodruff <r-woodruff2@ti.com>
+ eNET x86 x86 7e8c53d 2013-02-14 Graeme Russ <graeme.russ@gmail.com>
*/
#include <common.h>
-#include <asm/arch/hardware.h>
+#include <asm/gpio.h>
#include <asm/arch/gpio.h>
-#include <asm/arch/at91_pio.h>
#include <malloc.h>
#include <nand.h>
}
if (!timeout) {
- printk(KERN_ERR "atmel_nand : Timeout to calculate PMECC error location\n");
+ dev_err(host->dev, "atmel_nand : Timeout to calculate PMECC error location\n");
return -1;
}
*(buf + byte_pos) ^= (1 << bit_pos);
pos = sector_num * host->pmecc_sector_size + byte_pos;
- printk(KERN_INFO "Bit flip in data area, byte_pos: %d, bit_pos: %d, 0x%02x -> 0x%02x\n",
+ dev_dbg(host->dev, "Bit flip in data area, byte_pos: %d, bit_pos: %d, 0x%02x -> 0x%02x\n",
pos, bit_pos, err_byte, *(buf + byte_pos));
} else {
/* Bit flip in OOB area */
ecc[tmp] ^= (1 << bit_pos);
pos = tmp + nand_chip->ecc.layout->eccpos[0];
- printk(KERN_INFO "Bit flip in OOB, oob_byte_pos: %d, bit_pos: %d, 0x%02x -> 0x%02x\n",
+ dev_dbg(host->dev, "Bit flip in OOB, oob_byte_pos: %d, bit_pos: %d, 0x%02x -> 0x%02x\n",
pos, bit_pos, err_byte, ecc[tmp]);
}
err_nbr = pmecc_err_location(mtd);
if (err_nbr == -1) {
- printk(KERN_ERR "PMECC: Too many errors\n");
+ dev_err(host->dev, "PMECC: Too many errors\n");
mtd->ecc_stats.failed++;
return -EIO;
} else {
}
if (!timeout) {
- printk(KERN_ERR "atmel_nand : Timeout to read PMECC page\n");
+ dev_err(host->dev, "atmel_nand : Timeout to read PMECC page\n");
return -1;
}
}
if (!timeout) {
- printk(KERN_ERR "atmel_nand : Timeout to read PMECC status, fail to write PMECC in oob\n");
+ dev_err(host->dev, "atmel_nand : Timeout to read PMECC status, fail to write PMECC in oob\n");
goto out;
}
switch (mtd->writesize) {
case 2048:
case 4096:
+ case 8192:
host->pmecc_degree = (sector_size == 512) ?
PMECC_GF_DIMENSION_13 : PMECC_GF_DIMENSION_14;
host->pmecc_cw_len = (1 << host->pmecc_degree) - 1;
nand->ecc.steps = 1;
nand->ecc.bytes = host->pmecc_bytes_per_sector *
host->pmecc_sector_number;
+
+ if (nand->ecc.bytes > MTD_MAX_ECCPOS_ENTRIES_LARGE) {
+ dev_err(host->dev, "too large eccpos entries. max support ecc.bytes is %d\n",
+ MTD_MAX_ECCPOS_ENTRIES_LARGE);
+ return -EINVAL;
+ }
+
if (nand->ecc.bytes > mtd->oobsize - 2) {
- printk(KERN_ERR "No room for ECC bytes\n");
+ dev_err(host->dev, "No room for ECC bytes\n");
return -EINVAL;
}
pmecc_config_ecc_layout(&atmel_pmecc_oobinfo,
case 512:
case 1024:
/* TODO */
- printk(KERN_ERR "Unsupported page size for PMECC, use Software ECC\n");
+ dev_err(host->dev, "Unsupported page size for PMECC, use Software ECC\n");
default:
/* page size not handled by HW ECC */
/* switching back to soft ECC */
/* it doesn't seems to be a freshly
* erased block.
* We can't correct so many errors */
- printk(KERN_WARNING "atmel_nand : multiple errors detected."
+ dev_warn(host->dev, "atmel_nand : multiple errors detected."
" Unable to correct.\n");
return -EIO;
}
/* there's nothing much to do here.
* the bit error is on the ECC itself.
*/
- printk(KERN_WARNING "atmel_nand : one bit error on ECC code."
+ dev_warn(host->dev, "atmel_nand : one bit error on ECC code."
" Nothing to correct\n");
return 0;
}
- printk(KERN_WARNING "atmel_nand : one bit error on data."
+ dev_warn(host->dev, "atmel_nand : one bit error on data."
" (word offset in the page :"
" 0x%x bit offset : 0x%x)\n",
ecc_word, ecc_bit);
/* 8 bits words */
dat[ecc_word] ^= (1 << ecc_bit);
}
- printk(KERN_WARNING "atmel_nand : error corrected\n");
+ dev_warn(host->dev, "atmel_nand : error corrected\n");
return 1;
}
IO_ADDR_W |= CONFIG_SYS_NAND_MASK_ALE;
#ifdef CONFIG_SYS_NAND_ENABLE_PIN
- at91_set_gpio_value(CONFIG_SYS_NAND_ENABLE_PIN,
- !(ctrl & NAND_NCE));
+ gpio_set_value(CONFIG_SYS_NAND_ENABLE_PIN, !(ctrl & NAND_NCE));
#endif
this->IO_ADDR_W = (void *) IO_ADDR_W;
}
#ifdef CONFIG_SYS_NAND_READY_PIN
static int at91_nand_ready(struct mtd_info *mtd)
{
- return at91_get_gpio_value(CONFIG_SYS_NAND_READY_PIN);
+ return gpio_get_value(CONFIG_SYS_NAND_READY_PIN);
}
#endif
mtd->priv = nand;
nand->IO_ADDR_R = nand->IO_ADDR_W = (void __iomem *)base_addr;
+ #ifdef CONFIG_NAND_ECC_BCH
+ nand->ecc.mode = NAND_ECC_SOFT_BCH;
+ #else
nand->ecc.mode = NAND_ECC_SOFT;
+ #endif
#ifdef CONFIG_SYS_NAND_DBW_16
nand->options = NAND_BUSWIDTH_16;
#endif
#ifdef CONFIG_SYS_NAND_READY_PIN
nand->dev_ready = at91_nand_ready;
#endif
- nand->chip_delay = 20;
+ nand->chip_delay = 75;
ret = nand_scan_ident(mtd, CONFIG_SYS_NAND_MAX_CHIPS, NULL);
if (ret)
int i;
for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
if (atmel_nand_chip_init(i, base_addr[i]))
- printk(KERN_ERR "atmel_nand: Fail to initialize #%d chip",
+ dev_err(host->dev, "atmel_nand: Fail to initialize #%d chip",
i);
}
"dfu_alt_info_nand=" DFU_ALT_INFO_NAND "\0" \
"nandroot=ubi0:rootfs rw ubi.mtd=7,2048\0" \
"nandrootfstype=ubifs rootwait=1\0" \
- "nandsrcaddr=0x280000\0" \
- "nandboot=echo Booting from nand ...; " \
+ "nandboot=echo Booting from nand ...; " \
"run nandargs; " \
- "nand read ${loadaddr} ${nandsrcaddr} ${nandimgsize}; " \
- "bootz ${loadaddr}\0" \
- "nandimgsize=0x500000\0"
+ "nand read ${fdtaddr} u-boot-spl-os; " \
+ "nand read ${loadaddr} kernel; " \
+ "bootz ${loadaddr} - ${fdtaddr}\0"
#else
#define NANDARGS ""
#endif
#define CONFIG_SYS_NS16550_COM6 0x481aa000 /* UART5 */
#define CONFIG_BAUDRATE 115200
- /* I2C Configuration */
#define CONFIG_CMD_EEPROM
#define CONFIG_ENV_EEPROM_IS_ON_I2C
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */
#define CONFIG_SPL_POWER_SUPPORT
#define CONFIG_SPL_YMODEM_SUPPORT
+/* Bootcount using the RTC block */
+#define CONFIG_BOOTCOUNT_LIMIT
+#define CONFIG_BOOTCOUNT_AM33XX
+
/* CPSW support */
#define CONFIG_SPL_ETH_SUPPORT
#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/am33xx/u-boot-spl.lds"
#ifdef CONFIG_NAND
+ #define CONFIG_NAND_OMAP_GPMC
+ #define CONFIG_NAND_OMAP_ELM
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
CONFIG_SYS_NAND_PAGE_SIZE)
#define CONFIG_SYS_NAND_ECCSIZE 512
#define CONFIG_SYS_NAND_ECCBYTES 14
-
+ #define CONFIG_SYS_NAND_ONFI_DETECTION
+ #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW
#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
#endif
#undef CONFIG_CMD_IMLS /* List all found images */
#define CONFIG_SYS_NO_FLASH
- #define CONFIG_HARD_I2C 1
- #define CONFIG_SYS_I2C_SPEED 100000
- #define CONFIG_SYS_I2C_SLAVE 1
- #define CONFIG_DRIVER_OMAP34XX_I2C 1
+ #define CONFIG_SYS_I2C
+ #define CONFIG_SYS_OMAP24_I2C_SPEED 100000
+ #define CONFIG_SYS_OMAP24_I2C_SLAVE 1
+ #define CONFIG_SYS_I2C_OMAP34XX
-#undef CONFIG_CMD_NET
-#undef CONFIG_CMD_NFS
+/*
+ * Ethernet
+ */
+#define CONFIG_DRIVER_TI_EMAC
+#define CONFIG_DRIVER_TI_EMAC_USE_RMII
+#define CONFIG_MII
+#define CONFIG_BOOTP_DEFAULT
+#define CONFIG_BOOTP_DNS
+#define CONFIG_BOOTP_DNS2
+#define CONFIG_BOOTP_SEND_HOSTNAME
+#define CONFIG_NET_RETRY_COUNT 10
+
/*
* Board NAND Info.
*/
10, 11, 12, 13}
#define CONFIG_SYS_NAND_ECCSIZE 512
#define CONFIG_SYS_NAND_ECCBYTES 3
+ #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW
#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
#undef CONFIG_CMD_IMLS /* List all found images */
#define CONFIG_SYS_NO_FLASH
- #define CONFIG_HARD_I2C
- #define CONFIG_SYS_I2C_SPEED 100000
- #define CONFIG_SYS_I2C_SLAVE 1
- #define CONFIG_DRIVER_OMAP34XX_I2C
+ #define CONFIG_SYS_I2C
+ #define CONFIG_SYS_OMAP24_I2C_SPEED 100000
+ #define CONFIG_SYS_OMAP24_I2C_SLAVE 1
+ #define CONFIG_SYS_I2C_OMAP34XX
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
#define CONFIG_I2C_MULTI_BUS
/* Status LED */
#define CONFIG_STATUS_LED /* Status LED enabled */
#define CONFIG_BOARD_SPECIFIC_LED
-#define STATUS_LED_GREEN 0
-#define STATUS_LED_BIT STATUS_LED_GREEN
+#define CONFIG_GPIO_LED
+#define GREEN_LED_GPIO 186 /* CM-T35 Green LED is GPIO186 */
+#define GREEN_LED_DEV 0
+#define STATUS_LED_BIT GREEN_LED_GPIO
#define STATUS_LED_STATE STATUS_LED_ON
#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2)
-#define STATUS_LED_BOOT STATUS_LED_BIT
-#define GREEN_LED_GPIO 186 /* CM-T35 Green LED is GPIO186 */
+#define STATUS_LED_BOOT GREEN_LED_DEV
#define CONFIG_SPLASHIMAGE_GUARD
#define CONFIG_SPLASH_SCREEN
#define CONFIG_CMD_BMP
#define CONFIG_BMP_16BPP
+ #define CONFIG_SCF0403_LCD
+
+ #define CONFIG_OMAP3_SPI
#endif /* __CONFIG_H */
#define CONFIG_USB_EHCI_OMAP
#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 147
-#define CONFIG_USB_ULPI
-#define CONFIG_USB_ULPI_VIEWPORT_OMAP
-
#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
#define CONFIG_USB_HOST_ETHER
#define CONFIG_USB_ETHER_SMSC95XX
#undef CONFIG_CMD_IMLS /* List all found images */
#define CONFIG_SYS_NO_FLASH
- #define CONFIG_HARD_I2C 1
- #define CONFIG_SYS_I2C_SPEED 100000
- #define CONFIG_SYS_I2C_SLAVE 1
- #define CONFIG_I2C_MULTI_BUS 1
- #define CONFIG_DRIVER_OMAP34XX_I2C 1
+ #define CONFIG_SYS_I2C
+ #define CONFIG_SYS_OMAP24_I2C_SPEED 100000
+ #define CONFIG_SYS_OMAP24_I2C_SLAVE 1
+ #define CONFIG_SYS_I2C_OMAP34XX
#define CONFIG_VIDEO_OMAP3 /* DSS Support */
/*
10, 11, 12, 13}
#define CONFIG_SYS_NAND_ECCSIZE 512
#define CONFIG_SYS_NAND_ECCBYTES 3
+ #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW
#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
/* I2C Configuration */
#define CONFIG_I2C
#define CONFIG_CMD_I2C
- #define CONFIG_HARD_I2C
- #define CONFIG_SYS_I2C_SLAVE 1
- #define CONFIG_I2C_MULTI_BUS
- #define CONFIG_DRIVER_OMAP24XX_I2C
-
+ #define CONFIG_SYS_I2C
+ #define CONFIG_SYS_OMAP24_I2C_SPEED OMAP_I2C_STANDARD
+ #define CONFIG_SYS_OMAP24_I2C_SLAVE 1
+ #define CONFIG_SYS_I2C_OMAP24XX
/* Defines for SPL */
#define CONFIG_SPL
#define CONFIG_SYS_NAND_ECCSIZE 512
#define CONFIG_SYS_NAND_ECCBYTES 14
+ #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW
#define CONFIG_SYS_NAND_ECCSTEPS 4
#define CONFIG_SYS_NAND_ECCTOTAL (CONFIG_SYS_NAND_ECCBYTES * \
#define CONFIG_USB_GADGET
#define CONFIG_USBDOWNLOAD_GADGET
-/* USB TI's IDs */
+/* USB DRACO ID as default */
#define CONFIG_USBD_HS
-#define CONFIG_G_DNL_VENDOR_NUM 0x0525
-#define CONFIG_G_DNL_PRODUCT_NUM 0x4a47
-#define CONFIG_G_DNL_MANUFACTURER "Texas Instruments"
+#define CONFIG_G_DNL_VENDOR_NUM 0x0908
+#define CONFIG_G_DNL_PRODUCT_NUM 0x02d2
+#define CONFIG_G_DNL_MANUFACTURER "Siemens AG"
/* USB Device Firmware Update support */
#define CONFIG_DFU_FUNCTION
#define CONFIG_COMMON_ENV_SETTINGS \
"verify=no \0" \
"project_dir=systemone\0" \
+ "upgrade_available=0\0" \
+ "altbootcmd=run bootcmd\0" \
+ "bootlimit=3\0" \
+ "partitionset_active=A\0" \
"loadaddr=0x82000000\0" \
"kloadaddr=0x81000000\0" \
"script_addr=0x81900000\0" \
- "console=console=ttyMTD,mtdoops console=ttyO0,115200n8\0" \
- "active_set=a\0" \
+ "console=console=ttyMTD,mtdoops console=ttyO0,115200n8 panic=5\0" \
"nand_active_ubi_vol=rootfs_a\0" \
+ "nand_active_ubi_vol_A=rootfs_a\0" \
+ "nand_active_ubi_vol_B=rootfs_b\0" \
"nand_root_fs_type=ubifs rootwait=1\0" \
"nand_src_addr=0x280000\0" \
- "nand_src_addr_a=0x280000\0" \
- "nand_src_addr_b=0x780000\0" \
+ "nand_src_addr_A=0x280000\0" \
+ "nand_src_addr_B=0x780000\0" \
"nfsopts=nolock rw mem=128M\0" \
"ip_method=none\0" \
"bootenv=uEnv.txt\0" \
"bootargs_defaults=setenv bootargs " \
"console=${console} " \
+ "${testargs} " \
"${optargs}\0" \
"nand_args=run bootargs_defaults;" \
"mtdparts default;" \
- "setenv nand_active_ubi_vol rootfs_${active_set};" \
- "setenv ${active_set} true;" \
- "if test -n ${a}; then " \
- "setenv nand_src_addr ${nand_src_addr_a};" \
+ "setenv ${partitionset_active} true;" \
+ "if test -n ${A}; then " \
+ "setenv nand_active_ubi_vol ${nand_active_ubi_vol_A};" \
+ "setenv nand_src_addr ${nand_src_addr_A};" \
"fi;" \
- "if test -n ${b}; then " \
- "setenv nand_src_addr ${nand_src_addr_b};" \
+ "if test -n ${B}; then " \
+ "setenv nand_active_ubi_vol ${nand_active_ubi_vol_B};" \
+ "setenv nand_src_addr ${nand_src_addr_B};" \
"fi;" \
"setenv nand_root ubi0:${nand_active_ubi_vol} rw " \
"ubi.mtd=9,2048;" \
"setenv bootargs ${bootargs} " \
"root=/dev/nfs ${mtdparts} " \
"nfsroot=${serverip}:${rootpath},${nfsopts} " \
- "addip=setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}:" \
+ "ip=${ipaddr}:${serverip}:" \
"${gatewayip}:${netmask}:${hostname}:eth0:off\0" \
- "nand_boot=echo Booting from nand, active set ${active_set} ...; " \
+ "nand_boot=echo Booting from nand; " \
+ "if test ${upgrade_available} -eq 1; then " \
+ "if test ${bootcount} -gt ${bootlimit}; " \
+ "then " \
+ "setenv upgrade_available 0;" \
+ "setenv ${partitionset_active} true;" \
+ "if test -n ${A}; then " \
+ "setenv partitionset_active B; " \
+ "env delete A; " \
+ "fi;" \
+ "if test -n ${B}; then " \
+ "setenv partitionset_active A; " \
+ "env delete B; " \
+ "fi;" \
+ "saveenv; " \
+ "fi;" \
+ "fi;" \
+ "echo set ${partitionset_active}...;" \
"run nand_args; " \
"nand read.i ${kloadaddr} ${nand_src_addr} " \
"${nand_img_size}; bootm ${kloadaddr}\0" \
"tftpboot ${kloadaddr} ${serverip}:${bootfile}; " \
"bootm ${kloadaddr}\0" \
"flash_self=run nand_boot\0" \
- "flash_self_test=setenv bootargs_defaults ${bootargs_defaults} test; " \
+ "flash_self_test=setenv testargs test; " \
"run nand_boot\0" \
"dfu_start=echo Preparing for dfu mode ...; " \
"run dfu_args; \0" \
"mode; echo Not ready yet: 'run flash_nfs' to use kernel " \
"from memory and root filesystem over NFS; echo Type " \
"'run net_nfs' to get Kernel over TFTP and mount root " \
- "filesystem over NFS; echo Set active_set variable to 'a' " \
- "or 'b' to select kernel and rootfs partition; " \
+ "filesystem over NFS; " \
+ "echo Set partitionset_active variable to 'A' " \
+ "or 'B' to select kernel and rootfs partition; " \
"echo" \
"\0"
#define CONFIG_NAND_OMAP_GPMC
+ #define CONFIG_NAND_OMAP_ELM
#define GPMC_NAND_ECC_LP_x16_LAYOUT 1
#define CONFIG_SYS_NAND_BASE (0x08000000) /* physical address */
/* to access nand at */
#define CONFIG_AUTOBOOT_PROMPT "Autobooting in %d seconds, " \
"press \"<Esc><Esc>\" to stop\n", bootdelay
+/* Reboot after 60 sec if bootcmd fails */
+#define CONFIG_RESET_TO_RETRY
+#define CONFIG_BOOT_RETRY_TIME 60
+
+#define CONFIG_BOOTCOUNT_LIMIT
+#define CONFIG_BOOTCOUNT_ENV
+
+/* Enable Device-Tree (FDT) support */
+#define CONFIG_OF_LIBFDT
+#define CONFIG_CMD_FDT
+
#endif /* ! __CONFIG_SIEMENS_AM33X_COMMON_H */
projects / karo-tx-uboot.git / commitdiff