am33xx: Update DT files, add am335x_gp_evm_config target
authorTom Rini <trini@konsulko.com>
Fri, 31 Jul 2015 23:55:08 +0000 (19:55 -0400)
committerLothar Waßmann <LW@KARO-electronics.de>
Thu, 10 Sep 2015 08:19:14 +0000 (10:19 +0200)
- Re-sync DT files for am33xx with Linux Kernel v4.1
- Include DT file now for the "AM335x GP EVM" and build target for it,
  via device tree and DM.
- We only need to provide platform data for UART when OF_CONTROL isn't
  also enabled really.  We can just push GPIO to coming from DT

Signed-off-by: Tom Rini <trini@konsulko.com>
arch/arm/cpu/armv7/am33xx/board.c
arch/arm/dts/Makefile
arch/arm/dts/am335x-bone-common.dtsi
arch/arm/dts/am335x-bone.dts [new file with mode: 0644]
arch/arm/dts/am335x-boneblack.dts
arch/arm/dts/am335x-evm.dts [new file with mode: 0644]
arch/arm/dts/am33xx-clocks.dtsi [new file with mode: 0644]
arch/arm/dts/am33xx.dtsi
arch/arm/dts/tps65910.dtsi [new file with mode: 0644]
configs/am335x_gp_evm_defconfig [new file with mode: 0644]

index 31a9456..2f95758 100644 (file)
 
 DECLARE_GLOBAL_DATA_PTR;
 
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#ifdef CONFIG_DM_GPIO
-static const struct omap_gpio_platdata am33xx_gpio[] = {
-       { 0, AM33XX_GPIO0_BASE, METHOD_GPIO_24XX },
-       { 1, AM33XX_GPIO1_BASE, METHOD_GPIO_24XX },
-       { 2, AM33XX_GPIO2_BASE, METHOD_GPIO_24XX },
-       { 3, AM33XX_GPIO3_BASE, METHOD_GPIO_24XX },
-#ifdef CONFIG_AM43XX
-       { 4, AM33XX_GPIO4_BASE, METHOD_GPIO_24XX },
-       { 5, AM33XX_GPIO5_BASE, METHOD_GPIO_24XX },
-#endif
-};
-
-U_BOOT_DEVICES(am33xx_gpios) = {
-       { "gpio_omap", &am33xx_gpio[0] },
-       { "gpio_omap", &am33xx_gpio[1] },
-       { "gpio_omap", &am33xx_gpio[2] },
-       { "gpio_omap", &am33xx_gpio[3] },
-#ifdef CONFIG_AM43XX
-       { "gpio_omap", &am33xx_gpio[4] },
-       { "gpio_omap", &am33xx_gpio[5] },
-#endif
-};
-
-# ifndef CONFIG_OF_CONTROL
+#if defined(CONFIG_DM_SERIAL) && !defined(CONFIG_OF_CONTROL)
 /*
  * TODO(sjg@chromium.org): When we can move SPL serial to DM, we can remove
  * the CONFIGs. At the same time, we should move this to the board files.
  */
 static const struct ns16550_platdata am33xx_serial[] = {
        { CONFIG_SYS_NS16550_COM1, 2, CONFIG_SYS_NS16550_CLK },
 /*
  * TODO(sjg@chromium.org): When we can move SPL serial to DM, we can remove
  * the CONFIGs. At the same time, we should move this to the board files.
  */
 static const struct ns16550_platdata am33xx_serial[] = {
        { CONFIG_SYS_NS16550_COM1, 2, CONFIG_SYS_NS16550_CLK },
-#  ifdef CONFIG_SYS_NS16550_COM2
+# ifdef CONFIG_SYS_NS16550_COM2
        { CONFIG_SYS_NS16550_COM2, 2, CONFIG_SYS_NS16550_CLK },
        { CONFIG_SYS_NS16550_COM2, 2, CONFIG_SYS_NS16550_CLK },
-#   ifdef CONFIG_SYS_NS16550_COM3
+#  ifdef CONFIG_SYS_NS16550_COM3
        { CONFIG_SYS_NS16550_COM3, 2, CONFIG_SYS_NS16550_CLK },
        { CONFIG_SYS_NS16550_COM4, 2, CONFIG_SYS_NS16550_CLK },
        { CONFIG_SYS_NS16550_COM5, 2, CONFIG_SYS_NS16550_CLK },
        { CONFIG_SYS_NS16550_COM6, 2, CONFIG_SYS_NS16550_CLK },
        { CONFIG_SYS_NS16550_COM3, 2, CONFIG_SYS_NS16550_CLK },
        { CONFIG_SYS_NS16550_COM4, 2, CONFIG_SYS_NS16550_CLK },
        { CONFIG_SYS_NS16550_COM5, 2, CONFIG_SYS_NS16550_CLK },
        { CONFIG_SYS_NS16550_COM6, 2, CONFIG_SYS_NS16550_CLK },
-#   endif
 #  endif
 #  endif
+# endif
 };
 
 U_BOOT_DEVICES(am33xx_uarts) = {
 };
 
 U_BOOT_DEVICES(am33xx_uarts) = {
@@ -91,10 +68,10 @@ U_BOOT_DEVICES(am33xx_uarts) = {
 #   endif
 #  endif
 };
 #   endif
 #  endif
 };
-# endif
+#endif
 
 
-#else
 
 
+#ifndef CONFIG_DM_GPIO
 static const struct gpio_bank gpio_bank_am33xx[] = {
        { (void *)AM33XX_GPIO0_BASE, METHOD_GPIO_24XX },
        { (void *)AM33XX_GPIO1_BASE, METHOD_GPIO_24XX },
 static const struct gpio_bank gpio_bank_am33xx[] = {
        { (void *)AM33XX_GPIO0_BASE, METHOD_GPIO_24XX },
        { (void *)AM33XX_GPIO1_BASE, METHOD_GPIO_24XX },
@@ -107,7 +84,6 @@ static const struct gpio_bank gpio_bank_am33xx[] = {
 };
 
 const struct gpio_bank *const omap_gpio_bank = gpio_bank_am33xx;
 };
 
 const struct gpio_bank *const omap_gpio_bank = gpio_bank_am33xx;
-
 #endif
 
 #if defined(CONFIG_OMAP_HSMMC) && !defined(CONFIG_SPL_BUILD)
 #endif
 
 #if defined(CONFIG_OMAP_HSMMC) && !defined(CONFIG_SPL_BUILD)
index 3aaeb6a..ef71ac1 100644 (file)
@@ -52,7 +52,7 @@ dtb-$(CONFIG_ARCH_ZYNQ) += zynq-zc702.dtb \
        zynq-zc770-xm011.dtb \
        zynq-zc770-xm012.dtb \
        zynq-zc770-xm013.dtb
        zynq-zc770-xm011.dtb \
        zynq-zc770-xm012.dtb \
        zynq-zc770-xm013.dtb
-dtb-$(CONFIG_AM33XX) += am335x-boneblack.dtb
+dtb-$(CONFIG_AM33XX) += am335x-boneblack.dtb am335x-evm.dtb
 
 dtb-$(CONFIG_ARCH_SOCFPGA) +=                          \
        socfpga_arria5_socdk.dtb                        \
 
 dtb-$(CONFIG_ARCH_SOCFPGA) +=                          \
        socfpga_arria5_socdk.dtb                        \
index e70b4d1..fec7834 100644 (file)
@@ -7,13 +7,6 @@
  */
 
 / {
  */
 
 / {
-       model = "TI AM335x BeagleBone";
-       compatible = "ti,am335x-bone", "ti,am33xx";
-
-       chosen {
-               stdout-path = &uart0;
-       };
-
        cpus {
                cpu@0 {
                        cpu0-supply = <&dcdc2_reg>;
        cpus {
                cpu@0 {
                        cpu0-supply = <&dcdc2_reg>;
                reg = <0x80000000 0x10000000>; /* 256 MB */
        };
 
                reg = <0x80000000 0x10000000>; /* 256 MB */
        };
 
-       am33xx_pinmux: pinmux@44e10800 {
+       leds {
                pinctrl-names = "default";
                pinctrl-names = "default";
-               pinctrl-0 = <&clkout2_pin>;
-
-               user_leds_s0: user_leds_s0 {
-                       pinctrl-single,pins = <
-                               0x54 (PIN_OUTPUT_PULLDOWN | MUX_MODE7)  /* gpmc_a5.gpio1_21 */
-                               0x58 (PIN_OUTPUT_PULLUP | MUX_MODE7)    /* gpmc_a6.gpio1_22 */
-                               0x5c (PIN_OUTPUT_PULLDOWN | MUX_MODE7)  /* gpmc_a7.gpio1_23 */
-                               0x60 (PIN_OUTPUT_PULLUP | MUX_MODE7)    /* gpmc_a8.gpio1_24 */
-                       >;
-               };
+               pinctrl-0 = <&user_leds_s0>;
 
 
-               i2c0_pins: pinmux_i2c0_pins {
-                       pinctrl-single,pins = <
-                               0x188 (PIN_INPUT_PULLUP | MUX_MODE0)    /* i2c0_sda.i2c0_sda */
-                               0x18c (PIN_INPUT_PULLUP | MUX_MODE0)    /* i2c0_scl.i2c0_scl */
-                       >;
-               };
+               compatible = "gpio-leds";
 
 
-               uart0_pins: pinmux_uart0_pins {
-                       pinctrl-single,pins = <
-                               0x170 (PIN_INPUT_PULLUP | MUX_MODE0)    /* uart0_rxd.uart0_rxd */
-                               0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
-                       >;
+               led@2 {
+                       label = "beaglebone:green:heartbeat";
+                       gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>;
+                       linux,default-trigger = "heartbeat";
+                       default-state = "off";
                };
 
                };
 
-               clkout2_pin: pinmux_clkout2_pin {
-                       pinctrl-single,pins = <
-                               0x1b4 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr1.clkout2 */
-                       >;
+               led@3 {
+                       label = "beaglebone:green:mmc0";
+                       gpios = <&gpio1 22 GPIO_ACTIVE_HIGH>;
+                       linux,default-trigger = "mmc0";
+                       default-state = "off";
                };
 
                };
 
-               cpsw_default: cpsw_default {
-                       pinctrl-single,pins = <
-                               /* Slave 1 */
-                               0x110 (PIN_INPUT_PULLUP | MUX_MODE0)    /* mii1_rxerr.mii1_rxerr */
-                               0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txen.mii1_txen */
-                               0x118 (PIN_INPUT_PULLUP | MUX_MODE0)    /* mii1_rxdv.mii1_rxdv */
-                               0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd3.mii1_txd3 */
-                               0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd2.mii1_txd2 */
-                               0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd1.mii1_txd1 */
-                               0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd0.mii1_txd0 */
-                               0x12c (PIN_INPUT_PULLUP | MUX_MODE0)    /* mii1_txclk.mii1_txclk */
-                               0x130 (PIN_INPUT_PULLUP | MUX_MODE0)    /* mii1_rxclk.mii1_rxclk */
-                               0x134 (PIN_INPUT_PULLUP | MUX_MODE0)    /* mii1_rxd3.mii1_rxd3 */
-                               0x138 (PIN_INPUT_PULLUP | MUX_MODE0)    /* mii1_rxd2.mii1_rxd2 */
-                               0x13c (PIN_INPUT_PULLUP | MUX_MODE0)    /* mii1_rxd1.mii1_rxd1 */
-                               0x140 (PIN_INPUT_PULLUP | MUX_MODE0)    /* mii1_rxd0.mii1_rxd0 */
-                       >;
+               led@4 {
+                       label = "beaglebone:green:usr2";
+                       gpios = <&gpio1 23 GPIO_ACTIVE_HIGH>;
+                       linux,default-trigger = "cpu0";
+                       default-state = "off";
                };
 
                };
 
-               cpsw_sleep: cpsw_sleep {
-                       pinctrl-single,pins = <
-                               /* Slave 1 reset value */
-                               0x110 (PIN_INPUT_PULLDOWN | MUX_MODE7)
-                               0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7)
-                               0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7)
-                               0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7)
-                               0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7)
-                               0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7)
-                               0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7)
-                               0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7)
-                               0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7)
-                               0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7)
-                               0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7)
-                               0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7)
-                               0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       >;
+               led@5 {
+                       label = "beaglebone:green:usr3";
+                       gpios = <&gpio1 24 GPIO_ACTIVE_HIGH>;
+                       linux,default-trigger = "mmc1";
+                       default-state = "off";
                };
                };
+       };
 
 
-               davinci_mdio_default: davinci_mdio_default {
-                       pinctrl-single,pins = <
-                               /* MDIO */
-                               0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)    /* mdio_data.mdio_data */
-                               0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0)                   /* mdio_clk.mdio_clk */
-                       >;
-               };
+       vmmcsd_fixed: fixedregulator@0 {
+               compatible = "regulator-fixed";
+               regulator-name = "vmmcsd_fixed";
+               regulator-min-microvolt = <3300000>;
+               regulator-max-microvolt = <3300000>;
+       };
+};
 
 
-               davinci_mdio_sleep: davinci_mdio_sleep {
-                       pinctrl-single,pins = <
-                               /* MDIO reset value */
-                               0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7)
-                               0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       >;
-               };
+&am33xx_pinmux {
+       pinctrl-names = "default";
+       pinctrl-0 = <&clkout2_pin>;
+
+       user_leds_s0: user_leds_s0 {
+               pinctrl-single,pins = <
+                       0x54 (PIN_OUTPUT_PULLDOWN | MUX_MODE7)  /* gpmc_a5.gpio1_21 */
+                       0x58 (PIN_OUTPUT_PULLUP | MUX_MODE7)    /* gpmc_a6.gpio1_22 */
+                       0x5c (PIN_OUTPUT_PULLDOWN | MUX_MODE7)  /* gpmc_a7.gpio1_23 */
+                       0x60 (PIN_OUTPUT_PULLUP | MUX_MODE7)    /* gpmc_a8.gpio1_24 */
+               >;
        };
 
        };
 
-       ocp {
-               uart0: serial@44e09000 {
-                       pinctrl-names = "default";
-                       pinctrl-0 = <&uart0_pins>;
+       i2c0_pins: pinmux_i2c0_pins {
+               pinctrl-single,pins = <
+                       0x188 (PIN_INPUT_PULLUP | MUX_MODE0)    /* i2c0_sda.i2c0_sda */
+                       0x18c (PIN_INPUT_PULLUP | MUX_MODE0)    /* i2c0_scl.i2c0_scl */
+               >;
+       };
 
 
-                       status = "okay";
-               };
+       i2c2_pins: pinmux_i2c2_pins {
+               pinctrl-single,pins = <
+                       0x178 (PIN_INPUT_PULLUP | MUX_MODE3)    /* uart1_ctsn.i2c2_sda */
+                       0x17c (PIN_INPUT_PULLUP | MUX_MODE3)    /* uart1_rtsn.i2c2_scl */
+               >;
+       };
 
 
-               musb: usb@47400000 {
-                       status = "okay";
+       uart0_pins: pinmux_uart0_pins {
+               pinctrl-single,pins = <
+                       0x170 (PIN_INPUT_PULLUP | MUX_MODE0)    /* uart0_rxd.uart0_rxd */
+                       0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
+               >;
+       };
 
 
-                       control@44e10000 {
-                               status = "okay";
-                       };
+       clkout2_pin: pinmux_clkout2_pin {
+               pinctrl-single,pins = <
+                       0x1b4 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr1.clkout2 */
+               >;
+       };
 
 
-                       usb-phy@47401300 {
-                               status = "okay";
-                       };
+       cpsw_default: cpsw_default {
+               pinctrl-single,pins = <
+                       /* Slave 1 */
+                       0x110 (PIN_INPUT_PULLUP | MUX_MODE0)    /* mii1_rxerr.mii1_rxerr */
+                       0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txen.mii1_txen */
+                       0x118 (PIN_INPUT_PULLUP | MUX_MODE0)    /* mii1_rxdv.mii1_rxdv */
+                       0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd3.mii1_txd3 */
+                       0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd2.mii1_txd2 */
+                       0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd1.mii1_txd1 */
+                       0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd0.mii1_txd0 */
+                       0x12c (PIN_INPUT_PULLUP | MUX_MODE0)    /* mii1_txclk.mii1_txclk */
+                       0x130 (PIN_INPUT_PULLUP | MUX_MODE0)    /* mii1_rxclk.mii1_rxclk */
+                       0x134 (PIN_INPUT_PULLUP | MUX_MODE0)    /* mii1_rxd3.mii1_rxd3 */
+                       0x138 (PIN_INPUT_PULLUP | MUX_MODE0)    /* mii1_rxd2.mii1_rxd2 */
+                       0x13c (PIN_INPUT_PULLUP | MUX_MODE0)    /* mii1_rxd1.mii1_rxd1 */
+                       0x140 (PIN_INPUT_PULLUP | MUX_MODE0)    /* mii1_rxd0.mii1_rxd0 */
+               >;
+       };
 
 
-                       usb-phy@47401b00 {
-                               status = "okay";
-                       };
+       cpsw_sleep: cpsw_sleep {
+               pinctrl-single,pins = <
+                       /* Slave 1 reset value */
+                       0x110 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                       0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                       0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                       0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                       0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                       0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                       0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                       0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                       0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                       0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                       0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                       0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                       0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+               >;
+       };
 
 
-                       usb@47401000 {
-                               status = "okay";
-                       };
+       davinci_mdio_default: davinci_mdio_default {
+               pinctrl-single,pins = <
+                       /* MDIO */
+                       0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)    /* mdio_data.mdio_data */
+                       0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0)                   /* mdio_clk.mdio_clk */
+               >;
+       };
 
 
-                       usb@47401800 {
-                               status = "okay";
-                               dr_mode = "host";
-                       };
+       davinci_mdio_sleep: davinci_mdio_sleep {
+               pinctrl-single,pins = <
+                       /* MDIO reset value */
+                       0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                       0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
+               >;
+       };
 
 
-                       dma-controller@07402000  {
-                               status = "okay";
-                       };
-               };
+       mmc1_pins: pinmux_mmc1_pins {
+               pinctrl-single,pins = <
+                       0x160 (PIN_INPUT | MUX_MODE7) /* GPIO0_6 */
+               >;
+       };
+
+       emmc_pins: pinmux_emmc_pins {
+               pinctrl-single,pins = <
+                       0x80 (PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn1.mmc1_clk */
+                       0x84 (PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn2.mmc1_cmd */
+                       0x00 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */
+                       0x04 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */
+                       0x08 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */
+                       0x0c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */
+                       0x10 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad4.mmc1_dat4 */
+                       0x14 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad5.mmc1_dat5 */
+                       0x18 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad6.mmc1_dat6 */
+                       0x1c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad7.mmc1_dat7 */
+               >;
+       };
+};
+
+&uart0 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&uart0_pins>;
 
 
-               i2c0: i2c@44e0b000 {
-                       pinctrl-names = "default";
-                       pinctrl-0 = <&i2c0_pins>;
+       status = "okay";
+};
 
 
-                       status = "okay";
-                       clock-frequency = <400000>;
+&usb {
+       status = "okay";
+};
 
 
-                       tps: tps@24 {
-                               reg = <0x24>;
-                       };
+&usb_ctrl_mod {
+       status = "okay";
+};
 
 
+&usb0_phy {
+       status = "okay";
+};
+
+&usb1_phy {
+       status = "okay";
+};
+
+&usb0 {
+       status = "okay";
+       dr_mode = "peripheral";
+};
+
+&usb1 {
+       status = "okay";
+       dr_mode = "host";
+};
+
+&cppi41dma  {
+       status = "okay";
+};
+
+&i2c0 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&i2c0_pins>;
+
+       status = "okay";
+       clock-frequency = <400000>;
+
+       tps: tps@24 {
+               reg = <0x24>;
+       };
+
+       baseboard_eeprom: baseboard_eeprom@50 {
+               compatible = "at,24c256";
+               reg = <0x50>;
+
+               #address-cells = <1>;
+               #size-cells = <1>;
+               baseboard_data: baseboard_data@0 {
+                       reg = <0 0x100>;
                };
        };
                };
        };
+};
 
 
-       leds {
-               pinctrl-names = "default";
-               pinctrl-0 = <&user_leds_s0>;
+&i2c2 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&i2c2_pins>;
 
 
-               compatible = "gpio-leds";
+       status = "okay";
+       clock-frequency = <100000>;
 
 
-               led@2 {
-                       label = "beaglebone:green:heartbeat";
-                       gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>;
-                       linux,default-trigger = "heartbeat";
-                       default-state = "off";
+       cape_eeprom0: cape_eeprom0@54 {
+               compatible = "at,24c256";
+               reg = <0x54>;
+               #address-cells = <1>;
+               #size-cells = <1>;
+               cape0_data: cape_data@0 {
+                       reg = <0 0x100>;
                };
                };
+       };
 
 
-               led@3 {
-                       label = "beaglebone:green:mmc0";
-                       gpios = <&gpio1 22 GPIO_ACTIVE_HIGH>;
-                       linux,default-trigger = "mmc0";
-                       default-state = "off";
+       cape_eeprom1: cape_eeprom1@55 {
+               compatible = "at,24c256";
+               reg = <0x55>;
+               #address-cells = <1>;
+               #size-cells = <1>;
+               cape1_data: cape_data@0 {
+                       reg = <0 0x100>;
                };
                };
+       };
 
 
-               led@4 {
-                       label = "beaglebone:green:usr2";
-                       gpios = <&gpio1 23 GPIO_ACTIVE_HIGH>;
-                       default-state = "off";
+       cape_eeprom2: cape_eeprom2@56 {
+               compatible = "at,24c256";
+               reg = <0x56>;
+               #address-cells = <1>;
+               #size-cells = <1>;
+               cape2_data: cape_data@0 {
+                       reg = <0 0x100>;
                };
                };
+       };
 
 
-               led@5 {
-                       label = "beaglebone:green:usr3";
-                       gpios = <&gpio1 24 GPIO_ACTIVE_HIGH>;
-                       default-state = "off";
+       cape_eeprom3: cape_eeprom3@57 {
+               compatible = "at,24c256";
+               reg = <0x57>;
+               #address-cells = <1>;
+               #size-cells = <1>;
+               cape3_data: cape_data@0 {
+                       reg = <0 0x100>;
                };
        };
 };
 
                };
        };
 };
 
+
 /include/ "tps65217.dtsi"
 
 &tps {
 /include/ "tps65217.dtsi"
 
 &tps {
+       /*
+        * Configure pmic to enter OFF-state instead of SLEEP-state ("RTC-only
+        * mode") at poweroff.  Most BeagleBone versions do not support RTC-only
+        * mode and risk hardware damage if this mode is entered.
+        *
+        * For details, see linux-omap mailing list May 2015 thread
+        *      [PATCH] ARM: dts: am335x-bone* enable pmic-shutdown-controller
+        * In particular, messages:
+        *      http://www.spinics.net/lists/linux-omap/msg118585.html
+        *      http://www.spinics.net/lists/linux-omap/msg118615.html
+        *
+        * You can override this later with
+        *      &tps {  /delete-property/ ti,pmic-shutdown-controller;  }
+        * if you want to use RTC-only mode and made sure you are not affected
+        * by the hardware problems. (Tip: double-check by performing a current
+        * measurement after shutdown: it should be less than 1 mA.)
+        */
+       ti,pmic-shutdown-controller;
+
        regulators {
                dcdc1_reg: regulator@0 {
        regulators {
                dcdc1_reg: regulator@0 {
+                       regulator-name = "vdds_dpr";
                        regulator-always-on;
                };
 
                        regulator-always-on;
                };
 
                };
 
                ldo1_reg: regulator@3 {
                };
 
                ldo1_reg: regulator@3 {
+                       regulator-name = "vio,vrtc,vdds";
                        regulator-always-on;
                };
 
                ldo2_reg: regulator@4 {
                        regulator-always-on;
                };
 
                ldo2_reg: regulator@4 {
+                       regulator-name = "vdd_3v3aux";
                        regulator-always-on;
                };
 
                ldo3_reg: regulator@5 {
                        regulator-always-on;
                };
 
                ldo3_reg: regulator@5 {
+                       regulator-name = "vdd_1v8";
                        regulator-always-on;
                };
 
                ldo4_reg: regulator@6 {
                        regulator-always-on;
                };
 
                ldo4_reg: regulator@6 {
+                       regulator-name = "vdd_3v3a";
                        regulator-always-on;
                };
        };
                        regulator-always-on;
                };
        };
        pinctrl-names = "default", "sleep";
        pinctrl-0 = <&cpsw_default>;
        pinctrl-1 = <&cpsw_sleep>;
        pinctrl-names = "default", "sleep";
        pinctrl-0 = <&cpsw_default>;
        pinctrl-1 = <&cpsw_sleep>;
-
+       status = "okay";
 };
 
 &davinci_mdio {
        pinctrl-names = "default", "sleep";
        pinctrl-0 = <&davinci_mdio_default>;
        pinctrl-1 = <&davinci_mdio_sleep>;
 };
 
 &davinci_mdio {
        pinctrl-names = "default", "sleep";
        pinctrl-0 = <&davinci_mdio_default>;
        pinctrl-1 = <&davinci_mdio_sleep>;
+       status = "okay";
+};
+
+&mmc1 {
+       status = "okay";
+       bus-width = <0x4>;
+       pinctrl-names = "default";
+       pinctrl-0 = <&mmc1_pins>;
+       cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>;
+       cd-inverted;
+};
+
+&aes {
+       status = "okay";
+};
+
+&sham {
+       status = "okay";
 };
 };
diff --git a/arch/arm/dts/am335x-bone.dts b/arch/arm/dts/am335x-bone.dts
new file mode 100644 (file)
index 0000000..81441cc
--- /dev/null
@@ -0,0 +1,29 @@
+/*
+ * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/dts-v1/;
+
+#include "am33xx.dtsi"
+#include "am335x-bone-common.dtsi"
+
+/ {
+       model = "TI AM335x BeagleBone";
+       compatible = "ti,am335x-bone", "ti,am33xx";
+       chosen {
+               stdout-path = &uart0;
+       };
+};
+
+&ldo3_reg {
+       regulator-min-microvolt = <1800000>;
+       regulator-max-microvolt = <3300000>;
+       regulator-always-on;
+};
+
+&mmc1 {
+       vmmc-supply = <&ldo3_reg>;
+};
index 197cadf..679248a 100644 (file)
 #include "am33xx.dtsi"
 #include "am335x-bone-common.dtsi"
 
 #include "am33xx.dtsi"
 #include "am335x-bone-common.dtsi"
 
+/ {
+       model = "TI AM335x BeagleBone Black";
+       compatible = "ti,am335x-bone-black", "ti,am335x-bone", "ti,am33xx";
+       chosen {
+               stdout-path = &uart0;
+       };
+};
+
 &ldo3_reg {
        regulator-min-microvolt = <1800000>;
        regulator-max-microvolt = <1800000>;
        regulator-always-on;
 };
 &ldo3_reg {
        regulator-min-microvolt = <1800000>;
        regulator-max-microvolt = <1800000>;
        regulator-always-on;
 };
+
+&mmc1 {
+       vmmc-supply = <&vmmcsd_fixed>;
+};
+
+&mmc2 {
+       vmmc-supply = <&vmmcsd_fixed>;
+       pinctrl-names = "default";
+       pinctrl-0 = <&emmc_pins>;
+       bus-width = <8>;
+       status = "okay";
+};
+
+&am33xx_pinmux {
+       nxp_hdmi_bonelt_pins: nxp_hdmi_bonelt_pins {
+               pinctrl-single,pins = <
+                       0x1b0 0x03      /* xdma_event_intr0, OMAP_MUX_MODE3 | AM33XX_PIN_OUTPUT */
+                       0xa0 0x08       /* lcd_data0.lcd_data0, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
+                       0xa4 0x08       /* lcd_data1.lcd_data1, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
+                       0xa8 0x08       /* lcd_data2.lcd_data2, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
+                       0xac 0x08       /* lcd_data3.lcd_data3, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
+                       0xb0 0x08       /* lcd_data4.lcd_data4, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
+                       0xb4 0x08       /* lcd_data5.lcd_data5, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
+                       0xb8 0x08       /* lcd_data6.lcd_data6, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
+                       0xbc 0x08       /* lcd_data7.lcd_data7, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
+                       0xc0 0x08       /* lcd_data8.lcd_data8, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
+                       0xc4 0x08       /* lcd_data9.lcd_data9, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
+                       0xc8 0x08       /* lcd_data10.lcd_data10, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
+                       0xcc 0x08       /* lcd_data11.lcd_data11, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
+                       0xd0 0x08       /* lcd_data12.lcd_data12, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
+                       0xd4 0x08       /* lcd_data13.lcd_data13, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
+                       0xd8 0x08       /* lcd_data14.lcd_data14, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
+                       0xdc 0x08       /* lcd_data15.lcd_data15, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
+                       0xe0 0x00       /* lcd_vsync.lcd_vsync, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT */
+                       0xe4 0x00       /* lcd_hsync.lcd_hsync, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT */
+                       0xe8 0x00       /* lcd_pclk.lcd_pclk, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT */
+                       0xec 0x00       /* lcd_ac_bias_en.lcd_ac_bias_en, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT */
+               >;
+       };
+       nxp_hdmi_bonelt_off_pins: nxp_hdmi_bonelt_off_pins {
+               pinctrl-single,pins = <
+                       0x1b0 0x03      /* xdma_event_intr0, OMAP_MUX_MODE3 | AM33XX_PIN_OUTPUT */
+               >;
+       };
+};
+
+&lcdc {
+       status = "okay";
+};
+
+/ {
+       hdmi {
+               compatible = "ti,tilcdc,slave";
+               i2c = <&i2c0>;
+               pinctrl-names = "default", "off";
+               pinctrl-0 = <&nxp_hdmi_bonelt_pins>;
+               pinctrl-1 = <&nxp_hdmi_bonelt_off_pins>;
+               status = "okay";
+       };
+};
+
+&rtc {
+       system-power-controller;
+};
diff --git a/arch/arm/dts/am335x-evm.dts b/arch/arm/dts/am335x-evm.dts
new file mode 100644 (file)
index 0000000..e1c5d4f
--- /dev/null
@@ -0,0 +1,765 @@
+/*
+ * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/dts-v1/;
+
+#include "am33xx.dtsi"
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+       model = "TI AM335x EVM";
+       compatible = "ti,am335x-evm", "ti,am33xx";
+
+       chosen {
+               stdout-path = &uart0;
+       };
+
+       cpus {
+               cpu@0 {
+                       cpu0-supply = <&vdd1_reg>;
+               };
+       };
+
+       memory {
+               device_type = "memory";
+               reg = <0x80000000 0x10000000>; /* 256 MB */
+       };
+
+       vbat: fixedregulator@0 {
+               compatible = "regulator-fixed";
+               regulator-name = "vbat";
+               regulator-min-microvolt = <5000000>;
+               regulator-max-microvolt = <5000000>;
+               regulator-boot-on;
+       };
+
+       lis3_reg: fixedregulator@1 {
+               compatible = "regulator-fixed";
+               regulator-name = "lis3_reg";
+               regulator-boot-on;
+       };
+
+       wlan_en_reg: fixedregulator@2 {
+               compatible = "regulator-fixed";
+               regulator-name = "wlan-en-regulator";
+               regulator-min-microvolt = <1800000>;
+               regulator-max-microvolt = <1800000>;
+
+               /* WLAN_EN GPIO for this board - Bank1, pin16 */
+               gpio = <&gpio1 16 0>;
+
+               /* WLAN card specific delay */
+               startup-delay-us = <70000>;
+               enable-active-high;
+       };
+
+       matrix_keypad: matrix_keypad@0 {
+               compatible = "gpio-matrix-keypad";
+               debounce-delay-ms = <5>;
+               col-scan-delay-us = <2>;
+
+               row-gpios = <&gpio1 25 GPIO_ACTIVE_HIGH         /* Bank1, pin25 */
+                            &gpio1 26 GPIO_ACTIVE_HIGH         /* Bank1, pin26 */
+                            &gpio1 27 GPIO_ACTIVE_HIGH>;       /* Bank1, pin27 */
+
+               col-gpios = <&gpio1 21 GPIO_ACTIVE_HIGH         /* Bank1, pin21 */
+                            &gpio1 22 GPIO_ACTIVE_HIGH>;       /* Bank1, pin22 */
+
+               linux,keymap = <0x0000008b      /* MENU */
+                               0x0100009e      /* BACK */
+                               0x02000069      /* LEFT */
+                               0x0001006a      /* RIGHT */
+                               0x0101001c      /* ENTER */
+                               0x0201006c>;    /* DOWN */
+       };
+
+       gpio_keys: volume_keys@0 {
+               compatible = "gpio-keys";
+               #address-cells = <1>;
+               #size-cells = <0>;
+               autorepeat;
+
+               switch@9 {
+                       label = "volume-up";
+                       linux,code = <115>;
+                       gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
+                       gpio-key,wakeup;
+               };
+
+               switch@10 {
+                       label = "volume-down";
+                       linux,code = <114>;
+                       gpios = <&gpio0 3 GPIO_ACTIVE_LOW>;
+                       gpio-key,wakeup;
+               };
+       };
+
+       backlight {
+               compatible = "pwm-backlight";
+               pwms = <&ecap0 0 50000 0>;
+               brightness-levels = <0 51 53 56 62 75 101 152 255>;
+               default-brightness-level = <8>;
+       };
+
+       panel {
+               compatible = "ti,tilcdc,panel";
+               status = "okay";
+               pinctrl-names = "default";
+               pinctrl-0 = <&lcd_pins_s0>;
+               panel-info {
+                       ac-bias           = <255>;
+                       ac-bias-intrpt    = <0>;
+                       dma-burst-sz      = <16>;
+                       bpp               = <32>;
+                       fdd               = <0x80>;
+                       sync-edge         = <0>;
+                       sync-ctrl         = <1>;
+                       raster-order      = <0>;
+                       fifo-th           = <0>;
+               };
+
+               display-timings {
+                       800x480p62 {
+                               clock-frequency = <30000000>;
+                               hactive = <800>;
+                               vactive = <480>;
+                               hfront-porch = <39>;
+                               hback-porch = <39>;
+                               hsync-len = <47>;
+                               vback-porch = <29>;
+                               vfront-porch = <13>;
+                               vsync-len = <2>;
+                               hsync-active = <1>;
+                               vsync-active = <1>;
+                       };
+               };
+       };
+
+       sound {
+               compatible = "ti,da830-evm-audio";
+               ti,model = "AM335x-EVM";
+               ti,audio-codec = <&tlv320aic3106>;
+               ti,mcasp-controller = <&mcasp1>;
+               ti,codec-clock-rate = <12000000>;
+               ti,audio-routing =
+                       "Headphone Jack",       "HPLOUT",
+                       "Headphone Jack",       "HPROUT",
+                       "LINE1L",               "Line In",
+                       "LINE1R",               "Line In";
+       };
+};
+
+&am33xx_pinmux {
+       pinctrl-names = "default";
+       pinctrl-0 = <&matrix_keypad_s0 &volume_keys_s0 &clkout2_pin>;
+
+       matrix_keypad_s0: matrix_keypad_s0 {
+               pinctrl-single,pins = <
+                       0x54 (PIN_OUTPUT_PULLDOWN | MUX_MODE7)  /* gpmc_a5.gpio1_21 */
+                       0x58 (PIN_OUTPUT_PULLDOWN | MUX_MODE7)  /* gpmc_a6.gpio1_22 */
+                       0x64 (PIN_INPUT_PULLDOWN | MUX_MODE7)   /* gpmc_a9.gpio1_25 */
+                       0x68 (PIN_INPUT_PULLDOWN | MUX_MODE7)   /* gpmc_a10.gpio1_26 */
+                       0x6c (PIN_INPUT_PULLDOWN | MUX_MODE7)   /* gpmc_a11.gpio1_27 */
+               >;
+       };
+
+       volume_keys_s0: volume_keys_s0 {
+               pinctrl-single,pins = <
+                       0x150 (PIN_INPUT_PULLDOWN | MUX_MODE7)  /* spi0_sclk.gpio0_2 */
+                       0x154 (PIN_INPUT_PULLDOWN | MUX_MODE7)  /* spi0_d0.gpio0_3 */
+               >;
+       };
+
+       i2c0_pins: pinmux_i2c0_pins {
+               pinctrl-single,pins = <
+                       0x188 (PIN_INPUT_PULLUP | MUX_MODE0)    /* i2c0_sda.i2c0_sda */
+                       0x18c (PIN_INPUT_PULLUP | MUX_MODE0)    /* i2c0_scl.i2c0_scl */
+               >;
+       };
+
+       i2c1_pins: pinmux_i2c1_pins {
+               pinctrl-single,pins = <
+                       0x158 (PIN_INPUT_PULLUP | MUX_MODE2)    /* spi0_d1.i2c1_sda */
+                       0x15c (PIN_INPUT_PULLUP | MUX_MODE2)    /* spi0_cs0.i2c1_scl */
+               >;
+       };
+
+       uart0_pins: pinmux_uart0_pins {
+               pinctrl-single,pins = <
+                       0x170 (PIN_INPUT_PULLUP | MUX_MODE0)    /* uart0_rxd.uart0_rxd */
+                       0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
+               >;
+       };
+
+       uart1_pins: pinmux_uart1_pins {
+               pinctrl-single,pins = <
+                       0x178 (PIN_INPUT | MUX_MODE0)           /* uart1_ctsn.uart1_ctsn */
+                       0x17C (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart1_rtsn.uart1_rtsn */
+                       0x180 (PIN_INPUT_PULLUP | MUX_MODE0)    /* uart1_rxd.uart1_rxd */
+                       0x184 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart1_txd.uart1_txd */
+               >;
+       };
+
+       clkout2_pin: pinmux_clkout2_pin {
+               pinctrl-single,pins = <
+                       0x1b4 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr1.clkout2 */
+               >;
+       };
+
+       nandflash_pins_s0: nandflash_pins_s0 {
+               pinctrl-single,pins = <
+                       0x0 (PIN_INPUT_PULLUP | MUX_MODE0)      /* gpmc_ad0.gpmc_ad0 */
+                       0x4 (PIN_INPUT_PULLUP | MUX_MODE0)      /* gpmc_ad1.gpmc_ad1 */
+                       0x8 (PIN_INPUT_PULLUP | MUX_MODE0)      /* gpmc_ad2.gpmc_ad2 */
+                       0xc (PIN_INPUT_PULLUP | MUX_MODE0)      /* gpmc_ad3.gpmc_ad3 */
+                       0x10 (PIN_INPUT_PULLUP | MUX_MODE0)     /* gpmc_ad4.gpmc_ad4 */
+                       0x14 (PIN_INPUT_PULLUP | MUX_MODE0)     /* gpmc_ad5.gpmc_ad5 */
+                       0x18 (PIN_INPUT_PULLUP | MUX_MODE0)     /* gpmc_ad6.gpmc_ad6 */
+                       0x1c (PIN_INPUT_PULLUP | MUX_MODE0)     /* gpmc_ad7.gpmc_ad7 */
+                       0x70 (PIN_INPUT_PULLUP | MUX_MODE0)     /* gpmc_wait0.gpmc_wait0 */
+                       0x74 (PIN_INPUT_PULLUP | MUX_MODE7)     /* gpmc_wpn.gpio0_30 */
+                       0x7c (PIN_OUTPUT | MUX_MODE0)           /* gpmc_csn0.gpmc_csn0  */
+                       0x90 (PIN_OUTPUT | MUX_MODE0)           /* gpmc_advn_ale.gpmc_advn_ale */
+                       0x94 (PIN_OUTPUT | MUX_MODE0)           /* gpmc_oen_ren.gpmc_oen_ren */
+                       0x98 (PIN_OUTPUT | MUX_MODE0)           /* gpmc_wen.gpmc_wen */
+                       0x9c (PIN_OUTPUT | MUX_MODE0)           /* gpmc_be0n_cle.gpmc_be0n_cle */
+               >;
+       };
+
+       ecap0_pins: backlight_pins {
+               pinctrl-single,pins = <
+                       0x164 0x0       /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */
+               >;
+       };
+
+       cpsw_default: cpsw_default {
+               pinctrl-single,pins = <
+                       /* Slave 1 */
+                       0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_tctl */
+                       0x118 (PIN_INPUT_PULLDOWN | MUX_MODE2)  /* mii1_rxdv.rgmii1_rctl */
+                       0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd3.rgmii1_td3 */
+                       0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd2.rgmii1_td2 */
+                       0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_td1 */
+                       0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_td0 */
+                       0x12c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txclk.rgmii1_tclk */
+                       0x130 (PIN_INPUT_PULLDOWN | MUX_MODE2)  /* mii1_rxclk.rgmii1_rclk */
+                       0x134 (PIN_INPUT_PULLDOWN | MUX_MODE2)  /* mii1_rxd3.rgmii1_rd3 */
+                       0x138 (PIN_INPUT_PULLDOWN | MUX_MODE2)  /* mii1_rxd2.rgmii1_rd2 */
+                       0x13c (PIN_INPUT_PULLDOWN | MUX_MODE2)  /* mii1_rxd1.rgmii1_rd1 */
+                       0x140 (PIN_INPUT_PULLDOWN | MUX_MODE2)  /* mii1_rxd0.rgmii1_rd0 */
+               >;
+       };
+
+       cpsw_sleep: cpsw_sleep {
+               pinctrl-single,pins = <
+                       /* Slave 1 reset value */
+                       0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                       0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                       0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                       0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                       0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                       0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                       0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                       0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                       0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                       0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                       0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                       0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+               >;
+       };
+
+       davinci_mdio_default: davinci_mdio_default {
+               pinctrl-single,pins = <
+                       /* MDIO */
+                       0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)    /* mdio_data.mdio_data */
+                       0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0)                   /* mdio_clk.mdio_clk */
+               >;
+       };
+
+       davinci_mdio_sleep: davinci_mdio_sleep {
+               pinctrl-single,pins = <
+                       /* MDIO reset value */
+                       0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                       0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
+               >;
+       };
+
+       mmc1_pins: pinmux_mmc1_pins {
+               pinctrl-single,pins = <
+                       0x160 (PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */
+               >;
+       };
+
+       mmc3_pins: pinmux_mmc3_pins {
+               pinctrl-single,pins = <
+                       0x44 (PIN_INPUT_PULLUP | MUX_MODE3)     /* gpmc_a1.mmc2_dat0, INPUT_PULLUP | MODE3 */
+                       0x48 (PIN_INPUT_PULLUP | MUX_MODE3)     /* gpmc_a2.mmc2_dat1, INPUT_PULLUP | MODE3 */
+                       0x4C (PIN_INPUT_PULLUP | MUX_MODE3)     /* gpmc_a3.mmc2_dat2, INPUT_PULLUP | MODE3 */
+                       0x78 (PIN_INPUT_PULLUP | MUX_MODE3)     /* gpmc_ben1.mmc2_dat3, INPUT_PULLUP | MODE3 */
+                       0x88 (PIN_INPUT_PULLUP | MUX_MODE3)     /* gpmc_csn3.mmc2_cmd, INPUT_PULLUP | MODE3 */
+                       0x8C (PIN_INPUT_PULLUP | MUX_MODE3)     /* gpmc_clk.mmc2_clk, INPUT_PULLUP | MODE3 */
+               >;
+       };
+
+       wlan_pins: pinmux_wlan_pins {
+               pinctrl-single,pins = <
+                       0x40 (PIN_OUTPUT_PULLDOWN | MUX_MODE7)  /* gpmc_a0.gpio1_16 */
+                       0x19C (PIN_INPUT | MUX_MODE7)           /* mcasp0_ahclkr.gpio3_17 */
+                       0x1AC (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* mcasp0_ahclkx.gpio3_21 */
+               >;
+       };
+
+       lcd_pins_s0: lcd_pins_s0 {
+               pinctrl-single,pins = <
+                       0x20 (PIN_OUTPUT | MUX_MODE1)           /* gpmc_ad8.lcd_data23 */
+                       0x24 (PIN_OUTPUT | MUX_MODE1)           /* gpmc_ad9.lcd_data22 */
+                       0x28 (PIN_OUTPUT | MUX_MODE1)           /* gpmc_ad10.lcd_data21 */
+                       0x2c (PIN_OUTPUT | MUX_MODE1)           /* gpmc_ad11.lcd_data20 */
+                       0x30 (PIN_OUTPUT | MUX_MODE1)           /* gpmc_ad12.lcd_data19 */
+                       0x34 (PIN_OUTPUT | MUX_MODE1)           /* gpmc_ad13.lcd_data18 */
+                       0x38 (PIN_OUTPUT | MUX_MODE1)           /* gpmc_ad14.lcd_data17 */
+                       0x3c (PIN_OUTPUT | MUX_MODE1)           /* gpmc_ad15.lcd_data16 */
+                       0xa0 (PIN_OUTPUT | MUX_MODE0)           /* lcd_data0.lcd_data0 */
+                       0xa4 (PIN_OUTPUT | MUX_MODE0)           /* lcd_data1.lcd_data1 */
+                       0xa8 (PIN_OUTPUT | MUX_MODE0)           /* lcd_data2.lcd_data2 */
+                       0xac (PIN_OUTPUT | MUX_MODE0)           /* lcd_data3.lcd_data3 */
+                       0xb0 (PIN_OUTPUT | MUX_MODE0)           /* lcd_data4.lcd_data4 */
+                       0xb4 (PIN_OUTPUT | MUX_MODE0)           /* lcd_data5.lcd_data5 */
+                       0xb8 (PIN_OUTPUT | MUX_MODE0)           /* lcd_data6.lcd_data6 */
+                       0xbc (PIN_OUTPUT | MUX_MODE0)           /* lcd_data7.lcd_data7 */
+                       0xc0 (PIN_OUTPUT | MUX_MODE0)           /* lcd_data8.lcd_data8 */
+                       0xc4 (PIN_OUTPUT | MUX_MODE0)           /* lcd_data9.lcd_data9 */
+                       0xc8 (PIN_OUTPUT | MUX_MODE0)           /* lcd_data10.lcd_data10 */
+                       0xcc (PIN_OUTPUT | MUX_MODE0)           /* lcd_data11.lcd_data11 */
+                       0xd0 (PIN_OUTPUT | MUX_MODE0)           /* lcd_data12.lcd_data12 */
+                       0xd4 (PIN_OUTPUT | MUX_MODE0)           /* lcd_data13.lcd_data13 */
+                       0xd8 (PIN_OUTPUT | MUX_MODE0)           /* lcd_data14.lcd_data14 */
+                       0xdc (PIN_OUTPUT | MUX_MODE0)           /* lcd_data15.lcd_data15 */
+                       0xe0 (PIN_OUTPUT | MUX_MODE0)           /* lcd_vsync.lcd_vsync */
+                       0xe4 (PIN_OUTPUT | MUX_MODE0)           /* lcd_hsync.lcd_hsync */
+                       0xe8 (PIN_OUTPUT | MUX_MODE0)           /* lcd_pclk.lcd_pclk */
+                       0xec (PIN_OUTPUT | MUX_MODE0)           /* lcd_ac_bias_en.lcd_ac_bias_en */
+               >;
+       };
+
+       am335x_evm_audio_pins: am335x_evm_audio_pins {
+               pinctrl-single,pins = <
+                       0x10c (PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_crs.mcasp1_aclkx */
+                       0x110 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_rxerr.mcasp1_fsx */
+                       0x108 (PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* mii1_col.mcasp1_axr2 */
+                       0x144 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* rmii1_ref_clk.mcasp1_axr3 */
+               >;
+       };
+
+       dcan1_pins_default: dcan1_pins_default {
+               pinctrl-single,pins = <
+                       0x168 (PIN_OUTPUT | MUX_MODE2) /* uart0_ctsn.d_can1_tx */
+                       0x16c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* uart0_rtsn.d_can1_rx */
+               >;
+       };
+};
+
+&uart0 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&uart0_pins>;
+
+       status = "okay";
+};
+
+&uart1 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&uart1_pins>;
+
+       status = "okay";
+};
+
+&i2c0 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&i2c0_pins>;
+
+       status = "okay";
+       clock-frequency = <400000>;
+
+       tps: tps@2d {
+               reg = <0x2d>;
+       };
+};
+
+&usb {
+       status = "okay";
+};
+
+&usb_ctrl_mod {
+       status = "okay";
+};
+
+&usb0_phy {
+       status = "okay";
+};
+
+&usb1_phy {
+       status = "okay";
+};
+
+&usb0 {
+       status = "okay";
+};
+
+&usb1 {
+       status = "okay";
+       dr_mode = "host";
+};
+
+&cppi41dma  {
+       status = "okay";
+};
+
+&i2c1 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&i2c1_pins>;
+
+       status = "okay";
+       clock-frequency = <100000>;
+
+       lis331dlh: lis331dlh@18 {
+               compatible = "st,lis331dlh", "st,lis3lv02d";
+               reg = <0x18>;
+               Vdd-supply = <&lis3_reg>;
+               Vdd_IO-supply = <&lis3_reg>;
+
+               st,click-single-x;
+               st,click-single-y;
+               st,click-single-z;
+               st,click-thresh-x = <10>;
+               st,click-thresh-y = <10>;
+               st,click-thresh-z = <10>;
+               st,irq1-click;
+               st,irq2-click;
+               st,wakeup-x-lo;
+               st,wakeup-x-hi;
+               st,wakeup-y-lo;
+               st,wakeup-y-hi;
+               st,wakeup-z-lo;
+               st,wakeup-z-hi;
+               st,min-limit-x = <120>;
+               st,min-limit-y = <120>;
+               st,min-limit-z = <140>;
+               st,max-limit-x = <550>;
+               st,max-limit-y = <550>;
+               st,max-limit-z = <750>;
+       };
+
+       tsl2550: tsl2550@39 {
+               compatible = "taos,tsl2550";
+               reg = <0x39>;
+       };
+
+       tmp275: tmp275@48 {
+               compatible = "ti,tmp275";
+               reg = <0x48>;
+       };
+
+       tlv320aic3106: tlv320aic3106@1b {
+               compatible = "ti,tlv320aic3106";
+               reg = <0x1b>;
+               status = "okay";
+
+               /* Regulators */
+               AVDD-supply = <&vaux2_reg>;
+               IOVDD-supply = <&vaux2_reg>;
+               DRVDD-supply = <&vaux2_reg>;
+               DVDD-supply = <&vbat>;
+       };
+};
+
+&lcdc {
+       status = "okay";
+};
+
+&elm {
+       status = "okay";
+};
+
+&epwmss0 {
+       status = "okay";
+
+       ecap0: ecap@48300100 {
+               status = "okay";
+               pinctrl-names = "default";
+               pinctrl-0 = <&ecap0_pins>;
+       };
+};
+
+&gpmc {
+       status = "okay";
+       pinctrl-names = "default";
+       pinctrl-0 = <&nandflash_pins_s0>;
+       ranges = <0 0 0x08000000 0x1000000>;    /* CS0: 16MB for NAND */
+       nand@0,0 {
+               reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
+               ti,nand-ecc-opt = "bch8";
+               ti,elm-id = <&elm>;
+               nand-bus-width = <8>;
+               gpmc,device-width = <1>;
+               gpmc,sync-clk-ps = <0>;
+               gpmc,cs-on-ns = <0>;
+               gpmc,cs-rd-off-ns = <44>;
+               gpmc,cs-wr-off-ns = <44>;
+               gpmc,adv-on-ns = <6>;
+               gpmc,adv-rd-off-ns = <34>;
+               gpmc,adv-wr-off-ns = <44>;
+               gpmc,we-on-ns = <0>;
+               gpmc,we-off-ns = <40>;
+               gpmc,oe-on-ns = <0>;
+               gpmc,oe-off-ns = <54>;
+               gpmc,access-ns = <64>;
+               gpmc,rd-cycle-ns = <82>;
+               gpmc,wr-cycle-ns = <82>;
+               gpmc,wait-on-read = "true";
+               gpmc,wait-on-write = "true";
+               gpmc,bus-turnaround-ns = <0>;
+               gpmc,cycle2cycle-delay-ns = <0>;
+               gpmc,clk-activation-ns = <0>;
+               gpmc,wait-monitoring-ns = <0>;
+               gpmc,wr-access-ns = <40>;
+               gpmc,wr-data-mux-bus-ns = <0>;
+               /* MTD partition table */
+               /* All SPL-* partitions are sized to minimal length
+                * which can be independently programmable. For
+                * NAND flash this is equal to size of erase-block */
+               #address-cells = <1>;
+               #size-cells = <1>;
+               partition@0 {
+                       label = "NAND.SPL";
+                       reg = <0x00000000 0x000020000>;
+               };
+               partition@1 {
+                       label = "NAND.SPL.backup1";
+                       reg = <0x00020000 0x00020000>;
+               };
+               partition@2 {
+                       label = "NAND.SPL.backup2";
+                       reg = <0x00040000 0x00020000>;
+               };
+               partition@3 {
+                       label = "NAND.SPL.backup3";
+                       reg = <0x00060000 0x00020000>;
+               };
+               partition@4 {
+                       label = "NAND.u-boot-spl-os";
+                       reg = <0x00080000 0x00040000>;
+               };
+               partition@5 {
+                       label = "NAND.u-boot";
+                       reg = <0x000C0000 0x00100000>;
+               };
+               partition@6 {
+                       label = "NAND.u-boot-env";
+                       reg = <0x001C0000 0x00020000>;
+               };
+               partition@7 {
+                       label = "NAND.u-boot-env.backup1";
+                       reg = <0x001E0000 0x00020000>;
+               };
+               partition@8 {
+                       label = "NAND.kernel";
+                       reg = <0x00200000 0x00800000>;
+               };
+               partition@9 {
+                       label = "NAND.file-system";
+                       reg = <0x00A00000 0x0F600000>;
+               };
+       };
+};
+
+#include "tps65910.dtsi"
+
+&mcasp1 {
+               pinctrl-names = "default";
+               pinctrl-0 = <&am335x_evm_audio_pins>;
+
+               status = "okay";
+
+               op-mode = <0>;          /* MCASP_IIS_MODE */
+               tdm-slots = <2>;
+               /* 4 serializers */
+               serial-dir = <  /* 0: INACTIVE, 1: TX, 2: RX */
+                       0 0 1 2
+               >;
+               tx-num-evt = <32>;
+               rx-num-evt = <32>;
+};
+
+&tps {
+       vcc1-supply = <&vbat>;
+       vcc2-supply = <&vbat>;
+       vcc3-supply = <&vbat>;
+       vcc4-supply = <&vbat>;
+       vcc5-supply = <&vbat>;
+       vcc6-supply = <&vbat>;
+       vcc7-supply = <&vbat>;
+       vccio-supply = <&vbat>;
+
+       regulators {
+               vrtc_reg: regulator@0 {
+                       regulator-always-on;
+               };
+
+               vio_reg: regulator@1 {
+                       regulator-always-on;
+               };
+
+               vdd1_reg: regulator@2 {
+                       /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
+                       regulator-name = "vdd_mpu";
+                       regulator-min-microvolt = <912500>;
+                       regulator-max-microvolt = <1312500>;
+                       regulator-boot-on;
+                       regulator-always-on;
+               };
+
+               vdd2_reg: regulator@3 {
+                       /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
+                       regulator-name = "vdd_core";
+                       regulator-min-microvolt = <912500>;
+                       regulator-max-microvolt = <1150000>;
+                       regulator-boot-on;
+                       regulator-always-on;
+               };
+
+               vdd3_reg: regulator@4 {
+                       regulator-always-on;
+               };
+
+               vdig1_reg: regulator@5 {
+                       regulator-always-on;
+               };
+
+               vdig2_reg: regulator@6 {
+                       regulator-always-on;
+               };
+
+               vpll_reg: regulator@7 {
+                       regulator-always-on;
+               };
+
+               vdac_reg: regulator@8 {
+                       regulator-always-on;
+               };
+
+               vaux1_reg: regulator@9 {
+                       regulator-always-on;
+               };
+
+               vaux2_reg: regulator@10 {
+                       regulator-always-on;
+               };
+
+               vaux33_reg: regulator@11 {
+                       regulator-always-on;
+               };
+
+               vmmc_reg: regulator@12 {
+                       regulator-min-microvolt = <1800000>;
+                       regulator-max-microvolt = <3300000>;
+                       regulator-always-on;
+               };
+       };
+};
+
+&mac {
+       pinctrl-names = "default", "sleep";
+       pinctrl-0 = <&cpsw_default>;
+       pinctrl-1 = <&cpsw_sleep>;
+       status = "okay";
+};
+
+&davinci_mdio {
+       pinctrl-names = "default", "sleep";
+       pinctrl-0 = <&davinci_mdio_default>;
+       pinctrl-1 = <&davinci_mdio_sleep>;
+       status = "okay";
+};
+
+&cpsw_emac0 {
+       phy_id = <&davinci_mdio>, <0>;
+       phy-mode = "rgmii-txid";
+};
+
+&cpsw_emac1 {
+       phy_id = <&davinci_mdio>, <1>;
+       phy-mode = "rgmii-txid";
+};
+
+&tscadc {
+       status = "okay";
+       tsc {
+               ti,wires = <4>;
+               ti,x-plate-resistance = <200>;
+               ti,coordinate-readouts = <5>;
+               ti,wire-config = <0x00 0x11 0x22 0x33>;
+               ti,charge-delay = <0x400>;
+       };
+
+       adc {
+               ti,adc-channels = <4 5 6 7>;
+       };
+};
+
+&mmc1 {
+       status = "okay";
+       vmmc-supply = <&vmmc_reg>;
+       bus-width = <4>;
+       pinctrl-names = "default";
+       pinctrl-0 = <&mmc1_pins>;
+       cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>;
+};
+
+&mmc3 {
+       /* these are on the crossbar and are outlined in the
+          xbar-event-map element */
+       dmas = <&edma 12
+               &edma 13>;
+       dma-names = "tx", "rx";
+       status = "okay";
+       vmmc-supply = <&wlan_en_reg>;
+       bus-width = <4>;
+       pinctrl-names = "default";
+       pinctrl-0 = <&mmc3_pins &wlan_pins>;
+       ti,non-removable;
+       ti,needs-special-hs-handling;
+       cap-power-off-card;
+       keep-power-in-suspend;
+
+       #address-cells = <1>;
+       #size-cells = <0>;
+       wlcore: wlcore@0 {
+               compatible = "ti,wl1835";
+               reg = <2>;
+               interrupt-parent = <&gpio3>;
+               interrupts = <17 IRQ_TYPE_LEVEL_HIGH>;
+       };
+};
+
+&edma {
+       ti,edma-xbar-event-map = /bits/ 16 <1 12
+                                           2 13>;
+};
+
+&sham {
+       status = "okay";
+};
+
+&aes {
+       status = "okay";
+};
+
+&dcan1 {
+       status = "disabled";    /* Enable only if Profile 1 is selected */
+       pinctrl-names = "default";
+       pinctrl-0 = <&dcan1_pins_default>;
+};
diff --git a/arch/arm/dts/am33xx-clocks.dtsi b/arch/arm/dts/am33xx-clocks.dtsi
new file mode 100644 (file)
index 0000000..afb4b3a
--- /dev/null
@@ -0,0 +1,646 @@
+/*
+ * Device Tree Source for AM33xx clock data
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+&scm_clocks {
+       sys_clkin_ck: sys_clkin_ck {
+               #clock-cells = <0>;
+               compatible = "ti,mux-clock";
+               clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>;
+               ti,bit-shift = <22>;
+               reg = <0x0040>;
+       };
+
+       adc_tsc_fck: adc_tsc_fck {
+               #clock-cells = <0>;
+               compatible = "fixed-factor-clock";
+               clocks = <&sys_clkin_ck>;
+               clock-mult = <1>;
+               clock-div = <1>;
+       };
+
+       dcan0_fck: dcan0_fck {
+               #clock-cells = <0>;
+               compatible = "fixed-factor-clock";
+               clocks = <&sys_clkin_ck>;
+               clock-mult = <1>;
+               clock-div = <1>;
+       };
+
+       dcan1_fck: dcan1_fck {
+               #clock-cells = <0>;
+               compatible = "fixed-factor-clock";
+               clocks = <&sys_clkin_ck>;
+               clock-mult = <1>;
+               clock-div = <1>;
+       };
+
+       mcasp0_fck: mcasp0_fck {
+               #clock-cells = <0>;
+               compatible = "fixed-factor-clock";
+               clocks = <&sys_clkin_ck>;
+               clock-mult = <1>;
+               clock-div = <1>;
+       };
+
+       mcasp1_fck: mcasp1_fck {
+               #clock-cells = <0>;
+               compatible = "fixed-factor-clock";
+               clocks = <&sys_clkin_ck>;
+               clock-mult = <1>;
+               clock-div = <1>;
+       };
+
+       smartreflex0_fck: smartreflex0_fck {
+               #clock-cells = <0>;
+               compatible = "fixed-factor-clock";
+               clocks = <&sys_clkin_ck>;
+               clock-mult = <1>;
+               clock-div = <1>;
+       };
+
+       smartreflex1_fck: smartreflex1_fck {
+               #clock-cells = <0>;
+               compatible = "fixed-factor-clock";
+               clocks = <&sys_clkin_ck>;
+               clock-mult = <1>;
+               clock-div = <1>;
+       };
+
+       sha0_fck: sha0_fck {
+               #clock-cells = <0>;
+               compatible = "fixed-factor-clock";
+               clocks = <&sys_clkin_ck>;
+               clock-mult = <1>;
+               clock-div = <1>;
+       };
+
+       aes0_fck: aes0_fck {
+               #clock-cells = <0>;
+               compatible = "fixed-factor-clock";
+               clocks = <&sys_clkin_ck>;
+               clock-mult = <1>;
+               clock-div = <1>;
+       };
+
+       rng_fck: rng_fck {
+               #clock-cells = <0>;
+               compatible = "fixed-factor-clock";
+               clocks = <&sys_clkin_ck>;
+               clock-mult = <1>;
+               clock-div = <1>;
+       };
+
+       ehrpwm0_tbclk: ehrpwm0_tbclk@44e10664 {
+               #clock-cells = <0>;
+               compatible = "ti,gate-clock";
+               clocks = <&l4ls_gclk>;
+               ti,bit-shift = <0>;
+               reg = <0x0664>;
+       };
+
+       ehrpwm1_tbclk: ehrpwm1_tbclk@44e10664 {
+               #clock-cells = <0>;
+               compatible = "ti,gate-clock";
+               clocks = <&l4ls_gclk>;
+               ti,bit-shift = <1>;
+               reg = <0x0664>;
+       };
+
+       ehrpwm2_tbclk: ehrpwm2_tbclk@44e10664 {
+               #clock-cells = <0>;
+               compatible = "ti,gate-clock";
+               clocks = <&l4ls_gclk>;
+               ti,bit-shift = <2>;
+               reg = <0x0664>;
+       };
+};
+&prcm_clocks {
+       clk_32768_ck: clk_32768_ck {
+               #clock-cells = <0>;
+               compatible = "fixed-clock";
+               clock-frequency = <32768>;
+       };
+
+       clk_rc32k_ck: clk_rc32k_ck {
+               #clock-cells = <0>;
+               compatible = "fixed-clock";
+               clock-frequency = <32000>;
+       };
+
+       virt_19200000_ck: virt_19200000_ck {
+               #clock-cells = <0>;
+               compatible = "fixed-clock";
+               clock-frequency = <19200000>;
+       };
+
+       virt_24000000_ck: virt_24000000_ck {
+               #clock-cells = <0>;
+               compatible = "fixed-clock";
+               clock-frequency = <24000000>;
+       };
+
+       virt_25000000_ck: virt_25000000_ck {
+               #clock-cells = <0>;
+               compatible = "fixed-clock";
+               clock-frequency = <25000000>;
+       };
+
+       virt_26000000_ck: virt_26000000_ck {
+               #clock-cells = <0>;
+               compatible = "fixed-clock";
+               clock-frequency = <26000000>;
+       };
+
+       tclkin_ck: tclkin_ck {
+               #clock-cells = <0>;
+               compatible = "fixed-clock";
+               clock-frequency = <12000000>;
+       };
+
+       dpll_core_ck: dpll_core_ck {
+               #clock-cells = <0>;
+               compatible = "ti,am3-dpll-core-clock";
+               clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
+               reg = <0x0490>, <0x045c>, <0x0468>;
+       };
+
+       dpll_core_x2_ck: dpll_core_x2_ck {
+               #clock-cells = <0>;
+               compatible = "ti,am3-dpll-x2-clock";
+               clocks = <&dpll_core_ck>;
+       };
+
+       dpll_core_m4_ck: dpll_core_m4_ck {
+               #clock-cells = <0>;
+               compatible = "ti,divider-clock";
+               clocks = <&dpll_core_x2_ck>;
+               ti,max-div = <31>;
+               reg = <0x0480>;
+               ti,index-starts-at-one;
+       };
+
+       dpll_core_m5_ck: dpll_core_m5_ck {
+               #clock-cells = <0>;
+               compatible = "ti,divider-clock";
+               clocks = <&dpll_core_x2_ck>;
+               ti,max-div = <31>;
+               reg = <0x0484>;
+               ti,index-starts-at-one;
+       };
+
+       dpll_core_m6_ck: dpll_core_m6_ck {
+               #clock-cells = <0>;
+               compatible = "ti,divider-clock";
+               clocks = <&dpll_core_x2_ck>;
+               ti,max-div = <31>;
+               reg = <0x04d8>;
+               ti,index-starts-at-one;
+       };
+
+       dpll_mpu_ck: dpll_mpu_ck {
+               #clock-cells = <0>;
+               compatible = "ti,am3-dpll-clock";
+               clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
+               reg = <0x0488>, <0x0420>, <0x042c>;
+       };
+
+       dpll_mpu_m2_ck: dpll_mpu_m2_ck {
+               #clock-cells = <0>;
+               compatible = "ti,divider-clock";
+               clocks = <&dpll_mpu_ck>;
+               ti,max-div = <31>;
+               reg = <0x04a8>;
+               ti,index-starts-at-one;
+       };
+
+       dpll_ddr_ck: dpll_ddr_ck {
+               #clock-cells = <0>;
+               compatible = "ti,am3-dpll-no-gate-clock";
+               clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
+               reg = <0x0494>, <0x0434>, <0x0440>;
+       };
+
+       dpll_ddr_m2_ck: dpll_ddr_m2_ck {
+               #clock-cells = <0>;
+               compatible = "ti,divider-clock";
+               clocks = <&dpll_ddr_ck>;
+               ti,max-div = <31>;
+               reg = <0x04a0>;
+               ti,index-starts-at-one;
+       };
+
+       dpll_ddr_m2_div2_ck: dpll_ddr_m2_div2_ck {
+               #clock-cells = <0>;
+               compatible = "fixed-factor-clock";
+               clocks = <&dpll_ddr_m2_ck>;
+               clock-mult = <1>;
+               clock-div = <2>;
+       };
+
+       dpll_disp_ck: dpll_disp_ck {
+               #clock-cells = <0>;
+               compatible = "ti,am3-dpll-no-gate-clock";
+               clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
+               reg = <0x0498>, <0x0448>, <0x0454>;
+       };
+
+       dpll_disp_m2_ck: dpll_disp_m2_ck {
+               #clock-cells = <0>;
+               compatible = "ti,divider-clock";
+               clocks = <&dpll_disp_ck>;
+               ti,max-div = <31>;
+               reg = <0x04a4>;
+               ti,index-starts-at-one;
+               ti,set-rate-parent;
+       };
+
+       dpll_per_ck: dpll_per_ck {
+               #clock-cells = <0>;
+               compatible = "ti,am3-dpll-no-gate-j-type-clock";
+               clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
+               reg = <0x048c>, <0x0470>, <0x049c>;
+       };
+
+       dpll_per_m2_ck: dpll_per_m2_ck {
+               #clock-cells = <0>;
+               compatible = "ti,divider-clock";
+               clocks = <&dpll_per_ck>;
+               ti,max-div = <31>;
+               reg = <0x04ac>;
+               ti,index-starts-at-one;
+       };
+
+       dpll_per_m2_div4_wkupdm_ck: dpll_per_m2_div4_wkupdm_ck {
+               #clock-cells = <0>;
+               compatible = "fixed-factor-clock";
+               clocks = <&dpll_per_m2_ck>;
+               clock-mult = <1>;
+               clock-div = <4>;
+       };
+
+       dpll_per_m2_div4_ck: dpll_per_m2_div4_ck {
+               #clock-cells = <0>;
+               compatible = "fixed-factor-clock";
+               clocks = <&dpll_per_m2_ck>;
+               clock-mult = <1>;
+               clock-div = <4>;
+       };
+
+       cefuse_fck: cefuse_fck {
+               #clock-cells = <0>;
+               compatible = "ti,gate-clock";
+               clocks = <&sys_clkin_ck>;
+               ti,bit-shift = <1>;
+               reg = <0x0a20>;
+       };
+
+       clk_24mhz: clk_24mhz {
+               #clock-cells = <0>;
+               compatible = "fixed-factor-clock";
+               clocks = <&dpll_per_m2_ck>;
+               clock-mult = <1>;
+               clock-div = <8>;
+       };
+
+       clkdiv32k_ck: clkdiv32k_ck {
+               #clock-cells = <0>;
+               compatible = "fixed-factor-clock";
+               clocks = <&clk_24mhz>;
+               clock-mult = <1>;
+               clock-div = <732>;
+       };
+
+       clkdiv32k_ick: clkdiv32k_ick {
+               #clock-cells = <0>;
+               compatible = "ti,gate-clock";
+               clocks = <&clkdiv32k_ck>;
+               ti,bit-shift = <1>;
+               reg = <0x014c>;
+       };
+
+       l3_gclk: l3_gclk {
+               #clock-cells = <0>;
+               compatible = "fixed-factor-clock";
+               clocks = <&dpll_core_m4_ck>;
+               clock-mult = <1>;
+               clock-div = <1>;
+       };
+
+       pruss_ocp_gclk: pruss_ocp_gclk {
+               #clock-cells = <0>;
+               compatible = "ti,mux-clock";
+               clocks = <&l3_gclk>, <&dpll_disp_m2_ck>;
+               reg = <0x0530>;
+       };
+
+       mmu_fck: mmu_fck {
+               #clock-cells = <0>;
+               compatible = "ti,gate-clock";
+               clocks = <&dpll_core_m4_ck>;
+               ti,bit-shift = <1>;
+               reg = <0x0914>;
+       };
+
+       timer1_fck: timer1_fck {
+               #clock-cells = <0>;
+               compatible = "ti,mux-clock";
+               clocks = <&sys_clkin_ck>, <&clkdiv32k_ick>, <&tclkin_ck>, <&clk_rc32k_ck>, <&clk_32768_ck>;
+               reg = <0x0528>;
+       };
+
+       timer2_fck: timer2_fck {
+               #clock-cells = <0>;
+               compatible = "ti,mux-clock";
+               clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
+               reg = <0x0508>;
+       };
+
+       timer3_fck: timer3_fck {
+               #clock-cells = <0>;
+               compatible = "ti,mux-clock";
+               clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
+               reg = <0x050c>;
+       };
+
+       timer4_fck: timer4_fck {
+               #clock-cells = <0>;
+               compatible = "ti,mux-clock";
+               clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
+               reg = <0x0510>;
+       };
+
+       timer5_fck: timer5_fck {
+               #clock-cells = <0>;
+               compatible = "ti,mux-clock";
+               clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
+               reg = <0x0518>;
+       };
+
+       timer6_fck: timer6_fck {
+               #clock-cells = <0>;
+               compatible = "ti,mux-clock";
+               clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
+               reg = <0x051c>;
+       };
+
+       timer7_fck: timer7_fck {
+               #clock-cells = <0>;
+               compatible = "ti,mux-clock";
+               clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
+               reg = <0x0504>;
+       };
+
+       usbotg_fck: usbotg_fck {
+               #clock-cells = <0>;
+               compatible = "ti,gate-clock";
+               clocks = <&dpll_per_ck>;
+               ti,bit-shift = <8>;
+               reg = <0x047c>;
+       };
+
+       dpll_core_m4_div2_ck: dpll_core_m4_div2_ck {
+               #clock-cells = <0>;
+               compatible = "fixed-factor-clock";
+               clocks = <&dpll_core_m4_ck>;
+               clock-mult = <1>;
+               clock-div = <2>;
+       };
+
+       ieee5000_fck: ieee5000_fck {
+               #clock-cells = <0>;
+               compatible = "ti,gate-clock";
+               clocks = <&dpll_core_m4_div2_ck>;
+               ti,bit-shift = <1>;
+               reg = <0x00e4>;
+       };
+
+       wdt1_fck: wdt1_fck {
+               #clock-cells = <0>;
+               compatible = "ti,mux-clock";
+               clocks = <&clk_rc32k_ck>, <&clkdiv32k_ick>;
+               reg = <0x0538>;
+       };
+
+       l4_rtc_gclk: l4_rtc_gclk {
+               #clock-cells = <0>;
+               compatible = "fixed-factor-clock";
+               clocks = <&dpll_core_m4_ck>;
+               clock-mult = <1>;
+               clock-div = <2>;
+       };
+
+       l4hs_gclk: l4hs_gclk {
+               #clock-cells = <0>;
+               compatible = "fixed-factor-clock";
+               clocks = <&dpll_core_m4_ck>;
+               clock-mult = <1>;
+               clock-div = <1>;
+       };
+
+       l3s_gclk: l3s_gclk {
+               #clock-cells = <0>;
+               compatible = "fixed-factor-clock";
+               clocks = <&dpll_core_m4_div2_ck>;
+               clock-mult = <1>;
+               clock-div = <1>;
+       };
+
+       l4fw_gclk: l4fw_gclk {
+               #clock-cells = <0>;
+               compatible = "fixed-factor-clock";
+               clocks = <&dpll_core_m4_div2_ck>;
+               clock-mult = <1>;
+               clock-div = <1>;
+       };
+
+       l4ls_gclk: l4ls_gclk {
+               #clock-cells = <0>;
+               compatible = "fixed-factor-clock";
+               clocks = <&dpll_core_m4_div2_ck>;
+               clock-mult = <1>;
+               clock-div = <1>;
+       };
+
+       sysclk_div_ck: sysclk_div_ck {
+               #clock-cells = <0>;
+               compatible = "fixed-factor-clock";
+               clocks = <&dpll_core_m4_ck>;
+               clock-mult = <1>;
+               clock-div = <1>;
+       };
+
+       cpsw_125mhz_gclk: cpsw_125mhz_gclk {
+               #clock-cells = <0>;
+               compatible = "fixed-factor-clock";
+               clocks = <&dpll_core_m5_ck>;
+               clock-mult = <1>;
+               clock-div = <2>;
+       };
+
+       cpsw_cpts_rft_clk: cpsw_cpts_rft_clk {
+               #clock-cells = <0>;
+               compatible = "ti,mux-clock";
+               clocks = <&dpll_core_m5_ck>, <&dpll_core_m4_ck>;
+               reg = <0x0520>;
+       };
+
+       gpio0_dbclk_mux_ck: gpio0_dbclk_mux_ck {
+               #clock-cells = <0>;
+               compatible = "ti,mux-clock";
+               clocks = <&clk_rc32k_ck>, <&clk_32768_ck>, <&clkdiv32k_ick>;
+               reg = <0x053c>;
+       };
+
+       gpio0_dbclk: gpio0_dbclk {
+               #clock-cells = <0>;
+               compatible = "ti,gate-clock";
+               clocks = <&gpio0_dbclk_mux_ck>;
+               ti,bit-shift = <18>;
+               reg = <0x0408>;
+       };
+
+       gpio1_dbclk: gpio1_dbclk {
+               #clock-cells = <0>;
+               compatible = "ti,gate-clock";
+               clocks = <&clkdiv32k_ick>;
+               ti,bit-shift = <18>;
+               reg = <0x00ac>;
+       };
+
+       gpio2_dbclk: gpio2_dbclk {
+               #clock-cells = <0>;
+               compatible = "ti,gate-clock";
+               clocks = <&clkdiv32k_ick>;
+               ti,bit-shift = <18>;
+               reg = <0x00b0>;
+       };
+
+       gpio3_dbclk: gpio3_dbclk {
+               #clock-cells = <0>;
+               compatible = "ti,gate-clock";
+               clocks = <&clkdiv32k_ick>;
+               ti,bit-shift = <18>;
+               reg = <0x00b4>;
+       };
+
+       lcd_gclk: lcd_gclk {
+               #clock-cells = <0>;
+               compatible = "ti,mux-clock";
+               clocks = <&dpll_disp_m2_ck>, <&dpll_core_m5_ck>, <&dpll_per_m2_ck>;
+               reg = <0x0534>;
+               ti,set-rate-parent;
+       };
+
+       mmc_clk: mmc_clk {
+               #clock-cells = <0>;
+               compatible = "fixed-factor-clock";
+               clocks = <&dpll_per_m2_ck>;
+               clock-mult = <1>;
+               clock-div = <2>;
+       };
+
+       gfx_fclk_clksel_ck: gfx_fclk_clksel_ck {
+               #clock-cells = <0>;
+               compatible = "ti,mux-clock";
+               clocks = <&dpll_core_m4_ck>, <&dpll_per_m2_ck>;
+               ti,bit-shift = <1>;
+               reg = <0x052c>;
+       };
+
+       gfx_fck_div_ck: gfx_fck_div_ck {
+               #clock-cells = <0>;
+               compatible = "ti,divider-clock";
+               clocks = <&gfx_fclk_clksel_ck>;
+               reg = <0x052c>;
+               ti,max-div = <2>;
+       };
+
+       sysclkout_pre_ck: sysclkout_pre_ck {
+               #clock-cells = <0>;
+               compatible = "ti,mux-clock";
+               clocks = <&clk_32768_ck>, <&l3_gclk>, <&dpll_ddr_m2_ck>, <&dpll_per_m2_ck>, <&lcd_gclk>;
+               reg = <0x0700>;
+       };
+
+       clkout2_div_ck: clkout2_div_ck {
+               #clock-cells = <0>;
+               compatible = "ti,divider-clock";
+               clocks = <&sysclkout_pre_ck>;
+               ti,bit-shift = <3>;
+               ti,max-div = <8>;
+               reg = <0x0700>;
+       };
+
+       dbg_sysclk_ck: dbg_sysclk_ck {
+               #clock-cells = <0>;
+               compatible = "ti,gate-clock";
+               clocks = <&sys_clkin_ck>;
+               ti,bit-shift = <19>;
+               reg = <0x0414>;
+       };
+
+       dbg_clka_ck: dbg_clka_ck {
+               #clock-cells = <0>;
+               compatible = "ti,gate-clock";
+               clocks = <&dpll_core_m4_ck>;
+               ti,bit-shift = <30>;
+               reg = <0x0414>;
+       };
+
+       stm_pmd_clock_mux_ck: stm_pmd_clock_mux_ck {
+               #clock-cells = <0>;
+               compatible = "ti,mux-clock";
+               clocks = <&dbg_sysclk_ck>, <&dbg_clka_ck>;
+               ti,bit-shift = <22>;
+               reg = <0x0414>;
+       };
+
+       trace_pmd_clk_mux_ck: trace_pmd_clk_mux_ck {
+               #clock-cells = <0>;
+               compatible = "ti,mux-clock";
+               clocks = <&dbg_sysclk_ck>, <&dbg_clka_ck>;
+               ti,bit-shift = <20>;
+               reg = <0x0414>;
+       };
+
+       stm_clk_div_ck: stm_clk_div_ck {
+               #clock-cells = <0>;
+               compatible = "ti,divider-clock";
+               clocks = <&stm_pmd_clock_mux_ck>;
+               ti,bit-shift = <27>;
+               ti,max-div = <64>;
+               reg = <0x0414>;
+               ti,index-power-of-two;
+       };
+
+       trace_clk_div_ck: trace_clk_div_ck {
+               #clock-cells = <0>;
+               compatible = "ti,divider-clock";
+               clocks = <&trace_pmd_clk_mux_ck>;
+               ti,bit-shift = <24>;
+               ti,max-div = <64>;
+               reg = <0x0414>;
+               ti,index-power-of-two;
+       };
+
+       clkout2_ck: clkout2_ck {
+               #clock-cells = <0>;
+               compatible = "ti,gate-clock";
+               clocks = <&clkout2_div_ck>;
+               ti,bit-shift = <7>;
+               reg = <0x0700>;
+       };
+};
+
+&prcm_clockdomains {
+       clk_24mhz_clkdm: clk_24mhz_clkdm {
+               compatible = "ti,clockdomain";
+               clocks = <&clkdiv32k_ick>;
+       };
+};
index f9c5da9..21fcc44 100644 (file)
@@ -18,6 +18,9 @@
        interrupt-parent = <&intc>;
 
        aliases {
        interrupt-parent = <&intc>;
 
        aliases {
+               i2c0 = &i2c0;
+               i2c1 = &i2c1;
+               i2c2 = &i2c2;
                serial0 = &uart0;
                serial1 = &uart1;
                serial2 = &uart2;
                serial0 = &uart0;
                serial1 = &uart1;
                serial2 = &uart2;
@@ -30,6 +33,8 @@
                usb1 = &usb1;
                phy0 = &usb0_phy;
                phy1 = &usb1_phy;
                usb1 = &usb1;
                phy0 = &usb0_phy;
                phy1 = &usb1_phy;
+               ethernet0 = &cpsw_emac0;
+               ethernet1 = &cpsw_emac1;
        };
 
        cpus {
        };
 
        cpus {
                                275000  1125000
                        >;
                        voltage-tolerance = <2>; /* 2 percentage */
                                275000  1125000
                        >;
                        voltage-tolerance = <2>; /* 2 percentage */
+
+                       clocks = <&dpll_mpu_ck>;
+                       clock-names = "cpu";
+
                        clock-latency = <300000>; /* From omap-cpufreq driver */
                };
        };
 
                        clock-latency = <300000>; /* From omap-cpufreq driver */
                };
        };
 
+       pmu {
+               compatible = "arm,cortex-a8-pmu";
+               interrupts = <3>;
+       };
+
        /*
        /*
-        * The soc node represents the soc top level view. It is uses for IPs
+        * The soc node represents the soc top level view. It is used for IPs
         * that are not memory mapped in the MPU view or for the MPU itself.
         */
        soc {
         * that are not memory mapped in the MPU view or for the MPU itself.
         */
        soc {
                };
        };
 
                };
        };
 
-       am33xx_pinmux: pinmux@44e10800 {
-               compatible = "pinctrl-single";
-               reg = <0x44e10800 0x0238>;
-               #address-cells = <1>;
-               #size-cells = <0>;
-               pinctrl-single,register-width = <32>;
-               pinctrl-single,function-mask = <0x7f>;
-       };
-
        /*
         * XXX: Use a flat representation of the AM33XX interconnect.
        /*
         * XXX: Use a flat representation of the AM33XX interconnect.
-        * The real AM33XX interconnect network is quite complex.Since
-        * that will not bring real advantage to represent that in DT
+        * The real AM33XX interconnect network is quite complex. Since
+        * it will not bring real advantage to represent that in DT
         * for the moment, just use a fake OCP bus entry to represent
         * the whole bus hierarchy.
         */
         * for the moment, just use a fake OCP bus entry to represent
         * the whole bus hierarchy.
         */
                ranges;
                ti,hwmods = "l3_main";
 
                ranges;
                ti,hwmods = "l3_main";
 
+               l4_wkup: l4_wkup@44c00000 {
+                       compatible = "ti,am3-l4-wkup", "simple-bus";
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       ranges = <0 0x44c00000 0x280000>;
+
+                       prcm: prcm@200000 {
+                               compatible = "ti,am3-prcm";
+                               reg = <0x200000 0x4000>;
+
+                               prcm_clocks: clocks {
+                                       #address-cells = <1>;
+                                       #size-cells = <0>;
+                               };
+
+                               prcm_clockdomains: clockdomains {
+                               };
+                       };
+
+                       scm: scm@210000 {
+                               compatible = "ti,am3-scm", "simple-bus";
+                               reg = <0x210000 0x2000>;
+                               #address-cells = <1>;
+                               #size-cells = <1>;
+                               ranges = <0 0x210000 0x2000>;
+
+                               am33xx_pinmux: pinmux@800 {
+                                       compatible = "pinctrl-single";
+                                       reg = <0x800 0x238>;
+                                       #address-cells = <1>;
+                                       #size-cells = <0>;
+                                       pinctrl-single,register-width = <32>;
+                                       pinctrl-single,function-mask = <0x7f>;
+                               };
+
+                               scm_conf: scm_conf@0 {
+                                       compatible = "syscon";
+                                       reg = <0x0 0x800>;
+                                       #address-cells = <1>;
+                                       #size-cells = <1>;
+
+                                       scm_clocks: clocks {
+                                               #address-cells = <1>;
+                                               #size-cells = <0>;
+                                       };
+                               };
+
+                               scm_clockdomains: clockdomains {
+                               };
+                       };
+               };
+
                intc: interrupt-controller@48200000 {
                intc: interrupt-controller@48200000 {
-                       compatible = "ti,omap2-intc";
+                       compatible = "ti,am33xx-intc";
                        interrupt-controller;
                        #interrupt-cells = <1>;
                        interrupt-controller;
                        #interrupt-cells = <1>;
-                       ti,intc-size = <128>;
                        reg = <0x48200000 0x1000>;
                };
 
                        reg = <0x48200000 0x1000>;
                };
 
+               edma: edma@49000000 {
+                       compatible = "ti,edma3";
+                       ti,hwmods = "tpcc", "tptc0", "tptc1", "tptc2";
+                       reg =   <0x49000000 0x10000>,
+                               <0x44e10f90 0x40>;
+                       interrupts = <12 13 14>;
+                       #dma-cells = <1>;
+               };
+
                gpio0: gpio@44e07000 {
                        compatible = "ti,omap4-gpio";
                        ti,hwmods = "gpio1";
                        gpio-controller;
                        #gpio-cells = <2>;
                        interrupt-controller;
                gpio0: gpio@44e07000 {
                        compatible = "ti,omap4-gpio";
                        ti,hwmods = "gpio1";
                        gpio-controller;
                        #gpio-cells = <2>;
                        interrupt-controller;
-                       #interrupt-cells = <1>;
+                       #interrupt-cells = <2>;
                        reg = <0x44e07000 0x1000>;
                        interrupts = <96>;
                };
                        reg = <0x44e07000 0x1000>;
                        interrupts = <96>;
                };
                        gpio-controller;
                        #gpio-cells = <2>;
                        interrupt-controller;
                        gpio-controller;
                        #gpio-cells = <2>;
                        interrupt-controller;
-                       #interrupt-cells = <1>;
+                       #interrupt-cells = <2>;
                        reg = <0x4804c000 0x1000>;
                        interrupts = <98>;
                };
                        reg = <0x4804c000 0x1000>;
                        interrupts = <98>;
                };
                        gpio-controller;
                        #gpio-cells = <2>;
                        interrupt-controller;
                        gpio-controller;
                        #gpio-cells = <2>;
                        interrupt-controller;
-                       #interrupt-cells = <1>;
+                       #interrupt-cells = <2>;
                        reg = <0x481ac000 0x1000>;
                        interrupts = <32>;
                };
                        reg = <0x481ac000 0x1000>;
                        interrupts = <32>;
                };
                        gpio-controller;
                        #gpio-cells = <2>;
                        interrupt-controller;
                        gpio-controller;
                        #gpio-cells = <2>;
                        interrupt-controller;
-                       #interrupt-cells = <1>;
+                       #interrupt-cells = <2>;
                        reg = <0x481ae000 0x1000>;
                        interrupts = <62>;
                };
                        reg = <0x481ae000 0x1000>;
                        interrupts = <62>;
                };
                        reg = <0x44e09000 0x2000>;
                        interrupts = <72>;
                        status = "disabled";
                        reg = <0x44e09000 0x2000>;
                        interrupts = <72>;
                        status = "disabled";
+                       dmas = <&edma 26>, <&edma 27>;
+                       dma-names = "tx", "rx";
                };
 
                uart1: serial@48022000 {
                };
 
                uart1: serial@48022000 {
                        reg = <0x48022000 0x2000>;
                        interrupts = <73>;
                        status = "disabled";
                        reg = <0x48022000 0x2000>;
                        interrupts = <73>;
                        status = "disabled";
+                       dmas = <&edma 28>, <&edma 29>;
+                       dma-names = "tx", "rx";
                };
 
                uart2: serial@48024000 {
                };
 
                uart2: serial@48024000 {
                        reg = <0x48024000 0x2000>;
                        interrupts = <74>;
                        status = "disabled";
                        reg = <0x48024000 0x2000>;
                        interrupts = <74>;
                        status = "disabled";
+                       dmas = <&edma 30>, <&edma 31>;
+                       dma-names = "tx", "rx";
                };
 
                uart3: serial@481a6000 {
                };
 
                uart3: serial@481a6000 {
                        status = "disabled";
                };
 
                        status = "disabled";
                };
 
+               mmc1: mmc@48060000 {
+                       compatible = "ti,omap4-hsmmc";
+                       ti,hwmods = "mmc1";
+                       ti,dual-volt;
+                       ti,needs-special-reset;
+                       ti,needs-special-hs-handling;
+                       dmas = <&edma 24
+                               &edma 25>;
+                       dma-names = "tx", "rx";
+                       interrupts = <64>;
+                       interrupt-parent = <&intc>;
+                       reg = <0x48060000 0x1000>;
+                       status = "disabled";
+               };
+
+               mmc2: mmc@481d8000 {
+                       compatible = "ti,omap4-hsmmc";
+                       ti,hwmods = "mmc2";
+                       ti,needs-special-reset;
+                       dmas = <&edma 2
+                               &edma 3>;
+                       dma-names = "tx", "rx";
+                       interrupts = <28>;
+                       interrupt-parent = <&intc>;
+                       reg = <0x481d8000 0x1000>;
+                       status = "disabled";
+               };
+
+               mmc3: mmc@47810000 {
+                       compatible = "ti,omap4-hsmmc";
+                       ti,hwmods = "mmc3";
+                       ti,needs-special-reset;
+                       interrupts = <29>;
+                       interrupt-parent = <&intc>;
+                       reg = <0x47810000 0x1000>;
+                       status = "disabled";
+               };
+
+               hwspinlock: spinlock@480ca000 {
+                       compatible = "ti,omap4-hwspinlock";
+                       reg = <0x480ca000 0x1000>;
+                       ti,hwmods = "spinlock";
+                       #hwlock-cells = <1>;
+               };
+
                wdt2: wdt@44e35000 {
                        compatible = "ti,omap3-wdt";
                        ti,hwmods = "wd_timer2";
                wdt2: wdt@44e35000 {
                        compatible = "ti,omap3-wdt";
                        ti,hwmods = "wd_timer2";
                        interrupts = <91>;
                };
 
                        interrupts = <91>;
                };
 
-               dcan0: d_can@481cc000 {
-                       compatible = "bosch,d_can";
+               dcan0: can@481cc000 {
+                       compatible = "ti,am3352-d_can";
                        ti,hwmods = "d_can0";
                        ti,hwmods = "d_can0";
-                       reg = <0x481cc000 0x2000
-                               0x44e10644 0x4>;
+                       reg = <0x481cc000 0x2000>;
+                       clocks = <&dcan0_fck>;
+                       clock-names = "fck";
+                       syscon-raminit = <&scm_conf 0x644 0>;
                        interrupts = <52>;
                        status = "disabled";
                };
 
                        interrupts = <52>;
                        status = "disabled";
                };
 
-               dcan1: d_can@481d0000 {
-                       compatible = "bosch,d_can";
+               dcan1: can@481d0000 {
+                       compatible = "ti,am3352-d_can";
                        ti,hwmods = "d_can1";
                        ti,hwmods = "d_can1";
-                       reg = <0x481d0000 0x2000
-                               0x44e10644 0x4>;
+                       reg = <0x481d0000 0x2000>;
+                       clocks = <&dcan1_fck>;
+                       clock-names = "fck";
+                       syscon-raminit = <&scm_conf 0x644 1>;
                        interrupts = <55>;
                        status = "disabled";
                };
 
                        interrupts = <55>;
                        status = "disabled";
                };
 
+               mailbox: mailbox@480C8000 {
+                       compatible = "ti,omap4-mailbox";
+                       reg = <0x480C8000 0x200>;
+                       interrupts = <77>;
+                       ti,hwmods = "mailbox";
+                       #mbox-cells = <1>;
+                       ti,mbox-num-users = <4>;
+                       ti,mbox-num-fifos = <8>;
+                       mbox_wkupm3: wkup_m3 {
+                               ti,mbox-tx = <0 0 0>;
+                               ti,mbox-rx = <0 0 3>;
+                       };
+               };
+
                timer1: timer@44e31000 {
                        compatible = "ti,am335x-timer-1ms";
                        reg = <0x44e31000 0x400>;
                timer1: timer@44e31000 {
                        compatible = "ti,am335x-timer-1ms";
                        reg = <0x44e31000 0x400>;
                        ti,timer-pwm;
                };
 
                        ti,timer-pwm;
                };
 
-               rtc@44e3e000 {
-                       compatible = "ti,da830-rtc";
+               rtc: rtc@44e3e000 {
+                       compatible = "ti,am3352-rtc", "ti,da830-rtc";
                        reg = <0x44e3e000 0x1000>;
                        interrupts = <75
                                      76>;
                        reg = <0x44e3e000 0x1000>;
                        interrupts = <75
                                      76>;
                        interrupts = <65>;
                        ti,spi-num-cs = <2>;
                        ti,hwmods = "spi0";
                        interrupts = <65>;
                        ti,spi-num-cs = <2>;
                        ti,hwmods = "spi0";
+                       dmas = <&edma 16
+                               &edma 17
+                               &edma 18
+                               &edma 19>;
+                       dma-names = "tx0", "rx0", "tx1", "rx1";
                        status = "disabled";
                };
 
                        status = "disabled";
                };
 
                        interrupts = <125>;
                        ti,spi-num-cs = <2>;
                        ti,hwmods = "spi1";
                        interrupts = <125>;
                        ti,spi-num-cs = <2>;
                        ti,hwmods = "spi1";
+                       dmas = <&edma 42
+                               &edma 43
+                               &edma 44
+                               &edma 45>;
+                       dma-names = "tx0", "rx0", "tx1", "rx1";
                        status = "disabled";
                };
 
                        status = "disabled";
                };
 
                        ti,hwmods = "usb_otg_hs";
                        status = "disabled";
 
                        ti,hwmods = "usb_otg_hs";
                        status = "disabled";
 
-                       ctrl_mod: control@44e10000 {
+                       usb_ctrl_mod: control@44e10620 {
                                compatible = "ti,am335x-usb-ctrl-module";
                                reg = <0x44e10620 0x10
                                        0x44e10648 0x4>;
                                compatible = "ti,am335x-usb-ctrl-module";
                                reg = <0x44e10620 0x10
                                        0x44e10648 0x4>;
                                reg = <0x47401300 0x100>;
                                reg-names = "phy";
                                status = "disabled";
                                reg = <0x47401300 0x100>;
                                reg-names = "phy";
                                status = "disabled";
-                               ti,ctrl_mod = <&ctrl_mod>;
+                               ti,ctrl_mod = <&usb_ctrl_mod>;
                        };
 
                        usb0: usb@47401000 {
                        };
 
                        usb0: usb@47401000 {
                                reg = <0x47401b00 0x100>;
                                reg-names = "phy";
                                status = "disabled";
                                reg = <0x47401b00 0x100>;
                                reg-names = "phy";
                                status = "disabled";
-                               ti,ctrl_mod = <&ctrl_mod>;
+                               ti,ctrl_mod = <&usb_ctrl_mod>;
                        };
 
                        usb1: usb@47401800 {
                        };
 
                        usb1: usb@47401800 {
                                        "tx14", "tx15";
                        };
 
                                        "tx14", "tx15";
                        };
 
-                       cppi41dma: dma-controller@07402000 {
+                       cppi41dma: dma-controller@47402000 {
                                compatible = "ti,am3359-cppi41";
                                reg =  <0x47400000 0x1000
                                        0x47402000 0x1000
                                compatible = "ti,am3359-cppi41";
                                reg =  <0x47400000 0x1000
                                        0x47402000 0x1000
                                compatible = "ti,am33xx-ecap";
                                #pwm-cells = <3>;
                                reg = <0x48300100 0x80>;
                                compatible = "ti,am33xx-ecap";
                                #pwm-cells = <3>;
                                reg = <0x48300100 0x80>;
+                               interrupts = <31>;
+                               interrupt-names = "ecap0";
                                ti,hwmods = "ecap0";
                                status = "disabled";
                        };
                                ti,hwmods = "ecap0";
                                status = "disabled";
                        };
                                compatible = "ti,am33xx-ecap";
                                #pwm-cells = <3>;
                                reg = <0x48302100 0x80>;
                                compatible = "ti,am33xx-ecap";
                                #pwm-cells = <3>;
                                reg = <0x48302100 0x80>;
+                               interrupts = <47>;
+                               interrupt-names = "ecap1";
                                ti,hwmods = "ecap1";
                                status = "disabled";
                        };
                                ti,hwmods = "ecap1";
                                status = "disabled";
                        };
                                compatible = "ti,am33xx-ecap";
                                #pwm-cells = <3>;
                                reg = <0x48304100 0x80>;
                                compatible = "ti,am33xx-ecap";
                                #pwm-cells = <3>;
                                reg = <0x48304100 0x80>;
+                               interrupts = <61>;
+                               interrupt-names = "ecap2";
                                ti,hwmods = "ecap2";
                                status = "disabled";
                        };
                                ti,hwmods = "ecap2";
                                status = "disabled";
                        };
                mac: ethernet@4a100000 {
                        compatible = "ti,cpsw";
                        ti,hwmods = "cpgmac0";
                mac: ethernet@4a100000 {
                        compatible = "ti,cpsw";
                        ti,hwmods = "cpgmac0";
+                       clocks = <&cpsw_125mhz_gclk>, <&cpsw_cpts_rft_clk>;
+                       clock-names = "fck", "cpts";
                        cpdma_channels = <8>;
                        ale_entries = <1024>;
                        bd_ram_size = <0x2000>;
                        cpdma_channels = <8>;
                        ale_entries = <1024>;
                        bd_ram_size = <0x2000>;
                         */
                        interrupts = <40 41 42 43>;
                        ranges;
                         */
                        interrupts = <40 41 42 43>;
                        ranges;
+                       syscon = <&scm_conf>;
+                       status = "disabled";
 
                        davinci_mdio: mdio@4a101000 {
                                compatible = "ti,davinci_mdio";
 
                        davinci_mdio: mdio@4a101000 {
                                compatible = "ti,davinci_mdio";
                                ti,hwmods = "davinci_mdio";
                                bus_freq = <1000000>;
                                reg = <0x4a101000 0x100>;
                                ti,hwmods = "davinci_mdio";
                                bus_freq = <1000000>;
                                reg = <0x4a101000 0x100>;
+                               status = "disabled";
                        };
 
                        cpsw_emac0: slave@4a100200 {
                        };
 
                        cpsw_emac0: slave@4a100200 {
                                /* Filled in by U-Boot */
                                mac-address = [ 00 00 00 00 00 00 ];
                        };
                                /* Filled in by U-Boot */
                                mac-address = [ 00 00 00 00 00 00 ];
                        };
+
+                       phy_sel: cpsw-phy-sel@44e10650 {
+                               compatible = "ti,am3352-cpsw-phy-sel";
+                               reg= <0x44e10650 0x4>;
+                               reg-names = "gmii-sel";
+                       };
                };
 
                ocmcram: ocmcram@40300000 {
                };
 
                ocmcram: ocmcram@40300000 {
-                       compatible = "ti,am3352-ocmcram";
-                       reg = <0x40300000 0x10000>;
-                       ti,hwmods = "ocmcram";
+                       compatible = "mmio-sram";
+                       reg = <0x40300000 0x10000>; /* 64k */
                };
 
                wkup_m3: wkup_m3@44d00000 {
                };
 
                wkup_m3: wkup_m3@44d00000 {
                        reg = <0x44d00000 0x4000        /* M3 UMEM */
                               0x44d80000 0x2000>;      /* M3 DMEM */
                        ti,hwmods = "wkup_m3";
                        reg = <0x44d00000 0x4000        /* M3 UMEM */
                               0x44d80000 0x2000>;      /* M3 DMEM */
                        ti,hwmods = "wkup_m3";
+                       ti,no-reset-on-init;
                };
 
                elm: elm@48080000 {
                };
 
                elm: elm@48080000 {
                        status = "disabled";
                };
 
                        status = "disabled";
                };
 
+               lcdc: lcdc@4830e000 {
+                       compatible = "ti,am33xx-tilcdc";
+                       reg = <0x4830e000 0x1000>;
+                       interrupt-parent = <&intc>;
+                       interrupts = <36>;
+                       ti,hwmods = "lcdc";
+                       status = "disabled";
+               };
+
                tscadc: tscadc@44e0d000 {
                        compatible = "ti,am3359-tscadc";
                        reg = <0x44e0d000 0x1000>;
                tscadc: tscadc@44e0d000 {
                        compatible = "ti,am3359-tscadc";
                        reg = <0x44e0d000 0x1000>;
                gpmc: gpmc@50000000 {
                        compatible = "ti,am3352-gpmc";
                        ti,hwmods = "gpmc";
                gpmc: gpmc@50000000 {
                        compatible = "ti,am3352-gpmc";
                        ti,hwmods = "gpmc";
+                       ti,no-idle-on-init;
                        reg = <0x50000000 0x2000>;
                        interrupts = <100>;
                        gpmc,num-cs = <7>;
                        reg = <0x50000000 0x2000>;
                        interrupts = <100>;
                        gpmc,num-cs = <7>;
                        #size-cells = <1>;
                        status = "disabled";
                };
                        #size-cells = <1>;
                        status = "disabled";
                };
+
+               sham: sham@53100000 {
+                       compatible = "ti,omap4-sham";
+                       ti,hwmods = "sham";
+                       reg = <0x53100000 0x200>;
+                       interrupts = <109>;
+                       dmas = <&edma 36>;
+                       dma-names = "rx";
+               };
+
+               aes: aes@53500000 {
+                       compatible = "ti,omap4-aes";
+                       ti,hwmods = "aes";
+                       reg = <0x53500000 0xa0>;
+                       interrupts = <103>;
+                       dmas = <&edma 6>,
+                              <&edma 5>;
+                       dma-names = "tx", "rx";
+               };
+
+               mcasp0: mcasp@48038000 {
+                       compatible = "ti,am33xx-mcasp-audio";
+                       ti,hwmods = "mcasp0";
+                       reg = <0x48038000 0x2000>,
+                             <0x46000000 0x400000>;
+                       reg-names = "mpu", "dat";
+                       interrupts = <80>, <81>;
+                       interrupt-names = "tx", "rx";
+                       status = "disabled";
+                       dmas = <&edma 8>,
+                               <&edma 9>;
+                       dma-names = "tx", "rx";
+               };
+
+               mcasp1: mcasp@4803C000 {
+                       compatible = "ti,am33xx-mcasp-audio";
+                       ti,hwmods = "mcasp1";
+                       reg = <0x4803C000 0x2000>,
+                             <0x46400000 0x400000>;
+                       reg-names = "mpu", "dat";
+                       interrupts = <82>, <83>;
+                       interrupt-names = "tx", "rx";
+                       status = "disabled";
+                       dmas = <&edma 10>,
+                               <&edma 11>;
+                       dma-names = "tx", "rx";
+               };
+
+               rng: rng@48310000 {
+                       compatible = "ti,omap4-rng";
+                       ti,hwmods = "rng";
+                       reg = <0x48310000 0x2000>;
+                       interrupts = <111>;
+               };
        };
 };
        };
 };
+
+/include/ "am33xx-clocks.dtsi"
diff --git a/arch/arm/dts/tps65910.dtsi b/arch/arm/dts/tps65910.dtsi
new file mode 100644 (file)
index 0000000..b0ac665
--- /dev/null
@@ -0,0 +1,91 @@
+/*
+ * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/*
+ * Integrated Power Management Chip
+ * http://www.ti.com/lit/ds/symlink/tps65910.pdf
+ */
+
+&tps {
+       compatible = "ti,tps65910";
+
+       regulators {
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               vrtc_reg: regulator@0 {
+                       reg = <0>;
+                       regulator-compatible = "vrtc";
+               };
+
+               vio_reg: regulator@1 {
+                       reg = <1>;
+                       regulator-compatible = "vio";
+               };
+
+               vdd1_reg: regulator@2 {
+                       reg = <2>;
+                       regulator-compatible = "vdd1";
+               };
+
+               vdd2_reg: regulator@3 {
+                       reg = <3>;
+                       regulator-compatible = "vdd2";
+               };
+
+               vdd3_reg: regulator@4 {
+                       reg = <4>;
+                       regulator-compatible = "vdd3";
+               };
+
+               vdig1_reg: regulator@5 {
+                       reg = <5>;
+                       regulator-compatible = "vdig1";
+               };
+
+               vdig2_reg: regulator@6 {
+                       reg = <6>;
+                       regulator-compatible = "vdig2";
+               };
+
+               vpll_reg: regulator@7 {
+                       reg = <7>;
+                       regulator-compatible = "vpll";
+               };
+
+               vdac_reg: regulator@8 {
+                       reg = <8>;
+                       regulator-compatible = "vdac";
+               };
+
+               vaux1_reg: regulator@9 {
+                       reg = <9>;
+                       regulator-compatible = "vaux1";
+               };
+
+               vaux2_reg: regulator@10 {
+                       reg = <10>;
+                       regulator-compatible = "vaux2";
+               };
+
+               vaux33_reg: regulator@11 {
+                       reg = <11>;
+                       regulator-compatible = "vaux33";
+               };
+
+               vmmc_reg: regulator@12 {
+                       reg = <12>;
+                       regulator-compatible = "vmmc";
+               };
+
+               vbb_reg: regulator@13 {
+                       reg = <13>;
+                       regulator-compatible = "vbb";
+               };
+       };
+};
diff --git a/configs/am335x_gp_evm_defconfig b/configs/am335x_gp_evm_defconfig
new file mode 100644 (file)
index 0000000..62d3b6b
--- /dev/null
@@ -0,0 +1,14 @@
+CONFIG_ARM=y
+CONFIG_TARGET_AM335X_EVM=y
+CONFIG_DEFAULT_DEVICE_TREE="am335x-evm"
+CONFIG_SPL=y
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_STACK_R_ADDR=0x82000000
+CONFIG_SYS_EXTRA_OPTIONS="NAND"
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_DISABLE_OF_CONTROL=y
+CONFIG_SPI_FLASH=y
+CONFIG_RSA=y