Merge branch 'master' of git://git.denx.de/u-boot-usb

Conflicts:
	board/freescale/mx6sxsabresd/mx6sxsabresd.c

Signed-off-by: Tom Rini <trini@ti.com>

diff --combined board/freescale/mx6slevk/mx6slevk.c
index cac6d73a7f81a9a1f3a7b8bd1b3b682b8fd16807,3ae2c4627b726a1bb6d8e1868283a911e5b4f91b..3834eec60e866f9da37d512770c53dc1bcdff7b5
--- 1/board/freescale/mx6slevk/mx6slevk.c
--- 2/board/freescale/mx6slevk/mx6slevk.c
+++ b/board/freescale/mx6slevk/mx6slevk.c
@@@ -20,6 -20,8 +20,8 @@@
  #include <fsl_esdhc.h>
  #include <mmc.h>
  #include <netdev.h>
+ #include <usb.h>
+ #include <usb/ehci-fsl.h>
  
  DECLARE_GLOBAL_DATA_PTR;
  
@@@ -230,14 -232,61 +232,56 @@@ int board_eth_init(bd_t *bis
  static int setup_fec(void)
  {
        struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
 -      int ret;
  
        /* clear gpr1[14], gpr1[18:17] to select anatop clock */
        clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC_MASK, 0);
  
 -      ret = enable_fec_anatop_clock(ENET_50MHz);
 -      if (ret)
 -              return ret;
 -
 -      return 0;
 +      return enable_fec_anatop_clock(ENET_50MHZ);
  }
  #endif
  
+ #ifdef CONFIG_USB_EHCI_MX6
+ #define USB_OTHERREGS_OFFSET  0x800
+ #define UCTRL_PWR_POL         (1 << 9)
+ 
+ static iomux_v3_cfg_t const usb_otg_pads[] = {
+       /* OTG1 */
+       MX6_PAD_KEY_COL4__USB_USBOTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
+       MX6_PAD_EPDC_PWRCOM__ANATOP_USBOTG1_ID | MUX_PAD_CTRL(NO_PAD_CTRL),
+       /* OTG2 */
+       MX6_PAD_KEY_COL5__USB_USBOTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL)
+ };
+ 
+ static void setup_usb(void)
+ {
+       imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
+                                        ARRAY_SIZE(usb_otg_pads));
+ }
+ 
+ int board_usb_phy_mode(int port)
+ {
+       if (port == 1)
+               return USB_INIT_HOST;
+       else
+               return usb_phy_mode(port);
+ }
+ 
+ int board_ehci_hcd_init(int port)
+ {
+       u32 *usbnc_usb_ctrl;
+ 
+       if (port > 1)
+               return -EINVAL;
+ 
+       usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET +
+                                port * 4);
+ 
+       /* Set Power polarity */
+       setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL);
+ 
+       return 0;
+ }
+ #endif
  
  int board_early_init_f(void)
  {
@@@ -256,6 -305,11 +300,11 @@@ int board_init(void
  #ifdef        CONFIG_FEC_MXC
        setup_fec();
  #endif
+ 
+ #ifdef CONFIG_USB_EHCI_MX6
+       setup_usb();
+ #endif
+ 
        return 0;
  }
  

diff --combined board/freescale/mx6sxsabresd/mx6sxsabresd.c
index 8b959b9fc6a02b56afcc87b2fdd937ce8dad600b,02e82b2524405ba35381dfed1487ae14639a3ef4..fd8bc72827496c767c35699db4667655c7241f7e
--- 1/board/freescale/mx6sxsabresd/mx6sxsabresd.c
--- 2/board/freescale/mx6sxsabresd/mx6sxsabresd.c
+++ b/board/freescale/mx6sxsabresd/mx6sxsabresd.c
@@@ -25,7 -25,8 +25,9 @@@
  #include <netdev.h>
  #include <power/pmic.h>
  #include <power/pfuze100_pmic.h>
 +#include "../common/pfuze.h"
+ #include <usb.h>
+ #include <usb/ehci-fsl.h>
  
  DECLARE_GLOBAL_DATA_PTR;
  
@@@ -69,34 -70,6 +71,34 @@@ static iomux_v3_cfg_t const uart1_pads[
        MX6_PAD_GPIO1_IO05__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
  };
  
 +static iomux_v3_cfg_t const usdhc2_pads[] = {
 +      MX6_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 +      MX6_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 +      MX6_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 +      MX6_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 +      MX6_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 +      MX6_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 +};
 +
 +static iomux_v3_cfg_t const usdhc3_pads[] = {
 +      MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 +      MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 +      MX6_PAD_SD3_DATA0__USDHC3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 +      MX6_PAD_SD3_DATA1__USDHC3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 +      MX6_PAD_SD3_DATA2__USDHC3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 +      MX6_PAD_SD3_DATA3__USDHC3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 +      MX6_PAD_SD3_DATA4__USDHC3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 +      MX6_PAD_SD3_DATA5__USDHC3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 +      MX6_PAD_SD3_DATA6__USDHC3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 +      MX6_PAD_SD3_DATA7__USDHC3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 +
 +      /* CD pin */
 +      MX6_PAD_KEY_COL0__GPIO2_IO_10 | MUX_PAD_CTRL(NO_PAD_CTRL),
 +
 +      /* RST_B, used for power reset cycle */
 +      MX6_PAD_KEY_COL1__GPIO2_IO_11 | MUX_PAD_CTRL(NO_PAD_CTRL),
 +};
 +
  static iomux_v3_cfg_t const usdhc4_pads[] = {
        MX6_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
        MX6_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
@@@ -148,6 -121,7 +150,6 @@@ static int setup_fec(void
  {
        struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
        struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
 -      int ret;
        int reg;
  
        /* Use 125MHz anatop loopback REF_CLK1 for ENET1 */
@@@ -168,7 -142,11 +170,7 @@@
        reg |= BM_ANADIG_PLL_ENET_REF_25M_ENABLE;
        writel(reg, &anatop->pll_enet);
  
 -      ret = enable_fec_anatop_clock(ENET_125MHz);
 -      if (ret)
 -              return ret;
 -
 -      return 0;
 +      return enable_fec_anatop_clock(ENET_125MHZ);
  }
  
  int board_eth_init(bd_t *bis)
@@@ -194,24 -172,57 +196,67 @@@ static struct i2c_pads_info i2c_pad_inf
        },
  };
  
 -static int pfuze_init(void)
 +int power_init_board(void)
  {
        struct pmic *p;
 -      int ret;
        unsigned int reg;
  
 -      ret = power_pfuze100_init(I2C_PMIC);
 -      if (ret)
 -              return ret;
 -
 -      p = pmic_get("PFUZE100");
 -      ret = pmic_probe(p);
 -      if (ret)
 -              return ret;
 -
 -      pmic_reg_read(p, PFUZE100_DEVICEID, &reg);
 -      printf("PMIC:  PFUZE100 ID=0x%02x\n", reg);
 -
 -      /* Set SW1AB standby voltage to 0.975V */
 -      pmic_reg_read(p, PFUZE100_SW1ABSTBY, &reg);
 -      reg &= ~0x3f;
 -      reg |= 0x1b;
 -      pmic_reg_write(p, PFUZE100_SW1ABSTBY, reg);
 -
 -      /* Set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
 -      pmic_reg_read(p, PUZE_100_SW1ABCONF, &reg);
 -      reg &= ~0xc0;
 -      reg |= 0x40;
 -      pmic_reg_write(p, PUZE_100_SW1ABCONF, reg);
 -
 -      /* Set SW1C standby voltage to 0.975V */
 -      pmic_reg_read(p, PFUZE100_SW1CSTBY, &reg);
 -      reg &= ~0x3f;
 -      reg |= 0x1b;
 -      pmic_reg_write(p, PFUZE100_SW1CSTBY, reg);
 -
 -      /* Set SW1C/VDDSOC step ramp up time from 16us to 4us/25mV */
 -      pmic_reg_read(p, PFUZE100_SW1CCONF, &reg);
 -      reg &= ~0xc0;
 -      reg |= 0x40;
 -      pmic_reg_write(p, PFUZE100_SW1CCONF, reg);
 +      p = pfuze_common_init(I2C_PMIC);
 +      if (!p)
 +              return -ENODEV;
  
        /* Enable power of VGEN5 3V3, needed for SD3 */
        pmic_reg_read(p, PFUZE100_VGEN5VOL, &reg);
 -      reg &= ~0x1F;
 -      reg |= 0x1F;
 +      reg &= ~LDO_VOL_MASK;
 +      reg |= (LDOB_3_30V | (1 << LDO_EN));
        pmic_reg_write(p, PFUZE100_VGEN5VOL, reg);
  
        return 0;
  }
  
++#ifdef CONFIG_USB_EHCI_MX6
++#define USB_OTHERREGS_OFFSET  0x800
++#define UCTRL_PWR_POL         (1 << 9)
++
++static iomux_v3_cfg_t const usb_otg_pads[] = {
++      /* OGT1 */
++      MX6_PAD_GPIO1_IO09__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
++      MX6_PAD_GPIO1_IO10__ANATOP_OTG1_ID | MUX_PAD_CTRL(NO_PAD_CTRL),
++      /* OTG2 */
++      MX6_PAD_GPIO1_IO12__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL)
++};
++
++static void setup_usb(void)
++{
++      imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
++                                       ARRAY_SIZE(usb_otg_pads));
++}
++
++int board_usb_phy_mode(int port)
++{
++      if (port == 1)
++              return USB_INIT_HOST;
++      else
++              return usb_phy_mode(port);
++}
++
++int board_ehci_hcd_init(int port)
++{
++      u32 *usbnc_usb_ctrl;
++
++      if (port > 1)
++              return -EINVAL;
++
++      usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET +
++                               port * 4);
++
++      /* Set Power polarity */
++      setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL);
++
++      return 0;
++}
++#endif
++
  int board_phy_config(struct phy_device *phydev)
  {
        /*
@@@ -234,6 -245,7 +279,6 @@@
  int board_early_init_f(void)
  {
        setup_iomux_uart();
 -      setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
  
        /* Enable PERI_3V3, which is used by SD2, ENET, LVDS, BT */
        imx_iomux_v3_setup_multiple_pads(peri_3v3_pads,
@@@ -242,101 -254,85 +287,104 @@@
        /* Active high for ncp692 */
        gpio_direction_output(IMX_GPIO_NR(4, 16) , 1);
  
+ #ifdef CONFIG_USB_EHCI_MX6
+       setup_usb();
+ #endif
+ 
        return 0;
  }
  
 -static struct fsl_esdhc_cfg usdhc_cfg[1] = {
 +static struct fsl_esdhc_cfg usdhc_cfg[3] = {
 +      {USDHC2_BASE_ADDR, 0, 4},
 +      {USDHC3_BASE_ADDR},
        {USDHC4_BASE_ADDR},
  };
  
 +#define USDHC3_CD_GPIO        IMX_GPIO_NR(2, 10)
 +#define USDHC3_PWR_GPIO       IMX_GPIO_NR(2, 11)
 +#define USDHC4_CD_GPIO        IMX_GPIO_NR(6, 21)
 +
  int board_mmc_getcd(struct mmc *mmc)
  {
 -      return 1;       /* Assume boot SD always present */
 +      struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 +      int ret = 0;
 +
 +      switch (cfg->esdhc_base) {
 +      case USDHC2_BASE_ADDR:
 +              ret = 1; /* Assume uSDHC2 is always present */
 +              break;
 +      case USDHC3_BASE_ADDR:
 +              ret = !gpio_get_value(USDHC3_CD_GPIO);
 +              break;
 +      case USDHC4_BASE_ADDR:
 +              ret = !gpio_get_value(USDHC4_CD_GPIO);
 +              break;
 +      }
 +
 +      return ret;
  }
  
  int board_mmc_init(bd_t *bis)
  {
 -      imx_iomux_v3_setup_multiple_pads(usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
 -
 -      usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
 -      return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
 -}
 -
 -#ifdef CONFIG_USB_EHCI_MX6
 -#define USB_OTHERREGS_OFFSET  0x800
 -#define UCTRL_PWR_POL         (1 << 9)
 -
 -static iomux_v3_cfg_t const usb_otg_pads[] = {
 -      /* OGT1 */
 -      MX6_PAD_GPIO1_IO09__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
 -      MX6_PAD_GPIO1_IO10__ANATOP_OTG1_ID | MUX_PAD_CTRL(NO_PAD_CTRL),
 -      /* OTG2 */
 -      MX6_PAD_GPIO1_IO12__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL)
 -};
 -
 -static void setup_usb(void)
 -{
 -      imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
 -                                       ARRAY_SIZE(usb_otg_pads));
 -}
 -
 -int board_usb_phy_mode(int port)
 -{
 -      if (port == 1)
 -              return USB_INIT_HOST;
 -      else
 -              return usb_phy_mode(port);
 -}
 -
 -int board_ehci_hcd_init(int port)
 -{
 -      u32 *usbnc_usb_ctrl;
 -
 -      if (port > 1)
 -              return -EINVAL;
 -
 -      usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET +
 -                               port * 4);
 +      int i, ret;
  
 -      /* Set Power polarity */
 -      setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL);
 +      /*
 +       * According to the board_mmc_init() the following map is done:
 +       * (U-boot device node)    (Physical Port)
 +       * mmc0                    USDHC2
 +       * mmc1                    USDHC3
 +       * mmc2                    USDHC4
 +       */
 +      for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
 +              switch (i) {
 +              case 0:
 +                      imx_iomux_v3_setup_multiple_pads(
 +                              usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
 +                      usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
 +                      break;
 +              case 1:
 +                      imx_iomux_v3_setup_multiple_pads(
 +                              usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
 +                      gpio_direction_input(USDHC3_CD_GPIO);
 +                      gpio_direction_output(USDHC3_PWR_GPIO, 1);
 +                      usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
 +                      break;
 +              case 2:
 +                      imx_iomux_v3_setup_multiple_pads(
 +                              usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
 +                      gpio_direction_input(USDHC4_CD_GPIO);
 +                      usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
 +                      break;
 +              default:
 +                      printf("Warning: you configured more USDHC controllers"
 +                              "(%d) than supported by the board\n", i + 1);
 +                      return -EINVAL;
 +                      }
 +
 +                      ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
 +                      if (ret) {
 +                              printf("Warning: failed to initialize mmc dev %d\n", i);
 +                              return ret;
 +                      }
 +      }
  
        return 0;
  }
 -#endif
  
- 
  int board_init(void)
  {
        /* Address of boot parameters */
        gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
  
 +#ifdef CONFIG_SYS_I2C_MXC
 +      setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
 +#endif
 +
        return 0;
  }
  
  int board_late_init(void)
  {
 -      pfuze_init();
 -
        return 0;
  }
  

diff --combined drivers/dfu/dfu.c
index c0aba6e197c5ef3ea940685f874f75dd014c4dc4,deafda29c98bf2d400e1b6ed72239e8d4c13f3b8..14cb366b014cb3e7fb9de8f9e316783c1be05f19
--- 1/drivers/dfu/dfu.c
--- 2/drivers/dfu/dfu.c
+++ b/drivers/dfu/dfu.c
@@@ -289,7 -289,7 +289,7 @@@ static int dfu_read_buffer_fill(struct 
        readn = 0;
        while (size > 0) {
                /* get chunk that can be read */
 -              chunk = min(size, dfu->b_left);
 +              chunk = min((long)size, dfu->b_left);
                /* consume */
                if (chunk > 0) {
                        memcpy(buf, dfu->i_buf, chunk);
@@@ -544,10 -544,35 +544,35 @@@ struct dfu_entity *dfu_get_entity(int a
  int dfu_get_alt(char *name)
  {
        struct dfu_entity *dfu;
+       char *str;
  
        list_for_each_entry(dfu, &dfu_list, list) {
-               if (!strncmp(dfu->name, name, strlen(dfu->name)))
-                       return dfu->alt;
+               if (dfu->name[0] != '/') {
+                       if (!strncmp(dfu->name, name, strlen(dfu->name)))
+                               return dfu->alt;
+               } else {
+                       /*
+                        * One must also consider absolute path
+                        * (/boot/bin/uImage) available at dfu->name when
+                        * compared "plain" file name (uImage)
+                        *
+                        * It is the case for e.g. thor gadget where lthor SW
+                        * sends only the file name, so only the very last part
+                        * of path must be checked for equality
+                        */
+ 
+                       str = strstr(dfu->name, name);
+                       if (!str)
+                               continue;
+ 
+                       /*
+                        * Check if matching substring is the last element of
+                        * dfu->name (uImage)
+                        */
+                       if (strlen(dfu->name) ==
+                           ((str - dfu->name) + strlen(name)))
+                               return dfu->alt;
+               }
        }
  
        return -ENODEV;

diff --combined drivers/usb/host/ehci-hcd.c
index 5520805af37a1c99b84843535d10b7e78496b452,54e948aa31eec26582af8febc6ef638946b42797..bc7606646bbcf9ac76ab679a8f85405ceaa6d45a
--- 1/drivers/usb/host/ehci-hcd.c
--- 2/drivers/usb/host/ehci-hcd.c
+++ b/drivers/usb/host/ehci-hcd.c
@@@ -910,7 -910,7 +910,7 @@@ ehci_submit_root(struct usb_device *dev
        }
  
        mdelay(1);
 -      len = min3(srclen, le16_to_cpu(req->length), length);
 +      len = min3(srclen, (int)le16_to_cpu(req->length), length);
        if (srcptr != NULL && len > 0)
                memcpy(buffer, srcptr, len);
        else
@@@ -971,7 -971,6 +971,6 @@@ int usb_lowlevel_init(int index, enum u
        qh_list->qh_link = cpu_to_hc32((uint32_t)qh_list | QH_LINK_TYPE_QH);
        qh_list->qh_endpt1 = cpu_to_hc32(QH_ENDPT1_H(1) |
                                                QH_ENDPT1_EPS(USB_SPEED_HIGH));
-       qh_list->qh_curtd = cpu_to_hc32(QT_NEXT_TERMINATE);
        qh_list->qh_overlay.qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
        qh_list->qh_overlay.qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
        qh_list->qh_overlay.qt_token =

diff --combined include/configs/mx6slevk.h
index 271548c875f7c748a7a5dcd69e5c7d1376740d56,bd57159a87cffc3d688e26e0631ad9dc30c97947..e3e7f7686b59e289da319fb8f3181bc0160f5835
--- 1/include/configs/mx6slevk.h
--- 2/include/configs/mx6slevk.h
+++ b/include/configs/mx6slevk.h
@@@ -87,7 -87,7 +87,7 @@@
        "fdt_addr=0x88000000\0" \
        "boot_fdt=try\0" \
        "ip_dyn=yes\0" \
 -      "mmcdev=0\0" \
 +      "mmcdev=1\0" \
        "mmcpart=1\0" \
        "mmcroot=/dev/mmcblk0p2 rootwait rw\0" \
        "mmcargs=setenv bootargs console=${console},${baudrate} " \
@@@ -209,6 -209,20 +209,20 @@@
  #define CONFIG_SF_DEFAULT_MODE                SPI_MODE_0
  #endif
  
+ /* USB Configs */
+ #define CONFIG_CMD_USB
+ #ifdef CONFIG_CMD_USB
+ #define CONFIG_USB_EHCI
+ #define CONFIG_USB_EHCI_MX6
+ #define CONFIG_USB_STORAGE
+ #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+ #define CONFIG_USB_HOST_ETHER
+ #define CONFIG_USB_ETHER_ASIX
+ #define CONFIG_MXC_USB_PORTSC         (PORT_PTS_UTMI | PORT_PTS_PTW)
+ #define CONFIG_MXC_USB_FLAGS          0
+ #define CONFIG_USB_MAX_CONTROLLER_COUNT       2
+ #endif
+ 
  #define CONFIG_SYS_FSL_USDHC_NUM      3
  #if defined(CONFIG_ENV_IS_IN_MMC)
  #define CONFIG_SYS_MMC_ENV_DEV                1       /* SDHC2*/

diff --combined include/configs/mx6sxsabresd.h
index 5e0edabf3738812cfb84feb48280e7f841b87f7c,8edf1875d43f7e7742e9d401a1c35b8adcee0d9f..61a7a7a07ea3350b2a5bd64692ab955ade2243a8
--- 1/include/configs/mx6sxsabresd.h
--- 2/include/configs/mx6sxsabresd.h
+++ b/include/configs/mx6sxsabresd.h
@@@ -59,7 -59,7 +59,7 @@@
        "fdt_addr=0x88000000\0" \
        "boot_fdt=try\0" \
        "ip_dyn=yes\0" \
 -      "mmcdev=0\0" \
 +      "mmcdev=2\0" \
        "mmcpart=1\0" \
        "mmcroot=/dev/mmcblk0p2 rootwait rw\0" \
        "mmcargs=setenv bootargs console=${console},${baudrate} " \
@@@ -198,6 -198,20 +198,20 @@@
  #define CONFIG_PHYLIB
  #define CONFIG_PHY_ATHEROS
  
+ 
+ #define CONFIG_CMD_USB
+ #ifdef CONFIG_CMD_USB
+ #define CONFIG_USB_EHCI
+ #define CONFIG_USB_EHCI_MX6
+ #define CONFIG_USB_STORAGE
+ #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+ #define CONFIG_USB_HOST_ETHER
+ #define CONFIG_USB_ETHER_ASIX
+ #define CONFIG_MXC_USB_PORTSC  (PORT_PTS_UTMI | PORT_PTS_PTW)
+ #define CONFIG_MXC_USB_FLAGS   0
+ #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
+ #endif
+ 
  #define CONFIG_CMD_PCI
  #ifdef CONFIG_CMD_PCI
  #define CONFIG_PCI
@@@ -208,22 -222,13 +222,22 @@@
  #define CONFIG_PCIE_IMX_POWER_GPIO    IMX_GPIO_NR(2, 1)
  #endif
  
 +#define CONFIG_DM
 +#define CONFIG_DM_THERMAL
 +#define CONFIG_SYS_MALLOC_F_LEN       (1 << 10)
 +#define CONFIG_IMX6_THERMAL
 +
 +#define CONFIG_CMD_FUSE
 +#if defined(CONFIG_CMD_FUSE) || defined(CONFIG_IMX6_THERMAL)
 +#define CONFIG_MXC_OCOTP
 +#endif
 +
  /* FLASH and environment organization */
  #define CONFIG_SYS_NO_FLASH
  
  #define CONFIG_ENV_OFFSET             (6 * SZ_64K)
  #define CONFIG_ENV_SIZE                       SZ_8K
  #define CONFIG_ENV_IS_IN_MMC
 -#define CONFIG_SYS_MMC_ENV_DEV                0
  
  #define CONFIG_OF_LIBFDT
  #define CONFIG_CMD_BOOTZ
@@@ -232,9 -237,4 +246,9 @@@
  #define CONFIG_CMD_CACHE
  #endif
  
 +#define CONFIG_SYS_FSL_USDHC_NUM      3
 +#if defined(CONFIG_ENV_IS_IN_MMC)
 +#define CONFIG_SYS_MMC_ENV_DEV                2  /*USDHC4*/
 +#endif
 +
  #endif                                /* __CONFIG_H */

diff --combined include/usb/ehci-fsl.h
index 897018bf84c942ec7a6dad04324c26cdf381e06a,22114c1694fde02771f013b913f20afa6ba0be2f..e9349b5c1666db1838ef8da34d194ee5c83bbb16
--- 1/include/usb/ehci-fsl.h
--- 2/include/usb/ehci-fsl.h
+++ b/include/usb/ehci-fsl.h
@@@ -163,9 -163,6 +163,9 @@@
  #elif defined(CONFIG_MPC512X)
  #define CONFIG_SYS_FSL_USB1_ADDR CONFIG_SYS_MPC512x_USB1_ADDR
  #define CONFIG_SYS_FSL_USB2_ADDR      0
 +#elif defined(CONFIG_LS102XA)
 +#define CONFIG_SYS_FSL_USB1_ADDR CONFIG_SYS_LS102XA_USB1_ADDR
 +#define CONFIG_SYS_FSL_USB2_ADDR        0
  #endif
  
  /*
@@@ -280,7 -277,9 +280,9 @@@ struct usb_ehci 
  #define MXC_EHCI_IPPUE_DOWN           (1 << 10)
  #define MXC_EHCI_IPPUE_UP             (1 << 11)
  
+ int usb_phy_mode(int port);
  /* Board-specific initialization */
  int board_ehci_hcd_init(int port);
+ int board_usb_phy_mode(int port);
  
  #endif /* _EHCI_FSL_H */