#define KW_USB20_BASE (KW_REGISTER(0x50000))
#define KW_EGIGA0_BASE (KW_REGISTER(0x72000))
#define KW_EGIGA1_BASE (KW_REGISTER(0x76000))
+#define KW_SATA_BASE (KW_REGISTER(0x80000))
+
+/* Kirkwood Sata controller has two ports */
+#define KW_SATA_PORT0_OFFSET 0x2000
+#define KW_SATA_PORT1_OFFSET 0x4000
/* Kirkwood GbE controller has two ports */
#define MAX_MVGBE_DEVS 2
#define ORION5X_USB20_PORT0_BASE (ORION5X_REGISTER(0x50000))
#define ORION5X_USB20_PORT1_BASE (ORION5X_REGISTER(0xA0000))
#define ORION5X_EGIGA_BASE (ORION5X_REGISTER(0x72000))
+#define ORION5X_SATA_BASE (ORION5X_REGISTER(0x80000))
+#define ORION5X_SATA_PORT0_OFFSET 0x2000
+#define ORION5X_SATA_PORT1_OFFSET 0x4000
/* Orion5x GbE controller has a single port */
#define MAX_MVGBE_DEVS 1
#define CONFIG_FSL_LBC
#endif
+/* All PPC boards must swap IDE bytes */
+#define CONFIG_IDE_SWAP_IO
+
#endif /* _ASM_CONFIG_H_ */
/*
* IDE support
*/
+
#include <common.h>
#include <config.h>
#include <watchdog.h>
#include <mpc5xxx.h>
#endif
+#ifdef CONFIG_ORION5X
+#include <asm/arch/orion5x.h>
+#elif defined CONFIG_KIRKWOOD
+#include <asm/arch/kirkwood.h>
+#endif
+
#include <ide.h>
#include <ata.h>
#endif /* __LITTLE_ENDIAN || CONFIG_AU1X00 */
-#if defined(__PPC__) || defined(CONFIG_PXA_PCMCIA) || defined(CONFIG_SH)
+#if defined(CONFIG_IDE_SWAP_IO)
static void
output_data(int dev, ulong *sect_buf, int words)
{
}
#endif
}
-#else /* ! __PPC__ */
+#else /* ! CONFIG_IDE_SWAP_IO */
static void
output_data(int dev, ulong *sect_buf, int words)
{
outsw(ATA_CURR_BASE(dev)+ATA_DATA_REG, sect_buf, words<<1);
}
-#endif /* __PPC__ */
+#endif /* CONFIG_IDE_SWAP_IO */
-#if defined(__PPC__) || defined(CONFIG_PXA_PCMCIA) || defined(CONFIG_SH)
+#if defined(CONFIG_IDE_SWAP_IO)
static void
input_data(int dev, ulong *sect_buf, int words)
{
}
#endif
}
-#else /* ! __PPC__ */
+#else /* ! CONFIG_IDE_SWAP_IO */
static void
input_data(int dev, ulong *sect_buf, int words)
{
insw(ATA_CURR_BASE(dev)+ATA_DATA_REG, sect_buf, words << 1);
}
-#endif /* __PPC__ */
+#endif /* CONFIG_IDE_SWAP_IO */
/* -------------------------------------------------------------------------
*/
* ATAPI Support
*/
-#if defined(__PPC__) || defined(CONFIG_PXA_PCMCIA)
+#if defined(CONFIG_IDE_SWAP_IO)
/* since ATAPI may use commands with not 4 bytes alligned length
* we have our own transfer functions, 2 bytes alligned */
static void
#endif
}
-#else /* ! __PPC__ */
+#else /* ! CONFIG_IDE_SWAP_IO */
static void
output_data_shorts(int dev, ushort *sect_buf, int shorts)
{
insw(ATA_CURR_BASE(dev)+ATA_DATA_REG, sect_buf, shorts);
}
-#endif /* __PPC__ */
+#endif /* CONFIG_IDE_SWAP_IO */
/*
* Wait until (Status & mask) == res, or timeout (in ms)
marked memory configuration should be touched since the other parameters
are imposed by the PXA architecture.
+EDIT 2010-07-01: in common/cmd_ide.c, having CONFIG_PXA_PCMCIA defined
+would cause looping on inw()/outw() rather than using insw()/outsw(),
+thus making sure IDE / ATA bytes are properly swapped. This behaviour
+is now controlled by CONFIG_IDE_SWAP_IO, therefore PXA boards with
+PCMCIA should #define CONFIG_IDE_SWAP_IO.
+
+#define CONFIG_IDE_SWAP_IO
+
#define CONFIG_PXA_PCMCIA 1
#define CONFIG_PXA_IDE 1
LIB := $(obj)libblock.a
+COBJS-$(CONFIG_SCSI_AHCI) += ahci.o
COBJS-$(CONFIG_ATA_PIIX) += ata_piix.o
-COBJS-$(CONFIG_CMD_MG_DISK) += mg_disk.o
COBJS-$(CONFIG_FSL_SATA) += fsl_sata.o
-COBJS-$(CONFIG_IDE_SIL680) += sil680.o
COBJS-$(CONFIG_LIBATA) += libata.o
+COBJS-$(CONFIG_CMD_MG_DISK) += mg_disk.o
+COBJS-$(CONFIG_MVSATA_IDE) += mvsata_ide.o
COBJS-$(CONFIG_PATA_BFIN) += pata_bfin.o
COBJS-$(CONFIG_SATA_DWC) += sata_dwc.o
COBJS-$(CONFIG_SATA_SIL3114) += sata_sil3114.o
-COBJS-$(CONFIG_SCSI_AHCI) += ahci.o
+COBJS-$(CONFIG_IDE_SIL680) += sil680.o
COBJS-$(CONFIG_SCSI_SYM53C8XX) += sym53c8xx.o
COBJS-$(CONFIG_SYSTEMACE) += systemace.o
--- /dev/null
+/*
+ * Copyright (C) 2010 Albert ARIBAUD <albert.aribaud@free.fr>
+ *
+ * Written-by: Albert ARIBAUD <albert.aribaud@free.fr>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+
+#if defined(CONFIG_ORION5X)
+#include <asm/arch/orion5x.h>
+#elif defined(CONFIG_KIRKWOOD)
+#include <asm/arch/kirkwood.h>
+#endif
+
+/* SATA port registers */
+struct mvsata_port_registers {
+ u32 reserved1[192];
+ /* offset 0x300 : ATA Interface registers */
+ u32 sstatus;
+ u32 serror;
+ u32 scontrol;
+ u32 ltmode;
+ u32 phymode3;
+ u32 phymode4;
+ u32 reserved2[5];
+ u32 phymode1;
+ u32 phymode2;
+ u32 bist_cr;
+ u32 bist_dw1;
+ u32 bist_dw2;
+ u32 serrorintrmask;
+};
+
+/*
+ * Sanity checks:
+ * - to compile at all, we need CONFIG_SYS_ATA_BASE_ADDR.
+ * - for ide_preinit to make sense, we need at least one of
+ * CONFIG_SYS_ATA_IDE0_OFFSET or CONFIG_SYS_ATA_IDE0_OFFSET;
+ * - for inde_preinit to be called, we need CONFIG_IDE_PREINIT.
+ * Fail with an explanation message if these conditions are not met.
+ * This is particularly important for CONFIG_IDE_PREINIT, because
+ * its lack would not cause a build error.
+ */
+
+#if !defined(CONFIG_SYS_ATA_BASE_ADDR)
+#error CONFIG_SYS_ATA_BASE_ADDR must be defined
+#elif !defined(CONFIG_SYS_ATA_IDE0_OFFSET) \
+ && !defined(CONFIG_SYS_ATA_IDE1_OFFSET)
+#error CONFIG_SYS_ATA_IDE0_OFFSET or CONFIG_SYS_ATA_IDE1_OFFSET \
+ must be defined
+#elif !defined(CONFIG_IDE_PREINIT)
+#error CONFIG_IDE_PREINIT must be defined
+#endif
+
+/*
+ * Masks and values for SControl DETection and Interface Power Management,
+ * and for SStatus DETection.
+ */
+
+#define MVSATA_SCONTROL_DET_MASK 0x0000000F
+#define MVSATA_SCONTROL_DET_NONE 0x00000000
+#define MVSATA_SCONTROL_DET_INIT 0x00000001
+#define MVSATA_SCONTROL_IPM_MASK 0x00000F00
+#define MVSATA_SCONTROL_IPM_NO_LP_ALLOWED 0x00000300
+#define MVSATA_SCONTROL_MASK \
+ (MVSATA_SCONTROL_DET_MASK|MVSATA_SCONTROL_IPM_MASK)
+#define MVSATA_PORT_INIT \
+ (MVSATA_SCONTROL_DET_INIT|MVSATA_SCONTROL_IPM_NO_LP_ALLOWED)
+#define MVSATA_PORT_USE \
+ (MVSATA_SCONTROL_DET_NONE|MVSATA_SCONTROL_IPM_NO_LP_ALLOWED)
+#define MVSATA_SSTATUS_DET_MASK 0x0000000F
+#define MVSATA_SSTATUS_DET_DEVCOMM 0x00000003
+
+/*
+ * Initialize one MVSATAHC port: set SControl's IPM to "always active"
+ * and DET to "reset", then wait for SStatus's DET to become "device and
+ * comm ok" (or time out after 50 us if no device), then set SControl's
+ * DET back to "no action".
+ */
+
+static void mvsata_ide_initialize_port(struct mvsata_port_registers *port)
+{
+ u32 control;
+ u32 status;
+ u32 tout = 50; /* wait at most 50 us for SATA reset to complete */
+
+ control = readl(&port->scontrol);
+ control = (control & ~MVSATA_SCONTROL_MASK) | MVSATA_PORT_INIT;
+ writel(control, &port->scontrol);
+ while (--tout) {
+ status = readl(&port->sstatus) & MVSATA_SSTATUS_DET_MASK;
+ if (status == MVSATA_SSTATUS_DET_DEVCOMM)
+ break;
+ udelay(1);
+ }
+ control = (control & ~MVSATA_SCONTROL_MASK) | MVSATA_PORT_USE;
+ writel(control, &port->scontrol);
+}
+
+/*
+ * ide_preinit() will be called by ide_init in cmd_ide.c and will
+ * reset the MVSTATHC ports needed by the board.
+ */
+
+int ide_preinit(void)
+{
+ /* Enable ATA port 0 (could be SATA port 0 or 1) if declared */
+#if defined(CONFIG_SYS_ATA_IDE0_OFFSET)
+ mvsata_ide_initialize_port(
+ (struct mvsata_port_registers *)
+ (CONFIG_SYS_ATA_BASE_ADDR + CONFIG_SYS_ATA_IDE0_OFFSET));
+#endif
+ /* Enable ATA port 1 (could be SATA port 0 or 1) if declared */
+#if defined(CONFIG_SYS_ATA_IDE1_OFFSET)
+ mvsata_ide_initialize_port(
+ (struct mvsata_port_registers *)
+ (CONFIG_SYS_ATA_BASE_ADDR + CONFIG_SYS_ATA_IDE1_OFFSET));
+#endif
+ /* return 0 as we always succeed */
+ return 0;
+}
#define CONFIG_SYS_ATA_DATA_OFFSET 0x200 /* data reg offset */
#define CONFIG_SYS_ATA_REG_OFFSET 0x200 /* reg offset */
#define CONFIG_SYS_ATA_ALT_OFFSET 0x210 /* alternate register offset */
+#define CONFIG_IDE_SWAP_IO
/* if you use all NOR Flash , you change dip-switch. Please see Manual. */
#define CONFIG_SYS_MAX_FLASH_BANKS 1
#define ORION5X_MPP0_7 0x00000003
#define ORION5X_MPP8_15 0x55550000
-#define ORION5X_MPP16_23 0x00000000
+#define ORION5X_MPP16_23 0x00005555
/*
* Board-specific values for Orion5x GPIO low level init:
* Commands configuration - using default command set for now
*/
#include <config_cmd_default.h>
+#define CONFIG_CMD_IDE
/*
* Network
#define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */
#endif
+/*
+ * IDE
+ */
+#ifdef CONFIG_CMD_IDE
+#define __io
+#define CONFIG_IDE_PREINIT
+#define CONFIG_DOS_PARTITION
+#define CONFIG_CMD_EXT2
+/* ED Mini V has an IDE-compatible SATA connector for port 1 */
+#define CONFIG_MVSATA_IDE
+#define CONFIG_MVSATA_IDE_USE_PORT1
+/* Needs byte-swapping for ATA data register */
+#define CONFIG_IDE_SWAP_IO
+/* Data, registers and alternate blocks are at the same offset */
+#define CONFIG_SYS_ATA_DATA_OFFSET (0x0100)
+#define CONFIG_SYS_ATA_REG_OFFSET (0x0100)
+#define CONFIG_SYS_ATA_ALT_OFFSET (0x0100)
+/* Each 8-bit ATA register is aligned to a 4-bytes address */
+#define CONFIG_SYS_ATA_STRIDE 4
+/* Controller supports 48-bits LBA addressing */
+#define CONFIG_LBA48
+/* A single bus, a single device */
+#define CONFIG_SYS_IDE_MAXBUS 1
+#define CONFIG_SYS_IDE_MAXDEVICE 1
+/* ATA registers base is at SATA controller base */
+#define CONFIG_SYS_ATA_BASE_ADDR ORION5X_SATA_BASE
+/* ATA bus 0 is orion5x port 1 on ED Mini V2 */
+#define CONFIG_SYS_ATA_IDE0_OFFSET ORION5X_SATA_PORT1_OFFSET
+/* end of IDE defines */
+#endif /* CMD_IDE */
+
/*
* Environment variables configurations
*/
#define CONFIG_SYS_ATA_DATA_OFFSET 0 /* data reg offset */
#define CONFIG_SYS_ATA_REG_OFFSET 0 /* reg offset */
#define CONFIG_SYS_ATA_ALT_OFFSET 0x200 /* alternate register offset */
+#define CONFIG_IDE_SWAP_IO
#endif /* __MS7720SE_H */
#define CONFIG_CMD_NAND
#define CONFIG_CMD_PING
#define CONFIG_CMD_USB
+#define CONFIG_CMD_IDE
/*
* NAND configuration
#define CONFIG_SUPPORT_VFAT
#endif /* CONFIG_CMD_USB */
+/*
+ * IDe Support on SATA port0
+ */
+#ifdef CONFIG_CMD_IDE
+#define __io
+#define CONFIG_CMD_EXT2
+#define CONFIG_MVSATA_IDE
+#define CONFIG_IDE_PREINIT
+#define CONFIG_MVSATA_IDE_USE_PORT1
+/* Needs byte-swapping for ATA data register */
+#define CONFIG_IDE_SWAP_IO
+/* Data, registers and alternate blocks are at the same offset */
+#define CONFIG_SYS_ATA_DATA_OFFSET (0x0100)
+#define CONFIG_SYS_ATA_REG_OFFSET (0x0100)
+#define CONFIG_SYS_ATA_ALT_OFFSET (0x0100)
+/* Each 8-bit ATA register is aligned to a 4-bytes address */
+#define CONFIG_SYS_ATA_STRIDE 4
+/* Controller supports 48-bits LBA addressing */
+#define CONFIG_LBA48
+/* CONFIG_CMD_IDE requires some #defines for ATA registers */
+#define CONFIG_SYS_IDE_MAXBUS 2
+#define CONFIG_SYS_IDE_MAXDEVICE 2
+/* ATA registers base is at SATA controller base */
+#define CONFIG_SYS_ATA_BASE_ADDR KW_SATA_BASE
+/* ATA bus 0 is Kirkwood port 0 on openrd */
+#define CONFIG_SYS_ATA_IDE0_OFFSET KW_SATA_PORT0_OFFSET
+/* ATA bus 1 is Kirkwood port 1 on openrd */
+#define CONFIG_SYS_ATA_IDE1_OFFSET KW_SATA_PORT1_OFFSET
+#endif /* CONFIG_CMD_IDE */
+
/*
* File system
*/
#define CONFIG_SYS_ATA_DATA_OFFSET 0x1000 /* data reg offset */
#define CONFIG_SYS_ATA_REG_OFFSET 0x1000 /* reg offset */
#define CONFIG_SYS_ATA_ALT_OFFSET 0x800 /* alternate register offset */
+#define CONFIG_IDE_SWAP_IO
/*
* SuperH PCI Bridge Configration
#define CONFIG_SYS_ATA_DATA_OFFSET 0x1000 /* data reg offset */
#define CONFIG_SYS_ATA_REG_OFFSET 0x1000 /* reg offset */
#define CONFIG_SYS_ATA_ALT_OFFSET 0x800 /* alternate register offset */
+#define CONFIG_IDE_SWAP_IO
#endif /* CONFIG_CMD_IDE */
#endif /* __R7780RP_H */
projects / karo-tx-uboot.git / commitdiff