arm: remove bogus cp_delay() function

Due to a missing 'volatile' in the get_cr() function, the asm
instruction may be optimized away by the compiler.
This bug has been papered over with a delay loop after reading the
CP15 control register.
Fix the asm statement and remove the bogus workaround.

diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h
index 868ea54b4fef2c2d9d9819a986ca58f5e9c7800b..ae0cee6a00e32f40410ee3fd8547f621b05fd139 100644 (file)
--- a/arch/arm/include/asm/system.h
+++ b/arch/arm/include/asm/system.h
@@ -194,7 +194,8 @@ void save_boot_params_ret(void);
 static inline unsigned int get_cr(void)
 {
        unsigned int val;
-       asm("mrc p15, 0, %0, c1, c0, 0  @ get CR" : "=r" (val) : : "cc");
+       asm volatile("mrc p15, 0, %0, c1, c0, 0 @ get CR"
+         : "=r" (val) : : "cc");
        return val;
 }
 
@@ -208,7 +209,8 @@ static inline void set_cr(unsigned int val)
 static inline unsigned int get_dacr(void)
 {
        unsigned int val;
-       asm("mrc p15, 0, %0, c3, c0, 0  @ get DACR" : "=r" (val) : : "cc");
+       asm volatile("mrc p15, 0, %0, c3, c0, 0 @ get DACR"
+         : "=r" (val) : : "cc");
        return val;
 }
 

diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c
index c65e068857a2737f58d3ec70535dbb156af3d468..19e418cd28e08c92b6e5dd93e2d6a6bbe8fa5b72 100644 (file)
--- a/arch/arm/lib/cache-cp15.c
+++ b/arch/arm/lib/cache-cp15.c
@@ -22,16 +22,6 @@ __weak void arm_init_domains(void)
 {
 }
 
-static void cp_delay (void)
-{
-       volatile int i;
-
-       /* copro seems to need some delay between reading and writing */
-       for (i = 0; i < 100; i++)
-               nop();
-       asm volatile("" : : : "memory");
-}
-
 void set_section_dcache(int section, enum dcache_option option)
 {
        u32 *page_table = (u32 *)gd->arch.tlb_addr;
@@ -121,7 +111,6 @@ static inline void mmu_setup(void)
 
        /* and enable the mmu */
        reg = get_cr(); /* get control reg. */
-       cp_delay();
        set_cr(reg | CR_M);
 }
 
@@ -139,7 +128,6 @@ static void cache_enable(uint32_t cache_bit)
        if ((cache_bit == CR_C) && !mmu_enabled())
                mmu_setup();
        reg = get_cr(); /* get control reg. */
-       cp_delay();
        set_cr(reg | cache_bit);
 }
 
@@ -149,7 +137,6 @@ static void cache_disable(uint32_t cache_bit)
        uint32_t reg;
 
        reg = get_cr();
-       cp_delay();
 
        if (cache_bit == CR_C) {
                /* if cache isn;t enabled no need to disable */
@@ -159,7 +146,6 @@ static void cache_disable(uint32_t cache_bit)
                cache_bit |= CR_M;
        }
        reg = get_cr();
-       cp_delay();
        if (cache_bit == (CR_C | CR_M))
                flush_dcache_all();
        set_cr(reg & ~cache_bit);