From: Lothar Waßmann Date: Mon, 18 Apr 2016 12:45:01 +0000 (+0200) Subject: karo: tx6: add support for TX6Q-8037 (i.MX6QP) X-Git-Tag: KARO-TX6-2016-04-26~7 X-Git-Url: https://git.kernelconcepts.de/?p=karo-tx-uboot.git;a=commitdiff_plain;h=0bacb4d60fb1d17a66c032eb13ed8d01599bcc37 karo: tx6: add support for TX6Q-8037 (i.MX6QP) --- diff --git a/board/karo/tx6/Kconfig b/board/karo/tx6/Kconfig index 8800d059c4..fbf1d2ad6f 100644 --- a/board/karo/tx6/Kconfig +++ b/board/karo/tx6/Kconfig @@ -56,6 +56,9 @@ config TX6UL select SOC_MX6UL select SYS_SDRAM_BUS_WIDTH_16 +config TX6QP + bool + # # variables selected depending on module variant # @@ -166,6 +169,14 @@ config TARGET_TX6UL_0011 select TX6UL select TX6_EMMC +config TARGET_TX6QP_8037 + bool "TX6QP-8037" + select SOC_MX6Q + select SYS_I2C + select SYS_I2C_MXC + select TX6_EMMC + select TX6QP + endchoice choice diff --git a/board/karo/tx6/lowlevel_init.S b/board/karo/tx6/lowlevel_init.S index d43c5dc482..d9abf72d4e 100644 --- a/board/karo/tx6/lowlevel_init.S +++ b/board/karo/tx6/lowlevel_init.S @@ -17,11 +17,12 @@ #define SDRAM_CLK CONFIG_SYS_SDRAM_CLK #ifdef PHYS_SDRAM_2_SIZE -#define SDRAM_SIZE (PHYS_SDRAM_1_SIZE + PHYS_SDRAM_2_SIZE) +#define SDRAM_SIZE ((PHYS_SDRAM_1_SIZE + PHYS_SDRAM_2_SIZE) / SZ_1M) #else -#define SDRAM_SIZE PHYS_SDRAM_1_SIZE +#define SDRAM_SIZE (PHYS_SDRAM_1_SIZE / SZ_1M) #endif +#define BIT(x) (1 << (x)) #define CCGR(m) (3 << ((m) * 2)) #define CPU_2_BE_32(l) \ @@ -30,6 +31,7 @@ (((l) >> 8) & 0x0000FF00) | \ (((l) >> 24) & 0x000000FF)) +#ifndef CONFIG_TX6QP #define CHECK_DCD_ADDR(a) ( \ ((a) >= 0x020E0000 && (a) <= 0x020E3FFF) /* IOMUXC */ || \ ((a) >= 0x020C4000 && (a) <= 0x020C7FFF) /* CCM */ || \ @@ -39,6 +41,18 @@ ((a) >= 0x08000000 && (a) <= 0x0FFEFFFF) /* EIM (CS0) */ || \ ((a) >= 0x021B8000 && (a) <= 0x021BBFFF) /* EIM registers */ || \ ((a) >= 0x10000000 && (a) <= 0xFFFFFFFF) /* SDRAM */) +#else +#define CHECK_DCD_ADDR(a) ( \ + ((a) >= 0x020E0000 && (a) <= 0x020E3FFF) /* IOMUXC */ || \ + ((a) >= 0x020C4000 && (a) <= 0x020C7FFF) /* CCM */ || \ + ((a) >= 0x020C8000 && (a) <= 0x020C8FFF) /* ANALOG */ || \ + ((a) >= 0x021B0000 && (a) <= 0x021B7FFF) /* MMDC */ || \ + ((a) >= 0x00907000 && (a) <= 0x00937FF0) /* OCRAM */ || \ + ((a) >= 0x08000000 && (a) <= 0x0FFEFFFF) /* EIM (CS0) */ || \ + ((a) >= 0x021B8000 && (a) <= 0x021BBFFF) /* EIM registers */ || \ + ((a) >= 0x10000000 && (a) <= 0xFFFFFFFF) /* SDRAM */ || \ + ((a) >= 0x00BB0000 && (a) <= 0x00BB003F) /* NoC DDR config */) +#endif .macro mxc_dcd_item addr, val .ifne CHECK_DCD_ADDR(\addr) @@ -114,6 +128,7 @@ dcd_end: #define CK_TO_NS(ck) (((ck) * 1000 + SDRAM_CLK / 2) / SDRAM_CLK) #define NS_TO_CK(ns) (((ns) * SDRAM_CLK + 999) / 1000) #define NS_TO_CK10(ns) DIV_ROUND_UP(NS_TO_CK(ns), 10) +#define NS_TO_CK100(ns) DIV_ROUND_UP(NS_TO_CK(ns), 100) #define PS_TO_CK(ps) DIV_ROUND_UP(NS_TO_CK(ps), 1000) .macro CK_VAL, name, clks, offs, max @@ -185,6 +200,10 @@ dcd_end: #error SDRAM clock out of range: 303 .. 800 #endif +#if SDRAM_SIZE < 2048 +#define ROW_ADDR_BITS 14 +#define COL_ADDR_BITS 10 + /* MDCFG0 0x0c */ NS_VAL tRFC, 160, 1, 255 /* clks - 1 (0..255) */ CK_MAX tXS, NS_TO_CK(CK_TO_NS(tRFC + 1) + 10), 5, 1, 255 /* clks - 1 (0..255) tRFC + 10 */ @@ -211,6 +230,39 @@ CK_MAX tRRD, NS_TO_CK(10), 4, 1, 7 /* clks - 1 (0..7) (MT41K128M16JT: 6ns) */ /* MDOR 0x30 */ CK_MAX tXPR, NS_TO_CK(CK_TO_NS(tRFC + 1) + 10), 5, 1, 255 /* clks - 1 (0..255) max(tRFC + 10, 5CK) */ +#else +/* 4096MiB SDRAM: IM4G16D3EABG-125I */ +#define ROW_ADDR_BITS 15 +#define COL_ADDR_BITS 10 + +/* MDCFG0 0x0c */ +NS_VAL tRFC, 260, 1, 255 /* clks - 1 (0..255) */ +CK_MAX tXS, NS_TO_CK(CK_TO_NS(tRFC + 1) + 10), 5, 1, 255 /* clks - 1 (0..255) tRFC + 10 */ +CK_MAX tXP, NS_TO_CK(6), 3, 1, 7 /* clks - 1 (0..7) */ /* max(3tCK, 7.5ns) */ +CK_MAX tXPDLL, NS_TO_CK(24), 2, 1, 15 /* clks - 1 (0..15) */ +NS_VAL tFAW, 30, 1, 31 /* clks - 1 (0..31) */ +CK_VAL tCL, CL_VAL, 3, 8 /* clks - 3 (0..8) CAS Latency */ + +/* MDCFG1 0x10 */ +CK_VAL tRCD, NS_TO_CK100(1375), 1, 7 /* clks - 1 (0..7) */ /* 13.75 */ +CK_VAL tRP, NS_TO_CK100(1375), 1, 7 /* clks - 1 (0..7) */ /* 13.75 */ +CK_VAL tRC, NS_TO_CK100(4875), 1, 31 /* clks - 1 (0..31) */ /* 48.75 */ +CK_VAL tRAS, NS_TO_CK(35), 1, 31 /* clks - 1 (0..31) */ /* 35 */ +CK_VAL tRPA, 1, 0, 1 /* clks (0..1) */ +NS_VAL tWR, 15, 1, 15 /* clks - 1 (0..15) */ +CK_VAL tMRD, 4, 1, 15 /* clks - 1 (0..15) */ +CK_VAL tCWL, CWL_VAL, 2, 6 /* clks - 2 (0..6) */ + +/* MDCFG2 0x14 */ +CK_VAL tDLLK, 512, 1, 511 /* clks - 1 (0..511) */ +CK_MAX tRTP, NS_TO_CK10(75), 4, 1, 7 /* clks - 1 (0..7) */ /* max(4tCK, 7.5ns) */ +CK_MAX tWTR, NS_TO_CK10(75), 4, 1, 7 /* clks - 1 (0..7) */ /* max(4tCK, 7.5ns) */ +CK_MAX tRRD, NS_TO_CK10(75), 4, 1, 7 /* clks - 1 (0..7) */ /* max(4tCK, 7.5ns) */ + +/* MDOR 0x30 */ +CK_MAX tXPR, NS_TO_CK(CK_TO_NS(tRFC + 1) + 10), 5, 1, 255 /* clks - 1 (0..255) max(tRFC + 10, 5CK) */ +#endif + #define tSDE_RST (DIV_ROUND_UP(200000, MDOR_CLK_PERIOD_ns) + 2) #define tRST_CKE (DIV_ROUND_UP(500000, MDOR_CLK_PERIOD_ns) + 2) @@ -247,9 +299,6 @@ CK_MAX tCKSRE, NS_TO_CK(10), 5, 0, 7 (PWDT << 8) \ ) -#define ROW_ADDR_BITS 14 -#define COL_ADDR_BITS 10 - #define Rtt_Nom 1 /* ODT: 0: off 1: RZQ/4 2: RZQ/2 3: RZQ/6 4: RZQ/12 5: RZQ/8 */ #define Rtt_WR 0 /* Dynamic ODT: 0: off 1: RZQ/4 2: RZQ/2 */ #define DLL_DISABLE 0 @@ -416,7 +465,9 @@ ivt_end: #define MMDC1_MDOR 0x021b0030 #define MMDC1_MDASP 0x021b0040 +#define MMDC1_MAARCR 0x021b0400 #define MMDC1_MAPSR 0x021b0404 +#define MMDC1_MADPCR0 0x021b0410 #define MMDC1_MPZQHWCTRL 0x021b0800 #define MMDC1_MPWLGCR 0x021b0808 @@ -493,7 +544,20 @@ ivt_end: #endif #ifdef CONFIG_SOC_MX6Q +#define IOMUXC_GPR0 0x020e0000 #define IOMUXC_GPR1 0x020e0004 +#define IOMUXC_GPR2 0x020e0008 +#define IOMUXC_GPR3 0x020e000c +#define IOMUXC_GPR4 0x020e0010 +#define IOMUXC_GPR5 0x020e0014 +#define IOMUXC_GPR6 0x020e0018 +#define IOMUXC_GPR7 0x020e001c +#define IOMUXC_GPR8 0x020e0020 +#define IOMUXC_GPR9 0x020e0024 +#define IOMUXC_GPR10 0x020e0028 +#define IOMUXC_GPR11 0x020e002c +#define IOMUXC_GPR12 0x020e0030 +#define IOMUXC_GPR13 0x020e0034 #define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA20 0x020e00a0 #define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA21 0x020e00a4 #define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA28 0x020e00c4 @@ -733,7 +797,11 @@ dcd_hdr: MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR4, CCGR(14)) MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR2, CCGR(7)) MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE) +#ifndef CONFIG_TX6QP MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CS2CDR, 0x006336c1) /* default: 0x007236c1 */ +#else + MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CS2CDR, 0x0061b6c1) /* default: 0x007236c1 */ +#endif MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_SET) MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR4, CCGR(14)) MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR2, CCGR(7)) @@ -759,6 +827,13 @@ dcd_hdr: /* IOMUX: */ MXC_DCD_ITEM(IOMUXC_GPR1, 0x48640005) /* default: 0x48400005 ENET_CLK output */ +#ifdef CONFIG_TX6QP + /* enable AXI cache for VDOA/VPU/IPU */ + MXC_DCD_ITEM(IOMUXC_GPR4, 0xf00000cf) + /* set IPU AXI-id1 Qos=0x1 AXI-id0/2/3 Qos=0x7 */ + MXC_DCD_ITEM(IOMUXC_GPR6, 0x77177717) + MXC_DCD_ITEM(IOMUXC_GPR7, 0x77177717) +#endif /* UART1 pad config */ MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7, 0x00000001) /* UART1 TXD */ MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6, 0x00000001) /* UART1 RXD */ @@ -978,6 +1053,11 @@ dcd_hdr: /* DDR3 calibration */ MXC_DCD_ITEM(MMDC1_MPPDCMPR2, 0x00000003) /* select default compare pattern for DQ calibration */ +#ifdef CONFIG_TX6QP + MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_SET) + MXC_DCD_ITEM(MMDC1_MAARCR, BIT(25)) /* MMDC reorder disable BOOT_CFG3[5:4] */ + MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE) +#endif MXC_DCD_ITEM(MMDC1_MAPSR, 1) #ifdef DO_DDR_CALIB diff --git a/board/karo/tx6/tx6qdl.c b/board/karo/tx6/tx6qdl.c index 1b3c39cacc..d2d1e8364f 100644 --- a/board/karo/tx6/tx6qdl.c +++ b/board/karo/tx6/tx6qdl.c @@ -357,6 +357,9 @@ int checkboard(void) } else if (is_cpu_type(MXC_CPU_MX6Q)) { cpu_str = "Q"; tx6_mod_suffix = "Q"; + } else if (is_cpu_type(MXC_CPU_MX6QP)) { + cpu_str = "QP"; + tx6_mod_suffix = "QP"; } printf("CPU: Freescale i.MX6%s rev%d.%d at %d MHz\n", @@ -399,18 +402,22 @@ static bool tx6_temp_check_enabled = true; #define TX6_DDR_SZ (ffs(CONFIG_SYS_SDRAM_BUS_WIDTH / 16) - 1) static char tx6_mem_table[] = { - '4', /* 256MiB SDRAM 16bit; 128MiB NAND */ - '1', /* 512MiB SDRAM 32bit; 128MiB NAND */ - '0', /* 1GiB SDRAM 64bit; 128MiB NAND */ - '?', /* 256MiB SDRAM 16bit; 256MiB NAND */ - '?', /* 512MiB SDRAM 32bit; 256MiB NAND */ - '2', /* 1GiB SDRAM 64bit; 256MiB NAND */ - '?', /* 256MiB SDRAM 16bit; 4GiB eMMC */ - '5', /* 512MiB SDRAM 32bit; 4GiB eMMC */ - '3', /* 1GiB SDRAM 64bit; 4GiB eMMC */ - '?', /* 256MiB SDRAM 16bit; 8GiB eMMC */ - '?', /* 512MiB SDRAM 32bit; 8GiB eMMC */ - '0', /* 1GiB SDRAM 64bit; 8GiB eMMC */ + '4', /* TX6S-8034 256MiB SDRAM 16bit; 128MiB NAND */ + '1', /* TX6U-8011 512MiB SDRAM 32bit; 128MiB NAND */ + '0', /* TX6Q-1030/TX6U-8030 1GiB SDRAM 64bit; 128MiB NAND */ + '?', /* N/A 256MiB SDRAM 16bit; 256MiB NAND */ + '?', /* N/A 512MiB SDRAM 32bit; 256MiB NAND */ + '2', /* TX6U-8012 1GiB SDRAM 64bit; 256MiB NAND */ + '?', /* N/A 256MiB SDRAM 16bit; 4GiB eMMC */ + '5', /* TX6S-8035 512MiB SDRAM 32bit; 4GiB eMMC */ + '3', /* TX6U-8033 1GiB SDRAM 64bit; 4GiB eMMC */ + '?', /* N/A 256MiB SDRAM 16bit; 8GiB eMMC */ + '?', /* N/A 512MiB SDRAM 32bit; 8GiB eMMC */ +#if defined(CONFIG_TX6_REV) && CONFIG_TX6_REV == 2 + '0', /* TX6Q-1020 (legacy) 1GiB SDRAM 64bit; 8GiB eMMC */ +#else + '6', /* TX6Q-1036 1GiB SDRAM 64bit; 8GiB eMMC */ +#endif }; static struct { @@ -431,7 +438,10 @@ static inline char tx6_mem_suffix(void) if (mem_idx >= ARRAY_SIZE(tx6_mem_table)) return '?'; - + if (CONFIG_SYS_SDRAM_CHIP_SIZE > 512) + return '7'; + if (mem_idx == 8) + return is_cpu_type(MXC_CPU_MX6Q) ? '6' : '3'; return tx6_mem_table[mem_idx]; }; diff --git a/configs/tx6qp-8037_defconfig b/configs/tx6qp-8037_defconfig new file mode 100644 index 0000000000..8f2947b164 --- /dev/null +++ b/configs/tx6qp-8037_defconfig @@ -0,0 +1,33 @@ +CONFIG_SYS_EXTRA_OPTIONS="MMC_BOOT_SIZE=1024" +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_TX6=y +CONFIG_TARGET_TX6QP_8037=y +CONFIG_TX6_UBOOT=y +CONFIG_BOOTP_DNS=y +CONFIG_BOOTP_GATEWAY=y +CONFIG_BOOTP_SUBNETMASK=y +CONFIG_CMD_BMP=y +CONFIG_CMD_BOOTCE=y +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_FUSE=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_MII=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PING=y +CONFIG_CMD_TIME=y +CONFIG_DOS_PARTITION=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_FEC_MXC=y +CONFIG_FEC_MXC_PHYADDR=0 +CONFIG_IMX_WATCHDOG=y +CONFIG_LCD=y +CONFIG_NET=y +CONFIG_NETDEVICES=y +CONFIG_PHY_SMSC=y +CONFIG_SYS_PROMPT="TX6QP U-Boot > " +CONFIG_SYS_SDRAM_CHIP_SIZE=1024 diff --git a/configs/tx6qp-8037_mfg_defconfig b/configs/tx6qp-8037_mfg_defconfig new file mode 100644 index 0000000000..dd26543e10 --- /dev/null +++ b/configs/tx6qp-8037_mfg_defconfig @@ -0,0 +1,32 @@ +CONFIG_SYS_EXTRA_OPTIONS="MMC_BOOT_SIZE=1024" +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_TX6=y +CONFIG_TARGET_TX6QP_8037=y +CONFIG_TX6_UBOOT_MFG=y +CONFIG_BOOTP_DNS=y +CONFIG_BOOTP_GATEWAY=y +CONFIG_BOOTP_SUBNETMASK=y +CONFIG_CMD_BMP=y +CONFIG_CMD_BOOTCE=y +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_FUSE=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_MII=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PING=y +CONFIG_CMD_TIME=y +CONFIG_DOS_PARTITION=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_FEC_MXC=y +CONFIG_FEC_MXC_PHYADDR=0 +CONFIG_IMX_WATCHDOG=y +CONFIG_NET=y +CONFIG_NETDEVICES=y +CONFIG_PHY_SMSC=y +CONFIG_SYS_PROMPT="TX6QP U-Boot > " +CONFIG_SYS_SDRAM_CHIP_SIZE=1024 diff --git a/configs/tx6qp-8037_noenv_defconfig b/configs/tx6qp-8037_noenv_defconfig new file mode 100644 index 0000000000..d363bb4e65 --- /dev/null +++ b/configs/tx6qp-8037_noenv_defconfig @@ -0,0 +1,32 @@ +CONFIG_SYS_EXTRA_OPTIONS="MMC_BOOT_SIZE=1024" +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_TX6=y +CONFIG_TARGET_TX6QP_8037=y +CONFIG_TX6_UBOOT_NOENV=y +CONFIG_BOOTP_DNS=y +CONFIG_BOOTP_GATEWAY=y +CONFIG_BOOTP_SUBNETMASK=y +CONFIG_CMD_BMP=y +CONFIG_CMD_BOOTCE=y +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_FUSE=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_MII=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PING=y +CONFIG_CMD_TIME=y +CONFIG_DOS_PARTITION=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_FEC_MXC=y +CONFIG_FEC_MXC_PHYADDR=0 +CONFIG_IMX_WATCHDOG=y +CONFIG_NET=y +CONFIG_NETDEVICES=y +CONFIG_PHY_SMSC=y +CONFIG_SYS_PROMPT="TX6QP U-Boot > " +CONFIG_SYS_SDRAM_CHIP_SIZE=1024 diff --git a/configs/tx6qp-8037_sec_defconfig b/configs/tx6qp-8037_sec_defconfig new file mode 100644 index 0000000000..70b9d7c403 --- /dev/null +++ b/configs/tx6qp-8037_sec_defconfig @@ -0,0 +1,33 @@ +CONFIG_SYS_EXTRA_OPTIONS="MMC_BOOT_SIZE=1024,SECURE_BOOT" +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_TX6=y +CONFIG_TARGET_TX6QP_8037=y +CONFIG_TX6_UBOOT=y +CONFIG_BOOTP_DNS=y +CONFIG_BOOTP_GATEWAY=y +CONFIG_BOOTP_SUBNETMASK=y +CONFIG_CMD_BMP=y +CONFIG_CMD_BOOTCE=y +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_FUSE=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_MII=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PING=y +CONFIG_CMD_TIME=y +CONFIG_DOS_PARTITION=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_FEC_MXC=y +CONFIG_FEC_MXC_PHYADDR=0 +CONFIG_IMX_WATCHDOG=y +CONFIG_LCD=y +CONFIG_NET=y +CONFIG_NETDEVICES=y +CONFIG_PHY_SMSC=y +CONFIG_SYS_PROMPT="TX6QP U-Boot > " +CONFIG_SYS_SDRAM_CHIP_SIZE=1024