From: Lothar Waßmann Date: Mon, 22 Apr 2013 10:39:49 +0000 (+0200) Subject: TX6 Release 2013-04-22 X-Git-Tag: KARO-TX6-2013-04-22~1 X-Git-Url: https://git.kernelconcepts.de/?p=karo-tx-uboot.git;a=commitdiff_plain;h=1e362dc3e799fd86722a60f5639e52a67dfc0658 TX6 Release 2013-04-22 --- 1e362dc3e799fd86722a60f5639e52a67dfc0658 diff --cc Makefile index be62a69e40,51bd918475..26326e96df --- a/Makefile +++ b/Makefile @@@ -93,7 -113,7 +111,7 @@@ export CHECKSR ifneq ($(BUILD_DIR),) saved-output := $(BUILD_DIR) --# Attempt to create a output directory. ++# Attempt to create an output directory. $(shell [ -d ${BUILD_DIR} ] || mkdir -p ${BUILD_DIR}) # Verify if it was successful. @@@ -446,15 -508,49 +509,50 @@@ $(obj)u-boot.ais: $(obj)spl/u-boo $(OBJCOPY) ${OBJCFLAGS} -I binary \ --pad-to=$(CONFIG_SPL_MAX_SIZE) -O binary \ $(obj)spl/u-boot-spl.ais $(obj)spl/u-boot-spl-pad.ais - cat $(obj)spl/u-boot-spl-pad.ais $(obj)u-boot.bin > \ + cat $(obj)spl/u-boot-spl-pad.ais $(obj)u-boot.img > \ $(obj)u-boot.ais - rm $(obj)spl/u-boot-spl{,-pad}.ais - $(obj)u-boot.bd: $(TOPDIR)/board/$(BOARDDIR)/u-boot.bd - sed "s:@@BUILD_DIR@@:$(obj):g" $< > $@ + # Specify the target for use in elftosb call + ELFTOSB_TARGET-$(CONFIG_MX28) = imx28 + -$(obj)u-boot.sb: $(obj)u-boot.bin $(obj)spl/u-boot-spl.bin - elftosb -zf $(ELFTOSB_TARGET-y) -c $(TOPDIR)/$(CPUDIR)/$(SOC)/u-boot-$(ELFTOSB_TARGET-y).bd \ ++$(obj)u-boot.sb: $(obj)u-boot.bin $(obj)spl/u-boot-spl.bin elftosb ++ cd $(OBJTREE); \ ++ $(TOPDIR)/$(SUBDIR_TOOLS)/elftosb/bld/linux/elftosb -zdf $(ELFTOSB_TARGET-y) -c $(TOPDIR)/$(CPUDIR)/$(SOC)/u-boot-$(ELFTOSB_TARGET-y).bd \ + -o $(obj)u-boot.sb + + # On x600 (SPEAr600) U-Boot is appended to U-Boot SPL. + # Both images are created using mkimage (crc etc), so that the ROM + # bootloader can check its integrity. Padding needs to be done to the + # SPL image (with mkimage header) and not the binary. Otherwise the resulting image + # which is loaded/copied by the ROM bootloader to SRAM doesn't fit. + # The resulting image containing both U-Boot images is called u-boot.spr + $(obj)u-boot.spr: $(obj)u-boot.img $(obj)spl/u-boot-spl.bin + $(obj)tools/mkimage -A $(ARCH) -T firmware -C none \ + -a $(CONFIG_SPL_TEXT_BASE) -e $(CONFIG_SPL_TEXT_BASE) -n XLOADER \ + -d $(obj)spl/u-boot-spl.bin $(obj)spl/u-boot-spl.img + tr "\000" "\377" < /dev/zero | dd ibs=1 count=$(CONFIG_SPL_PAD_TO) \ + of=$(obj)spl/u-boot-spl-pad.img 2>/dev/null + dd if=$(obj)spl/u-boot-spl.img of=$(obj)spl/u-boot-spl-pad.img \ + conv=notrunc 2>/dev/null + cat $(obj)spl/u-boot-spl-pad.img $(obj)u-boot.img > $@ + + ifeq ($(SOC),tegra20) + ifeq ($(CONFIG_OF_SEPARATE),y) + nodtb=dtb + dtbfile=$(obj)u-boot.dtb + else + nodtb=nodtb + dtbfile= + endif + + $(obj)u-boot-$(nodtb)-tegra.bin: $(obj)spl/u-boot-spl.bin $(obj)u-boot.bin $(dtbfile) + $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(CONFIG_SYS_TEXT_BASE) -O binary $(obj)spl/u-boot-spl $(obj)spl/u-boot-spl-pad.bin + cat $(obj)spl/u-boot-spl-pad.bin $(obj)u-boot.bin $(dtbfile) > $@ + rm $(obj)spl/u-boot-spl-pad.bin + endif - $(obj)u-boot.sb: $(obj)u-boot.bd elftosb $(obj)u-boot.bin $(obj)spl/u-boot-spl.bin - $(TOPDIR)/tools/elftosb/bld/linux/elftosb -zdf imx28 -c $< -o $@ + $(obj)u-boot-img.bin: $(obj)spl/u-boot-spl.bin $(obj)u-boot.img + cat $(obj)spl/u-boot-spl.bin $(obj)u-boot.img > $@ ifeq ($(CONFIG_SANDBOX),y) GEN_UBOOT = \ diff --cc arch/arm/cpu/arm926ejs/mxs/mxs.c index 887ab7129a,6ce8019b83..d314144f50 --- a/arch/arm/cpu/arm926ejs/mxs/mxs.c +++ b/arch/arm/cpu/arm926ejs/mxs/mxs.c @@@ -81,83 -81,59 +81,85 @@@ void enable_caches(void #endif } +#define MX28_HW_DIGCTL_MICROSECONDS (void *)0x8001c0c0 + - int mx28_wait_mask_set(struct mx28_register_32 *reg, uint32_t mask, int timeout) + int mxs_wait_mask_set(struct mxs_register_32 *reg, uint32_t mask, unsigned + int timeout) { - while (--timeout) { - if ((readl(®->reg) & mask) == mask) - break; + uint32_t start = readl(MX28_HW_DIGCTL_MICROSECONDS); + + /* Wait for at least one microsecond for the bit mask to be set */ + while (readl(MX28_HW_DIGCTL_MICROSECONDS) - start <= 1 || --timeout) { + if ((readl(®->reg) & mask) == mask) { + while (readl(MX28_HW_DIGCTL_MICROSECONDS) - start <= 1) + ; + return 0; + } udelay(1); } return !timeout; } - int mx28_wait_mask_clr(struct mx28_register_32 *reg, uint32_t mask, int timeout) + int mxs_wait_mask_clr(struct mxs_register_32 *reg, uint32_t mask, unsigned + int timeout) { - while (--timeout) { - if ((readl(®->reg) & mask) == 0) - break; + uint32_t start = readl(MX28_HW_DIGCTL_MICROSECONDS); + + /* Wait for at least one microsecond for the bit mask to be cleared */ + while (readl(MX28_HW_DIGCTL_MICROSECONDS) - start <= 1 || --timeout) { + if ((readl(®->reg) & mask) == 0) { + while (readl(MX28_HW_DIGCTL_MICROSECONDS) - start <= 1) + ; + return 0; + } udelay(1); } return !timeout; } - int mx28_reset_block(struct mx28_register_32 *reg) + int mxs_reset_block(struct mxs_register_32 *reg) { /* Clear SFTRST */ - writel(MX28_BLOCK_SFTRST, ®->reg_clr); + writel(MXS_BLOCK_SFTRST, ®->reg_clr); - if (mx28_wait_mask_clr(reg, MX28_BLOCK_SFTRST, RESET_MAX_TIMEOUT)) { - if (mxs_wait_mask_clr(reg, MXS_BLOCK_SFTRST, RESET_MAX_TIMEOUT)) ++ if (mxs_wait_mask_clr(reg, MXS_BLOCK_SFTRST, RESET_MAX_TIMEOUT)) { + printf("TIMEOUT waiting for SFTRST[%p] to clear: %08x\n", + reg, readl(®->reg)); return 1; + } /* Clear CLKGATE */ - writel(MX28_BLOCK_CLKGATE, ®->reg_clr); + writel(MXS_BLOCK_CLKGATE, ®->reg_clr); /* Set SFTRST */ - writel(MX28_BLOCK_SFTRST, ®->reg_set); + writel(MXS_BLOCK_SFTRST, ®->reg_set); /* Wait for CLKGATE being set */ - if (mx28_wait_mask_set(reg, MX28_BLOCK_CLKGATE, RESET_MAX_TIMEOUT)) { - if (mxs_wait_mask_set(reg, MXS_BLOCK_CLKGATE, RESET_MAX_TIMEOUT)) ++ if (mxs_wait_mask_set(reg, MXS_BLOCK_CLKGATE, RESET_MAX_TIMEOUT)) { + printf("TIMEOUT waiting for CLKGATE[%p] to set: %08x\n", + reg, readl(®->reg)); return 1; + } /* Clear SFTRST */ - writel(MX28_BLOCK_SFTRST, ®->reg_clr); + writel(MXS_BLOCK_SFTRST, ®->reg_clr); - if (mx28_wait_mask_clr(reg, MX28_BLOCK_SFTRST, RESET_MAX_TIMEOUT)) { - if (mxs_wait_mask_clr(reg, MXS_BLOCK_SFTRST, RESET_MAX_TIMEOUT)) ++ if (mxs_wait_mask_clr(reg, MXS_BLOCK_SFTRST, RESET_MAX_TIMEOUT)) { + printf("TIMEOUT waiting for SFTRST[%p] to clear: %08x\n", + reg, readl(®->reg)); return 1; + } /* Clear CLKGATE */ - writel(MX28_BLOCK_CLKGATE, ®->reg_clr); + writel(MXS_BLOCK_CLKGATE, ®->reg_clr); - if (mx28_wait_mask_clr(reg, MX28_BLOCK_CLKGATE, RESET_MAX_TIMEOUT)) { - if (mxs_wait_mask_clr(reg, MXS_BLOCK_CLKGATE, RESET_MAX_TIMEOUT)) ++ if (mxs_wait_mask_clr(reg, MXS_BLOCK_CLKGATE, RESET_MAX_TIMEOUT)) { + printf("TIMEOUT waiting for CLKGATE[%p] to clear: %08x\n", + reg, readl(®->reg)); return 1; + } return 0; } @@@ -179,11 -155,10 +181,11 @@@ int arch_misc_init(void } #endif +#ifdef CONFIG_ARCH_CPU_INIT int arch_cpu_init(void) { - struct mx28_clkctrl_regs *clkctrl_regs = - (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE; + struct mxs_clkctrl_regs *clkctrl_regs = + (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE; extern uint32_t _start; mx28_fixup_vt((uint32_t)&_start); @@@ -213,17 -188,50 +215,51 @@@ return 0; } +#endif #if defined(CONFIG_DISPLAY_CPUINFO) - int print_cpuinfo(void) + static const char *get_cpu_type(void) + { + struct mxs_digctl_regs *digctl_regs = + (struct mxs_digctl_regs *)MXS_DIGCTL_BASE; + + switch (readl(&digctl_regs->hw_digctl_chipid) & HW_DIGCTL_CHIPID_MASK) { + case HW_DIGCTL_CHIPID_MX28: + return "28"; + default: + return "??"; + } + } + + static const char *get_cpu_rev(void) { - struct mx28_spl_data *data = (struct mx28_spl_data *) - ((CONFIG_SYS_TEXT_BASE - sizeof(struct mx28_spl_data)) & ~0xf); + struct mxs_digctl_regs *digctl_regs = + (struct mxs_digctl_regs *)MXS_DIGCTL_BASE; + uint8_t rev = readl(&digctl_regs->hw_digctl_chipid) & 0x000000FF; + + switch (readl(&digctl_regs->hw_digctl_chipid) & HW_DIGCTL_CHIPID_MASK) { + case HW_DIGCTL_CHIPID_MX28: + switch (rev) { + case 0x1: + return "1.2"; + default: + return "??"; + } + default: + return "??"; + } + } - printf("Freescale i.MX28 family at %d MHz\n", - mxc_get_clock(MXC_ARM_CLK) / 1000000); - printf("BOOT: %s\n", mx28_boot_modes[data->boot_mode_idx].mode); + int print_cpuinfo(void) + { + struct mxs_spl_data *data = (struct mxs_spl_data *) + ((CONFIG_SYS_TEXT_BASE - sizeof(struct mxs_spl_data)) & ~0xf); + + printf("CPU: Freescale i.MX%s rev%s at %d MHz\n", + get_cpu_type(), + get_cpu_rev(), + mxc_get_clock(MXC_ARM_CLK) / 1000000); + printf("BOOT: %s\n", mxs_boot_modes[data->boot_mode_idx].mode); return 0; } #endif diff --cc arch/arm/cpu/arm926ejs/mxs/spl_boot.c index f0d012d2aa,1b8502eb9d..57da57dd9b --- a/arch/arm/cpu/arm926ejs/mxs/spl_boot.c +++ b/arch/arm/cpu/arm926ejs/mxs/spl_boot.c @@@ -39,16 -38,15 +38,17 @@@ * takes a few seconds to roll. The boot doesn't take that long, so to keep the * code simple, it doesn't take rolling into consideration. */ +/* + * There's nothing to be taken into consideration for the rollover. + * Two's complement arithmetic used correctly does all the magic automagically. + */ - #define HW_DIGCTRL_MICROSECONDS 0x8001c0c0 void early_delay(int delay) { - uint32_t st = readl(HW_DIGCTRL_MICROSECONDS); + struct mxs_digctl_regs *digctl_regs = + (struct mxs_digctl_regs *)MXS_DIGCTL_BASE; ++ u32 start = readl(&digctl_regs->hw_digctl_microseconds); - while (readl(HW_DIGCTRL_MICROSECONDS) - st < delay); - uint32_t st = readl(&digctl_regs->hw_digctl_microseconds); - st += delay; - while (st > readl(&digctl_regs->hw_digctl_microseconds)) - ; ++ while (readl(&digctl_regs->hw_digctl_microseconds) - start < delay); } #define MUX_CONFIG_BOOTMODE_PAD (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL) @@@ -110,10 -108,10 +110,10 @@@ void mxs_common_spl_init(const iomux_cf data->boot_mode_idx = bootmode; - mx28_power_wait_pswitch(); + mxs_power_wait_pswitch(); } -/* Support aparatus */ +/* Support apparatus */ inline void board_init_f(unsigned long bootflag) { for (;;) diff --cc arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c index 88a1259afb,401c51362b..fa2dd972db --- a/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c +++ b/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c @@@ -67,12 -131,14 +132,12 @@@ static void mxs_mem_init_clock(void /* Unbypass EMI */ writel(CLKCTRL_CLKSEQ_BYPASS_EMI, &clkctrl_regs->hw_clkctrl_clkseq_clr); - - early_delay(10000); } - static void mx28_mem_setup_cpu_and_hbus(void) + static void mxs_mem_setup_cpu_and_hbus(void) { - struct mx28_clkctrl_regs *clkctrl_regs = - (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE; + struct mxs_clkctrl_regs *clkctrl_regs = + (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE; /* Set fractional divider for ref_cpu to 480 * 18 / 19 = 454MHz * and ungate CPU clock */ @@@ -100,19 -163,22 +165,14 @@@ /* Disable CPU bypass */ writel(CLKCTRL_CLKSEQ_BYPASS_CPU, &clkctrl_regs->hw_clkctrl_clkseq_clr); -- -- early_delay(15000); } - #define HW_DIGCTRL_SCRATCH0 0x8001c280 - #define HW_DIGCTRL_SCRATCH1 0x8001c290 - static void data_abort_memdetect_handler(void) __attribute__((naked)); - static void data_abort_memdetect_handler(void) -static void mxs_mem_setup_vdda(void) ++static void __attribute__((naked)) data_abort_memdetect_handler(void) { - struct mxs_power_regs *power_regs = - (struct mxs_power_regs *)MXS_POWER_BASE; - - writel((0xc << POWER_VDDACTRL_TRG_OFFSET) | - (0x7 << POWER_VDDACTRL_BO_OFFSET_OFFSET) | - POWER_VDDACTRL_LINREG_OFFSET_1STEPS_BELOW, - &power_regs->hw_power_vddactrl); + asm volatile("subs pc, r14, #4"); } - uint32_t mx28_mem_get_size(void) + uint32_t mxs_mem_get_size(void) { uint32_t sz, da; uint32_t *vt = (uint32_t *)0x20; @@@ -144,11 -212,12 +204,11 @@@ void mxs_mem_init(void writel(CLKCTRL_PLL0CTRL0_POWER, &clkctrl_regs->hw_clkctrl_pll0ctrl0_set); - early_delay(11000); + /* enabling the PLL requires a 10µs delay before use as clk source */ + early_delay(11); - mx28_mem_init_clock(); + mxs_mem_init_clock(); - mxs_mem_setup_vdda(); - /* * Configure the DRAM registers */ @@@ -168,5 -237,7 +228,5 @@@ while (!(readl(MXS_DRAM_BASE + 0xe8) & (1 << 20))) ; - mx28_mem_setup_cpu_and_hbus(); - early_delay(10000); - + mxs_mem_setup_cpu_and_hbus(); } diff --cc arch/arm/cpu/arm926ejs/mxs/spl_power_init.c index 6b74e2e557,be44c22976..362df4cb66 --- a/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c +++ b/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c @@@ -28,72 -28,12 +28,72 @@@ #include #include - #include "mx28_init.h" + #include "mxs_init.h" +#ifdef CONFIG_SYS_SPL_VDDD_VAL +#define VDDD_VAL CONFIG_SYS_SPL_VDDD_VAL +#else +#define VDDD_VAL 1350 +#endif +#ifdef CONFIG_SYS_SPL_VDDIO_VAL +#define VDDIO_VAL CONFIG_SYS_SPL_VDDIO_VAL +#else +#define VDDIO_VAL 3300 +#endif +#ifdef CONFIG_SYS_SPL_VDDA_VAL +#define VDDA_VAL CONFIG_SYS_SPL_VDDA_VAL +#else +#define VDDA_VAL 1800 +#endif +#ifdef CONFIG_SYS_SPL_VDDMEM_VAL +#define VDDMEM_VAL CONFIG_SYS_SPL_VDDMEM_VAL +#else +#define VDDMEM_VAL 1500 +#endif + +#ifdef CONFIG_SYS_SPL_VDDD_BO_VAL +#define VDDD_BO_VAL CONFIG_SYS_SPL_VDDD_BO_VAL +#else +#define VDDD_BO_VAL 150 +#endif +#ifdef CONFIG_SYS_SPL_VDDIO_BO_VAL +#define VDDIO_BO_VAL CONFIG_SYS_SPL_VDDIO_BO_VAL +#else +#define VDDIO_BO_VAL 150 +#endif +#ifdef CONFIG_SYS_SPL_VDDA_BO_VAL +#define VDDA_BO_VAL CONFIG_SYS_SPL_VDDA_BO_VAL +#else +#define VDDA_BO_VAL 175 +#endif +#ifdef CONFIG_SYS_SPL_VDDMEM_BO_VAL +#define VDDMEM_BO_VAL CONFIG_SYS_SPL_VDDMEM_BO_VAL +#else +#define VDDMEM_BO_VAL 25 +#endif + +#ifdef CONFIG_SYS_SPL_BATT_BO_LEVEL +#if CONFIG_SYS_SPL_BATT_BO_LEVEL < 2400 || CONFIG_SYS_SPL_BATT_BO_LEVEL > 3640 +#error CONFIG_SYS_SPL_BATT_BO_LEVEL out of range +#endif +#define BATT_BO_VAL (((CONFIG_SYS_SPL_BATT_BO_LEVEL) - 2400) / 40) +#else +/* Brownout default at 3V */ +#define BATT_BO_VAL ((3000 - 2400) / 40) +#endif + +#ifdef CONFIG_SYS_SPL_FIXED_BATT_SUPPLY +static const int fixed_batt_supply = 1; +#else +static const int fixed_batt_supply; +#endif + - static struct mx28_power_regs *power_regs = (void *)MXS_POWER_BASE; ++static struct mxs_power_regs *power_regs = (void *)MXS_POWER_BASE; + - static void mx28_power_clock2xtal(void) + static void mxs_power_clock2xtal(void) { - struct mx28_clkctrl_regs *clkctrl_regs = - (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE; + struct mxs_clkctrl_regs *clkctrl_regs = + (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE; /* Set XTAL as CPU reference clock */ writel(CLKCTRL_CLKSEQ_BYPASS_CPU, @@@ -145,8 -85,11 +145,8 @@@ static void mxs_power_clear_auto_restar ; } - static void mx28_power_set_linreg(void) + static void mxs_power_set_linreg(void) { - struct mxs_power_regs *power_regs = - (struct mxs_power_regs *)MXS_POWER_BASE; - /* Set linear regulator 25mV below switching converter */ clrsetbits_le32(&power_regs->hw_power_vdddctrl, POWER_VDDDCTRL_LINREG_OFFSET_MASK, @@@ -161,27 -104,27 +161,24 @@@ POWER_VDDIOCTRL_LINREG_OFFSET_1STEPS_BELOW); } - int mx28_get_batt_volt(void) + static int mxs_get_batt_volt(void) { - struct mx28_power_regs *power_regs = - (struct mx28_power_regs *)MXS_POWER_BASE; - struct mxs_power_regs *power_regs = - (struct mxs_power_regs *)MXS_POWER_BASE; uint32_t volt = readl(&power_regs->hw_power_battmonitor); ++ volt &= POWER_BATTMONITOR_BATT_VAL_MASK; volt >>= POWER_BATTMONITOR_BATT_VAL_OFFSET; volt *= 8; return volt; } - int mx28_is_batt_ready(void) + static int mxs_is_batt_ready(void) { - return (mx28_get_batt_volt() >= 3600); + return (mxs_get_batt_volt() >= 3600); } - int mx28_is_batt_good(void) + static int mxs_is_batt_good(void) { - struct mx28_power_regs *power_regs = - (struct mx28_power_regs *)MXS_POWER_BASE; - uint32_t volt = mx28_get_batt_volt(); - struct mxs_power_regs *power_regs = - (struct mxs_power_regs *)MXS_POWER_BASE; + uint32_t volt = mxs_get_batt_volt(); if ((volt >= 2400) && (volt <= 4300)) return 1; @@@ -217,8 -160,11 +214,8 @@@ return 0; } - static void mx28_power_setup_5v_detect(void) + static void mxs_power_setup_5v_detect(void) { - struct mxs_power_regs *power_regs = - (struct mxs_power_regs *)MXS_POWER_BASE; - /* Start 5V detection */ clrsetbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_VBUSVALID_TRSH_MASK, @@@ -226,8 -172,11 +223,8 @@@ POWER_5VCTRL_PWRUP_VBUS_CMPS); } - static void mx28_src_power_init(void) + static void mxs_src_power_init(void) { - struct mxs_power_regs *power_regs = - (struct mxs_power_regs *)MXS_POWER_BASE; - /* Improve efficieny and reduce transient ripple */ writel(POWER_LOOPCTRL_TOGGLE_DIF | POWER_LOOPCTRL_EN_CM_HYST | POWER_LOOPCTRL_EN_DF_HYST, &power_regs->hw_power_loopctrl_set); @@@ -254,16 -197,17 +251,16 @@@ clrsetbits_le32(&power_regs->hw_power_minpwr, POWER_MINPWR_HALFFETS, POWER_MINPWR_DOUBLE_FETS); - /* 5V to battery handoff ... FIXME */ - setbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER); - early_delay(30); - clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER); + if (!fixed_batt_supply) { + /* 5V to battery handoff ... FIXME */ + setbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER); + early_delay(30); + clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER); + } } - static void mx28_power_init_4p2_params(void) + static void mxs_power_init_4p2_params(void) { - struct mxs_power_regs *power_regs = - (struct mxs_power_regs *)MXS_POWER_BASE; - /* Setup 4P2 parameters */ clrsetbits_le32(&power_regs->hw_power_dcdc4p2, POWER_DCDC4P2_CMPTRIP_MASK | POWER_DCDC4P2_TRG_MASK, @@@ -283,8 -227,10 +280,8 @@@ 0x3f << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET); } - static void mx28_enable_4p2_dcdc_input(int xfer) + static void mxs_enable_4p2_dcdc_input(int xfer) { - struct mxs_power_regs *power_regs = - (struct mxs_power_regs *)MXS_POWER_BASE; uint32_t tmp, vbus_thresh, vbus_5vdetect, pwd_bo; uint32_t prev_5v_brnout, prev_5v_droop; @@@ -377,8 -323,10 +374,8 @@@ POWER_CTRL_ENIRQ_VDD5V_DROOP); } - static void mx28_power_init_4p2_regulator(void) + static void mxs_power_init_4p2_regulator(void) { - struct mxs_power_regs *power_regs = - (struct mxs_power_regs *)MXS_POWER_BASE; uint32_t tmp, tmp2; setbits_le32(&power_regs->hw_power_dcdc4p2, POWER_DCDC4P2_ENABLE_4P2); @@@ -459,8 -407,11 +456,8 @@@ writel(POWER_CTRL_DCDC4P2_BO_IRQ, &power_regs->hw_power_ctrl_clr); } - static void mx28_power_init_dcdc_4p2_source(void) + static void mxs_power_init_dcdc_4p2_source(void) { - struct mxs_power_regs *power_regs = - (struct mxs_power_regs *)MXS_POWER_BASE; - if (!(readl(&power_regs->hw_power_dcdc4p2) & POWER_DCDC4P2_ENABLE_DCDC)) { hang(); @@@ -478,8 -429,10 +475,8 @@@ } } - static void mx28_power_enable_4p2(void) + static void mxs_power_enable_4p2(void) { - struct mxs_power_regs *power_regs = - (struct mxs_power_regs *)MXS_POWER_BASE; uint32_t vdddctrl, vddactrl, vddioctrl; uint32_t tmp; @@@ -535,8 -488,11 +532,8 @@@ &power_regs->hw_power_charge_clr); } - static void mx28_boot_valid_5v(void) + static void mxs_boot_valid_5v(void) { - struct mxs_power_regs *power_regs = - (struct mxs_power_regs *)MXS_POWER_BASE; - /* * Use VBUSVALID level instead of VDD5V_GT_VDDIO level to trigger a 5V * disconnect event. FIXME @@@ -552,21 -508,23 +549,18 @@@ writel(POWER_CTRL_VBUS_VALID_IRQ | POWER_CTRL_VDD5V_GT_VDDIO_IRQ, &power_regs->hw_power_ctrl_clr); - mx28_power_enable_4p2(); + mxs_power_enable_4p2(); } - static void mx28_powerdown(void) + static void mxs_powerdown(void) { - struct mxs_power_regs *power_regs = - (struct mxs_power_regs *)MXS_POWER_BASE; writel(POWER_RESET_UNLOCK_KEY, &power_regs->hw_power_reset); writel(POWER_RESET_UNLOCK_KEY | POWER_RESET_PWD_OFF, &power_regs->hw_power_reset); } - void mx28_batt_boot(void) + static void mxs_batt_boot(void) { - struct mx28_power_regs *power_regs = - (struct mx28_power_regs *)MXS_POWER_BASE; - struct mxs_power_regs *power_regs = - (struct mxs_power_regs *)MXS_POWER_BASE; -- clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_PWDN_5VBRNOUT); clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_ENABLE_DCDC); @@@ -606,8 -564,10 +600,8 @@@ 0x8 << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET); } - void mx28_handle_5v_conflict(void) + static void mxs_handle_5v_conflict(void) { - struct mxs_power_regs *power_regs = - (struct mxs_power_regs *)MXS_POWER_BASE; uint32_t tmp; setbits_le32(&power_regs->hw_power_vddioctrl, @@@ -636,8 -600,11 +634,8 @@@ } } - static void mx28_5v_boot(void) + static void mxs_5v_boot(void) { - struct mxs_power_regs *power_regs = - (struct mxs_power_regs *)MXS_POWER_BASE; - /* * NOTE: In original IMX-Bootlets, this also checks for VBUSVALID, * but their implementation always returns 1 so we omit it here. @@@ -653,52 -620,28 +651,52 @@@ return; } - mx28_handle_5v_conflict(); + mxs_handle_5v_conflict(); } - static void mx28_fixed_batt_boot(void) -static void mxs_init_batt_bo(void) ++static void mxs_fixed_batt_boot(void) { - struct mxs_power_regs *power_regs = - (struct mxs_power_regs *)MXS_POWER_BASE; + writel(POWER_CTRL_ENIRQ_BATT_BO, &power_regs->hw_power_ctrl_clr); + + setbits_le32(&power_regs->hw_power_5vctrl, + POWER_5VCTRL_PWDN_5VBRNOUT | + POWER_5VCTRL_ENABLE_DCDC | + POWER_5VCTRL_ILIMIT_EQ_ZERO | + POWER_5VCTRL_PWDN_5VBRNOUT | + POWER_5VCTRL_PWD_CHARGE_4P2_MASK); + + writel(POWER_CHARGE_PWD_BATTCHRG, &power_regs->hw_power_charge_set); + + clrbits_le32(&power_regs->hw_power_vdddctrl, + POWER_VDDDCTRL_DISABLE_FET | + POWER_VDDDCTRL_ENABLE_LINREG | + POWER_VDDDCTRL_DISABLE_STEPPING); + + clrbits_le32(&power_regs->hw_power_vddactrl, + POWER_VDDACTRL_DISABLE_FET | POWER_VDDACTRL_ENABLE_LINREG | + POWER_VDDACTRL_DISABLE_STEPPING); + + clrbits_le32(&power_regs->hw_power_vddioctrl, + POWER_VDDIOCTRL_DISABLE_FET | + POWER_VDDIOCTRL_DISABLE_STEPPING); - /* Brownout at 3V */ + /* Stop 5V detection */ + writel(POWER_5VCTRL_PWRUP_VBUS_CMPS, + &power_regs->hw_power_5vctrl_clr); +} + - static void mx28_init_batt_bo(void) ++static void mxs_init_batt_bo(void) +{ clrsetbits_le32(&power_regs->hw_power_battmonitor, POWER_BATTMONITOR_BRWNOUT_LVL_MASK, - 15 << POWER_BATTMONITOR_BRWNOUT_LVL_OFFSET); + BATT_BO_VAL << POWER_BATTMONITOR_BRWNOUT_LVL_OFFSET); writel(POWER_CTRL_BATT_BO_IRQ, &power_regs->hw_power_ctrl_clr); writel(POWER_CTRL_ENIRQ_BATT_BO, &power_regs->hw_power_ctrl_clr); } - static void mx28_switch_vddd_to_dcdc_source(void) + static void mxs_switch_vddd_to_dcdc_source(void) { - struct mxs_power_regs *power_regs = - (struct mxs_power_regs *)MXS_POWER_BASE; - clrsetbits_le32(&power_regs->hw_power_vdddctrl, POWER_VDDDCTRL_LINREG_OFFSET_MASK, POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_BELOW); @@@ -708,24 -651,49 +706,45 @@@ POWER_VDDDCTRL_DISABLE_STEPPING); } - static void mx28_power_configure_power_source(void) + static void mxs_power_configure_power_source(void) { - mx28_src_power_init(); - int batt_ready, batt_good; - struct mxs_power_regs *power_regs = - (struct mxs_power_regs *)MXS_POWER_BASE; + struct mxs_lradc_regs *lradc_regs = + (struct mxs_lradc_regs *)MXS_LRADC_BASE; - if (!fixed_batt_supply) - mx28_5v_boot(); - else - mx28_fixed_batt_boot(); + mxs_src_power_init(); - mx28_power_clock2pll(); - if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) { - batt_ready = mxs_is_batt_ready(); - if (batt_ready) { - /* 5V source detected, good battery detected. */ - mxs_batt_boot(); - } else { - batt_good = mxs_is_batt_good(); - if (!batt_good) { - /* 5V source detected, bad battery detected. */ - writel(LRADC_CONVERSION_AUTOMATIC, - &lradc_regs->hw_lradc_conversion_clr); - clrbits_le32(&power_regs->hw_power_battmonitor, - POWER_BATTMONITOR_BATT_VAL_MASK); ++ if (!fixed_batt_supply) { ++ if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) { ++ if (mxs_is_batt_ready()) { ++ /* 5V source detected, good battery detected. */ ++ mxs_batt_boot(); ++ } else { ++ if (!mxs_is_batt_good()) { ++ /* 5V source detected, bad battery detected. */ ++ writel(LRADC_CONVERSION_AUTOMATIC, ++ &lradc_regs->hw_lradc_conversion_clr); ++ clrbits_le32(&power_regs->hw_power_battmonitor, ++ POWER_BATTMONITOR_BATT_VAL_MASK); ++ } ++ mxs_5v_boot(); + } - mxs_5v_boot(); ++ } else { ++ /* 5V not detected, booting from battery. */ ++ mxs_batt_boot(); + } + } else { - /* 5V not detected, booting from battery. */ - mxs_batt_boot(); ++ mxs_fixed_batt_boot(); + } + + mxs_power_clock2pll(); - mx28_init_batt_bo(); + mxs_init_batt_bo(); - mx28_switch_vddd_to_dcdc_source(); + mxs_switch_vddd_to_dcdc_source(); } - static void mx28_enable_output_rail_protection(void) + static void mxs_enable_output_rail_protection(void) { - struct mxs_power_regs *power_regs = - (struct mxs_power_regs *)MXS_POWER_BASE; - writel(POWER_CTRL_VDDD_BO_IRQ | POWER_CTRL_VDDA_BO_IRQ | POWER_CTRL_VDDIO_BO_IRQ, &power_regs->hw_power_ctrl_clr); @@@ -739,14 -707,13 +758,14 @@@ POWER_VDDIOCTRL_PWDN_BRNOUT); } - static inline int mx28_get_vddio_power_source_off(void) + static int mxs_get_vddio_power_source_off(void) { - struct mxs_power_regs *power_regs = - (struct mxs_power_regs *)MXS_POWER_BASE; uint32_t tmp; - if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) { + if ((readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) && + !(readl(&power_regs->hw_power_5vctrl) & + POWER_5VCTRL_ILIMIT_EQ_ZERO)) { + tmp = readl(&power_regs->hw_power_vddioctrl); if (tmp & POWER_VDDIOCTRL_DISABLE_FET) { if ((tmp & POWER_VDDIOCTRL_LINREG_OFFSET_MASK) == @@@ -765,10 -732,13 +784,10 @@@ } return 0; - } - static inline int mx28_get_vddd_power_source_off(void) + static int mxs_get_vddd_power_source_off(void) { - struct mxs_power_regs *power_regs = - (struct mxs_power_regs *)MXS_POWER_BASE; uint32_t tmp; tmp = readl(&power_regs->hw_power_vdddctrl); @@@ -796,229 -766,139 +815,209 @@@ return 0; } - static inline int mx28_get_vdda_power_source_off(void) ++static int mxs_get_vdda_power_source_off(void) +{ + uint32_t tmp; + + tmp = readl(&power_regs->hw_power_vddactrl); + if (tmp & POWER_VDDACTRL_DISABLE_FET) { + if ((tmp & POWER_VDDACTRL_LINREG_OFFSET_MASK) == - POWER_VDDACTRL_LINREG_OFFSET_0STEPS) ++ POWER_VDDACTRL_LINREG_OFFSET_0STEPS) { + return 1; ++ } + } + + if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) { + if (!(readl(&power_regs->hw_power_5vctrl) & - POWER_5VCTRL_ENABLE_DCDC)) ++ POWER_5VCTRL_ENABLE_DCDC)) { + return 1; ++ } + } + + if (!(tmp & POWER_VDDACTRL_ENABLE_LINREG)) { + if ((tmp & POWER_VDDACTRL_LINREG_OFFSET_MASK) == - POWER_VDDACTRL_LINREG_OFFSET_1STEPS_BELOW) ++ POWER_VDDACTRL_LINREG_OFFSET_1STEPS_BELOW) { + return 1; ++ } + } ++ + return 0; +} + - static inline void mx28_power_set_vddx( - uint32_t new_target, uint32_t new_brownout, - uint32_t *reg, const char *name, - uint32_t min_trg, uint32_t max_trg, - uint8_t step_size, - uint32_t trg_mask, uint32_t trg_shift, - uint32_t bo_mask, uint32_t bo_shift, - int powered_by_linreg) + struct mxs_vddx_cfg { + uint32_t *reg; + uint8_t step_mV; + uint16_t lowest_mV; ++ uint16_t highest_mV; + int (*powered_by_linreg)(void); + uint32_t trg_mask; + uint32_t bo_irq; + uint32_t bo_enirq; + uint32_t bo_offset_mask; + uint32_t bo_offset_offset; + }; + + static const struct mxs_vddx_cfg mxs_vddio_cfg = { + .reg = &(((struct mxs_power_regs *)MXS_POWER_BASE)-> + hw_power_vddioctrl), + .step_mV = 50, + .lowest_mV = 2800, ++ .highest_mV = 3600, + .powered_by_linreg = mxs_get_vddio_power_source_off, + .trg_mask = POWER_VDDIOCTRL_TRG_MASK, + .bo_irq = POWER_CTRL_VDDIO_BO_IRQ, + .bo_enirq = POWER_CTRL_ENIRQ_VDDIO_BO, + .bo_offset_mask = POWER_VDDIOCTRL_BO_OFFSET_MASK, + .bo_offset_offset = POWER_VDDIOCTRL_BO_OFFSET_OFFSET, + }; + + static const struct mxs_vddx_cfg mxs_vddd_cfg = { + .reg = &(((struct mxs_power_regs *)MXS_POWER_BASE)-> + hw_power_vdddctrl), + .step_mV = 25, + .lowest_mV = 800, ++ .highest_mV = 1575, + .powered_by_linreg = mxs_get_vddd_power_source_off, + .trg_mask = POWER_VDDDCTRL_TRG_MASK, + .bo_irq = POWER_CTRL_VDDD_BO_IRQ, + .bo_enirq = POWER_CTRL_ENIRQ_VDDD_BO, + .bo_offset_mask = POWER_VDDDCTRL_BO_OFFSET_MASK, + .bo_offset_offset = POWER_VDDDCTRL_BO_OFFSET_OFFSET, + }; + ++static const struct mxs_vddx_cfg mxs_vdda_cfg = { ++ .reg = &(((struct mxs_power_regs *)MXS_POWER_BASE)-> ++ hw_power_vddactrl), ++ .step_mV = 50, ++ .lowest_mV = 2800, ++ .highest_mV = 3600, ++ .powered_by_linreg = mxs_get_vdda_power_source_off, ++ .trg_mask = POWER_VDDACTRL_TRG_MASK, ++ .bo_irq = POWER_CTRL_VDDA_BO_IRQ, ++ .bo_enirq = POWER_CTRL_ENIRQ_VDDA_BO, ++ .bo_offset_mask = POWER_VDDACTRL_BO_OFFSET_MASK, ++ .bo_offset_offset = POWER_VDDACTRL_BO_OFFSET_OFFSET, ++}; ++ ++static const struct mxs_vddx_cfg mxs_vddmem_cfg = { ++ .reg = &(((struct mxs_power_regs *)MXS_POWER_BASE)-> ++ hw_power_vddmemctrl), ++ .step_mV = 25, ++ .lowest_mV = 1100, ++ .highest_mV = 1750, ++ .bo_offset_mask = POWER_VDDMEMCTRL_BO_OFFSET_MASK, ++ .bo_offset_offset = POWER_VDDMEMCTRL_BO_OFFSET_OFFSET, ++}; ++ + static void mxs_power_set_vddx(const struct mxs_vddx_cfg *cfg, + uint32_t new_target, uint32_t new_brownout) { - uint32_t cur_target, cur_brownout; - uint32_t diff; - - if (new_target < min_trg || new_target > max_trg) - new_target = (new_target > max_trg) ? max_trg : min_trg; - - if (new_brownout / step_size > 7) - new_brownout = 7 * step_size; - - cur_target = readl(reg); - - cur_brownout = (cur_target & bo_mask) >> bo_shift; - cur_brownout *= step_size; - - cur_target = (cur_target & trg_mask) >> trg_shift; - cur_target *= step_size; - cur_target += min_trg; - if (cur_target > max_trg) - cur_target = max_trg; - - if (new_target == cur_target && new_brownout == cur_brownout) - return; - struct mxs_power_regs *power_regs = - (struct mxs_power_regs *)MXS_POWER_BASE; + uint32_t cur_target, diff, bo_int = 0; - uint32_t powered_by_linreg = 0; - int adjust_up, tmp; ++ int powered_by_linreg = 0; ++ int adjust_up; ++ ++ if (new_target < cfg->lowest_mV) ++ new_target = cfg->lowest_mV; ++ if (new_target > cfg->highest_mV) ++ new_target = cfg->highest_mV; + + new_brownout = DIV_ROUND(new_target - new_brownout, cfg->step_mV); + + cur_target = readl(cfg->reg); + cur_target &= cfg->trg_mask; + cur_target *= cfg->step_mV; + cur_target += cfg->lowest_mV; + + adjust_up = new_target > cur_target; - powered_by_linreg = cfg->powered_by_linreg(); ++ if (cfg->powered_by_linreg) ++ powered_by_linreg = cfg->powered_by_linreg(); + + if (adjust_up) { + if (powered_by_linreg) { + bo_int = readl(cfg->reg); + clrbits_le32(cfg->reg, cfg->bo_enirq); + } + setbits_le32(cfg->reg, cfg->bo_offset_mask); + } - if (new_target > cur_target) { - setbits_le32(reg, bo_mask); - do { - if (new_target - cur_target > 100) + do { + if (abs(new_target - cur_target) > 100) { + if (adjust_up) diff = cur_target + 100; else - diff = new_target; - - diff -= min_trg; - diff /= step_size; - - clrsetbits_le32(reg, trg_mask, diff); - - if (powered_by_linreg) { - early_delay(1500); - } else { - while (!(readl(&power_regs->hw_power_sts) & - POWER_STS_DC_OK)) { - } - } - - cur_target = readl(reg); - cur_target &= trg_mask; - cur_target *= step_size; - cur_target += min_trg; - } while (new_target > cur_target); - } else { - do { - if (cur_target - new_target > 100) diff = cur_target - 100; - else - diff = new_target; + } else { + diff = new_target; + } - diff -= min_trg; - diff /= step_size; + diff -= cfg->lowest_mV; + diff /= cfg->step_mV; - clrsetbits_le32(reg, trg_mask, diff); + clrsetbits_le32(cfg->reg, cfg->trg_mask, diff); - if (powered_by_linreg) { - early_delay(1500); - } else { - while (!(readl(&power_regs->hw_power_sts) & + if (powered_by_linreg || + (readl(&power_regs->hw_power_sts) & - POWER_STS_VDD5V_GT_VDDIO)) ++ POWER_STS_VDD5V_GT_VDDIO)) { + early_delay(500); - else { - for (;;) { - tmp = readl(&power_regs->hw_power_sts); - if (tmp & POWER_STS_DC_OK) - break; ++ } else { ++ while (!(readl(&power_regs->hw_power_sts) & + POWER_STS_DC_OK)) { - } - } - - cur_target = readl(reg); - cur_target &= trg_mask; - cur_target *= step_size; - cur_target += min_trg; - } while (new_target < cur_target); - } - - clrsetbits_le32(reg, bo_mask, (new_brownout / step_size) << bo_shift); - } + - #define __mx28_power_set_vddx(trg, bo, min, max, step, reg, name, lr) \ - mx28_power_set_vddx(trg, bo, \ - &power_regs->hw_power_##reg##ctrl, #name, \ - min, max, step, \ - POWER_##name##CTRL_TRG_MASK, \ - POWER_##name##CTRL_TRG_OFFSET, \ - POWER_##name##CTRL_BO_OFFSET_MASK, \ - POWER_##name##CTRL_BO_OFFSET_OFFSET, lr) + } + } - static inline void mx28_power_set_vddd(uint32_t target, uint32_t brownout) - { - int powered_by_linreg = mx28_get_vddd_power_source_off(); - uint32_t bo_int = 0; + cur_target = readl(cfg->reg); + cur_target &= cfg->trg_mask; + cur_target *= cfg->step_mV; + cur_target += cfg->lowest_mV; + } while (new_target > cur_target); - if (powered_by_linreg) { - bo_int = readl(&power_regs->hw_power_vdddctrl); - clrbits_le32(&power_regs->hw_power_vdddctrl, - POWER_CTRL_ENIRQ_VDDD_BO); + if (adjust_up && powered_by_linreg) { + writel(cfg->bo_irq, &power_regs->hw_power_ctrl_clr); + if (bo_int & cfg->bo_enirq) + setbits_le32(cfg->reg, cfg->bo_enirq); } - __mx28_power_set_vddx(target, brownout, 800, 1575, 25, vddd, VDDD, - powered_by_linreg); - - if (powered_by_linreg) { - writel(POWER_CTRL_VDDD_BO_IRQ, - &power_regs->hw_power_ctrl_clr); - if (bo_int & POWER_CTRL_ENIRQ_VDDD_BO) - setbits_le32(&power_regs->hw_power_vdddctrl, - POWER_CTRL_ENIRQ_VDDD_BO); - } + clrsetbits_le32(cfg->reg, cfg->bo_offset_mask, + new_brownout << cfg->bo_offset_offset); } - static inline void mx28_power_set_vddio(uint32_t target, uint32_t brownout) + static void mxs_setup_batt_detect(void) { - int powered_by_linreg = mx28_get_vddio_power_source_off(); - uint32_t bo_int = 0; - - if (powered_by_linreg) { - bo_int = readl(&power_regs->hw_power_vddioctrl); - clrbits_le32(&power_regs->hw_power_vddioctrl, - POWER_CTRL_ENIRQ_VDDIO_BO); - } - __mx28_power_set_vddx(target, brownout, 2800, 3600, 50, vddio, VDDIO, - powered_by_linreg); - if (powered_by_linreg) { - writel(POWER_CTRL_VDDIO_BO_IRQ, - &power_regs->hw_power_ctrl_clr); - if (bo_int & POWER_CTRL_ENIRQ_VDDIO_BO) - setbits_le32(&power_regs->hw_power_vddioctrl, - POWER_CTRL_ENIRQ_VDDIO_BO); - } + mxs_lradc_init(); + mxs_lradc_enable_batt_measurement(); + early_delay(10); } - static inline void mx28_power_set_vdda(uint32_t target, uint32_t brownout) + void mxs_power_init(void) { - int powered_by_linreg = mx28_get_vdda_power_source_off(); - uint32_t bo_int = 0; - struct mxs_power_regs *power_regs = - (struct mxs_power_regs *)MXS_POWER_BASE; - + mxs_power_clock2xtal(); + mxs_power_clear_auto_restart(); + mxs_power_set_linreg(); - mxs_power_setup_5v_detect(); - if (powered_by_linreg) { - bo_int = readl(&power_regs->hw_power_vddioctrl); - clrbits_le32(&power_regs->hw_power_vddioctrl, - POWER_CTRL_ENIRQ_VDDIO_BO); - } - __mx28_power_set_vddx(target, brownout, 1500, 2275, 25, vdda, VDDA, - powered_by_linreg); - if (powered_by_linreg) { - writel(POWER_CTRL_VDDIO_BO_IRQ, - &power_regs->hw_power_ctrl_clr); - if (bo_int & POWER_CTRL_ENIRQ_VDDIO_BO) - setbits_le32(&power_regs->hw_power_vddioctrl, - POWER_CTRL_ENIRQ_VDDIO_BO); - mxs_setup_batt_detect(); ++ if (!fixed_batt_supply) { ++ mxs_power_setup_5v_detect(); ++ mxs_setup_batt_detect(); + } - } - static inline void mx28_power_set_vddmem(uint32_t target, uint32_t brownout) - { - __mx28_power_set_vddx(target, brownout, 1100, 1750, 25, vddmem, VDDMEM, - 0); + mxs_power_configure_power_source(); + mxs_enable_output_rail_protection(); + - mxs_power_set_vddx(&mxs_vddio_cfg, 3300, 3150); - mxs_power_set_vddx(&mxs_vddd_cfg, 1500, 1000); - ++ mxs_power_set_vddx(&mxs_vddio_cfg, VDDIO_VAL, VDDIO_BO_VAL); ++ mxs_power_set_vddx(&mxs_vddd_cfg, VDDD_VAL, VDDD_BO_VAL); ++ mxs_power_set_vddx(&mxs_vdda_cfg, VDDA_VAL, VDDA_BO_VAL); ++#if VDDMEM_VAL > 0 ++ mxs_power_set_vddx(&mxs_vddmem_cfg, VDDMEM_VAL, VDDMEM_BO_VAL); + ++ setbits_le32(&power_regs->hw_power_vddmemctrl, ++ POWER_VDDMEMCTRL_ENABLE_LINREG); ++ early_delay(500); + clrbits_le32(&power_regs->hw_power_vddmemctrl, - POWER_VDDMEMCTRL_ENABLE_LINREG | + POWER_VDDMEMCTRL_ENABLE_ILIMIT); - } - - void mx28_setup_batt_detect(void) - { - mx28_lradc_init(); - mx28_lradc_enable_batt_measurement(); - early_delay(10); - } - - void mx28_power_init(void) - { - mx28_power_clock2xtal(); - mx28_power_clear_auto_restart(); - mx28_power_set_linreg(); - if (!fixed_batt_supply) - mx28_power_setup_5v_detect(); - - mx28_power_configure_power_source(); - mx28_enable_output_rail_protection(); - - mx28_power_set_vddio(VDDIO_VAL, VDDIO_BO_VAL); - - mx28_power_set_vddd(VDDD_VAL, VDDD_BO_VAL); - - mx28_power_set_vdda(VDDA_VAL, VDDA_BO_VAL); - - mx28_power_set_vddmem(VDDMEM_VAL, VDDMEM_BO_VAL); - ++#else ++ clrbits_le32(&power_regs->hw_power_vddmemctrl, ++ POWER_VDDMEMCTRL_ENABLE_LINREG); ++#endif writel(POWER_CTRL_VDDD_BO_IRQ | POWER_CTRL_VDDA_BO_IRQ | POWER_CTRL_VDDIO_BO_IRQ | POWER_CTRL_VDD5V_DROOP_IRQ | POWER_CTRL_VBUS_VALID_IRQ | POWER_CTRL_BATT_BO_IRQ | @@@ -1029,8 -910,11 +1028,8 @@@ } #ifdef CONFIG_SPL_MX28_PSWITCH_WAIT - void mx28_power_wait_pswitch(void) + void mxs_power_wait_pswitch(void) { - struct mxs_power_regs *power_regs = - (struct mxs_power_regs *)MXS_POWER_BASE; - while (!(readl(&power_regs->hw_power_sts) & POWER_STS_PSWITCH_MASK)) ; } diff --cc arch/arm/cpu/arm926ejs/mxs/timer.c index 116932cb56,373841180f..f2dfc8a6dd --- a/arch/arm/cpu/arm926ejs/mxs/timer.c +++ b/arch/arm/cpu/arm926ejs/mxs/timer.c @@@ -54,16 -42,22 +54,16 @@@ DECLARE_GLOBAL_DATA_PTR /* * This driver uses 1kHz clock source. */ --#define MX28_INCREMENTER_HZ 1000 ++#define MXS_INCREMENTER_HZ 1000 static inline unsigned long tick_to_time(unsigned long tick) { -- return tick / (MX28_INCREMENTER_HZ / CONFIG_SYS_HZ); ++ return tick / (MXS_INCREMENTER_HZ / CONFIG_SYS_HZ); } static inline unsigned long time_to_tick(unsigned long time) { -- return time * (MX28_INCREMENTER_HZ / CONFIG_SYS_HZ); -} - -/* Calculate how many ticks happen in "us" microseconds */ -static inline unsigned long us_to_tick(unsigned long us) -{ - return (us * MX28_INCREMENTER_HZ) / 1000000; ++ return time * (MXS_INCREMENTER_HZ / CONFIG_SYS_HZ); } int timer_init(void) @@@ -82,70 -76,34 +82,53 @@@ TIMROT_TIMCTRLn_SELECT_1KHZ_XTAL, &timrot_regs->hw_timrot_timctrl0); - /* Set fixed_count to maximal value */ +#ifndef DEBUG_TIMER_WRAP + /* Set fixed_count to maximum value */ writel(TIMER_LOAD_VAL, &timrot_regs->hw_timrot_fixed_count0); - +#else + /* Set fixed_count so that the counter will wrap after 20 seconds */ - writel(20 * MX28_INCREMENTER_HZ, ++ writel(20 * MXS_INCREMENTER_HZ, + &timrot_regs->hw_timrot_fixed_count0); - gd->lastinc = TIMER_LOAD_VAL - 20 * MX28_INCREMENTER_HZ; ++ gd->arch.lastinc = TIMER_LOAD_VAL - 20 * MXS_INCREMENTER_HZ; +#endif +#ifdef DEBUG_TIMER_WRAP + /* Make the usec counter roll over 30 seconds after startup */ - writel(-30000000, MX28_HW_DIGCTL_MICROSECONDS); ++ writel(-30000000, MXS_HW_DIGCTL_MICROSECONDS); +#endif + writel(TIMROT_TIMCTRLn_UPDATE, + &timrot_regs->hw_timrot_timctrl0_clr); +#ifdef DEBUG_TIMER_WRAP + /* Set fixed_count to maximal value for subsequent loads */ + writel(TIMER_LOAD_VAL, &timrot_regs->hw_timrot_fixed_count0); +#endif - gd->timer_rate_hz = MX28_INCREMENTER_HZ; - gd->tbl = TIMER_START; - gd->tbu = 0; ++ gd->arch.timer_rate_hz = MXS_INCREMENTER_HZ; ++ gd->arch.tbl = TIMER_START; ++ gd->arch.tbu = 0; return 0; } - /* We use the HW_DIGCTL_MICROSECONDS register for sub-millisecond timer. */ - #define MX28_HW_DIGCTL_MICROSECONDS 0x8001c0c0 - - void __udelay(unsigned long usec) - { - uint32_t start = readl(MX28_HW_DIGCTL_MICROSECONDS); - - while (readl(MX28_HW_DIGCTL_MICROSECONDS) - start <= usec) - /* use '<=' to guarantee a delay of _at least_ - * the given number of microseconds. - * No need for fancy rollover checks - * Two's complement arithmetic applied correctly - * does everything that's needed automagically! - */ - ; - } - +/* Note: This function works correctly for TIMER_LOAD_VAL == 0xffffffff! + * The rollover is handled automagically due to the properties of + * two's complement arithmetic. + * For any other value of TIMER_LOAD_VAL the calculations would have + * to be done modulus(TIMER_LOAD_VAL + 1). + */ unsigned long long get_ticks(void) { - struct mx28_timrot_regs *timrot_regs = - (struct mx28_timrot_regs *)MXS_TIMROT_BASE; + struct mxs_timrot_regs *timrot_regs = + (struct mxs_timrot_regs *)MXS_TIMROT_BASE; - - /* Current tick value */ - uint32_t now = readl(&timrot_regs->hw_timrot_running_count0); - - if (lastdec >= now) { - /* - * normal mode (non roll) - * move stamp forward with absolut diff ticks - */ - timestamp += (lastdec - now); - } else { - /* we have rollover of decrementer */ - timestamp += (TIMER_LOAD_VAL - now) + lastdec; - - } - lastdec = now; - - return timestamp; + /* The timer is counting down, so subtract the register value from + * the counter period length to get an incrementing timestamp + */ + unsigned long now = -readl(&timrot_regs->hw_timrot_running_count0); - ulong inc = now - gd->lastinc; ++ ulong inc = now - gd->arch.lastinc; + - gd->tbl += inc; - gd->lastinc = now; ++ gd->arch.tbl += inc; ++ gd->arch.lastinc = now; + /* Since the get_timer() function only uses a 32bit value + * it doesn't make sense to return a real 64 bit value here. + */ - return gd->tbl; ++ return gd->arch.tbl; } ulong get_timer_masked(void) @@@ -155,15 -113,44 +138,28 @@@ ulong get_timer(ulong base) { - return get_timer_masked() - base; + /* NOTE: time_to_tick(base) is required to correctly handle rollover! */ + return tick_to_time(get_ticks() - time_to_tick(base)); } - /* - * This function is derived from PowerPC code (timebase clock frequency). - * On ARM it returns the number of timer ticks per second. - */ + /* We use the HW_DIGCTL_MICROSECONDS register for sub-millisecond timer. */ -#define MX28_HW_DIGCTL_MICROSECONDS 0x8001c0c0 ++#define MXS_HW_DIGCTL_MICROSECONDS 0x8001c0c0 + + void __udelay(unsigned long usec) + { - uint32_t old, new, incr; - uint32_t counter = 0; - - old = readl(MX28_HW_DIGCTL_MICROSECONDS); - - while (counter < usec) { - new = readl(MX28_HW_DIGCTL_MICROSECONDS); - - /* Check if the timer wrapped. */ - if (new < old) { - incr = 0xffffffff - old; - incr += new; - } else { - incr = new - old; - } - - /* - * Check if we are close to the maximum time and the counter - * would wrap if incremented. If that's the case, break out - * from the loop as the requested delay time passed. ++ uint32_t start = readl(MXS_HW_DIGCTL_MICROSECONDS); ++ ++ while (readl(MXS_HW_DIGCTL_MICROSECONDS) - start <= usec) ++ /* use '<=' to guarantee a delay of _at least_ ++ * the given number of microseconds. ++ * No need for fancy rollover checks ++ * Two's complement arithmetic applied correctly ++ * does everything that's needed automagically! + */ - if (counter + incr < counter) - break; - - counter += incr; - old = new; - } ++ ; + } + ulong get_tbclk(void) { - return gd->timer_rate_hz; - return MX28_INCREMENTER_HZ; ++ return gd->arch.timer_rate_hz; } diff --cc arch/arm/cpu/arm926ejs/mxs/u-boot-imx28.bd index 0000000000,c60615a456..d336393205 mode 000000,100644..100644 --- a/arch/arm/cpu/arm926ejs/mxs/u-boot-imx28.bd +++ b/arch/arm/cpu/arm926ejs/mxs/u-boot-imx28.bd @@@ -1,0 -1,14 +1,14 @@@ + sources { - u_boot_spl="spl/u-boot-spl.bin"; - u_boot="u-boot.bin"; ++ u_boot_spl="spl/u-boot-spl"; ++ u_boot="u-boot"; + } + + section (0) { - load u_boot_spl > 0x0000; - load ivt (entry = 0x0014) > 0x8000; ++ load u_boot_spl; ++ load ivt (entry = u_boot_spl:reset) > 0x8000; + hab call 0x8000; + - load u_boot > 0x40000100; - load ivt (entry = 0x40000100) > 0x8000; ++ load u_boot; ++ load ivt (entry = u_boot:reset) > 0x8000; + hab call 0x8000; + } diff --cc arch/arm/cpu/armv7/am33xx/Makefile index 0ad202d7af,70c443edbb..a7a468edb1 --- a/arch/arm/cpu/armv7/am33xx/Makefile +++ b/arch/arm/cpu/armv7/am33xx/Makefile @@@ -18,12 -18,12 +18,13 @@@ LIB = $(obj)lib$(SOC). COBJS += clock.o COBJS += sys_info.o - COBJS-$(CONFIG_SYS_SDRAM_DDR3) += ddr3.o - COBJS-$(CONFIG_SYS_SDRAM_DDR2) += ddr2.o COBJS += mem.o + COBJS += ddr.o COBJS += emif4.o COBJS += board.o + COBJS += mux.o + COBJS-$(CONFIG_NAND_OMAP_GPMC) += elm.o +COBJS-$(CONFIG_NAND_AM33XX) += elm.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS) $(COBJS-y) $(SOBJS)) diff --cc arch/arm/cpu/armv7/am33xx/board.c index 46134899e4,ab313265d0..e711f0bf4a --- a/arch/arm/cpu/armv7/am33xx/board.c +++ b/arch/arm/cpu/armv7/am33xx/board.c @@@ -22,169 -24,128 +24,174 @@@ #include #include #include + #include + #include #include - #include + #include #include - #include + #include + #include + #include + #include -#include ++//#include + #include + #include + #include + #include + #include DECLARE_GLOBAL_DATA_PTR; - /* UART Defines */ - #ifdef CONFIG_SPL_BUILD - #define UART_RESET (0x1 << 1) - #define UART_CLK_RUNNING_MASK 0x1 - #define UART_SMART_IDLE_EN (0x1 << 0x3) - #endif + static const struct gpio_bank gpio_bank_am33xx[4] = { + { (void *)AM33XX_GPIO0_BASE, METHOD_GPIO_24XX }, + { (void *)AM33XX_GPIO1_BASE, METHOD_GPIO_24XX }, + { (void *)AM33XX_GPIO2_BASE, METHOD_GPIO_24XX }, + { (void *)AM33XX_GPIO3_BASE, METHOD_GPIO_24XX }, + }; - void reset_cpu(unsigned long ignored) - { - /* clear RESET flags */ - writel(~0, PRM_RSTST); - writel(PRM_RSTCTRL_RESET, PRM_RSTCTRL); - } + const struct gpio_bank *const omap_gpio_bank = gpio_bank_am33xx; +#ifdef CONFIG_HW_WATCHDOG +void hw_watchdog_reset(void) +{ + struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE; + static int trg __attribute__((section(".data"))); + + switch (trg) { + case 0: + case 1: + if (readl(&wdtimer->wdtwwps) & (1 << 4)) + return; + writel(trg ? 0x5555 : 0xaaaa, &wdtimer->wdtwspr); + break; + case 2: + if (readl(&wdtimer->wdtwwps) & (1 << 2)) + return; + /* 10 sec timeout */ + writel(-32768 * 10, &wdtimer->wdtwldr); + + if (readl(&wdtimer->wdtwwps) & (1 << 0)) + return; + /* prescaler = 1 */ + writel(0, &wdtimer->wdtwclr); + break; + + case 3: + case 4: + /* enable watchdog */ + if (readl(&wdtimer->wdtwwps) & (1 << 4)) + return; + writel((trg & 1) ? 0xBBBB : 0x4444, &wdtimer->wdtwspr); + break; + + default: + /* retrigger watchdog */ + if (readl(&wdtimer->wdtwwps) & (1 << 3)) + return; + + writel(trg, &wdtimer->wdtwtgr); + trg ^= 0x2; + return; + } + trg++; +} +#endif + - /* - * early system init of muxing and clocks. - */ - void s_init(void) + #if defined(CONFIG_OMAP_HSMMC) && !defined(CONFIG_SPL_BUILD) + int cpu_mmc_init(bd_t *bis) { - #ifdef CONFIG_SPL_BUILD - #ifndef CONFIG_HW_WATCHDOG - struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE; - - /* WDT1 is already running when the bootloader gets control - * Disable it to avoid "random" resets - */ - writel(0xAAAA, &wdtimer->wdtwspr); - while (readl(&wdtimer->wdtwwps) != 0x0) - ; - writel(0x5555, &wdtimer->wdtwspr); - while (readl(&wdtimer->wdtwwps) != 0x0) - ; - #endif - /* Setup the PLLs and the clocks for the peripherals */ - pll_init(); - - /* UART softreset */ - u32 regVal; - struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE; + int ret; - enable_uart0_pin_mux(); - - regVal = readl(&uart_base->uartsyscfg); - regVal |= UART_RESET; - writel(regVal, &uart_base->uartsyscfg); - while ((readl(&uart_base->uartsyssts) & - UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK) - ; - - /* Disable smart idle */ - regVal = readl(&uart_base->uartsyscfg); - regVal |= UART_SMART_IDLE_EN; - writel(regVal, &uart_base->uartsyscfg); + ret = omap_mmc_init(0, 0, 0); + if (ret) + return ret; - /* Initialize the Timer */ - timer_init(); + return omap_mmc_init(1, 0, 0); + } + #endif - preloader_console_init(); + void setup_clocks_for_console(void) + { + /* Not yet implemented */ + return; + } - config_ddr(); + /* AM33XX has two MUSB controllers which can be host or gadget */ + #if (defined(CONFIG_MUSB_GADGET) || defined(CONFIG_MUSB_HOST)) && \ + (defined(CONFIG_AM335X_USB0) || defined(CONFIG_AM335X_USB1)) + static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; - /* Enable MMC0 */ - enable_mmc0_pin_mux(); - #endif - } + /* USB 2.0 PHY Control */ + #define CM_PHY_PWRDN (1 << 0) + #define CM_PHY_OTG_PWRDN (1 << 1) + #define OTGVDET_EN (1 << 19) + #define OTGSESSENDEN (1 << 20) - #if defined(CONFIG_OMAP_HSMMC) && !defined(CONFIG_SPL_BUILD) - int board_mmc_init(bd_t *bis) + static void am33xx_usb_set_phy_power(u8 on, u32 *reg_addr) { - int ret = 0; - #ifdef CONFIG_OMAP_MMC_DEV_0 - ret = omap_mmc_init(0, 0, 0); - if (ret) - printf("Error %d while initializing MMC dev 0\n", ret); - #endif - #ifdef CONFIG_OMAP_MMC_DEV_1 - ret = omap_mmc_init(1, 0, 0); - if (ret) - printf("Error %d while initializing MMC dev 1\n", ret); - #endif - return ret; + if (on) { + clrsetbits_le32(reg_addr, CM_PHY_PWRDN | CM_PHY_OTG_PWRDN, + OTGVDET_EN | OTGSESSENDEN); + } else { + clrsetbits_le32(reg_addr, 0, CM_PHY_PWRDN | CM_PHY_OTG_PWRDN); + } } - #endif - #ifndef CONFIG_SYS_DCACHE_OFF - void enable_caches(void) + static struct musb_hdrc_config musb_config = { + .multipoint = 1, + .dyn_fifo = 1, + .num_eps = 16, + .ram_bits = 12, + }; + + #ifdef CONFIG_AM335X_USB0 + static void am33xx_otg0_set_phy_power(u8 on) { - /* Enable D-cache. I-cache is already enabled in start.S */ - dcache_enable(); + am33xx_usb_set_phy_power(on, &cdev->usb_ctrl0); } + + struct omap_musb_board_data otg0_board_data = { + .set_phy_power = am33xx_otg0_set_phy_power, + }; + + static struct musb_hdrc_platform_data otg0_plat = { + .mode = CONFIG_AM335X_USB0_MODE, + .config = &musb_config, + .power = 50, + .platform_ops = &musb_dsps_ops, + .board_data = &otg0_board_data, + }; #endif - static u32 cortex_rev(void) + #ifdef CONFIG_AM335X_USB1 + static void am33xx_otg1_set_phy_power(u8 on) { - - unsigned int rev; - - /* Read Main ID Register (MIDR) */ - asm ("mrc p15, 0, %0, c0, c0, 0" : "=r" (rev)); - - return rev; + am33xx_usb_set_phy_power(on, &cdev->usb_ctrl1); } - void omap_rev_string(void) - { - u32 omap_rev = cortex_rev(); - u32 omap_variant = (omap_rev & 0xFFFF0000) >> 16; - u32 major_rev = (omap_rev & 0x00000F00) >> 8; - u32 minor_rev = (omap_rev & 0x000000F0) >> 4; + struct omap_musb_board_data otg1_board_data = { + .set_phy_power = am33xx_otg1_set_phy_power, + }; + + static struct musb_hdrc_platform_data otg1_plat = { + .mode = CONFIG_AM335X_USB1_MODE, + .config = &musb_config, + .power = 50, + .platform_ops = &musb_dsps_ops, + .board_data = &otg1_board_data, + }; + #endif + #endif - printf("OMAP%x ES%x.%x\n", omap_variant, major_rev, - minor_rev); + int arch_misc_init(void) + { + #ifdef CONFIG_AM335X_USB0 + musb_register(&otg0_plat, &otg0_board_data, + (void *)AM335X_USB0_OTG_BASE); + #endif + #ifdef CONFIG_AM335X_USB1 + musb_register(&otg1_plat, &otg1_board_data, + (void *)AM335X_USB1_OTG_BASE); + #endif + return 0; } diff --cc arch/arm/cpu/armv7/am33xx/clock.c index 26882c5ec6,d7d98d1111..97ebc72c51 --- a/arch/arm/cpu/armv7/am33xx/clock.c +++ b/arch/arm/cpu/armv7/am33xx/clock.c @@@ -35,43 -36,47 +36,45 @@@ #define CLK_DIV_MASK 0x1f #define CLK_DIV2_MASK 0x7f #define CLK_SEL_SHIFT 0x8 +#define CLK_MODE_MASK 0x7 #define CLK_MODE_SEL 0x7 -#define CLK_MODE_MASK 0xfffffff8 -#define CLK_DIV_SEL 0xFFFFFFE0 -#define CPGMAC0_IDLE 0x30000 -#define DPLL_CLKDCOLDO_GATE_CTRL 0x300 ++#define DPLL_CLKDCOLDO_GATE_CTRL 0x300 + const struct cm_perpll *cmper = (struct cm_perpll *)CM_PER; const struct cm_wkuppll *cmwkup = (struct cm_wkuppll *)CM_WKUP; const struct cm_dpll *cmdpll = (struct cm_dpll *)CM_DPLL; + const struct cm_rtc *cmrtc = (struct cm_rtc *)CM_RTC; +#ifdef CONFIG_SPL_BUILD +#define enable_clk(reg, val) __enable_clk(#reg, ®, val) + +static void __enable_clk(const char *name, const void *reg, u32 mask) +{ + unsigned long timeout = 10000000; + + writel(mask, reg); + while (readl(reg) != mask) + /* poor man's timeout, since timers not initialized */ + if (timeout-- == 0) + /* no error message, since console not yet available */ + break; +} + static void enable_interface_clocks(void) { /* Enable all the Interconnect Modules */ - writel(PRCM_MOD_EN, &cmper->l3clkctrl); - while (readl(&cmper->l3clkctrl) != PRCM_MOD_EN) - ; - - writel(PRCM_MOD_EN, &cmper->l4lsclkctrl); - while (readl(&cmper->l4lsclkctrl) != PRCM_MOD_EN) - ; - - writel(PRCM_MOD_EN, &cmper->l4fwclkctrl); - while (readl(&cmper->l4fwclkctrl) != PRCM_MOD_EN) - ; - - writel(PRCM_MOD_EN, &cmwkup->wkl4wkclkctrl); - while (readl(&cmwkup->wkl4wkclkctrl) != PRCM_MOD_EN) - ; - - writel(PRCM_MOD_EN, &cmper->l3instrclkctrl); - while (readl(&cmper->l3instrclkctrl) != PRCM_MOD_EN) - ; - - writel(PRCM_MOD_EN, &cmper->l4hsclkctrl); - while (readl(&cmper->l4hsclkctrl) != PRCM_MOD_EN) - ; - - writel(PRCM_MOD_EN, &cmwkup->wkgpio0clkctrl); - while (readl(&cmwkup->wkgpio0clkctrl) != PRCM_MOD_EN) - ; + enable_clk(cmper->l3clkctrl, PRCM_MOD_EN); + enable_clk(cmper->l4lsclkctrl, PRCM_MOD_EN); + enable_clk(cmper->l4fwclkctrl, PRCM_MOD_EN); + enable_clk(cmwkup->wkl4wkclkctrl, PRCM_MOD_EN); + enable_clk(cmper->l3instrclkctrl, PRCM_MOD_EN); + enable_clk(cmper->l4hsclkctrl, PRCM_MOD_EN); +#ifdef CONFIG_HW_WATCHDOG + enable_clk(cmwkup->wdtimer1ctrl, PRCM_MOD_EN); +#endif + /* GPIO0 */ - enable_clk(cmwkup->gpio0clkctrl, PRCM_MOD_EN); ++ enable_clk(cmwkup->wkgpio0clkctrl, PRCM_MOD_EN); } /* @@@ -100,52 -111,105 +103,64 @@@ static void enable_per_clocks(void /* Select the Master osc 24 MHZ as Timer2 clock source */ writel(0x1, &cmdpll->clktimer2clk); +#ifdef CONFIG_SYS_NS16550_COM1 /* UART0 */ - writel(PRCM_MOD_EN, &cmwkup->wkup_uart0ctrl); - while (readl(&cmwkup->wkup_uart0ctrl) != PRCM_MOD_EN) - ; - - /* UART1 */ -#ifdef CONFIG_SERIAL2 - writel(PRCM_MOD_EN, &cmper->uart1clkctrl); - while (readl(&cmper->uart1clkctrl) != PRCM_MOD_EN) - ; -#endif /* CONFIG_SERIAL2 */ - - /* UART2 */ -#ifdef CONFIG_SERIAL3 - writel(PRCM_MOD_EN, &cmper->uart2clkctrl); - while (readl(&cmper->uart2clkctrl) != PRCM_MOD_EN) - ; -#endif /* CONFIG_SERIAL3 */ - - /* UART3 */ -#ifdef CONFIG_SERIAL4 - writel(PRCM_MOD_EN, &cmper->uart3clkctrl); - while (readl(&cmper->uart3clkctrl) != PRCM_MOD_EN) - ; -#endif /* CONFIG_SERIAL4 */ - - /* UART4 */ -#ifdef CONFIG_SERIAL5 - writel(PRCM_MOD_EN, &cmper->uart4clkctrl); - while (readl(&cmper->uart4clkctrl) != PRCM_MOD_EN) - ; -#endif /* CONFIG_SERIAL5 */ - - /* UART5 */ -#ifdef CONFIG_SERIAL6 - writel(PRCM_MOD_EN, &cmper->uart5clkctrl); - while (readl(&cmper->uart5clkctrl) != PRCM_MOD_EN) - ; -#endif /* CONFIG_SERIAL6 */ - + enable_clk(cmwkup->wkup_uart0ctrl, PRCM_MOD_EN); +#endif +#ifdef CONFIG_SYS_NS16550_COM2 + enable_clk(cmper->uart1clkctrl, PRCM_MOD_EN); +#endif +#ifdef CONFIG_SYS_NS16550_COM3 + enable_clk(cmper->uart2clkctrl, PRCM_MOD_EN); +#endif +#ifdef CONFIG_SYS_NS16550_COM4 + enable_clk(cmper->uart3clkctrl, PRCM_MOD_EN); +#endif +#ifdef CONFIG_SYS_NS16550_COM5 + enable_clk(cmper->uart4clkctrl, PRCM_MOD_EN); +#endif +#ifdef CONFIG_SYS_NS16550_COM6 + enable_clk(cmper->uart5clkctrl, PRCM_MOD_EN); +#endif /* GPMC */ - writel(PRCM_MOD_EN, &cmper->gpmcclkctrl); - while (readl(&cmper->gpmcclkctrl) != PRCM_MOD_EN) - ; + enable_clk(cmper->gpmcclkctrl, PRCM_MOD_EN); /* ELM */ - writel(PRCM_MOD_EN, &cmper->elmclkctrl); - while (readl(&cmper->elmclkctrl) != PRCM_MOD_EN) - ; + enable_clk(cmper->elmclkctrl, PRCM_MOD_EN); - /* MMC0*/ - writel(PRCM_MOD_EN, &cmper->mmc0clkctrl); - while (readl(&cmper->mmc0clkctrl) != PRCM_MOD_EN) - ; + /* Ethernet */ - enable_clk(cmper->cpswclkctrl, PRCM_MOD_EN); ++ enable_clk(cmper->cpswclkstctrl, PRCM_MOD_EN); + enable_clk(cmper->cpgmac0clkctrl, PRCM_MOD_EN); + + /* MMC */ +#ifndef CONFIG_OMAP_MMC_DEV_0 + enable_clk(cmper->mmc0clkctrl, PRCM_MOD_EN); +#endif +#ifdef CONFIG_OMAP_MMC_DEV_1 + enable_clk(cmper->mmc1clkctrl, PRCM_MOD_EN); +#endif + /* LCD */ - enable_clk(cmper->lcdcclkctrl, PRCM_MOD_EN); ++ enable_clk(cmper->lcdclkctrl, PRCM_MOD_EN); /* i2c0 */ - writel(PRCM_MOD_EN, &cmwkup->wkup_i2c0ctrl); - while (readl(&cmwkup->wkup_i2c0ctrl) != PRCM_MOD_EN) - ; + enable_clk(cmwkup->wkup_i2c0ctrl, PRCM_MOD_EN); - /* gpio1 module */ - writel(PRCM_MOD_EN, &cmper->gpio1clkctrl); - while (readl(&cmper->gpio1clkctrl) != PRCM_MOD_EN) - ; - - /* gpio2 module */ - writel(PRCM_MOD_EN, &cmper->gpio2clkctrl); - while (readl(&cmper->gpio2clkctrl) != PRCM_MOD_EN) - ; - - /* gpio3 module */ - writel(PRCM_MOD_EN, &cmper->gpio3clkctrl); - while (readl(&cmper->gpio3clkctrl) != PRCM_MOD_EN) - ; + /* GPIO1-3 */ + enable_clk(cmper->gpio1clkctrl, PRCM_MOD_EN); + enable_clk(cmper->gpio2clkctrl, PRCM_MOD_EN); + enable_clk(cmper->gpio3clkctrl, PRCM_MOD_EN); + + /* i2c1 */ - writel(PRCM_MOD_EN, &cmper->i2c1clkctrl); - while (readl(&cmper->i2c1clkctrl) != PRCM_MOD_EN) - ; - - /* Ethernet */ - writel(PRCM_MOD_EN, &cmper->cpgmac0clkctrl); - while ((readl(&cmper->cpgmac0clkctrl) & CPGMAC0_IDLE) != PRCM_FUNCTL) - ; ++ enable_clk(cmper->i2c1clkctrl, PRCM_MOD_EN); + + /* spi0 */ - writel(PRCM_MOD_EN, &cmper->spi0clkctrl); - while (readl(&cmper->spi0clkctrl) != PRCM_MOD_EN) - ; ++ enable_clk(cmper->spi0clkctrl, PRCM_MOD_EN); + - /* RTC */ - writel(PRCM_MOD_EN, &cmrtc->rtcclkctrl); - while (readl(&cmrtc->rtcclkctrl) != PRCM_MOD_EN) - ; ++ /* rtc */ ++ enable_clk(cmrtc->rtcclkctrl, PRCM_MOD_EN); + - /* MUSB */ - writel(PRCM_MOD_EN, &cmper->usb0clkctrl); - while (readl(&cmper->usb0clkctrl) != PRCM_MOD_EN) - ; ++ /* usb0 */ ++ enable_clk(cmper->usb0clkctrl, PRCM_MOD_EN); } static void mpu_pll_config(void) @@@ -245,39 -306,11 +260,41 @@@ static void per_pll_config(void while (readl(&cmwkup->idlestdpllper) != ST_DPLL_CLK) ; + + writel(DPLL_CLKDCOLDO_GATE_CTRL, &cmwkup->clkdcoldodpllper); } +static void disp_pll_config(void) +{ + u32 clkmode, clksel, div_m2; + + clkmode = readl(&cmwkup->clkmoddplldisp); + clksel = readl(&cmwkup->clkseldplldisp); + div_m2 = readl(&cmwkup->divm2dplldisp); + + /* Set the PLL to bypass Mode */ + writel(PLL_BYPASS_MODE, &cmwkup->clkmoddplldisp); + + while (!(readl(&cmwkup->idlestdplldisp) & ST_MN_BYPASS)) + ; + + clksel &= ~CLK_SEL_MASK; + clksel |= (DISPPLL_M << CLK_SEL_SHIFT) | DISPPLL_N; + writel(clksel, &cmwkup->clkseldplldisp); + + div_m2 &= ~CLK_DIV2_MASK; + div_m2 |= DISPPLL_M2; + writel(div_m2, &cmwkup->divm2dplldisp); + + clkmode &= ~CLK_MODE_MASK; + clkmode |= CLK_MODE_SEL; + writel(clkmode, &cmwkup->clkmoddplldisp); + + while (!(readl(&cmwkup->idlestdplldisp) & ST_DPLL_CLK)) + ; +} + - static void ddr_pll_config(void) + void ddr_pll_config(unsigned int ddrpll_m) { u32 clkmode, clksel, div_m2; @@@ -291,19 -323,19 +308,19 @@@ writel(clkmode, &cmwkup->clkmoddpllddr); /* Wait till bypass mode is enabled */ - while ((readl(&cmwkup->idlestdpllddr) & ST_MN_BYPASS) - != ST_MN_BYPASS) + while (!(readl(&cmwkup->idlestdpllddr) & ST_MN_BYPASS)) ; - clksel = clksel & (~CLK_SEL_MASK); - clksel = clksel | ((ddrpll_m << CLK_SEL_SHIFT) | DDRPLL_N); + clksel &= ~CLK_SEL_MASK; - clksel |= (DDRPLL_M << CLK_SEL_SHIFT) | DDRPLL_N; ++ clksel |= (ddrpll_m << CLK_SEL_SHIFT) | DDRPLL_N; writel(clksel, &cmwkup->clkseldpllddr); - div_m2 = div_m2 & CLK_DIV_SEL; - div_m2 = div_m2 | DDRPLL_M2; + div_m2 &= ~CLK_DIV_MASK; + div_m2 |= DDRPLL_M2; writel(div_m2, &cmwkup->divm2dpllddr); - clkmode = (clkmode & CLK_MODE_MASK) | CLK_MODE_SEL; + clkmode &= ~CLK_MODE_MASK; + clkmode |= CLK_MODE_SEL; writel(clkmode, &cmwkup->clkmoddpllddr); /* Wait till dpll is locked */ @@@ -335,8 -362,6 +347,7 @@@ void pll_init( mpu_pll_config(); core_pll_config(); per_pll_config(); - ddr_pll_config(); + disp_pll_config(); /* Enable the required interconnect clocks */ enable_interface_clocks(); diff --cc arch/arm/cpu/armv7/am33xx/sys_info.c index 5eb7de7452,507b6180e6..5a032854ec --- a/arch/arm/cpu/armv7/am33xx/sys_info.c +++ b/arch/arm/cpu/armv7/am33xx/sys_info.c @@@ -85,24 -85,7 +85,24 @@@ u32 get_sysboot_value(void return mode; } + #ifdef CONFIG_DISPLAY_CPUINFO +#define SYSBOOT_FREQ_SHIFT 22 +#define SYSBOOT_FREQ_MASK (3 << SYSBOOT_FREQ_SHIFT) + +static unsigned long bootfreqs[] = { + 19200000, + 24000000, + 25000000, + 26000000, +}; + - u32 get_sysboot_freq(void) ++static u32 get_sysboot_freq(void) +{ + int mode; + mode = readl(&cstat->statusreg) & SYSBOOT_FREQ_MASK; + return bootfreqs[mode >> SYSBOOT_FREQ_SHIFT]; +} + - #ifdef CONFIG_DISPLAY_CPUINFO /** * Print CPU information */ diff --cc arch/arm/cpu/armv7/mx5/clock.c index c4c8fbeb6a,76c2c529a8..bb51b8278c --- a/arch/arm/cpu/armv7/mx5/clock.c +++ b/arch/arm/cpu/armv7/mx5/clock.c @@@ -84,64 -89,76 +89,133 @@@ struct pll_param struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE; - void set_usboh3_clk(void) ++int clk_enable(struct clk *clk) +{ - unsigned int reg; ++ int ret = 0; ++ ++ if (!clk) ++ return 0; ++ if (clk->usecount++ == 0) { ++ ret = clk->enable(clk); ++ if (ret) ++ clk->usecount--; ++ } ++ return ret; ++} + - reg = readl(&mxc_ccm->cscmr1) & - ~MXC_CCM_CSCMR1_USBOH3_CLK_SEL_MASK; - reg |= 1 << MXC_CCM_CSCMR1_USBOH3_CLK_SEL_OFFSET; - writel(reg, &mxc_ccm->cscmr1); ++void clk_disable(struct clk *clk) ++{ ++ if (!clk) ++ return; + - reg = readl(&mxc_ccm->cscdr1); - reg &= ~MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK; - reg &= ~MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK; - reg |= 4 << MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET; - reg |= 1 << MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET; ++ if (!(--clk->usecount)) { ++ if (clk->disable) ++ clk->disable(clk); ++ } ++ if (clk->usecount < 0) { ++ printf("%s: clk %p underflow\n", __func__, clk); ++ hang(); ++ } ++} + - writel(reg, &mxc_ccm->cscdr1); + void set_usboh3_clk(void) + { + clrsetbits_le32(&mxc_ccm->cscmr1, + MXC_CCM_CSCMR1_USBOH3_CLK_SEL_MASK, + MXC_CCM_CSCMR1_USBOH3_CLK_SEL(1)); + clrsetbits_le32(&mxc_ccm->cscdr1, + MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK | + MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK, + MXC_CCM_CSCDR1_USBOH3_CLK_PRED(4) | + MXC_CCM_CSCDR1_USBOH3_CLK_PODF(1)); } void enable_usboh3_clk(unsigned char enable) { - unsigned int reg; + unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON : MXC_CCM_CCGR_CG_OFF; - reg = readl(&mxc_ccm->CCGR2); - if (enable) - reg |= 1 << MXC_CCM_CCGR2_CG14_OFFSET; - else - reg &= ~(1 << MXC_CCM_CCGR2_CG14_OFFSET); - writel(reg, &mxc_ccm->CCGR2); + clrsetbits_le32(&mxc_ccm->CCGR2, + MXC_CCM_CCGR2_USBOH3_60M(MXC_CCM_CCGR_CG_MASK), + MXC_CCM_CCGR2_USBOH3_60M(cg)); } - void set_usb_phy1_clk(void) ++void ipu_clk_enable(void) +{ - unsigned int reg; ++ /* IPU root clock derived from AXI B */ ++ clrsetbits_le32(&mxc_ccm->cbcmr, MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_MASK, ++ MXC_CCM_CBCMR_IPU_HSP_CLK_SEL(1)); + - reg = readl(&mxc_ccm->cscmr1); - reg &= ~MXC_CCM_CSCMR1_USB_PHY_CLK_SEL; - writel(reg, &mxc_ccm->cscmr1); ++ setbits_le32(&mxc_ccm->CCGR5, ++ MXC_CCM_CCGR5_IPU(MXC_CCM_CCGR_CG_MASK)); ++ ++ /* Handshake with IPU when certain clock rates are changed. */ ++ clrbits_le32(&mxc_ccm->ccdr, MXC_CCM_CCDR_IPU_HS_MASK); ++ ++ /* Handshake with IPU when LPM is entered as its enabled. */ ++ clrbits_le32(&mxc_ccm->clpcr, MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS); +} + - void enable_usb_phy1_clk(unsigned char enable) ++void ipu_clk_disable(void) ++{ ++ clrbits_le32(&mxc_ccm->CCGR5, ++ MXC_CCM_CCGR5_IPU(MXC_CCM_CCGR_CG_MASK)); ++ ++ /* Handshake with IPU when certain clock rates are changed. */ ++ setbits_le32(&mxc_ccm->ccdr, MXC_CCM_CCDR_IPU_HS_MASK); ++ ++ /* Handshake with IPU when LPM is entered as its enabled. */ ++ setbits_le32(&mxc_ccm->clpcr, MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS); ++} ++ + #ifdef CONFIG_I2C_MXC + /* i2c_num can be from 0, to 1 for i.MX51 and 2 for i.MX53 */ + int enable_i2c_clk(unsigned char enable, unsigned i2c_num) { - unsigned int reg; + u32 mask; - reg = readl(&mxc_ccm->CCGR4); + #if defined(CONFIG_MX51) + if (i2c_num > 1) + #elif defined(CONFIG_MX53) + if (i2c_num > 2) + #endif + return -EINVAL; + mask = MXC_CCM_CCGR_CG_MASK << + (MXC_CCM_CCGR1_I2C1_OFFSET + (i2c_num << 1)); if (enable) - reg |= 1 << MXC_CCM_CCGR4_CG5_OFFSET; + setbits_le32(&mxc_ccm->CCGR1, mask); else - reg &= ~(1 << MXC_CCM_CCGR4_CG5_OFFSET); - writel(reg, &mxc_ccm->CCGR4); + clrbits_le32(&mxc_ccm->CCGR1, mask); + return 0; + } + #endif + + void set_usb_phy_clk(void) + { + clrbits_le32(&mxc_ccm->cscmr1, MXC_CCM_CSCMR1_USB_PHY_CLK_SEL); } - void set_usb_phy2_clk(void) + #if defined(CONFIG_MX51) + void enable_usb_phy1_clk(unsigned char enable) { - unsigned int reg; + unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON : MXC_CCM_CCGR_CG_OFF; - reg = readl(&mxc_ccm->cscmr1); - reg &= ~MXC_CCM_CSCMR1_USB_PHY_CLK_SEL; - writel(reg, &mxc_ccm->cscmr1); + clrsetbits_le32(&mxc_ccm->CCGR2, + MXC_CCM_CCGR2_USB_PHY(MXC_CCM_CCGR_CG_MASK), + MXC_CCM_CCGR2_USB_PHY(cg)); + } + + void enable_usb_phy2_clk(unsigned char enable) + { + /* i.MX51 has a single USB PHY clock, so do nothing here. */ + } + #elif defined(CONFIG_MX53) + void enable_usb_phy1_clk(unsigned char enable) + { + unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON : MXC_CCM_CCGR_CG_OFF; + + clrsetbits_le32(&mxc_ccm->CCGR4, + MXC_CCM_CCGR4_USB_PHY1(MXC_CCM_CCGR_CG_MASK), + MXC_CCM_CCGR4_USB_PHY1(cg)); } void enable_usb_phy2_clk(unsigned char enable) @@@ -633,17 -695,22 +747,19 @@@ static int config_pll_clk(enum pll_cloc pll_param->mfi, pll_param->mfn, pll_param->mfd); /* Switch back */ - writel(ccsr & ~MXC_CCM_CCSR_PLL3_SW_CLK_SEL, - &mxc_ccm->ccsr); + __raw_writel(ccsr & ~0x1, &mxc_ccm->ccsr); break; + #ifdef CONFIG_MX53 case PLL4_CLOCK: /* Switch to pll4 bypass clock */ - writel(ccsr | MXC_CCM_CCSR_PLL4_SW_CLK_SEL, - &mxc_ccm->ccsr); + __raw_writel(ccsr | 0x20, &mxc_ccm->ccsr); CHANGE_PLL_SETTINGS(pll, pll_param->pd, pll_param->mfi, pll_param->mfn, pll_param->mfd); /* Switch back */ - writel(ccsr & ~MXC_CCM_CCSR_PLL4_SW_CLK_SEL, - &mxc_ccm->ccsr); + __raw_writel(ccsr & ~0x20, &mxc_ccm->ccsr); break; + #endif default: return -EINVAL; } diff --cc arch/arm/cpu/armv7/mx5/lowlevel_init.S index f3a15f64b8,6d9396a976..8b95d77630 --- a/arch/arm/cpu/armv7/mx5/lowlevel_init.S +++ b/arch/arm/cpu/armv7/mx5/lowlevel_init.S @@@ -209,16 -206,9 +206,15 @@@ setup_pll_func setup_pll PLL1_BASE_ADDR, 864 setup_pll_errata PLL1_BASE_ADDR, W_DP_MFN_800_DIT #else +#if !defined(CONFIG_SYS_CPU_CLK) || CONFIG_SYS_CPU_CLK == 800 setup_pll PLL1_BASE_ADDR, 800 +#elif CONFIG_SYS_CPU_CLK == 600 + setup_pll PLL1_BASE_ADDR, 600 +#else +#error Unsupported CONFIG_SYS_CPU_CLK value +#endif #endif - #if defined(CONFIG_MX51) setup_pll PLL3_BASE_ADDR, 665 /* Switch peripheral to PLL 3 */ @@@ -230,52 -220,12 +226,11 @@@ setup_pll PLL2_BASE_ADDR, 665 /* Switch peripheral to PLL2 */ - ldr r0, =CCM_BASE_ADDR ldr r1, =0x19239145 str r1, [r0, #CLKCTL_CBCDR] - ldr r1, =0x000020C0 - orr r1,r1,#CONFIG_SYS_DDR_CLKSEL - str r1, [r0, #CLKCTL_CBCMR] - #elif defined(CONFIG_TX53) - setup_pll PLL3_BASE_ADDR, 400 - - /* Switch peripheral to PLL 3 */ - ldr r1, [r0, #CLKCTL_CBCMR] - bic r1, #(0x3 << 12) - orr r1, r1, #(1 << 12) + ldr r1, =0x000020C0 | CONFIG_SYS_DDR_CLKSEL str r1, [r0, #CLKCTL_CBCMR] - ldr r1, [r0, #CLKCTL_CBCDR] - orr r1, r1, #(1 << 25) - str r1, [r0, #CLKCTL_CBCDR] - 1: - /* make sure change is effective */ - ldr r1, [r0, #CLKCTL_CDHIPR] - tst r1, #0x7f - bne 1b - #if CONFIG_SYS_SDRAM_CLK == 400 - setup_pll PLL2_BASE_ADDR, 400 - #elif CONFIG_SYS_SDRAM_CLK == 333 - setup_pll PLL2_BASE_ADDR, 333 - #else - #error Unsupported CONFIG_SYS_SDRAM_CLK - #endif - /* Switch peripheral to PLL2 */ - ldr r0, =CCM_BASE_ADDR - ldr r1, [r0, #CLKCTL_CBCDR] - bic r1, #(1 << 25) - str r1, [r0, #CLKCTL_CBCDR] - - ldr r1, [r0, #CLKCTL_CBCMR] - bic r1, #(3 << 12) - orr r1, #(2 << 12) - str r1, [r0, #CLKCTL_CBCMR] - - /* make sure change is effective */ - 1: - ldr r1, [r0, #CLKCTL_CDHIPR] - cmp r1, #0x0 - bne 1b - #endif setup_pll PLL3_BASE_ADDR, 216 /* Set the platform clock dividers */ @@@ -332,8 -269,58 +274,57 @@@ str r1, [r0, #CLKCTL_CSCMR1] ldr r1, =0x00C30321 str r1, [r0, #CLKCTL_CSCDR1] - #elif defined(CONFIG_MX53) + /* make sure divider effective */ + 1: ldr r1, [r0, #CLKCTL_CDHIPR] + cmp r1, #0x0 + bne 1b + + str r4, [r0, #CLKCTL_CCDR] + + /* for cko - for ARM div by 8 */ + mov r1, #0x000A0000 + add r1, r1, #0x00000F0 + str r1, [r0, #CLKCTL_CCOSR] + #else /* CONFIG_MX53 */ + ldr r0, =CCM_BASE_ADDR + + /* Gate of clocks to the peripherals first */ + ldr r1, =0x3FFFFFFF + str r1, [r0, #CLKCTL_CCGR0] + str r4, [r0, #CLKCTL_CCGR1] + str r4, [r0, #CLKCTL_CCGR2] + str r4, [r0, #CLKCTL_CCGR3] + str r4, [r0, #CLKCTL_CCGR7] + ldr r1, =0x00030000 + str r1, [r0, #CLKCTL_CCGR4] + ldr r1, =0x00FFF030 + str r1, [r0, #CLKCTL_CCGR5] + ldr r1, =0x0F00030F + str r1, [r0, #CLKCTL_CCGR6] + + /* Switch ARM to step clock */ + mov r1, #0x4 + str r1, [r0, #CLKCTL_CCSR] + + setup_pll PLL1_BASE_ADDR, 800 + + setup_pll PLL3_BASE_ADDR, 400 + + /* Switch peripheral to PLL3 */ + ldr r0, =CCM_BASE_ADDR + ldr r1, =0x00015154 + str r1, [r0, #CLKCTL_CBCMR] + ldr r1, =0x02888945 + orr r1, r1, #(1 << 16) + str r1, [r0, #CLKCTL_CBCDR] + /* make sure change is effective */ + 1: ldr r1, [r0, #CLKCTL_CDHIPR] + cmp r1, #0x0 + bne 1b + + setup_pll PLL2_BASE_ADDR, 400 + /* Switch peripheral to PLL2 */ - ldr r0, =CCM_BASE_ADDR ldr r1, =0x00808145 orr r1, r1, #(2 << 10) orr r1, r1, #(0 << 16) @@@ -342,28 -329,61 +333,65 @@@ ldr r1, =0x00016154 str r1, [r0, #CLKCTL_CBCMR] - /* Change uart clk parent to pll2*/ + + /*change uart clk parent to pll2*/ ldr r1, [r0, #CLKCTL_CSCMR1] - and r1, r1, #0xfcffffff - orr r1, r1, #0x01000000 + bic r1, #(0x3 << 24) + orr r1, r1, #(0x1 << 24) str r1, [r0, #CLKCTL_CSCMR1] + + /* make sure change is effective */ + 1: ldr r1, [r0, #CLKCTL_CDHIPR] + cmp r1, #0x0 + bne 1b + + setup_pll PLL3_BASE_ADDR, 216 + + setup_pll PLL4_BASE_ADDR, 455 + + /* Set the platform clock dividers */ + ldr r0, =ARM_BASE_ADDR + ldr r1, =0x00000124 + str r1, [r0, #0x14] + + ldr r0, =CCM_BASE_ADDR + mov r1, #0 + str r1, [r0, #CLKCTL_CACRR] + + /* Switch ARM back to PLL 1. */ + mov r1, #0x0 + str r1, [r0, #CLKCTL_CCSR] + + /* make uart div=6 */ ldr r1, [r0, #CLKCTL_CSCDR1] - and r1, r1, #0xffffffc0 + bic r1, #(0x3f << 0) orr r1, r1, #0x0a str r1, [r0, #CLKCTL_CSCDR1] - #endif + /* make sure divider effective */ +1: ldr r1, [r0, #CLKCTL_CDHIPR] + cmp r1, #0x0 + bne 1b - #endif - mov r1, #0x0 - str r1, [r0, #CLKCTL_CCDR] - /* for cko - for ARM div by 8 */ - mov r1, #0x000A0000 - add r1, r1, #0x00000F0 - str r1, [r0, #CLKCTL_CCOSR] + /* Restore the default values in the Gate registers */ + ldr r1, =0xFFFFFFFF + str r1, [r0, #CLKCTL_CCGR0] + str r1, [r0, #CLKCTL_CCGR1] + str r1, [r0, #CLKCTL_CCGR2] + str r1, [r0, #CLKCTL_CCGR3] + str r1, [r0, #CLKCTL_CCGR4] + str r1, [r0, #CLKCTL_CCGR5] + str r1, [r0, #CLKCTL_CCGR6] + str r1, [r0, #CLKCTL_CCGR7] + + mov r1, #0x00000 + str r1, [r0, #CLKCTL_CCDR] + + /* for cko - for ARM div by 8 */ + mov r1, #0x000A0000 + add r1, r1, #0x00000F0 + str r1, [r0, #CLKCTL_CCOSR] + + #endif /* CONFIG_MX53 */ .endm .macro setup_wdog @@@ -398,25 -420,27 +428,30 @@@ ENTRY(lowlevel_init ENDPROC(lowlevel_init) /* Board level setting value */ - W_DP_OP_864: .word DP_OP_864 - W_DP_MFD_864: .word DP_MFD_864 - W_DP_MFN_864: .word DP_MFN_864 - W_DP_MFN_800_DIT: .word DP_MFN_800_DIT - W_DP_OP_800: .word DP_OP_800 - W_DP_MFD_800: .word DP_MFD_800 - W_DP_MFN_800: .word DP_MFN_800 - W_DP_OP_665: .word DP_OP_665 - W_DP_MFD_665: .word DP_MFD_665 - W_DP_MFN_665: .word DP_MFN_665 - W_DP_OP_600: .word DP_OP_600 - W_DP_MFD_600: .word DP_MFD_600 - W_DP_MFN_600: .word DP_MFN_600 - W_DP_OP_400: .word DP_OP_400 - W_DP_MFD_400: .word DP_MFD_400 - W_DP_MFN_400: .word DP_MFN_400 - W_DP_OP_333: .word DP_OP_333 - W_DP_MFD_333: .word DP_MFD_333 - W_DP_MFN_333: .word DP_MFN_333 - W_DP_OP_216: .word DP_OP_216 - W_DP_MFD_216: .word DP_MFD_216 - W_DP_MFN_216: .word DP_MFN_216 + #if defined(CONFIG_MX51_PLL_ERRATA) + W_DP_864: .word DP_OP_864 + .word DP_MFD_864 + .word DP_MFN_864 + W_DP_MFN_800_DIT: .word DP_MFN_800_DIT + #else + W_DP_800: .word DP_OP_800 + .word DP_MFD_800 + .word DP_MFN_800 + #endif + #if defined(CONFIG_MX51) + W_DP_665: .word DP_OP_665 + .word DP_MFD_665 + .word DP_MFN_665 ++W_DP_600: .word DP_OP_600 ++ .word DP_MFD_600 ++ .word DP_MFN_600 + #endif + W_DP_216: .word DP_OP_216 + .word DP_MFD_216 + .word DP_MFN_216 + W_DP_400: .word DP_OP_400 + .word DP_MFD_400 + .word DP_MFN_400 + W_DP_455: .word DP_OP_455 + .word DP_MFD_455 + .word DP_MFN_455 diff --cc arch/arm/cpu/armv7/mx5/soc.c index d104a66a7f,263658aa4b..8d8cf61b16 --- a/arch/arm/cpu/armv7/mx5/soc.c +++ b/arch/arm/cpu/armv7/mx5/soc.c @@@ -88,8 -72,16 +89,16 @@@ u32 get_cpu_rev(void return system_rev; } + #ifndef CONFIG_SYS_DCACHE_OFF + void enable_caches(void) + { + /* Enable D-cache. I-cache is already enabled in start.S */ + dcache_enable(); + } + #endif + #if defined(CONFIG_FEC_MXC) -void imx_get_mac_from_fuse(int dev_id, unsigned char *mac) +static void __imx_get_mac_from_fuse(int dev_id, unsigned char *mac) { int i; struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE; diff --cc arch/arm/cpu/armv7/mx6/clock.c index 52d5dc4d90,a50db70b19..41d2b049ef --- a/arch/arm/cpu/armv7/mx6/clock.c +++ b/arch/arm/cpu/armv7/mx6/clock.c @@@ -19,6 -19,6 +19,7 @@@ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA */ ++//#define DEBUG #include #include @@@ -29,13 -29,13 +30,49 @@@ #include enum pll_clocks { -- PLL_SYS, /* System PLL */ -- PLL_BUS, /* System Bus PLL*/ -- PLL_USBOTG, /* OTG USB PLL */ -- PLL_ENET, /* ENET PLL */ ++ PLL_ARM, /* PLL1: ARM PLL */ ++ PLL_BUS, /* PLL2: System Bus PLL*/ ++ PLL_USBOTG, /* PLL3: OTG USB PLL */ ++ PLL_AUDIO, /* PLL4: Audio PLL */ ++ PLL_VIDEO, /* PLL5: Video PLL */ ++ PLL_ENET, /* PLL6: ENET PLL */ ++ PLL_USB2, /* PLL7: USB2 PLL */ ++ PLL_MLB, /* PLL8: MLB PLL */ }; --struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; ++struct mxc_ccm_reg *const imx_ccm = (void *)CCM_BASE_ADDR; ++struct anatop_regs *const anatop = (void *)ANATOP_BASE_ADDR; ++ ++int clk_enable(struct clk *clk) ++{ ++ int ret = 0; ++ ++ if (!clk) ++ return 0; ++ if (clk->usecount == 0) { ++debug("%s: Enabling %s clock\n", __func__, clk->name); ++ ret = clk->enable(clk); ++ if (ret) ++ return ret; ++ clk->usecount++; ++ } ++ assert(clk->usecount > 0); ++ return ret; ++} ++ ++void clk_disable(struct clk *clk) ++{ ++ if (!clk) ++ return; ++ ++ assert(clk->usecount > 0); ++ if (!(--clk->usecount)) { ++ if (clk->disable) { ++debug("%s: Disabling %s clock\n", __func__, clk->name); ++ clk->disable(clk); ++ } ++ } ++} void enable_usboh3_clk(unsigned char enable) { @@@ -55,30 -77,30 +114,64 @@@ static u32 decode_pll(enum pll_clocks p u32 div; switch (pll) { -- case PLL_SYS: -- div = __raw_readl(&imx_ccm->analog_pll_sys); -- div &= BM_ANADIG_PLL_SYS_DIV_SELECT; -- -- return infreq * (div >> 1); ++ case PLL_ARM: ++ div = __raw_readl(&anatop->pll_arm); ++ if (div & BM_ANADIG_PLL_ARM_BYPASS) ++ /* Assume the bypass clock is always derived from OSC */ ++ return infreq; ++ div &= BM_ANADIG_PLL_ARM_DIV_SELECT; ++ ++ return infreq * div / 2; case PLL_BUS: -- div = __raw_readl(&imx_ccm->analog_pll_528); -- div &= BM_ANADIG_PLL_528_DIV_SELECT; ++ div = __raw_readl(&anatop->pll_528); ++ if (div & BM_ANADIG_PLL_SYS_BYPASS) ++ return infreq; ++ div &= BM_ANADIG_PLL_SYS_DIV_SELECT; -- return infreq * (20 + (div << 1)); ++ return infreq * (20 + div * 2); case PLL_USBOTG: -- div = __raw_readl(&imx_ccm->analog_usb1_pll_480_ctrl); ++ div = __raw_readl(&anatop->usb1_pll_480_ctrl); ++ if (div & BM_ANADIG_USB1_PLL_480_CTRL_BYPASS) ++ return infreq; div &= BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT; -- return infreq * (20 + (div << 1)); ++ return infreq * (20 + div * 2); ++ case PLL_AUDIO: ++ div = __raw_readl(&anatop->pll_audio); ++ if (div & BM_ANADIG_PLL_AUDIO_BYPASS) ++ return infreq; ++ div &= BM_ANADIG_PLL_AUDIO_DIV_SELECT; ++ ++ return infreq * div; ++ case PLL_VIDEO: ++ div = __raw_readl(&anatop->pll_video); ++ if (div & BM_ANADIG_PLL_VIDEO_BYPASS) ++ return infreq; ++ div &= BM_ANADIG_PLL_VIDEO_DIV_SELECT; ++ ++ return infreq * div; case PLL_ENET: -- div = __raw_readl(&imx_ccm->analog_pll_enet); ++ div = __raw_readl(&anatop->pll_enet); ++ if (div & BM_ANADIG_PLL_ENET_BYPASS) ++ return infreq; div &= BM_ANADIG_PLL_ENET_DIV_SELECT; -- return (div == 3 ? 125000000 : 25000000 * (div << 1)); -- default: ++ return (div == 3 ? 125000000 : 25000000 * div * 2); ++ case PLL_USB2: ++ div = __raw_readl(&anatop->usb2_pll_480_ctrl); ++ if (div & BM_ANADIG_USB2_PLL_480_CTRL_BYPASS) ++ return infreq; ++ div &= BM_ANADIG_USB2_PLL_480_CTRL_DIV_SELECT; ++ ++ return infreq * (20 + div * 2); ++ case PLL_MLB: ++ div = __raw_readl(&anatop->pll_mlb); ++ if (div & BM_ANADIG_PLL_MLB_BYPASS) ++ return infreq; ++ /* unknown external clock provided on MLB_CLK pin */ return 0; } -- /* NOTREACHED */ ++ return 0; } static u32 get_mcu_main_clk(void) @@@ -88,7 -110,7 +181,7 @@@ reg = __raw_readl(&imx_ccm->cacrr); reg &= MXC_CCM_CACRR_ARM_PODF_MASK; reg >>= MXC_CCM_CACRR_ARM_PODF_OFFSET; - freq = decode_pll(PLL_SYS, CONFIG_SYS_MX6_HCLK); - freq = decode_pll(PLL_SYS, MXC_HCLK); ++ freq = decode_pll(PLL_ARM, MXC_HCLK); return freq / (reg + 1); } @@@ -109,10 -131,10 +202,8 @@@ u32 get_periph_clk(void break; case 1: case 2: - freq = CONFIG_SYS_MX6_HCLK; - break; - default: + freq = MXC_HCLK; break; - default: - break; } } else { reg = __raw_readl(&imx_ccm->cbcmr); @@@ -132,8 -154,8 +223,6 @@@ case 3: freq = PLL2_PFD2_DIV_FREQ; break; -- default: -- break; } } @@@ -230,6 -252,6 +319,33 @@@ static u32 get_emi_slow_clk(void return root_freq / (emi_slow_pof + 1); } ++static u32 get_nfc_clk(void) ++{ ++ u32 cs2cdr = __raw_readl(&imx_ccm->cs2cdr); ++ u32 podf = (cs2cdr & MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK) >> MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET; ++ u32 pred = (cs2cdr & MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK) >> MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET; ++ int nfc_clk_sel = (cs2cdr & MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK) >> ++ MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET; ++ u32 root_freq; ++ ++ switch (nfc_clk_sel) { ++ case 0: ++ root_freq = PLL2_PFD0_FREQ; ++ break; ++ case 1: ++ root_freq = decode_pll(PLL_BUS, MXC_HCLK); ++ break; ++ case 2: ++ root_freq = decode_pll(PLL_USBOTG, MXC_HCLK); ++ break; ++ case 3: ++ root_freq = PLL2_PFD2_FREQ; ++ break; ++ } ++ ++ return root_freq / (pred + 1) / (podf + 1); ++} ++ static u32 get_mmdc_ch0_clk(void) { u32 cbcdr = __raw_readl(&imx_ccm->cbcdr); @@@ -294,10 -316,10 +410,8 @@@ u32 imx_get_fecclk(void int enable_sata_clock(void) { -- u32 reg = 0; ++ u32 reg; s32 timeout = 100000; -- struct mxc_ccm_reg *const imx_ccm -- = (struct mxc_ccm_reg *) CCM_BASE_ADDR; /* Enable sata clock */ reg = readl(&imx_ccm->CCGR5); /* CCGR5 */ @@@ -305,24 -327,24 +419,52 @@@ writel(reg, &imx_ccm->CCGR5); /* Enable PLLs */ -- reg = readl(&imx_ccm->analog_pll_enet); -- reg &= ~BM_ANADIG_PLL_SYS_POWERDOWN; -- writel(reg, &imx_ccm->analog_pll_enet); -- reg |= BM_ANADIG_PLL_SYS_ENABLE; ++ reg = readl(&anatop->pll_enet); ++ reg &= ~BM_ANADIG_PLL_ENET_POWERDOWN; ++ writel(reg, &anatop->pll_enet); ++ reg |= BM_ANADIG_PLL_ENET_ENABLE; while (timeout--) { -- if (readl(&imx_ccm->analog_pll_enet) & BM_ANADIG_PLL_SYS_LOCK) ++ if (readl(&anatop->pll_enet) & BM_ANADIG_PLL_ENET_LOCK) break; } if (timeout <= 0) return -EIO; -- reg &= ~BM_ANADIG_PLL_SYS_BYPASS; -- writel(reg, &imx_ccm->analog_pll_enet); ++ reg &= ~BM_ANADIG_PLL_ENET_BYPASS; ++ writel(reg, &anatop->pll_enet); reg |= BM_ANADIG_PLL_ENET_ENABLE_SATA; -- writel(reg, &imx_ccm->analog_pll_enet); ++ writel(reg, &anatop->pll_enet); return 0 ; } ++void ipu_clk_enable(void) ++{ ++ u32 reg = readl(&imx_ccm->CCGR3); ++ reg |= MXC_CCM_CCGR3_CG0_MASK; ++ writel(reg, &imx_ccm->CCGR3); ++} ++ ++void ipu_clk_disable(void) ++{ ++ u32 reg = readl(&imx_ccm->CCGR3); ++ reg &= ~MXC_CCM_CCGR3_CG0_MASK; ++ writel(reg, &imx_ccm->CCGR3); ++} ++ ++void ocotp_clk_enable(void) ++{ ++ u32 reg = readl(&imx_ccm->CCGR2); ++ reg |= MXC_CCM_CCGR2_CG6_MASK; ++ writel(reg, &imx_ccm->CCGR2); ++} ++ ++void ocotp_clk_disable(void) ++{ ++ u32 reg = readl(&imx_ccm->CCGR2); ++ reg &= ~MXC_CCM_CCGR2_CG6_MASK; ++ writel(reg, &imx_ccm->CCGR2); ++} ++ unsigned int mxc_get_clock(enum mxc_clock clk) { switch (clk) { @@@ -356,41 -379,43 +499,168 @@@ return get_usdhc_clk(3); case MXC_SATA_CLK: return get_ahb_clk(); -- default: -- break; ++ case MXC_NFC_CLK: ++ return get_nfc_clk(); } return -1; } ++static inline int gcd(int m, int n) ++{ ++ int t; ++ while (m > 0) { ++ if (n > m) { ++ t = m; ++ m = n; ++ n = t; ++ } /* swap */ ++ m -= n; ++ } ++ return n; ++} ++ ++/* Config CPU clock */ ++static int config_core_clk(u32 ref, u32 freq) ++{ ++ int d; ++ int div = 0; ++ int mul = 0; ++ int min_err = ~0 >> 1; ++ u32 reg; ++ ++ if (freq / ref > 108 || freq / ref * 8 < 54) { ++ return -EINVAL; ++ } ++ ++ for (d = 1; d < 8; d++) { ++ int m = (freq + (ref - 1)) / ref; ++ unsigned long f; ++ int err; ++ ++ if (m > 108 || m < 54) ++ return -EINVAL; ++ ++ f = ref * m / d; ++ while (f > freq) { ++ if (--m < 54) ++ return -EINVAL; ++ f = ref * m / d; ++ } ++ err = freq - f; ++ if (err == 0) ++ break; ++ if (err < 0) ++ return -EINVAL; ++ if (err < min_err) { ++ mul = m; ++ div = d; ++ } ++ } ++ printf("Setting M=%3u D=%2u for %u.%03uMHz (actual: %u.%03uMHz)\n", ++ mul, div, freq / 1000000, freq / 1000 % 1000, ++ ref * mul / div / 1000000, ref * mul / div / 1000 % 1000); ++ ++ reg = readl(&anatop->pll_arm); ++ printf("anadig_pll_arm=%08x -> %08x\n", ++ reg, (reg & ~0x7f) | mul); ++#if 0 ++ writel(div - 1, &imx_ccm->caccr); ++ reg &= 0x7f; ++ writel(reg | mul, &anatop->pll_arm); ++#endif ++ return 0; ++} ++ /* -- * Dump some core clockes. ++ * This function assumes the expected core clock has to be changed by ++ * modifying the PLL. This is NOT true always but for most of the times, ++ * it is. So it assumes the PLL output freq is the same as the expected ++ * core clock (presc=1) unless the core clock is less than PLL_FREQ_MIN. ++ * In the latter case, it will try to increase the presc value until ++ * (presc*core_clk) is greater than PLL_FREQ_MIN. It then makes call to ++ * calc_pll_params() and obtains the values of PD, MFI,MFN, MFD based ++ * on the targeted PLL and reference input clock to the PLL. Lastly, ++ * it sets the register based on these values along with the dividers. ++ * Note 1) There is no value checking for the passed-in divider values ++ * so the caller has to make sure those values are sensible. ++ * 2) Also adjust the NFC divider such that the NFC clock doesn't ++ * exceed NFC_CLK_MAX. ++ * 3) IPU HSP clock is independent of AHB clock. Even it can go up to ++ * 177MHz for higher voltage, this function fixes the max to 133MHz. ++ * 4) This function should not have allowed diag_printf() calls since ++ * the serial driver has been stoped. But leave then here to allow ++ * easy debugging by NOT calling the cyg_hal_plf_serial_stop(). */ ++int mxc_set_clock(u32 ref, u32 freq, enum mxc_clock clk) ++{ ++ freq *= 1000000; ++ ++ switch (clk) { ++ case MXC_ARM_CLK: ++ if (config_core_clk(ref, freq)) ++ return -EINVAL; ++ break; ++#if 0 ++ case MXC_PER_CLK: ++ if (config_periph_clk(ref, freq)) ++ return -EINVAL; ++ break; ++ case MXC_DDR_CLK: ++ if (config_ddr_clk(freq)) ++ return -EINVAL; ++ break; ++ case MXC_NFC_CLK: ++ if (config_nfc_clk(freq)) ++ return -EINVAL; ++ break; ++#endif ++ default: ++ printf("Warning: Unsupported or invalid clock type: %d\n", ++ clk); ++ return -EINVAL; ++ } ++ ++ return 0; ++} ++ ++/* ++ * Dump some core clocks. ++ */ ++#define print_pll(pll) printf("%-12s %4d.%03d MHz\n", #pll, \ ++ decode_pll(pll, MXC_HCLK) / 1000000, \ ++ decode_pll(pll, MXC_HCLK) / 1000 % 1000) ++ ++#define MXC_IPG_PER_CLK MXC_IPG_PERCLK ++#define print_clk(clk) printf("%-12s %4d.%03d MHz\n", #clk, \ ++ mxc_get_clock(MXC_##clk##_CLK) / 1000000, \ ++ mxc_get_clock(MXC_##clk##_CLK) / 1000 % 1000) ++ int do_mx6_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { -- u32 freq; - freq = decode_pll(PLL_SYS, CONFIG_SYS_MX6_HCLK); - freq = decode_pll(PLL_SYS, MXC_HCLK); -- printf("PLL_SYS %8d MHz\n", freq / 1000000); - freq = decode_pll(PLL_BUS, CONFIG_SYS_MX6_HCLK); - freq = decode_pll(PLL_BUS, MXC_HCLK); -- printf("PLL_BUS %8d MHz\n", freq / 1000000); - freq = decode_pll(PLL_USBOTG, CONFIG_SYS_MX6_HCLK); - freq = decode_pll(PLL_USBOTG, MXC_HCLK); -- printf("PLL_OTG %8d MHz\n", freq / 1000000); - freq = decode_pll(PLL_ENET, CONFIG_SYS_MX6_HCLK); - freq = decode_pll(PLL_ENET, MXC_HCLK); -- printf("PLL_NET %8d MHz\n", freq / 1000000); ++ print_pll(PLL_ARM); ++ print_pll(PLL_BUS); ++ print_pll(PLL_USBOTG); ++ print_pll(PLL_AUDIO); ++ print_pll(PLL_VIDEO); ++ print_pll(PLL_ENET); ++ print_pll(PLL_USB2); printf("\n"); -- printf("IPG %8d kHz\n", mxc_get_clock(MXC_IPG_CLK) / 1000); -- printf("UART %8d kHz\n", mxc_get_clock(MXC_UART_CLK) / 1000); -#ifdef CONFIG_MXC_SPI -- printf("CSPI %8d kHz\n", mxc_get_clock(MXC_CSPI_CLK) / 1000); -#endif -- printf("AHB %8d kHz\n", mxc_get_clock(MXC_AHB_CLK) / 1000); -- printf("AXI %8d kHz\n", mxc_get_clock(MXC_AXI_CLK) / 1000); -- printf("DDR %8d kHz\n", mxc_get_clock(MXC_DDR_CLK) / 1000); -- printf("USDHC1 %8d kHz\n", mxc_get_clock(MXC_ESDHC_CLK) / 1000); -- printf("USDHC2 %8d kHz\n", mxc_get_clock(MXC_ESDHC2_CLK) / 1000); -- printf("USDHC3 %8d kHz\n", mxc_get_clock(MXC_ESDHC3_CLK) / 1000); -- printf("USDHC4 %8d kHz\n", mxc_get_clock(MXC_ESDHC4_CLK) / 1000); -- printf("EMI SLOW %8d kHz\n", mxc_get_clock(MXC_EMI_SLOW_CLK) / 1000); -- printf("IPG PERCLK %8d kHz\n", mxc_get_clock(MXC_IPG_PERCLK) / 1000); ++ print_clk(IPG); ++ print_clk(UART); ++ print_clk(CSPI); ++ print_clk(AHB); ++ print_clk(AXI); ++ print_clk(DDR); ++ print_clk(ESDHC); ++ print_clk(ESDHC2); ++ print_clk(ESDHC3); ++ print_clk(ESDHC4); ++ print_clk(EMI_SLOW); ++ print_clk(NFC); ++ print_clk(IPG_PER); ++ print_clk(ARM); return 0; } diff --cc arch/arm/cpu/armv7/mx6/soc.c index 90f208809b,a8aad5dd0a..06b36deecd --- a/arch/arm/cpu/armv7/mx6/soc.c +++ b/arch/arm/cpu/armv7/mx6/soc.c @@@ -27,9 -27,18 +27,55 @@@ #include #include #include ++#include ++#include #include ++#include #include + #include ++#ifdef CONFIG_VIDEO_IPUV3 ++#include ++#endif ++ ++DECLARE_GLOBAL_DATA_PTR; ++ ++#define TEMPERATURE_MIN -40 ++#define TEMPERATURE_HOT 80 ++#define TEMPERATURE_MAX 125 ++#define REG_VALUE_TO_CEL(ratio, raw) ((raw_n40c - raw) * 100 / ratio - 40) ++ ++#define __data __attribute__((section(".data"))) + + struct scu_regs { + u32 ctrl; + u32 config; + u32 status; + u32 invalidate; + u32 fpga_rev; + }; + ++#ifdef CONFIG_HW_WATCHDOG ++#define wdog_base ((void *)WDOG1_BASE_ADDR) ++#define WDOG_WCR 0x00 ++#define WCR_WDE (1 << 2) ++#define WDOG_WSR 0x02 ++ ++void hw_watchdog_reset(void) ++{ ++ if (readw(wdog_base + WDOG_WCR) & WCR_WDE) { ++ static u16 toggle = 0xaaaa; ++ static int first = 1; ++ ++ if (first) { ++ printf("Watchdog active\n"); ++ first = 0; ++ } ++ writew(toggle, wdog_base + WDOG_WSR); ++ toggle ^= 0xffff; ++ } ++} ++#endif + u32 get_cpu_rev(void) { struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; @@@ -85,7 -101,7 +138,7 @@@ void init_aips(void * Possible values are from 0.725V to 1.450V in steps of * 0.025V (25mV). */ --void set_vddsoc(u32 mv) ++static void set_vddsoc(u32 mv) { struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; u32 val, reg = readl(&anatop->reg_core); @@@ -105,15 -121,14 +158,134 @@@ writel(reg, &anatop->reg_core); } ++static u32 __data thermal_calib; ++ ++int read_cpu_temperature(void) ++{ ++ unsigned int reg, tmp, i; ++ unsigned int raw_25c, raw_hot, hot_temp, raw_n40c, ratio; ++ int temperature; ++ struct anatop_regs *const anatop = (void *)ANATOP_BASE_ADDR; ++ struct mx6_ocotp_regs *const ocotp_regs = (void *)OCOTP_BASE_ADDR; ++ ++ if (!thermal_calib) { ++ ocotp_clk_enable(); ++ writel(1, &ocotp_regs->hw_ocotp_read_ctrl); ++ thermal_calib = readl(&ocotp_regs->hw_ocotp_ana1); ++ writel(0, &ocotp_regs->hw_ocotp_read_ctrl); ++ ocotp_clk_disable(); ++ } ++ ++ if (thermal_calib == 0 || thermal_calib == 0xffffffff) ++ return TEMPERATURE_MIN; ++ ++ /* Fuse data layout: ++ * [31:20] sensor value @ 25C ++ * [19:8] sensor value of hot ++ * [7:0] hot temperature value */ ++ raw_25c = thermal_calib >> 20; ++ raw_hot = (thermal_calib & 0xfff00) >> 8; ++ hot_temp = thermal_calib & 0xff; ++ ++ ratio = ((raw_25c - raw_hot) * 100) / (hot_temp - 25); ++ raw_n40c = raw_25c + (13 * ratio) / 20; ++ ++ /* now we only using single measure, every time we measure ++ the temperature, we will power on/down the anadig module*/ ++ writel(BM_ANADIG_TEMPSENSE0_POWER_DOWN, &anatop->tempsense0_clr); ++ writel(BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF, &anatop->ana_misc0_set); ++ ++ /* write measure freq */ ++ reg = readl(&anatop->tempsense1); ++ reg &= ~BM_ANADIG_TEMPSENSE1_MEASURE_FREQ; ++ reg |= 327; ++ writel(reg, &anatop->tempsense1); ++ ++ writel(BM_ANADIG_TEMPSENSE0_MEASURE_TEMP, &anatop->tempsense0_clr); ++ writel(BM_ANADIG_TEMPSENSE0_FINISHED, &anatop->tempsense0_clr); ++ writel(BM_ANADIG_TEMPSENSE0_MEASURE_TEMP, &anatop->tempsense0_set); ++ ++ tmp = 0; ++ /* read five times of temperature values to get average*/ ++ for (i = 0; i < 5; i++) { ++ while ((readl(&anatop->tempsense0) & ++ BM_ANADIG_TEMPSENSE0_FINISHED) == 0) ++ udelay(10000); ++ reg = readl(&anatop->tempsense0); ++ tmp += (reg & BM_ANADIG_TEMPSENSE0_TEMP_VALUE) >> ++ BP_ANADIG_TEMPSENSE0_TEMP_VALUE; ++ writel(BM_ANADIG_TEMPSENSE0_FINISHED, ++ &anatop->tempsense0_clr); ++ } ++ ++ tmp = tmp / 5; ++ if (tmp <= raw_n40c) ++ temperature = REG_VALUE_TO_CEL(ratio, tmp); ++ else ++ temperature = TEMPERATURE_MIN; ++ ++ /* power down anatop thermal sensor */ ++ writel(BM_ANADIG_TEMPSENSE0_POWER_DOWN, &anatop->tempsense0_set); ++ writel(BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF, &anatop->ana_misc0_clr); ++ ++ return temperature; ++} ++ ++int check_cpu_temperature(int boot) ++{ ++ static int __data max_temp; ++ int boot_limit = TEMPERATURE_HOT; ++ int tmp = read_cpu_temperature(); ++ ++debug("max_temp[%p]=%d diff=%d\n", &max_temp, max_temp, tmp - max_temp); ++ ++ if (tmp < TEMPERATURE_MIN || tmp > TEMPERATURE_MAX) { ++ printf("Temperature: can't get valid data!\n"); ++ return tmp; ++ } ++ ++ while (tmp >= boot_limit) { ++ if (boot) { ++ printf("CPU is %d C, too hot to boot, waiting...\n", ++ tmp); ++ udelay(5000000); ++ tmp = read_cpu_temperature(); ++ boot_limit = TEMPERATURE_HOT - 1; ++ } else { ++ printf("CPU is %d C, too hot, resetting...\n", ++ tmp); ++ udelay(1000000); ++ reset_cpu(0); ++ } ++ } ++ ++ if (boot) { ++ printf("Temperature: %d C, calibration data 0x%x\n", ++ tmp, thermal_calib); ++ } else if (tmp > max_temp) { ++ if (tmp > TEMPERATURE_HOT - 5) ++ printf("WARNING: CPU temperature %d C\n", tmp); ++ max_temp = tmp; ++ } ++ return tmp; ++} ++ int arch_cpu_init(void) { init_aips(); set_vddsoc(1200); /* Set VDDSOC to 1.2V */ ++#ifdef CONFIG_VIDEO_IPUV3 ++ gd->arch.ipu_hw_rev = IPUV3_HW_REV_IPUV3H; ++#endif ++#ifdef CONFIG_APBH_DMA ++ /* Timer is required for Initializing APBH DMA */ ++ timer_init(); ++ mxs_dma_init(); ++#endif return 0; } - #endif #ifndef CONFIG_SYS_DCACHE_OFF void enable_caches(void) @@@ -133,13 -148,48 +305,144 @@@ void imx_get_mac_from_fuse(int dev_id, u32 value = readl(&fuse->mac_addr_high); mac[0] = (value >> 8); -- mac[1] = value ; ++ mac[1] = value; value = readl(&fuse->mac_addr_low); -- mac[2] = value >> 24 ; -- mac[3] = value >> 16 ; -- mac[4] = value >> 8 ; -- mac[5] = value ; -- ++ mac[2] = value >> 24; ++ mac[3] = value >> 16; ++ mac[4] = value >> 8; ++ mac[5] = value; } #endif + + void boot_mode_apply(unsigned cfg_val) + { + unsigned reg; + struct src *psrc = (struct src *)SRC_BASE_ADDR; + writel(cfg_val, &psrc->gpr9); + reg = readl(&psrc->gpr10); + if (cfg_val) + reg |= 1 << 28; + else + reg &= ~(1 << 28); + writel(reg, &psrc->gpr10); + } + /* + * cfg_val will be used for + * Boot_cfg4[7:0]:Boot_cfg3[7:0]:Boot_cfg2[7:0]:Boot_cfg1[7:0] + * After reset, if GPR10[28] is 1, ROM will copy GPR9[25:0] + * to SBMR1, which will determine the boot device. + */ + const struct boot_mode soc_boot_modes[] = { + {"normal", MAKE_CFGVAL(0x00, 0x00, 0x00, 0x00)}, + /* reserved value should start rom usb */ + {"usb", MAKE_CFGVAL(0x01, 0x00, 0x00, 0x00)}, + {"sata", MAKE_CFGVAL(0x20, 0x00, 0x00, 0x00)}, + {"escpi1:0", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x08)}, + {"escpi1:1", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x18)}, + {"escpi1:2", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x28)}, + {"escpi1:3", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x38)}, + /* 4 bit bus width */ + {"esdhc1", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)}, + {"esdhc2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)}, + {"esdhc3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)}, + {"esdhc4", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)}, + {NULL, 0}, + }; ++#define RESET_MAX_TIMEOUT 1000000 ++#define MXS_BLOCK_SFTRST (1 << 31) ++#define MXS_BLOCK_CLKGATE (1 << 30) ++#include ++ ++static const int scale = 1; ++ ++int mxs_wait_mask_set(struct mx6_register_32 *mx6_reg, uint32_t mask, unsigned long timeout) ++{ ++ unsigned long loops = 0; ++ ++ timeout /= scale; ++ if (timeout == 0) ++ timeout++; ++ ++ /* Wait for at least one microsecond for the bit mask to be set */ ++ while ((readl(&mx6_reg->reg) & mask) != mask) { ++ if ((loops += scale) >= timeout) { ++ printf("MASK %08x in %p not set after %lu ticks\n", ++ mask, &mx6_reg->reg, loops * scale); ++ return 1; ++ } ++ udelay(scale); ++ } ++ if (loops == 0) ++ udelay(1); ++ ++ return 0; ++} ++ ++int mxs_wait_mask_clr(struct mx6_register_32 *mx6_reg, uint32_t mask, unsigned long timeout) ++{ ++ unsigned long loops = 0; ++ ++ timeout /= scale; ++ if (timeout == 0) ++ timeout++; ++ ++ /* Wait for at least one microsecond for the bit mask to be cleared */ ++ while ((readl(&mx6_reg->reg) & mask) != 0) { ++ if ((loops += scale) >= timeout) { ++ printf("MASK %08x in %p not cleared after %lu ticks\n", ++ mask, &mx6_reg->reg, loops * scale); ++ return 1; ++ } ++ udelay(scale); ++ } ++ if (loops == 0) ++ udelay(1); ++ ++ return 0; ++} ++ ++int mxs_reset_block(struct mx6_register_32 *mx6_reg) ++{ ++ /* Clear SFTRST */ ++ writel(MXS_BLOCK_SFTRST, &mx6_reg->reg_clr); ++ ++ if (mxs_wait_mask_clr(mx6_reg, MXS_BLOCK_SFTRST, RESET_MAX_TIMEOUT)) { ++ printf("TIMEOUT waiting for SFTRST[%p] to clear: %08x\n", ++ &mx6_reg->reg, readl(&mx6_reg->reg)); ++ return 1; ++ } ++ ++ /* Clear CLKGATE */ ++ writel(MXS_BLOCK_CLKGATE, &mx6_reg->reg_clr); ++ ++ /* Set SFTRST */ ++ writel(MXS_BLOCK_SFTRST, &mx6_reg->reg_set); ++ ++ /* Wait for CLKGATE being set */ ++ if (mxs_wait_mask_set(mx6_reg, MXS_BLOCK_CLKGATE, RESET_MAX_TIMEOUT)) { ++ printf("TIMEOUT waiting for CLKGATE[%p] to set: %08x\n", ++ &mx6_reg->reg, readl(&mx6_reg->reg)); ++ return 0; ++ } ++ ++ /* Clear SFTRST */ ++ writel(MXS_BLOCK_SFTRST, &mx6_reg->reg_clr); ++ ++ if (mxs_wait_mask_clr(mx6_reg, MXS_BLOCK_SFTRST, RESET_MAX_TIMEOUT)) { ++ printf("TIMEOUT waiting for SFTRST[%p] to clear: %08x\n", ++ &mx6_reg->reg, readl(&mx6_reg->reg)); ++ return 1; ++ } ++ ++ /* Clear CLKGATE */ ++ writel(MXS_BLOCK_CLKGATE, &mx6_reg->reg_clr); ++ ++ if (mxs_wait_mask_clr(mx6_reg, MXS_BLOCK_CLKGATE, RESET_MAX_TIMEOUT)) { ++ printf("TIMEOUT waiting for CLKGATE[%p] to clear: %08x\n", ++ &mx6_reg->reg, readl(&mx6_reg->reg)); ++ return 1; ++ } ++ ++ return 0; ++} diff --cc arch/arm/cpu/armv7/omap-common/boot-common.c index 44ca6829a8,2b584e0a53..d5fb40e22e --- a/arch/arm/cpu/armv7/omap-common/boot-common.c +++ b/arch/arm/cpu/armv7/omap-common/boot-common.c @@@ -35,14 -38,14 +38,14 @@@ struct omap_boot_parameters boot_param * We would not typically need to save these parameters in regular * U-Boot. This is needed only in SPL at the moment. */ -u32 omap_bootmode = MMCSD_MODE_FAT; +u32 omap_bootmode __attribute__ ((section(".data"))) = MMCSD_MODE_UNDEFINED; - u32 omap_boot_device(void) + u32 spl_boot_device(void) { - return (u32) (boot_params.omap_bootdevice); + return boot_params.omap_bootdevice; } - u32 omap_boot_mode(void) + u32 spl_boot_mode(void) { return omap_bootmode; } diff --cc arch/arm/cpu/armv7/omap-common/lowlevel_init.S index 087aebb84b,358107776d..fb99cea722 --- a/arch/arm/cpu/armv7/omap-common/lowlevel_init.S +++ b/arch/arm/cpu/armv7/omap-common/lowlevel_init.S @@@ -52,17 -53,18 +53,17 @@@ ENTRY(save_boot_params ldr r1, =boot_params str r0, [r1] #ifdef CONFIG_SPL_BUILD - /* Store the boot device in omap_boot_device */ + /* Store the boot device in spl_boot_device */ - ldrb r2, [r0, #BOOT_DEVICE_OFFSET] @ r1 <- value of boot device + ldrb r2, [r0, #BOOT_DEVICE_OFFSET] @ r2 <- value of boot device and r2, #BOOT_DEVICE_MASK - strb r2, [r1, #BOOT_DEVICE_OFFSET] @ omap_boot_device <- r2 - ldr r3, =boot_params - strb r2, [r3, #BOOT_DEVICE_OFFSET] @ spl_boot_device <- r1 ++ strb r2, [r1, #BOOT_DEVICE_OFFSET] @ spl_boot_device <- r2 - /* boot mode is passed only for devices that can do raw/fat mode */ - cmp r2, #2 + /* boot mode is passed only for devices that can raw/fat mode */ + cmp r2, #BOOT_DEVICE_XIP blt 2f - cmp r2, #7 + cmp r2, #BOOT_DEVICE_MMC2 bgt 2f - /* Store the boot mode (raw/FAT) in omap_boot_mode */ + /* Store the boot mode (raw/FAT) in omap_bootmode */ ldr r2, [r0, #DEV_DESC_PTR_OFFSET] @ get the device descriptor ptr ldr r2, [r2, #DEV_DATA_PTR_OFFSET] @ get the pDeviceData ptr ldr r2, [r2, #BOOT_MODE_OFFSET] @ get the boot mode @@@ -98,6 -83,6 +81,7 @@@ ENTRY(set_pl310_ctrl_reg PUSH {r4-r11, lr} @ save registers - ROM code may pollute @ our registers LDR r12, =0x102 @ Set PL310 control register - value in R0 ++ smc #0 .word 0xe1600070 @ SMC #0 - hand assembled because -march=armv5 @ call ROM Code API to set control register POP {r4-r11, pc} diff --cc arch/arm/cpu/armv7/omap-common/timer.c index c4c0e6e59f,36bea5f94c..2292ea0eaf --- a/arch/arm/cpu/armv7/omap-common/timer.c +++ b/arch/arm/cpu/armv7/omap-common/timer.c @@@ -98,13 -52,14 +98,13 @@@ int timer_init(void /* start the counter ticking up, reload value on overflow */ writel(TIMER_LOAD_VAL, &timer_base->tldr); /* enable timer */ - writel((CONFIG_SYS_PTV << 2) | TCLR_PRE | TCLR_AR | TCLR_ST, - &timer_base->tclr); - - /* reset time, capture current incrementer value time */ - gd->arch.lastinc = readl(&timer_base->tcrr) / - (TIMER_CLOCK / CONFIG_SYS_HZ); - gd->arch.tbl = 0; /* start "advancing" time stamp from 0 */ - + writel(TCLR_VAL, &timer_base->tclr); +#endif +#ifndef CONFIG_SPL_BUILD - gd->lastinc = -30 * TIMER_CLOCK; - gd->tbl = TIMER_START; - gd->timer_rate_hz = TIMER_CLOCK; ++ gd->arch.lastinc = -30 * TIMER_CLOCK; ++ gd->arch.tbl = TIMER_START; ++ gd->arch.timer_rate_hz = TIMER_CLOCK; +#endif return 0; } @@@ -144,12 -109,7 +144,12 @@@ ulong get_timer_masked(void */ unsigned long long get_ticks(void) { - return get_timer(0); + ulong now = readl(&timer_base->tcrr); - ulong inc = now - gd->lastinc; ++ ulong inc = now - gd->arch.lastinc; + - gd->tbl += inc; - gd->lastinc = now; - return gd->tbl; ++ gd->arch.tbl += inc; ++ gd->arch.lastinc = now; ++ return gd->arch.tbl; } /* @@@ -158,5 -118,5 +158,5 @@@ */ ulong get_tbclk(void) { - return gd->timer_rate_hz; - return CONFIG_SYS_HZ; ++ return gd->arch.timer_rate_hz; } diff --cc arch/arm/cpu/armv7/start.S index ebb7c5cee0,dcc1f831bc..0eebe22690 --- a/arch/arm/cpu/armv7/start.S +++ b/arch/arm/cpu/armv7/start.S @@@ -81,11 -81,7 +81,7 @@@ _end_vect .globl _TEXT_BASE _TEXT_BASE: - #ifndef CONFIG_SPL_BUILD -- .word CONFIG_SYS_TEXT_BASE - #else - .word CONFIG_SPL_TEXT_BASE - #endif ++ .word _start /* * These are defined in the board-specific linker script. @@@ -182,13 -172,10 +172,9 @@@ ENTRY(relocate_code mov r5, r1 /* save addr of gd */ mov r6, r2 /* save addr of destination */ - /* Set up the stack */ - stack_setup: - mov sp, r4 - adr r0, _start - cmp r0, r6 - moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */ + subs r9, r6, r0 - beq clear_bss /* skip relocation */ + beq relocate_done /* skip relocation */ mov r1, r6 /* r1 <- scratch for copy_loop */ ldr r3, _image_copy_end_ofs add r2, r0, r3 /* r2 <- source end address */ @@@ -211,8 -197,8 +196,11 @@@ copy_loop add r2, r2, r0 /* r2 <- rel dyn start in FLASH */ ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */ add r3, r3, r0 /* r3 <- rel dyn end in FLASH */ ++ mov r4, r0 fixloop: ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */ ++ cmp r0, r4 ++ blo skipfix add r0, r0, r9 /* r0 <- location to fix up in RAM */ ldr r1, [r2, #4] and r7, r1, #0xff @@@ -235,6 -221,6 +223,7 @@@ fixrel add r1, r1, r9 fixnext: str r1, [r0] ++skipfix: add r2, r2, #8 /* each rel.dyn entry is 8 bytes */ cmp r2, r3 blo fixloop diff --cc arch/arm/dts/mx6q.dtsi index 0000000000,0000000000..e6d834f42c new file mode 100644 --- /dev/null +++ b/arch/arm/dts/mx6q.dtsi @@@ -1,0 -1,0 +1,428 @@@ ++ ++/* ++ * Copyright 2013 Freescale Semiconductor, Inc. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ */ ++ ++/include/ "imx6qdl.dtsi" ++ ++/ { ++ cpus { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ cpu@0 { ++ compatible = "arm,cortex-a9"; ++ reg = <0>; ++ next-level-cache = <&L2>; ++ operating-points = < ++ /* kHz uV */ ++ 1200000 1275000 ++ 996000 1250000 ++ 792000 1150000 ++ 396000 950000 ++ >; ++ clock-latency = <61036>; /* two CLK32 periods */ ++ clocks = <&clks 104>, <&clks 6>, <&clks 16>, ++ <&clks 17>, <&clks 170>; ++ clock-names = "arm", "pll2_pfd2_396m", "step", ++ "pll1_sw", "pll1_sys"; ++ arm-supply = <®_arm>; ++ pu-supply = <®_pu>; ++ soc-supply = <®_soc>; ++ }; ++ ++ cpu@1 { ++ compatible = "arm,cortex-a9"; ++ reg = <1>; ++ next-level-cache = <&L2>; ++ }; ++ ++ cpu@2 { ++ compatible = "arm,cortex-a9"; ++ reg = <2>; ++ next-level-cache = <&L2>; ++ }; ++ ++ cpu@3 { ++ compatible = "arm,cortex-a9"; ++ reg = <3>; ++ next-level-cache = <&L2>; ++ }; ++ }; ++ ++ soc { ++ aips-bus@02000000 { /* AIPS1 */ ++ spba-bus@02000000 { ++ ecspi5: ecspi@02018000 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; ++ reg = <0x02018000 0x4000>; ++ interrupts = <0 35 0x04>; ++ clocks = <&clks 116>, <&clks 116>; ++ clock-names = "ipg", "per"; ++ status = "disabled"; ++ }; ++ }; ++ ++ iomuxc: iomuxc@020e0000 { ++ compatible = "fsl,imx6q-iomuxc"; ++ reg = <0x020e0000 0x4000>; ++ ++ /* shared pinctrl settings */ ++ audmux { ++ pinctrl_audmux_1: audmux-1 { ++ fsl,pins = < ++ 18 0x80000000 /* MX6Q_PAD_SD2_DAT0__AUDMUX_AUD4_RXD */ ++ 1586 0x80000000 /* MX6Q_PAD_SD2_DAT3__AUDMUX_AUD4_TXC */ ++ 11 0x80000000 /* MX6Q_PAD_SD2_DAT2__AUDMUX_AUD4_TXD */ ++ 3 0x80000000 /* MX6Q_PAD_SD2_DAT1__AUDMUX_AUD4_TXFS */ ++ >; ++ }; ++ }; ++ ++ ecspi1 { ++ pinctrl_ecspi1_1: ecspi1grp-1 { ++ fsl,pins = < ++ 101 0x100b1 /* MX6Q_PAD_EIM_D17__ECSPI1_MISO */ ++ 109 0x100b1 /* MX6Q_PAD_EIM_D18__ECSPI1_MOSI */ ++ 94 0x100b1 /* MX6Q_PAD_EIM_D16__ECSPI1_SCLK */ ++ >; ++ }; ++ }; ++ ++ enet { ++ pinctrl_enet_1: enetgrp-1 { ++ fsl,pins = < ++ 695 0x1b0b0 /* MX6Q_PAD_ENET_MDIO__ENET_MDIO */ ++ 756 0x1b0b0 /* MX6Q_PAD_ENET_MDC__ENET_MDC */ ++ 24 0x1b0b0 /* MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC */ ++ 30 0x1b0b0 /* MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 */ ++ 34 0x1b0b0 /* MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 */ ++ 39 0x1b0b0 /* MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 */ ++ 44 0x1b0b0 /* MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 */ ++ 56 0x1b0b0 /* MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL */ ++ 702 0x1b0b0 /* MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK */ ++ 74 0x1b0b0 /* MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC */ ++ 52 0x1b0b0 /* MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 */ ++ 61 0x1b0b0 /* MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 */ ++ 66 0x1b0b0 /* MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 */ ++ 70 0x1b0b0 /* MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 */ ++ 48 0x1b0b0 /* MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL */ ++ 1033 0x4001b0a8 /* MX6Q_PAD_GPIO_16__ENET_ANATOP_ETHERNET_REF_OUT*/ ++ >; ++ }; ++ ++ pinctrl_enet_2: enetgrp-2 { ++ fsl,pins = < ++ 890 0x1b0b0 /* MX6Q_PAD_KEY_COL1__ENET_MDIO */ ++ 909 0x1b0b0 /* MX6Q_PAD_KEY_COL2__ENET_MDC */ ++ 24 0x1b0b0 /* MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC */ ++ 30 0x1b0b0 /* MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 */ ++ 34 0x1b0b0 /* MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 */ ++ 39 0x1b0b0 /* MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 */ ++ 44 0x1b0b0 /* MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 */ ++ 56 0x1b0b0 /* MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL */ ++ 702 0x1b0b0 /* MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK */ ++ 74 0x1b0b0 /* MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC */ ++ 52 0x1b0b0 /* MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 */ ++ 61 0x1b0b0 /* MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 */ ++ 66 0x1b0b0 /* MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 */ ++ 70 0x1b0b0 /* MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 */ ++ 48 0x1b0b0 /* MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL */ ++ >; ++ }; ++ }; ++ ++ gpmi-nand { ++ pinctrl_gpmi_nand_1: gpmi-nand-1 { ++ fsl,pins = < ++ 1328 0xb0b1 /* MX6Q_PAD_NANDF_CLE__RAWNAND_CLE */ ++ 1336 0xb0b1 /* MX6Q_PAD_NANDF_ALE__RAWNAND_ALE */ ++ 1344 0xb0b1 /* MX6Q_PAD_NANDF_WP_B__RAWNAND_RESETN */ ++ 1352 0xb000 /* MX6Q_PAD_NANDF_RB0__RAWNAND_READY0 */ ++ 1360 0xb0b1 /* MX6Q_PAD_NANDF_CS0__RAWNAND_CE0N */ ++ 1365 0xb0b1 /* MX6Q_PAD_NANDF_CS1__RAWNAND_CE1N */ ++ 1371 0xb0b1 /* MX6Q_PAD_NANDF_CS2__RAWNAND_CE2N */ ++ 1378 0xb0b1 /* MX6Q_PAD_NANDF_CS3__RAWNAND_CE3N */ ++ 1387 0xb0b1 /* MX6Q_PAD_SD4_CMD__RAWNAND_RDN */ ++ 1393 0xb0b1 /* MX6Q_PAD_SD4_CLK__RAWNAND_WRN */ ++ 1397 0xb0b1 /* MX6Q_PAD_NANDF_D0__RAWNAND_D0 */ ++ 1405 0xb0b1 /* MX6Q_PAD_NANDF_D1__RAWNAND_D1 */ ++ 1413 0xb0b1 /* MX6Q_PAD_NANDF_D2__RAWNAND_D2 */ ++ 1421 0xb0b1 /* MX6Q_PAD_NANDF_D3__RAWNAND_D3 */ ++ 1429 0xb0b1 /* MX6Q_PAD_NANDF_D4__RAWNAND_D4 */ ++ 1437 0xb0b1 /* MX6Q_PAD_NANDF_D5__RAWNAND_D5 */ ++ 1445 0xb0b1 /* MX6Q_PAD_NANDF_D6__RAWNAND_D6 */ ++ 1453 0xb0b1 /* MX6Q_PAD_NANDF_D7__RAWNAND_D7 */ ++ 1463 0x00b1 /* MX6Q_PAD_SD4_DAT0__RAWNAND_DQS */ ++ >; ++ }; ++ }; ++ ++ i2c1 { ++ pinctrl_i2c1_1: i2c1grp-1 { ++ fsl,pins = < ++ 137 0x4001b8b1 /* MX6Q_PAD_EIM_D21__I2C1_SCL */ ++ 196 0x4001b8b1 /* MX6Q_PAD_EIM_D28__I2C1_SDA */ ++ >; ++ }; ++ }; ++ ++ uart1 { ++ pinctrl_uart1_1: uart1grp-1 { ++ fsl,pins = < ++ 1140 0x1b0b1 /* MX6Q_PAD_CSI0_DAT10__UART1_TXD */ ++ 1148 0x1b0b1 /* MX6Q_PAD_CSI0_DAT11__UART1_RXD */ ++ >; ++ }; ++ pinctrl_uart1_2: uart1-grp-2 { ++ fsl,pins = < ++ 120 0x1b0b1 /* MX6Q_PAD_EIM_D19__UART1_CTS */ ++ 128 0x1b0b1 /* MX6Q_PAD_EIM_D20__UART1_RTS */ ++ >; ++ }; ++ ++ pinctrl_uart1_3: uart1grp-3 { ++ fsl,pins = < ++ 1242 0x1b0b1 /* MX6Q_PAD_SD3_DAT7__UART1_TXD */ ++ 1250 0x1b0b1 /* MX6Q_PAD_SD3_DAT6__UART1_RXD */ ++ >; ++ }; ++ pinctrl_uart1_4: uart1-grp-4 { ++ fsl,pins = < ++ 1290 0x1b0b1 /* MX6Q_PAD_SD3_DAT0__UART1_CTS */ ++ 1298 0x1b0b1 /* MX6Q_PAD_SD3_DAT1__UART1_RTS */ ++ >; ++ }; ++ }; ++ ++ uart2 { ++ pinctrl_uart2_1: uart2grp-1 { ++ fsl,pins = < ++ 183 0x1b0b1 /* MX6Q_PAD_EIM_D26__UART2_TXD */ ++ 191 0x1b0b1 /* MX6Q_PAD_EIM_D27__UART2_RXD */ ++ >; ++ }; ++ pinctrl_uart2_2: uart2grp-2 { ++ fsl,pins = < ++ 199 0x1b0b1 /* MX6Q_PAD_EIM_D28__UART2_CTS */ ++ 206 0x1b0b1 /* MX6Q_PAD_EIM_D29__UART2_RTS */ ++ >; ++ }; ++ ++ pinctrl_uart2_3: uart2grp-3 { ++ fsl,pins = < ++ 1258 0x1b0b1 /* MX6Q_PAD_SD3_DAT5__UART2_TXD */ ++ 1266 0x1b0b1 /* MX6Q_PAD_SD3_DAT6__UART2_RXD */ ++ >; ++ }; ++ pinctrl_uart2_4: uart2grp-4 { ++ fsl,pins = < ++ 1274 0x1b0b1 /* MX6Q_PAD_SD3_CMD__UART2_CTS */ ++ 1282 0x1b0b1 /* MX6Q_PAD_SD3_CLK__UART2_RTS */ ++ >; ++ }; ++ ++ pinctrl_uart2_5: uart2grp-5 { ++ fsl,pins = < ++ 1518 0x1b0b1 /* MX6Q_PAD_SD4_DAT7__UART2_TXD */ ++ 1494 0x1b0b1 /* MX6Q_PAD_SD4_DAT4__UART2_RXD */ ++ >; ++ }; ++ pinctrl_uart2_6: uart2grp-6 { ++ fsl,pins = < ++ 1510 0x1b0b1 /* MX6Q_PAD_SD4_DAT6__UART2_CTS */ ++ 1502 0x1b0b1 /* MX6Q_PAD_SD4_DAT5__UART2_RTS */ ++ >; ++ }; ++ ++ pinctrl_uart2_7: uart2grp-7 { ++ fsl,pins = < ++ 1019 0x1b0b1 /* MX6Q_PAD_GPIO_7__UART2_TXD */ ++ 1027 0x1b0b1 /* MX6Q_PAD_GPIO_8__UART2_RXD */ ++ >; ++ }; ++ }; ++ ++ uart3 { ++ pinctrl_uart3_1: uart3grp-1 { ++ fsl,pins = < ++ 165 0x1b0b1 /* MX6Q_PAD_EIM_D24__UART3_TXD */ ++ 173 0x1b0b1 /* MX6Q_PAD_EIM_D25__UART3_RXD */ ++ >; ++ }; ++ pinctrl_uart3_2: uart3grp-2 { ++ fsl,pins = < ++ 149 0x1b0b1 /* MX6Q_PAD_EIM_D23__UART3_CTS */ ++ 157 0x1b0b1 /* MX6Q_PAD_EIM_EB3__UART3_RTS */ ++ >; ++ }; ++ ++ pinctrl_uart3_3: uart3grp-3 { ++ fsl,pins = < ++ 1388 0x1b0b1 /* MX6Q_PAD_SD4_CMD__UART3_TXD */ ++ 1394 0x1b0b1 /* MX6Q_PAD_SD4_CLK__UART3_RXD */ ++ >; ++ }; ++ pinctrl_uart3_4: uart3grp-4 { ++ fsl,pins = < ++ 1313 0x1b0b1 /* MX6Q_PAD_SD3_DAT3__UART3_CTS */ ++ 1321 0x1b0b1 /* MX6Q_PAD_SD3_RST__UART3_RTS */ ++ >; ++ }; ++ ++ pinctrl_uart3_5: uart3grp-5 { ++ fsl,pins = < ++ 214 0x1b0b1 /* MX6Q_PAD_EIM_D30__UART3_CTS */ ++ 222 0x1b0b1 /* MX6Q_PAD_EIM_D31__UART3_RTS */ ++ >; ++ }; ++ }; ++ ++ uart4 { ++ pinctrl_uart4_1: uart4grp-1 { ++ fsl,pins = < ++ 877 0x1b0b1 /* MX6Q_PAD_KEY_COL0__UART4_TXD */ ++ 885 0x1b0b1 /* MX6Q_PAD_KEY_ROW0__UART4_RXD */ ++ >; ++ }; ++ }; ++ ++ usbotg { ++ pinctrl_usbotg_1: usbotggrp-1 { ++ fsl,pins = < ++ 1592 0x17059 /* MX6Q_PAD_GPIO_1__ANATOP_USBOTG_ID */ ++ >; ++ }; ++ }; ++ ++ usdhc1 { ++ pinctrl_usdhc1_1: usdhc1grp-1 { ++ fsl,pins = < ++ 1548 0x17059 /* MX6Q_PAD_SD1_CMD__USDHC1_CMD */ ++ 1562 0x10059 /* MX6Q_PAD_SD1_CLK__USDHC1_CLK */ ++ 1532 0x17059 /* MX6Q_PAD_SD1_DAT0__USDHC1_DAT0 */ ++ 1524 0x17059 /* MX6Q_PAD_SD1_DAT1__USDHC1_DAT1 */ ++ 1554 0x17059 /* MX6Q_PAD_SD1_DAT2__USDHC1_DAT2 */ ++ 1540 0x17059 /* MX6Q_PAD_SD1_DAT3__USDHC1_DAT3 */ ++ 1398 0x17059 /* MX6Q_PAD_NANDF_D0__USDHC1_DAT4 */ ++ 1406 0x17059 /* MX6Q_PAD_NANDF_D1__USDHC1_DAT5 */ ++ 1414 0x17059 /* MX6Q_PAD_NANDF_D2__USDHC1_DAT6 */ ++ 1422 0x17059 /* MX6Q_PAD_NANDF_D3__USDHC1_DAT7 */ ++ >; ++ }; ++ ++ pinctrl_usdhc1_2: usdhc1grp-2 { ++ fsl,pins = < ++ 1548 0x17059 /* MX6Q_PAD_SD1_CMD__USDHC1_CMD */ ++ 1562 0x10059 /* MX6Q_PAD_SD1_CLK__USDHC1_CLK */ ++ 1532 0x17059 /* MX6Q_PAD_SD1_DAT0__USDHC1_DAT0 */ ++ 1524 0x17059 /* MX6Q_PAD_SD1_DAT1__USDHC1_DAT1 */ ++ 1554 0x17059 /* MX6Q_PAD_SD1_DAT2__USDHC1_DAT2 */ ++ 1540 0x17059 /* MX6Q_PAD_SD1_DAT3__USDHC1_DAT3 */ ++ >; ++ }; ++ }; ++ ++ usdhc2 { ++ pinctrl_usdhc2_1: usdhc2grp-1 { ++ fsl,pins = < ++ 1577 0x17059 /* MX6Q_PAD_SD2_CMD__USDHC2_CMD */ ++ 1569 0x10059 /* MX6Q_PAD_SD2_CLK__USDHC2_CLK */ ++ 16 0x17059 /* MX6Q_PAD_SD2_DAT0__USDHC2_DAT0 */ ++ 0 0x17059 /* MX6Q_PAD_SD2_DAT1__USDHC2_DAT1 */ ++ 8 0x17059 /* MX6Q_PAD_SD2_DAT2__USDHC2_DAT2 */ ++ 1583 0x17059 /* MX6Q_PAD_SD2_DAT3__USDHC2_DAT3 */ ++ 1430 0x17059 /* MX6Q_PAD_NANDF_D4__USDHC2_DAT4 */ ++ 1438 0x17059 /* MX6Q_PAD_NANDF_D5__USDHC2_DAT5 */ ++ 1446 0x17059 /* MX6Q_PAD_NANDF_D6__USDHC2_DAT6 */ ++ 1454 0x17059 /* MX6Q_PAD_NANDF_D7__USDHC2_DAT7 */ ++ >; ++ }; ++ ++ pinctrl_usdhc2_2: usdhc2grp-2 { ++ fsl,pins = < ++ 1577 0x17059 /* MX6Q_PAD_SD2_CMD__USDHC2_CMD */ ++ 1569 0x10059 /* MX6Q_PAD_SD2_CLK__USDHC2_CLK */ ++ 16 0x17059 /* MX6Q_PAD_SD2_DAT0__USDHC2_DAT0 */ ++ 0 0x17059 /* MX6Q_PAD_SD2_DAT1__USDHC2_DAT1 */ ++ 8 0x17059 /* MX6Q_PAD_SD2_DAT2__USDHC2_DAT2 */ ++ 1583 0x17059 /* MX6Q_PAD_SD2_DAT3__USDHC2_DAT3 */ ++ >; ++ }; ++ }; ++ ++ usdhc3 { ++ pinctrl_usdhc3_1: usdhc3grp-1 { ++ fsl,pins = < ++ 1273 0x17059 /* MX6Q_PAD_SD3_CMD__USDHC3_CMD */ ++ 1281 0x10059 /* MX6Q_PAD_SD3_CLK__USDHC3_CLK */ ++ 1289 0x17059 /* MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 */ ++ 1297 0x17059 /* MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 */ ++ 1305 0x17059 /* MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 */ ++ 1312 0x17059 /* MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 */ ++ 1265 0x17059 /* MX6Q_PAD_SD3_DAT4__USDHC3_DAT4 */ ++ 1257 0x17059 /* MX6Q_PAD_SD3_DAT5__USDHC3_DAT5 */ ++ 1249 0x17059 /* MX6Q_PAD_SD3_DAT6__USDHC3_DAT6 */ ++ 1241 0x17059 /* MX6Q_PAD_SD3_DAT7__USDHC3_DAT7 */ ++ >; ++ }; ++ ++ pinctrl_usdhc3_2: usdhc3grp-2 { ++ fsl,pins = < ++ 1273 0x17059 /* MX6Q_PAD_SD3_CMD__USDHC3_CMD */ ++ 1281 0x10059 /* MX6Q_PAD_SD3_CLK__USDHC3_CLK */ ++ 1289 0x17059 /* MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 */ ++ 1297 0x17059 /* MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 */ ++ 1305 0x17059 /* MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 */ ++ 1312 0x17059 /* MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 */ ++ >; ++ }; ++ }; ++ ++ usdhc4 { ++ pinctrl_usdhc4_1: usdhc4grp-1 { ++ fsl,pins = < ++ 1386 0x17059 /* MX6Q_PAD_SD4_CMD__USDHC4_CMD */ ++ 1392 0x10059 /* MX6Q_PAD_SD4_CLK__USDHC4_CLK */ ++ 1462 0x17059 /* MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 */ ++ 1470 0x17059 /* MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 */ ++ 1478 0x17059 /* MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 */ ++ 1486 0x17059 /* MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 */ ++ 1493 0x17059 /* MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 */ ++ 1501 0x17059 /* MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 */ ++ 1509 0x17059 /* MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 */ ++ 1517 0x17059 /* MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 */ ++ >; ++ }; ++ ++ pinctrl_usdhc4_2: usdhc4grp-2 { ++ fsl,pins = < ++ 1386 0x17059 /* MX6Q_PAD_SD4_CMD__USDHC4_CMD */ ++ 1392 0x10059 /* MX6Q_PAD_SD4_CLK__USDHC4_CLK */ ++ 1462 0x17059 /* MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 */ ++ 1470 0x17059 /* MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 */ ++ 1478 0x17059 /* MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 */ ++ 1486 0x17059 /* MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 */ ++ >; ++ }; ++ }; ++ }; ++ }; ++ ++ ipu2: ipu@02800000 { ++ #crtc-cells = <1>; ++ compatible = "fsl,imx6q-ipu"; ++ reg = <0x02800000 0x400000>; ++ interrupts = <0 8 0x4 0 7 0x4>; ++ clocks = <&clks 133>, <&clks 134>, <&clks 137>; ++ clock-names = "bus", "di0", "di1"; ++ }; ++ }; ++}; diff --cc arch/arm/imx-common/cpu.c index 9aad798c1e,a9b86c1173..a02f2e75c0 --- a/arch/arm/imx-common/cpu.c +++ b/arch/arm/imx-common/cpu.c @@@ -64,23 -65,75 +64,75 @@@ char *get_reset_cause(void } } -#if defined(CONFIG_MX53) || defined(CONFIG_MX6) ++#if defined(CONFIG_MX53) || defined(CONFIG_MX6Q) + #if defined(CONFIG_MX53) + #define MEMCTL_BASE ESDCTL_BASE_ADDR; + #else + #define MEMCTL_BASE MMDC_P0_BASE_ADDR; + #endif + static const unsigned char col_lookup[] = {9, 10, 11, 8, 12, 9, 9, 9}; + static const unsigned char bank_lookup[] = {3, 2}; + + struct esd_mmdc_regs { + uint32_t ctl; + uint32_t pdc; + uint32_t otc; + uint32_t cfg0; + uint32_t cfg1; + uint32_t cfg2; + uint32_t misc; + uint32_t scr; + uint32_t ref; + uint32_t rsvd1; + uint32_t rsvd2; + uint32_t rwd; + uint32_t or; + uint32_t mrr; + uint32_t cfg3lp; + uint32_t mr4; + }; + + #define ESD_MMDC_CTL_GET_ROW(mdctl) ((ctl >> 24) & 7) + #define ESD_MMDC_CTL_GET_COLUMN(mdctl) ((ctl >> 20) & 7) + #define ESD_MMDC_CTL_GET_WIDTH(mdctl) ((ctl >> 16) & 3) + #define ESD_MMDC_CTL_GET_CS1(mdctl) ((ctl >> 30) & 1) + #define ESD_MMDC_MISC_GET_BANK(mdmisc) ((misc >> 5) & 1) + + unsigned imx_ddr_size(void) + { + struct esd_mmdc_regs *mem = (struct esd_mmdc_regs *)MEMCTL_BASE; + unsigned ctl = readl(&mem->ctl); + unsigned misc = readl(&mem->misc); + int bits = 11 + 0 + 0 + 1; /* row + col + bank + width */ + + bits += ESD_MMDC_CTL_GET_ROW(ctl); + bits += col_lookup[ESD_MMDC_CTL_GET_COLUMN(ctl)]; + bits += bank_lookup[ESD_MMDC_MISC_GET_BANK(misc)]; + bits += ESD_MMDC_CTL_GET_WIDTH(ctl); + bits += ESD_MMDC_CTL_GET_CS1(ctl); + return 1 << bits; + } + #endif + #if defined(CONFIG_DISPLAY_CPUINFO) - static char *get_imx_type(u32 imxtype) + const char *get_imx_type(u32 imxtype) { switch (imxtype) { - case 0x63: + case MXC_CPU_MX6Q: return "6Q"; /* Quad-core version of the mx6 */ - case 0x61: - return "6DS"; /* Dual/Solo version of the mx6 */ - case 0x60: + case MXC_CPU_MX6DL: + return "6DL"; /* Dual Lite version of the mx6 */ + case MXC_CPU_MX6SOLO: + return "6SOLO"; /* Solo version of the mx6 */ + case MXC_CPU_MX6SL: return "6SL"; /* Solo-Lite version of the mx6 */ - case 0x51: + case MXC_CPU_MX51: return "51"; - case 0x53: + case MXC_CPU_MX53: return "53"; default: - return "unknown"; + return "??"; } } diff --cc arch/arm/imx-common/iomux-v3.c index 8785532163,08fad7851c..2831964d6d --- a/arch/arm/imx-common/iomux-v3.c +++ b/arch/arm/imx-common/iomux-v3.c @@@ -49,7 -48,7 +48,7 @@@ int imx_iomux_v3_setup_pad(iomux_v3_cfg if (sel_input_ofs) __raw_writel(sel_input, base + sel_input_ofs); -- if (!(pad_ctrl & NO_PAD_CTRL) && pad_ctrl_ofs) ++ if ((pad & PAD_CTRL_VALID) && pad_ctrl_ofs) __raw_writel(pad_ctrl, base + pad_ctrl_ofs); return 0; @@@ -62,6 -62,6 +62,21 @@@ int imx_iomux_v3_setup_multiple_pads(io int ret; for (i = 0; i < count; i++) { ++#if 0 ++ u32 mux_ctrl_ofs = (*p & MUX_CTRL_OFS_MASK) >> MUX_CTRL_OFS_SHIFT; ++ u32 mux_mode = (*p & MUX_MODE_MASK) >> MUX_MODE_SHIFT; ++ u32 sel_input_ofs = ++ (*p & MUX_SEL_INPUT_OFS_MASK) >> MUX_SEL_INPUT_OFS_SHIFT; ++ u32 sel_input = ++ (*p & MUX_SEL_INPUT_MASK) >> MUX_SEL_INPUT_SHIFT; ++ u32 pad_ctrl_ofs = ++ (*p & MUX_PAD_CTRL_OFS_MASK) >> MUX_PAD_CTRL_OFS_SHIFT; ++ u32 pad_ctrl = (*p & MUX_PAD_CTRL_MASK) >> MUX_PAD_CTRL_SHIFT; ++ ++ printf("PAD[%2d]=%016llx mux[%03x]=%02x pad[%03x]=%05x%c inp[%03x]=%d\n", ++ i, *p, mux_ctrl_ofs, mux_mode, pad_ctrl_ofs, pad_ctrl, ++ *p & PAD_CTRL_VALID ? ' ' : '!', sel_input_ofs, sel_input); ++#endif ret = imx_iomux_v3_setup_pad(*p); if (ret) return ret; diff --cc arch/arm/imx-common/timer.c index 39d2862a01,ab37d641ec..b2ce8fee17 --- a/arch/arm/imx-common/timer.c +++ b/arch/arm/imx-common/timer.c @@@ -27,7 -27,8 +27,10 @@@ #include #include #include + #include + ++#define DEBUG_TIMER_WRAP + /* General purpose timers registers */ struct mxc_gpt { unsigned int control; @@@ -42,53 -43,28 +45,64 @@@ static struct mxc_gpt *cur_gpt = (struc /* General purpose timers bitfields */ #define GPTCR_SWR (1 << 15) /* Software reset */ #define GPTCR_FRR (1 << 9) /* Freerun / restart */ -#define GPTCR_CLKSOURCE_32 (4 << 6) /* Clock source */ +#define GPTCR_CLKSOURCE_IPG (1 << 6) /* Clock source */ +#define GPTCR_CLKSOURCE_CKIH (2 << 6) +#define GPTCR_CLKSOURCE_32kHz (4 << 6) ++#ifdef CONFIG_MX6Q ++#define GPTCR_CLKSOURCE_OSC_DIV_8 (5 << 6) ++#define GPTCR_CLKSOURCE_OSC (7 << 6) ++#else +#define GPTCR_CLKSOURCE_OSC (5 << 6) ++#endif +#define GPTCR_CLKSOURCE_MASK (7 << 6) #define GPTCR_TEN 1 /* Timer enable */ ++#if 1 ++#define GPT_CLKSOURCE GPTCR_CLKSOURCE_OSC ++#define GPT_REFCLK 24000000 ++#define GPT_PRESCALER 24 ++#else +#define GPT_CLKSOURCE GPTCR_CLKSOURCE_32kHz +#define GPT_REFCLK 32768 +#define GPT_PRESCALER 1 ++#endif +#define GPT_CLK (GPT_REFCLK / GPT_PRESCALER) + +#ifdef DEBUG_TIMER_WRAP +/* + * Let the timer wrap 30 seconds after start to catch misbehaving + * timer related code early + */ +#define TIMER_START (-time_to_tick(30 * CONFIG_SYS_HZ)) +#else +#define TIMER_START 0UL +#endif + DECLARE_GLOBAL_DATA_PTR; -#define timestamp (gd->arch.tbl) -#define lastinc (gd->arch.lastinc) +static inline unsigned long tick_to_time(unsigned long tick) +{ + unsigned long long t = (unsigned long long)tick * CONFIG_SYS_HZ; + do_div(t, GPT_CLK); + return t; +} -static inline unsigned long long tick_to_time(unsigned long long tick) +static inline unsigned long time_to_tick(unsigned long time) { - tick *= CONFIG_SYS_HZ; - do_div(tick, MXC_CLK32); + unsigned long long ticks = (unsigned long long)time; - return tick; + ticks *= GPT_CLK; + do_div(ticks, CONFIG_SYS_HZ); + return ticks; } -static inline unsigned long long us_to_tick(unsigned long long usec) +static inline unsigned long us_to_tick(unsigned long usec) { - usec = usec * MXC_CLK32 + 999999; - do_div(usec, 1000000); + unsigned long long ticks = (unsigned long long)usec; - return usec; + ticks *= GPT_CLK; + do_div(ticks, 1000 * CONFIG_SYS_HZ); + return ticks; } int timer_init(void) @@@ -103,18 -79,15 +117,18 @@@ for (i = 0; i < 100; i++) __raw_writel(0, &cur_gpt->control); - __raw_writel(0, &cur_gpt->prescaler); - __raw_writel(0, &cur_gpt->prescaler); /* 32Khz */ ++ __raw_writel(GPT_PRESCALER - 1, &cur_gpt->prescaler); /* Freerun Mode, PERCLK1 input */ i = __raw_readl(&cur_gpt->control); - __raw_writel(i | GPTCR_CLKSOURCE_32 | GPTCR_TEN, &cur_gpt->control); + i &= ~GPTCR_CLKSOURCE_MASK; + __raw_writel(i | GPT_CLKSOURCE | GPTCR_TEN, &cur_gpt->control); val = __raw_readl(&cur_gpt->counter); - gd->lastinc = val; - gd->tbu = 0; - gd->tbl = TIMER_START; - gd->timer_rate_hz = GPT_CLK; - lastinc = val / (MXC_CLK32 / CONFIG_SYS_HZ); - timestamp = 0; ++ gd->arch.lastinc = val; ++ gd->arch.tbu = 0; ++ gd->arch.tbl = TIMER_START; ++ gd->arch.timer_rate_hz = GPT_CLK; return 0; } @@@ -122,11 -95,19 +136,11 @@@ unsigned long long get_ticks(void) { ulong now = __raw_readl(&cur_gpt->counter); /* current tick value */ - ulong inc = now - gd->lastinc; ++ ulong inc = now - gd->arch.lastinc; - gd->tbl += inc; - gd->lastinc = now; - return gd->tbl; - if (now >= lastinc) { - /* - * normal mode (non roll) - * move stamp forward with absolut diff ticks - */ - timestamp += (now - lastinc); - } else { - /* we have rollover of incrementer */ - timestamp += (0xFFFFFFFF - lastinc) + now; - } - lastinc = now; - return timestamp; ++ gd->arch.tbl += inc; ++ gd->arch.lastinc = now; ++ return gd->arch.tbl; } ulong get_timer_masked(void) @@@ -149,9 -123,9 +163,11 @@@ ulong get_timer(ulong base) { - return get_timer_masked() - base; + return tick_to_time(get_ticks() - time_to_tick(base)); } ++#include ++ /* delay x useconds AND preserve advance timstamp value */ void __udelay(unsigned long usec) { @@@ -175,5 -145,5 +191,5 @@@ */ ulong get_tbclk(void) { - return gd->timer_rate_hz; - return MXC_CLK32; ++ return gd->arch.timer_rate_hz; } diff --cc arch/arm/include/asm/arch-am33xx/clocks_am33xx.h index 1c28fce729,d748dd2787..aae804f336 --- a/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h +++ b/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h @@@ -19,21 -19,16 +19,20 @@@ #ifndef _CLOCKS_AM33XX_H_ #define _CLOCKS_AM33XX_H_ - #define OSC 24 + #define OSC (V_OSCK/1000000) - /* MAIN PLL */ +#ifndef CONFIG_SYS_MPU_CLK - /* default to 500 MHz */ - #define MPUPLL_M 500 + /* MAIN PLL Fdll = 550 MHZ, */ + #define MPUPLL_M 550 -#define MPUPLL_N (OSC-1) +#else +#define MPUPLL_M CONFIG_SYS_MPU_CLK +#endif - #define MPUPLL_N 23 ++#define MPUPLL_N (OSC - 1) #define MPUPLL_M2 1 /* Core PLL Fdll = 1 GHZ, */ #define COREPLL_M 1000 - #define COREPLL_N 23 -#define COREPLL_N (OSC-1) ++#define COREPLL_N (OSC - 1) #define COREPLL_M4 10 /* CORE_CLKOUTM4 = 200 MHZ */ #define COREPLL_M5 8 /* CORE_CLKOUTM5 = 250 MHZ */ @@@ -45,23 -40,15 +44,23 @@@ * For clkout = 192 MHZ, Fdll = 960 MHZ, divider values are given below */ #define PERPLL_M 960 - #define PERPLL_N 23 -#define PERPLL_N (OSC-1) ++#define PERPLL_N (OSC - 1) #define PERPLL_M2 5 /* DDR Freq is 266 MHZ for now */ /* Set Fdll = 400 MHZ , Fdll = M * 2 * CLKINP/ N + 1; clkout = Fdll /(2 * M2) */ +#ifndef CONFIG_SYS_DDR_CLK #define DDRPLL_M 266 -#define DDRPLL_N (OSC-1) +#else +#define DDRPLL_M CONFIG_SYS_DDR_CLK +#endif - #define DDRPLL_N 23 ++#define DDRPLL_N (OSC - 1) #define DDRPLL_M2 1 +#define DISPPLL_M 200 - #define DISPPLL_N 23 ++#define DISPPLL_N (OSC - 1) +#define DISPPLL_M2 1 + extern void pll_init(void); extern void enable_emif_clocks(void); diff --cc arch/arm/include/asm/arch-am33xx/cpu.h index 963b01fb2b,16e8a80700..f10cffb292 --- a/arch/arm/include/asm/arch-am33xx/cpu.h +++ b/arch/arm/include/asm/arch-am33xx/cpu.h @@@ -47,13 -47,16 +47,14 @@@ #define DEVICE_ID 0x44E10600 /* This gives the status of the boot mode pins on the evm */ -#define SYSBOOT_MASK (BIT(0) | BIT(1) | BIT(2)\ - | BIT(3) | BIT(4)) +#define SYSBOOT_MASK (BIT(0) | BIT(1) | BIT(2) | \ + BIT(3) | BIT(4)) /* Reset control */ -#ifdef CONFIG_AM33XX #define PRM_RSTCTRL 0x44E00F00 #define PRM_RSTST 0x44E00F08 -#endif #define PRM_RSTCTRL_RESET 0x01 + #define PRM_RSTST_WARM_RESET_MASK 0x232 #ifndef __KERNEL_STRICT_NAMES #ifndef __ASSEMBLY__ @@@ -113,9 -167,10 +168,10 @@@ struct cm_perpll unsigned int l3clkstctrl; /* offset 0x0c */ unsigned int resv1; unsigned int cpgmac0clkctrl; /* offset 0x14 */ - unsigned int lcdcclkctrl; /* offset 0x18 */ + unsigned int lcdclkctrl; /* offset 0x18 */ - unsigned int usb0clkctrl; /* offset 0x1C */ + unsigned int usb0clkctrl; /* offset 0x1c */ - unsigned int resv2[2]; + unsigned int resv2; + unsigned int tptc0clkctrl; /* offset 0x24 */ unsigned int emifclkctrl; /* offset 0x28 */ unsigned int ocmcramclkctrl; /* offset 0x2c */ unsigned int gpmcclkctrl; /* offset 0x30 */ @@@ -227,68 -303,44 +304,55 @@@ struct vtp_reg struct ctrl_stat { unsigned int resv1[16]; unsigned int statusreg; /* ofset 0x40 */ + unsigned int resv2[51]; + unsigned int secure_emif_sdram_config; /* offset 0x0110 */ }; - struct gpmc_cs { - u32 config1; /* 0x00 */ - u32 config2; /* 0x04 */ - u32 config3; /* 0x08 */ - u32 config4; /* 0x0C */ - u32 config5; /* 0x10 */ - u32 config6; /* 0x14 */ - u32 config7; /* 0x18 */ - u32 nand_cmd; /* 0x1C */ - u32 nand_adr; /* 0x20 */ - u32 nand_dat; /* 0x24 */ - u8 res[8]; /* blow up to 0x30 byte */ - }; + /* AM33XX GPIO registers */ + #define OMAP_GPIO_REVISION 0x0000 + #define OMAP_GPIO_SYSCONFIG 0x0010 + #define OMAP_GPIO_SYSSTATUS 0x0114 + #define OMAP_GPIO_IRQSTATUS1 0x002c + #define OMAP_GPIO_IRQSTATUS2 0x0030 + #define OMAP_GPIO_CTRL 0x0130 + #define OMAP_GPIO_OE 0x0134 + #define OMAP_GPIO_DATAIN 0x0138 + #define OMAP_GPIO_DATAOUT 0x013c + #define OMAP_GPIO_LEVELDETECT0 0x0140 + #define OMAP_GPIO_LEVELDETECT1 0x0144 + #define OMAP_GPIO_RISINGDETECT 0x0148 + #define OMAP_GPIO_FALLINGDETECT 0x014c + #define OMAP_GPIO_DEBOUNCE_EN 0x0150 + #define OMAP_GPIO_DEBOUNCE_VAL 0x0154 + #define OMAP_GPIO_CLEARDATAOUT 0x0190 + #define OMAP_GPIO_SETDATAOUT 0x0194 - struct bch_res_0_3 { - u32 bch_result_x[4]; - }; - - - - struct gpmc { - u8 res1[0x10]; - u32 sysconfig; /* 0x10 */ - u8 res2[0x4]; - u32 irqstatus; /* 0x18 */ - u32 irqenable; /* 0x1C */ - u8 res3[0x20]; - u32 timeout_control; /* 0x40 */ - u8 res4[0xC]; - u32 config; /* 0x50 */ - u32 status; /* 0x54 */ - u8 res5[0x8]; /* 0x58 */ - struct gpmc_cs cs[8]; /* 0x60, 0x90, .. */ - u8 res6[0x14]; /* 0x1E0 */ - u32 ecc_config; /* 0x1F4 */ - u32 ecc_control; /* 0x1F8 */ - u32 ecc_size_config; /* 0x1FC */ - u32 ecc1_result; /* 0x200 */ - u32 ecc2_result; /* 0x204 */ - u32 ecc3_result; /* 0x208 */ - u32 ecc4_result; /* 0x20C */ - u32 ecc5_result; /* 0x210 */ - u32 ecc6_result; /* 0x214 */ - u32 ecc7_result; /* 0x218 */ - u32 ecc8_result; /* 0x21C */ - u32 ecc9_result; /* 0x220 */ - u8 res7[12]; /* 0x224 */ - u32 testmomde_ctrl; /* 0x230 */ - u8 res8[12]; /* 0x234 */ - struct bch_res_0_3 bch_result_0_3[2]; /* 0x240 */ + /* Control Device Register */ + struct ctrl_dev { + unsigned int deviceid; /* offset 0x00 */ + unsigned int resv1[7]; + unsigned int usb_ctrl0; /* offset 0x20 */ + unsigned int resv2; + unsigned int usb_ctrl1; /* offset 0x28 */ + unsigned int resv3; + unsigned int macid0l; /* offset 0x30 */ + unsigned int macid0h; /* offset 0x34 */ + unsigned int macid1l; /* offset 0x38 */ + unsigned int macid1h; /* offset 0x3c */ + unsigned int resv4[4]; + unsigned int miisel; /* offset 0x50 */ }; + +void init_timer(void); + +#define clk_get_rate(c,p) \ + __clk_get_rate(readl(&(c)->clkseldpll##p), \ + readl(&(c)->divm2dpll##p)) + +unsigned long __clk_get_rate(u32 m_n, u32 div_m2); + ++unsigned long lcdc_clk_rate(void); ++ #endif /* __ASSEMBLY__ */ #endif /* __KERNEL_STRICT_NAMES */ diff --cc arch/arm/include/asm/arch-am33xx/gpio.h index 51f8541c11,1a211e95e8..173097ca8d --- a/arch/arm/include/asm/arch-am33xx/gpio.h +++ b/arch/arm/include/asm/arch-am33xx/gpio.h @@@ -10,12 -10,20 +10,22 @@@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * */ - #ifndef _GPIO_AM33XX_H - #define _GPIO_AM33XX_H + #ifndef _GPIO_AM33xx_H + #define _GPIO_AM33xx_H + + #include - #include + #define AM33XX_GPIO0_BASE 0x44E07000 + #define AM33XX_GPIO1_BASE 0x4804C000 + #define AM33XX_GPIO2_BASE 0x481AC000 + #define AM33XX_GPIO3_BASE 0x481AE000 +#define AM33XX_GPIO_NR(bank, pin) (((bank) << 5) | (pin)) + - #endif /* _GPIO_AM33XX_H */ + #endif /* _GPIO_AM33xx_H */ diff --cc arch/arm/include/asm/arch-am33xx/hardware.h index e620ab3548,6dd3296907..8d689282ad --- a/arch/arm/include/asm/arch-am33xx/hardware.h +++ b/arch/arm/include/asm/arch-am33xx/hardware.h @@@ -19,9 -19,9 +19,10 @@@ #ifndef __AM33XX_HARDWARE_H #define __AM33XX_HARDWARE_H + #include + /* Module base addresses */ +#define LOW_LEVEL_SRAM_STACK 0x4030B7FC - #define SRAM0_START 0x402F0400 #define UART0_BASE 0x44E09000 /* DM Timer base addresses */ @@@ -34,12 -34,11 +35,6 @@@ #define DM_TIMER6_BASE 0x48048000 #define DM_TIMER7_BASE 0x4804A000 --/* GPIO Base address */ - #define GPIO0_BASE 0x44E07000 -#define GPIO0_BASE 0x48032000 --#define GPIO1_BASE 0x4804C000 --#define GPIO2_BASE 0x481AC000 - #define GPIO3_BASE 0x481AE000 -- /* BCH Error Location Module */ #define ELM_BASE 0x48080000 diff --cc arch/arm/include/asm/arch-am33xx/mmc_host_def.h index b387237ee0,1f597c0eec..06405b6769 --- a/arch/arm/include/asm/arch-am33xx/mmc_host_def.h +++ b/arch/arm/include/asm/arch-am33xx/mmc_host_def.h @@@ -19,32 -19,31 +19,32 @@@ /* * OMAP HSMMC register definitions */ -#define OMAP_HSMMC1_BASE 0x48060100 -#define OMAP_HSMMC2_BASE 0x481D8100 +#define OMAP_HSMMC1_BASE 0x48060000 +#define OMAP_HSMMC2_BASE 0x481D8000 +#define OMAP_HSMMC3_BASE 0x47810000 typedef struct hsmmc { - unsigned char res1[0x110]; - unsigned char res1[0x10]; - unsigned int sysconfig; /* 0x10 */ - unsigned int sysstatus; /* 0x14 */ - unsigned char res2[0x14]; - unsigned int con; /* 0x2C */ - unsigned char res3[0xD4]; - unsigned int blk; /* 0x104 */ - unsigned int arg; /* 0x108 */ - unsigned int cmd; /* 0x10C */ - unsigned int rsp10; /* 0x110 */ - unsigned int rsp32; /* 0x114 */ - unsigned int rsp54; /* 0x118 */ - unsigned int rsp76; /* 0x11C */ - unsigned int data; /* 0x120 */ - unsigned int pstate; /* 0x124 */ - unsigned int hctl; /* 0x128 */ - unsigned int sysctl; /* 0x12C */ - unsigned int stat; /* 0x130 */ - unsigned int ie; /* 0x134 */ - unsigned char res4[0x8]; - unsigned int capa; /* 0x140 */ ++ unsigned int res1[0x110 / 4]; + unsigned int sysconfig; /* 0x110 */ + unsigned int sysstatus; /* 0x114 */ - unsigned char res2[0x14]; ++ unsigned int res2[0x14 / 4]; + unsigned int con; /* 0x12C */ - unsigned char res3[0xD4]; ++ unsigned int res3[0xD4 / 4]; + unsigned int blk; /* 0x204 */ + unsigned int arg; /* 0x208 */ + unsigned int cmd; /* 0x20C */ + unsigned int rsp10; /* 0x210 */ + unsigned int rsp32; /* 0x214 */ + unsigned int rsp54; /* 0x218 */ + unsigned int rsp76; /* 0x21C */ + unsigned int data; /* 0x220 */ + unsigned int pstate; /* 0x224 */ + unsigned int hctl; /* 0x228 */ + unsigned int sysctl; /* 0x22C */ + unsigned int stat; /* 0x230 */ + unsigned int ie; /* 0x234 */ - unsigned char res4[0x8]; ++ unsigned int res4[2]; + unsigned int capa; /* 0x240 */ } hsmmc_t; /* @@@ -78,7 -77,7 +78,7 @@@ #define DDIR_READ (0x1 << 4) #define MSBS_SGLEBLK (0x0 << 5) #define MSBS_MULTIBLK (0x1 << 5) --#define RSP_TYPE_OFFSET (16) ++#define RSP_TYPE_OFFSET 16 #define RSP_TYPE_MASK (0x3 << 16) #define RSP_TYPE_NORSP (0x0 << 16) #define RSP_TYPE_LGHT136 (0x1 << 16) diff --cc arch/arm/include/asm/arch-exynos/system.h index c85f949da4,42e1d21e53..2ea985aa7f --- a/arch/arm/include/asm/arch-exynos/system.h +++ b/arch/arm/include/asm/arch-exynos/system.h @@@ -24,7 -24,7 +24,7 @@@ #ifndef __ASSEMBLY__ struct exynos4_sysreg { -- unsigned char res1[0x210]; ++ unsigned int res1[0x210 / 4]; unsigned int display_ctrl; unsigned int display_ctrl2; unsigned int camera_control; @@@ -33,7 -33,7 +33,7 @@@ }; struct exynos5_sysreg { -- unsigned char res1[0x214]; ++ unsigned int res1[0x214 / 4]; unsigned int disp1blk_cfg; unsigned int disp2blk_cfg; unsigned int hdcp_e_fuse; @@@ -42,6 -42,7 +42,7 @@@ unsigned int reserved; unsigned int ispblk_cfg; unsigned int usb20phy_cfg; - unsigned char res2[0x29c]; ++ unsigned int res2[0x29c / 4]; unsigned int mipi_dphy; unsigned int dptx_dphy; unsigned int phyclk_sel; diff --cc arch/arm/include/asm/arch-mx5/clock.h index 35ee8155de,9cdfb48a7a..6f676f2160 --- a/arch/arm/include/asm/arch-mx5/clock.h +++ b/arch/arm/include/asm/arch-mx5/clock.h @@@ -36,18 -54,19 +54,68 @@@ enum mxc_clock MXC_DDR_CLK, MXC_NFC_CLK, MXC_PERIPH_CLK, + MXC_I2C_CLK, }; - unsigned int imx_decode_pll(unsigned int pll, unsigned int f_ref); ++ ++struct clk { ++ const char *name; ++ int id; ++ /* Source clock this clk depends on */ ++ struct clk *parent; ++ /* Secondary clock to enable/disable with this clock */ ++ struct clk *secondary; ++ /* Current clock rate */ ++ unsigned long rate; ++ /* Reference count of clock enable/disable */ ++ __s8 usecount; ++ /* Register bit position for clock's enable/disable control. */ ++ u8 enable_shift; ++ /* Register address for clock's enable/disable control. */ ++ void *enable_reg; ++ u32 flags; ++ /* ++ * Function ptr to recalculate the clock's rate based on parent ++ * clock's rate ++ */ ++ void (*recalc) (struct clk *); ++ /* ++ * Function ptr to set the clock to a new rate. The rate must match a ++ * supported rate returned from round_rate. Leave blank if clock is not ++ * programmable ++ */ ++ int (*set_rate) (struct clk *, unsigned long); ++ /* ++ * Function ptr to round the requested clock rate to the nearest ++ * supported rate that is less than or equal to the requested rate. ++ */ ++ unsigned long (*round_rate) (struct clk *, unsigned long); ++ /* ++ * Function ptr to enable the clock. Leave blank if clock can not ++ * be gated. ++ */ ++ int (*enable) (struct clk *); ++ /* ++ * Function ptr to disable the clock. Leave blank if clock can not ++ * be gated. ++ */ ++ void (*disable) (struct clk *); ++ /* Function ptr to set the parent clock of the clock. */ ++ int (*set_parent) (struct clk *, struct clk *); ++}; + u32 imx_get_uartclk(void); u32 imx_get_fecclk(void); unsigned int mxc_get_clock(enum mxc_clock clk); --int mxc_set_clock(u32 ref, u32 freq, u32 clk_type); - void set_usb_phy2_clk(void); ++int mxc_set_clock(u32 ref, u32 freq, enum mxc_clock clk); + void set_usb_phy_clk(void); + void enable_usb_phy1_clk(unsigned char enable); void enable_usb_phy2_clk(unsigned char enable); void set_usboh3_clk(void); void enable_usboh3_clk(unsigned char enable); void mxc_set_sata_internal_clock(void); + int enable_i2c_clk(unsigned char enable, unsigned i2c_num); ++void ipu_clk_enable(void); ++void ipu_clk_disable(void); #endif /* __ASM_ARCH_CLOCK_H */ diff --cc arch/arm/include/asm/arch-mx5/crm_regs.h index 4e0fc1bc1d,ddfab709b5..b4501351e3 --- a/arch/arm/include/asm/arch-mx5/crm_regs.h +++ b/arch/arm/include/asm/arch-mx5/crm_regs.h @@@ -178,36 -283,328 +283,328 @@@ struct mxc_ccm_reg /* Define the bits in register CSCDR1 */ #define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_OFFSET 22 #define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_MASK (0x7 << 22) + #define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED(v) (((v) & 0x7) << 22) + #define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_RD(r) (((r) >> 22) & 0x7) #define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_OFFSET 19 #define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_MASK (0x7 << 19) + #define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF(v) (((v) & 0x7) << 19) + #define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_RD(r) (((r) >> 19) & 0x7) #define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_OFFSET 16 #define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_MASK (0x7 << 16) + #define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED(v) (((v) & 0x7) << 16) + #define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_RD(r) (((r) >> 16) & 0x7) #define MXC_CCM_CSCDR1_PGC_CLK_PODF_OFFSET 14 #define MXC_CCM_CSCDR1_PGC_CLK_PODF_MASK (0x3 << 14) + #define MXC_CCM_CSCDR1_PGC_CLK_PODF(v) (((v) & 0x3) << 14) + #define MXC_CCM_CSCDR1_PGC_CLK_PODF_RD(r) (((r) >> 14) & 0x3) #define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_OFFSET 11 #define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_MASK (0x7 << 11) + #define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF(v) (((v) & 0x7) << 11) + #define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_RD(r) (((r) >> 11) & 0x7) #define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET 8 #define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK (0x7 << 8) + #define MXC_CCM_CSCDR1_USBOH3_CLK_PRED(v) (((v) & 0x7) << 8) + #define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_RD(r) (((r) >> 8) & 0x7) #define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET 6 #define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK (0x3 << 6) + #define MXC_CCM_CSCDR1_USBOH3_CLK_PODF(v) (((v) & 0x3) << 6) + #define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_RD(r) (((r) >> 6) & 0x3) #define MXC_CCM_CSCDR1_UART_CLK_PRED_OFFSET 3 #define MXC_CCM_CSCDR1_UART_CLK_PRED_MASK (0x7 << 3) + #define MXC_CCM_CSCDR1_UART_CLK_PRED(v) (((v) & 0x7) << 3) + #define MXC_CCM_CSCDR1_UART_CLK_PRED_RD(r) (((r) >> 3) & 0x7) #define MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET 0 #define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK 0x7 + #define MXC_CCM_CSCDR1_UART_CLK_PODF(v) ((v) & 0x7) + #define MXC_CCM_CSCDR1_UART_CLK_PODF_RD(r) ((r) & 0x7) /* Define the bits in register CCDR */ --#define MXC_CCM_CCDR_IPU_HS_MASK (0x1 << 17) ++#define MXC_CCM_CCDR_IPU_HS_MASK (0x1 << 21) /* Define the bits in register CCGRx */ #define MXC_CCM_CCGR_CG_MASK 0x3 + #define MXC_CCM_CCGR_CG_OFF 0x0 + #define MXC_CCM_CCGR_CG_RUN_ON 0x1 + #define MXC_CCM_CCGR_CG_ON 0x3 + + #define MXC_CCM_CCGR0_ARM_BUS_OFFSET 0 + #define MXC_CCM_CCGR0_ARM_BUS(v) (((v) & 0x3) << 0) + #define MXC_CCM_CCGR0_ARM_AXI_OFFSET 2 + #define MXC_CCM_CCGR0_ARM_AXI(v) (((v) & 0x3) << 2) + #define MXC_CCM_CCGR0_ARM_DEBUG_OFFSET 4 + #define MXC_CCM_CCGR0_ARM_DEBUG(v) (((v) & 0x3) << 4) + #define MXC_CCM_CCGR0_TZIC_OFFSET 6 + #define MXC_CCM_CCGR0_TZIC(v) (((v) & 0x3) << 6) + #define MXC_CCM_CCGR0_DAP_OFFSET 8 + #define MXC_CCM_CCGR0_DAP(v) (((v) & 0x3) << 8) + #define MXC_CCM_CCGR0_TPIU_OFFSET 10 + #define MXC_CCM_CCGR0_TPIU(v) (((v) & 0x3) << 10) + #define MXC_CCM_CCGR0_CTI2_OFFSET 12 + #define MXC_CCM_CCGR0_CTI2(v) (((v) & 0x3) << 12) + #define MXC_CCM_CCGR0_CTI3_OFFSET 14 + #define MXC_CCM_CCGR0_CTI3(v) (((v) & 0x3) << 14) + #define MXC_CCM_CCGR0_AHBMUX1_OFFSET 16 + #define MXC_CCM_CCGR0_AHBMUX1(v) (((v) & 0x3) << 16) + #define MXC_CCM_CCGR0_AHBMUX2_OFFSET 18 + #define MXC_CCM_CCGR0_AHBMUX2(v) (((v) & 0x3) << 18) + #define MXC_CCM_CCGR0_ROMCP_OFFSET 20 + #define MXC_CCM_CCGR0_ROMCP(v) (((v) & 0x3) << 20) + #define MXC_CCM_CCGR0_ROM_OFFSET 22 + #define MXC_CCM_CCGR0_ROM(v) (((v) & 0x3) << 22) + #define MXC_CCM_CCGR0_AIPS_TZ1_OFFSET 24 + #define MXC_CCM_CCGR0_AIPS_TZ1(v) (((v) & 0x3) << 24) + #define MXC_CCM_CCGR0_AIPS_TZ2_OFFSET 26 + #define MXC_CCM_CCGR0_AIPS_TZ2(v) (((v) & 0x3) << 26) + #define MXC_CCM_CCGR0_AHB_MAX_OFFSET 28 + #define MXC_CCM_CCGR0_AHB_MAX(v) (((v) & 0x3) << 28) + #define MXC_CCM_CCGR0_IIM_OFFSET 30 + #define MXC_CCM_CCGR0_IIM(v) (((v) & 0x3) << 30) + + #define MXC_CCM_CCGR1_TMAX1_OFFSET 0 + #define MXC_CCM_CCGR1_TMAX1(v) (((v) & 0x3) << 0) + #define MXC_CCM_CCGR1_TMAX2_OFFSET 2 + #define MXC_CCM_CCGR1_TMAX2(v) (((v) & 0x3) << 2) + #define MXC_CCM_CCGR1_TMAX3_OFFSET 4 + #define MXC_CCM_CCGR1_TMAX3(v) (((v) & 0x3) << 4) + #define MXC_CCM_CCGR1_UART1_IPG_OFFSET 6 + #define MXC_CCM_CCGR1_UART1_IPG(v) (((v) & 0x3) << 6) + #define MXC_CCM_CCGR1_UART1_PER_OFFSET 8 + #define MXC_CCM_CCGR1_UART1_PER(v) (((v) & 0x3) << 8) + #define MXC_CCM_CCGR1_UART2_IPG_OFFSET 10 + #define MXC_CCM_CCGR1_UART2_IPG(v) (((v) & 0x3) << 10) + #define MXC_CCM_CCGR1_UART2_PER_OFFSET 12 + #define MXC_CCM_CCGR1_UART2_PER(v) (((v) & 0x3) << 12) + #define MXC_CCM_CCGR1_UART3_IPG_OFFSET 14 + #define MXC_CCM_CCGR1_UART3_IPG(v) (((v) & 0x3) << 14) + #define MXC_CCM_CCGR1_UART3_PER_OFFSET 16 + #define MXC_CCM_CCGR1_UART3_PER(v) (((v) & 0x3) << 16) + #define MXC_CCM_CCGR1_I2C1_OFFSET 18 + #define MXC_CCM_CCGR1_I2C1(v) (((v) & 0x3) << 18) + #define MXC_CCM_CCGR1_I2C2_OFFSET 20 + #define MXC_CCM_CCGR1_I2C2(v) (((v) & 0x3) << 20) + #if defined(CONFIG_MX51) + #define MXC_CCM_CCGR1_HSI2C_IPG_OFFSET 22 + #define MXC_CCM_CCGR1_HSI2C_IPG(v) (((v) & 0x3) << 22) + #define MXC_CCM_CCGR1_HSI2C_SERIAL_OFFSET 24 + #define MXC_CCM_CCGR1_HSI2C_SERIAL(v) (((v) & 0x3) << 24) + #elif defined(CONFIG_MX53) + #define MXC_CCM_CCGR1_I2C3_OFFSET 22 + #define MXC_CCM_CCGR1_I2C3(v) (((v) & 0x3) << 22) + #endif + #define MXC_CCM_CCGR1_FIRI_IPG_OFFSET 26 + #define MXC_CCM_CCGR1_FIRI_IPG(v) (((v) & 0x3) << 26) + #define MXC_CCM_CCGR1_FIRI_SERIAL_OFFSET 28 + #define MXC_CCM_CCGR1_FIRI_SERIAL(v) (((v) & 0x3) << 28) + #define MXC_CCM_CCGR1_SCC_OFFSET 30 + #define MXC_CCM_CCGR1_SCC(v) (((v) & 0x3) << 30) + + #if defined(CONFIG_MX51) + #define MXC_CCM_CCGR2_USB_PHY_OFFSET 0 + #define MXC_CCM_CCGR2_USB_PHY(v) (((v) & 0x3) << 0) + #endif + #define MXC_CCM_CCGR2_EPIT1_IPG_OFFSET 2 + #define MXC_CCM_CCGR2_EPIT1_IPG(v) (((v) & 0x3) << 2) + #define MXC_CCM_CCGR2_EPIT1_HF_OFFSET 4 + #define MXC_CCM_CCGR2_EPIT1_HF(v) (((v) & 0x3) << 4) + #define MXC_CCM_CCGR2_EPIT2_IPG_OFFSET 6 + #define MXC_CCM_CCGR2_EPIT2_IPG(v) (((v) & 0x3) << 6) + #define MXC_CCM_CCGR2_EPIT2_HF_OFFSET 8 + #define MXC_CCM_CCGR2_EPIT2_HF(v) (((v) & 0x3) << 8) + #define MXC_CCM_CCGR2_PWM1_IPG_OFFSET 10 + #define MXC_CCM_CCGR2_PWM1_IPG(v) (((v) & 0x3) << 10) + #define MXC_CCM_CCGR2_PWM1_HF_OFFSET 12 + #define MXC_CCM_CCGR2_PWM1_HF(v) (((v) & 0x3) << 12) + #define MXC_CCM_CCGR2_PWM2_IPG_OFFSET 14 + #define MXC_CCM_CCGR2_PWM2_IPG(v) (((v) & 0x3) << 14) + #define MXC_CCM_CCGR2_PWM2_HF_OFFSET 16 + #define MXC_CCM_CCGR2_PWM2_HF(v) (((v) & 0x3) << 16) + #define MXC_CCM_CCGR2_GPT_IPG_OFFSET 18 + #define MXC_CCM_CCGR2_GPT_IPG(v) (((v) & 0x3) << 18) + #define MXC_CCM_CCGR2_GPT_HF_OFFSET 20 + #define MXC_CCM_CCGR2_GPT_HF(v) (((v) & 0x3) << 20) + #define MXC_CCM_CCGR2_OWIRE_OFFSET 22 + #define MXC_CCM_CCGR2_OWIRE(v) (((v) & 0x3) << 22) + #define MXC_CCM_CCGR2_FEC_OFFSET 24 + #define MXC_CCM_CCGR2_FEC(v) (((v) & 0x3) << 24) + #define MXC_CCM_CCGR2_USBOH3_IPG_AHB_OFFSET 26 + #define MXC_CCM_CCGR2_USBOH3_IPG_AHB(v) (((v) & 0x3) << 26) + #define MXC_CCM_CCGR2_USBOH3_60M_OFFSET 28 + #define MXC_CCM_CCGR2_USBOH3_60M(v) (((v) & 0x3) << 28) + #define MXC_CCM_CCGR2_TVE_OFFSET 30 + #define MXC_CCM_CCGR2_TVE(v) (((v) & 0x3) << 30) - #define MXC_CCM_CCGR4_CG5_OFFSET 10 - #define MXC_CCM_CCGR4_CG6_OFFSET 12 - #define MXC_CCM_CCGR5_CG5_OFFSET 10 - #define MXC_CCM_CCGR2_CG14_OFFSET 28 + #define MXC_CCM_CCGR3_ESDHC1_IPG_OFFSET 0 + #define MXC_CCM_CCGR3_ESDHC1_IPG(v) (((v) & 0x3) << 0) + #define MXC_CCM_CCGR3_ESDHC1_PER_OFFSET 2 + #define MXC_CCM_CCGR3_ESDHC1_PER(v) (((v) & 0x3) << 2) + #define MXC_CCM_CCGR3_ESDHC2_IPG_OFFSET 4 + #define MXC_CCM_CCGR3_ESDHC2_IPG(v) (((v) & 0x3) << 4) + #define MXC_CCM_CCGR3_ESDHC2_PER_OFFSET 6 + #define MXC_CCM_CCGR3_ESDHC2_PER(v) (((v) & 0x3) << 6) + #define MXC_CCM_CCGR3_ESDHC3_IPG_OFFSET 8 + #define MXC_CCM_CCGR3_ESDHC3_IPG(v) (((v) & 0x3) << 8) + #define MXC_CCM_CCGR3_ESDHC3_PER_OFFSET 10 + #define MXC_CCM_CCGR3_ESDHC3_PER(v) (((v) & 0x3) << 10) + #define MXC_CCM_CCGR3_ESDHC4_IPG_OFFSET 12 + #define MXC_CCM_CCGR3_ESDHC4_IPG(v) (((v) & 0x3) << 12) + #define MXC_CCM_CCGR3_ESDHC4_PER_OFFSET 14 + #define MXC_CCM_CCGR3_ESDHC4_PER(v) (((v) & 0x3) << 14) + #define MXC_CCM_CCGR3_SSI1_IPG_OFFSET 16 + #define MXC_CCM_CCGR3_SSI1_IPG(v) (((v) & 0x3) << 16) + #define MXC_CCM_CCGR3_SSI1_SSI_OFFSET 18 + #define MXC_CCM_CCGR3_SSI1_SSI(v) (((v) & 0x3) << 18) + #define MXC_CCM_CCGR3_SSI2_IPG_OFFSET 20 + #define MXC_CCM_CCGR3_SSI2_IPG(v) (((v) & 0x3) << 20) + #define MXC_CCM_CCGR3_SSI2_SSI_OFFSET 22 + #define MXC_CCM_CCGR3_SSI2_SSI(v) (((v) & 0x3) << 22) + #define MXC_CCM_CCGR3_SSI3_IPG_OFFSET 24 + #define MXC_CCM_CCGR3_SSI3_IPG(v) (((v) & 0x3) << 24) + #define MXC_CCM_CCGR3_SSI3_SSI_OFFSET 26 + #define MXC_CCM_CCGR3_SSI3_SSI(v) (((v) & 0x3) << 26) + #define MXC_CCM_CCGR3_SSI_EXT1_OFFSET 28 + #define MXC_CCM_CCGR3_SSI_EXT1(v) (((v) & 0x3) << 28) + #define MXC_CCM_CCGR3_SSI_EXT2_OFFSET 30 + #define MXC_CCM_CCGR3_SSI_EXT2(v) (((v) & 0x3) << 30) + + #define MXC_CCM_CCGR4_PATA_OFFSET 0 + #define MXC_CCM_CCGR4_PATA(v) (((v) & 0x3) << 0) + #if defined(CONFIG_MX51) + #define MXC_CCM_CCGR4_SIM_IPG_OFFSET 2 + #define MXC_CCM_CCGR4_SIM_IPG(v) (((v) & 0x3) << 2) + #define MXC_CCM_CCGR4_SIM_SERIAL_OFFSET 4 + #define MXC_CCM_CCGR4_SIM_SERIAL(v) (((v) & 0x3) << 4) + #elif defined(CONFIG_MX53) + #define MXC_CCM_CCGR4_SATA_OFFSET 2 + #define MXC_CCM_CCGR4_SATA(v) (((v) & 0x3) << 2) + #define MXC_CCM_CCGR4_CAN2_IPG_OFFSET 6 + #define MXC_CCM_CCGR4_CAN2_IPG(v) (((v) & 0x3) << 6) + #define MXC_CCM_CCGR4_CAN2_SERIAL_OFFSET 8 + #define MXC_CCM_CCGR4_CAN2_SERIAL(v) (((v) & 0x3) << 8) + #define MXC_CCM_CCGR4_USB_PHY1_OFFSET 10 + #define MXC_CCM_CCGR4_USB_PHY1(v) (((v) & 0x3) << 10) + #define MXC_CCM_CCGR4_USB_PHY2_OFFSET 12 + #define MXC_CCM_CCGR4_USB_PHY2(v) (((v) & 0x3) << 12) + #endif + #define MXC_CCM_CCGR4_SAHARA_OFFSET 14 + #define MXC_CCM_CCGR4_SAHARA(v) (((v) & 0x3) << 14) + #define MXC_CCM_CCGR4_RTIC_OFFSET 16 + #define MXC_CCM_CCGR4_RTIC(v) (((v) & 0x3) << 16) + #define MXC_CCM_CCGR4_ECSPI1_IPG_OFFSET 18 + #define MXC_CCM_CCGR4_ECSPI1_IPG(v) (((v) & 0x3) << 18) + #define MXC_CCM_CCGR4_ECSPI1_PER_OFFSET 20 + #define MXC_CCM_CCGR4_ECSPI1_PER(v) (((v) & 0x3) << 20) + #define MXC_CCM_CCGR4_ECSPI2_IPG_OFFSET 22 + #define MXC_CCM_CCGR4_ECSPI2_IPG(v) (((v) & 0x3) << 22) + #define MXC_CCM_CCGR4_ECSPI2_PER_OFFSET 24 + #define MXC_CCM_CCGR4_ECSPI2_PER(v) (((v) & 0x3) << 24) + #define MXC_CCM_CCGR4_CSPI_IPG_OFFSET 26 + #define MXC_CCM_CCGR4_CSPI_IPG(v) (((v) & 0x3) << 26) + #define MXC_CCM_CCGR4_SRTC_OFFSET 28 + #define MXC_CCM_CCGR4_SRTC(v) (((v) & 0x3) << 28) + #define MXC_CCM_CCGR4_SDMA_OFFSET 30 + #define MXC_CCM_CCGR4_SDMA(v) (((v) & 0x3) << 30) + + #define MXC_CCM_CCGR5_SPBA_OFFSET 0 + #define MXC_CCM_CCGR5_SPBA(v) (((v) & 0x3) << 0) + #define MXC_CCM_CCGR5_GPU_OFFSET 2 + #define MXC_CCM_CCGR5_GPU(v) (((v) & 0x3) << 2) + #define MXC_CCM_CCGR5_GARB_OFFSET 4 + #define MXC_CCM_CCGR5_GARB(v) (((v) & 0x3) << 4) + #define MXC_CCM_CCGR5_VPU_OFFSET 6 + #define MXC_CCM_CCGR5_VPU(v) (((v) & 0x3) << 6) + #define MXC_CCM_CCGR5_VPU_REF_OFFSET 8 + #define MXC_CCM_CCGR5_VPU_REF(v) (((v) & 0x3) << 8) + #define MXC_CCM_CCGR5_IPU_OFFSET 10 + #define MXC_CCM_CCGR5_IPU(v) (((v) & 0x3) << 10) + #if defined(CONFIG_MX51) + #define MXC_CCM_CCGR5_IPUMUX12_OFFSET 12 + #define MXC_CCM_CCGR5_IPUMUX12(v) (((v) & 0x3) << 12) + #elif defined(CONFIG_MX53) + #define MXC_CCM_CCGR5_IPUMUX1_OFFSET 12 + #define MXC_CCM_CCGR5_IPUMUX1(v) (((v) & 0x3) << 12) + #endif + #define MXC_CCM_CCGR5_EMI_FAST_OFFSET 14 + #define MXC_CCM_CCGR5_EMI_FAST(v) (((v) & 0x3) << 14) + #define MXC_CCM_CCGR5_EMI_SLOW_OFFSET 16 + #define MXC_CCM_CCGR5_EMI_SLOW(v) (((v) & 0x3) << 16) + #define MXC_CCM_CCGR5_EMI_INT1_OFFSET 18 + #define MXC_CCM_CCGR5_EMI_INT1(v) (((v) & 0x3) << 18) + #define MXC_CCM_CCGR5_EMI_ENFC_OFFSET 20 + #define MXC_CCM_CCGR5_EMI_ENFC(v) (((v) & 0x3) << 20) + #define MXC_CCM_CCGR5_EMI_WRCK_OFFSET 22 + #define MXC_CCM_CCGR5_EMI_WRCK(v) (((v) & 0x3) << 22) + #define MXC_CCM_CCGR5_GPC_IPG_OFFSET 24 + #define MXC_CCM_CCGR5_GPC_IPG(v) (((v) & 0x3) << 24) + #define MXC_CCM_CCGR5_SPDIF0_OFFSET 26 + #define MXC_CCM_CCGR5_SPDIF0(v) (((v) & 0x3) << 26) + #if defined(CONFIG_MX51) + #define MXC_CCM_CCGR5_SPDIF1_OFFSET 28 + #define MXC_CCM_CCGR5_SPDIF1(v) (((v) & 0x3) << 28) + #endif + #define MXC_CCM_CCGR5_SPDIF_IPG_OFFSET 30 + #define MXC_CCM_CCGR5_SPDIF_IPG(v) (((v) & 0x3) << 30) + + #if defined(CONFIG_MX53) + #define MXC_CCM_CCGR6_IPUMUX2_OFFSET 0 + #define MXC_CCM_CCGR6_IPUMUX2(v) (((v) & 0x3) << 0) + #define MXC_CCM_CCGR6_OCRAM_OFFSET 2 + #define MXC_CCM_CCGR6_OCRAM(v) (((v) & 0x3) << 2) + #endif + #define MXC_CCM_CCGR6_CSI_MCLK1_OFFSET 4 + #define MXC_CCM_CCGR6_CSI_MCLK1(v) (((v) & 0x3) << 4) + #if defined(CONFIG_MX51) + #define MXC_CCM_CCGR6_CSI_MCLK2_OFFSET 6 + #define MXC_CCM_CCGR6_CSI_MCLK2(v) (((v) & 0x3) << 6) + #define MXC_CCM_CCGR6_EMI_GARB_OFFSET 8 + #define MXC_CCM_CCGR6_EMI_GARB(v) (((v) & 0x3) << 8) + #elif defined(CONFIG_MX53) + #define MXC_CCM_CCGR6_EMI_INT2_OFFSET 8 + #define MXC_CCM_CCGR6_EMI_INT2(v) (((v) & 0x3) << 8) + #endif + #define MXC_CCM_CCGR6_IPU_DI0_OFFSET 10 + #define MXC_CCM_CCGR6_IPU_DI0(v) (((v) & 0x3) << 10) + #define MXC_CCM_CCGR6_IPU_DI1_OFFSET 12 + #define MXC_CCM_CCGR6_IPU_DI1(v) (((v) & 0x3) << 12) + #define MXC_CCM_CCGR6_GPU2D_OFFSET 14 + #define MXC_CCM_CCGR6_GPU2D(v) (((v) & 0x3) << 14) + #if defined(CONFIG_MX53) + #define MXC_CCM_CCGR6_ESAI_IPG_OFFSET 16 + #define MXC_CCM_CCGR6_ESAI_IPG(v) (((v) & 0x3) << 16) + #define MXC_CCM_CCGR6_ESAI_ROOT_OFFSET 18 + #define MXC_CCM_CCGR6_ESAI_ROOT(v) (((v) & 0x3) << 18) + #define MXC_CCM_CCGR6_CAN1_IPG_OFFSET 20 + #define MXC_CCM_CCGR6_CAN1_IPG(v) (((v) & 0x3) << 20) + #define MXC_CCM_CCGR6_CAN1_SERIAL_OFFSET 22 + #define MXC_CCM_CCGR6_CAN1_SERIAL(v) (((v) & 0x3) << 22) + #define MXC_CCM_CCGR6_PL301_4X1_OFFSET 24 + #define MXC_CCM_CCGR6_PL301_4X1(v) (((v) & 0x3) << 24) + #define MXC_CCM_CCGR6_PL301_2X2_OFFSET 26 + #define MXC_CCM_CCGR6_PL301_2X2(v) (((v) & 0x3) << 26) + #define MXC_CCM_CCGR6_LDB_DI0_OFFSET 28 + #define MXC_CCM_CCGR6_LDB_DI0(v) (((v) & 0x3) << 28) + #define MXC_CCM_CCGR6_LDB_DI1_OFFSET 30 + #define MXC_CCM_CCGR6_LDB_DI1(v) (((v) & 0x3) << 30) + + #define MXC_CCM_CCGR7_ASRC_IPG_OFFSET 0 + #define MXC_CCM_CCGR7_ASRC_IPG(v) (((v) & 0x3) << 0) + #define MXC_CCM_CCGR7_ASRC_ASRCK_OFFSET 2 + #define MXC_CCM_CCGR7_ASRC_ASRCK(v) (((v) & 0x3) << 2) + #define MXC_CCM_CCGR7_MLB_OFFSET 4 + #define MXC_CCM_CCGR7_MLB(v) (((v) & 0x3) << 4) + #define MXC_CCM_CCGR7_IEEE1588_OFFSET 6 + #define MXC_CCM_CCGR7_IEEE1588(v) (((v) & 0x3) << 6) + #define MXC_CCM_CCGR7_UART4_IPG_OFFSET 8 + #define MXC_CCM_CCGR7_UART4_IPG(v) (((v) & 0x3) << 8) + #define MXC_CCM_CCGR7_UART4_PER_OFFSET 10 + #define MXC_CCM_CCGR7_UART4_PER(v) (((v) & 0x3) << 10) + #define MXC_CCM_CCGR7_UART5_IPG_OFFSET 12 + #define MXC_CCM_CCGR7_UART5_IPG(v) (((v) & 0x3) << 12) + #define MXC_CCM_CCGR7_UART5_PER_OFFSET 14 + #define MXC_CCM_CCGR7_UART5_PER(v) (((v) & 0x3) << 14) + #endif /* Define the bits in register CLPCR */ --#define MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS (0x1 << 18) ++#define MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS (0x1 << 18) #define MXC_DPLLC_CTL_HFSM (1 << 7) #define MXC_DPLLC_CTL_DPDCK0_2_EN (1 << 12) diff --cc arch/arm/include/asm/arch-mx5/imx-regs.h index 6f06c88568,249d15a505..75d89b056c --- a/arch/arm/include/asm/arch-mx5/imx-regs.h +++ b/arch/arm/include/asm/arch-mx5/imx-regs.h @@@ -23,26 -23,30 +23,28 @@@ #ifndef __ASM_ARCH_MX5_IMX_REGS_H__ #define __ASM_ARCH_MX5_IMX_REGS_H__ + #define ARCH_MXC + #if defined(CONFIG_MX51) #define IRAM_BASE_ADDR 0x1FFE0000 /* internal ram */ -#define IPU_SOC_BASE_ADDR 0x40000000 -#define IPU_SOC_OFFSET 0x1E000000 +#define IPU_CTRL_BASE_ADDR 0x40000000 - #define SPBA0_BASE_ADDR 0x70000000 - #define AIPS1_BASE_ADDR 0x73F00000 - #define AIPS2_BASE_ADDR 0x83F00000 - #define CSD0_BASE_ADDR 0x90000000 - #define CSD1_BASE_ADDR 0xA0000000 - #define NFC_BASE_ADDR_AXI 0xCFFF0000 - #define CS1_BASE_ADDR 0xB8000000 + #define SPBA0_BASE_ADDR 0x70000000 + #define AIPS1_BASE_ADDR 0x73F00000 + #define AIPS2_BASE_ADDR 0x83F00000 + #define CSD0_BASE_ADDR 0x90000000 + #define CSD1_BASE_ADDR 0xA0000000 + #define NFC_BASE_ADDR_AXI 0xCFFF0000 + #define CS1_BASE_ADDR 0xB8000000 #elif defined(CONFIG_MX53) -#define IPU_SOC_BASE_ADDR 0x18000000 -#define IPU_SOC_OFFSET 0x06000000 +#define IPU_CTRL_BASE_ADDR 0x00000000 - #define SPBA0_BASE_ADDR 0x50000000 - #define AIPS1_BASE_ADDR 0x53F00000 - #define AIPS2_BASE_ADDR 0x63F00000 - #define CSD0_BASE_ADDR 0x70000000 - #define CSD1_BASE_ADDR 0xB0000000 - #define NFC_BASE_ADDR_AXI 0xF7FF0000 - #define IRAM_BASE_ADDR 0xF8000000 - #define CS1_BASE_ADDR 0xF4000000 + #define SPBA0_BASE_ADDR 0x50000000 + #define AIPS1_BASE_ADDR 0x53F00000 + #define AIPS2_BASE_ADDR 0x63F00000 + #define CSD0_BASE_ADDR 0x70000000 + #define CSD1_BASE_ADDR 0xB0000000 + #define NFC_BASE_ADDR_AXI 0xF7FF0000 + #define IRAM_BASE_ADDR 0xF8000000 + #define CS1_BASE_ADDR 0xF4000000 #define SATA_BASE_ADDR 0x10000000 #else #error "CPU_TYPE not defined" @@@ -91,10 -95,11 +93,11 @@@ #define GPC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000D8000) #if defined(CONFIG_MX53) -#define GPIO5_BASE_ADDR (AIPS1_BASE_ADDR + 0x000DC000) -#define GPIO6_BASE_ADDR (AIPS1_BASE_ADDR + 0x000E0000) -#define GPIO7_BASE_ADDR (AIPS1_BASE_ADDR + 0x000E4000) +#define GPIO5_BASE_ADDR (AIPS1_BASE_ADDR + 0x000DC000) +#define GPIO6_BASE_ADDR (AIPS1_BASE_ADDR + 0x000E0000) +#define GPIO7_BASE_ADDR (AIPS1_BASE_ADDR + 0x000E4000) +#define UART4_BASE_ADDR (AIPS1_BASE_ADDR + 0x000F0000) + #define I2C3_BASE_ADDR (AIPS1_BASE_ADDR + 0x000EC000) -#define UART4_BASE_ADDR (AIPS1_BASE_ADDR + 0x000F0000) #endif /* * AIPS 2 @@@ -303,6 -294,6 +306,10 @@@ #define DP_MFD_532 (24 - 1) #define DP_MFN_532 13 ++#define DP_OP_455 ((9 << 4) + ((2 - 1) << 0)) ++#define DP_MFD_455 (48 - 1) ++#define DP_MFN_455 23 ++ #define DP_OP_400 ((8 << 4) + ((2 - 1) << 0)) #define DP_MFD_400 (3 - 1) #define DP_MFN_400 1 @@@ -315,16 -306,18 +322,18 @@@ #define DP_MFD_216 (4 - 1) #define DP_MFN_216 3 -#define CHIP_REV_1_0 0x10 -#define CHIP_REV_1_1 0x11 -#define CHIP_REV_2_0 0x20 -#define CHIP_REV_2_5 0x25 -#define CHIP_REV_3_0 0x30 +#define CHIP_REV_1_0 0x10 +#define CHIP_REV_1_1 0x11 +#define CHIP_REV_2_0 0x20 +#define CHIP_REV_2_5 0x25 +#define CHIP_REV_3_0 0x30 -#define BOARD_REV_1_0 0x0 -#define BOARD_REV_2_0 0x1 +#define BOARD_REV_1_0 0x0 +#define BOARD_REV_2_0 0x1 + #define BOARD_VER_OFFSET 0x8 + -#define IMX_IIM_BASE (IIM_BASE_ADDR) +#define IMX_IIM_BASE IIM_BASE_ADDR #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) #include diff --cc arch/arm/include/asm/arch-mx5/iomux-mx51.h index 7e3027b603,4f37295994..283a11f89f --- a/arch/arm/include/asm/arch-mx5/iomux-mx51.h +++ b/arch/arm/include/asm/arch-mx5/iomux-mx51.h @@@ -36,778 -61,104 +61,777 @@@ PAD_CTL_SRE_FAST | PAD_CTL_DVS) #define MX51_GPIO_PAD_CTRL (PAD_CTL_DSE_HIGH | PAD_CTL_PKE | PAD_CTL_SRE_FAST) + #define __NA_ 0x000 + +#define MX51_PAD_CTRL_2 (PAD_CTL_PKE | PAD_CTL_HYS) +#define MX51_PAD_CTRL_3 (PAD_CTL_PKE | PAD_CTL_PUS_100K_UP) +#define MX51_PAD_CTRL_4 (PAD_CTL_PKE | PAD_CTL_DVS | PAD_CTL_HYS) +#define MX51_PAD_CTRL_5 (PAD_CTL_DVS | PAD_CTL_DSE_HIGH) + /* * The naming convention for the pad modes is MX51_PAD___ * If or refers to a GPIO, it is named GPIO_ * See also iomux-v3.h */ - /* Raw pin modes without pad control */ -/* PAD MUX ALT INPSE PATH PADCTRL */ -enum { - MX51_PAD_EIM_D16__USBH2_DATA0 = IOMUX_PAD(0x3f0, 0x05c, 2, __NA_, 0, NO_PAD_CTRL), - MX51_PAD_EIM_D17__USBH2_DATA1 = IOMUX_PAD(0x3f4, 0x060, 2, __NA_, 0, NO_PAD_CTRL), - MX51_PAD_EIM_D18__USBH2_DATA2 = IOMUX_PAD(0x3f8, 0x064, 2, __NA_, 0, NO_PAD_CTRL), - MX51_PAD_EIM_D19__USBH2_DATA3 = IOMUX_PAD(0x3fc, 0x068, 2, __NA_, 0, NO_PAD_CTRL), - MX51_PAD_EIM_D20__USBH2_DATA4 = IOMUX_PAD(0x400, 0x06c, 2, __NA_, 0, NO_PAD_CTRL), - MX51_PAD_EIM_D21__USBH2_DATA5 = IOMUX_PAD(0x404, 0x070, 2, __NA_, 0, NO_PAD_CTRL), - MX51_PAD_EIM_D22__USBH2_DATA6 = IOMUX_PAD(0x408, 0x074, 2, __NA_, 0, NO_PAD_CTRL), - MX51_PAD_EIM_D23__USBH2_DATA7 = IOMUX_PAD(0x40c, 0x078, 2, __NA_, 0, NO_PAD_CTRL), - MX51_PAD_EIM_D27__GPIO2_9 = IOMUX_PAD(0x41c, 0x088, 1, __NA_, 0, MX51_GPIO_PAD_CTRL), - MX51_PAD_EIM_A24__USBH2_CLK = IOMUX_PAD(0x450, 0x0bc, 2, __NA_, 0, NO_PAD_CTRL), - MX51_PAD_EIM_A25__USBH2_DIR = IOMUX_PAD(0x454, 0x0c0, 2, __NA_, 0, NO_PAD_CTRL), - MX51_PAD_EIM_A26__GPIO2_20 = IOMUX_PAD(0x458, 0x0c4, 1, __NA_, 0, MX51_GPIO_PAD_CTRL), - MX51_PAD_EIM_A26__USBH2_STP = IOMUX_PAD(0x458, 0x0c4, 2, __NA_, 0, NO_PAD_CTRL), - MX51_PAD_EIM_A27__USBH2_NXT = IOMUX_PAD(0x45c, 0x0c8, 2, __NA_, 0, NO_PAD_CTRL), - MX51_PAD_EIM_CS0__GPIO2_25 = IOMUX_PAD(0x474, 0x0e0, 1, __NA_, 0, MX51_GPIO_PAD_CTRL), - MX51_PAD_EIM_CS2__SD1_CD = IOMUX_PAD(0x47c, 0x0e8, 1, __NA_, 0, MX51_ESDHC_PAD_CTRL), - MX51_PAD_EIM_CS3__GPIO2_28 = IOMUX_PAD(0x480, 0x0ec, 1, __NA_, 0, MX51_GPIO_PAD_CTRL), - MX51_PAD_EIM_CS4__GPIO2_29 = IOMUX_PAD(0x484, 0x0f0, 1, __NA_, 0, MX51_GPIO_PAD_CTRL), - MX51_PAD_NANDF_WE_B__PATA_DIOW = IOMUX_PAD(0x4e4, 0x108, 1, __NA_, 0, NO_PAD_CTRL), - MX51_PAD_NANDF_RE_B__PATA_DIOR = IOMUX_PAD(0x4e8, 0x10c, 1, __NA_, 0, NO_PAD_CTRL), - MX51_PAD_NANDF_ALE__PATA_BUFFER_EN = IOMUX_PAD(0x4ec, 0x110, 1, __NA_, 0, NO_PAD_CTRL), - MX51_PAD_NANDF_CLE__PATA_RESET_B = IOMUX_PAD(0x4f0, 0x114, 1, __NA_, 0, NO_PAD_CTRL), - MX51_PAD_NANDF_WP_B__PATA_DMACK = IOMUX_PAD(0x4f4, 0x118, 1, __NA_, 0, NO_PAD_CTRL), - MX51_PAD_NANDF_RB0__PATA_DMARQ = IOMUX_PAD(0x4f8, 0x11c, 1, __NA_, 0, NO_PAD_CTRL), - MX51_PAD_NANDF_RB1__PATA_IORDY = IOMUX_PAD(0x4fc, 0x120, 1, __NA_, 0, NO_PAD_CTRL), - MX51_PAD_GPIO_NAND__PATA_INTRQ = IOMUX_PAD(0x514, 0x12c, 1, __NA_, 0, NO_PAD_CTRL), - MX51_PAD_NANDF_CS2__PATA_CS_0 = IOMUX_PAD(0x520, 0x138, 1, __NA_, 0, NO_PAD_CTRL), - MX51_PAD_NANDF_CS3__PATA_CS_1 = IOMUX_PAD(0x524, 0x13c, 1, __NA_, 0, NO_PAD_CTRL), - MX51_PAD_NANDF_CS4__PATA_DA_0 = IOMUX_PAD(0x528, 0x140, 1, __NA_, 0, NO_PAD_CTRL), - MX51_PAD_NANDF_CS5__PATA_DA_1 = IOMUX_PAD(0x52c, 0x144, 1, __NA_, 0, NO_PAD_CTRL), - MX51_PAD_NANDF_CS6__PATA_DA_2 = IOMUX_PAD(0x530, 0x148, 1, __NA_, 0, NO_PAD_CTRL), - MX51_PAD_NANDF_D15__PATA_DATA15 = IOMUX_PAD(0x53c, 0x154, 1, __NA_, 0, NO_PAD_CTRL), - MX51_PAD_NANDF_D14__PATA_DATA14 = IOMUX_PAD(0x540, 0x158, 1, __NA_, 0, NO_PAD_CTRL), - MX51_PAD_NANDF_D13__PATA_DATA13 = IOMUX_PAD(0x544, 0x15c, 1, __NA_, 0, NO_PAD_CTRL), - MX51_PAD_NANDF_D12__PATA_DATA12 = IOMUX_PAD(0x548, 0x160, 1, __NA_, 0, NO_PAD_CTRL), - MX51_PAD_NANDF_D11__PATA_DATA11 = IOMUX_PAD(0x54c, 0x164, 1, __NA_, 0, NO_PAD_CTRL), - MX51_PAD_NANDF_D10__PATA_DATA10 = IOMUX_PAD(0x550, 0x168, 1, __NA_, 0, NO_PAD_CTRL), - MX51_PAD_NANDF_D9__PATA_DATA9 = IOMUX_PAD(0x554, 0x16c, 1, __NA_, 0, NO_PAD_CTRL), - MX51_PAD_NANDF_D8__PATA_DATA8 = IOMUX_PAD(0x558, 0x170, 1, __NA_, 0, NO_PAD_CTRL), - MX51_PAD_NANDF_D7__PATA_DATA7 = IOMUX_PAD(0x55c, 0x174, 1, __NA_, 0, NO_PAD_CTRL), - MX51_PAD_NANDF_D6__PATA_DATA6 = IOMUX_PAD(0x560, 0x178, 1, __NA_, 0, NO_PAD_CTRL), - MX51_PAD_NANDF_D5__PATA_DATA5 = IOMUX_PAD(0x564, 0x17c, 1, __NA_, 0, NO_PAD_CTRL), - MX51_PAD_NANDF_D4__PATA_DATA4 = IOMUX_PAD(0x568, 0x180, 1, __NA_, 0, NO_PAD_CTRL), - MX51_PAD_NANDF_D3__PATA_DATA3 = IOMUX_PAD(0x56c, 0x184, 1, __NA_, 0, NO_PAD_CTRL), - MX51_PAD_NANDF_D2__PATA_DATA2 = IOMUX_PAD(0x570, 0x188, 1, __NA_, 0, NO_PAD_CTRL), - MX51_PAD_NANDF_D1__PATA_DATA1 = IOMUX_PAD(0x574, 0x18c, 1, __NA_, 0, NO_PAD_CTRL), - MX51_PAD_NANDF_D0__PATA_DATA0 = IOMUX_PAD(0x578, 0x190, 1, __NA_, 0, NO_PAD_CTRL), - MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI = IOMUX_PAD(0x600, 0x210, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL), - MX51_PAD_CSPI1_MISO__ECSPI1_MISO = IOMUX_PAD(0x604, 0x214, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL), - MX51_PAD_CSPI1_SS0__GPIO4_24 = IOMUX_PAD(0x608, 0x218, 3, __NA_, 0, MX51_GPIO_PAD_CTRL), - MX51_PAD_CSPI1_SS1__GPIO4_25 = IOMUX_PAD(0x60c, 0x21c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL), - MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK = IOMUX_PAD(0x614, 0x224, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL), - MX51_PAD_UART1_RXD__UART1_RXD = IOMUX_PAD(0x618, 0x228, 0, 0x9e4, 0, MX51_UART_PAD_CTRL), - MX51_PAD_UART1_TXD__UART1_TXD = IOMUX_PAD(0x61c, 0x22c, 0, __NA_, 0, MX51_UART_PAD_CTRL), - MX51_PAD_UART1_RTS__UART1_RTS = IOMUX_PAD(0x620, 0x230, 0, 0x9e0, 0, MX51_UART_PAD_CTRL), - MX51_PAD_UART1_CTS__UART1_CTS = IOMUX_PAD(0x624, 0x234, 0, __NA_, 0, MX51_UART_PAD_CTRL), - MX51_PAD_USBH1_CLK__USBH1_CLK = IOMUX_PAD(0x678, 0x278, 0, __NA_, 0, MX51_USBH1_PAD_CTRL), - MX51_PAD_USBH1_DIR__USBH1_DIR = IOMUX_PAD(0x67c, 0x27c, 0, __NA_, 0, MX51_USBH1_PAD_CTRL), - MX51_PAD_USBH1_STP__USBH1_STP = IOMUX_PAD(0x680, 0x280, 0, __NA_, 0, MX51_USBH1_PAD_CTRL), - MX51_PAD_USBH1_STP__GPIO1_27 = IOMUX_PAD(0x680, 0x280, 2, __NA_, 0, MX51_GPIO_PAD_CTRL), - MX51_PAD_USBH1_NXT__USBH1_NXT = IOMUX_PAD(0x684, 0x284, 0, __NA_, 0, MX51_USBH1_PAD_CTRL), - MX51_PAD_USBH1_DATA0__USBH1_DATA0 = IOMUX_PAD(0x688, 0x288, 0, __NA_, 0, MX51_USBH1_PAD_CTRL), - MX51_PAD_USBH1_DATA1__USBH1_DATA1 = IOMUX_PAD(0x68c, 0x28c, 0, __NA_, 0, MX51_USBH1_PAD_CTRL), - MX51_PAD_USBH1_DATA2__USBH1_DATA2 = IOMUX_PAD(0x690, 0x290, 0, __NA_, 0, MX51_USBH1_PAD_CTRL), - MX51_PAD_USBH1_DATA3__USBH1_DATA3 = IOMUX_PAD(0x694, 0x294, 0, __NA_, 0, MX51_USBH1_PAD_CTRL), - MX51_PAD_USBH1_DATA4__USBH1_DATA4 = IOMUX_PAD(0x698, 0x298, 0, __NA_, 0, MX51_USBH1_PAD_CTRL), - MX51_PAD_USBH1_DATA5__USBH1_DATA5 = IOMUX_PAD(0x69c, 0x29c, 0, __NA_, 0, MX51_USBH1_PAD_CTRL), - MX51_PAD_USBH1_DATA6__USBH1_DATA6 = IOMUX_PAD(0x6a0, 0x2a0, 0, __NA_, 0, MX51_USBH1_PAD_CTRL), - MX51_PAD_USBH1_DATA7__USBH1_DATA7 = IOMUX_PAD(0x6a4, 0x2a4, 0, __NA_, 0, MX51_USBH1_PAD_CTRL), - MX51_PAD_SD1_CMD__SD1_CMD = IOMUX_PAD(0x79c, 0x394, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL), - MX51_PAD_SD1_CLK__SD1_CLK = IOMUX_PAD(0x7a0, 0x398, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS), - MX51_PAD_SD1_DATA0__SD1_DATA0 = IOMUX_PAD(0x7a4, 0x39c, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL), - MX51_PAD_SD1_DATA1__SD1_DATA1 = IOMUX_PAD(0x7a8, 0x3a0, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL), - MX51_PAD_SD1_DATA2__SD1_DATA2 = IOMUX_PAD(0x7ac, 0x3a4, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL), - MX51_PAD_SD1_DATA3__SD1_DATA3 = IOMUX_PAD(0x7b0, 0x3a8, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL), - MX51_PAD_GPIO1_0__SD1_CD = IOMUX_PAD(0x7b4, 0x3ac, 0, __NA_, 0, MX51_ESDHC_PAD_CTRL), - MX51_PAD_GPIO1_1__SD1_WP = IOMUX_PAD(0x7b8, 0x3b0, 0, __NA_, 0, MX51_ESDHC_PAD_CTRL), - MX51_PAD_SD2_CMD__SD2_CMD = IOMUX_PAD(0x7bc, 0x3b4, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL), - MX51_PAD_SD2_CLK__SD2_CLK = IOMUX_PAD(0x7c0, 0x3b8, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS), - MX51_PAD_SD2_DATA0__SD2_DATA0 = IOMUX_PAD(0x7c4, 0x3bc, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL), - MX51_PAD_SD2_DATA1__SD2_DATA1 = IOMUX_PAD(0x7c8, 0x3c0, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL), - MX51_PAD_SD2_DATA2__SD2_DATA2 = IOMUX_PAD(0x7cc, 0x3c4, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL), - MX51_PAD_SD2_DATA3__SD2_DATA3 = IOMUX_PAD(0x7d0, 0x3c8, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL), - MX51_PAD_GPIO1_3__GPIO1_3 = IOMUX_PAD(0x7d8, 0x3d0, 0, __NA_, 0, MX51_GPIO_PAD_CTRL), - MX51_PAD_GPIO1_5__GPIO1_5 = IOMUX_PAD(0x808, 0x3dc, 0, __NA_, 0, MX51_GPIO_PAD_CTRL), - MX51_PAD_GPIO1_6__GPIO1_6 = IOMUX_PAD(0x80c, 0x3e0, 0, __NA_, 0, MX51_GPIO_PAD_CTRL), - MX51_PAD_GPIO1_7__SD2_WP = IOMUX_PAD(0x810, 0x3e4, 6, __NA_, 0, MX51_ESDHC_PAD_CTRL), - MX51_PAD_GPIO1_8__SD2_CD = IOMUX_PAD(0x814, 0x3e8, 6, __NA_, 0, MX51_ESDHC_PAD_CTRL), -}; +/* PAD MUX ALT INPSE PATH PADCTRL */ - - /* The same pins as above but with the default pad control values applied */ +#define MX51_PAD_EIM_D16__AUD4_RXFS IOMUX_PAD(0x3f0, 0x05c, 5, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_D16__AUD5_TXD IOMUX_PAD(0x3f0, 0x05c, 7, 0x8d8, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_D16__EIM_D16 IOMUX_PAD(0x3f0, 0x05c, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_D16__GPIO2_0 IOMUX_PAD(0x3f0, 0x05c, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_EIM_D16__I2C1_SDA IOMUX_PAD(0x3f0, 0x05c, 0x14, 0x9b4, 0, MX51_I2C_PAD_CTRL) +#define MX51_PAD_EIM_D16__UART2_CTS IOMUX_PAD(0x3f0, 0x05c, 3, __NA_, 0, MX51_UART_PAD_CTRL) +#define MX51_PAD_EIM_D16__USBH2_DATA0 IOMUX_PAD(0x3f0, 0x05c, 2, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_D17__AUD5_RXD IOMUX_PAD(0x3f4, 0x060, 7, 0x8d4, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_D17__EIM_D17 IOMUX_PAD(0x3f4, 0x060, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_D17__GPIO2_1 IOMUX_PAD(0x3f4, 0x060, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_EIM_D17__UART2_RXD IOMUX_PAD(0x3f4, 0x060, 3, 0x9ec, 0, MX51_UART_PAD_CTRL) +#define MX51_PAD_EIM_D17__UART3_CTS IOMUX_PAD(0x3f4, 0x060, 4, __NA_, 0, MX51_UART_PAD_CTRL) +#define MX51_PAD_EIM_D17__USBH2_DATA1 IOMUX_PAD(0x3f4, 0x060, 2, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_D18__AUD5_TXC IOMUX_PAD(0x3f8, 0x064, 7, 0x8e4, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_D18__EIM_D18 IOMUX_PAD(0x3f8, 0x064, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_D18__GPIO2_2 IOMUX_PAD(0x3f8, 0x064, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_EIM_D18__UART2_TXD IOMUX_PAD(0x3f8, 0x064, 3, __NA_, 0, MX51_UART_PAD_CTRL) +#define MX51_PAD_EIM_D18__UART3_RTS IOMUX_PAD(0x3f8, 0x064, 4, 0x9f0, 1, MX51_UART_PAD_CTRL) +#define MX51_PAD_EIM_D18__USBH2_DATA2 IOMUX_PAD(0x3f8, 0x064, 2, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_D19__AUD4_RXC IOMUX_PAD(0x3fc, 0x068, 5, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_D19__AUD5_TXFS IOMUX_PAD(0x3fc, 0x068, 7, 0x8e8, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_D19__EIM_D19 IOMUX_PAD(0x3fc, 0x068, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_D19__GPIO2_3 IOMUX_PAD(0x3fc, 0x068, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_EIM_D19__I2C1_SCL IOMUX_PAD(0x3fc, 0x068, 0x14, 0x9b0, 0, MX51_I2C_PAD_CTRL) +#define MX51_PAD_EIM_D19__UART2_RTS IOMUX_PAD(0x3fc, 0x068, 3, 0x9e8, 1, MX51_UART_PAD_CTRL) +#define MX51_PAD_EIM_D19__USBH2_DATA3 IOMUX_PAD(0x3fc, 0x068, 2, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_D20__AUD4_TXD IOMUX_PAD(0x400, 0x06c, 5, 0x8c8, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_D20__EIM_D20 IOMUX_PAD(0x400, 0x06c, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_D20__GPIO2_4 IOMUX_PAD(0x400, 0x06c, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_EIM_D20__SRTC_ALARM_DEB IOMUX_PAD(0x400, 0x06c, 4, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_D20__USBH2_DATA4 IOMUX_PAD(0x400, 0x06c, 2, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_D21__AUD4_RXD IOMUX_PAD(0x404, 0x070, 5, 0x8c4, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_D21__EIM_D21 IOMUX_PAD(0x404, 0x070, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_D21__GPIO2_5 IOMUX_PAD(0x404, 0x070, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_EIM_D21__SRTC_ALARM_DEB IOMUX_PAD(0x404, 0x070, 3, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_D21__USBH2_DATA5 IOMUX_PAD(0x404, 0x070, 2, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_D22__AUD4_TXC IOMUX_PAD(0x408, 0x074, 5, 0x8cc, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_D22__EIM_D22 IOMUX_PAD(0x408, 0x074, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_D22__GPIO2_6 IOMUX_PAD(0x408, 0x074, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_EIM_D22__USBH2_DATA6 IOMUX_PAD(0x408, 0x074, 2, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_D23__AUD4_TXFS IOMUX_PAD(0x40c, 0x078, 5, 0x8d0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_D23__EIM_D23 IOMUX_PAD(0x40c, 0x078, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_D23__GPIO2_7 IOMUX_PAD(0x40c, 0x078, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_EIM_D23__SPDIF_OUT1 IOMUX_PAD(0x40c, 0x078, 4, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_D23__USBH2_DATA7 IOMUX_PAD(0x40c, 0x078, 2, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_D24__AUD6_RXFS IOMUX_PAD(0x410, 0x07c, 5, 0x8f8, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_D24__EIM_D24 IOMUX_PAD(0x410, 0x07c, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_D24__GPIO2_8 IOMUX_PAD(0x410, 0x07c, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_EIM_D24__I2C2_SDA IOMUX_PAD(0x410, 0x07c, 0x14, 0x9bc, 0, MX51_I2C_PAD_CTRL) +#define MX51_PAD_EIM_D24__UART3_CTS IOMUX_PAD(0x410, 0x07c, 3, __NA_, 0, MX51_UART_PAD_CTRL) +#define MX51_PAD_EIM_D24__USBOTG_DATA0 IOMUX_PAD(0x410, 0x07c, 2, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_D25__EIM_D25 IOMUX_PAD(0x414, 0x080, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_D25__KEY_COL6 IOMUX_PAD(0x414, 0x080, 1, 0x9c8, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_D25__UART2_CTS IOMUX_PAD(0x414, 0x080, 4, __NA_, 0, MX51_UART_PAD_CTRL) +#define MX51_PAD_EIM_D25__UART3_RXD IOMUX_PAD(0x414, 0x080, 3, 0x9f4, 0, MX51_UART_PAD_CTRL) +#define MX51_PAD_EIM_D25__USBOTG_DATA1 IOMUX_PAD(0x414, 0x080, 2, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_D26__EIM_D26 IOMUX_PAD(0x418, 0x084, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_D26__KEY_COL7 IOMUX_PAD(0x418, 0x084, 1, 0x9cc, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_D26__UART2_RTS IOMUX_PAD(0x418, 0x084, 4, 0x9e8, 3, MX51_UART_PAD_CTRL) +#define MX51_PAD_EIM_D26__UART3_TXD IOMUX_PAD(0x418, 0x084, 3, __NA_, 0, MX51_UART_PAD_CTRL) +#define MX51_PAD_EIM_D26__USBOTG_DATA2 IOMUX_PAD(0x418, 0x084, 2, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_D27__AUD6_RXC IOMUX_PAD(0x41c, 0x088, 5, 0x8f4, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_D27__EIM_D27 IOMUX_PAD(0x41c, 0x088, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_D27__GPIO2_9 IOMUX_PAD(0x41c, 0x088, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_EIM_D27__I2C2_SCL IOMUX_PAD(0x41c, 0x088, 0x14, 0x9b8, 0, MX51_I2C_PAD_CTRL) +#define MX51_PAD_EIM_D27__UART3_RTS IOMUX_PAD(0x41c, 0x088, 3, 0x9f0, 3, MX51_UART_PAD_CTRL) +#define MX51_PAD_EIM_D27__USBOTG_DATA3 IOMUX_PAD(0x41c, 0x088, 2, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_D28__AUD6_TXD IOMUX_PAD(0x420, 0x08c, 5, 0x8f0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_D28__EIM_D28 IOMUX_PAD(0x420, 0x08c, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_D28__KEY_ROW4 IOMUX_PAD(0x420, 0x08c, 1, 0x9d0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_D28__USBOTG_DATA4 IOMUX_PAD(0x420, 0x08c, 2, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_D29__AUD6_RXD IOMUX_PAD(0x424, 0x090, 5, 0x8ec, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_D29__EIM_D29 IOMUX_PAD(0x424, 0x090, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_D29__KEY_ROW5 IOMUX_PAD(0x424, 0x090, 1, 0x9d4, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_D29__USBOTG_DATA5 IOMUX_PAD(0x424, 0x090, 2, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_D30__AUD6_TXC IOMUX_PAD(0x428, 0x094, 5, 0x8fc, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_D30__EIM_D30 IOMUX_PAD(0x428, 0x094, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_D30__KEY_ROW6 IOMUX_PAD(0x428, 0x094, 1, 0x9d8, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_D30__USBOTG_DATA6 IOMUX_PAD(0x428, 0x094, 2, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_D31__AUD6_TXFS IOMUX_PAD(0x42c, 0x098, 5, 0x900, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_D31__EIM_D31 IOMUX_PAD(0x42c, 0x098, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_D31__KEY_ROW7 IOMUX_PAD(0x42c, 0x098, 1, 0x9dc, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_D31__USBOTG_DATA7 IOMUX_PAD(0x42c, 0x098, 2, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_A16__EIM_A16 IOMUX_PAD(0x430, 0x09c, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_A16__GPIO2_10 IOMUX_PAD(0x430, 0x09c, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_EIM_A16__OSC_FREQ_SEL0 IOMUX_PAD(0x430, 0x09c, 7, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_A17__EIM_A17 IOMUX_PAD(0x434, 0x0a0, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_A17__GPIO2_11 IOMUX_PAD(0x434, 0x0a0, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_EIM_A17__OSC_FREQ_SEL1 IOMUX_PAD(0x434, 0x0a0, 7, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_A18__BOOT_LPB0 IOMUX_PAD(0x438, 0x0a4, 7, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_A18__EIM_A18 IOMUX_PAD(0x438, 0x0a4, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_A18__GPIO2_12 IOMUX_PAD(0x438, 0x0a4, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_EIM_A19__BOOT_LPB1 IOMUX_PAD(0x43c, 0x0a8, 7, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_A19__EIM_A19 IOMUX_PAD(0x43c, 0x0a8, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_A19__GPIO2_13 IOMUX_PAD(0x43c, 0x0a8, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_EIM_A20__BOOT_UART_SRC0 IOMUX_PAD(0x440, 0x0ac, 7, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_A20__EIM_A20 IOMUX_PAD(0x440, 0x0ac, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_A20__GPIO2_14 IOMUX_PAD(0x440, 0x0ac, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_EIM_A21__BOOT_UART_SRC1 IOMUX_PAD(0x444, 0x0b0, 7, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_A21__EIM_A21 IOMUX_PAD(0x444, 0x0b0, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_A21__GPIO2_15 IOMUX_PAD(0x444, 0x0b0, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_EIM_A22__EIM_A22 IOMUX_PAD(0x448, 0x0b4, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_A22__GPIO2_16 IOMUX_PAD(0x448, 0x0b4, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_EIM_A23__BOOT_HPN_EN IOMUX_PAD(0x44c, 0x0b8, 7, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_A23__EIM_A23 IOMUX_PAD(0x44c, 0x0b8, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_A23__GPIO2_17 IOMUX_PAD(0x44c, 0x0b8, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_EIM_A24__EIM_A24 IOMUX_PAD(0x450, 0x0bc, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_A24__GPIO2_18 IOMUX_PAD(0x450, 0x0bc, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_EIM_A24__USBH2_CLK IOMUX_PAD(0x450, 0x0bc, 2, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_A25__DISP1_PIN4 IOMUX_PAD(0x454, 0x0c0, 6, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_A25__EIM_A25 IOMUX_PAD(0x454, 0x0c0, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_A25__GPIO2_19 IOMUX_PAD(0x454, 0x0c0, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_EIM_A25__USBH2_DIR IOMUX_PAD(0x454, 0x0c0, 2, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_A26__CSI1_DATA_EN IOMUX_PAD(0x458, 0x0c4, 5, 0x9a0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_A26__DISP2_EXT_CLK IOMUX_PAD(0x458, 0x0c4, 6, 0x908, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_A26__EIM_A26 IOMUX_PAD(0x458, 0x0c4, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_A26__GPIO2_20 IOMUX_PAD(0x458, 0x0c4, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_EIM_A26__USBH2_STP IOMUX_PAD(0x458, 0x0c4, 2, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_A27__CSI2_DATA_EN IOMUX_PAD(0x45c, 0x0c8, 5, 0x99c, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_A27__DISP1_PIN1 IOMUX_PAD(0x45c, 0x0c8, 6, 0x9a4, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_A27__EIM_A27 IOMUX_PAD(0x45c, 0x0c8, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_A27__GPIO2_21 IOMUX_PAD(0x45c, 0x0c8, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_EIM_A27__USBH2_NXT IOMUX_PAD(0x45c, 0x0c8, 2, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_EB0__EIM_EB0 IOMUX_PAD(0x460, 0x0cc, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_EB1__EIM_EB1 IOMUX_PAD(0x464, 0x0d0, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_EB2__AUD5_RXFS IOMUX_PAD(0x468, 0x0d4, 6, 0x8e0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_EB2__CSI1_D2 IOMUX_PAD(0x468, 0x0d4, 5, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_EB2__EIM_EB2 IOMUX_PAD(0x468, 0x0d4, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_EB2__FEC_MDIO (IOMUX_PAD(0x468, 0x0d4, 3, 0x954, 0, 0) | \ + MUX_PAD_CTRL(PAD_CTL_PUS_22K_UP | PAD_CTL_PKE | PAD_CTL_SRE_FAST | \ + PAD_CTL_DSE_HIGH | PAD_CTL_PUE | PAD_CTL_HYS)) +#define MX51_PAD_EIM_EB2__GPIO2_22 IOMUX_PAD(0x468, 0x0d4, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_EIM_EB2__GPT_CMPOUT1 IOMUX_PAD(0x468, 0x0d4, 7, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_EB3__AUD5_RXC IOMUX_PAD(0x46c, 0x0d8, 6, 0x8dc, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_EB3__CSI1_D3 IOMUX_PAD(0x46c, 0x0d8, 5, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_EB3__EIM_EB3 IOMUX_PAD(0x46c, 0x0d8, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_EB3__FEC_RDATA1 IOMUX_PAD(0x46c, 0x0d8, 3, 0x95c, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_EB3__GPIO2_23 IOMUX_PAD(0x46c, 0x0d8, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_EIM_EB3__GPT_CMPOUT2 IOMUX_PAD(0x46c, 0x0d8, 7, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_OE__EIM_OE IOMUX_PAD(0x470, 0x0dc, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_OE__GPIO2_24 IOMUX_PAD(0x470, 0x0dc, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_EIM_CS0__EIM_CS0 IOMUX_PAD(0x474, 0x0e0, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_CS0__GPIO2_25 IOMUX_PAD(0x474, 0x0e0, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_EIM_CS1__EIM_CS1 IOMUX_PAD(0x478, 0x0e4, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_CS1__GPIO2_26 IOMUX_PAD(0x478, 0x0e4, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_EIM_CS2__AUD5_TXD IOMUX_PAD(0x47c, 0x0e8, 6, 0x8d8, 1, NO_PAD_CTRL) +#define MX51_PAD_EIM_CS2__CSI1_D4 IOMUX_PAD(0x47c, 0x0e8, 5, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_CS2__EIM_CS2 IOMUX_PAD(0x47c, 0x0e8, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_CS2__FEC_RDATA2 IOMUX_PAD(0x47c, 0x0e8, 3, 0x960, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_CS2__GPIO2_27 IOMUX_PAD(0x47c, 0x0e8, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_EIM_CS2__USBOTG_STP IOMUX_PAD(0x47c, 0x0e8, 2, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_CS3__AUD5_RXD IOMUX_PAD(0x480, 0x0ec, 6, 0x8d4, 1, NO_PAD_CTRL) +#define MX51_PAD_EIM_CS3__CSI1_D5 IOMUX_PAD(0x480, 0x0ec, 5, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_CS3__EIM_CS3 IOMUX_PAD(0x480, 0x0ec, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_CS3__FEC_RDATA3 IOMUX_PAD(0x480, 0x0ec, 3, 0x964, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_CS3__GPIO2_28 IOMUX_PAD(0x480, 0x0ec, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_EIM_CS3__USBOTG_NXT IOMUX_PAD(0x480, 0x0ec, 2, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_CS4__AUD5_TXC IOMUX_PAD(0x484, 0x0f0, 6, 0x8e4, 1, NO_PAD_CTRL) +#define MX51_PAD_EIM_CS4__CSI1_D6 IOMUX_PAD(0x484, 0x0f0, 5, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_CS4__EIM_CS4 IOMUX_PAD(0x484, 0x0f0, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_CS4__FEC_RX_ER IOMUX_PAD(0x484, 0x0f0, 3, 0x970, 0, MX51_PAD_CTRL_2) +#define MX51_PAD_EIM_CS4__GPIO2_29 IOMUX_PAD(0x484, 0x0f0, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_EIM_CS4__USBOTG_CLK IOMUX_PAD(0x484, 0x0f0, 2, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_CS5__AUD5_TXFS IOMUX_PAD(0x488, 0x0f4, 6, 0x8e8, 1, NO_PAD_CTRL) +#define MX51_PAD_EIM_CS5__CSI1_D7 IOMUX_PAD(0x488, 0x0f4, 5, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_CS5__DISP1_EXT_CLK IOMUX_PAD(0x488, 0x0f4, 4, 0x904, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_CS5__EIM_CS5 IOMUX_PAD(0x488, 0x0f4, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_CS5__FEC_CRS IOMUX_PAD(0x488, 0x0f4, 3, 0x950, 0, MX51_PAD_CTRL_2) +#define MX51_PAD_EIM_CS5__GPIO2_30 IOMUX_PAD(0x488, 0x0f4, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_EIM_CS5__USBOTG_DIR IOMUX_PAD(0x488, 0x0f4, 2, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_DTACK__EIM_DTACK IOMUX_PAD(0x48c, 0x0f8, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_DTACK__GPIO2_31 IOMUX_PAD(0x48c, 0x0f8, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_EIM_LBA__EIM_LBA IOMUX_PAD(0x494, 0x0fc, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_LBA__GPIO3_1 IOMUX_PAD(0x494, 0x0fc, 1, 0x978, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_EIM_CRE__EIM_CRE IOMUX_PAD(0x4a0, 0x100, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_CRE__GPIO3_2 IOMUX_PAD(0x4a0, 0x100, 1, 0x97c, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_DRAM_CS1__DRAM_CS1 IOMUX_PAD(0x4d0, 0x104, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_WE_B__GPIO3_3 IOMUX_PAD(0x4e4, 0x108, 3, 0x980, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_NANDF_WE_B__NANDF_WE_B IOMUX_PAD(0x4e4, 0x108, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_WE_B__PATA_DIOW IOMUX_PAD(0x4e4, 0x108, 1, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_WE_B__SD3_DATA0 IOMUX_PAD(0x4e4, 0x108, 2, 0x93c, 0, MX51_SDHCI_PAD_CTRL) +#define MX51_PAD_NANDF_RE_B__GPIO3_4 IOMUX_PAD(0x4e8, 0x10c, 3, 0x984, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_NANDF_RE_B__NANDF_RE_B IOMUX_PAD(0x4e8, 0x10c, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_RE_B__PATA_DIOR IOMUX_PAD(0x4e8, 0x10c, 1, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_RE_B__SD3_DATA1 IOMUX_PAD(0x4e8, 0x10c, 2, 0x940, 0, MX51_SDHCI_PAD_CTRL) +#define MX51_PAD_NANDF_ALE__GPIO3_5 IOMUX_PAD(0x4ec, 0x110, 3, 0x988, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_NANDF_ALE__NANDF_ALE IOMUX_PAD(0x4ec, 0x110, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_ALE__PATA_BUFFER_EN IOMUX_PAD(0x4ec, 0x110, 1, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_CLE__GPIO3_6 IOMUX_PAD(0x4f0, 0x114, 3, 0x98c, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_NANDF_CLE__NANDF_CLE IOMUX_PAD(0x4f0, 0x114, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_CLE__PATA_RESET_B IOMUX_PAD(0x4f0, 0x114, 1, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_WP_B__GPIO3_7 IOMUX_PAD(0x4f4, 0x118, 3, 0x990, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_NANDF_WP_B__NANDF_WP_B IOMUX_PAD(0x4f4, 0x118, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_WP_B__PATA_DMACK IOMUX_PAD(0x4f4, 0x118, 1, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_WP_B__SD3_DATA2 IOMUX_PAD(0x4f4, 0x118, 2, 0x944, 0, MX51_SDHCI_PAD_CTRL) +#define MX51_PAD_NANDF_RB0__ECSPI2_SS1 IOMUX_PAD(0x4f8, 0x11c, 5, 0x930, 0, MX51_ECSPI_PAD_CTRL) +#define MX51_PAD_NANDF_RB0__GPIO3_8 IOMUX_PAD(0x4f8, 0x11c, 3, 0x994, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_NANDF_RB0__NANDF_RB0 IOMUX_PAD(0x4f8, 0x11c, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_RB0__PATA_DMARQ IOMUX_PAD(0x4f8, 0x11c, 1, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_RB0__SD3_DATA3 IOMUX_PAD(0x4f8, 0x11c, 2, 0x948, 0, MX51_SDHCI_PAD_CTRL) +#define MX51_PAD_NANDF_RB1__CSPI_MOSI IOMUX_PAD(0x4fc, 0x120, 6, 0x91c, 0, MX51_ECSPI_PAD_CTRL) +#define MX51_PAD_NANDF_RB1__ECSPI2_RDY IOMUX_PAD(0x4fc, 0x120, 2, __NA_, 0, MX51_ECSPI_PAD_CTRL) +#define MX51_PAD_NANDF_RB1__GPIO3_9 IOMUX_PAD(0x4fc, 0x120, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_NANDF_RB1__NANDF_RB1 IOMUX_PAD(0x4fc, 0x120, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_RB1__PATA_IORDY IOMUX_PAD(0x4fc, 0x120, 1, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_RB1__SD4_CMD IOMUX_PAD(0x4fc, 0x120, 5, __NA_, 0, MX51_SDHCI_PAD_CTRL) +#define MX51_PAD_NANDF_RB2__DISP2_WAIT IOMUX_PAD(0x500, 0x124, 5, 0x9a8, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_RB2__ECSPI2_SCLK IOMUX_PAD(0x500, 0x124, 2, __NA_, 0, MX51_ECSPI_PAD_CTRL) +#define MX51_PAD_NANDF_RB2__FEC_COL IOMUX_PAD(0x500, 0x124, 1, 0x94c, 0, MX51_PAD_CTRL_2) +#define MX51_PAD_NANDF_RB2__GPIO3_10 IOMUX_PAD(0x500, 0x124, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_NANDF_RB2__NANDF_RB2 IOMUX_PAD(0x500, 0x124, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_RB2__USBH3_H3_DP IOMUX_PAD(0x500, 0x124, 7, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_RB2__USBH3_NXT IOMUX_PAD(0x500, 0x124, 6, 0xa20, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_RB3__DISP1_WAIT IOMUX_PAD(0x504, 0x128, 5, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_RB3__ECSPI2_MISO IOMUX_PAD(0x504, 0x128, 2, __NA_, 0, MX51_ECSPI_PAD_CTRL) +#define MX51_PAD_NANDF_RB3__FEC_RX_CLK IOMUX_PAD(0x504, 0x128, 1, 0x968, 0, MX51_PAD_CTRL_2) +#define MX51_PAD_NANDF_RB3__GPIO3_11 IOMUX_PAD(0x504, 0x128, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_NANDF_RB3__NANDF_RB3 IOMUX_PAD(0x504, 0x128, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_RB3__USBH3_CLK IOMUX_PAD(0x504, 0x128, 6, 0x9f8, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_RB3__USBH3_H3_DM IOMUX_PAD(0x504, 0x128, 7, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_NAND__GPIO_NAND IOMUX_PAD(0x514, 0x12c, 0, 0x998, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_GPIO_NAND__PATA_INTRQ IOMUX_PAD(0x514, 0x12c, 1, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_CS0__GPIO3_16 IOMUX_PAD(0x518, 0x130, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_NANDF_CS0__NANDF_CS0 IOMUX_PAD(0x518, 0x130, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_CS1__GPIO3_17 IOMUX_PAD(0x51c, 0x134, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_NANDF_CS1__NANDF_CS1 IOMUX_PAD(0x51c, 0x134, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_CS2__CSPI_SCLK IOMUX_PAD(0x520, 0x138, 6, 0x914, 0, MX51_ECSPI_PAD_CTRL) +#define MX51_PAD_NANDF_CS2__FEC_TX_ER IOMUX_PAD(0x520, 0x138, 2, __NA_, 0, MX51_PAD_CTRL_5) +#define MX51_PAD_NANDF_CS2__GPIO3_18 IOMUX_PAD(0x520, 0x138, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_NANDF_CS2__NANDF_CS2 IOMUX_PAD(0x520, 0x138, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_CS2__PATA_CS_0 IOMUX_PAD(0x520, 0x138, 1, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_CS2__SD4_CLK IOMUX_PAD(0x520, 0x138, 5, __NA_, 0, MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS) +#define MX51_PAD_NANDF_CS2__USBH3_H1_DP IOMUX_PAD(0x520, 0x138, 7, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_CS3__FEC_MDC IOMUX_PAD(0x524, 0x13c, 2, __NA_, 0, MX51_PAD_CTRL_5) +#define MX51_PAD_NANDF_CS3__GPIO3_19 IOMUX_PAD(0x524, 0x13c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_NANDF_CS3__NANDF_CS3 IOMUX_PAD(0x524, 0x13c, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_CS3__PATA_CS_1 IOMUX_PAD(0x524, 0x13c, 1, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_CS3__SD4_DAT0 IOMUX_PAD(0x524, 0x13c, 5, __NA_, 0, MX51_SDHCI_PAD_CTRL) +#define MX51_PAD_NANDF_CS3__USBH3_H1_DM IOMUX_PAD(0x524, 0x13c, 7, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_CS4__FEC_TDATA1 IOMUX_PAD(0x528, 0x140, 2, __NA_, 0, MX51_PAD_CTRL_5) +#define MX51_PAD_NANDF_CS4__GPIO3_20 IOMUX_PAD(0x528, 0x140, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_NANDF_CS4__NANDF_CS4 IOMUX_PAD(0x528, 0x140, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_CS4__PATA_DA_0 IOMUX_PAD(0x528, 0x140, 1, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_CS4__SD4_DAT1 IOMUX_PAD(0x528, 0x140, 5, __NA_, 0, MX51_SDHCI_PAD_CTRL) +#define MX51_PAD_NANDF_CS4__USBH3_STP IOMUX_PAD(0x528, 0x140, 7, 0xa24, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_CS5__FEC_TDATA2 IOMUX_PAD(0x52c, 0x144, 2, __NA_, 0, MX51_PAD_CTRL_5) +#define MX51_PAD_NANDF_CS5__GPIO3_21 IOMUX_PAD(0x52c, 0x144, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_NANDF_CS5__NANDF_CS5 IOMUX_PAD(0x52c, 0x144, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_CS5__PATA_DA_1 IOMUX_PAD(0x52c, 0x144, 1, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_CS5__SD4_DAT2 IOMUX_PAD(0x52c, 0x144, 5, __NA_, 0, MX51_SDHCI_PAD_CTRL) +#define MX51_PAD_NANDF_CS5__USBH3_DIR IOMUX_PAD(0x52c, 0x144, 7, 0xa1c, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_CS6__CSPI_SS3 IOMUX_PAD(0x530, 0x148, 7, 0x928, 0, MX51_ECSPI_PAD_CTRL) +#define MX51_PAD_NANDF_CS6__FEC_TDATA3 IOMUX_PAD(0x530, 0x148, 2, __NA_, 0, MX51_PAD_CTRL_5) +#define MX51_PAD_NANDF_CS6__GPIO3_22 IOMUX_PAD(0x530, 0x148, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_NANDF_CS6__NANDF_CS6 IOMUX_PAD(0x530, 0x148, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_CS6__PATA_DA_2 IOMUX_PAD(0x530, 0x148, 1, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_CS6__SD4_DAT3 IOMUX_PAD(0x530, 0x148, 5, __NA_, 0, MX51_SDHCI_PAD_CTRL) +#define MX51_PAD_NANDF_CS7__FEC_TX_EN IOMUX_PAD(0x534, 0x14c, 1, __NA_, 0, MX51_PAD_CTRL_5) +#define MX51_PAD_NANDF_CS7__GPIO3_23 IOMUX_PAD(0x534, 0x14c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_NANDF_CS7__NANDF_CS7 IOMUX_PAD(0x534, 0x14c, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_CS7__SD3_CLK IOMUX_PAD(0x534, 0x14c, 5, __NA_, 0, MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS) +#define MX51_PAD_NANDF_RDY_INT__ECSPI2_SS0 IOMUX_PAD(0x538, 0x150, 2, __NA_, 0, MX51_ECSPI_PAD_CTRL) +#define MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK IOMUX_PAD(0x538, 0x150, 1, 0x974, 0, MX51_PAD_CTRL_4) +#define MX51_PAD_NANDF_RDY_INT__GPIO3_24 IOMUX_PAD(0x538, 0x150, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_NANDF_RDY_INT__NANDF_RDY_INT IOMUX_PAD(0x538, 0x150, 0, 0x938, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_RDY_INT__SD3_CMD IOMUX_PAD(0x538, 0x150, 5, __NA_, 0, MX51_SDHCI_PAD_CTRL) +#define MX51_PAD_NANDF_D15__ECSPI2_MOSI IOMUX_PAD(0x53c, 0x154, 2, __NA_, 0, MX51_ECSPI_PAD_CTRL) +#define MX51_PAD_NANDF_D15__GPIO3_25 IOMUX_PAD(0x53c, 0x154, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_NANDF_D15__NANDF_D15 IOMUX_PAD(0x53c, 0x154, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D15__PATA_DATA15 IOMUX_PAD(0x53c, 0x154, 1, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D15__SD3_DAT7 IOMUX_PAD(0x53c, 0x154, 5, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D14__ECSPI2_SS3 IOMUX_PAD(0x540, 0x158, 2, 0x934, 0, MX51_ECSPI_PAD_CTRL) +#define MX51_PAD_NANDF_D14__GPIO3_26 IOMUX_PAD(0x540, 0x158, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_NANDF_D14__NANDF_D14 IOMUX_PAD(0x540, 0x158, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D14__PATA_DATA14 IOMUX_PAD(0x540, 0x158, 1, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D14__SD3_DAT6 IOMUX_PAD(0x540, 0x158, 5, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D13__ECSPI2_SS2 IOMUX_PAD(0x544, 0x15c, 2, __NA_, 0, MX51_ECSPI_PAD_CTRL) +#define MX51_PAD_NANDF_D13__GPIO3_27 IOMUX_PAD(0x544, 0x15c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_NANDF_D13__NANDF_D13 IOMUX_PAD(0x544, 0x15c, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D13__PATA_DATA13 IOMUX_PAD(0x544, 0x15c, 1, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D13__SD3_DAT5 IOMUX_PAD(0x544, 0x15c, 5, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D12__ECSPI2_SS1 IOMUX_PAD(0x548, 0x160, 2, 0x930, 1, MX51_ECSPI_PAD_CTRL) +#define MX51_PAD_NANDF_D12__GPIO3_28 IOMUX_PAD(0x548, 0x160, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_NANDF_D12__NANDF_D12 IOMUX_PAD(0x548, 0x160, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D12__PATA_DATA12 IOMUX_PAD(0x548, 0x160, 1, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D12__SD3_DAT4 IOMUX_PAD(0x548, 0x160, 5, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D11__FEC_RX_DV IOMUX_PAD(0x54c, 0x164, 2, 0x96c, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D11__GPIO3_29 IOMUX_PAD(0x54c, 0x164, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_NANDF_D11__NANDF_D11 IOMUX_PAD(0x54c, 0x164, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D11__PATA_DATA11 IOMUX_PAD(0x54c, 0x164, 1, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D11__SD3_DATA3 IOMUX_PAD(0x54c, 0x164, 5, 0x948, 1, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D10__GPIO3_30 IOMUX_PAD(0x550, 0x168, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_NANDF_D10__NANDF_D10 IOMUX_PAD(0x550, 0x168, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D10__PATA_DATA10 IOMUX_PAD(0x550, 0x168, 1, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D10__SD3_DATA2 IOMUX_PAD(0x550, 0x168, 5, 0x944, 1, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D9__FEC_RDATA0 IOMUX_PAD(0x554, 0x16c, 2, 0x958, 0, MX51_PAD_CTRL_4) +#define MX51_PAD_NANDF_D9__GPIO3_31 IOMUX_PAD(0x554, 0x16c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_NANDF_D9__NANDF_D9 IOMUX_PAD(0x554, 0x16c, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D9__PATA_DATA9 IOMUX_PAD(0x554, 0x16c, 1, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D9__SD3_DATA1 IOMUX_PAD(0x554, 0x16c, 5, 0x940, 1, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D8__FEC_TDATA0 IOMUX_PAD(0x558, 0x170, 2, __NA_, 0, MX51_PAD_CTRL_5) +#define MX51_PAD_NANDF_D8__GPIO4_0 IOMUX_PAD(0x558, 0x170, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_NANDF_D8__NANDF_D8 IOMUX_PAD(0x558, 0x170, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D8__PATA_DATA8 IOMUX_PAD(0x558, 0x170, 1, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D8__SD3_DATA0 IOMUX_PAD(0x558, 0x170, 5, 0x93c, 1, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D7__GPIO4_1 IOMUX_PAD(0x55c, 0x174, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_NANDF_D7__NANDF_D7 IOMUX_PAD(0x55c, 0x174, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D7__PATA_DATA7 IOMUX_PAD(0x55c, 0x174, 1, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D7__USBH3_DATA0 IOMUX_PAD(0x55c, 0x174, 5, 0x9fc, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D6__GPIO4_2 IOMUX_PAD(0x560, 0x178, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_NANDF_D6__NANDF_D6 IOMUX_PAD(0x560, 0x178, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D6__PATA_DATA6 IOMUX_PAD(0x560, 0x178, 1, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D6__SD4_LCTL IOMUX_PAD(0x560, 0x178, 2, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D6__USBH3_DATA1 IOMUX_PAD(0x560, 0x178, 5, 0xa00, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D5__GPIO4_3 IOMUX_PAD(0x564, 0x17c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_NANDF_D5__NANDF_D5 IOMUX_PAD(0x564, 0x17c, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D5__PATA_DATA5 IOMUX_PAD(0x564, 0x17c, 1, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D5__SD4_WP IOMUX_PAD(0x564, 0x17c, 2, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D5__USBH3_DATA2 IOMUX_PAD(0x564, 0x17c, 5, 0xa04, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D4__GPIO4_4 IOMUX_PAD(0x568, 0x180, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_NANDF_D4__NANDF_D4 IOMUX_PAD(0x568, 0x180, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D4__PATA_DATA4 IOMUX_PAD(0x568, 0x180, 1, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D4__SD4_CD IOMUX_PAD(0x568, 0x180, 2, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D4__USBH3_DATA3 IOMUX_PAD(0x568, 0x180, 5, 0xa08, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D3__GPIO4_5 IOMUX_PAD(0x56c, 0x184, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_NANDF_D3__NANDF_D3 IOMUX_PAD(0x56c, 0x184, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D3__PATA_DATA3 IOMUX_PAD(0x56c, 0x184, 1, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D3__SD4_DAT4 IOMUX_PAD(0x56c, 0x184, 2, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D3__USBH3_DATA4 IOMUX_PAD(0x56c, 0x184, 5, 0xa0c, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D2__GPIO4_6 IOMUX_PAD(0x570, 0x188, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_NANDF_D2__NANDF_D2 IOMUX_PAD(0x570, 0x188, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D2__PATA_DATA2 IOMUX_PAD(0x570, 0x188, 1, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D2__SD4_DAT5 IOMUX_PAD(0x570, 0x188, 2, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D2__USBH3_DATA5 IOMUX_PAD(0x570, 0x188, 5, 0xa10, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D1__GPIO4_7 IOMUX_PAD(0x574, 0x18c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_NANDF_D1__NANDF_D1 IOMUX_PAD(0x574, 0x18c, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D1__PATA_DATA1 IOMUX_PAD(0x574, 0x18c, 1, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D1__SD4_DAT6 IOMUX_PAD(0x574, 0x18c, 2, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D1__USBH3_DATA6 IOMUX_PAD(0x574, 0x18c, 5, 0xa14, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D0__GPIO4_8 IOMUX_PAD(0x578, 0x190, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_NANDF_D0__NANDF_D0 IOMUX_PAD(0x578, 0x190, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D0__PATA_DATA0 IOMUX_PAD(0x578, 0x190, 1, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D0__SD4_DAT7 IOMUX_PAD(0x578, 0x190, 2, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D0__USBH3_DATA7 IOMUX_PAD(0x578, 0x190, 5, 0xa18, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI1_D8__CSI1_D8 IOMUX_PAD(0x57c, 0x194, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI1_D8__GPIO3_12 IOMUX_PAD(0x57c, 0x194, 3, 0x998, 1, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_CSI1_D9__CSI1_D9 IOMUX_PAD(0x580, 0x198, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI1_D9__GPIO3_13 IOMUX_PAD(0x580, 0x198, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_CSI1_D10__CSI1_D10 IOMUX_PAD(0x584, 0x19c, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI1_D11__CSI1_D11 IOMUX_PAD(0x588, 0x1a0, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI1_D12__CSI1_D12 IOMUX_PAD(0x58c, 0x1a4, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI1_D13__CSI1_D13 IOMUX_PAD(0x590, 0x1a8, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI1_D14__CSI1_D14 IOMUX_PAD(0x594, 0x1ac, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI1_D15__CSI1_D15 IOMUX_PAD(0x598, 0x1b0, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI1_D16__CSI1_D16 IOMUX_PAD(0x59c, 0x1b4, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI1_D17__CSI1_D17 IOMUX_PAD(0x5a0, 0x1b8, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI1_D18__CSI1_D18 IOMUX_PAD(0x5a4, 0x1bc, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI1_D19__CSI1_D19 IOMUX_PAD(0x5a8, 0x1c0, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI1_VSYNC__CSI1_VSYNC IOMUX_PAD(0x5ac, 0x1c4, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI1_VSYNC__GPIO3_14 IOMUX_PAD(0x5ac, 0x1c4, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_CSI1_HSYNC__CSI1_HSYNC IOMUX_PAD(0x5b0, 0x1c8, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI1_HSYNC__GPIO3_15 IOMUX_PAD(0x5b0, 0x1c8, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_CSI1_PIXCLK__CSI1_PIXCLK IOMUX_PAD(0x5b4, __NA_, 0, 0x000, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI1_MCLK__CSI1_MCLK IOMUX_PAD(0x5b8, __NA_, 0, 0x000, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI2_D12__CSI2_D12 IOMUX_PAD(0x5bc, 0x1cc, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI2_D12__GPIO4_9 IOMUX_PAD(0x5bc, 0x1cc, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_CSI2_D13__CSI2_D13 IOMUX_PAD(0x5c0, 0x1d0, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI2_D13__GPIO4_10 IOMUX_PAD(0x5c0, 0x1d0, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_CSI2_D14__CSI2_D14 IOMUX_PAD(0x5c4, 0x1d4, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI2_D15__CSI2_D15 IOMUX_PAD(0x5c8, 0x1d8, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI2_D16__CSI2_D16 IOMUX_PAD(0x5cc, 0x1dc, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI2_D17__CSI2_D17 IOMUX_PAD(0x5d0, 0x1e0, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI2_D18__CSI2_D18 IOMUX_PAD(0x5d4, 0x1e4, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI2_D18__GPIO4_11 IOMUX_PAD(0x5d4, 0x1e4, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_CSI2_D19__CSI2_D19 IOMUX_PAD(0x5d8, 0x1e8, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI2_D19__GPIO4_12 IOMUX_PAD(0x5d8, 0x1e8, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_CSI2_VSYNC__CSI2_VSYNC IOMUX_PAD(0x5dc, 0x1ec, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI2_VSYNC__GPIO4_13 IOMUX_PAD(0x5dc, 0x1ec, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_CSI2_HSYNC__CSI2_HSYNC IOMUX_PAD(0x5e0, 0x1f0, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI2_HSYNC__GPIO4_14 IOMUX_PAD(0x5e0, 0x1f0, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_CSI2_PIXCLK__CSI2_PIXCLK IOMUX_PAD(0x5e4, 0x1f4, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI2_PIXCLK__GPIO4_15 IOMUX_PAD(0x5e4, 0x1f4, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_I2C1_CLK__GPIO4_16 IOMUX_PAD(0x5e8, 0x1f8, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_I2C1_CLK__I2C1_CLK IOMUX_PAD(0x5e8, 0x1f8, 0x10, __NA_, 0, MX51_I2C_PAD_CTRL) +#define MX51_PAD_I2C1_DAT__GPIO4_17 IOMUX_PAD(0x5ec, 0x1fc, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_I2C1_DAT__I2C1_DAT IOMUX_PAD(0x5ec, 0x1fc, 0x10, __NA_, 0, MX51_I2C_PAD_CTRL) +#define MX51_PAD_AUD3_BB_TXD__AUD3_TXD IOMUX_PAD(0x5f0, 0x200, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_AUD3_BB_TXD__GPIO4_18 IOMUX_PAD(0x5f0, 0x200, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_AUD3_BB_RXD__AUD3_RXD IOMUX_PAD(0x5f4, 0x204, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_AUD3_BB_RXD__GPIO4_19 IOMUX_PAD(0x5f4, 0x204, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_AUD3_BB_RXD__UART3_RXD IOMUX_PAD(0x5f4, 0x204, 1, 0x9f4, 2, MX51_UART_PAD_CTRL) +#define MX51_PAD_AUD3_BB_CK__AUD3_TXC IOMUX_PAD(0x5f8, 0x208, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_AUD3_BB_CK__GPIO4_20 IOMUX_PAD(0x5f8, 0x208, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_AUD3_BB_FS__AUD3_TXFS IOMUX_PAD(0x5fc, 0x20c, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_AUD3_BB_FS__GPIO4_21 IOMUX_PAD(0x5fc, 0x20c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_AUD3_BB_FS__UART3_TXD IOMUX_PAD(0x5fc, 0x20c, 1, __NA_, 0, MX51_UART_PAD_CTRL) +#define MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI IOMUX_PAD(0x600, 0x210, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL) +#define MX51_PAD_CSPI1_MOSI__GPIO4_22 IOMUX_PAD(0x600, 0x210, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_CSPI1_MOSI__I2C1_SDA IOMUX_PAD(0x600, 0x210, 0x11, 0x9b4, 1, MX51_I2C_PAD_CTRL) +#define MX51_PAD_CSPI1_MISO__AUD4_RXD IOMUX_PAD(0x604, 0x214, 1, 0x8c4, 1, NO_PAD_CTRL) +#define MX51_PAD_CSPI1_MISO__ECSPI1_MISO IOMUX_PAD(0x604, 0x214, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL) +#define MX51_PAD_CSPI1_MISO__GPIO4_23 IOMUX_PAD(0x604, 0x214, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_CSPI1_SS0__AUD4_TXC IOMUX_PAD(0x608, 0x218, 1, 0x8cc, 1, NO_PAD_CTRL) +#define MX51_PAD_CSPI1_SS0__ECSPI1_SS0 IOMUX_PAD(0x608, 0x218, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL) +#define MX51_PAD_CSPI1_SS0__GPIO4_24 IOMUX_PAD(0x608, 0x218, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_CSPI1_SS1__AUD4_TXD IOMUX_PAD(0x60c, 0x21c, 1, 0x8c8, 1, NO_PAD_CTRL) +#define MX51_PAD_CSPI1_SS1__ECSPI1_SS1 IOMUX_PAD(0x60c, 0x21c, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL) +#define MX51_PAD_CSPI1_SS1__GPIO4_25 IOMUX_PAD(0x60c, 0x21c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_CSPI1_RDY__AUD4_TXFS IOMUX_PAD(0x610, 0x220, 1, 0x8d0, 1, NO_PAD_CTRL) +#define MX51_PAD_CSPI1_RDY__ECSPI1_RDY IOMUX_PAD(0x610, 0x220, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL) +#define MX51_PAD_CSPI1_RDY__GPIO4_26 IOMUX_PAD(0x610, 0x220, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK IOMUX_PAD(0x614, 0x224, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL) +#define MX51_PAD_CSPI1_SCLK__GPIO4_27 IOMUX_PAD(0x614, 0x224, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_CSPI1_SCLK__I2C1_SCL IOMUX_PAD(0x614, 0x224, 0x11, 0x9b0, 1, MX51_I2C_PAD_CTRL) +#define MX51_PAD_UART1_RXD__GPIO4_28 IOMUX_PAD(0x618, 0x228, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_UART1_RXD__UART1_RXD IOMUX_PAD(0x618, 0x228, 0, 0x9e4, 0, MX51_UART_PAD_CTRL) +#define MX51_PAD_UART1_TXD__GPIO4_29 IOMUX_PAD(0x61c, 0x22c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_UART1_TXD__PWM2_PWMO IOMUX_PAD(0x61c, 0x22c, 1, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_UART1_TXD__UART1_TXD IOMUX_PAD(0x61c, 0x22c, 0, __NA_, 0, MX51_UART_PAD_CTRL) +#define MX51_PAD_UART1_RTS__GPIO4_30 IOMUX_PAD(0x620, 0x230, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_UART1_RTS__UART1_RTS IOMUX_PAD(0x620, 0x230, 0, 0x9e0, 0, MX51_UART_PAD_CTRL) +#define MX51_PAD_UART1_CTS__GPIO4_31 IOMUX_PAD(0x624, 0x234, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_UART1_CTS__UART1_CTS IOMUX_PAD(0x624, 0x234, 0, __NA_, 0, MX51_UART_PAD_CTRL) +#define MX51_PAD_UART2_RXD__FIRI_TXD IOMUX_PAD(0x628, 0x238, 1, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_UART2_RXD__GPIO1_20 IOMUX_PAD(0x628, 0x238, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_UART2_RXD__UART2_RXD IOMUX_PAD(0x628, 0x238, 0, 0x9ec, 2, MX51_UART_PAD_CTRL) +#define MX51_PAD_UART2_TXD__FIRI_RXD IOMUX_PAD(0x62c, 0x23c, 1, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_UART2_TXD__GPIO1_21 IOMUX_PAD(0x62c, 0x23c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_UART2_TXD__UART2_TXD IOMUX_PAD(0x62c, 0x23c, 0, __NA_, 0, MX51_UART_PAD_CTRL) +#define MX51_PAD_UART3_RXD__CSI1_D0 IOMUX_PAD(0x630, 0x240, 2, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_UART3_RXD__GPIO1_22 IOMUX_PAD(0x630, 0x240, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_UART3_RXD__UART1_DTR IOMUX_PAD(0x630, 0x240, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_UART3_RXD__UART3_RXD IOMUX_PAD(0x630, 0x240, 1, 0x9f4, 4, MX51_UART_PAD_CTRL) +#define MX51_PAD_UART3_TXD__CSI1_D1 IOMUX_PAD(0x634, 0x244, 2, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_UART3_TXD__GPIO1_23 IOMUX_PAD(0x634, 0x244, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_UART3_TXD__UART1_DSR IOMUX_PAD(0x634, 0x244, 0, __NA_, 0, MX51_UART_PAD_CTRL) +#define MX51_PAD_UART3_TXD__UART3_TXD IOMUX_PAD(0x634, 0x244, 1, __NA_, 0, MX51_UART_PAD_CTRL) +#define MX51_PAD_OWIRE_LINE__GPIO1_24 IOMUX_PAD(0x638, 0x248, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_OWIRE_LINE__OWIRE_LINE IOMUX_PAD(0x638, 0x248, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_OWIRE_LINE__SPDIF_OUT IOMUX_PAD(0x638, 0x248, 6, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_KEY_ROW0__KEY_ROW0 IOMUX_PAD(0x63c, 0x24c, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_KEY_ROW1__KEY_ROW1 IOMUX_PAD(0x640, 0x250, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_KEY_ROW2__KEY_ROW2 IOMUX_PAD(0x644, 0x254, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_KEY_ROW3__KEY_ROW3 IOMUX_PAD(0x648, 0x258, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_KEY_COL0__KEY_COL0 IOMUX_PAD(0x64c, 0x25c, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_KEY_COL0__PLL1_BYP IOMUX_PAD(0x64c, 0x25c, 7, 0x90c, 0, NO_PAD_CTRL) +#define MX51_PAD_KEY_COL1__KEY_COL1 IOMUX_PAD(0x650, 0x260, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_KEY_COL1__PLL2_BYP IOMUX_PAD(0x650, 0x260, 7, 0x910, 0, NO_PAD_CTRL) +#define MX51_PAD_KEY_COL2__KEY_COL2 IOMUX_PAD(0x654, 0x264, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_KEY_COL2__PLL3_BYP IOMUX_PAD(0x654, 0x264, 7, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_KEY_COL3__KEY_COL3 IOMUX_PAD(0x658, 0x268, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_KEY_COL4__I2C2_SCL IOMUX_PAD(0x65c, 0x26c, 0x13, 0x9b8, 1, MX51_I2C_PAD_CTRL) +#define MX51_PAD_KEY_COL4__KEY_COL4 IOMUX_PAD(0x65c, 0x26c, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_KEY_COL4__SPDIF_OUT1 IOMUX_PAD(0x65c, 0x26c, 6, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_KEY_COL4__UART1_RI IOMUX_PAD(0x65c, 0x26c, 1, __NA_, 0, MX51_UART_PAD_CTRL) +#define MX51_PAD_KEY_COL4__UART3_RTS IOMUX_PAD(0x65c, 0x26c, 2, 0x9f0, 4, MX51_UART_PAD_CTRL) +#define MX51_PAD_KEY_COL5__I2C2_SDA IOMUX_PAD(0x660, 0x270, 0x13, 0x9bc, 1, MX51_I2C_PAD_CTRL) +#define MX51_PAD_KEY_COL5__KEY_COL5 IOMUX_PAD(0x660, 0x270, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_KEY_COL5__UART1_DCD IOMUX_PAD(0x660, 0x270, 1, __NA_, 0, MX51_UART_PAD_CTRL) +#define MX51_PAD_KEY_COL5__UART3_CTS IOMUX_PAD(0x660, 0x270, 2, __NA_, 0, MX51_UART_PAD_CTRL) +#define MX51_PAD_USBH1_CLK__CSPI_SCLK IOMUX_PAD(0x678, 0x278, 1, 0x914, 1, MX51_ECSPI_PAD_CTRL) +#define MX51_PAD_USBH1_CLK__GPIO1_25 IOMUX_PAD(0x678, 0x278, 2, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_USBH1_CLK__I2C2_SCL IOMUX_PAD(0x678, 0x278, 0x15, 0x9b8, 2, MX51_I2C_PAD_CTRL) +#define MX51_PAD_USBH1_CLK__USBH1_CLK IOMUX_PAD(0x678, 0x278, 0, __NA_, 0, MX51_USBH1_PAD_CTRL) +#define MX51_PAD_USBH1_DIR__CSPI_MOSI IOMUX_PAD(0x67c, 0x27c, 1, 0x91c, 1, MX51_ECSPI_PAD_CTRL) +#define MX51_PAD_USBH1_DIR__GPIO1_26 IOMUX_PAD(0x67c, 0x27c, 2, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_USBH1_DIR__I2C2_SDA IOMUX_PAD(0x67c, 0x27c, 0x15, 0x9bc, 2, MX51_I2C_PAD_CTRL) +#define MX51_PAD_USBH1_DIR__USBH1_DIR IOMUX_PAD(0x67c, 0x27c, 0, __NA_, 0, MX51_USBH1_PAD_CTRL) +#define MX51_PAD_USBH1_STP__CSPI_RDY IOMUX_PAD(0x680, 0x280, 1, __NA_, 0, MX51_ECSPI_PAD_CTRL) +#define MX51_PAD_USBH1_STP__GPIO1_27 IOMUX_PAD(0x680, 0x280, 2, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_USBH1_STP__UART3_RXD IOMUX_PAD(0x680, 0x280, 5, 0x9f4, 6, MX51_UART_PAD_CTRL) +#define MX51_PAD_USBH1_STP__USBH1_STP IOMUX_PAD(0x680, 0x280, 0, __NA_, 0, MX51_USBH1_PAD_CTRL) +#define MX51_PAD_USBH1_NXT__CSPI_MISO IOMUX_PAD(0x684, 0x284, 1, 0x918, 0, MX51_ECSPI_PAD_CTRL) +#define MX51_PAD_USBH1_NXT__GPIO1_28 IOMUX_PAD(0x684, 0x284, 2, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_USBH1_NXT__UART3_TXD IOMUX_PAD(0x684, 0x284, 5, __NA_, 0, MX51_UART_PAD_CTRL) +#define MX51_PAD_USBH1_NXT__USBH1_NXT IOMUX_PAD(0x684, 0x284, 0, __NA_, 0, MX51_USBH1_PAD_CTRL) +#define MX51_PAD_USBH1_DATA0__GPIO1_11 IOMUX_PAD(0x688, 0x288, 2, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_USBH1_DATA0__UART2_CTS IOMUX_PAD(0x688, 0x288, 1, __NA_, 0, MX51_UART_PAD_CTRL) +#define MX51_PAD_USBH1_DATA0__USBH1_DATA0 IOMUX_PAD(0x688, 0x288, 0, __NA_, 0, MX51_USBH1_PAD_CTRL) +#define MX51_PAD_USBH1_DATA1__GPIO1_12 IOMUX_PAD(0x68c, 0x28c, 2, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_USBH1_DATA1__UART2_RXD IOMUX_PAD(0x68c, 0x28c, 1, 0x9ec, 4, MX51_UART_PAD_CTRL) +#define MX51_PAD_USBH1_DATA1__USBH1_DATA1 IOMUX_PAD(0x68c, 0x28c, 0, __NA_, 0, MX51_USBH1_PAD_CTRL) +#define MX51_PAD_USBH1_DATA2__GPIO1_13 IOMUX_PAD(0x690, 0x290, 2, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_USBH1_DATA2__UART2_TXD IOMUX_PAD(0x690, 0x290, 1, __NA_, 0, MX51_UART_PAD_CTRL) +#define MX51_PAD_USBH1_DATA2__USBH1_DATA2 IOMUX_PAD(0x690, 0x290, 0, __NA_, 0, MX51_USBH1_PAD_CTRL) +#define MX51_PAD_USBH1_DATA3__GPIO1_14 IOMUX_PAD(0x694, 0x294, 2, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_USBH1_DATA3__UART2_RTS IOMUX_PAD(0x694, 0x294, 1, 0x9e8, 5, MX51_UART_PAD_CTRL) +#define MX51_PAD_USBH1_DATA3__USBH1_DATA3 IOMUX_PAD(0x694, 0x294, 0, __NA_, 0, MX51_USBH1_PAD_CTRL) +#define MX51_PAD_USBH1_DATA4__CSPI_SS0 IOMUX_PAD(0x698, 0x298, 1, __NA_, 0, MX51_ECSPI_PAD_CTRL) +#define MX51_PAD_USBH1_DATA4__GPIO1_15 IOMUX_PAD(0x698, 0x298, 2, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_USBH1_DATA4__USBH1_DATA4 IOMUX_PAD(0x698, 0x298, 0, __NA_, 0, MX51_USBH1_PAD_CTRL) +#define MX51_PAD_USBH1_DATA5__CSPI_SS1 IOMUX_PAD(0x69c, 0x29c, 1, 0x920, 0, MX51_ECSPI_PAD_CTRL) +#define MX51_PAD_USBH1_DATA5__GPIO1_16 IOMUX_PAD(0x69c, 0x29c, 2, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_USBH1_DATA5__USBH1_DATA5 IOMUX_PAD(0x69c, 0x29c, 0, __NA_, 0, MX51_USBH1_PAD_CTRL) +#define MX51_PAD_USBH1_DATA6__CSPI_SS3 IOMUX_PAD(0x6a0, 0x2a0, 1, 0x928, 1, MX51_ECSPI_PAD_CTRL) +#define MX51_PAD_USBH1_DATA6__GPIO1_17 IOMUX_PAD(0x6a0, 0x2a0, 2, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_USBH1_DATA6__USBH1_DATA6 IOMUX_PAD(0x6a0, 0x2a0, 0, __NA_, 0, MX51_USBH1_PAD_CTRL) +#define MX51_PAD_USBH1_DATA7__ECSPI1_SS3 IOMUX_PAD(0x6a4, 0x2a4, 1, __NA_, 0, MX51_ECSPI_PAD_CTRL) +#define MX51_PAD_USBH1_DATA7__ECSPI2_SS3 IOMUX_PAD(0x6a4, 0x2a4, 5, 0x934, 1, MX51_ECSPI_PAD_CTRL) +#define MX51_PAD_USBH1_DATA7__GPIO1_18 IOMUX_PAD(0x6a4, 0x2a4, 2, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_USBH1_DATA7__USBH1_DATA7 IOMUX_PAD(0x6a4, 0x2a4, 0, __NA_, 0, MX51_USBH1_PAD_CTRL) +#define MX51_PAD_DI1_PIN11__DI1_PIN11 IOMUX_PAD(0x6a8, 0x2a8, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DI1_PIN11__ECSPI1_SS2 IOMUX_PAD(0x6a8, 0x2a8, 7, __NA_, 0, MX51_ECSPI_PAD_CTRL) +#define MX51_PAD_DI1_PIN11__GPIO3_0 IOMUX_PAD(0x6a8, 0x2a8, 4, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_DI1_PIN12__DI1_PIN12 IOMUX_PAD(0x6ac, 0x2ac, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DI1_PIN12__GPIO3_1 IOMUX_PAD(0x6ac, 0x2ac, 4, 0x978, 1, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_DI1_PIN13__DI1_PIN13 IOMUX_PAD(0x6b0, 0x2b0, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DI1_PIN13__GPIO3_2 IOMUX_PAD(0x6b0, 0x2b0, 4, 0x97c, 1, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_DI1_D0_CS__DI1_D0_CS IOMUX_PAD(0x6b4, 0x2b4, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DI1_D0_CS__GPIO3_3 IOMUX_PAD(0x6b4, 0x2b4, 4, 0x980, 1, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_DI1_D1_CS__DI1_D1_CS IOMUX_PAD(0x6b8, 0x2b8, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DI1_D1_CS__DISP1_PIN14 IOMUX_PAD(0x6b8, 0x2b8, 2, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DI1_D1_CS__DISP1_PIN5 IOMUX_PAD(0x6b8, 0x2b8, 3, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DI1_D1_CS__GPIO3_4 IOMUX_PAD(0x6b8, 0x2b8, 4, 0x984, 1, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_DISPB2_SER_DIN__DISP1_PIN1 IOMUX_PAD(0x6bc, 0x2bc, 2, 0x9a4, 1, NO_PAD_CTRL) +#define MX51_PAD_DISPB2_SER_DIN__DISPB2_SER_DIN IOMUX_PAD(0x6bc, 0x2bc, 0, 0x9c4, 0, NO_PAD_CTRL) +#define MX51_PAD_DISPB2_SER_DIN__GPIO3_5 IOMUX_PAD(0x6bc, 0x2bc, 4, 0x988, 1, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_DISPB2_SER_DIO__DISP1_PIN6 IOMUX_PAD(0x6c0, 0x2c0, 3, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DISPB2_SER_DIO__DISPB2_SER_DIO IOMUX_PAD(0x6c0, 0x2c0, 0, 0x9c4, 1, NO_PAD_CTRL) +#define MX51_PAD_DISPB2_SER_DIO__GPIO3_6 IOMUX_PAD(0x6c0, 0x2c0, 4, 0x98c, 1, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_DISPB2_SER_CLK__DISP1_PIN17 IOMUX_PAD(0x6c4, 0x2c4, 2, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DISPB2_SER_CLK__DISP1_PIN7 IOMUX_PAD(0x6c4, 0x2c4, 3, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DISPB2_SER_CLK__DISPB2_SER_CLK IOMUX_PAD(0x6c4, 0x2c4, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DISPB2_SER_CLK__GPIO3_7 IOMUX_PAD(0x6c4, 0x2c4, 4, 0x990, 1, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_DISPB2_SER_RS__DISP1_EXT_CLK IOMUX_PAD(0x6c8, 0x2c8, 2, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DISPB2_SER_RS__DISP1_PIN16 IOMUX_PAD(0x6c8, 0x2c8, 2, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DISPB2_SER_RS__DISP1_PIN8 IOMUX_PAD(0x6c8, 0x2c8, 3, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DISPB2_SER_RS__DISPB2_SER_RS IOMUX_PAD(0x6c8, 0x2c8, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DISPB2_SER_RS__DISPB2_SER_RS IOMUX_PAD(0x6c8, 0x2c8, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DISPB2_SER_RS__GPIO3_8 IOMUX_PAD(0x6c8, 0x2c8, 4, 0x994, 1, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT0__DISP1_DAT0 IOMUX_PAD(0x6cc, 0x2cc, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT1__DISP1_DAT1 IOMUX_PAD(0x6d0, 0x2d0, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT2__DISP1_DAT2 IOMUX_PAD(0x6d4, 0x2d4, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT3__DISP1_DAT3 IOMUX_PAD(0x6d8, 0x2d8, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT4__DISP1_DAT4 IOMUX_PAD(0x6dc, 0x2dc, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT5__DISP1_DAT5 IOMUX_PAD(0x6e0, 0x2e0, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT6__BOOT_USB_SRC IOMUX_PAD(0x6e4, 0x2e4, 7, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT6__DISP1_DAT6 IOMUX_PAD(0x6e4, 0x2e4, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT7__BOOT_EEPROM_CFG IOMUX_PAD(0x6e8, 0x2e8, 7, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT7__DISP1_DAT7 IOMUX_PAD(0x6e8, 0x2e8, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT8__BOOT_SRC0 IOMUX_PAD(0x6ec, 0x2ec, 7, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT8__DISP1_DAT8 IOMUX_PAD(0x6ec, 0x2ec, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT9__BOOT_SRC1 IOMUX_PAD(0x6f0, 0x2f0, 7, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT9__DISP1_DAT9 IOMUX_PAD(0x6f0, 0x2f0, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT10__BOOT_SPARE_SIZE IOMUX_PAD(0x6f4, 0x2f4, 7, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT10__DISP1_DAT10 IOMUX_PAD(0x6f4, 0x2f4, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT11__BOOT_LPB_FREQ2 IOMUX_PAD(0x6f8, 0x2f8, 7, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT11__DISP1_DAT11 IOMUX_PAD(0x6f8, 0x2f8, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT12__BOOT_MLC_SEL IOMUX_PAD(0x6fc, 0x2fc, 7, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT12__DISP1_DAT12 IOMUX_PAD(0x6fc, 0x2fc, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT13__BOOT_MEM_CTL0 IOMUX_PAD(0x700, 0x300, 7, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT13__DISP1_DAT13 IOMUX_PAD(0x700, 0x300, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT14__BOOT_MEM_CTL1 IOMUX_PAD(0x704, 0x304, 7, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT14__DISP1_DAT14 IOMUX_PAD(0x704, 0x304, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT15__BOOT_BUS_WIDTH IOMUX_PAD(0x708, 0x308, 7, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT15__DISP1_DAT15 IOMUX_PAD(0x708, 0x308, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT16__BOOT_PAGE_SIZE0 IOMUX_PAD(0x70c, 0x30c, 7, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT16__DISP1_DAT16 IOMUX_PAD(0x70c, 0x30c, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT17__BOOT_PAGE_SIZE1 IOMUX_PAD(0x710, 0x310, 7, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT17__DISP1_DAT17 IOMUX_PAD(0x710, 0x310, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT18__BOOT_WEIM_MUXED0 IOMUX_PAD(0x714, 0x314, 7, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT18__DISP1_DAT18 IOMUX_PAD(0x714, 0x314, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT18__DISP2_PIN11 IOMUX_PAD(0x714, 0x314, 5, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT18__DISP2_PIN5 IOMUX_PAD(0x714, 0x314, 4, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT19__BOOT_WEIM_MUXED1 IOMUX_PAD(0x718, 0x318, 7, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT19__DISP1_DAT19 IOMUX_PAD(0x718, 0x318, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT19__DISP2_PIN12 IOMUX_PAD(0x718, 0x318, 5, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT19__DISP2_PIN6 IOMUX_PAD(0x718, 0x318, 4, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT20__BOOT_MEM_TYPE0 IOMUX_PAD(0x71c, 0x31c, 7, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT20__DISP1_DAT20 IOMUX_PAD(0x71c, 0x31c, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT20__DISP2_PIN13 IOMUX_PAD(0x71c, 0x31c, 5, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT20__DISP2_PIN7 IOMUX_PAD(0x71c, 0x31c, 4, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT21__BOOT_MEM_TYPE1 IOMUX_PAD(0x720, 0x320, 7, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT21__DISP1_DAT21 IOMUX_PAD(0x720, 0x320, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT21__DISP2_PIN14 IOMUX_PAD(0x720, 0x320, 5, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT21__DISP2_PIN8 IOMUX_PAD(0x720, 0x320, 4, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT22__BOOT_LPB_FREQ0 IOMUX_PAD(0x724, 0x324, 7, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT22__DISP1_DAT22 IOMUX_PAD(0x724, 0x324, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT22__DISP2_D0_CS IOMUX_PAD(0x724, 0x324, 6, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT22__DISP2_DAT16 IOMUX_PAD(0x724, 0x324, 5, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT23__BOOT_LPB_FREQ1 IOMUX_PAD(0x728, 0x328, 7, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT23__DISP1_DAT23 IOMUX_PAD(0x728, 0x328, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT23__DISP2_D1_CS IOMUX_PAD(0x728, 0x328, 6, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT23__DISP2_DAT17 IOMUX_PAD(0x728, 0x328, 5, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT23__DISP2_SER_CS IOMUX_PAD(0x728, 0x328, 4, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DI1_PIN3__DI1_PIN3 IOMUX_PAD(0x72c, 0x32c, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DI1_PIN2__DI1_PIN2 IOMUX_PAD(0x734, 0x330, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DI_GP2__DISP1_SER_CLK IOMUX_PAD(0x740, 0x338, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DI_GP2__DISP2_WAIT IOMUX_PAD(0x740, 0x338, 2, 0x9a8, 1, NO_PAD_CTRL) +#define MX51_PAD_DI_GP3__CSI1_DATA_EN IOMUX_PAD(0x744, 0x33c, 3, 0x9a0, 1, NO_PAD_CTRL) +#define MX51_PAD_DI_GP3__DISP1_SER_DIO IOMUX_PAD(0x744, 0x33c, 0, 0x9c0, 0, NO_PAD_CTRL) +#define MX51_PAD_DI_GP3__FEC_TX_ER IOMUX_PAD(0x744, 0x33c, 2, __NA_, 0, MX51_PAD_CTRL_5) +#define MX51_PAD_DI2_PIN4__CSI2_DATA_EN IOMUX_PAD(0x748, 0x340, 3, 0x99c, 1, NO_PAD_CTRL) +#define MX51_PAD_DI2_PIN4__DI2_PIN4 IOMUX_PAD(0x748, 0x340, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DI2_PIN4__FEC_CRS IOMUX_PAD(0x748, 0x340, 2, 0x950, 1, NO_PAD_CTRL) +#define MX51_PAD_DI2_PIN2__DI2_PIN2 IOMUX_PAD(0x74c, 0x344, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DI2_PIN2__FEC_MDC IOMUX_PAD(0x74c, 0x344, 2, __NA_, 0, MX51_PAD_CTRL_5) +#define MX51_PAD_DI2_PIN3__DI2_PIN3 IOMUX_PAD(0x750, 0x348, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DI2_PIN3__FEC_MDIO IOMUX_PAD(0x750, 0x348, 2, 0x954, 1, NO_PAD_CTRL) +#define MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK IOMUX_PAD(0x754, 0x34c, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 IOMUX_PAD(0x754, 0x34c, 2, 0x95c, 1, NO_PAD_CTRL) +#define MX51_PAD_DI_GP4__DI2_PIN15 IOMUX_PAD(0x758, 0x350, 4, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DI_GP4__DISP1_SER_DIN IOMUX_PAD(0x758, 0x350, 0, 0x9c0, 1, NO_PAD_CTRL) +#define MX51_PAD_DI_GP4__DISP2_PIN1 IOMUX_PAD(0x758, 0x350, 3, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DI_GP4__FEC_RDATA2 IOMUX_PAD(0x758, 0x350, 2, 0x960, 1, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT0__DISP2_DAT0 IOMUX_PAD(0x75c, 0x354, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT0__FEC_RDATA3 IOMUX_PAD(0x75c, 0x354, 2, 0x964, 1, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT0__KEY_COL6 IOMUX_PAD(0x75c, 0x354, 4, 0x9c8, 1, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT0__UART3_RXD IOMUX_PAD(0x75c, 0x354, 5, 0x9f4, 8, MX51_UART_PAD_CTRL) +#define MX51_PAD_DISP2_DAT0__USBH3_CLK IOMUX_PAD(0x75c, 0x354, 3, 0x9f8, 1, MX51_UART_PAD_CTRL) +#define MX51_PAD_DISP2_DAT1__DISP2_DAT1 IOMUX_PAD(0x760, 0x358, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT1__FEC_RX_ER IOMUX_PAD(0x760, 0x358, 2, 0x970, 1, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT1__KEY_COL7 IOMUX_PAD(0x760, 0x358, 4, 0x9cc, 1, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT1__UART3_TXD IOMUX_PAD(0x760, 0x358, 5, __NA_, 0, MX51_UART_PAD_CTRL) +#define MX51_PAD_DISP2_DAT1__USBH3_DIR IOMUX_PAD(0x760, 0x358, 3, 0xa1c, 1, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT2__DISP2_DAT2 IOMUX_PAD(0x764, 0x35c, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT3__DISP2_DAT3 IOMUX_PAD(0x768, 0x360, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT4__DISP2_DAT4 IOMUX_PAD(0x76c, 0x364, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT5__DISP2_DAT5 IOMUX_PAD(0x770, 0x368, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT6__DISP2_DAT6 IOMUX_PAD(0x774, 0x36c, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT6__FEC_TDATA1 IOMUX_PAD(0x774, 0x36c, 2, __NA_, 0, MX51_PAD_CTRL_5) +#define MX51_PAD_DISP2_DAT6__GPIO1_19 IOMUX_PAD(0x774, 0x36c, 5, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT6__KEY_ROW4 IOMUX_PAD(0x774, 0x36c, 4, 0x9d0, 1, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT6__USBH3_STP IOMUX_PAD(0x774, 0x36c, 3, 0xa24, 1, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT7__DISP2_DAT7 IOMUX_PAD(0x778, 0x370, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT7__FEC_TDATA2 IOMUX_PAD(0x778, 0x370, 2, __NA_, 0, MX51_PAD_CTRL_5) +#define MX51_PAD_DISP2_DAT7__GPIO1_29 IOMUX_PAD(0x778, 0x370, 5, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT7__KEY_ROW5 IOMUX_PAD(0x778, 0x370, 4, 0x9d4, 1, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT7__USBH3_NXT IOMUX_PAD(0x778, 0x370, 3, 0xa20, 1, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT8__DISP2_DAT8 IOMUX_PAD(0x77c, 0x374, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT8__FEC_TDATA3 IOMUX_PAD(0x77c, 0x374, 2, __NA_, 0, MX51_PAD_CTRL_5) +#define MX51_PAD_DISP2_DAT8__GPIO1_30 IOMUX_PAD(0x77c, 0x374, 5, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT8__KEY_ROW6 IOMUX_PAD(0x77c, 0x374, 4, 0x9d8, 1, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT8__USBH3_DATA0 IOMUX_PAD(0x77c, 0x374, 3, 0x9fc, 1, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT9__AUD6_RXC IOMUX_PAD(0x780, 0x378, 4, 0x8f4, 1, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT9__DISP2_DAT9 IOMUX_PAD(0x780, 0x378, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT9__FEC_TX_EN IOMUX_PAD(0x780, 0x378, 2, __NA_, 0, MX51_PAD_CTRL_5) +#define MX51_PAD_DISP2_DAT9__GPIO1_31 IOMUX_PAD(0x780, 0x378, 5, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT9__USBH3_DATA1 IOMUX_PAD(0x780, 0x378, 3, 0xa00, 1, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT10__DISP2_DAT10 IOMUX_PAD(0x784, 0x37c, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT10__DISP2_SER_CS IOMUX_PAD(0x784, 0x37c, 5, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT10__FEC_COL IOMUX_PAD(0x784, 0x37c, 2, 0x94c, 1, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT10__KEY_ROW7 IOMUX_PAD(0x784, 0x37c, 4, 0x9dc, 1, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT10__USBH3_DATA2 IOMUX_PAD(0x784, 0x37c, 3, 0xa04, 1, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT11__AUD6_TXD IOMUX_PAD(0x788, 0x380, 4, 0x8f0, 1, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT11__DISP2_DAT11 IOMUX_PAD(0x788, 0x380, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT11__FEC_RX_CLK IOMUX_PAD(0x788, 0x380, 2, 0x968, 1, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT11__GPIO1_10 IOMUX_PAD(0x788, 0x380, 7, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT11__USBH3_DATA3 IOMUX_PAD(0x788, 0x380, 3, 0xa08, 1, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT12__AUD6_RXD IOMUX_PAD(0x78c, 0x384, 4, 0x8ec, 1, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT12__DISP2_DAT12 IOMUX_PAD(0x78c, 0x384, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT12__FEC_RX_DV IOMUX_PAD(0x78c, 0x384, 2, 0x96c, 1, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT12__USBH3_DATA4 IOMUX_PAD(0x78c, 0x384, 3, 0xa0c, 1, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT13__AUD6_TXC IOMUX_PAD(0x790, 0x388, 4, 0x8fc, 1, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT13__DISP2_DAT13 IOMUX_PAD(0x790, 0x388, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT13__FEC_TX_CLK IOMUX_PAD(0x790, 0x388, 2, 0x974, 1, MX51_PAD_CTRL_4) +#define MX51_PAD_DISP2_DAT13__USBH3_DATA5 IOMUX_PAD(0x790, 0x388, 3, 0xa10, 1, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT14__AUD6_TXFS IOMUX_PAD(0x794, 0x38c, 4, 0x900, 1, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT14__DISP2_DAT14 IOMUX_PAD(0x794, 0x38c, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT14__FEC_RDATA0 IOMUX_PAD(0x794, 0x38c, 2, 0x958, 1, MX51_PAD_CTRL_4) +#define MX51_PAD_DISP2_DAT14__USBH3_DATA6 IOMUX_PAD(0x794, 0x38c, 3, 0xa14, 1, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT15__AUD6_RXFS IOMUX_PAD(0x798, 0x390, 4, 0x8f8, 1, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT15__DISP1_SER_CS IOMUX_PAD(0x798, 0x390, 5, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT15__DISP2_DAT15 IOMUX_PAD(0x798, 0x390, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT15__FEC_TDATA0 IOMUX_PAD(0x798, 0x390, 2, __NA_, 0, MX51_PAD_CTRL_5) +#define MX51_PAD_DISP2_DAT15__USBH3_DATA7 IOMUX_PAD(0x798, 0x390, 3, 0xa18, 1, NO_PAD_CTRL) +#define MX51_PAD_SD1_CMD__AUD5_RXFS IOMUX_PAD(0x79c, 0x394, 1, 0x8e0, 1, NO_PAD_CTRL) +#define MX51_PAD_SD1_CMD__CSPI_MOSI IOMUX_PAD(0x79c, 0x394, 2, 0x91c, 2, NO_PAD_CTRL) +#define MX51_PAD_SD1_CMD__SD1_CMD IOMUX_PAD(0x79c, 0x394, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL) +#define MX51_PAD_SD1_CLK__AUD5_RXC IOMUX_PAD(0x7a0, 0x398, 1, 0x8dc, 1, NO_PAD_CTRL) +#define MX51_PAD_SD1_CLK__CSPI_SCLK IOMUX_PAD(0x7a0, 0x398, 2, 0x914, 2, NO_PAD_CTRL) +#define MX51_PAD_SD1_CLK__SD1_CLK IOMUX_PAD(0x7a0, 0x398, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS) +#define MX51_PAD_SD1_DATA0__AUD5_TXD IOMUX_PAD(0x7a4, 0x39c, 1, 0x8d8, 2, NO_PAD_CTRL) +#define MX51_PAD_SD1_DATA0__CSPI_MISO IOMUX_PAD(0x7a4, 0x39c, 2, 0x918, 1, MX51_ECSPI_PAD_CTRL) +#define MX51_PAD_SD1_DATA0__SD1_DATA0 IOMUX_PAD(0x7a4, 0x39c, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL) +#define MX51_PAD_EIM_DA0__EIM_DA0 IOMUX_PAD(__NA_, 0x01c, 0, 0x000, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_DA1__EIM_DA1 IOMUX_PAD(__NA_, 0x020, 0, 0x000, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_DA2__EIM_DA2 IOMUX_PAD(__NA_, 0x024, 0, 0x000, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_DA3__EIM_DA3 IOMUX_PAD(__NA_, 0x028, 0, 0x000, 0, NO_PAD_CTRL) +#define MX51_PAD_SD1_DATA1__AUD5_RXD IOMUX_PAD(0x7a8, 0x3a0, 1, 0x8d4, 2, NO_PAD_CTRL) +#define MX51_PAD_SD1_DATA1__SD1_DATA1 IOMUX_PAD(0x7a8, 0x3a0, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL) +#define MX51_PAD_EIM_DA4__EIM_DA4 IOMUX_PAD(__NA_, 0x02c, 0, 0x000, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_DA5__EIM_DA5 IOMUX_PAD(__NA_, 0x030, 0, 0x000, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_DA6__EIM_DA6 IOMUX_PAD(__NA_, 0x034, 0, 0x000, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_DA7__EIM_DA7 IOMUX_PAD(__NA_, 0x038, 0, 0x000, 0, NO_PAD_CTRL) +#define MX51_PAD_SD1_DATA2__AUD5_TXC IOMUX_PAD(0x7ac, 0x3a4, 1, 0x8e4, 2, NO_PAD_CTRL) +#define MX51_PAD_SD1_DATA2__SD1_DATA2 IOMUX_PAD(0x7ac, 0x3a4, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL) +#define MX51_PAD_EIM_DA10__EIM_DA10 IOMUX_PAD(__NA_, 0x044, 0, 0x000, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_DA11__EIM_DA11 IOMUX_PAD(__NA_, 0x048, 0, 0x000, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_DA8__EIM_DA8 IOMUX_PAD(__NA_, 0x03c, 0, 0x000, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_DA9__EIM_DA9 IOMUX_PAD(__NA_, 0x040, 0, 0x000, 0, NO_PAD_CTRL) +#define MX51_PAD_SD1_DATA3__AUD5_TXFS IOMUX_PAD(0x7b0, 0x3a8, 1, 0x8e8, 2, NO_PAD_CTRL) +#define MX51_PAD_SD1_DATA3__CSPI_SS1 IOMUX_PAD(0x7b0, 0x3a8, 2, 0x920, 1, MX51_ECSPI_PAD_CTRL) +#define MX51_PAD_SD1_DATA3__SD1_DATA3 IOMUX_PAD(0x7b0, 0x3a8, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL) +#define MX51_PAD_GPIO1_0__CSPI_SS2 IOMUX_PAD(0x7b4, 0x3ac, 2, 0x924, 0, MX51_ECSPI_PAD_CTRL) +#define MX51_PAD_GPIO1_0__GPIO1_0 IOMUX_PAD(0x7b4, 0x3ac, 1, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO1_0__SD1_CD IOMUX_PAD(0x7b4, 0x3ac, 0, __NA_, 0, MX51_ESDHC_PAD_CTRL) +#define MX51_PAD_GPIO1_1__CSPI_MISO IOMUX_PAD(0x7b8, 0x3b0, 2, 0x918, 2, MX51_ECSPI_PAD_CTRL) +#define MX51_PAD_GPIO1_1__GPIO1_1 IOMUX_PAD(0x7b8, 0x3b0, 1, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO1_1__SD1_WP IOMUX_PAD(0x7b8, 0x3b0, 0, __NA_, 0, MX51_ESDHC_PAD_CTRL) +#define MX51_PAD_EIM_DA12__EIM_DA12 IOMUX_PAD(__NA_, 0x04c, 0, 0x000, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_DA13__EIM_DA13 IOMUX_PAD(__NA_, 0x050, 0, 0x000, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_DA14__EIM_DA14 IOMUX_PAD(__NA_, 0x054, 0, 0x000, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_DA15__EIM_DA15 IOMUX_PAD(__NA_, 0x058, 0, 0x000, 0, NO_PAD_CTRL) +#define MX51_PAD_SD2_CMD__CSPI_MOSI IOMUX_PAD(__NA_, 0x3b4, 2, 0x91c, 3, MX51_ECSPI_PAD_CTRL) +#define MX51_PAD_SD2_CMD__I2C1_SCL IOMUX_PAD(0x7bc, 0x3b4, 0x11, 0x9b0, 2, MX51_I2C_PAD_CTRL) +#define MX51_PAD_SD2_CMD__SD2_CMD IOMUX_PAD(0x7bc, 0x3b4, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL) +#define MX51_PAD_SD2_CLK__CSPI_SCLK IOMUX_PAD(0x7c0, 0x3b8, 2, 0x914, 3, MX51_ECSPI_PAD_CTRL) +#define MX51_PAD_SD2_CLK__I2C1_SDA IOMUX_PAD(0x7c0, 0x3b8, 0x11, 0x9b4, 2, MX51_I2C_PAD_CTRL) +#define MX51_PAD_SD2_CLK__SD2_CLK IOMUX_PAD(0x7c0, 0x3b8, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS) +#define MX51_PAD_SD2_DATA0__CSPI_MISO IOMUX_PAD(0x7c4, 0x3bc, 2, 0x918, 3, MX51_ECSPI_PAD_CTRL) +#define MX51_PAD_SD2_DATA0__SD1_DAT4 IOMUX_PAD(0x7c4, 0x3bc, 1, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_SD2_DATA0__SD2_DATA0 IOMUX_PAD(0x7c4, 0x3bc, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL) +#define MX51_PAD_SD2_DATA1__SD1_DAT5 IOMUX_PAD(0x7c8, 0x3c0, 1, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_SD2_DATA1__SD2_DATA1 IOMUX_PAD(0x7c8, 0x3c0, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL) +#define MX51_PAD_SD2_DATA1__USBH3_H2_DP IOMUX_PAD(0x7c8, 0x3c0, 2, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_SD2_DATA2__SD1_DAT6 IOMUX_PAD(0x7cc, 0x3c4, 1, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_SD2_DATA2__SD2_DATA2 IOMUX_PAD(0x7cc, 0x3c4, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL) +#define MX51_PAD_SD2_DATA2__USBH3_H2_DM IOMUX_PAD(0x7cc, 0x3c4, 2, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_SD2_DATA3__CSPI_SS2 IOMUX_PAD(0x7d0, 0x3c8, 2, 0x924, 1, MX51_ECSPI_PAD_CTRL) +#define MX51_PAD_SD2_DATA3__SD1_DAT7 IOMUX_PAD(0x7d0, 0x3c8, 1, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_SD2_DATA3__SD2_DATA3 IOMUX_PAD(0x7d0, 0x3c8, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL) +#define MX51_PAD_GPIO1_2__CCM_OUT_2 IOMUX_PAD(0x7d4, 0x3cc, 5, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO1_2__GPIO1_2 IOMUX_PAD(0x7d4, 0x3cc, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO1_2__I2C2_SCL IOMUX_PAD(0x7d4, 0x3cc, 0x12, 0x9b8, 3, MX51_I2C_PAD_CTRL) +#define MX51_PAD_GPIO1_2__PLL1_BYP IOMUX_PAD(0x7d4, 0x3cc, 7, 0x90c, 1, NO_PAD_CTRL) +#define MX51_PAD_GPIO1_2__PWM1_PWMO IOMUX_PAD(0x7d4, 0x3cc, 1, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO1_3__GPIO1_3 IOMUX_PAD(0x7d8, 0x3d0, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO1_3__I2C2_SDA IOMUX_PAD(0x7d8, 0x3d0, 0x12, 0x9bc, 3, MX51_I2C_PAD_CTRL) +#define MX51_PAD_GPIO1_3__PLL2_BYP IOMUX_PAD(0x7d8, 0x3d0, 7, 0x910, 1, NO_PAD_CTRL) +#define MX51_PAD_GPIO1_3__PWM2_PWMO IOMUX_PAD(0x7d8, 0x3d0, 1, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_PMIC_INT_REQ__PMIC_INT_REQ IOMUX_PAD(0x7fc, 0x3d4, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_PMIC_INT_REQ__PMIC_PMU_IRQ_B IOMUX_PAD(0x7fc, 0x3d4, 1, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO1_4__DISP2_EXT_CLK IOMUX_PAD(0x804, 0x3d8, 4, 0x908, 1, NO_PAD_CTRL) +#define MX51_PAD_GPIO1_4__EIM_RDY IOMUX_PAD(0x804, 0x3d8, 3, 0x938, 1, NO_PAD_CTRL) +#define MX51_PAD_GPIO1_4__GPIO1_4 IOMUX_PAD(0x804, 0x3d8, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO1_4__WDOG1_WDOG_B IOMUX_PAD(0x804, 0x3d8, 2, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO1_5__CSI2_MCLK IOMUX_PAD(0x808, 0x3dc, 6, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO1_5__DISP2_PIN16 IOMUX_PAD(0x808, 0x3dc, 3, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO1_5__GPIO1_5 IOMUX_PAD(0x808, 0x3dc, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO1_5__WDOG2_WDOG_B IOMUX_PAD(0x808, 0x3dc, 2, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO1_6__DISP2_PIN17 IOMUX_PAD(0x80c, 0x3e0, 4, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO1_6__GPIO1_6 IOMUX_PAD(0x80c, 0x3e0, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO1_6__REF_EN_B IOMUX_PAD(0x80c, 0x3e0, 3, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO1_7__CCM_OUT_0 IOMUX_PAD(0x810, 0x3e4, 3, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO1_7__GPIO1_7 IOMUX_PAD(0x810, 0x3e4, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO1_7__SD2_WP IOMUX_PAD(0x810, 0x3e4, 6, __NA_, 0, MX51_ESDHC_PAD_CTRL) +#define MX51_PAD_GPIO1_7__SPDIF_OUT1 IOMUX_PAD(0x810, 0x3e4, 2, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO1_8__CSI2_DATA_EN IOMUX_PAD(0x814, 0x3e8, 2, 0x99c, 2, NO_PAD_CTRL) +#define MX51_PAD_GPIO1_8__GPIO1_8 IOMUX_PAD(0x814, 0x3e8, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO1_8__SD2_CD IOMUX_PAD(0x814, 0x3e8, 6, __NA_, 0, MX51_ESDHC_PAD_CTRL) +#define MX51_PAD_GPIO1_8__USBH3_PWR IOMUX_PAD(0x814, 0x3e8, 1, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO1_9__CCM_OUT_1 IOMUX_PAD(0x818, 0x3ec, 3, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO1_9__DISP2_D1_CS IOMUX_PAD(0x818, 0x3ec, 2, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO1_9__DISP2_SER_CS IOMUX_PAD(0x818, 0x3ec, 7, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO1_9__GPIO1_9 IOMUX_PAD(0x818, 0x3ec, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO1_9__SD2_LCTL IOMUX_PAD(0x818, 0x3ec, 6, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO1_9__USBH3_OC IOMUX_PAD(0x818, 0x3ec, 1, __NA_, 0, NO_PAD_CTRL) - #endif /* __MACH_IOMUX_MX51_H__ */ + #endif /* __IOMUX_MX51_H__ */ diff --cc arch/arm/include/asm/arch-mx5/iomux-mx53.h index 4361cd64c8,0000000000..6bbe0778a7 mode 100644,000000..100644 --- a/arch/arm/include/asm/arch-mx5/iomux-mx53.h +++ b/arch/arm/include/asm/arch-mx5/iomux-mx53.h @@@ -1,1219 -1,0 +1,1240 @@@ +/* + * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc.. + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + - #ifndef __MACH_IOMUX_MX53_H__ - #define __MACH_IOMUX_MX53_H__ ++#ifndef __ASM_ARCH_IOMUX_MX53_H__ ++#define __ASM_ARCH_IOMUX_MX53_H__ + - #include "iomux-v3.h" ++#include ++ ++#define PAD_CTL_DVS (1 << 13) ++#define PAD_CTL_INPUT_DDR (1 << 9) ++#define PAD_CTL_HYS (1 << 8) ++ ++#define PAD_CTL_PKE (1 << 7) ++#define PAD_CTL_PUE (1 << 6 | PAD_CTL_PKE) ++#define PAD_CTL_PUS_100K_DOWN (0 << 4 | PAD_CTL_PUE) ++#define PAD_CTL_PUS_47K_UP (1 << 4 | PAD_CTL_PUE) ++#define PAD_CTL_PUS_100K_UP (2 << 4 | PAD_CTL_PUE) ++#define PAD_CTL_PUS_22K_UP (3 << 4 | PAD_CTL_PUE) ++ ++#define PAD_CTL_ODE (1 << 3) ++ ++#define PAD_CTL_DSE_LOW (0 << 1) ++#define PAD_CTL_DSE_MED (1 << 1) ++#define PAD_CTL_DSE_HIGH (2 << 1) ++#define PAD_CTL_DSE_MAX (3 << 1) ++ ++#define PAD_CTL_SRE_FAST (1 << 0) ++#define PAD_CTL_SRE_SLOW (0 << 0) + +/* These 2 defines are for pins that may not have a mux register, but could + * have a pad setting register, and vice-versa. */ +#define __NA_ 0x00 + +#define MX53_UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST | PAD_CTL_HYS) - #define MX53_SDHC_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_PUE | \ ++#define MX53_SDHC_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_HIGH | \ + PAD_CTL_SRE_FAST) + + +#define MX53_PAD_GPIO_19__KPP_COL_5 IOMUX_PAD(0x348, 0x020, 0, 0x840, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_19__GPIO4_5 IOMUX_PAD(0x348, 0x020, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_19__CCM_CLKO IOMUX_PAD(0x348, 0x020, 2, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_19__SPDIF_OUT1 IOMUX_PAD(0x348, 0x020, 3, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_19__RTC_CE_RTC_EXT_TRIG2 IOMUX_PAD(0x348, 0x020, 4, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_19__ECSPI1_RDY IOMUX_PAD(0x348, 0x020, 5, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_19__FEC_TDATA_3 IOMUX_PAD(0x348, 0x020, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_19__SRC_INT_BOOT IOMUX_PAD(0x348, 0x020, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_COL0__KPP_COL_0 IOMUX_PAD(0x34C, 0x024, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_COL0__GPIO4_6 IOMUX_PAD(0x34C, 0x024, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC IOMUX_PAD(0x34C, 0x024, 2, 0x758, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_COL0__UART4_TXD_MUX IOMUX_PAD(0x34C, 0x024, 4, __NA_, 0, MX53_UART_PAD_CTRL) +#define MX53_PAD_KEY_COL0__ECSPI1_SCLK IOMUX_PAD(0x34C, 0x024, 5, 0x79C, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_COL0__FEC_RDATA_3 IOMUX_PAD(0x34C, 0x024, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_COL0__SRC_ANY_PU_RST IOMUX_PAD(0x34C, 0x024, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_ROW0__KPP_ROW_0 IOMUX_PAD(0x350, 0x028, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_ROW0__GPIO4_7 IOMUX_PAD(0x350, 0x028, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD IOMUX_PAD(0x350, 0x028, 2, 0x74C, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_ROW0__UART4_RXD_MUX IOMUX_PAD(0x350, 0x028, 4, 0x890, 1, MX53_UART_PAD_CTRL) +#define MX53_PAD_KEY_ROW0__ECSPI1_MOSI IOMUX_PAD(0x350, 0x028, 5, 0x7A4, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_ROW0__FEC_TX_ER IOMUX_PAD(0x350, 0x028, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_COL1__KPP_COL_1 IOMUX_PAD(0x354, 0x02C, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_COL1__GPIO4_8 IOMUX_PAD(0x354, 0x02C, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS IOMUX_PAD(0x354, 0x02C, 2, 0x75C, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_COL1__UART5_TXD_MUX IOMUX_PAD(0x354, 0x02C, 4, __NA_, 0, MX53_UART_PAD_CTRL) +#define MX53_PAD_KEY_COL1__ECSPI1_MISO IOMUX_PAD(0x354, 0x02C, 5, 0x7A0, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_COL1__FEC_RX_CLK IOMUX_PAD(0x354, 0x02C, 6, 0x808, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_COL1__USBPHY1_TXREADY IOMUX_PAD(0x354, 0x02C, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_ROW1__KPP_ROW_1 IOMUX_PAD(0x358, 0x030, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_ROW1__GPIO4_9 IOMUX_PAD(0x358, 0x030, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD IOMUX_PAD(0x358, 0x030, 2, 0x748, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_ROW1__UART5_RXD_MUX IOMUX_PAD(0x358, 0x030, 4, 0x898, 1, MX53_UART_PAD_CTRL) +#define MX53_PAD_KEY_ROW1__ECSPI1_SS0 IOMUX_PAD(0x358, 0x030, 5, 0x7A8, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_ROW1__FEC_COL IOMUX_PAD(0x358, 0x030, 6, 0x800, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_ROW1__USBPHY1_RXVALID IOMUX_PAD(0x358, 0x030, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_COL2__KPP_COL_2 IOMUX_PAD(0x35C, 0x034, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_COL2__GPIO4_10 IOMUX_PAD(0x35C, 0x034, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_COL2__CAN1_TXCAN IOMUX_PAD(0x35C, 0x034, 2, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_COL2__FEC_MDIO IOMUX_PAD(0x35C, 0x034, 4, 0x804, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_COL2__ECSPI1_SS1 IOMUX_PAD(0x35C, 0x034, 5, 0x7AC, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_COL2__FEC_RDATA_2 IOMUX_PAD(0x35C, 0x034, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_COL2__USBPHY1_RXACTIVE IOMUX_PAD(0x35C, 0x034, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_ROW2__KPP_ROW_2 IOMUX_PAD(0x360, 0x038, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_ROW2__GPIO4_11 IOMUX_PAD(0x360, 0x038, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_ROW2__CAN1_RXCAN IOMUX_PAD(0x360, 0x038, 2, 0x760, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_ROW2__FEC_MDC IOMUX_PAD(0x360, 0x038, 4, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_ROW2__ECSPI1_SS2 IOMUX_PAD(0x360, 0x038, 5, 0x7B0, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_ROW2__FEC_TDATA_2 IOMUX_PAD(0x360, 0x038, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_ROW2__USBPHY1_RXERROR IOMUX_PAD(0x360, 0x038, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_COL3__KPP_COL_3 IOMUX_PAD(0x364, 0x03C, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_COL3__GPIO4_12 IOMUX_PAD(0x364, 0x03C, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_COL3__USBOH3_H2_DP IOMUX_PAD(0x364, 0x03C, 2, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_COL3__SPDIF_IN1 IOMUX_PAD(0x364, 0x03C, 3, 0x870, 0, NO_PAD_CTRL) - #define MX53_PAD_KEY_COL3__I2C2_SCL IOMUX_PAD(0x364, 0x03C, 4 | IOMUX_CONFIG_SION, 0x81C, 0, NO_PAD_CTRL) ++#define MX53_PAD_KEY_COL3__I2C2_SCL IOMUX_PAD(0x364, 0x03C, 4 | MUX_CONFIG_SION, 0x81C, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_COL3__ECSPI1_SS3 IOMUX_PAD(0x364, 0x03C, 5, 0x7B4, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_COL3__FEC_CRS IOMUX_PAD(0x364, 0x03C, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_COL3__USBPHY1_SIECLOCK IOMUX_PAD(0x364, 0x03C, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_ROW3__KPP_ROW_3 IOMUX_PAD(0x368, 0x040, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_ROW3__GPIO4_13 IOMUX_PAD(0x368, 0x040, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_ROW3__USBOH3_H2_DM IOMUX_PAD(0x368, 0x040, 2, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_ROW3__CCM_ASRC_EXT_CLK IOMUX_PAD(0x368, 0x040, 3, 0x768, 0, NO_PAD_CTRL) - #define MX53_PAD_KEY_ROW3__I2C2_SDA IOMUX_PAD(0x368, 0x040, 4 | IOMUX_CONFIG_SION, 0x820, 0, NO_PAD_CTRL) ++#define MX53_PAD_KEY_ROW3__I2C2_SDA IOMUX_PAD(0x368, 0x040, 4 | MUX_CONFIG_SION, 0x820, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_ROW3__OSC32K_32K_OUT IOMUX_PAD(0x368, 0x040, 5, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_ROW3__CCM_PLL4_BYP IOMUX_PAD(0x368, 0x040, 6, 0x77C, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_ROW3__USBPHY1_LINESTATE_0 IOMUX_PAD(0x368, 0x040, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_COL4__KPP_COL_4 IOMUX_PAD(0x36C, 0x044, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_COL4__GPIO4_14 IOMUX_PAD(0x36C, 0x044, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_COL4__CAN2_TXCAN IOMUX_PAD(0x36C, 0x044, 2, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_COL4__IPU_SISG_4 IOMUX_PAD(0x36C, 0x044, 3, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_COL4__UART5_RTS IOMUX_PAD(0x36C, 0x044, 4, 0x894, 0, MX53_UART_PAD_CTRL) +#define MX53_PAD_KEY_COL4__USBOH3_USBOTG_OC IOMUX_PAD(0x36C, 0x044, 5, 0x89C, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_COL4__USBPHY1_LINESTATE_1 IOMUX_PAD(0x36C, 0x044, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_ROW4__KPP_ROW_4 IOMUX_PAD(0x370, 0x048, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_ROW4__GPIO4_15 IOMUX_PAD(0x370, 0x048, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_ROW4__CAN2_RXCAN IOMUX_PAD(0x370, 0x048, 2, 0x764, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_ROW4__IPU_SISG_5 IOMUX_PAD(0x370, 0x048, 3, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_ROW4__UART5_CTS IOMUX_PAD(0x370, 0x048, 4, __NA_, 0, MX53_UART_PAD_CTRL) +#define MX53_PAD_KEY_ROW4__USBOH3_USBOTG_PWR IOMUX_PAD(0x370, 0x048, 5, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_ROW4__USBPHY1_VBUSVALID IOMUX_PAD(0x370, 0x048, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK IOMUX_PAD(0x378, 0x04C, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DI0_DISP_CLK__GPIO4_16 IOMUX_PAD(0x378, 0x04C, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DI0_DISP_CLK__USBOH3_USBH2_DIR IOMUX_PAD(0x378, 0x04C, 2, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DI0_DISP_CLK__SDMA_DEBUG_CORE_STATE_0 IOMUX_PAD(0x378, 0x04C, 5, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DI0_DISP_CLK__EMI_EMI_DEBUG_0 IOMUX_PAD(0x378, 0x04C, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DI0_DISP_CLK__USBPHY1_AVALID IOMUX_PAD(0x378, 0x04C, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DI0_PIN15__IPU_DI0_PIN15 IOMUX_PAD(0x37C, 0x050, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DI0_PIN15__GPIO4_17 IOMUX_PAD(0x37C, 0x050, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DI0_PIN15__AUDMUX_AUD6_TXC IOMUX_PAD(0x37C, 0x050, 2, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DI0_PIN15__SDMA_DEBUG_CORE_STATE_1 IOMUX_PAD(0x37C, 0x050, 5, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DI0_PIN15__EMI_EMI_DEBUG_1 IOMUX_PAD(0x37C, 0x050, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DI0_PIN15__USBPHY1_BVALID IOMUX_PAD(0x37C, 0x050, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DI0_PIN2__IPU_DI0_PIN2 IOMUX_PAD(0x380, 0x054, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DI0_PIN2__GPIO4_18 IOMUX_PAD(0x380, 0x054, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DI0_PIN2__AUDMUX_AUD6_TXD IOMUX_PAD(0x380, 0x054, 2, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DI0_PIN2__SDMA_DEBUG_CORE_STATE_2 IOMUX_PAD(0x380, 0x054, 5, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DI0_PIN2__EMI_EMI_DEBUG_2 IOMUX_PAD(0x380, 0x054, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DI0_PIN2__USBPHY1_ENDSESSION IOMUX_PAD(0x380, 0x054, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DI0_PIN3__IPU_DI0_PIN3 IOMUX_PAD(0x384, 0x058, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DI0_PIN3__GPIO4_19 IOMUX_PAD(0x384, 0x058, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS IOMUX_PAD(0x384, 0x058, 2, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DI0_PIN3__SDMA_DEBUG_CORE_STATE_3 IOMUX_PAD(0x384, 0x058, 5, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DI0_PIN3__EMI_EMI_DEBUG_3 IOMUX_PAD(0x384, 0x058, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DI0_PIN3__USBPHY1_IDDIG IOMUX_PAD(0x384, 0x058, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DI0_PIN4__IPU_DI0_PIN4 IOMUX_PAD(0x388, 0x05C, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DI0_PIN4__GPIO4_20 IOMUX_PAD(0x388, 0x05C, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DI0_PIN4__AUDMUX_AUD6_RXD IOMUX_PAD(0x388, 0x05C, 2, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DI0_PIN4__ESDHC1_WP IOMUX_PAD(0x388, 0x05C, 3, 0x7FC, 0, NO_PAD_CTRL) +#define MX53_PAD_DI0_PIN4__SDMA_DEBUG_YIELD IOMUX_PAD(0x388, 0x05C, 5, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DI0_PIN4__EMI_EMI_DEBUG_4 IOMUX_PAD(0x388, 0x05C, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DI0_PIN4__USBPHY1_HOSTDISCONNECT IOMUX_PAD(0x388, 0x05C, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0 IOMUX_PAD(0x38C, 0x060, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT0__GPIO4_21 IOMUX_PAD(0x38C, 0x060, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT0__CSPI_SCLK IOMUX_PAD(0x38C, 0x060, 2, 0x780, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT0__USBOH3_USBH2_DATA_0 IOMUX_PAD(0x38C, 0x060, 3, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT0__SDMA_DEBUG_CORE_RUN IOMUX_PAD(0x38C, 0x060, 5, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT0__EMI_EMI_DEBUG_5 IOMUX_PAD(0x38C, 0x060, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT0__USBPHY2_TXREADY IOMUX_PAD(0x38C, 0x060, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1 IOMUX_PAD(0x390, 0x064, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT1__GPIO4_22 IOMUX_PAD(0x390, 0x064, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT1__CSPI_MOSI IOMUX_PAD(0x390, 0x064, 2, 0x788, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT1__USBOH3_USBH2_DATA_1 IOMUX_PAD(0x390, 0x064, 3, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT1__SDMA_DEBUG_EVENT_CHANNEL_SEL \ + IOMUX_PAD(0x390, 0x064, 5, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT1__EMI_EMI_DEBUG_6 IOMUX_PAD(0x390, 0x064, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT1__USBPHY2_RXVALID IOMUX_PAD(0x390, 0x064, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2 IOMUX_PAD(0x394, 0x068, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT2__GPIO4_23 IOMUX_PAD(0x394, 0x068, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT2__CSPI_MISO IOMUX_PAD(0x394, 0x068, 2, 0x784, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT2__USBOH3_USBH2_DATA_2 IOMUX_PAD(0x394, 0x068, 3, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT2__SDMA_DEBUG_MODE IOMUX_PAD(0x394, 0x068, 5, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT2__EMI_EMI_DEBUG_7 IOMUX_PAD(0x394, 0x068, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT2__USBPHY2_RXACTIVE IOMUX_PAD(0x394, 0x068, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3 IOMUX_PAD(0x398, 0x06C, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT3__GPIO4_24 IOMUX_PAD(0x398, 0x06C, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT3__CSPI_SS0 IOMUX_PAD(0x398, 0x06C, 2, 0x78C, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT3__USBOH3_USBH2_DATA_3 IOMUX_PAD(0x398, 0x06C, 3, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT3__SDMA_DEBUG_BUS_ERROR IOMUX_PAD(0x398, 0x06C, 5, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT3__EMI_EMI_DEBUG_8 IOMUX_PAD(0x398, 0x06C, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT3__USBPHY2_RXERROR IOMUX_PAD(0x398, 0x06C, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4 IOMUX_PAD(0x39C, 0x070, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT4__GPIO4_25 IOMUX_PAD(0x39C, 0x070, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT4__CSPI_SS1 IOMUX_PAD(0x39C, 0x070, 2, 0x790, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT4__USBOH3_USBH2_DATA_4 IOMUX_PAD(0x39C, 0x070, 3, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT4__SDMA_DEBUG_BUS_RWB IOMUX_PAD(0x39C, 0x070, 5, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT4__EMI_EMI_DEBUG_9 IOMUX_PAD(0x39C, 0x070, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT4__USBPHY2_SIECLOCK IOMUX_PAD(0x39C, 0x070, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5 IOMUX_PAD(0x3A0, 0x074, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT5__GPIO4_26 IOMUX_PAD(0x3A0, 0x074, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT5__CSPI_SS2 IOMUX_PAD(0x3A0, 0x074, 2, 0x794, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT5__USBOH3_USBH2_DATA_5 IOMUX_PAD(0x3A0, 0x074, 3, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT5__SDMA_DEBUG_MATCHED_DMBUS IOMUX_PAD(0x3A0, 0x074, 5, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT5__EMI_EMI_DEBUG_10 IOMUX_PAD(0x3A0, 0x074, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT5__USBPHY2_LINESTATE_0 IOMUX_PAD(0x3A0, 0x074, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6 IOMUX_PAD(0x3A4, 0x078, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT6__GPIO4_27 IOMUX_PAD(0x3A4, 0x078, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT6__CSPI_SS3 IOMUX_PAD(0x3A4, 0x078, 2, 0x798, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT6__USBOH3_USBH2_DATA_6 IOMUX_PAD(0x3A4, 0x078, 3, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT6__SDMA_DEBUG_RTBUFFER_WRITE IOMUX_PAD(0x3A4, 0x078, 5, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT6__EMI_EMI_DEBUG_11 IOMUX_PAD(0x3A4, 0x078, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT6__USBPHY2_LINESTATE_1 IOMUX_PAD(0x3A4, 0x078, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7 IOMUX_PAD(0x3A8, 0x07C, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT7__GPIO4_28 IOMUX_PAD(0x3A8, 0x07C, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT7__CSPI_RDY IOMUX_PAD(0x3A8, 0x07C, 2, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT7__USBOH3_USBH2_DATA_7 IOMUX_PAD(0x3A8, 0x07C, 3, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT7__SDMA_DEBUG_EVENT_CHANNEL_0 IOMUX_PAD(0x3A8, 0x07C, 5, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT7__EMI_EMI_DEBUG_12 IOMUX_PAD(0x3A8, 0x07C, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT7__USBPHY2_VBUSVALID IOMUX_PAD(0x3A8, 0x07C, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8 IOMUX_PAD(0x3AC, 0x080, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT8__GPIO4_29 IOMUX_PAD(0x3AC, 0x080, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT8__PWM1_PWMO IOMUX_PAD(0x3AC, 0x080, 2, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT8__WDOG1_WDOG_B IOMUX_PAD(0x3AC, 0x080, 3, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT8__SDMA_DEBUG_EVENT_CHANNEL_1 IOMUX_PAD(0x3AC, 0x080, 5, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT8__EMI_EMI_DEBUG_13 IOMUX_PAD(0x3AC, 0x080, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT8__USBPHY2_AVALID IOMUX_PAD(0x3AC, 0x080, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9 IOMUX_PAD(0x3B0, 0x084, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT9__GPIO4_30 IOMUX_PAD(0x3B0, 0x084, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT9__PWM2_PWMO IOMUX_PAD(0x3B0, 0x084, 2, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT9__WDOG2_WDOG_B IOMUX_PAD(0x3B0, 0x084, 3, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT9__SDMA_DEBUG_EVENT_CHANNEL_2 IOMUX_PAD(0x3B0, 0x084, 5, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT9__EMI_EMI_DEBUG_14 IOMUX_PAD(0x3B0, 0x084, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT9__USBPHY2_VSTATUS_0 IOMUX_PAD(0x3B0, 0x084, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10 IOMUX_PAD(0x3B4, 0x088, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT10__GPIO4_31 IOMUX_PAD(0x3B4, 0x088, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT10__USBOH3_USBH2_STP IOMUX_PAD(0x3B4, 0x088, 2, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT10__SDMA_DEBUG_EVENT_CHANNEL_3 \ + IOMUX_PAD(0x3B4, 0x088, 5, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT10__EMI_EMI_DEBUG_15 IOMUX_PAD(0x3B4, 0x088, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT10__USBPHY2_VSTATUS_1 IOMUX_PAD(0x3B4, 0x088, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11 IOMUX_PAD(0x3B8, 0x08C, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT11__GPIO5_5 IOMUX_PAD(0x3B8, 0x08C, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT11__USBOH3_USBH2_NXT IOMUX_PAD(0x3B8, 0x08C, 2, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT11__SDMA_DEBUG_EVENT_CHANNEL_4 \ + IOMUX_PAD(0x3B8, 0x08C, 5, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT11__EMI_EMI_DEBUG_16 IOMUX_PAD(0x3B8, 0x08C, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT11__USBPHY2_VSTATUS_2 IOMUX_PAD(0x3B8, 0x08C, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12 IOMUX_PAD(0x3BC, 0x090, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT12__GPIO5_6 IOMUX_PAD(0x3BC, 0x090, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT12__USBOH3_USBH2_CLK IOMUX_PAD(0x3BC, 0x090, 2, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT12__SDMA_DEBUG_EVENT_CHANNEL_5 \ + IOMUX_PAD(0x3BC, 0x090, 5, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT12__EMI_EMI_DEBUG_17 IOMUX_PAD(0x3BC, 0x090, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT12__USBPHY2_VSTATUS_3 IOMUX_PAD(0x3BC, 0x090, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13 IOMUX_PAD(0x3C0, 0x094, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT13__GPIO5_7 IOMUX_PAD(0x3C0, 0x094, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT13__AUDMUX_AUD5_RXFS IOMUX_PAD(0x3C0, 0x094, 3, 0x754, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT13__SDMA_DEBUG_EVT_CHN_LINES_0 \ + IOMUX_PAD(0x3C0, 0x094, 5, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT13__EMI_EMI_DEBUG_18 IOMUX_PAD(0x3C0, 0x094, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT13__USBPHY2_VSTATUS_4 IOMUX_PAD(0x3C0, 0x094, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14 IOMUX_PAD(0x3C4, 0x098, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT14__GPIO5_8 IOMUX_PAD(0x3C4, 0x098, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT14__AUDMUX_AUD5_RXC IOMUX_PAD(0x3C4, 0x098, 3, 0x750, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT14__SDMA_DEBUG_EVT_CHN_LINES_1 \ + IOMUX_PAD(0x3C4, 0x098, 5, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT14__EMI_EMI_DEBUG_19 IOMUX_PAD(0x3C4, 0x098, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT14__USBPHY2_VSTATUS_5 IOMUX_PAD(0x3C4, 0x098, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15 IOMUX_PAD(0x3C8, 0x09C, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT15__GPIO5_9 IOMUX_PAD(0x3C8, 0x09C, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT15__ECSPI1_SS1 IOMUX_PAD(0x3C8, 0x09C, 2, 0x7AC, 1, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT15__ECSPI2_SS1 IOMUX_PAD(0x3C8, 0x09C, 3, 0x7C8, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT15__SDMA_DEBUG_EVT_CHN_LINES_2 \ + IOMUX_PAD(0x3C8, 0x09C, 5, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT15__EMI_EMI_DEBUG_20 IOMUX_PAD(0x3C8, 0x09C, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT15__USBPHY2_VSTATUS_6 IOMUX_PAD(0x3C8, 0x09C, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16 IOMUX_PAD(0x3CC, 0x0A0, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT16__GPIO5_10 IOMUX_PAD(0x3CC, 0x0A0, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT16__ECSPI2_MOSI IOMUX_PAD(0x3CC, 0x0A0, 2, 0x7C0, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC IOMUX_PAD(0x3CC, 0x0A0, 3, 0x758, 1, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT16__SDMA_EXT_EVENT_0 IOMUX_PAD(0x3CC, 0x0A0, 4, 0x868, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT16__SDMA_DEBUG_EVT_CHN_LINES_3 \ + IOMUX_PAD(0x3CC, 0x0A0, 5, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT16__EMI_EMI_DEBUG_21 IOMUX_PAD(0x3CC, 0x0A0, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT16__USBPHY2_VSTATUS_7 IOMUX_PAD(0x3CC, 0x0A0, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17 IOMUX_PAD(0x3D0, 0x0A4, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT17__GPIO5_11 IOMUX_PAD(0x3D0, 0x0A4, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT17__ECSPI2_MISO IOMUX_PAD(0x3D0, 0x0A4, 2, 0x7BC, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD IOMUX_PAD(0x3D0, 0x0A4, 3, 0x74C, 1, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT17__SDMA_EXT_EVENT_1 IOMUX_PAD(0x3D0, 0x0A4, 4, 0x86C, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT17__SDMA_DEBUG_EVT_CHN_LINES_4 \ + IOMUX_PAD(0x3D0, 0x0A4, 5, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT17__EMI_EMI_DEBUG_22 IOMUX_PAD(0x3D0, 0x0A4, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18 IOMUX_PAD(0x3D4, 0x0A8, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT18__GPIO5_12 IOMUX_PAD(0x3D4, 0x0A8, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT18__ECSPI2_SS0 IOMUX_PAD(0x3D4, 0x0A8, 2, 0x7C4, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS IOMUX_PAD(0x3D4, 0x0A8, 3, 0x75C, 1, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT18__AUDMUX_AUD4_RXFS IOMUX_PAD(0x3D4, 0x0A8, 4, 0x73C, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT18__SDMA_DEBUG_EVT_CHN_LINES_5 \ + IOMUX_PAD(0x3D4, 0x0A8, 5, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT18__EMI_EMI_DEBUG_23 IOMUX_PAD(0x3D4, 0x0A8, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT18__EMI_WEIM_CS_2 IOMUX_PAD(0x3D4, 0x0A8, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19 IOMUX_PAD(0x3D8, 0x0AC, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT19__GPIO5_13 IOMUX_PAD(0x3D8, 0x0AC, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT19__ECSPI2_SCLK IOMUX_PAD(0x3D8, 0x0AC, 2, 0x7B8, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD IOMUX_PAD(0x3D8, 0x0AC, 3, 0x748, 1, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT19__AUDMUX_AUD4_RXC IOMUX_PAD(0x3D8, 0x0AC, 4, 0x738, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT19__SDMA_DEBUG_EVT_CHN_LINES_6 \ + IOMUX_PAD(0x3D8, 0x0AC, 5, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT19__EMI_EMI_DEBUG_24 IOMUX_PAD(0x3D8, 0x0AC, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT19__EMI_WEIM_CS_3 IOMUX_PAD(0x3D8, 0x0AC, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20 IOMUX_PAD(0x3DC, 0x0B0, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT20__GPIO5_14 IOMUX_PAD(0x3DC, 0x0B0, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT20__ECSPI1_SCLK IOMUX_PAD(0x3DC, 0x0B0, 2, 0x79C, 1, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT20__AUDMUX_AUD4_TXC IOMUX_PAD(0x3DC, 0x0B0, 3, 0x740, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT20__SDMA_DEBUG_EVT_CHN_LINES_7 \ + IOMUX_PAD(0x3DC, 0x0B0, 5, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT20__EMI_EMI_DEBUG_25 IOMUX_PAD(0x3DC, 0x0B0, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT20__SATA_PHY_TDI IOMUX_PAD(0x3DC, 0x0B0, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21 IOMUX_PAD(0x3E0, 0x0B4, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT21__GPIO5_15 IOMUX_PAD(0x3E0, 0x0B4, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT21__ECSPI1_MOSI IOMUX_PAD(0x3E0, 0x0B4, 2, 0x7A4, 1, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT21__AUDMUX_AUD4_TXD IOMUX_PAD(0x3E0, 0x0B4, 3, 0x734, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT21__SDMA_DEBUG_BUS_DEVICE_0 IOMUX_PAD(0x3E0, 0x0B4, 5, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT21__EMI_EMI_DEBUG_26 IOMUX_PAD(0x3E0, 0x0B4, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT21__SATA_PHY_TDO IOMUX_PAD(0x3E0, 0x0B4, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22 IOMUX_PAD(0x3E4, 0x0B8, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT22__GPIO5_16 IOMUX_PAD(0x3E4, 0x0B8, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT22__ECSPI1_MISO IOMUX_PAD(0x3E4, 0x0B8, 2, 0x7A0, 1, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT22__AUDMUX_AUD4_TXFS IOMUX_PAD(0x3E4, 0x0B8, 3, 0x744, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT22__SDMA_DEBUG_BUS_DEVICE_1 IOMUX_PAD(0x3E4, 0x0B8, 5, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT22__EMI_EMI_DEBUG_27 IOMUX_PAD(0x3E4, 0x0B8, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT22__SATA_PHY_TCK IOMUX_PAD(0x3E4, 0x0B8, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23 IOMUX_PAD(0x3E8, 0x0BC, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT23__GPIO5_17 IOMUX_PAD(0x3E8, 0x0BC, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT23__ECSPI1_SS0 IOMUX_PAD(0x3E8, 0x0BC, 2, 0x7A8, 1, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT23__AUDMUX_AUD4_RXD IOMUX_PAD(0x3E8, 0x0BC, 3, 0x730, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT23__SDMA_DEBUG_BUS_DEVICE_2 IOMUX_PAD(0x3E8, 0x0BC, 5, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT23__EMI_EMI_DEBUG_28 IOMUX_PAD(0x3E8, 0x0BC, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT23__SATA_PHY_TMS IOMUX_PAD(0x3E8, 0x0BC, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK IOMUX_PAD(0x3EC, 0x0C0, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_PIXCLK__GPIO5_18 IOMUX_PAD(0x3EC, 0x0C0, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_PIXCLK__SDMA_DEBUG_PC_0 IOMUX_PAD(0x3EC, 0x0C0, 5, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_PIXCLK__EMI_EMI_DEBUG_29 IOMUX_PAD(0x3EC, 0x0C0, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC IOMUX_PAD(0x3F0, 0x0C4, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_MCLK__GPIO5_19 IOMUX_PAD(0x3F0, 0x0C4, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_MCLK__CCM_CSI0_MCLK IOMUX_PAD(0x3F0, 0x0C4, 2, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_MCLK__SDMA_DEBUG_PC_1 IOMUX_PAD(0x3F0, 0x0C4, 5, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_MCLK__EMI_EMI_DEBUG_30 IOMUX_PAD(0x3F0, 0x0C4, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_MCLK__TPIU_TRCTL IOMUX_PAD(0x3F0, 0x0C4, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DATA_EN__IPU_CSI0_DATA_EN IOMUX_PAD(0x3F4, 0x0C8, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DATA_EN__GPIO5_20 IOMUX_PAD(0x3F4, 0x0C8, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DATA_EN__SDMA_DEBUG_PC_2 IOMUX_PAD(0x3F4, 0x0C8, 5, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DATA_EN__EMI_EMI_DEBUG_31 IOMUX_PAD(0x3F4, 0x0C8, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DATA_EN__TPIU_TRCLK IOMUX_PAD(0x3F4, 0x0C8, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC IOMUX_PAD(0x3F8, 0x0CC, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_VSYNC__GPIO5_21 IOMUX_PAD(0x3F8, 0x0CC, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_VSYNC__SDMA_DEBUG_PC_3 IOMUX_PAD(0x3F8, 0x0CC, 5, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_VSYNC__EMI_EMI_DEBUG_32 IOMUX_PAD(0x3F8, 0x0CC, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_VSYNC__TPIU_TRACE_0 IOMUX_PAD(0x3F8, 0x0CC, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT4__IPU_CSI0_D_4 IOMUX_PAD(0x3FC, 0x0D0, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT4__GPIO5_22 IOMUX_PAD(0x3FC, 0x0D0, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT4__KPP_COL_5 IOMUX_PAD(0x3FC, 0x0D0, 2, 0x840, 1, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT4__ECSPI1_SCLK IOMUX_PAD(0x3FC, 0x0D0, 3, 0x79C, 2, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT4__USBOH3_USBH3_STP IOMUX_PAD(0x3FC, 0x0D0, 4, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC IOMUX_PAD(0x3FC, 0x0D0, 5, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT4__EMI_EMI_DEBUG_33 IOMUX_PAD(0x3FC, 0x0D0, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT4__TPIU_TRACE_1 IOMUX_PAD(0x3FC, 0x0D0, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT5__IPU_CSI0_D_5 IOMUX_PAD(0x400, 0x0D4, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT5__GPIO5_23 IOMUX_PAD(0x400, 0x0D4, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT5__KPP_ROW_5 IOMUX_PAD(0x400, 0x0D4, 2, 0x84C, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT5__ECSPI1_MOSI IOMUX_PAD(0x400, 0x0D4, 3, 0x7A4, 2, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT5__USBOH3_USBH3_NXT IOMUX_PAD(0x400, 0x0D4, 4, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD IOMUX_PAD(0x400, 0x0D4, 5, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT5__EMI_EMI_DEBUG_34 IOMUX_PAD(0x400, 0x0D4, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT5__TPIU_TRACE_2 IOMUX_PAD(0x400, 0x0D4, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT6__IPU_CSI0_D_6 IOMUX_PAD(0x404, 0x0D8, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT6__GPIO5_24 IOMUX_PAD(0x404, 0x0D8, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT6__KPP_COL_6 IOMUX_PAD(0x404, 0x0D8, 2, 0x844, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT6__ECSPI1_MISO IOMUX_PAD(0x404, 0x0D8, 3, 0x7A0, 2, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT6__USBOH3_USBH3_CLK IOMUX_PAD(0x404, 0x0D8, 4, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS IOMUX_PAD(0x404, 0x0D8, 5, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT6__EMI_EMI_DEBUG_35 IOMUX_PAD(0x404, 0x0D8, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT6__TPIU_TRACE_3 IOMUX_PAD(0x404, 0x0D8, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT7__IPU_CSI0_D_7 IOMUX_PAD(0x408, 0x0DC, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT7__GPIO5_25 IOMUX_PAD(0x408, 0x0DC, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT7__KPP_ROW_6 IOMUX_PAD(0x408, 0x0DC, 2, 0x850, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT7__ECSPI1_SS0 IOMUX_PAD(0x408, 0x0DC, 3, 0x7A8, 2, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT7__USBOH3_USBH3_DIR IOMUX_PAD(0x408, 0x0DC, 4, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD IOMUX_PAD(0x408, 0x0DC, 5, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT7__EMI_EMI_DEBUG_36 IOMUX_PAD(0x408, 0x0DC, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT7__TPIU_TRACE_4 IOMUX_PAD(0x408, 0x0DC, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT8__IPU_CSI0_D_8 IOMUX_PAD(0x40C, 0x0E0, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT8__GPIO5_26 IOMUX_PAD(0x40C, 0x0E0, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT8__KPP_COL_7 IOMUX_PAD(0x40C, 0x0E0, 2, 0x848, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT8__ECSPI2_SCLK IOMUX_PAD(0x40C, 0x0E0, 3, 0x7B8, 1, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT8__USBOH3_USBH3_OC IOMUX_PAD(0x40C, 0x0E0, 4, __NA_, 0, NO_PAD_CTRL) - #define MX53_PAD_CSI0_DAT8__I2C1_SDA IOMUX_PAD(0x40C, 0x0E0, 5 | IOMUX_CONFIG_SION, 0x818, 0, NO_PAD_CTRL) ++#define MX53_PAD_CSI0_DAT8__I2C1_SDA IOMUX_PAD(0x40C, 0x0E0, 5 | MUX_CONFIG_SION, 0x818, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT8__EMI_EMI_DEBUG_37 IOMUX_PAD(0x40C, 0x0E0, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT8__TPIU_TRACE_5 IOMUX_PAD(0x40C, 0x0E0, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT9__IPU_CSI0_D_9 IOMUX_PAD(0x410, 0x0E4, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT9__GPIO5_27 IOMUX_PAD(0x410, 0x0E4, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT9__KPP_ROW_7 IOMUX_PAD(0x410, 0x0E4, 2, 0x854, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT9__ECSPI2_MOSI IOMUX_PAD(0x410, 0x0E4, 3, 0x7C0, 1, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT9__USBOH3_USBH3_PWR IOMUX_PAD(0x410, 0x0E4, 4, __NA_, 0, NO_PAD_CTRL) - #define MX53_PAD_CSI0_DAT9__I2C1_SCL IOMUX_PAD(0x410, 0x0E4, 5 | IOMUX_CONFIG_SION, 0x814, 0, NO_PAD_CTRL) ++#define MX53_PAD_CSI0_DAT9__I2C1_SCL IOMUX_PAD(0x410, 0x0E4, 5 | MUX_CONFIG_SION, 0x814, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT9__EMI_EMI_DEBUG_38 IOMUX_PAD(0x410, 0x0E4, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT9__TPIU_TRACE_6 IOMUX_PAD(0x410, 0x0E4, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT10__IPU_CSI0_D_10 IOMUX_PAD(0x414, 0x0E8, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT10__GPIO5_28 IOMUX_PAD(0x414, 0x0E8, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT10__UART1_TXD_MUX IOMUX_PAD(0x414, 0x0E8, 2, __NA_, 0, MX53_UART_PAD_CTRL) +#define MX53_PAD_CSI0_DAT10__ECSPI2_MISO IOMUX_PAD(0x414, 0x0E8, 3, 0x7BC, 1, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT10__AUDMUX_AUD3_RXC IOMUX_PAD(0x414, 0x0E8, 4, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT10__SDMA_DEBUG_PC_4 IOMUX_PAD(0x414, 0x0E8, 5, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT10__EMI_EMI_DEBUG_39 IOMUX_PAD(0x414, 0x0E8, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT10__TPIU_TRACE_7 IOMUX_PAD(0x414, 0x0E8, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT11__IPU_CSI0_D_11 IOMUX_PAD(0x418, 0x0EC, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT11__GPIO5_29 IOMUX_PAD(0x418, 0x0EC, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT11__UART1_RXD_MUX IOMUX_PAD(0x418, 0x0EC, 2, 0x878, 1, MX53_UART_PAD_CTRL) +#define MX53_PAD_CSI0_DAT11__ECSPI2_SS0 IOMUX_PAD(0x418, 0x0EC, 3, 0x7C4, 1, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT11__AUDMUX_AUD3_RXFS IOMUX_PAD(0x418, 0x0EC, 4, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT11__SDMA_DEBUG_PC_5 IOMUX_PAD(0x418, 0x0EC, 5, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT11__EMI_EMI_DEBUG_40 IOMUX_PAD(0x418, 0x0EC, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT11__TPIU_TRACE_8 IOMUX_PAD(0x418, 0x0EC, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12 IOMUX_PAD(0x41C, 0x0F0, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT12__GPIO5_30 IOMUX_PAD(0x41C, 0x0F0, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT12__UART4_TXD_MUX IOMUX_PAD(0x41C, 0x0F0, 2, __NA_, 0, MX53_UART_PAD_CTRL) +#define MX53_PAD_CSI0_DAT12__USBOH3_USBH3_DATA_0 IOMUX_PAD(0x41C, 0x0F0, 4, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT12__SDMA_DEBUG_PC_6 IOMUX_PAD(0x41C, 0x0F0, 5, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT12__EMI_EMI_DEBUG_41 IOMUX_PAD(0x41C, 0x0F0, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT12__TPIU_TRACE_9 IOMUX_PAD(0x41C, 0x0F0, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13 IOMUX_PAD(0x420, 0x0F4, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT13__GPIO5_31 IOMUX_PAD(0x420, 0x0F4, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT13__UART4_RXD_MUX IOMUX_PAD(0x420, 0x0F4, 2, 0x890, 3, MX53_UART_PAD_CTRL) +#define MX53_PAD_CSI0_DAT13__USBOH3_USBH3_DATA_1 IOMUX_PAD(0x420, 0x0F4, 4, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT13__SDMA_DEBUG_PC_7 IOMUX_PAD(0x420, 0x0F4, 5, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT13__EMI_EMI_DEBUG_42 IOMUX_PAD(0x420, 0x0F4, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT13__TPIU_TRACE_10 IOMUX_PAD(0x420, 0x0F4, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14 IOMUX_PAD(0x424, 0x0F8, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT14__GPIO6_0 IOMUX_PAD(0x424, 0x0F8, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT14__UART5_TXD_MUX IOMUX_PAD(0x424, 0x0F8, 2, __NA_, 0, MX53_UART_PAD_CTRL) +#define MX53_PAD_CSI0_DAT14__USBOH3_USBH3_DATA_2 IOMUX_PAD(0x424, 0x0F8, 4, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT14__SDMA_DEBUG_PC_8 IOMUX_PAD(0x424, 0x0F8, 5, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT14__EMI_EMI_DEBUG_43 IOMUX_PAD(0x424, 0x0F8, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT14__TPIU_TRACE_11 IOMUX_PAD(0x424, 0x0F8, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15 IOMUX_PAD(0x428, 0x0FC, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT15__GPIO6_1 IOMUX_PAD(0x428, 0x0FC, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT15__UART5_RXD_MUX IOMUX_PAD(0x428, 0x0FC, 2, 0x898, 3, MX53_UART_PAD_CTRL) +#define MX53_PAD_CSI0_DAT15__USBOH3_USBH3_DATA_3 IOMUX_PAD(0x428, 0x0FC, 4, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT15__SDMA_DEBUG_PC_9 IOMUX_PAD(0x428, 0x0FC, 5, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT15__EMI_EMI_DEBUG_44 IOMUX_PAD(0x428, 0x0FC, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT15__TPIU_TRACE_12 IOMUX_PAD(0x428, 0x0FC, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16 IOMUX_PAD(0x42C, 0x100, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT16__GPIO6_2 IOMUX_PAD(0x42C, 0x100, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT16__UART4_RTS IOMUX_PAD(0x42C, 0x100, 2, 0x88C, 0, MX53_UART_PAD_CTRL) +#define MX53_PAD_CSI0_DAT16__USBOH3_USBH3_DATA_4 IOMUX_PAD(0x42C, 0x100, 4, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT16__SDMA_DEBUG_PC_10 IOMUX_PAD(0x42C, 0x100, 5, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT16__EMI_EMI_DEBUG_45 IOMUX_PAD(0x42C, 0x100, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT16__TPIU_TRACE_13 IOMUX_PAD(0x42C, 0x100, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17 IOMUX_PAD(0x430, 0x104, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT17__GPIO6_3 IOMUX_PAD(0x430, 0x104, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT17__UART4_CTS IOMUX_PAD(0x430, 0x104, 2, __NA_, 0, MX53_UART_PAD_CTRL) +#define MX53_PAD_CSI0_DAT17__USBOH3_USBH3_DATA_5 IOMUX_PAD(0x430, 0x104, 4, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT17__SDMA_DEBUG_PC_11 IOMUX_PAD(0x430, 0x104, 5, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT17__EMI_EMI_DEBUG_46 IOMUX_PAD(0x430, 0x104, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT17__TPIU_TRACE_14 IOMUX_PAD(0x430, 0x104, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18 IOMUX_PAD(0x434, 0x108, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT18__GPIO6_4 IOMUX_PAD(0x434, 0x108, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT18__UART5_RTS IOMUX_PAD(0x434, 0x108, 2, 0x894, 2, MX53_UART_PAD_CTRL) +#define MX53_PAD_CSI0_DAT18__USBOH3_USBH3_DATA_6 IOMUX_PAD(0x434, 0x108, 4, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT18__SDMA_DEBUG_PC_12 IOMUX_PAD(0x434, 0x108, 5, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT18__EMI_EMI_DEBUG_47 IOMUX_PAD(0x434, 0x108, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT18__TPIU_TRACE_15 IOMUX_PAD(0x434, 0x108, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19 IOMUX_PAD(0x438, 0x10C, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT19__GPIO6_5 IOMUX_PAD(0x438, 0x10C, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT19__UART5_CTS IOMUX_PAD(0x438, 0x10C, 2, __NA_, 0, MX53_UART_PAD_CTRL) +#define MX53_PAD_CSI0_DAT19__USBOH3_USBH3_DATA_7 IOMUX_PAD(0x438, 0x10C, 4, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT19__SDMA_DEBUG_PC_13 IOMUX_PAD(0x438, 0x10C, 5, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT19__EMI_EMI_DEBUG_48 IOMUX_PAD(0x438, 0x10C, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT19__USBPHY2_BISTOK IOMUX_PAD(0x438, 0x10C, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_A25__EMI_WEIM_A_25 IOMUX_PAD(0x458, 0x110, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_A25__GPIO5_2 IOMUX_PAD(0x458, 0x110, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_A25__ECSPI2_RDY IOMUX_PAD(0x458, 0x110, 2, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_A25__IPU_DI1_PIN12 IOMUX_PAD(0x458, 0x110, 3, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_A25__CSPI_SS1 IOMUX_PAD(0x458, 0x110, 4, 0x790, 1, NO_PAD_CTRL) +#define MX53_PAD_EIM_A25__IPU_DI0_D1_CS IOMUX_PAD(0x458, 0x110, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_A25__USBPHY1_BISTOK IOMUX_PAD(0x458, 0x110, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_EB2__EMI_WEIM_EB_2 IOMUX_PAD(0x45C, 0x114, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_EB2__GPIO2_30 IOMUX_PAD(0x45C, 0x114, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_EB2__CCM_DI1_EXT_CLK IOMUX_PAD(0x45C, 0x114, 2, 0x76C, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_EB2__IPU_SER_DISP1_CS IOMUX_PAD(0x45C, 0x114, 3, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_EB2__ECSPI1_SS0 IOMUX_PAD(0x45C, 0x114, 4, 0x7A8, 3, NO_PAD_CTRL) - #define MX53_PAD_EIM_EB2__I2C2_SCL IOMUX_PAD(0x45C, 0x114, 5 | IOMUX_CONFIG_SION, 0x81C, 1, NO_PAD_CTRL) ++#define MX53_PAD_EIM_EB2__I2C2_SCL IOMUX_PAD(0x45C, 0x114, 5 | MUX_CONFIG_SION, 0x81C, 1, NO_PAD_CTRL) +#define MX53_PAD_EIM_D16__EMI_WEIM_D_16 IOMUX_PAD(0x460, 0x118, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D16__GPIO3_16 IOMUX_PAD(0x460, 0x118, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D16__IPU_DI0_PIN5 IOMUX_PAD(0x460, 0x118, 2, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D16__IPU_DISPB1_SER_CLK IOMUX_PAD(0x460, 0x118, 3, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D16__ECSPI1_SCLK IOMUX_PAD(0x460, 0x118, 4, 0x79C, 3, NO_PAD_CTRL) - #define MX53_PAD_EIM_D16__I2C2_SDA IOMUX_PAD(0x460, 0x118, 5 | IOMUX_CONFIG_SION, 0x820, 1, NO_PAD_CTRL) ++#define MX53_PAD_EIM_D16__I2C2_SDA IOMUX_PAD(0x460, 0x118, 5 | MUX_CONFIG_SION, 0x820, 1, NO_PAD_CTRL) +#define MX53_PAD_EIM_D17__EMI_WEIM_D_17 IOMUX_PAD(0x464, 0x11C, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D17__GPIO3_17 IOMUX_PAD(0x464, 0x11C, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D17__IPU_DI0_PIN6 IOMUX_PAD(0x464, 0x11C, 2, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D17__IPU_DISPB1_SER_DIN IOMUX_PAD(0x464, 0x11C, 3, 0x830, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D17__ECSPI1_MISO IOMUX_PAD(0x464, 0x11C, 4, 0x7A0, 3, NO_PAD_CTRL) - #define MX53_PAD_EIM_D17__I2C3_SCL IOMUX_PAD(0x464, 0x11C, 5 | IOMUX_CONFIG_SION, 0x824, 0, NO_PAD_CTRL) ++#define MX53_PAD_EIM_D17__I2C3_SCL IOMUX_PAD(0x464, 0x11C, 5 | MUX_CONFIG_SION, 0x824, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D18__EMI_WEIM_D_18 IOMUX_PAD(0x468, 0x120, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D18__GPIO3_18 IOMUX_PAD(0x468, 0x120, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D18__IPU_DI0_PIN7 IOMUX_PAD(0x468, 0x120, 2, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D18__IPU_DISPB1_SER_DIO IOMUX_PAD(0x468, 0x120, 3, 0x830, 1, NO_PAD_CTRL) +#define MX53_PAD_EIM_D18__ECSPI1_MOSI IOMUX_PAD(0x468, 0x120, 4, 0x7A4, 3, NO_PAD_CTRL) - #define MX53_PAD_EIM_D18__I2C3_SDA IOMUX_PAD(0x468, 0x120, 5 | IOMUX_CONFIG_SION, 0x828, 0, NO_PAD_CTRL) ++#define MX53_PAD_EIM_D18__I2C3_SDA IOMUX_PAD(0x468, 0x120, 5 | MUX_CONFIG_SION, 0x828, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D18__IPU_DI1_D0_CS IOMUX_PAD(0x468, 0x120, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D19__EMI_WEIM_D_19 IOMUX_PAD(0x46C, 0x124, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D19__GPIO3_19 IOMUX_PAD(0x46C, 0x124, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D19__IPU_DI0_PIN8 IOMUX_PAD(0x46C, 0x124, 2, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D19__IPU_DISPB1_SER_RS IOMUX_PAD(0x46C, 0x124, 3, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D19__ECSPI1_SS1 IOMUX_PAD(0x46C, 0x124, 4, 0x7AC, 2, NO_PAD_CTRL) +#define MX53_PAD_EIM_D19__EPIT1_EPITO IOMUX_PAD(0x46C, 0x124, 5, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D19__UART1_CTS IOMUX_PAD(0x46C, 0x124, 6, __NA_, 0, MX53_UART_PAD_CTRL) +#define MX53_PAD_EIM_D19__USBOH3_USBH2_OC IOMUX_PAD(0x46C, 0x124, 7, 0x8A4, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D20__EMI_WEIM_D_20 IOMUX_PAD(0x470, 0x128, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D20__GPIO3_20 IOMUX_PAD(0x470, 0x128, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D20__IPU_DI0_PIN16 IOMUX_PAD(0x470, 0x128, 2, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D20__IPU_SER_DISP0_CS IOMUX_PAD(0x470, 0x128, 3, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D20__CSPI_SS0 IOMUX_PAD(0x470, 0x128, 4, 0x78C, 1, NO_PAD_CTRL) +#define MX53_PAD_EIM_D20__EPIT2_EPITO IOMUX_PAD(0x470, 0x128, 5, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D20__UART1_RTS IOMUX_PAD(0x470, 0x128, 6, 0x874, 1, MX53_UART_PAD_CTRL) +#define MX53_PAD_EIM_D20__USBOH3_USBH2_PWR IOMUX_PAD(0x470, 0x128, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D21__EMI_WEIM_D_21 IOMUX_PAD(0x474, 0x12C, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D21__GPIO3_21 IOMUX_PAD(0x474, 0x12C, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D21__IPU_DI0_PIN17 IOMUX_PAD(0x474, 0x12C, 2, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D21__IPU_DISPB0_SER_CLK IOMUX_PAD(0x474, 0x12C, 3, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D21__CSPI_SCLK IOMUX_PAD(0x474, 0x12C, 4, 0x780, 1, NO_PAD_CTRL) - #define MX53_PAD_EIM_D21__I2C1_SCL IOMUX_PAD(0x474, 0x12C, 5 | IOMUX_CONFIG_SION, 0x814, 1, NO_PAD_CTRL) ++#define MX53_PAD_EIM_D21__I2C1_SCL IOMUX_PAD(0x474, 0x12C, 5 | MUX_CONFIG_SION, 0x814, 1, NO_PAD_CTRL) +#define MX53_PAD_EIM_D21__USBOH3_USBOTG_OC IOMUX_PAD(0x474, 0x12C, 6, 0x89C, 1, NO_PAD_CTRL) +#define MX53_PAD_EIM_D22__EMI_WEIM_D_22 IOMUX_PAD(0x478, 0x130, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D22__GPIO3_22 IOMUX_PAD(0x478, 0x130, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D22__IPU_DI0_PIN1 IOMUX_PAD(0x478, 0x130, 2, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D22__IPU_DISPB0_SER_DIN IOMUX_PAD(0x478, 0x130, 3, 0x82C, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D22__CSPI_MISO IOMUX_PAD(0x478, 0x130, 4, 0x784, 1, NO_PAD_CTRL) +#define MX53_PAD_EIM_D22__USBOH3_USBOTG_PWR IOMUX_PAD(0x478, 0x130, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D23__EMI_WEIM_D_23 IOMUX_PAD(0x47C, 0x134, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D23__GPIO3_23 IOMUX_PAD(0x47C, 0x134, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D23__UART3_CTS IOMUX_PAD(0x47C, 0x134, 2, __NA_, 0, MX53_UART_PAD_CTRL) +#define MX53_PAD_EIM_D23__UART1_DCD IOMUX_PAD(0x47C, 0x134, 3, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D23__IPU_DI0_D0_CS IOMUX_PAD(0x47C, 0x134, 4, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D23__IPU_DI1_PIN2 IOMUX_PAD(0x47C, 0x134, 5, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D23__IPU_CSI1_DATA_EN IOMUX_PAD(0x47C, 0x134, 6, 0x834, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D23__IPU_DI1_PIN14 IOMUX_PAD(0x47C, 0x134, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_EB3__EMI_WEIM_EB_3 IOMUX_PAD(0x480, 0x138, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_EB3__GPIO2_31 IOMUX_PAD(0x480, 0x138, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_EB3__UART3_RTS IOMUX_PAD(0x480, 0x138, 2, 0x884, 1, MX53_UART_PAD_CTRL) +#define MX53_PAD_EIM_EB3__UART1_RI IOMUX_PAD(0x480, 0x138, 3, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_EB3__IPU_DI1_PIN3 IOMUX_PAD(0x480, 0x138, 5, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_EB3__IPU_CSI1_HSYNC IOMUX_PAD(0x480, 0x138, 6, 0x838, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_EB3__IPU_DI1_PIN16 IOMUX_PAD(0x480, 0x138, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D24__EMI_WEIM_D_24 IOMUX_PAD(0x484, 0x13C, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D24__GPIO3_24 IOMUX_PAD(0x484, 0x13C, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D24__UART3_TXD_MUX IOMUX_PAD(0x484, 0x13C, 2, __NA_, 0, MX53_UART_PAD_CTRL) +#define MX53_PAD_EIM_D24__ECSPI1_SS2 IOMUX_PAD(0x484, 0x13C, 3, 0x7B0, 1, NO_PAD_CTRL) +#define MX53_PAD_EIM_D24__CSPI_SS2 IOMUX_PAD(0x484, 0x13C, 4, 0x794, 1, NO_PAD_CTRL) +#define MX53_PAD_EIM_D24__AUDMUX_AUD5_RXFS IOMUX_PAD(0x484, 0x13C, 5, 0x754, 1, NO_PAD_CTRL) +#define MX53_PAD_EIM_D24__ECSPI2_SS2 IOMUX_PAD(0x484, 0x13C, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D24__UART1_DTR IOMUX_PAD(0x484, 0x13C, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D25__EMI_WEIM_D_25 IOMUX_PAD(0x488, 0x140, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D25__GPIO3_25 IOMUX_PAD(0x488, 0x140, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D25__UART3_RXD_MUX IOMUX_PAD(0x488, 0x140, 2, 0x888, 1, MX53_UART_PAD_CTRL) +#define MX53_PAD_EIM_D25__ECSPI1_SS3 IOMUX_PAD(0x488, 0x140, 3, 0x7B4, 1, NO_PAD_CTRL) +#define MX53_PAD_EIM_D25__CSPI_SS3 IOMUX_PAD(0x488, 0x140, 4, 0x798, 1, NO_PAD_CTRL) +#define MX53_PAD_EIM_D25__AUDMUX_AUD5_RXC IOMUX_PAD(0x488, 0x140, 5, 0x750, 1, NO_PAD_CTRL) +#define MX53_PAD_EIM_D25__ECSPI2_SS3 IOMUX_PAD(0x488, 0x140, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D25__UART1_DSR IOMUX_PAD(0x488, 0x140, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D26__EMI_WEIM_D_26 IOMUX_PAD(0x48C, 0x144, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D26__GPIO3_26 IOMUX_PAD(0x48C, 0x144, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D26__UART2_TXD_MUX IOMUX_PAD(0x48C, 0x144, 2, __NA_, 0, MX53_UART_PAD_CTRL) +#define MX53_PAD_EIM_D26__FIRI_RXD IOMUX_PAD(0x48C, 0x144, 3, 0x80C, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D26__IPU_CSI0_D_1 IOMUX_PAD(0x48C, 0x144, 4, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D26__IPU_DI1_PIN11 IOMUX_PAD(0x48C, 0x144, 5, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D26__IPU_SISG_2 IOMUX_PAD(0x48C, 0x144, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D26__IPU_DISP1_DAT_22 IOMUX_PAD(0x48C, 0x144, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D27__EMI_WEIM_D_27 IOMUX_PAD(0x490, 0x148, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D27__GPIO3_27 IOMUX_PAD(0x490, 0x148, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D27__UART2_RXD_MUX IOMUX_PAD(0x490, 0x148, 2, 0x880, 1, MX53_UART_PAD_CTRL) +#define MX53_PAD_EIM_D27__FIRI_TXD IOMUX_PAD(0x490, 0x148, 3, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D27__IPU_CSI0_D_0 IOMUX_PAD(0x490, 0x148, 4, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D27__IPU_DI1_PIN13 IOMUX_PAD(0x490, 0x148, 5, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D27__IPU_SISG_3 IOMUX_PAD(0x490, 0x148, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D27__IPU_DISP1_DAT_23 IOMUX_PAD(0x490, 0x148, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D28__EMI_WEIM_D_28 IOMUX_PAD(0x494, 0x14C, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D28__GPIO3_28 IOMUX_PAD(0x494, 0x14C, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D28__UART2_CTS IOMUX_PAD(0x494, 0x14C, 2, __NA_, 0, MX53_UART_PAD_CTRL) +#define MX53_PAD_EIM_D28__IPU_DISPB0_SER_DIO IOMUX_PAD(0x494, 0x14C, 3, 0x82C, 1, NO_PAD_CTRL) +#define MX53_PAD_EIM_D28__CSPI_MOSI IOMUX_PAD(0x494, 0x14C, 4, 0x788, 1, NO_PAD_CTRL) - #define MX53_PAD_EIM_D28__I2C1_SDA IOMUX_PAD(0x494, 0x14C, 5 | IOMUX_CONFIG_SION, 0x818, 1, NO_PAD_CTRL) ++#define MX53_PAD_EIM_D28__I2C1_SDA IOMUX_PAD(0x494, 0x14C, 5 | MUX_CONFIG_SION, 0x818, 1, NO_PAD_CTRL) +#define MX53_PAD_EIM_D28__IPU_EXT_TRIG IOMUX_PAD(0x494, 0x14C, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D28__IPU_DI0_PIN13 IOMUX_PAD(0x494, 0x14C, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D29__EMI_WEIM_D_29 IOMUX_PAD(0x498, 0x150, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D29__GPIO3_29 IOMUX_PAD(0x498, 0x150, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D29__UART2_RTS IOMUX_PAD(0x498, 0x150, 2, 0x87C, 1, MX53_UART_PAD_CTRL) +#define MX53_PAD_EIM_D29__IPU_DISPB0_SER_RS IOMUX_PAD(0x498, 0x150, 3, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D29__CSPI_SS0 IOMUX_PAD(0x498, 0x150, 4, 0x78C, 2, NO_PAD_CTRL) +#define MX53_PAD_EIM_D29__IPU_DI1_PIN15 IOMUX_PAD(0x498, 0x150, 5, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D29__IPU_CSI1_VSYNC IOMUX_PAD(0x498, 0x150, 6, 0x83C, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D29__IPU_DI0_PIN14 IOMUX_PAD(0x498, 0x150, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D30__EMI_WEIM_D_30 IOMUX_PAD(0x49C, 0x154, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D30__GPIO3_30 IOMUX_PAD(0x49C, 0x154, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D30__UART3_CTS IOMUX_PAD(0x49C, 0x154, 2, __NA_, 0, MX53_UART_PAD_CTRL) +#define MX53_PAD_EIM_D30__IPU_CSI0_D_3 IOMUX_PAD(0x49C, 0x154, 3, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D30__IPU_DI0_PIN11 IOMUX_PAD(0x49C, 0x154, 4, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D30__IPU_DISP1_DAT_21 IOMUX_PAD(0x49C, 0x154, 5, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D30__USBOH3_USBH1_OC IOMUX_PAD(0x49C, 0x154, 6, 0x8A0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D30__USBOH3_USBH2_OC IOMUX_PAD(0x49C, 0x154, 7, 0x8A4, 1, NO_PAD_CTRL) +#define MX53_PAD_EIM_D31__EMI_WEIM_D_31 IOMUX_PAD(0x4A0, 0x158, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D31__GPIO3_31 IOMUX_PAD(0x4A0, 0x158, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D31__UART3_RTS IOMUX_PAD(0x4A0, 0x158, 2, 0x884, 3, MX53_UART_PAD_CTRL) +#define MX53_PAD_EIM_D31__IPU_CSI0_D_2 IOMUX_PAD(0x4A0, 0x158, 3, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D31__IPU_DI0_PIN12 IOMUX_PAD(0x4A0, 0x158, 4, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D31__IPU_DISP1_DAT_20 IOMUX_PAD(0x4A0, 0x158, 5, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D31__USBOH3_USBH1_PWR IOMUX_PAD(0x4A0, 0x158, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D31__USBOH3_USBH2_PWR IOMUX_PAD(0x4A0, 0x158, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_A24__EMI_WEIM_A_24 IOMUX_PAD(0x4A8, 0x15C, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_A24__GPIO5_4 IOMUX_PAD(0x4A8, 0x15C, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_A24__IPU_DISP1_DAT_19 IOMUX_PAD(0x4A8, 0x15C, 2, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_A24__IPU_CSI1_D_19 IOMUX_PAD(0x4A8, 0x15C, 3, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_A24__IPU_SISG_2 IOMUX_PAD(0x4A8, 0x15C, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_A24__USBPHY2_BVALID IOMUX_PAD(0x4A8, 0x15C, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_A23__EMI_WEIM_A_23 IOMUX_PAD(0x4AC, 0x160, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_A23__GPIO6_6 IOMUX_PAD(0x4AC, 0x160, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_A23__IPU_DISP1_DAT_18 IOMUX_PAD(0x4AC, 0x160, 2, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_A23__IPU_CSI1_D_18 IOMUX_PAD(0x4AC, 0x160, 3, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_A23__IPU_SISG_3 IOMUX_PAD(0x4AC, 0x160, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_A23__USBPHY2_ENDSESSION IOMUX_PAD(0x4AC, 0x160, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_A22__EMI_WEIM_A_22 IOMUX_PAD(0x4B0, 0x164, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_A22__GPIO2_16 IOMUX_PAD(0x4B0, 0x164, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_A22__IPU_DISP1_DAT_17 IOMUX_PAD(0x4B0, 0x164, 2, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_A22__IPU_CSI1_D_17 IOMUX_PAD(0x4B0, 0x164, 3, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_A22__SRC_BT_CFG1_7 IOMUX_PAD(0x4B0, 0x164, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_A21__EMI_WEIM_A_21 IOMUX_PAD(0x4B4, 0x168, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_A21__GPIO2_17 IOMUX_PAD(0x4B4, 0x168, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_A21__IPU_DISP1_DAT_16 IOMUX_PAD(0x4B4, 0x168, 2, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_A21__IPU_CSI1_D_16 IOMUX_PAD(0x4B4, 0x168, 3, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_A21__SRC_BT_CFG1_6 IOMUX_PAD(0x4B4, 0x168, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_A20__EMI_WEIM_A_20 IOMUX_PAD(0x4B8, 0x16C, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_A20__GPIO2_18 IOMUX_PAD(0x4B8, 0x16C, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_A20__IPU_DISP1_DAT_15 IOMUX_PAD(0x4B8, 0x16C, 2, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_A20__IPU_CSI1_D_15 IOMUX_PAD(0x4B8, 0x16C, 3, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_A20__SRC_BT_CFG1_5 IOMUX_PAD(0x4B8, 0x16C, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_A19__EMI_WEIM_A_19 IOMUX_PAD(0x4BC, 0x170, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_A19__GPIO2_19 IOMUX_PAD(0x4BC, 0x170, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_A19__IPU_DISP1_DAT_14 IOMUX_PAD(0x4BC, 0x170, 2, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_A19__IPU_CSI1_D_14 IOMUX_PAD(0x4BC, 0x170, 3, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_A19__SRC_BT_CFG1_4 IOMUX_PAD(0x4BC, 0x170, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_A18__EMI_WEIM_A_18 IOMUX_PAD(0x4C0, 0x174, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_A18__GPIO2_20 IOMUX_PAD(0x4C0, 0x174, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_A18__IPU_DISP1_DAT_13 IOMUX_PAD(0x4C0, 0x174, 2, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_A18__IPU_CSI1_D_13 IOMUX_PAD(0x4C0, 0x174, 3, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_A18__SRC_BT_CFG1_3 IOMUX_PAD(0x4C0, 0x174, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_A17__EMI_WEIM_A_17 IOMUX_PAD(0x4C4, 0x178, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_A17__GPIO2_21 IOMUX_PAD(0x4C4, 0x178, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_A17__IPU_DISP1_DAT_12 IOMUX_PAD(0x4C4, 0x178, 2, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_A17__IPU_CSI1_D_12 IOMUX_PAD(0x4C4, 0x178, 3, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_A17__SRC_BT_CFG1_2 IOMUX_PAD(0x4C4, 0x178, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_A16__EMI_WEIM_A_16 IOMUX_PAD(0x4C8, 0x17C, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_A16__GPIO2_22 IOMUX_PAD(0x4C8, 0x17C, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK IOMUX_PAD(0x4C8, 0x17C, 2, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_A16__IPU_CSI1_PIXCLK IOMUX_PAD(0x4C8, 0x17C, 3, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_A16__SRC_BT_CFG1_1 IOMUX_PAD(0x4C8, 0x17C, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_CS0__EMI_WEIM_CS_0 IOMUX_PAD(0x4CC, 0x180, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_CS0__GPIO2_23 IOMUX_PAD(0x4CC, 0x180, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_CS0__ECSPI2_SCLK IOMUX_PAD(0x4CC, 0x180, 2, 0x7B8, 2, NO_PAD_CTRL) +#define MX53_PAD_EIM_CS0__IPU_DI1_PIN5 IOMUX_PAD(0x4CC, 0x180, 3, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_CS1__EMI_WEIM_CS_1 IOMUX_PAD(0x4D0, 0x184, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_CS1__GPIO2_24 IOMUX_PAD(0x4D0, 0x184, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_CS1__ECSPI2_MOSI IOMUX_PAD(0x4D0, 0x184, 2, 0x7C0, 2, NO_PAD_CTRL) +#define MX53_PAD_EIM_CS1__IPU_DI1_PIN6 IOMUX_PAD(0x4D0, 0x184, 3, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_OE__EMI_WEIM_OE IOMUX_PAD(0x4D4, 0x188, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_OE__GPIO2_25 IOMUX_PAD(0x4D4, 0x188, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_OE__ECSPI2_MISO IOMUX_PAD(0x4D4, 0x188, 2, 0x7BC, 2, NO_PAD_CTRL) +#define MX53_PAD_EIM_OE__IPU_DI1_PIN7 IOMUX_PAD(0x4D4, 0x188, 3, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_OE__USBPHY2_IDDIG IOMUX_PAD(0x4D4, 0x188, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_RW__EMI_WEIM_RW IOMUX_PAD(0x4D8, 0x18C, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_RW__GPIO2_26 IOMUX_PAD(0x4D8, 0x18C, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_RW__ECSPI2_SS0 IOMUX_PAD(0x4D8, 0x18C, 2, 0x7C4, 2, NO_PAD_CTRL) +#define MX53_PAD_EIM_RW__IPU_DI1_PIN8 IOMUX_PAD(0x4D8, 0x18C, 3, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_RW__USBPHY2_HOSTDISCONNECT IOMUX_PAD(0x4D8, 0x18C, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_LBA__EMI_WEIM_LBA IOMUX_PAD(0x4DC, 0x190, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_LBA__GPIO2_27 IOMUX_PAD(0x4DC, 0x190, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_LBA__ECSPI2_SS1 IOMUX_PAD(0x4DC, 0x190, 2, 0x7C8, 1, NO_PAD_CTRL) +#define MX53_PAD_EIM_LBA__IPU_DI1_PIN17 IOMUX_PAD(0x4DC, 0x190, 3, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_LBA__SRC_BT_CFG1_0 IOMUX_PAD(0x4DC, 0x190, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_EB0__EMI_WEIM_EB_0 IOMUX_PAD(0x4E4, 0x194, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_EB0__GPIO2_28 IOMUX_PAD(0x4E4, 0x194, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11 IOMUX_PAD(0x4E4, 0x194, 3, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_EB0__IPU_CSI1_D_11 IOMUX_PAD(0x4E4, 0x194, 4, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_EB0__GPC_PMIC_RDY IOMUX_PAD(0x4E4, 0x194, 5, 0x810, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_EB0__SRC_BT_CFG2_7 IOMUX_PAD(0x4E4, 0x194, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_EB1__EMI_WEIM_EB_1 IOMUX_PAD(0x4E8, 0x198, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_EB1__GPIO2_29 IOMUX_PAD(0x4E8, 0x198, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10 IOMUX_PAD(0x4E8, 0x198, 3, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_EB1__IPU_CSI1_D_10 IOMUX_PAD(0x4E8, 0x198, 4, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_EB1__SRC_BT_CFG2_6 IOMUX_PAD(0x4E8, 0x198, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0 IOMUX_PAD(0x4EC, 0x19C, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA0__GPIO3_0 IOMUX_PAD(0x4EC, 0x19C, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9 IOMUX_PAD(0x4EC, 0x19C, 3, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA0__IPU_CSI1_D_9 IOMUX_PAD(0x4EC, 0x19C, 4, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA0__SRC_BT_CFG2_5 IOMUX_PAD(0x4EC, 0x19C, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1 IOMUX_PAD(0x4F0, 0x1A0, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA1__GPIO3_1 IOMUX_PAD(0x4F0, 0x1A0, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8 IOMUX_PAD(0x4F0, 0x1A0, 3, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA1__IPU_CSI1_D_8 IOMUX_PAD(0x4F0, 0x1A0, 4, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA1__SRC_BT_CFG2_4 IOMUX_PAD(0x4F0, 0x1A0, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2 IOMUX_PAD(0x4F4, 0x1A4, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA2__GPIO3_2 IOMUX_PAD(0x4F4, 0x1A4, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7 IOMUX_PAD(0x4F4, 0x1A4, 3, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA2__IPU_CSI1_D_7 IOMUX_PAD(0x4F4, 0x1A4, 4, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA2__SRC_BT_CFG2_3 IOMUX_PAD(0x4F4, 0x1A4, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3 IOMUX_PAD(0x4F8, 0x1A8, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA3__GPIO3_3 IOMUX_PAD(0x4F8, 0x1A8, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6 IOMUX_PAD(0x4F8, 0x1A8, 3, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA3__IPU_CSI1_D_6 IOMUX_PAD(0x4F8, 0x1A8, 4, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA3__SRC_BT_CFG2_2 IOMUX_PAD(0x4F8, 0x1A8, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4 IOMUX_PAD(0x4FC, 0x1AC, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA4__GPIO3_4 IOMUX_PAD(0x4FC, 0x1AC, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5 IOMUX_PAD(0x4FC, 0x1AC, 3, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA4__IPU_CSI1_D_5 IOMUX_PAD(0x4FC, 0x1AC, 4, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA4__SRC_BT_CFG3_7 IOMUX_PAD(0x4FC, 0x1AC, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5 IOMUX_PAD(0x500, 0x1B0, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA5__GPIO3_5 IOMUX_PAD(0x500, 0x1B0, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4 IOMUX_PAD(0x500, 0x1B0, 3, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA5__IPU_CSI1_D_4 IOMUX_PAD(0x500, 0x1B0, 4, __NA_, 0, NO_PAD_CTRL) - #define MX53_PAD_EIM_DA5__SRC_BT_CFG3_6 IOMUX_PAD(0x500, 0x1B0, 7 | IOMUX_CONFIG_SION, __NA_, 0, NO_PAD_CTRL) ++#define MX53_PAD_EIM_DA5__SRC_BT_CFG3_6 IOMUX_PAD(0x500, 0x1B0, 7 | MUX_CONFIG_SION, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6 IOMUX_PAD(0x504, 0x1B4, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA6__GPIO3_6 IOMUX_PAD(0x504, 0x1B4, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3 IOMUX_PAD(0x504, 0x1B4, 3, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA6__IPU_CSI1_D_3 IOMUX_PAD(0x504, 0x1B4, 4, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA6__SRC_BT_CFG3_5 IOMUX_PAD(0x504, 0x1B4, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA7__EMI_NAND_WEIM_DA_7 IOMUX_PAD(0x508, 0x1B8, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA7__GPIO3_7 IOMUX_PAD(0x508, 0x1B8, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2 IOMUX_PAD(0x508, 0x1B8, 3, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA7__IPU_CSI1_D_2 IOMUX_PAD(0x508, 0x1B8, 4, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA7__SRC_BT_CFG3_4 IOMUX_PAD(0x508, 0x1B8, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA8__EMI_NAND_WEIM_DA_8 IOMUX_PAD(0x50C, 0x1BC, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA8__GPIO3_8 IOMUX_PAD(0x50C, 0x1BC, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1 IOMUX_PAD(0x50C, 0x1BC, 3, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA8__IPU_CSI1_D_1 IOMUX_PAD(0x50C, 0x1BC, 4, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA8__SRC_BT_CFG3_3 IOMUX_PAD(0x50C, 0x1BC, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA9__EMI_NAND_WEIM_DA_9 IOMUX_PAD(0x510, 0x1C0, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA9__GPIO3_9 IOMUX_PAD(0x510, 0x1C0, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0 IOMUX_PAD(0x510, 0x1C0, 3, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA9__IPU_CSI1_D_0 IOMUX_PAD(0x510, 0x1C0, 4, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA9__SRC_BT_CFG3_2 IOMUX_PAD(0x510, 0x1C0, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA10__EMI_NAND_WEIM_DA_10 IOMUX_PAD(0x514, 0x1C4, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA10__GPIO3_10 IOMUX_PAD(0x514, 0x1C4, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA10__IPU_DI1_PIN15 IOMUX_PAD(0x514, 0x1C4, 3, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA10__IPU_CSI1_DATA_EN IOMUX_PAD(0x514, 0x1C4, 4, 0x834, 1, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA10__SRC_BT_CFG3_1 IOMUX_PAD(0x514, 0x1C4, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA11__EMI_NAND_WEIM_DA_11 IOMUX_PAD(0x518, 0x1C8, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA11__GPIO3_11 IOMUX_PAD(0x518, 0x1C8, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA11__IPU_DI1_PIN2 IOMUX_PAD(0x518, 0x1C8, 3, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA11__IPU_CSI1_HSYNC IOMUX_PAD(0x518, 0x1C8, 4, 0x838, 1, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA12__EMI_NAND_WEIM_DA_12 IOMUX_PAD(0x51C, 0x1CC, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA12__GPIO3_12 IOMUX_PAD(0x51C, 0x1CC, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA12__IPU_DI1_PIN3 IOMUX_PAD(0x51C, 0x1CC, 3, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA12__IPU_CSI1_VSYNC IOMUX_PAD(0x51C, 0x1CC, 4, 0x83C, 1, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA13__EMI_NAND_WEIM_DA_13 IOMUX_PAD(0x520, 0x1D0, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA13__GPIO3_13 IOMUX_PAD(0x520, 0x1D0, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA13__IPU_DI1_D0_CS IOMUX_PAD(0x520, 0x1D0, 3, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA13__CCM_DI1_EXT_CLK IOMUX_PAD(0x520, 0x1D0, 4, 0x76C, 1, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA14__EMI_NAND_WEIM_DA_14 IOMUX_PAD(0x524, 0x1D4, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA14__GPIO3_14 IOMUX_PAD(0x524, 0x1D4, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA14__IPU_DI1_D1_CS IOMUX_PAD(0x524, 0x1D4, 3, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA14__CCM_DI0_EXT_CLK IOMUX_PAD(0x524, 0x1D4, 4, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA15__EMI_NAND_WEIM_DA_15 IOMUX_PAD(0x528, 0x1D8, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA15__GPIO3_15 IOMUX_PAD(0x528, 0x1D8, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA15__IPU_DI1_PIN1 IOMUX_PAD(0x528, 0x1D8, 3, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA15__IPU_DI1_PIN4 IOMUX_PAD(0x528, 0x1D8, 4, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B IOMUX_PAD(0x52C, 0x1DC, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_NANDF_WE_B__GPIO6_12 IOMUX_PAD(0x52C, 0x1DC, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B IOMUX_PAD(0x530, 0x1E0, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_NANDF_RE_B__GPIO6_13 IOMUX_PAD(0x530, 0x1E0, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_WAIT__EMI_WEIM_WAIT IOMUX_PAD(0x534, 0x1E4, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_WAIT__GPIO5_0 IOMUX_PAD(0x534, 0x1E4, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_WAIT__EMI_WEIM_DTACK_B IOMUX_PAD(0x534, 0x1E4, 2, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_LVDS1_TX3_P__GPIO6_22 IOMUX_PAD(__NA_, 0x1EC, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 IOMUX_PAD(__NA_, 0x1EC, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_LVDS1_TX2_P__GPIO6_24 IOMUX_PAD(__NA_, 0x1F0, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 IOMUX_PAD(__NA_, 0x1F0, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_LVDS1_CLK_P__GPIO6_26 IOMUX_PAD(__NA_, 0x1F4, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK IOMUX_PAD(__NA_, 0x1F4, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_LVDS1_TX1_P__GPIO6_28 IOMUX_PAD(__NA_, 0x1F8, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 IOMUX_PAD(__NA_, 0x1F8, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_LVDS1_TX0_P__GPIO6_30 IOMUX_PAD(__NA_, 0x1FC, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 IOMUX_PAD(__NA_, 0x1FC, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_LVDS0_TX3_P__GPIO7_22 IOMUX_PAD(__NA_, 0x200, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 IOMUX_PAD(__NA_, 0x200, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_LVDS0_CLK_P__GPIO7_24 IOMUX_PAD(__NA_, 0x204, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK IOMUX_PAD(__NA_, 0x204, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_LVDS0_TX2_P__GPIO7_26 IOMUX_PAD(__NA_, 0x208, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 IOMUX_PAD(__NA_, 0x208, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_LVDS0_TX1_P__GPIO7_28 IOMUX_PAD(__NA_, 0x20C, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 IOMUX_PAD(__NA_, 0x20C, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_LVDS0_TX0_P__GPIO7_30 IOMUX_PAD(__NA_, 0x210, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 IOMUX_PAD(__NA_, 0x210, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_10__GPIO4_0 IOMUX_PAD(0x540, 0x214, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_10__OSC32k_32K_OUT IOMUX_PAD(0x540, 0x214, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_11__GPIO4_1 IOMUX_PAD(0x544, 0x218, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_12__GPIO4_2 IOMUX_PAD(0x548, 0x21C, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_13__GPIO4_3 IOMUX_PAD(0x54C, 0x220, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_14__GPIO4_4 IOMUX_PAD(0x550, 0x224, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_NANDF_CLE__EMI_NANDF_CLE IOMUX_PAD(0x5A0, 0x228, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_NANDF_CLE__GPIO6_7 IOMUX_PAD(0x5A0, 0x228, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_NANDF_CLE__USBPHY1_VSTATUS_0 IOMUX_PAD(0x5A0, 0x228, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_NANDF_ALE__EMI_NANDF_ALE IOMUX_PAD(0x5A4, 0x22C, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_NANDF_ALE__GPIO6_8 IOMUX_PAD(0x5A4, 0x22C, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_NANDF_ALE__USBPHY1_VSTATUS_1 IOMUX_PAD(0x5A4, 0x22C, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B IOMUX_PAD(0x5A8, 0x230, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_NANDF_WP_B__GPIO6_9 IOMUX_PAD(0x5A8, 0x230, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_NANDF_WP_B__USBPHY1_VSTATUS_2 IOMUX_PAD(0x5A8, 0x230, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0 IOMUX_PAD(0x5AC, 0x234, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_NANDF_RB0__GPIO6_10 IOMUX_PAD(0x5AC, 0x234, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_NANDF_RB0__USBPHY1_VSTATUS_3 IOMUX_PAD(0x5AC, 0x234, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0 IOMUX_PAD(0x5B0, 0x238, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_NANDF_CS0__GPIO6_11 IOMUX_PAD(0x5B0, 0x238, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_NANDF_CS0__USBPHY1_VSTATUS_4 IOMUX_PAD(0x5B0, 0x238, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_NANDF_CS1__EMI_NANDF_CS_1 IOMUX_PAD(0x5B4, 0x23C, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_NANDF_CS1__GPIO6_14 IOMUX_PAD(0x5B4, 0x23C, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_NANDF_CS1__MLB_MLBCLK IOMUX_PAD(0x5B4, 0x23C, 6, 0x858, 0, NO_PAD_CTRL) +#define MX53_PAD_NANDF_CS1__USBPHY1_VSTATUS_5 IOMUX_PAD(0x5B4, 0x23C, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_NANDF_CS2__EMI_NANDF_CS_2 IOMUX_PAD(0x5B8, 0x240, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_NANDF_CS2__GPIO6_15 IOMUX_PAD(0x5B8, 0x240, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_NANDF_CS2__IPU_SISG_0 IOMUX_PAD(0x5B8, 0x240, 2, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_NANDF_CS2__ESAI1_TX0 IOMUX_PAD(0x5B8, 0x240, 3, 0x7E4, 0, NO_PAD_CTRL) +#define MX53_PAD_NANDF_CS2__EMI_WEIM_CRE IOMUX_PAD(0x5B8, 0x240, 4, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_NANDF_CS2__CCM_CSI0_MCLK IOMUX_PAD(0x5B8, 0x240, 5, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_NANDF_CS2__MLB_MLBSIG IOMUX_PAD(0x5B8, 0x240, 6, 0x860, 0, NO_PAD_CTRL) +#define MX53_PAD_NANDF_CS2__USBPHY1_VSTATUS_6 IOMUX_PAD(0x5B8, 0x240, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_NANDF_CS3__EMI_NANDF_CS_3 IOMUX_PAD(0x5BC, 0x244, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_NANDF_CS3__GPIO6_16 IOMUX_PAD(0x5BC, 0x244, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_NANDF_CS3__IPU_SISG_1 IOMUX_PAD(0x5BC, 0x244, 2, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_NANDF_CS3__ESAI1_TX1 IOMUX_PAD(0x5BC, 0x244, 3, 0x7E8, 0, NO_PAD_CTRL) +#define MX53_PAD_NANDF_CS3__EMI_WEIM_A_26 IOMUX_PAD(0x5BC, 0x244, 4, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_NANDF_CS3__MLB_MLBDAT IOMUX_PAD(0x5BC, 0x244, 6, 0x85C, 0, NO_PAD_CTRL) +#define MX53_PAD_NANDF_CS3__USBPHY1_VSTATUS_7 IOMUX_PAD(0x5BC, 0x244, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_FEC_MDIO__FEC_MDIO IOMUX_PAD(0x5C4, 0x248, 0, 0x804, 1, NO_PAD_CTRL) +#define MX53_PAD_FEC_MDIO__GPIO1_22 IOMUX_PAD(0x5C4, 0x248, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_FEC_MDIO__ESAI1_SCKR IOMUX_PAD(0x5C4, 0x248, 2, 0x7DC, 0, NO_PAD_CTRL) +#define MX53_PAD_FEC_MDIO__FEC_COL IOMUX_PAD(0x5C4, 0x248, 3, 0x800, 1, NO_PAD_CTRL) +#define MX53_PAD_FEC_MDIO__RTC_CE_RTC_PS2 IOMUX_PAD(0x5C4, 0x248, 4, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_FEC_MDIO__SDMA_DEBUG_BUS_DEVICE_3 IOMUX_PAD(0x5C4, 0x248, 5, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_FEC_MDIO__EMI_EMI_DEBUG_49 IOMUX_PAD(0x5C4, 0x248, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_FEC_REF_CLK__FEC_TX_CLK IOMUX_PAD(0x5C8, 0x24C, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_FEC_REF_CLK__GPIO1_23 IOMUX_PAD(0x5C8, 0x24C, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_FEC_REF_CLK__ESAI1_FSR IOMUX_PAD(0x5C8, 0x24C, 2, 0x7CC, 0, NO_PAD_CTRL) +#define MX53_PAD_FEC_REF_CLK__SDMA_DEBUG_BUS_DEVICE_4 IOMUX_PAD(0x5C8, 0x24C, 5, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_FEC_REF_CLK__EMI_EMI_DEBUG_50 IOMUX_PAD(0x5C8, 0x24C, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_FEC_RX_ER__FEC_RX_ER IOMUX_PAD(0x5CC, 0x250, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_FEC_RX_ER__GPIO1_24 IOMUX_PAD(0x5CC, 0x250, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_FEC_RX_ER__ESAI1_HCKR IOMUX_PAD(0x5CC, 0x250, 2, 0x7D4, 0, NO_PAD_CTRL) +#define MX53_PAD_FEC_RX_ER__FEC_RX_CLK IOMUX_PAD(0x5CC, 0x250, 3, 0x808, 1, NO_PAD_CTRL) +#define MX53_PAD_FEC_RX_ER__RTC_CE_RTC_PS3 IOMUX_PAD(0x5CC, 0x250, 4, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_FEC_CRS_DV__FEC_RX_DV IOMUX_PAD(0x5D0, 0x254, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_FEC_CRS_DV__GPIO1_25 IOMUX_PAD(0x5D0, 0x254, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_FEC_CRS_DV__ESAI1_SCKT IOMUX_PAD(0x5D0, 0x254, 2, 0x7E0, 0, NO_PAD_CTRL) +#define MX53_PAD_FEC_RXD1__FEC_RDATA_1 IOMUX_PAD(0x5D4, 0x258, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_FEC_RXD1__GPIO1_26 IOMUX_PAD(0x5D4, 0x258, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_FEC_RXD1__ESAI1_FST IOMUX_PAD(0x5D4, 0x258, 2, 0x7D0, 0, NO_PAD_CTRL) +#define MX53_PAD_FEC_RXD1__MLB_MLBSIG IOMUX_PAD(0x5D4, 0x258, 3, 0x860, 1, NO_PAD_CTRL) +#define MX53_PAD_FEC_RXD1__RTC_CE_RTC_PS1 IOMUX_PAD(0x5D4, 0x258, 4, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_FEC_RXD0__FEC_RDATA_0 IOMUX_PAD(0x5D8, 0x25C, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_FEC_RXD0__GPIO1_27 IOMUX_PAD(0x5D8, 0x25C, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_FEC_RXD0__ESAI1_HCKT IOMUX_PAD(0x5D8, 0x25C, 2, 0x7D8, 0, NO_PAD_CTRL) +#define MX53_PAD_FEC_RXD0__OSC32k_32K_OUT IOMUX_PAD(0x5D8, 0x25C, 3, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_FEC_TX_EN__FEC_TX_EN IOMUX_PAD(0x5DC, 0x260, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_FEC_TX_EN__GPIO1_28 IOMUX_PAD(0x5DC, 0x260, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_FEC_TX_EN__ESAI1_TX3_RX2 IOMUX_PAD(0x5DC, 0x260, 2, 0x7F0, 0, NO_PAD_CTRL) +#define MX53_PAD_FEC_TXD1__FEC_TDATA_1 IOMUX_PAD(0x5E0, 0x264, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_FEC_TXD1__GPIO1_29 IOMUX_PAD(0x5E0, 0x264, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_FEC_TXD1__ESAI1_TX2_RX3 IOMUX_PAD(0x5E0, 0x264, 2, 0x7EC, 0, NO_PAD_CTRL) +#define MX53_PAD_FEC_TXD1__MLB_MLBCLK IOMUX_PAD(0x5E0, 0x264, 3, 0x858, 1, NO_PAD_CTRL) +#define MX53_PAD_FEC_TXD1__RTC_CE_RTC_PRSC_CLK IOMUX_PAD(0x5E0, 0x264, 4, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_FEC_TXD0__FEC_TDATA_0 IOMUX_PAD(0x5E4, 0x268, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_FEC_TXD0__GPIO1_30 IOMUX_PAD(0x5E4, 0x268, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_FEC_TXD0__ESAI1_TX4_RX1 IOMUX_PAD(0x5E4, 0x268, 2, 0x7F4, 0, NO_PAD_CTRL) +#define MX53_PAD_FEC_TXD0__USBPHY2_DATAOUT_0 IOMUX_PAD(0x5E4, 0x268, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_FEC_MDC__FEC_MDC IOMUX_PAD(0x5E8, 0x26C, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_FEC_MDC__GPIO1_31 IOMUX_PAD(0x5E8, 0x26C, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_FEC_MDC__ESAI1_TX5_RX0 IOMUX_PAD(0x5E8, 0x26C, 2, 0x7F8, 0, NO_PAD_CTRL) +#define MX53_PAD_FEC_MDC__MLB_MLBDAT IOMUX_PAD(0x5E8, 0x26C, 3, 0x85C, 1, NO_PAD_CTRL) +#define MX53_PAD_FEC_MDC__RTC_CE_RTC_ALARM1_TRIG IOMUX_PAD(0x5E8, 0x26C, 4, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_FEC_MDC__USBPHY2_DATAOUT_1 IOMUX_PAD(0x5E8, 0x26C, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DIOW__PATA_DIOW IOMUX_PAD(0x5F0, 0x270, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DIOW__GPIO6_17 IOMUX_PAD(0x5F0, 0x270, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DIOW__UART1_TXD_MUX IOMUX_PAD(0x5F0, 0x270, 3, __NA_, 0, MX53_UART_PAD_CTRL) +#define MX53_PAD_PATA_DIOW__USBPHY2_DATAOUT_2 IOMUX_PAD(0x5F0, 0x270, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DMACK__PATA_DMACK IOMUX_PAD(0x5F4, 0x274, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DMACK__GPIO6_18 IOMUX_PAD(0x5F4, 0x274, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DMACK__UART1_RXD_MUX IOMUX_PAD(0x5F4, 0x274, 3, 0x878, 3, MX53_UART_PAD_CTRL) +#define MX53_PAD_PATA_DMACK__USBPHY2_DATAOUT_3 IOMUX_PAD(0x5F4, 0x274, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DMARQ__PATA_DMARQ IOMUX_PAD(0x5F8, 0x278, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DMARQ__GPIO7_0 IOMUX_PAD(0x5F8, 0x278, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DMARQ__UART2_TXD_MUX IOMUX_PAD(0x5F8, 0x278, 3, __NA_, 0, MX53_UART_PAD_CTRL) +#define MX53_PAD_PATA_DMARQ__CCM_CCM_OUT_0 IOMUX_PAD(0x5F8, 0x278, 5, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DMARQ__USBPHY2_DATAOUT_4 IOMUX_PAD(0x5F8, 0x278, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_BUFFER_EN__PATA_BUFFER_EN IOMUX_PAD(0x5FC, 0x27C, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_BUFFER_EN__GPIO7_1 IOMUX_PAD(0x5FC, 0x27C, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX IOMUX_PAD(0x5FC, 0x27C, 3, 0x880, 3, MX53_UART_PAD_CTRL) +#define MX53_PAD_PATA_BUFFER_EN__CCM_CCM_OUT_1 IOMUX_PAD(0x5FC, 0x27C, 5, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_BUFFER_EN__USBPHY2_DATAOUT_5 IOMUX_PAD(0x5FC, 0x27C, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_INTRQ__PATA_INTRQ IOMUX_PAD(0x600, 0x280, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_INTRQ__GPIO7_2 IOMUX_PAD(0x600, 0x280, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_INTRQ__UART2_CTS IOMUX_PAD(0x600, 0x280, 3, __NA_, 0, MX53_UART_PAD_CTRL) +#define MX53_PAD_PATA_INTRQ__CAN1_TXCAN IOMUX_PAD(0x600, 0x280, 4, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_INTRQ__CCM_CCM_OUT_2 IOMUX_PAD(0x600, 0x280, 5, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_INTRQ__USBPHY2_DATAOUT_6 IOMUX_PAD(0x600, 0x280, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DIOR__PATA_DIOR IOMUX_PAD(0x604, 0x284, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DIOR__GPIO7_3 IOMUX_PAD(0x604, 0x284, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DIOR__UART2_RTS IOMUX_PAD(0x604, 0x284, 3, 0x87C, 3, MX53_UART_PAD_CTRL) +#define MX53_PAD_PATA_DIOR__CAN1_RXCAN IOMUX_PAD(0x604, 0x284, 4, 0x760, 1, NO_PAD_CTRL) +#define MX53_PAD_PATA_DIOR__USBPHY2_DATAOUT_7 IOMUX_PAD(0x604, 0x284, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_RESET_B__PATA_PATA_RESET_B IOMUX_PAD(0x608, 0x288, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_RESET_B__GPIO7_4 IOMUX_PAD(0x608, 0x288, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_RESET_B__ESDHC3_CMD IOMUX_PAD(0x608, 0x288, 2, __NA_, 0, MX53_SDHC_PAD_CTRL) +#define MX53_PAD_PATA_RESET_B__UART1_CTS IOMUX_PAD(0x608, 0x288, 3, __NA_, 0, MX53_UART_PAD_CTRL) +#define MX53_PAD_PATA_RESET_B__CAN2_TXCAN IOMUX_PAD(0x608, 0x288, 4, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_RESET_B__USBPHY1_DATAOUT_0 IOMUX_PAD(0x608, 0x288, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_IORDY__PATA_IORDY IOMUX_PAD(0x60C, 0x28C, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_IORDY__GPIO7_5 IOMUX_PAD(0x60C, 0x28C, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_IORDY__ESDHC3_CLK IOMUX_PAD(0x60C, 0x28C, 2, __NA_, 0, MX53_SDHC_PAD_CTRL) +#define MX53_PAD_PATA_IORDY__UART1_RTS IOMUX_PAD(0x60C, 0x28C, 3, 0x874, 3, MX53_UART_PAD_CTRL) +#define MX53_PAD_PATA_IORDY__CAN2_RXCAN IOMUX_PAD(0x60C, 0x28C, 4, 0x764, 1, NO_PAD_CTRL) +#define MX53_PAD_PATA_IORDY__USBPHY1_DATAOUT_1 IOMUX_PAD(0x60C, 0x28C, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DA_0__PATA_DA_0 IOMUX_PAD(0x610, 0x290, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DA_0__GPIO7_6 IOMUX_PAD(0x610, 0x290, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DA_0__ESDHC3_RST IOMUX_PAD(0x610, 0x290, 2, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DA_0__OWIRE_LINE IOMUX_PAD(0x610, 0x290, 4, 0x864, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DA_0__USBPHY1_DATAOUT_2 IOMUX_PAD(0x610, 0x290, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DA_1__PATA_DA_1 IOMUX_PAD(0x614, 0x294, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DA_1__GPIO7_7 IOMUX_PAD(0x614, 0x294, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DA_1__ESDHC4_CMD IOMUX_PAD(0x614, 0x294, 2, __NA_, 0, MX53_SDHC_PAD_CTRL) +#define MX53_PAD_PATA_DA_1__UART3_CTS IOMUX_PAD(0x614, 0x294, 4, __NA_, 0, MX53_UART_PAD_CTRL) +#define MX53_PAD_PATA_DA_1__USBPHY1_DATAOUT_3 IOMUX_PAD(0x614, 0x294, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DA_2__PATA_DA_2 IOMUX_PAD(0x618, 0x298, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DA_2__GPIO7_8 IOMUX_PAD(0x618, 0x298, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DA_2__ESDHC4_CLK IOMUX_PAD(0x618, 0x298, 2, __NA_, 0, MX53_SDHC_PAD_CTRL) +#define MX53_PAD_PATA_DA_2__UART3_RTS IOMUX_PAD(0x618, 0x298, 4, 0x884, 5, MX53_UART_PAD_CTRL) +#define MX53_PAD_PATA_DA_2__USBPHY1_DATAOUT_4 IOMUX_PAD(0x618, 0x298, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_CS_0__PATA_CS_0 IOMUX_PAD(0x61C, 0x29C, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_CS_0__GPIO7_9 IOMUX_PAD(0x61C, 0x29C, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_CS_0__UART3_TXD_MUX IOMUX_PAD(0x61C, 0x29C, 4, __NA_, 0, MX53_UART_PAD_CTRL) +#define MX53_PAD_PATA_CS_0__USBPHY1_DATAOUT_5 IOMUX_PAD(0x61C, 0x29C, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_CS_1__PATA_CS_1 IOMUX_PAD(0x620, 0x2A0, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_CS_1__GPIO7_10 IOMUX_PAD(0x620, 0x2A0, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_CS_1__UART3_RXD_MUX IOMUX_PAD(0x620, 0x2A0, 4, 0x888, 3, MX53_UART_PAD_CTRL) +#define MX53_PAD_PATA_CS_1__USBPHY1_DATAOUT_6 IOMUX_PAD(0x620, 0x2A0, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DATA0__PATA_DATA_0 IOMUX_PAD(0x628, 0x2A4, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DATA0__GPIO2_0 IOMUX_PAD(0x628, 0x2A4, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DATA0__EMI_NANDF_D_0 IOMUX_PAD(0x628, 0x2A4, 3, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DATA0__ESDHC3_DAT4 IOMUX_PAD(0x628, 0x2A4, 4, __NA_, 0, MX53_SDHC_PAD_CTRL) +#define MX53_PAD_PATA_DATA0__GPU3d_GPU_DEBUG_OUT_0 IOMUX_PAD(0x628, 0x2A4, 5, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DATA0__IPU_DIAG_BUS_0 IOMUX_PAD(0x628, 0x2A4, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DATA0__USBPHY1_DATAOUT_7 IOMUX_PAD(0x628, 0x2A4, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DATA1__PATA_DATA_1 IOMUX_PAD(0x62C, 0x2A8, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DATA1__GPIO2_1 IOMUX_PAD(0x62C, 0x2A8, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DATA1__EMI_NANDF_D_1 IOMUX_PAD(0x62C, 0x2A8, 3, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DATA1__ESDHC3_DAT5 IOMUX_PAD(0x62C, 0x2A8, 4, __NA_, 0, MX53_SDHC_PAD_CTRL) +#define MX53_PAD_PATA_DATA1__GPU3d_GPU_DEBUG_OUT_1 IOMUX_PAD(0x62C, 0x2A8, 5, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DATA1__IPU_DIAG_BUS_1 IOMUX_PAD(0x62C, 0x2A8, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DATA2__PATA_DATA_2 IOMUX_PAD(0x630, 0x2AC, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DATA2__GPIO2_2 IOMUX_PAD(0x630, 0x2AC, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DATA2__EMI_NANDF_D_2 IOMUX_PAD(0x630, 0x2AC, 3, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DATA2__ESDHC3_DAT6 IOMUX_PAD(0x630, 0x2AC, 4, __NA_, 0, MX53_SDHC_PAD_CTRL) +#define MX53_PAD_PATA_DATA2__GPU3d_GPU_DEBUG_OUT_2 IOMUX_PAD(0x630, 0x2AC, 5, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DATA2__IPU_DIAG_BUS_2 IOMUX_PAD(0x630, 0x2AC, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DATA3__PATA_DATA_3 IOMUX_PAD(0x634, 0x2B0, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DATA3__GPIO2_3 IOMUX_PAD(0x634, 0x2B0, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DATA3__EMI_NANDF_D_3 IOMUX_PAD(0x634, 0x2B0, 3, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DATA3__ESDHC3_DAT7 IOMUX_PAD(0x634, 0x2B0, 4, __NA_, 0, MX53_SDHC_PAD_CTRL) +#define MX53_PAD_PATA_DATA3__GPU3d_GPU_DEBUG_OUT_3 IOMUX_PAD(0x634, 0x2B0, 5, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DATA3__IPU_DIAG_BUS_3 IOMUX_PAD(0x634, 0x2B0, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DATA4__PATA_DATA_4 IOMUX_PAD(0x638, 0x2B4, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DATA4__GPIO2_4 IOMUX_PAD(0x638, 0x2B4, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DATA4__EMI_NANDF_D_4 IOMUX_PAD(0x638, 0x2B4, 3, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DATA4__ESDHC4_DAT4 IOMUX_PAD(0x638, 0x2B4, 4, __NA_, 0, MX53_SDHC_PAD_CTRL) +#define MX53_PAD_PATA_DATA4__GPU3d_GPU_DEBUG_OUT_4 IOMUX_PAD(0x638, 0x2B4, 5, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DATA4__IPU_DIAG_BUS_4 IOMUX_PAD(0x638, 0x2B4, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DATA5__PATA_DATA_5 IOMUX_PAD(0x63C, 0x2B8, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DATA5__GPIO2_5 IOMUX_PAD(0x63C, 0x2B8, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DATA5__EMI_NANDF_D_5 IOMUX_PAD(0x63C, 0x2B8, 3, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DATA5__ESDHC4_DAT5 IOMUX_PAD(0x63C, 0x2B8, 4, __NA_, 0, MX53_SDHC_PAD_CTRL) +#define MX53_PAD_PATA_DATA5__GPU3d_GPU_DEBUG_OUT_5 IOMUX_PAD(0x63C, 0x2B8, 5, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DATA5__IPU_DIAG_BUS_5 IOMUX_PAD(0x63C, 0x2B8, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DATA6__PATA_DATA_6 IOMUX_PAD(0x640, 0x2BC, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DATA6__GPIO2_6 IOMUX_PAD(0x640, 0x2BC, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DATA6__EMI_NANDF_D_6 IOMUX_PAD(0x640, 0x2BC, 3, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DATA6__ESDHC4_DAT6 IOMUX_PAD(0x640, 0x2BC, 4, __NA_, 0, MX53_SDHC_PAD_CTRL) +#define MX53_PAD_PATA_DATA6__GPU3d_GPU_DEBUG_OUT_6 IOMUX_PAD(0x640, 0x2BC, 5, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DATA6__IPU_DIAG_BUS_6 IOMUX_PAD(0x640, 0x2BC, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DATA7__PATA_DATA_7 IOMUX_PAD(0x644, 0x2C0, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DATA7__GPIO2_7 IOMUX_PAD(0x644, 0x2C0, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DATA7__EMI_NANDF_D_7 IOMUX_PAD(0x644, 0x2C0, 3, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DATA7__ESDHC4_DAT7 IOMUX_PAD(0x644, 0x2C0, 4, __NA_, 0, MX53_SDHC_PAD_CTRL) +#define MX53_PAD_PATA_DATA7__GPU3d_GPU_DEBUG_OUT_7 IOMUX_PAD(0x644, 0x2C0, 5, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DATA7__IPU_DIAG_BUS_7 IOMUX_PAD(0x644, 0x2C0, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DATA8__PATA_DATA_8 IOMUX_PAD(0x648, 0x2C4, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DATA8__GPIO2_8 IOMUX_PAD(0x648, 0x2C4, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DATA8__ESDHC1_DAT4 IOMUX_PAD(0x648, 0x2C4, 2, __NA_, 0, MX53_SDHC_PAD_CTRL) +#define MX53_PAD_PATA_DATA8__EMI_NANDF_D_8 IOMUX_PAD(0x648, 0x2C4, 3, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DATA8__ESDHC3_DAT0 IOMUX_PAD(0x648, 0x2C4, 4, __NA_, 0, MX53_SDHC_PAD_CTRL) +#define MX53_PAD_PATA_DATA8__GPU3d_GPU_DEBUG_OUT_8 IOMUX_PAD(0x648, 0x2C4, 5, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DATA8__IPU_DIAG_BUS_8 IOMUX_PAD(0x648, 0x2C4, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DATA9__PATA_DATA_9 IOMUX_PAD(0x64C, 0x2C8, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DATA9__GPIO2_9 IOMUX_PAD(0x64C, 0x2C8, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DATA9__ESDHC1_DAT5 IOMUX_PAD(0x64C, 0x2C8, 2, __NA_, 0, MX53_SDHC_PAD_CTRL) +#define MX53_PAD_PATA_DATA9__EMI_NANDF_D_9 IOMUX_PAD(0x64C, 0x2C8, 3, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DATA9__ESDHC3_DAT1 IOMUX_PAD(0x64C, 0x2C8, 4, __NA_, 0, MX53_SDHC_PAD_CTRL) +#define MX53_PAD_PATA_DATA9__GPU3d_GPU_DEBUG_OUT_9 IOMUX_PAD(0x64C, 0x2C8, 5, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DATA9__IPU_DIAG_BUS_9 IOMUX_PAD(0x64C, 0x2C8, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DATA10__PATA_DATA_10 IOMUX_PAD(0x650, 0x2CC, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DATA10__GPIO2_10 IOMUX_PAD(0x650, 0x2CC, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DATA10__ESDHC1_DAT6 IOMUX_PAD(0x650, 0x2CC, 2, __NA_, 0, MX53_SDHC_PAD_CTRL) +#define MX53_PAD_PATA_DATA10__EMI_NANDF_D_10 IOMUX_PAD(0x650, 0x2CC, 3, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DATA10__ESDHC3_DAT2 IOMUX_PAD(0x650, 0x2CC, 4, __NA_, 0, MX53_SDHC_PAD_CTRL) +#define MX53_PAD_PATA_DATA10__GPU3d_GPU_DEBUG_OUT_10 IOMUX_PAD(0x650, 0x2CC, 5, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DATA10__IPU_DIAG_BUS_10 IOMUX_PAD(0x650, 0x2CC, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DATA11__PATA_DATA_11 IOMUX_PAD(0x654, 0x2D0, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DATA11__GPIO2_11 IOMUX_PAD(0x654, 0x2D0, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DATA11__ESDHC1_DAT7 IOMUX_PAD(0x654, 0x2D0, 2, __NA_, 0, MX53_SDHC_PAD_CTRL) +#define MX53_PAD_PATA_DATA11__EMI_NANDF_D_11 IOMUX_PAD(0x654, 0x2D0, 3, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DATA11__ESDHC3_DAT3 IOMUX_PAD(0x654, 0x2D0, 4, __NA_, 0, MX53_SDHC_PAD_CTRL) +#define MX53_PAD_PATA_DATA11__GPU3d_GPU_DEBUG_OUT_11 IOMUX_PAD(0x654, 0x2D0, 5, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DATA11__IPU_DIAG_BUS_11 IOMUX_PAD(0x654, 0x2D0, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DATA12__PATA_DATA_12 IOMUX_PAD(0x658, 0x2D4, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DATA12__GPIO2_12 IOMUX_PAD(0x658, 0x2D4, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DATA12__ESDHC2_DAT4 IOMUX_PAD(0x658, 0x2D4, 2, __NA_, 0, MX53_SDHC_PAD_CTRL) +#define MX53_PAD_PATA_DATA12__EMI_NANDF_D_12 IOMUX_PAD(0x658, 0x2D4, 3, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DATA12__ESDHC4_DAT0 IOMUX_PAD(0x658, 0x2D4, 4, __NA_, 0, MX53_SDHC_PAD_CTRL) +#define MX53_PAD_PATA_DATA12__GPU3d_GPU_DEBUG_OUT_12 IOMUX_PAD(0x658, 0x2D4, 5, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DATA12__IPU_DIAG_BUS_12 IOMUX_PAD(0x658, 0x2D4, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DATA13__PATA_DATA_13 IOMUX_PAD(0x65C, 0x2D8, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DATA13__GPIO2_13 IOMUX_PAD(0x65C, 0x2D8, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DATA13__ESDHC2_DAT5 IOMUX_PAD(0x65C, 0x2D8, 2, __NA_, 0, MX53_SDHC_PAD_CTRL) +#define MX53_PAD_PATA_DATA13__EMI_NANDF_D_13 IOMUX_PAD(0x65C, 0x2D8, 3, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DATA13__ESDHC4_DAT1 IOMUX_PAD(0x65C, 0x2D8, 4, __NA_, 0, MX53_SDHC_PAD_CTRL) +#define MX53_PAD_PATA_DATA13__GPU3d_GPU_DEBUG_OUT_13 IOMUX_PAD(0x65C, 0x2D8, 5, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DATA13__IPU_DIAG_BUS_13 IOMUX_PAD(0x65C, 0x2D8, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DATA14__PATA_DATA_14 IOMUX_PAD(0x660, 0x2DC, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DATA14__GPIO2_14 IOMUX_PAD(0x660, 0x2DC, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DATA14__ESDHC2_DAT6 IOMUX_PAD(0x660, 0x2DC, 2, __NA_, 0, MX53_SDHC_PAD_CTRL) +#define MX53_PAD_PATA_DATA14__EMI_NANDF_D_14 IOMUX_PAD(0x660, 0x2DC, 3, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DATA14__ESDHC4_DAT2 IOMUX_PAD(0x660, 0x2DC, 4, __NA_, 0, MX53_SDHC_PAD_CTRL) +#define MX53_PAD_PATA_DATA14__GPU3d_GPU_DEBUG_OUT_14 IOMUX_PAD(0x660, 0x2DC, 5, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DATA14__IPU_DIAG_BUS_14 IOMUX_PAD(0x660, 0x2DC, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DATA15__PATA_DATA_15 IOMUX_PAD(0x664, 0x2E0, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DATA15__GPIO2_15 IOMUX_PAD(0x664, 0x2E0, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DATA15__ESDHC2_DAT7 IOMUX_PAD(0x664, 0x2E0, 2, __NA_, 0, MX53_SDHC_PAD_CTRL) +#define MX53_PAD_PATA_DATA15__EMI_NANDF_D_15 IOMUX_PAD(0x664, 0x2E0, 3, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DATA15__ESDHC4_DAT3 IOMUX_PAD(0x664, 0x2E0, 4, __NA_, 0, MX53_SDHC_PAD_CTRL) +#define MX53_PAD_PATA_DATA15__GPU3d_GPU_DEBUG_OUT_15 IOMUX_PAD(0x664, 0x2E0, 5, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DATA15__IPU_DIAG_BUS_15 IOMUX_PAD(0x664, 0x2E0, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_SD1_DATA0__ESDHC1_DAT0 IOMUX_PAD(0x66C, 0x2E4, 0, __NA_, 0, MX53_SDHC_PAD_CTRL) +#define MX53_PAD_SD1_DATA0__GPIO1_16 IOMUX_PAD(0x66C, 0x2E4, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_SD1_DATA0__GPT_CAPIN1 IOMUX_PAD(0x66C, 0x2E4, 3, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_SD1_DATA0__CSPI_MISO IOMUX_PAD(0x66C, 0x2E4, 5, 0x784, 2, NO_PAD_CTRL) +#define MX53_PAD_SD1_DATA0__CCM_PLL3_BYP IOMUX_PAD(0x66C, 0x2E4, 7, 0x778, 0, NO_PAD_CTRL) +#define MX53_PAD_SD1_DATA1__ESDHC1_DAT1 IOMUX_PAD(0x670, 0x2E8, 0, __NA_, 0, MX53_SDHC_PAD_CTRL) +#define MX53_PAD_SD1_DATA1__GPIO1_17 IOMUX_PAD(0x670, 0x2E8, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_SD1_DATA1__GPT_CAPIN2 IOMUX_PAD(0x670, 0x2E8, 3, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_SD1_DATA1__CSPI_SS0 IOMUX_PAD(0x670, 0x2E8, 5, 0x78C, 3, NO_PAD_CTRL) +#define MX53_PAD_SD1_DATA1__CCM_PLL4_BYP IOMUX_PAD(0x670, 0x2E8, 7, 0x77C, 1, NO_PAD_CTRL) - #define MX53_PAD_SD1_CMD__ESDHC1_CMD IOMUX_PAD(0x674, 0x2EC, 0 | IOMUX_CONFIG_SION, __NA_, 0, MX53_SDHC_PAD_CTRL) ++#define MX53_PAD_SD1_CMD__ESDHC1_CMD IOMUX_PAD(0x674, 0x2EC, 0 | MUX_CONFIG_SION, __NA_, 0, MX53_SDHC_PAD_CTRL) +#define MX53_PAD_SD1_CMD__GPIO1_18 IOMUX_PAD(0x674, 0x2EC, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_SD1_CMD__GPT_CMPOUT1 IOMUX_PAD(0x674, 0x2EC, 3, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_SD1_CMD__CSPI_MOSI IOMUX_PAD(0x674, 0x2EC, 5, 0x788, 2, NO_PAD_CTRL) +#define MX53_PAD_SD1_CMD__CCM_PLL1_BYP IOMUX_PAD(0x674, 0x2EC, 7, 0x770, 0, NO_PAD_CTRL) +#define MX53_PAD_SD1_DATA2__ESDHC1_DAT2 IOMUX_PAD(0x678, 0x2F0, 0, __NA_, 0, MX53_SDHC_PAD_CTRL) +#define MX53_PAD_SD1_DATA2__GPIO1_19 IOMUX_PAD(0x678, 0x2F0, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_SD1_DATA2__GPT_CMPOUT2 IOMUX_PAD(0x678, 0x2F0, 2, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_SD1_DATA2__PWM2_PWMO IOMUX_PAD(0x678, 0x2F0, 3, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_SD1_DATA2__WDOG1_WDOG_B IOMUX_PAD(0x678, 0x2F0, 4, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_SD1_DATA2__CSPI_SS1 IOMUX_PAD(0x678, 0x2F0, 5, 0x790, 2, NO_PAD_CTRL) +#define MX53_PAD_SD1_DATA2__WDOG1_WDOG_RST_B_DEB IOMUX_PAD(0x678, 0x2F0, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_SD1_DATA2__CCM_PLL2_BYP IOMUX_PAD(0x678, 0x2F0, 7, 0x774, 0, NO_PAD_CTRL) +#define MX53_PAD_SD1_CLK__ESDHC1_CLK IOMUX_PAD(0x67C, 0x2F4, 0, __NA_, 0, MX53_SDHC_PAD_CTRL) +#define MX53_PAD_SD1_CLK__GPIO1_20 IOMUX_PAD(0x67C, 0x2F4, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_SD1_CLK__OSC32k_32K_OUT IOMUX_PAD(0x67C, 0x2F4, 2, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_SD1_CLK__GPT_CLKIN IOMUX_PAD(0x67C, 0x2F4, 3, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_SD1_CLK__CSPI_SCLK IOMUX_PAD(0x67C, 0x2F4, 5, 0x780, 2, NO_PAD_CTRL) +#define MX53_PAD_SD1_CLK__SATA_PHY_DTB_0 IOMUX_PAD(0x67C, 0x2F4, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_SD1_DATA3__ESDHC1_DAT3 IOMUX_PAD(0x680, 0x2F8, 0, __NA_, 0, MX53_SDHC_PAD_CTRL) +#define MX53_PAD_SD1_DATA3__GPIO1_21 IOMUX_PAD(0x680, 0x2F8, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_SD1_DATA3__GPT_CMPOUT3 IOMUX_PAD(0x680, 0x2F8, 2, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_SD1_DATA3__PWM1_PWMO IOMUX_PAD(0x680, 0x2F8, 3, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_SD1_DATA3__WDOG2_WDOG_B IOMUX_PAD(0x680, 0x2F8, 4, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_SD1_DATA3__CSPI_SS2 IOMUX_PAD(0x680, 0x2F8, 5, 0x794, 2, NO_PAD_CTRL) +#define MX53_PAD_SD1_DATA3__WDOG2_WDOG_RST_B_DEB IOMUX_PAD(0x680, 0x2F8, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_SD1_DATA3__SATA_PHY_DTB_1 IOMUX_PAD(0x680, 0x2F8, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_SD2_CLK__ESDHC2_CLK IOMUX_PAD(0x688, 0x2FC, 0, __NA_, 0, MX53_SDHC_PAD_CTRL) +#define MX53_PAD_SD2_CLK__GPIO1_10 IOMUX_PAD(0x688, 0x2FC, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_SD2_CLK__KPP_COL_5 IOMUX_PAD(0x688, 0x2FC, 2, 0x840, 2, NO_PAD_CTRL) +#define MX53_PAD_SD2_CLK__AUDMUX_AUD4_RXFS IOMUX_PAD(0x688, 0x2FC, 3, 0x73C, 1, NO_PAD_CTRL) +#define MX53_PAD_SD2_CLK__CSPI_SCLK IOMUX_PAD(0x688, 0x2FC, 5, 0x780, 3, NO_PAD_CTRL) +#define MX53_PAD_SD2_CLK__SCC_RANDOM_V IOMUX_PAD(0x688, 0x2FC, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_SD2_CMD__ESDHC2_CMD IOMUX_PAD(0x68C, 0x300, 0, __NA_, 0, MX53_SDHC_PAD_CTRL) +#define MX53_PAD_SD2_CMD__GPIO1_11 IOMUX_PAD(0x68C, 0x300, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_SD2_CMD__KPP_ROW_5 IOMUX_PAD(0x68C, 0x300, 2, 0x84C, 1, NO_PAD_CTRL) +#define MX53_PAD_SD2_CMD__AUDMUX_AUD4_RXC IOMUX_PAD(0x68C, 0x300, 3, 0x738, 1, NO_PAD_CTRL) +#define MX53_PAD_SD2_CMD__CSPI_MOSI IOMUX_PAD(0x68C, 0x300, 5, 0x788, 3, NO_PAD_CTRL) +#define MX53_PAD_SD2_CMD__SCC_RANDOM IOMUX_PAD(0x68C, 0x300, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_SD2_DATA3__ESDHC2_DAT3 IOMUX_PAD(0x690, 0x304, 0, __NA_, 0, MX53_SDHC_PAD_CTRL) +#define MX53_PAD_SD2_DATA3__GPIO1_12 IOMUX_PAD(0x690, 0x304, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_SD2_DATA3__KPP_COL_6 IOMUX_PAD(0x690, 0x304, 2, 0x844, 1, NO_PAD_CTRL) +#define MX53_PAD_SD2_DATA3__AUDMUX_AUD4_TXC IOMUX_PAD(0x690, 0x304, 3, 0x740, 1, NO_PAD_CTRL) +#define MX53_PAD_SD2_DATA3__CSPI_SS2 IOMUX_PAD(0x690, 0x304, 5, 0x794, 3, NO_PAD_CTRL) +#define MX53_PAD_SD2_DATA3__SJC_DONE IOMUX_PAD(0x690, 0x304, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_SD2_DATA2__ESDHC2_DAT2 IOMUX_PAD(0x694, 0x308, 0, __NA_, 0, MX53_SDHC_PAD_CTRL) +#define MX53_PAD_SD2_DATA2__GPIO1_13 IOMUX_PAD(0x694, 0x308, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_SD2_DATA2__KPP_ROW_6 IOMUX_PAD(0x694, 0x308, 2, 0x850, 1, NO_PAD_CTRL) +#define MX53_PAD_SD2_DATA2__AUDMUX_AUD4_TXD IOMUX_PAD(0x694, 0x308, 3, 0x734, 1, NO_PAD_CTRL) +#define MX53_PAD_SD2_DATA2__CSPI_SS1 IOMUX_PAD(0x694, 0x308, 5, 0x790, 3, NO_PAD_CTRL) +#define MX53_PAD_SD2_DATA2__SJC_FAIL IOMUX_PAD(0x694, 0x308, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_SD2_DATA1__ESDHC2_DAT1 IOMUX_PAD(0x698, 0x30C, 0, __NA_, 0, MX53_SDHC_PAD_CTRL) +#define MX53_PAD_SD2_DATA1__GPIO1_14 IOMUX_PAD(0x698, 0x30C, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_SD2_DATA1__KPP_COL_7 IOMUX_PAD(0x698, 0x30C, 2, 0x848, 1, NO_PAD_CTRL) +#define MX53_PAD_SD2_DATA1__AUDMUX_AUD4_TXFS IOMUX_PAD(0x698, 0x30C, 3, 0x744, 0, NO_PAD_CTRL) +#define MX53_PAD_SD2_DATA1__CSPI_SS0 IOMUX_PAD(0x698, 0x30C, 5, 0x78C, 4, NO_PAD_CTRL) +#define MX53_PAD_SD2_DATA1__RTIC_SEC_VIO IOMUX_PAD(0x698, 0x30C, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_SD2_DATA0__ESDHC2_DAT0 IOMUX_PAD(0x69C, 0x310, 0, __NA_, 0, MX53_SDHC_PAD_CTRL) +#define MX53_PAD_SD2_DATA0__GPIO1_15 IOMUX_PAD(0x69C, 0x310, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_SD2_DATA0__KPP_ROW_7 IOMUX_PAD(0x69C, 0x310, 2, 0x854, 1, NO_PAD_CTRL) +#define MX53_PAD_SD2_DATA0__AUDMUX_AUD4_RXD IOMUX_PAD(0x69C, 0x310, 3, 0x730, 1, NO_PAD_CTRL) +#define MX53_PAD_SD2_DATA0__CSPI_MISO IOMUX_PAD(0x69C, 0x310, 5, 0x784, 3, NO_PAD_CTRL) +#define MX53_PAD_SD2_DATA0__RTIC_DONE_INT IOMUX_PAD(0x69C, 0x310, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_0__CCM_CLKO IOMUX_PAD(0x6A4, 0x314, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_0__GPIO1_0 IOMUX_PAD(0x6A4, 0x314, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_0__KPP_COL_5 IOMUX_PAD(0x6A4, 0x314, 2, 0x840, 3, NO_PAD_CTRL) +#define MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK IOMUX_PAD(0x6A4, 0x314, 3, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_0__EPIT1_EPITO IOMUX_PAD(0x6A4, 0x314, 4, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_0__SRTC_ALARM_DEB IOMUX_PAD(0x6A4, 0x314, 5, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_0__USBOH3_USBH1_PWR IOMUX_PAD(0x6A4, 0x314, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_0__CSU_TD IOMUX_PAD(0x6A4, 0x314, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_1__ESAI1_SCKR IOMUX_PAD(0x6A8, 0x318, 0, 0x7DC, 1, NO_PAD_CTRL) +#define MX53_PAD_GPIO_1__GPIO1_1 IOMUX_PAD(0x6A8, 0x318, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_1__KPP_ROW_5 IOMUX_PAD(0x6A8, 0x318, 2, 0x84C, 2, NO_PAD_CTRL) +#define MX53_PAD_GPIO_1__CCM_SSI_EXT2_CLK IOMUX_PAD(0x6A8, 0x318, 3, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_1__PWM2_PWMO IOMUX_PAD(0x6A8, 0x318, 4, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_1__WDOG2_WDOG_B IOMUX_PAD(0x6A8, 0x318, 5, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_1__ESDHC1_CD IOMUX_PAD(0x6A8, 0x318, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_1__SRC_TESTER_ACK IOMUX_PAD(0x6A8, 0x318, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_9__ESAI1_FSR IOMUX_PAD(0x6AC, 0x31C, 0, 0x7CC, 1, NO_PAD_CTRL) +#define MX53_PAD_GPIO_9__GPIO1_9 IOMUX_PAD(0x6AC, 0x31C, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_9__KPP_COL_6 IOMUX_PAD(0x6AC, 0x31C, 2, 0x844, 2, NO_PAD_CTRL) +#define MX53_PAD_GPIO_9__CCM_REF_EN_B IOMUX_PAD(0x6AC, 0x31C, 3, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_9__PWM1_PWMO IOMUX_PAD(0x6AC, 0x31C, 4, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_9__WDOG1_WDOG_B IOMUX_PAD(0x6AC, 0x31C, 5, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_9__ESDHC1_WP IOMUX_PAD(0x6AC, 0x31C, 6, 0x7FC, 1, NO_PAD_CTRL) +#define MX53_PAD_GPIO_9__SCC_FAIL_STATE IOMUX_PAD(0x6AC, 0x31C, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_3__ESAI1_HCKR IOMUX_PAD(0x6B0, 0x320, 0, 0x7D4, 1, NO_PAD_CTRL) +#define MX53_PAD_GPIO_3__GPIO1_3 IOMUX_PAD(0x6B0, 0x320, 1, __NA_, 0, NO_PAD_CTRL) - #define MX53_PAD_GPIO_3__I2C3_SCL IOMUX_PAD(0x6B0, 0x320, 2 | IOMUX_CONFIG_SION, 0x824, 1, NO_PAD_CTRL) ++#define MX53_PAD_GPIO_3__I2C3_SCL IOMUX_PAD(0x6B0, 0x320, 2 | MUX_CONFIG_SION, 0x824, 1, NO_PAD_CTRL) +#define MX53_PAD_GPIO_3__DPLLIP1_TOG_EN IOMUX_PAD(0x6B0, 0x320, 3, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_3__CCM_CLKO2 IOMUX_PAD(0x6B0, 0x320, 4, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_3__OBSERVE_MUX_OBSRV_INT_OUT0 IOMUX_PAD(0x6B0, 0x320, 5, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_3__USBOH3_USBH1_OC IOMUX_PAD(0x6B0, 0x320, 6, 0x8A0, 1, NO_PAD_CTRL) +#define MX53_PAD_GPIO_3__MLB_MLBCLK IOMUX_PAD(0x6B0, 0x320, 7, 0x858, 2, NO_PAD_CTRL) +#define MX53_PAD_GPIO_6__ESAI1_SCKT IOMUX_PAD(0x6B4, 0x324, 0, 0x7E0, 1, NO_PAD_CTRL) +#define MX53_PAD_GPIO_6__GPIO1_6 IOMUX_PAD(0x6B4, 0x324, 1, __NA_, 0, NO_PAD_CTRL) - #define MX53_PAD_GPIO_6__I2C3_SDA IOMUX_PAD(0x6B4, 0x324, 2 | IOMUX_CONFIG_SION, 0x828, 1, NO_PAD_CTRL) ++#define MX53_PAD_GPIO_6__I2C3_SDA IOMUX_PAD(0x6B4, 0x324, 2 | MUX_CONFIG_SION, 0x828, 1, NO_PAD_CTRL) +#define MX53_PAD_GPIO_6__CCM_CCM_OUT_0 IOMUX_PAD(0x6B4, 0x324, 3, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_6__CSU_CSU_INT_DEB IOMUX_PAD(0x6B4, 0x324, 4, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_6__OBSERVE_MUX_OBSRV_INT_OUT1 IOMUX_PAD(0x6B4, 0x324, 5, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_6__ESDHC2_LCTL IOMUX_PAD(0x6B4, 0x324, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_6__MLB_MLBSIG IOMUX_PAD(0x6B4, 0x324, 7, 0x860, 2, NO_PAD_CTRL) +#define MX53_PAD_GPIO_2__ESAI1_FST IOMUX_PAD(0x6B8, 0x328, 0, 0x7D0, 1, NO_PAD_CTRL) +#define MX53_PAD_GPIO_2__GPIO1_2 IOMUX_PAD(0x6B8, 0x328, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_2__KPP_ROW_6 IOMUX_PAD(0x6B8, 0x328, 2, 0x850, 2, NO_PAD_CTRL) +#define MX53_PAD_GPIO_2__CCM_CCM_OUT_1 IOMUX_PAD(0x6B8, 0x328, 3, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_2__CSU_CSU_ALARM_AUT_0 IOMUX_PAD(0x6B8, 0x328, 4, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_2__OBSERVE_MUX_OBSRV_INT_OUT2 IOMUX_PAD(0x6B8, 0x328, 5, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_2__ESDHC2_WP IOMUX_PAD(0x6B8, 0x328, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_2__MLB_MLBDAT IOMUX_PAD(0x6B8, 0x328, 7, 0x85C, 2, NO_PAD_CTRL) +#define MX53_PAD_GPIO_4__ESAI1_HCKT IOMUX_PAD(0x6BC, 0x32C, 0, 0x7D8, 1, NO_PAD_CTRL) +#define MX53_PAD_GPIO_4__GPIO1_4 IOMUX_PAD(0x6BC, 0x32C, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_4__KPP_COL_7 IOMUX_PAD(0x6BC, 0x32C, 2, 0x848, 2, NO_PAD_CTRL) +#define MX53_PAD_GPIO_4__CCM_CCM_OUT_2 IOMUX_PAD(0x6BC, 0x32C, 3, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_4__CSU_CSU_ALARM_AUT_1 IOMUX_PAD(0x6BC, 0x32C, 4, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_4__OBSERVE_MUX_OBSRV_INT_OUT3 IOMUX_PAD(0x6BC, 0x32C, 5, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_4__ESDHC2_CD IOMUX_PAD(0x6BC, 0x32C, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_4__SCC_SEC_STATE IOMUX_PAD(0x6BC, 0x32C, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_5__ESAI1_TX2_RX3 IOMUX_PAD(0x6C0, 0x330, 0, 0x7EC, 1, NO_PAD_CTRL) +#define MX53_PAD_GPIO_5__GPIO1_5 IOMUX_PAD(0x6C0, 0x330, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_5__KPP_ROW_7 IOMUX_PAD(0x6C0, 0x330, 2, 0x854, 2, NO_PAD_CTRL) +#define MX53_PAD_GPIO_5__CCM_CLKO IOMUX_PAD(0x6C0, 0x330, 3, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_5__CSU_CSU_ALARM_AUT_2 IOMUX_PAD(0x6C0, 0x330, 4, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_5__OBSERVE_MUX_OBSRV_INT_OUT4 IOMUX_PAD(0x6C0, 0x330, 5, __NA_, 0, NO_PAD_CTRL) - #define MX53_PAD_GPIO_5__I2C3_SCL IOMUX_PAD(0x6C0, 0x330, 6 | IOMUX_CONFIG_SION, 0x824, 2, NO_PAD_CTRL) ++#define MX53_PAD_GPIO_5__I2C3_SCL IOMUX_PAD(0x6C0, 0x330, 6 | MUX_CONFIG_SION, 0x824, 2, NO_PAD_CTRL) +#define MX53_PAD_GPIO_5__CCM_PLL1_BYP IOMUX_PAD(0x6C0, 0x330, 7, 0x770, 1, NO_PAD_CTRL) +#define MX53_PAD_GPIO_7__ESAI1_TX4_RX1 IOMUX_PAD(0x6C4, 0x334, 0, 0x7F4, 1, NO_PAD_CTRL) +#define MX53_PAD_GPIO_7__GPIO1_7 IOMUX_PAD(0x6C4, 0x334, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_7__EPIT1_EPITO IOMUX_PAD(0x6C4, 0x334, 2, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_7__CAN1_TXCAN IOMUX_PAD(0x6C4, 0x334, 3, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_7__UART2_TXD_MUX IOMUX_PAD(0x6C4, 0x334, 4, __NA_, 0, MX53_UART_PAD_CTRL) +#define MX53_PAD_GPIO_7__FIRI_RXD IOMUX_PAD(0x6C4, 0x334, 5, 0x80C, 1, NO_PAD_CTRL) +#define MX53_PAD_GPIO_7__SPDIF_PLOCK IOMUX_PAD(0x6C4, 0x334, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_7__CCM_PLL2_BYP IOMUX_PAD(0x6C4, 0x334, 7, 0x774, 1, NO_PAD_CTRL) +#define MX53_PAD_GPIO_8__ESAI1_TX5_RX0 IOMUX_PAD(0x6C8, 0x338, 0, 0x7F8, 1, NO_PAD_CTRL) +#define MX53_PAD_GPIO_8__GPIO1_8 IOMUX_PAD(0x6C8, 0x338, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_8__EPIT2_EPITO IOMUX_PAD(0x6C8, 0x338, 2, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_8__CAN1_RXCAN IOMUX_PAD(0x6C8, 0x338, 3, 0x760, 2, NO_PAD_CTRL) +#define MX53_PAD_GPIO_8__UART2_RXD_MUX IOMUX_PAD(0x6C8, 0x338, 4, 0x880, 5, MX53_UART_PAD_CTRL) +#define MX53_PAD_GPIO_8__FIRI_TXD IOMUX_PAD(0x6C8, 0x338, 5, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_8__SPDIF_SRCLK IOMUX_PAD(0x6C8, 0x338, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_8__CCM_PLL3_BYP IOMUX_PAD(0x6C8, 0x338, 7, 0x778, 1, NO_PAD_CTRL) +#define MX53_PAD_GPIO_16__ESAI1_TX3_RX2 IOMUX_PAD(0x6CC, 0x33C, 0, 0x7F0, 1, NO_PAD_CTRL) +#define MX53_PAD_GPIO_16__GPIO7_11 IOMUX_PAD(0x6CC, 0x33C, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_16__TZIC_PWRFAIL_INT IOMUX_PAD(0x6CC, 0x33C, 2, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_16__RTC_CE_RTC_EXT_TRIG1 IOMUX_PAD(0x6CC, 0x33C, 4, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_16__SPDIF_IN1 IOMUX_PAD(0x6CC, 0x33C, 5, 0x870, 1, NO_PAD_CTRL) - #define MX53_PAD_GPIO_16__I2C3_SDA IOMUX_PAD(0x6CC, 0x33C, 6 | IOMUX_CONFIG_SION, 0x828, 2, NO_PAD_CTRL) ++#define MX53_PAD_GPIO_16__I2C3_SDA IOMUX_PAD(0x6CC, 0x33C, 6 | MUX_CONFIG_SION, 0x828, 2, NO_PAD_CTRL) +#define MX53_PAD_GPIO_16__SJC_DE_B IOMUX_PAD(0x6CC, 0x33C, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_17__ESAI1_TX0 IOMUX_PAD(0x6D0, 0x340, 0, 0x7E4, 1, NO_PAD_CTRL) +#define MX53_PAD_GPIO_17__GPIO7_12 IOMUX_PAD(0x6D0, 0x340, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_17__SDMA_EXT_EVENT_0 IOMUX_PAD(0x6D0, 0x340, 2, 0x868, 1, NO_PAD_CTRL) +#define MX53_PAD_GPIO_17__GPC_PMIC_RDY IOMUX_PAD(0x6D0, 0x340, 3, 0x810, 1, NO_PAD_CTRL) +#define MX53_PAD_GPIO_17__RTC_CE_RTC_FSV_TRIG IOMUX_PAD(0x6D0, 0x340, 4, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_17__SPDIF_OUT1 IOMUX_PAD(0x6D0, 0x340, 5, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_17__IPU_SNOOP2 IOMUX_PAD(0x6D0, 0x340, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_17__SJC_JTAG_ACT IOMUX_PAD(0x6D0, 0x340, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_18__ESAI1_TX1 IOMUX_PAD(0x6D4, 0x344, 0, 0x7E8, 1, NO_PAD_CTRL) +#define MX53_PAD_GPIO_18__GPIO7_13 IOMUX_PAD(0x6D4, 0x344, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_18__SDMA_EXT_EVENT_1 IOMUX_PAD(0x6D4, 0x344, 2, 0x86C, 1, NO_PAD_CTRL) +#define MX53_PAD_GPIO_18__OWIRE_LINE IOMUX_PAD(0x6D4, 0x344, 3, 0x864, 1, NO_PAD_CTRL) +#define MX53_PAD_GPIO_18__RTC_CE_RTC_ALARM2_TRIG IOMUX_PAD(0x6D4, 0x344, 4, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_18__CCM_ASRC_EXT_CLK IOMUX_PAD(0x6D4, 0x344, 5, 0x768, 1, NO_PAD_CTRL) +#define MX53_PAD_GPIO_18__ESDHC1_LCTL IOMUX_PAD(0x6D4, 0x344, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_18__SRC_SYSTEM_RST IOMUX_PAD(0x6D4, 0x344, 7, __NA_, 0, NO_PAD_CTRL) + - #endif /* __MACH_IOMUX_MX53_H__ */ ++#endif /* __ASM_ARCH_IOMUX_MX53_H__ */ diff --cc arch/arm/include/asm/arch-mx5/sys_proto.h index 7b5246eea6,93ad1c6b33..e036ae6673 --- a/arch/arm/include/asm/arch-mx5/sys_proto.h +++ b/arch/arm/include/asm/arch-mx5/sys_proto.h @@@ -24,10 -24,18 +24,19 @@@ #ifndef _SYS_PROTO_H_ #define _SYS_PROTO_H_ - u32 get_cpu_rev(void); + #define MXC_CPU_MX51 0x51 + #define MXC_CPU_MX53 0x53 + #define MXC_CPU_MX6SL 0x60 + #define MXC_CPU_MX6DL 0x61 + #define MXC_CPU_MX6SOLO 0x62 + #define MXC_CPU_MX6Q 0x63 + #define is_soc_rev(rev) ((get_cpu_rev() & 0xFF) - rev) + u32 get_cpu_rev(void); + unsigned imx_ddr_size(void); void sdelay(unsigned long); void set_chipselect_size(int const); ++void imx_get_mac_from_fuse(int dev_id, unsigned char *mac); /* * Initializes on-chip ethernet controllers. diff --cc arch/arm/include/asm/arch-mx6/clock.h index b91d8bf450,db377cc31d..1104c857c4 --- a/arch/arm/include/asm/arch-mx6/clock.h +++ b/arch/arm/include/asm/arch-mx6/clock.h @@@ -41,12 -55,14 +55,66 @@@ enum mxc_clock MXC_ESDHC4_CLK, MXC_SATA_CLK, MXC_NFC_CLK, + MXC_I2C_CLK, + }; + ++ ++struct clk { ++ const char *name; ++ int id; ++ /* Source clock this clk depends on */ ++ struct clk *parent; ++ /* Secondary clock to enable/disable with this clock */ ++ struct clk *secondary; ++ /* Current clock rate */ ++ unsigned long rate; ++ /* Reference count of clock enable/disable */ ++ __s8 usecount; ++ /* Register bit position for clock's enable/disable control. */ ++ u8 enable_shift; ++ /* Register address for clock's enable/disable control. */ ++ void *enable_reg; ++ u32 flags; ++ /* ++ * Function ptr to recalculate the clock's rate based on parent ++ * clock's rate ++ */ ++ void (*recalc) (struct clk *); ++ /* ++ * Function ptr to set the clock to a new rate. The rate must match a ++ * supported rate returned from round_rate. Leave blank if clock is not ++ * programmable ++ */ ++ int (*set_rate) (struct clk *, unsigned long); ++ /* ++ * Function ptr to round the requested clock rate to the nearest ++ * supported rate that is less than or equal to the requested rate. ++ */ ++ unsigned long (*round_rate) (struct clk *, unsigned long); ++ /* ++ * Function ptr to enable the clock. Leave blank if clock can not ++ * be gated. ++ */ ++ int (*enable) (struct clk *); ++ /* ++ * Function ptr to disable the clock. Leave blank if clock can not ++ * be gated. ++ */ ++ void (*disable) (struct clk *); ++ /* Function ptr to set the parent clock of the clock. */ ++ int (*set_parent) (struct clk *, struct clk *); +}; + u32 imx_get_uartclk(void); u32 imx_get_fecclk(void); unsigned int mxc_get_clock(enum mxc_clock clk); ++int mxc_set_clock(u32 ref, u32 freq, enum mxc_clock clk); void enable_usboh3_clk(unsigned char enable); int enable_sata_clock(void); + int enable_i2c_clk(unsigned char enable, unsigned i2c_num); ++void ipu_clk_enable(void); ++void ipu_clk_disable(void); ++void ocotp_clk_enable(void); ++void ocotp_clk_disable(void); #endif /* __ASM_ARCH_CLOCK_H */ diff --cc arch/arm/include/asm/arch-mx6/crm_regs.h index 0e605c26f5,d670f30c02..038cd70e4a --- a/arch/arm/include/asm/arch-mx6/crm_regs.h +++ b/arch/arm/include/asm/arch-mx6/crm_regs.h @@@ -56,64 -56,64 +56,16 @@@ struct mxc_ccm_reg u32 CCGR6; /* 0x0080 */ u32 CCGR7; u32 cmeor; -- u32 resv[0xfdd]; -- u32 analog_pll_sys; /* 0x4000 */ -- u32 analog_pll_sys_set; -- u32 analog_pll_sys_clr; -- u32 analog_pll_sys_tog; -- u32 analog_usb1_pll_480_ctrl; /* 0x4010 */ -- u32 analog_usb1_pll_480_ctrl_set; -- u32 analog_usb1_pll_480_ctrl_clr; -- u32 analog_usb1_pll_480_ctrl_tog; -- u32 analog_reserved0[4]; -- u32 analog_pll_528; /* 0x4030 */ -- u32 analog_pll_528_set; -- u32 analog_pll_528_clr; -- u32 analog_pll_528_tog; -- u32 analog_pll_528_ss; /* 0x4040 */ -- u32 analog_reserved1[3]; -- u32 analog_pll_528_num; /* 0x4050 */ -- u32 analog_reserved2[3]; -- u32 analog_pll_528_denom; /* 0x4060 */ -- u32 analog_reserved3[3]; -- u32 analog_pll_audio; /* 0x4070 */ -- u32 analog_pll_audio_set; -- u32 analog_pll_audio_clr; -- u32 analog_pll_audio_tog; -- u32 analog_pll_audio_num; /* 0x4080*/ -- u32 analog_reserved4[3]; -- u32 analog_pll_audio_denom; /* 0x4090 */ -- u32 analog_reserved5[3]; -- u32 analog_pll_video; /* 0x40a0 */ -- u32 analog_pll_video_set; -- u32 analog_pll_video_clr; -- u32 analog_pll_video_tog; -- u32 analog_pll_video_num; /* 0x40b0 */ -- u32 analog_reserved6[3]; -- u32 analog_pll_vedio_denon; /* 0x40c0 */ -- u32 analog_reserved7[7]; -- u32 analog_pll_enet; /* 0x40e0 */ -- u32 analog_pll_enet_set; -- u32 analog_pll_enet_clr; -- u32 analog_pll_enet_tog; -- u32 analog_pfd_480; /* 0x40f0 */ -- u32 analog_pfd_480_set; -- u32 analog_pfd_480_clr; -- u32 analog_pfd_480_tog; -- u32 analog_pfd_528; /* 0x4100 */ -- u32 analog_pfd_528_set; -- u32 analog_pfd_528_clr; -- u32 analog_pfd_528_tog; }; /* Define the bits in register CCR */ #define MXC_CCM_CCR_RBC_EN (1 << 27) --#define MXC_CCM_CCR_REG_BYPASS_CNT_MASK (0x3F << 21) ++#define MXC_CCM_CCR_REG_BYPASS_CNT_MASK (0x3F << CCR_REG_BYPASS_CNT_OFFSET) #define MXC_CCM_CCR_REG_BYPASS_CNT_OFFSET 21 --#define MXC_CCM_CCR_WB_COUNT_MASK 0x7 ++#define MXC_CCM_CCR_WB_COUNT_MASK (0x7 << MXC_CCM_CCR_WB_COUNT_OFFSET) #define MXC_CCM_CCR_WB_COUNT_OFFSET (1 << 16) #define MXC_CCM_CCR_COSC_EN (1 << 12) --#define MXC_CCM_CCR_OSCNT_MASK 0xFF ++#define MXC_CCM_CCR_OSCNT_MASK (0xFF << MXC_CCM_CCR_OSCNT_OFFSET) #define MXC_CCM_CCR_OSCNT_OFFSET 0 /* Define the bits in register CCDR */ @@@ -139,185 -139,189 +91,186 @@@ /* Define the bits in register CACRR */ #define MXC_CCM_CACRR_ARM_PODF_OFFSET 0 --#define MXC_CCM_CACRR_ARM_PODF_MASK 0x7 ++#define MXC_CCM_CACRR_ARM_PODF_MASK (0x7 << MXC_CCM_CACRR_ARM_PODF_OFFSET) /* Define the bits in register CBCDR */ --#define MXC_CCM_CBCDR_PERIPH_CLK2_PODF_MASK (0x7 << 27) ++#define MXC_CCM_CBCDR_PERIPH_CLK2_PODF_MASK (0x7 << MXC_CCM_CBCDR_PERIPH_CLK2_PODF_OFFSET) #define MXC_CCM_CBCDR_PERIPH_CLK2_PODF_OFFSET 27 #define MXC_CCM_CBCDR_PERIPH2_CLK2_SEL (1 << 26) #define MXC_CCM_CBCDR_PERIPH_CLK_SEL (1 << 25) --#define MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK (0x7 << 19) ++#define MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK (0x7 << MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET) #define MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET 19 --#define MXC_CCM_CBCDR_AXI_PODF_MASK (0x7 << 16) ++#define MXC_CCM_CBCDR_AXI_PODF_MASK (0x7 << MXC_CCM_CBCDR_AXI_PODF_OFFSET) #define MXC_CCM_CBCDR_AXI_PODF_OFFSET 16 --#define MXC_CCM_CBCDR_AHB_PODF_MASK (0x7 << 10) ++#define MXC_CCM_CBCDR_AHB_PODF_MASK (0x7 << MXC_CCM_CBCDR_AHB_PODF_OFFSET) #define MXC_CCM_CBCDR_AHB_PODF_OFFSET 10 --#define MXC_CCM_CBCDR_IPG_PODF_MASK (0x3 << 8) ++#define MXC_CCM_CBCDR_IPG_PODF_MASK (0x3 << MXC_CCM_CBCDR_IPG_PODF_OFFSET) #define MXC_CCM_CBCDR_IPG_PODF_OFFSET 8 #define MXC_CCM_CBCDR_AXI_ALT_SEL (1 << 7) #define MXC_CCM_CBCDR_AXI_SEL (1 << 6) --#define MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK (0x7 << 3) ++#define MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK (0x7 << MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET) #define MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET 3 --#define MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_MASK (0x7 << 0) ++#define MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_MASK (0x7 << MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_OFFSET) #define MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_OFFSET 0 /* Define the bits in register CBCMR */ --#define MXC_CCM_CBCMR_GPU3D_SHADER_PODF_MASK (0x7 << 29) ++#define MXC_CCM_CBCMR_GPU3D_SHADER_PODF_MASK (0x7 << MXC_CCM_CBCMR_GPU3D_SHADER_PODF_OFFSET) #define MXC_CCM_CBCMR_GPU3D_SHADER_PODF_OFFSET 29 --#define MXC_CCM_CBCMR_GPU3D_CORE_PODF_MASK (0x7 << 26) ++#define MXC_CCM_CBCMR_GPU3D_CORE_PODF_MASK (0x7 << MXC_CCM_CBCMR_GPU3D_CORE_PODF_OFFSET) #define MXC_CCM_CBCMR_GPU3D_CORE_PODF_OFFSET 26 --#define MXC_CCM_CBCMR_GPU2D_CORE_PODF_MASK (0x7 << 23) ++#define MXC_CCM_CBCMR_GPU2D_CORE_PODF_MASK (0x7 << MXC_CCM_CBCMR_GPU2D_CORE_PODF_OFFSET) #define MXC_CCM_CBCMR_GPU2D_CORE_PODF_OFFSET 23 --#define MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK (0x3 << 21) ++#define MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK (0x3 << MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET) #define MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET 21 #define MXC_CCM_CBCMR_PRE_PERIPH2_CLK2_SEL (1 << 20) --#define MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK (0x3 << 18) ++#define MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK (0x3 << MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET) #define MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET 18 --#define MXC_CCM_CBCMR_GPU2D_CLK_SEL_MASK (0x3 << 16) ++#define MXC_CCM_CBCMR_GPU2D_CLK_SEL_MASK (0x3 << MXC_CCM_CBCMR_GPU2D_CLK_SEL_OFFSET) #define MXC_CCM_CBCMR_GPU2D_CLK_SEL_OFFSET 16 --#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_MASK (0x3 << 14) ++#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_MASK (0x3 << MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET) #define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET 14 --#define MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK (0x3 << 12) ++#define MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK (0x3 << MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET) #define MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET 12 #define MXC_CCM_CBCMR_VDOAXI_CLK_SEL (1 << 11) #define MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL (1 << 10) --#define MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_MASK (0x3 << 8) ++#define MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_MASK (0x3 << MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_OFFSET) #define MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_OFFSET 8 --#define MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_MASK (0x3 << 4) ++#define MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_MASK (0x3 << MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_OFFSET) #define MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_OFFSET 4 #define MXC_CCM_CBCMR_GPU3D_AXI_CLK_SEL (1 << 1) #define MXC_CCM_CBCMR_GPU2D_AXI_CLK_SEL (1 << 0) /* Define the bits in register CSCMR1 */ --#define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK (0x3 << 29) ++#define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK (0x3 << MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET) #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET 29 --#define MXC_CCM_CSCMR1_ACLK_EMI_MASK (0x3 << 27) ++#define MXC_CCM_CSCMR1_ACLK_EMI_MASK (0x3 << MXC_CCM_CSCMR1_ACLK_EMI_OFFSET) #define MXC_CCM_CSCMR1_ACLK_EMI_OFFSET 27 --#define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK (0x7 << 23) ++#define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK (0x7 << MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET) #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET 23 --#define MXC_CCM_CSCMR1_ACLK_EMI_PODF_MASK (0x7 << 20) ++#define MXC_CCM_CSCMR1_ACLK_EMI_PODF_MASK (0x7 << MXC_CCM_CSCMR1_ACLK_EMI_PODF_OFFSET) #define MXC_CCM_CSCMR1_ACLK_EMI_PODF_OFFSET 20 #define MXC_CCM_CSCMR1_USDHC4_CLK_SEL (1 << 19) #define MXC_CCM_CSCMR1_USDHC3_CLK_SEL (1 << 18) #define MXC_CCM_CSCMR1_USDHC2_CLK_SEL (1 << 17) #define MXC_CCM_CSCMR1_USDHC1_CLK_SEL (1 << 16) --#define MXC_CCM_CSCMR1_SSI3_CLK_SEL_MASK (0x3 << 14) ++#define MXC_CCM_CSCMR1_SSI3_CLK_SEL_MASK (0x3 << MXC_CCM_CSCMR1_SSI3_CLK_SEL_OFFSET) #define MXC_CCM_CSCMR1_SSI3_CLK_SEL_OFFSET 14 --#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_MASK (0x3 << 12) ++#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_MASK (0x3 << MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET) #define MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET 12 --#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK (0x3 << 10) ++#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK (0x3 << MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET) #define MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET 10 --#define MXC_CCM_CSCMR1_PERCLK_PODF_MASK 0x3F ++#define MXC_CCM_CSCMR1_PERCLK_PODF_OFFSET 0 ++#define MXC_CCM_CSCMR1_PERCLK_PODF_MASK (0x3F << MXC_CCM_CSCMR1_PERCLK_PODF_OFFSET) /* Define the bits in register CSCMR2 */ --#define MXC_CCM_CSCMR2_ESAI_PRE_SEL_MASK (0x3 << 19) ++#define MXC_CCM_CSCMR2_ESAI_PRE_SEL_MASK (0x3 << MXC_CCM_CSCMR2_ESAI_PRE_SEL_OFFSET) #define MXC_CCM_CSCMR2_ESAI_PRE_SEL_OFFSET 19 #define MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV (1 << 11) #define MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV (1 << 10) --#define MXC_CCM_CSCMR2_CAN_CLK_SEL_MASK (0x3F << 2) ++#define MXC_CCM_CSCMR2_CAN_CLK_SEL_MASK (0x3F << MXC_CCM_CSCMR2_CAN_CLK_SEL_OFFSET) #define MXC_CCM_CSCMR2_CAN_CLK_SEL_OFFSET 2 /* Define the bits in register CSCDR1 */ --#define MXC_CCM_CSCDR1_VPU_AXI_PODF_MASK (0x7 << 25) ++#define MXC_CCM_CSCDR1_VPU_AXI_PODF_MASK (0x7 << MXC_CCM_CSCDR1_VPU_AXI_PODF_OFFSET) #define MXC_CCM_CSCDR1_VPU_AXI_PODF_OFFSET 25 --#define MXC_CCM_CSCDR1_USDHC4_PODF_MASK (0x7 << 22) ++#define MXC_CCM_CSCDR1_USDHC4_PODF_MASK (0x7 << MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET) #define MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET 22 --#define MXC_CCM_CSCDR1_USDHC3_PODF_MASK (0x7 << 19) ++#define MXC_CCM_CSCDR1_USDHC3_PODF_MASK (0x7 << MXC_CCM_CSCDR1_USDHC3_PODF_OFFSET) #define MXC_CCM_CSCDR1_USDHC3_PODF_OFFSET 19 --#define MXC_CCM_CSCDR1_USDHC2_PODF_MASK (0x7 << 16) ++#define MXC_CCM_CSCDR1_USDHC2_PODF_MASK (0x7 << MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET) #define MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET 16 --#define MXC_CCM_CSCDR1_USDHC1_PODF_MASK (0x7 << 11) ++#define MXC_CCM_CSCDR1_USDHC1_PODF_MASK (0x7 << MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET) #define MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET 11 #define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET 8 --#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK (0x7 << 8) ++#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK (0x7 << MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET) #define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET 6 --#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK (0x3 << 6) --#define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK 0x3F ++#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK (0x3 << MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET) ++#define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK (0x3F << MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET) #define MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET 0 /* Define the bits in register CS1CDR */ --#define MXC_CCM_CS1CDR_ESAI_CLK_PODF_MASK (0x3F << 25) ++#define MXC_CCM_CS1CDR_ESAI_CLK_PODF_MASK (0x3F << MXC_CCM_CS1CDR_ESAI_CLK_PODF_OFFSET) #define MXC_CCM_CS1CDR_ESAI_CLK_PODF_OFFSET 25 --#define MXC_CCM_CS1CDR_SSI3_CLK_PODF_MASK (0x3F << 16) ++#define MXC_CCM_CS1CDR_SSI3_CLK_PODF_MASK (0x3F << MXC_CCM_CS1CDR_SSI3_CLK_PODF_OFFSET) #define MXC_CCM_CS1CDR_SSI3_CLK_PODF_OFFSET 16 --#define MXC_CCM_CS1CDR_ESAI_CLK_PRED_MASK (0x3 << 9) ++#define MXC_CCM_CS1CDR_ESAI_CLK_PRED_MASK (0x3 << MXC_CCM_CS1CDR_ESAI_CLK_PRED_OFFSET) #define MXC_CCM_CS1CDR_ESAI_CLK_PRED_OFFSET 9 --#define MXC_CCM_CS1CDR_SSI1_CLK_PRED_MASK (0x7 << 6) ++#define MXC_CCM_CS1CDR_SSI1_CLK_PRED_MASK (0x7 << MXC_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET) #define MXC_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET 6 --#define MXC_CCM_CS1CDR_SSI1_CLK_PODF_MASK 0x3F ++#define MXC_CCM_CS1CDR_SSI1_CLK_PODF_MASK (0x3F << MXC_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET) #define MXC_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET 0 /* Define the bits in register CS2CDR */ --#define MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK (0x3F << 21) ++#define MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK (0x3F << MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET) #define MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET 21 --#define MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK (0x7 << 18) ++#define MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK (0x7 << MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET) #define MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET 18 --#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK (0x3 << 16) ++#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK (0x3 << MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET) #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET 16 --#define MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK (0x7 << 12) ++#define MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK (0x7 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET) #define MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET 12 --#define MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK (0x7 << 9) ++#define MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK (0x7 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET) #define MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET 9 --#define MXC_CCM_CS2CDR_SSI2_CLK_PRED_MASK (0x7 << 6) ++#define MXC_CCM_CS2CDR_SSI2_CLK_PRED_MASK (0x7 << MXC_CCM_CS2CDR_SSI2_CLK_PRED_OFFSET) #define MXC_CCM_CS2CDR_SSI2_CLK_PRED_OFFSET 6 --#define MXC_CCM_CS2CDR_SSI2_CLK_PODF_MASK 0x3F ++#define MXC_CCM_CS2CDR_SSI2_CLK_PODF_MASK (0x3F << MXC_CCM_CS2CDR_SSI2_CLK_PODF_OFFSET) #define MXC_CCM_CS2CDR_SSI2_CLK_PODF_OFFSET 0 /* Define the bits in register CDCDR */ --#define MXC_CCM_CDCDR_HSI_TX_PODF_MASK (0x7 << 29) ++#define MXC_CCM_CDCDR_HSI_TX_PODF_MASK (0x7 << MXC_CCM_CDCDR_HSI_TX_PODF_OFFSET) #define MXC_CCM_CDCDR_HSI_TX_PODF_OFFSET 29 #define MXC_CCM_CDCDR_HSI_TX_CLK_SEL (1 << 28) --#define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_MASK (0x7 << 25) ++#define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_MASK (0x7 << MXC_CCM_CDCDR_SPDIF0_CLK_PRED_OFFSET) #define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_OFFSET 25 --#define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_MASK (0x7 << 19) ++#define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_MASK (0x7 << MXC_CCM_CDCDR_SPDIF0_CLK_PODF_OFFSET) #define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_OFFSET 19 --#define MXC_CCM_CDCDR_SPDIF0_CLK_SEL_MASK (0x3 << 20) ++#define MXC_CCM_CDCDR_SPDIF0_CLK_SEL_MASK (0x3 << MXC_CCM_CDCDR_SPDIF0_CLK_SEL_OFFSET) #define MXC_CCM_CDCDR_SPDIF0_CLK_SEL_OFFSET 20 --#define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_MASK (0x7 << 12) ++#define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_MASK (0x7 << MXC_CCM_CDCDR_SPDIF1_CLK_PRED_OFFSET) #define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_OFFSET 12 --#define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_MASK (0x7 << 9) ++#define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_MASK (0x7 << MXC_CCM_CDCDR_SPDIF1_CLK_PODF_OFFSET) #define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_OFFSET 9 --#define MXC_CCM_CDCDR_SPDIF1_CLK_SEL_MASK (0x3 << 7) ++#define MXC_CCM_CDCDR_SPDIF1_CLK_SEL_MASK (0x3 << MXC_CCM_CDCDR_SPDIF1_CLK_SEL_OFFSET) #define MXC_CCM_CDCDR_SPDIF1_CLK_SEL_OFFSET 7 /* Define the bits in register CHSCCDR */ --#define MXC_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_MASK (0x7 << 15) ++#define MXC_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_MASK (0x7 << MXC_CCM_CHSCCDR_DI1_PRE_CLK_SEL_OFFSET) #define MXC_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_OFFSET 15 --#define MXC_CCM_CHSCCDR_IPU1_DI1_PODF_MASK (0x7 << 12) ++#define MXC_CCM_CHSCCDR_IPU1_DI1_PODF_MASK (0x7 << MXC_CCM_CHSCCDR_IPU1_DI1_PODF_OFFSET) #define MXC_CCM_CHSCCDR_IPU1_DI1_PODF_OFFSET 12 --#define MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_MASK (0x7 << 9) ++#define MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_MASK (0x7 << MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET) #define MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET 9 --#define MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK (0x7 << 6) ++#define MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK (0x7 << MXC_CCM_CHSCCDR_DI0_PRE_CLK_SEL_OFFSET) #define MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET 6 --#define MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK (0x7 << 3) ++#define MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK (0x7 << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET) #define MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET 3 --#define MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK (0x7) ++#define MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK (0x7 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET) #define MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET 0 -#define CHSCCDR_CLK_SEL_LDB_DI0 3 -#define CHSCCDR_PODF_DIVIDE_BY_3 2 -#define CHSCCDR_IPU_PRE_CLK_540M_PFD 5 - /* Define the bits in register CSCDR2 */ --#define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK (0x3F << 19) ++#define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK (0x3F << MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET) #define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET 19 --#define MXC_CCM_CHSCCDR_IPU2_DI1_PRE_CLK_SEL_MASK (0x7 << 15) --#define MXC_CCM_CHSCCDR_IPU2_DI1_PRE_CLK_SEL_OFFSET 15 --#define MXC_CCM_CHSCCDR_IPU2_DI1_PODF_MASK (0x7 << 12) --#define MXC_CCM_CHSCCDR_IPU2_DI1_PODF_OFFSET 12 --#define MXC_CCM_CHSCCDR_IPU2_DI1_CLK_SEL_MASK (0x7 << 9) --#define MXC_CCM_CHSCCDR_IPU2_DI1_CLK_SEL_OFFSET 9 --#define MXC_CCM_CHSCCDR_IPU2_DI0_PRE_CLK_SEL_MASK (0x7 << 6) --#define MXC_CCM_CHSCCDR_IPU2_DI0_PRE_CLK_SEL_OFFSET 6 --#define MXC_CCM_CHSCCDR_IPU2_DI0_PODF_MASK (0x7 << 3) --#define MXC_CCM_CHSCCDR_IPU2_DI0_PODF_OFFSET 3 --#define MXC_CCM_CHSCCDR_IPU2_DI0_CLK_SEL_MASK 0x7 --#define MXC_CCM_CHSCCDR_IPU2_DI0_CLK_SEL_OFFSET 0 ++#define MXC_CCM_CSCDR2_IPU2_DI1_PRE_CLK_SEL_MASK (0x7 << MXC_CCM_CSCDR2_DI1_PRE_CLK_SEL_OFFSET) ++#define MXC_CCM_CSCDR2_IPU2_DI1_PRE_CLK_SEL_OFFSET 15 ++#define MXC_CCM_CSCDR2_IPU2_DI1_PODF_MASK (0x7 << MXC_CCM_CSCDR2_IPU2_DI1_PODF_OFFSET) ++#define MXC_CCM_CSCDR2_IPU2_DI1_PODF_OFFSET 12 ++#define MXC_CCM_CSCDR2_IPU2_DI1_CLK_SEL_MASK (0x7 << MXC_CCM_CSCDR2_IPU2_DI1_CLK_SEL_OFFSET) ++#define MXC_CCM_CSCDR2_IPU2_DI1_CLK_SEL_OFFSET 9 ++#define MXC_CCM_CSCDR2_IPU2_DI0_PRE_CLK_SEL_MASK (0x7 << MXC_CCM_CSCDR2_DI0_PRE_CLK_SEL_OFFSET) ++#define MXC_CCM_CSCDR2_IPU2_DI0_PRE_CLK_SEL_OFFSET 6 ++#define MXC_CCM_CSCDR2_IPU2_DI0_PODF_MASK (0x7 << MXC_CCM_CSCDR2_IPU2_DI0_PODF_OFFSET) ++#define MXC_CCM_CSCDR2_IPU2_DI0_PODF_OFFSET 3 ++#define MXC_CCM_CSCDR2_IPU2_DI0_CLK_SEL_MASK (0x7 << MXC_CCM_CSCDR2_IPU2_DI0_CLK_SEL_OFFSET) ++#define MXC_CCM_CSCDR2_IPU2_DI0_CLK_SEL_OFFSET 0 /* Define the bits in register CSCDR3 */ --#define MXC_CCM_CSCDR3_IPU2_HSP_PODF_MASK (0x7 << 16) ++#define MXC_CCM_CSCDR3_IPU2_HSP_PODF_MASK (0x7 << MXC_CCM_CSCDR3_IPU2_HSP_PODF_OFFSET) #define MXC_CCM_CSCDR3_IPU2_HSP_PODF_OFFSET 16 --#define MXC_CCM_CSCDR3_IPU2_HSP_CLK_SEL_MASK (0x3 << 14) ++#define MXC_CCM_CSCDR3_IPU2_HSP_CLK_SEL_MASK (0x3 << MXC_CCM_CSCDR3_IPU2_HSP_CLK_SEL_OFFSET) #define MXC_CCM_CSCDR3_IPU2_HSP_CLK_SEL_OFFSET 14 --#define MXC_CCM_CSCDR3_IPU1_HSP_PODF_MASK (0x7 << 11) ++#define MXC_CCM_CSCDR3_IPU1_HSP_PODF_MASK (0x7 << MXC_CCM_CSCDR3_IPU1_HSP_PODF_OFFSET) #define MXC_CCM_CSCDR3_IPU1_HSP_PODF_OFFSET 11 --#define MXC_CCM_CSCDR3_IPU1_HSP_CLK_SEL_MASK (0x3 << 9) ++#define MXC_CCM_CSCDR3_IPU1_HSP_CLK_SEL_MASK (0x3 << MXC_CCM_CSCDR3_IPU1_HSP_CLK_SEL_OFFSET) #define MXC_CCM_CSCDR3_IPU1_HSP_CLK_SEL_OFFSET 9 /* Define the bits in register CDHIPR */ @@@ -327,7 -331,7 +280,7 @@@ #define MXC_CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY (1 << 3) #define MXC_CCM_CDHIPR_MMDC_CH1_PODF_BUSY (1 << 2) #define MXC_CCM_CDHIPR_AHB_PODF_BUSY (1 << 1) --#define MXC_CCM_CDHIPR_AXI_PODF_BUSY 1 ++#define MXC_CCM_CDHIPR_AXI_PODF_BUSY (1 << 0) /* Define the bits in register CLPCR */ #define MXC_CCM_CLPCR_MASK_L2CC_IDLE (1 << 27) @@@ -341,16 -345,16 +294,16 @@@ #define MXC_CCM_CLPCR_WB_CORE_AT_LPM (1 << 17) #define MXC_CCM_CLPCR_WB_PER_AT_LPM (1 << 17) #define MXC_CCM_CLPCR_COSC_PWRDOWN (1 << 11) --#define MXC_CCM_CLPCR_STBY_COUNT_MASK (0x3 << 9) ++#define MXC_CCM_CLPCR_STBY_COUNT_MASK (0x3 << MXC_CCM_CLPCR_STBY_COUNT_OFFSET) #define MXC_CCM_CLPCR_STBY_COUNT_OFFSET 9 #define MXC_CCM_CLPCR_VSTBY (1 << 8) #define MXC_CCM_CLPCR_DIS_REF_OSC (1 << 7) #define MXC_CCM_CLPCR_SBYOS (1 << 6) #define MXC_CCM_CLPCR_ARM_CLK_DIS_ON_LPM (1 << 5) --#define MXC_CCM_CLPCR_LPSR_CLK_SEL_MASK (0x3 << 3) ++#define MXC_CCM_CLPCR_LPSR_CLK_SEL_MASK (0x3 << MXC_CCM_CLPCR_LPSR_CLK_SEL_OFFSET) #define MXC_CCM_CLPCR_LPSR_CLK_SEL_OFFSET 3 #define MXC_CCM_CLPCR_BYPASS_PMIC_VFUNC_READY (1 << 2) --#define MXC_CCM_CLPCR_LPM_MASK 0x3 ++#define MXC_CCM_CLPCR_LPM_MASK (0x3 << MXC_CCM_CLPCR_LPM_OFFSET) #define MXC_CCM_CLPCR_LPM_OFFSET 0 /* Define the bits in register CISR */ @@@ -362,7 -366,7 +315,7 @@@ #define MXC_CCM_CISR_PERIPH2_CLK_SEL_LOADED (1 << 19) #define MXC_CCM_CISR_AXI_PODF_LOADED (1 << 17) #define MXC_CCM_CISR_COSC_READY (1 << 6) --#define MXC_CCM_CISR_LRF_PLL 1 ++#define MXC_CCM_CISR_LRF_PLL (1 << 0) /* Define the bits in register CIMR */ #define MXC_CCM_CIMR_MASK_ARM_PODF_LOADED (1 << 26) @@@ -373,511 -377,511 +326,817 @@@ #define MXC_CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED (1 << 22) #define MXC_CCM_CIMR_MASK_AXI_PODF_LOADED (1 << 17) #define MXC_CCM_CIMR_MASK_COSC_READY (1 << 6) --#define MXC_CCM_CIMR_MASK_LRF_PLL 1 ++#define MXC_CCM_CIMR_MASK_LRF_PLL (1 << 0) /* Define the bits in register CCOSR */ #define MXC_CCM_CCOSR_CKO2_EN_OFFSET (1 << 24) --#define MXC_CCM_CCOSR_CKO2_DIV_MASK (0x7 << 21) ++#define MXC_CCM_CCOSR_CKO2_DIV_MASK (0x7 << MXC_CCM_CCOSR_CKO2_DIV_OFFSET) #define MXC_CCM_CCOSR_CKO2_DIV_OFFSET 21 #define MXC_CCM_CCOSR_CKO2_SEL_OFFSET 16 --#define MXC_CCM_CCOSR_CKO2_SEL_MASK (0x1F << 16) ++#define MXC_CCM_CCOSR_CKO2_SEL_MASK (0x1F << MXC_CCM_CCOSR_CKO2_SEL_OFFSET) #define MXC_CCM_CCOSR_CKOL_EN (0x1 << 7) --#define MXC_CCM_CCOSR_CKOL_DIV_MASK (0x7 << 4) ++#define MXC_CCM_CCOSR_CKOL_DIV_MASK (0x7 << MXC_CCM_CCOSR_CKOL_DIV_OFFSET) #define MXC_CCM_CCOSR_CKOL_DIV_OFFSET 4 --#define MXC_CCM_CCOSR_CKOL_SEL_MASK 0xF ++#define MXC_CCM_CCOSR_CKOL_SEL_MASK (0xF << MXC_CCM_CCOSR_CKOL_SEL_OFFSET) #define MXC_CCM_CCOSR_CKOL_SEL_OFFSET 0 /* Define the bits in registers CGPR */ #define MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE (1 << 4) #define MXC_CCM_CGPR_MMDC_EXT_CLK_DIS (1 << 2) --#define MXC_CCM_CGPR_PMIC_DELAY_SCALER 1 ++#define MXC_CCM_CGPR_PMIC_DELAY_SCALER (1 << 0) /* Define the bits in registers CCGRx */ #define MXC_CCM_CCGR_CG_MASK 3 - #define MXC_CCM_CCGR0_CG15_OFFSET 30 - #define MXC_CCM_CCGR0_CG15_MASK (0x3 << 30) -#define MXC_CCM_CCGR0_AIPS_TZ1_OFFSET 0 -#define MXC_CCM_CCGR0_AIPS_TZ1_MASK (3< ++ * on behalf of DENX Software Engineering GmbH ++ * ++ * Based on code from LTIB: ++ * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ * ++ */ ++ ++#ifndef __DMA_H__ ++#define __DMA_H__ ++ ++#include ++ ++#ifndef CONFIG_ARCH_DMA_PIO_WORDS ++#define DMA_PIO_WORDS 15 ++#else ++#define DMA_PIO_WORDS CONFIG_ARCH_DMA_PIO_WORDS ++#endif ++ ++#define MXS_DMA_ALIGNMENT 32 ++ ++/* ++ * MXS DMA channels ++ */ ++enum { ++ MXS_DMA_CHANNEL_AHB_APBH_GPMI0, ++ MXS_DMA_CHANNEL_AHB_APBH_GPMI1, ++ MXS_DMA_CHANNEL_AHB_APBH_GPMI2, ++ MXS_DMA_CHANNEL_AHB_APBH_GPMI3, ++ MXS_DMA_CHANNEL_AHB_APBH_GPMI4, ++ MXS_DMA_CHANNEL_AHB_APBH_GPMI5, ++ MXS_DMA_CHANNEL_AHB_APBH_GPMI6, ++ MXS_DMA_CHANNEL_AHB_APBH_GPMI7, ++ MXS_DMA_CHANNEL_AHB_APBH_SSP, ++ MXS_MAX_DMA_CHANNELS ++}; ++ ++/* ++ * MXS DMA hardware command. ++ * ++ * This structure describes the in-memory layout of an entire DMA command, ++ * including space for the maximum number of PIO accesses. See the appropriate ++ * reference manual for a detailed description of what these fields mean to the ++ * DMA hardware. ++ */ ++#define MXS_DMA_DESC_COMMAND_MASK 0x3 ++#define MXS_DMA_DESC_COMMAND_OFFSET 0 ++#define MXS_DMA_DESC_COMMAND_NO_DMAXFER 0x0 ++#define MXS_DMA_DESC_COMMAND_DMA_WRITE 0x1 ++#define MXS_DMA_DESC_COMMAND_DMA_READ 0x2 ++#define MXS_DMA_DESC_COMMAND_DMA_SENSE 0x3 ++#define MXS_DMA_DESC_CHAIN (1 << 2) ++#define MXS_DMA_DESC_IRQ (1 << 3) ++#define MXS_DMA_DESC_NAND_LOCK (1 << 4) ++#define MXS_DMA_DESC_NAND_WAIT_4_READY (1 << 5) ++#define MXS_DMA_DESC_DEC_SEM (1 << 6) ++#define MXS_DMA_DESC_WAIT4END (1 << 7) ++#define MXS_DMA_DESC_HALT_ON_TERMINATE (1 << 8) ++#define MXS_DMA_DESC_PIO_WORDS_MASK (0xf << MXS_DMA_DESC_PIO_WORDS_OFFSET) ++#define MXS_DMA_DESC_PIO_WORDS_OFFSET 12 ++#define MXS_DMA_DESC_BYTES_MASK (0xffff << MXS_DMA_DESC_BYTES_OFFSET) ++#define MXS_DMA_DESC_BYTES_OFFSET 16 ++ ++struct mxs_dma_cmd { ++ unsigned long next; ++ unsigned long data; ++ union { ++ dma_addr_t address; ++ unsigned long alternate; ++ }; ++ unsigned long pio_words[DMA_PIO_WORDS]; ++}; ++ ++/* ++ * MXS DMA command descriptor. ++ * ++ * This structure incorporates an MXS DMA hardware command structure, along ++ * with metadata. ++ */ ++#define MXS_DMA_DESC_FIRST (1 << 0) ++#define MXS_DMA_DESC_LAST (1 << 1) ++#define MXS_DMA_DESC_READY (1 << 31) ++ ++struct mxs_dma_desc { ++ struct mxs_dma_cmd cmd; ++ unsigned int flags; ++ dma_addr_t address; ++ void *buffer; ++ struct list_head node; ++}; ++ ++/** ++ * MXS DMA channel ++ * ++ * This structure represents a single DMA channel. The MXS platform code ++ * maintains an array of these structures to represent every DMA channel in the ++ * system (see mxs_dma_channels). ++ */ ++#define MXS_DMA_FLAGS_BUSY (1 << 0) ++#define MXS_DMA_FLAGS_ALLOCATED (1 << 16) ++#define MXS_DMA_FLAGS_VALID (1 << 31) ++ ++struct mxs_dma_chan { ++ const char *name; ++ unsigned long dev; ++ struct mxs_dma_device *dma; ++ unsigned int flags; ++ unsigned int active_num; ++ unsigned int pending_num; ++ struct list_head active; ++ struct list_head done; ++}; ++ ++struct mxs_dma_desc *mxs_dma_desc_alloc(void); ++void mxs_dma_desc_free(struct mxs_dma_desc *); ++int mxs_dma_desc_append(int channel, struct mxs_dma_desc *pdesc); ++ ++int mxs_dma_go(int chan); ++void mxs_dma_init(void); ++int mxs_dma_init_channel(int chan); ++int mxs_dma_release(int chan); ++ ++#endif /* __DMA_H__ */ diff --cc arch/arm/include/asm/arch-mx6/imx-regs.h index e165810ddc,3eb0081ca8..7b39aac1b0 --- a/arch/arm/include/asm/arch-mx6/imx-regs.h +++ b/arch/arm/include/asm/arch-mx6/imx-regs.h @@@ -19,162 -19,165 +19,188 @@@ #ifndef __ASM_ARCH_MX6_IMX_REGS_H__ #define __ASM_ARCH_MX6_IMX_REGS_H__ + #define ARCH_MXC + #define CONFIG_SYS_CACHELINE_SIZE 32 --#define ROMCP_ARB_BASE_ADDR 0x00000000 --#define ROMCP_ARB_END_ADDR 0x000FFFFF --#define CAAM_ARB_BASE_ADDR 0x00100000 --#define CAAM_ARB_END_ADDR 0x00103FFF --#define APBH_DMA_ARB_BASE_ADDR 0x00110000 --#define APBH_DMA_ARB_END_ADDR 0x00117FFF --#define HDMI_ARB_BASE_ADDR 0x00120000 --#define HDMI_ARB_END_ADDR 0x00128FFF --#define GPU_3D_ARB_BASE_ADDR 0x00130000 --#define GPU_3D_ARB_END_ADDR 0x00133FFF --#define GPU_2D_ARB_BASE_ADDR 0x00134000 --#define GPU_2D_ARB_END_ADDR 0x00137FFF --#define DTCP_ARB_BASE_ADDR 0x00138000 --#define DTCP_ARB_END_ADDR 0x0013BFFF ++#define ROMCP_ARB_BASE_ADDR 0x00000000 ++#define ROMCP_ARB_END_ADDR 0x000FFFFF ++#define CAAM_ARB_BASE_ADDR 0x00100000 ++#define CAAM_ARB_END_ADDR 0x00103FFF ++#define APBH_DMA_ARB_BASE_ADDR 0x00110000 ++#define APBH_DMA_ARB_END_ADDR 0x00117FFF ++#define HDMI_ARB_BASE_ADDR 0x00120000 ++#define HDMI_ARB_END_ADDR 0x00128FFF ++#define GPU_3D_ARB_BASE_ADDR 0x00130000 ++#define GPU_3D_ARB_END_ADDR 0x00133FFF ++#define GPU_2D_ARB_BASE_ADDR 0x00134000 ++#define GPU_2D_ARB_END_ADDR 0x00137FFF ++#define DTCP_ARB_BASE_ADDR 0x00138000 ++#define DTCP_ARB_END_ADDR 0x0013BFFF /* GPV - PL301 configuration ports */ #define GPV2_BASE_ADDR 0x00200000 #define GPV3_BASE_ADDR 0x00300000 #define GPV4_BASE_ADDR 0x00800000 #define IRAM_BASE_ADDR 0x00900000 --#define SCU_BASE_ADDR 0x00A00000 --#define IC_INTERFACES_BASE_ADDR 0x00A00100 --#define GLOBAL_TIMER_BASE_ADDR 0x00A00200 --#define PRIVATE_TIMERS_WD_BASE_ADDR 0x00A00600 --#define IC_DISTRIBUTOR_BASE_ADDR 0x00A01000 --#define GPV0_BASE_ADDR 0x00B00000 --#define GPV1_BASE_ADDR 0x00C00000 --#define PCIE_ARB_BASE_ADDR 0x01000000 --#define PCIE_ARB_END_ADDR 0x01FFFFFF -- --#define AIPS1_ARB_BASE_ADDR 0x02000000 --#define AIPS1_ARB_END_ADDR 0x020FFFFF --#define AIPS2_ARB_BASE_ADDR 0x02100000 --#define AIPS2_ARB_END_ADDR 0x021FFFFF --#define SATA_ARB_BASE_ADDR 0x02200000 --#define SATA_ARB_END_ADDR 0x02203FFF --#define OPENVG_ARB_BASE_ADDR 0x02204000 --#define OPENVG_ARB_END_ADDR 0x02207FFF --#define HSI_ARB_BASE_ADDR 0x02208000 --#define HSI_ARB_END_ADDR 0x0220BFFF --#define IPU1_ARB_BASE_ADDR 0x02400000 --#define IPU1_ARB_END_ADDR 0x027FFFFF --#define IPU2_ARB_BASE_ADDR 0x02800000 --#define IPU2_ARB_END_ADDR 0x02BFFFFF --#define WEIM_ARB_BASE_ADDR 0x08000000 --#define WEIM_ARB_END_ADDR 0x0FFFFFFF -- --#define MMDC0_ARB_BASE_ADDR 0x10000000 --#define MMDC0_ARB_END_ADDR 0x7FFFFFFF --#define MMDC1_ARB_BASE_ADDR 0x80000000 --#define MMDC1_ARB_END_ADDR 0xFFFFFFFF - -#define IPU_SOC_BASE_ADDR IPU1_ARB_BASE_ADDR -#define IPU_SOC_OFFSET 0x00200000 ++#define SCU_BASE_ADDR 0x00A00000 ++#define IC_INTERFACES_BASE_ADDR 0x00A00100 ++#define GLOBAL_TIMER_BASE_ADDR 0x00A00200 ++#define PRIVATE_TIMERS_WD_BASE_ADDR 0x00A00600 ++#define IC_DISTRIBUTOR_BASE_ADDR 0x00A01000 ++#define GPV0_BASE_ADDR 0x00B00000 ++#define GPV1_BASE_ADDR 0x00C00000 ++#define PCIE_ARB_BASE_ADDR 0x01000000 ++#define PCIE_ARB_END_ADDR 0x01FFFFFF ++ ++#define AIPS1_ARB_BASE_ADDR 0x02000000 ++#define AIPS1_ARB_END_ADDR 0x020FFFFF ++#define AIPS2_ARB_BASE_ADDR 0x02100000 ++#define AIPS2_ARB_END_ADDR 0x021FFFFF ++#define SATA_ARB_BASE_ADDR 0x02200000 ++#define SATA_ARB_END_ADDR 0x02203FFF ++#define OPENVG_ARB_BASE_ADDR 0x02204000 ++#define OPENVG_ARB_END_ADDR 0x02207FFF ++#define HSI_ARB_BASE_ADDR 0x02208000 ++#define HSI_ARB_END_ADDR 0x0220BFFF ++#define IPU1_ARB_BASE_ADDR 0x02400000 ++#define IPU_CTRL_BASE_ADDR IPU1_ARB_BASE_ADDR ++#define IPU1_ARB_END_ADDR 0x027FFFFF ++#define IPU2_ARB_BASE_ADDR 0x02800000 ++#define IPU2_ARB_END_ADDR 0x02BFFFFF ++#define WEIM_ARB_BASE_ADDR 0x08000000 ++#define WEIM_ARB_END_ADDR 0x0FFFFFFF ++ ++#define MMDC0_ARB_BASE_ADDR 0x10000000 ++#define MMDC0_ARB_END_ADDR 0x7FFFFFFF ++#define MMDC1_ARB_BASE_ADDR 0x80000000 ++#define MMDC1_ARB_END_ADDR 0xFFFFFFFF /* Defines for Blocks connected via AIPS (SkyBlue) */ --#define ATZ1_BASE_ADDR AIPS1_ARB_BASE_ADDR --#define ATZ2_BASE_ADDR AIPS2_ARB_BASE_ADDR --#define AIPS1_BASE_ADDR AIPS1_ON_BASE_ADDR --#define AIPS2_BASE_ADDR AIPS2_ON_BASE_ADDR -- --#define SPDIF_BASE_ADDR (ATZ1_BASE_ADDR + 0x04000) --#define ECSPI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x08000) --#define ECSPI2_BASE_ADDR (ATZ1_BASE_ADDR + 0x0C000) --#define ECSPI3_BASE_ADDR (ATZ1_BASE_ADDR + 0x10000) --#define ECSPI4_BASE_ADDR (ATZ1_BASE_ADDR + 0x14000) --#define ECSPI5_BASE_ADDR (ATZ1_BASE_ADDR + 0x18000) --#define UART1_BASE (ATZ1_BASE_ADDR + 0x20000) --#define ESAI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x24000) --#define SSI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x28000) --#define SSI2_BASE_ADDR (ATZ1_BASE_ADDR + 0x2C000) --#define SSI3_BASE_ADDR (ATZ1_BASE_ADDR + 0x30000) --#define ASRC_BASE_ADDR (ATZ1_BASE_ADDR + 0x34000) --#define SPBA_BASE_ADDR (ATZ1_BASE_ADDR + 0x3C000) --#define VPU_BASE_ADDR (ATZ1_BASE_ADDR + 0x40000) --#define AIPS1_ON_BASE_ADDR (ATZ1_BASE_ADDR + 0x7C000) -- --#define AIPS1_OFF_BASE_ADDR (ATZ1_BASE_ADDR + 0x80000) --#define PWM1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x0000) --#define PWM2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x4000) --#define PWM3_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x8000) --#define PWM4_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0xC000) --#define CAN1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x10000) --#define CAN2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x14000) --#define GPT1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x18000) --#define GPIO1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x1C000) --#define GPIO2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x20000) --#define GPIO3_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x24000) --#define GPIO4_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x28000) --#define GPIO5_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x2C000) --#define GPIO6_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x30000) --#define GPIO7_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x34000) --#define KPP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x38000) --#define WDOG1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x3C000) --#define WDOG2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x40000) --#define ANATOP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x48000) --#define USB_PHY0_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x49000) --#define USB_PHY1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x4a000) --#define CCM_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x44000) --#define SNVS_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x4C000) --#define EPIT1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x50000) --#define EPIT2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x54000) --#define SRC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x58000) --#define GPC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x5C000) --#define IOMUXC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x60000) --#define DCIC1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x64000) --#define DCIC2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000) ++#define ATZ1_BASE_ADDR AIPS1_ARB_BASE_ADDR ++#define ATZ2_BASE_ADDR AIPS2_ARB_BASE_ADDR ++#define AIPS1_BASE_ADDR AIPS1_ON_BASE_ADDR ++#define AIPS2_BASE_ADDR AIPS2_ON_BASE_ADDR ++ ++#define SPDIF_BASE_ADDR (ATZ1_BASE_ADDR + 0x04000) ++#define ECSPI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x08000) ++#define ECSPI2_BASE_ADDR (ATZ1_BASE_ADDR + 0x0C000) ++#define ECSPI3_BASE_ADDR (ATZ1_BASE_ADDR + 0x10000) ++#define ECSPI4_BASE_ADDR (ATZ1_BASE_ADDR + 0x14000) ++#define ECSPI5_BASE_ADDR (ATZ1_BASE_ADDR + 0x18000) ++#define UART1_BASE (ATZ1_BASE_ADDR + 0x20000) ++#define ESAI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x24000) ++#define SSI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x28000) ++#define SSI2_BASE_ADDR (ATZ1_BASE_ADDR + 0x2C000) ++#define SSI3_BASE_ADDR (ATZ1_BASE_ADDR + 0x30000) ++#define ASRC_BASE_ADDR (ATZ1_BASE_ADDR + 0x34000) ++#define SPBA_BASE_ADDR (ATZ1_BASE_ADDR + 0x3C000) ++#define VPU_BASE_ADDR (ATZ1_BASE_ADDR + 0x40000) ++#define AIPS1_ON_BASE_ADDR (ATZ1_BASE_ADDR + 0x7C000) ++ ++#define AIPS1_OFF_BASE_ADDR (ATZ1_BASE_ADDR + 0x80000) ++#define PWM1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x0000) ++#define PWM2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x4000) ++#define PWM3_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x8000) ++#define PWM4_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0xC000) ++#define CAN1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x10000) ++#define CAN2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x14000) ++#define GPT1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x18000) ++#define GPIO1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x1C000) ++#define GPIO2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x20000) ++#define GPIO3_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x24000) ++#define GPIO4_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x28000) ++#define GPIO5_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x2C000) ++#define GPIO6_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x30000) ++#define GPIO7_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x34000) ++#define KPP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x38000) ++#define WDOG1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x3C000) ++#define WDOG2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x40000) ++#define CCM_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x44000) ++#define ANATOP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x48000) ++#define USB_PHY0_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x49000) ++#define USB_PHY1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x4a000) ++#define SNVS_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x4C000) ++#define EPIT1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x50000) ++#define EPIT2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x54000) ++#define SRC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x58000) ++#define GPC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x5C000) ++#define IOMUXC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x60000) ++#define DCIC1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x64000) ++#define DCIC2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000) #define DMA_REQ_PORT_HOST_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000) --#define AIPS2_ON_BASE_ADDR (ATZ2_BASE_ADDR + 0x7C000) --#define AIPS2_OFF_BASE_ADDR (ATZ2_BASE_ADDR + 0x80000) --#define CAAM_BASE_ADDR (ATZ2_BASE_ADDR) ++#define AIPS2_ON_BASE_ADDR (ATZ2_BASE_ADDR + 0x7C000) ++#define AIPS2_OFF_BASE_ADDR (ATZ2_BASE_ADDR + 0x80000) ++#define CAAM_BASE_ADDR (ATZ2_BASE_ADDR) #define ARM_BASE_ADDR (ATZ2_BASE_ADDR + 0x40000) --#define USBOH3_PL301_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x0000) --#define USBOH3_USB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4000) --#define ENET_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x8000) --#define MLB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0xC000) --#define USDHC1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x10000) --#define USDHC2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x14000) --#define USDHC3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x18000) --#define USDHC4_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x1C000) --#define I2C1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x20000) --#define I2C2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x24000) --#define I2C3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x28000) --#define ROMCP_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x2C000) --#define MMDC_P0_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x30000) --#define MMDC_P1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x34000) --#define WEIM_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x38000) --#define OCOTP_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x3C000) --#define CSU_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x40000) ++#define USBOH3_PL301_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x0000) ++#define USBOH3_USB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4000) ++#define ENET_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x8000) ++#define MLB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0xC000) ++#define USDHC1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x10000) ++#define USDHC2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x14000) ++#define USDHC3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x18000) ++#define USDHC4_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x1C000) ++#define I2C1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x20000) ++#define I2C2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x24000) ++#define I2C3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x28000) ++#define ROMCP_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x2C000) ++#define MMDC_P0_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x30000) ++#define MMDC_P1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x34000) ++#define WEIM_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x38000) ++#define OCOTP_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x3C000) ++#define CSU_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x40000) #define IP2APB_PERFMON1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x44000) #define IP2APB_PERFMON2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x48000) #define IP2APB_PERFMON3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4C000) --#define IP2APB_TZASC1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x50000) --#define IP2APB_TZASC2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x54000) --#define AUDMUX_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x58000) --#define MIPI_CSI2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x5C000) --#define MIPI_DSI_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x60000) --#define VDOA_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x64000) --#define UART2_BASE (AIPS2_OFF_BASE_ADDR + 0x68000) --#define UART3_BASE (AIPS2_OFF_BASE_ADDR + 0x6C000) --#define UART4_BASE (AIPS2_OFF_BASE_ADDR + 0x70000) --#define UART5_BASE (AIPS2_OFF_BASE_ADDR + 0x74000) ++#define IP2APB_TZASC1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x50000) ++#define IP2APB_TZASC2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x54000) ++#define AUDMUX_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x58000) ++#define MIPI_CSI2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x5C000) ++#define MIPI_DSI_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x60000) ++#define VDOA_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x64000) ++#define UART2_BASE (AIPS2_OFF_BASE_ADDR + 0x68000) ++#define UART3_BASE (AIPS2_OFF_BASE_ADDR + 0x6C000) ++#define UART4_BASE (AIPS2_OFF_BASE_ADDR + 0x70000) ++#define UART5_BASE (AIPS2_OFF_BASE_ADDR + 0x74000) #define IP2APB_USBPHY1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x78000) #define IP2APB_USBPHY2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x7C000) --#define CHIP_REV_1_0 0x10 --#define IRAM_SIZE 0x00040000 --#define IMX_IIM_BASE OCOTP_BASE_ADDR ++#define CHIP_REV_1_0 0x10 ++#define IRAM_SIZE 0x00040000 ++#define IMX_IIM_BASE OCOTP_BASE_ADDR #define FEC_QUIRK_ENET_MAC - #define GPIO_NUMBER(port, index) ((((port)-1)*32)+((index)&31)) - #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) #include --extern void imx_get_mac_from_fuse(int dev_id, unsigned char *mac); ++#define __reg_32(name) \ ++ uint32_t name; \ ++ uint32_t reserved_##name[3] ++ ++#define __mx6_reg_32(name) \ ++ uint32_t name; \ ++ uint32_t name##_set; \ ++ uint32_t name##_clr; \ ++ uint32_t name##_tog ++ ++struct register_32 { ++ __reg_32(reg); ++}; ++ ++struct mx6_register_32 { ++ __mx6_reg_32(reg); ++}; ++ ++#define reg_32(name) \ ++ struct { __reg_32(name); }; \ ++ ++#define mx6_reg_32(name) \ ++ union { \ ++ struct { __mx6_reg_32(name); }; \ ++ struct mx6_register_32 name##_reg; \ ++ } /* System Reset Controller (SRC) */ struct src { @@@ -184,19 -187,146 +210,140 @@@ u32 reserved1[2]; u32 sisr; u32 simr; -- u32 sbmr2; -- u32 gpr1; -- u32 gpr2; -- u32 gpr3; -- u32 gpr4; -- u32 gpr5; -- u32 gpr6; -- u32 gpr7; -- u32 gpr8; -- u32 gpr9; -- u32 gpr10; -}; - -/* OCOTP Registers */ -struct ocotp_regs { - u32 reserved[0x198]; - u32 gp1; /* 0x660 */ ++ u32 sbmr2; ++ u32 gpr1; ++ u32 gpr2; ++ u32 gpr3; ++ u32 gpr4; ++ u32 gpr5; ++ u32 gpr6; ++ u32 gpr7; ++ u32 gpr8; ++ u32 gpr9; ++ u32 gpr10; + }; + + /* GPR3 bitfields */ + #define IOMUXC_GPR3_GPU_DBG_OFFSET 29 + #define IOMUXC_GPR3_GPU_DBG_MASK (3< ++ ++/* ++ * Use to set PAD control ++ */ ++#define MX6_PAD_CTL_HYS (1 << 16) ++ ++#define MX6_PAD_CTL_PUS_100K_DOWN (MX6_PAD_CTL_PULL | (0 << 14)) ++#define MX6_PAD_CTL_PUS_47K_UP (MX6_PAD_CTL_PULL | (1 << 14)) ++#define MX6_PAD_CTL_PUS_100K_UP (MX6_PAD_CTL_PULL | (2 << 14)) ++#define MX6_PAD_CTL_PUS_22K_UP (MX6_PAD_CTL_PULL | (3 << 14)) ++ ++#define MX6_PAD_CTL_PULL (MX6_PAD_CTL_PKE | MX6_PAD_CTL_PUE) ++#define MX6_PAD_CTL_PUE (1 << 13) ++#define MX6_PAD_CTL_PKE (1 << 12) ++#define MX6_PAD_CTL_ODE (1 << 11) ++ ++#define MX6_PAD_CTL_SPEED_LOW (1 << 6) ++#define MX6_PAD_CTL_SPEED_MED (2 << 6) ++#define MX6_PAD_CTL_SPEED_HIGH (3 << 6) ++ ++#define MX6_PAD_CTL_DSE_DISABLE (0 << 3) ++#define MX6_PAD_CTL_DSE_240ohm (1 << 3) ++#define MX6_PAD_CTL_DSE_120ohm (2 << 3) ++#define MX6_PAD_CTL_DSE_80ohm (3 << 3) ++#define MX6_PAD_CTL_DSE_60ohm (4 << 3) ++#define MX6_PAD_CTL_DSE_48ohm (5 << 3) ++#define MX6_PAD_CTL_DSE_40ohm (6 << 3) ++#define MX6_PAD_CTL_DSE_34ohm (7 << 3) ++ ++#define MX6_PAD_CTL_SRE_FAST (1 << 0) ++#define MX6_PAD_CTL_SRE_SLOW (0 << 0) ++ ++#define MX6Q_UART_PAD_CTRL (MX6_PAD_CTL_PUS_100K_UP | MX6_PAD_CTL_SPEED_MED | \ ++ MX6_PAD_CTL_DSE_40ohm | MX6_PAD_CTL_SRE_FAST | MX6_PAD_CTL_HYS) ++ ++#define MX6Q_ECSPI_PAD_CTRL (MX6_PAD_CTL_SRE_FAST | MX6_PAD_CTL_PUS_100K_DOWN | MX6_PAD_CTL_SPEED_MED | \ ++ MX6_PAD_CTL_DSE_40ohm | MX6_PAD_CTL_HYS) ++ ++#define MX6Q_USDHC_PAD_CTRL (MX6_PAD_CTL_PUS_47K_UP | MX6_PAD_CTL_SPEED_MED | \ ++ MX6_PAD_CTL_DSE_40ohm | MX6_PAD_CTL_SRE_FAST | MX6_PAD_CTL_HYS) ++ ++#define MX6Q_ENET_PAD_CTRL (MX6_PAD_CTL_PUS_100K_UP | MX6_PAD_CTL_SPEED_MED | \ ++ MX6_PAD_CTL_DSE_40ohm | MX6_PAD_CTL_HYS) ++ ++#define MX6Q_I2C_PAD_CTRL (MX6_PAD_CTL_PUS_100K_UP | MX6_PAD_CTL_SPEED_MED | \ ++ MX6_PAD_CTL_DSE_40ohm | MX6_PAD_CTL_HYS | \ ++ MX6_PAD_CTL_ODE | MX6_PAD_CTL_SRE_FAST) ++ ++#define MX6Q_PWM_PAD_CTRL (MX6_PAD_CTL_PUS_100K_UP | MX6_PAD_CTL_SPEED_MED | \ ++ MX6_PAD_CTL_DSE_40ohm | MX6_PAD_CTL_HYS | \ ++ MX6_PAD_CTL_SRE_FAST) ++ ++#define MX6Q_HIGH_DRV MX6_PAD_CTL_DSE_120ohm ++ ++#define _MX6Q_PAD_SD2_DAT1__USDHC2_DAT1 \ ++ IOMUX_PAD(0x0360, 0x004C, 0, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD2_DAT1__ECSPI5_SS0 \ ++ IOMUX_PAD(0x0360, 0x004C, 1, 0x0834, 0, 0) ++#define _MX6Q_PAD_SD2_DAT1__WEIM_WEIM_CS_2 \ ++ IOMUX_PAD(0x0360, 0x004C, 2, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD2_DAT1__AUDMUX_AUD4_TXFS \ ++ IOMUX_PAD(0x0360, 0x004C, 3, 0x07C8, 0, 0) ++#define _MX6Q_PAD_SD2_DAT1__KPP_COL_7 \ ++ IOMUX_PAD(0x0360, 0x004C, 4, 0x08F0, 0, 0) ++#define _MX6Q_PAD_SD2_DAT1__GPIO_1_14 \ ++ IOMUX_PAD(0x0360, 0x004C, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD2_DAT1__CCM_WAIT \ ++ IOMUX_PAD(0x0360, 0x004C, 6, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD2_DAT1__ANATOP_ANATOP_TESTO_0 \ ++ IOMUX_PAD(0x0360, 0x004C, 7, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_SD2_DAT2__USDHC2_DAT2 \ ++ IOMUX_PAD(0x0364, 0x0050, 0, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD2_DAT2__ECSPI5_SS1 \ ++ IOMUX_PAD(0x0364, 0x0050, 1, 0x0838, 0, 0) ++#define _MX6Q_PAD_SD2_DAT2__WEIM_WEIM_CS_3 \ ++ IOMUX_PAD(0x0364, 0x0050, 2, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD2_DAT2__AUDMUX_AUD4_TXD \ ++ IOMUX_PAD(0x0364, 0x0050, 3, 0x07B8, 0, 0) ++#define _MX6Q_PAD_SD2_DAT2__KPP_ROW_6 \ ++ IOMUX_PAD(0x0364, 0x0050, 4, 0x08F8, 0, 0) ++#define _MX6Q_PAD_SD2_DAT2__GPIO_1_13 \ ++ IOMUX_PAD(0x0364, 0x0050, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD2_DAT2__CCM_STOP \ ++ IOMUX_PAD(0x0364, 0x0050, 6, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD2_DAT2__ANATOP_ANATOP_TESTO_1 \ ++ IOMUX_PAD(0x0364, 0x0050, 7, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_SD2_DAT0__USDHC2_DAT0 \ ++ IOMUX_PAD(0x0368, 0x0054, 0, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD2_DAT0__ECSPI5_MISO \ ++ IOMUX_PAD(0x0368, 0x0054, 1, 0x082C, 0, 0) ++#define _MX6Q_PAD_SD2_DAT0__AUDMUX_AUD4_RXD \ ++ IOMUX_PAD(0x0368, 0x0054, 3, 0x07B4, 0, 0) ++#define _MX6Q_PAD_SD2_DAT0__KPP_ROW_7 \ ++ IOMUX_PAD(0x0368, 0x0054, 4, 0x08FC, 0, 0) ++#define _MX6Q_PAD_SD2_DAT0__GPIO_1_15 \ ++ IOMUX_PAD(0x0368, 0x0054, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD2_DAT0__DCIC2_DCIC_OUT \ ++ IOMUX_PAD(0x0368, 0x0054, 6, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD2_DAT0__ANATOP_ANATOP_TESTO_2 \ ++ IOMUX_PAD(0x0368, 0x0054, 7, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_RGMII_TXC__USBOH3_H2_DATA \ ++ IOMUX_PAD(0x036C, 0x0058, 0, 0x0000, 0, 0) ++#define _MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC \ ++ IOMUX_PAD(0x036C, 0x0058, 1, 0x0000, 0, 0) ++#define _MX6Q_PAD_RGMII_TXC__SPDIF_SPDIF_EXTCLK \ ++ IOMUX_PAD(0x036C, 0x0058, 2, 0x0918, 0, 0) ++#define _MX6Q_PAD_RGMII_TXC__GPIO_6_19 \ ++ IOMUX_PAD(0x036C, 0x0058, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_RGMII_TXC__MIPI_CORE_DPHY_TEST_IN_0 \ ++ IOMUX_PAD(0x036C, 0x0058, 6, 0x0000, 0, 0) ++#define _MX6Q_PAD_RGMII_TXC__ANATOP_ANATOP_24M_OUT \ ++ IOMUX_PAD(0x036C, 0x0058, 7, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_RGMII_TD0__MIPI_HSI_CTRL_TX_READY \ ++ IOMUX_PAD(0x0370, 0x005C, 0, 0x0000, 0, 0) ++#define _MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 \ ++ IOMUX_PAD(0x0370, 0x005C, 1, 0x0000, 0, 0) ++#define _MX6Q_PAD_RGMII_TD0__GPIO_6_20 \ ++ IOMUX_PAD(0x0370, 0x005C, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_RGMII_TD0__MIPI_CORE_DPHY_TEST_IN_1 \ ++ IOMUX_PAD(0x0370, 0x005C, 6, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_RGMII_TD1__MIPI_HSI_CTRL_RX_FLAG \ ++ IOMUX_PAD(0x0374, 0x0060, 0, 0x0000, 0, 0) ++#define _MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 \ ++ IOMUX_PAD(0x0374, 0x0060, 1, 0x0000, 0, 0) ++#define _MX6Q_PAD_RGMII_TD1__GPIO_6_21 \ ++ IOMUX_PAD(0x0374, 0x0060, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_RGMII_TD1__MIPI_CORE_DPHY_TEST_IN_2 \ ++ IOMUX_PAD(0x0374, 0x0060, 6, 0x0000, 0, 0) ++#define _MX6Q_PAD_RGMII_TD1__CCM_PLL3_BYP \ ++ IOMUX_PAD(0x0374, 0x0060, 7, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_RGMII_TD2__MIPI_HSI_CTRL_RX_DATA \ ++ IOMUX_PAD(0x0378, 0x0064, 0, 0x0000, 0, 0) ++#define _MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 \ ++ IOMUX_PAD(0x0378, 0x0064, 1, 0x0000, 0, 0) ++#define _MX6Q_PAD_RGMII_TD2__GPIO_6_22 \ ++ IOMUX_PAD(0x0378, 0x0064, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_RGMII_TD2__MIPI_CORE_DPHY_TEST_IN_3 \ ++ IOMUX_PAD(0x0378, 0x0064, 6, 0x0000, 0, 0) ++#define _MX6Q_PAD_RGMII_TD2__CCM_PLL2_BYP \ ++ IOMUX_PAD(0x0378, 0x0064, 7, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_RGMII_TD3__MIPI_HSI_CTRL_RX_WAKE \ ++ IOMUX_PAD(0x037C, 0x0068, 0, 0x0000, 0, 0) ++#define _MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 \ ++ IOMUX_PAD(0x037C, 0x0068, 1, 0x0000, 0, 0) ++#define _MX6Q_PAD_RGMII_TD3__GPIO_6_23 \ ++ IOMUX_PAD(0x037C, 0x0068, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_RGMII_TD3__MIPI_CORE_DPHY_TEST_IN_4 \ ++ IOMUX_PAD(0x037C, 0x0068, 6, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_RGMII_RX_CTL__USBOH3_H3_DATA \ ++ IOMUX_PAD(0x0380, 0x006C, 0, 0x0000, 0, 0) ++#define _MX6Q_PAD_RGMII_RX_CTL__ENET_RGMII_RX_CTL \ ++ IOMUX_PAD(0x0380, 0x006C, 1, 0x0858, 0, 0) ++#define _MX6Q_PAD_RGMII_RX_CTL__GPIO_6_24 \ ++ IOMUX_PAD(0x0380, 0x006C, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_RGMII_RX_CTL__MIPI_CORE_DPHY_TEST_IN_5 \ ++ IOMUX_PAD(0x0380, 0x006C, 6, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_RGMII_RD0__MIPI_HSI_CTRL_RX_READY \ ++ IOMUX_PAD(0x0384, 0x0070, 0, 0x0000, 0, 0) ++#define _MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 \ ++ IOMUX_PAD(0x0384, 0x0070, 1, 0x0848, 0, 0) ++#define _MX6Q_PAD_RGMII_RD0__GPIO_6_25 \ ++ IOMUX_PAD(0x0384, 0x0070, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_RGMII_RD0__MIPI_CORE_DPHY_TEST_IN_6 \ ++ IOMUX_PAD(0x0384, 0x0070, 6, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_RGMII_TX_CTL__USBOH3_H2_STROBE \ ++ IOMUX_PAD(0x0388, 0x0074, 0, 0x0000, 0, 0) ++#define _MX6Q_PAD_RGMII_TX_CTL__ENET_RGMII_TX_CTL \ ++ IOMUX_PAD(0x0388, 0x0074, 1, 0x0000, 0, 0) ++#define _MX6Q_PAD_RGMII_TX_CTL__GPIO_6_26 \ ++ IOMUX_PAD(0x0388, 0x0074, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_RGMII_TX_CTL__MIPI_CORE_DPHY_TEST_IN_7 \ ++ IOMUX_PAD(0x0388, 0x0074, 6, 0x0000, 0, 0) ++#define _MX6Q_PAD_RGMII_TX_CTL__ENET_ANATOP_ETHERNET_REF_OUT \ ++ IOMUX_PAD(0x0388, 0x0074, 0x17, 0x083C, 0, 0) ++ ++#define _MX6Q_PAD_RGMII_RD1__MIPI_HSI_CTRL_TX_FLAG \ ++ IOMUX_PAD(0x038C, 0x0078, 0, 0x0000, 0, 0) ++#define _MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 \ ++ IOMUX_PAD(0x038C, 0x0078, 1, 0x084C, 0, 0) ++#define _MX6Q_PAD_RGMII_RD1__GPIO_6_27 \ ++ IOMUX_PAD(0x038C, 0x0078, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_RGMII_RD1__MIPI_CORE_DPHY_TEST_IN_8 \ ++ IOMUX_PAD(0x038C, 0x0078, 6, 0x0000, 0, 0) ++#define _MX6Q_PAD_RGMII_RD1__SJC_FAIL \ ++ IOMUX_PAD(0x038C, 0x0078, 7, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_RGMII_RD2__MIPI_HSI_CTRL_TX_DATA \ ++ IOMUX_PAD(0x0390, 0x007C, 0, 0x0000, 0, 0) ++#define _MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 \ ++ IOMUX_PAD(0x0390, 0x007C, 1, 0x0850, 0, 0) ++#define _MX6Q_PAD_RGMII_RD2__GPIO_6_28 \ ++ IOMUX_PAD(0x0390, 0x007C, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_RGMII_RD2__MIPI_CORE_DPHY_TEST_IN_9 \ ++ IOMUX_PAD(0x0390, 0x007C, 6, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_RGMII_RD3__MIPI_HSI_CTRL_TX_WAKE \ ++ IOMUX_PAD(0x0394, 0x0080, 0, 0x0000, 0, 0) ++#define _MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 \ ++ IOMUX_PAD(0x0394, 0x0080, 1, 0x0854, 0, 0) ++#define _MX6Q_PAD_RGMII_RD3__GPIO_6_29 \ ++ IOMUX_PAD(0x0394, 0x0080, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_RGMII_RD3__MIPI_CORE_DPHY_TEST_IN_10 \ ++ IOMUX_PAD(0x0394, 0x0080, 6, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_RGMII_RXC__USBOH3_H3_STROBE \ ++ IOMUX_PAD(0x0398, 0x0084, 0, 0x0000, 0, 0) ++#define _MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC \ ++ IOMUX_PAD(0x0398, 0x0084, 1, 0x0844, 0, 0) ++#define _MX6Q_PAD_RGMII_RXC__GPIO_6_30 \ ++ IOMUX_PAD(0x0398, 0x0084, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_RGMII_RXC__MIPI_CORE_DPHY_TEST_IN_11 \ ++ IOMUX_PAD(0x0398, 0x0084, 6, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_EIM_A25__WEIM_WEIM_A_25 \ ++ IOMUX_PAD(0x039C, 0x0088, 0, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_A25__ECSPI4_SS1 \ ++ IOMUX_PAD(0x039C, 0x0088, 1, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_A25__ECSPI2_RDY \ ++ IOMUX_PAD(0x039C, 0x0088, 2, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_A25__IPU1_DI1_PIN12 \ ++ IOMUX_PAD(0x039C, 0x0088, 3, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_A25__IPU1_DI0_D1_CS \ ++ IOMUX_PAD(0x039C, 0x0088, 4, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_A25__GPIO_5_2 \ ++ IOMUX_PAD(0x039C, 0x0088, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_A25__HDMI_TX_CEC_LINE \ ++ IOMUX_PAD(0x039C, 0x0088, 6, 0x088C, 0, 0) ++#define _MX6Q_PAD_EIM_A25__PL301_MX6QPER1_HBURST_0 \ ++ IOMUX_PAD(0x039C, 0x0088, 7, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_EIM_EB2__WEIM_WEIM_EB_2 \ ++ IOMUX_PAD(0x03A0, 0x008C, 0, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_EB2__ECSPI1_SS0 \ ++ IOMUX_PAD(0x03A0, 0x008C, 1, 0x0800, 0, 0) ++#define _MX6Q_PAD_EIM_EB2__CCM_DI1_EXT_CLK \ ++ IOMUX_PAD(0x03A0, 0x008C, 2, 0x07EC, 0, 0) ++#define _MX6Q_PAD_EIM_EB2__IPU2_CSI1_D_19 \ ++ IOMUX_PAD(0x03A0, 0x008C, 3, 0x08D4, 0, 0) ++#define _MX6Q_PAD_EIM_EB2__HDMI_TX_DDC_SCL \ ++ IOMUX_PAD(0x03A0, 0x008C, 4, 0x0890, 0, 0) ++#define _MX6Q_PAD_EIM_EB2__GPIO_2_30 \ ++ IOMUX_PAD(0x03A0, 0x008C, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_EB2__I2C2_SCL \ ++ IOMUX_PAD(0x03A0, 0x008C, 6 | IOMUX_CONFIG_SION, 0x08A0, 0, 0) ++#define _MX6Q_PAD_EIM_EB2__SRC_BT_CFG_30 \ ++ IOMUX_PAD(0x03A0, 0x008C, 7, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_EIM_D16__WEIM_WEIM_D_16 \ ++ IOMUX_PAD(0x03A4, 0x0090, 0, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_D16__ECSPI1_SCLK \ ++ IOMUX_PAD(0x03A4, 0x0090, 1, 0x07F4, 0, 0) ++#define _MX6Q_PAD_EIM_D16__IPU1_DI0_PIN5 \ ++ IOMUX_PAD(0x03A4, 0x0090, 2, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_D16__IPU2_CSI1_D_18 \ ++ IOMUX_PAD(0x03A4, 0x0090, 3, 0x08D0, 0, 0) ++#define _MX6Q_PAD_EIM_D16__HDMI_TX_DDC_SDA \ ++ IOMUX_PAD(0x03A4, 0x0090, 4, 0x0894, 0, 0) ++#define _MX6Q_PAD_EIM_D16__GPIO_3_16 \ ++ IOMUX_PAD(0x03A4, 0x0090, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_D16__I2C2_SDA \ ++ IOMUX_PAD(0x03A4, 0x0090, 6 | IOMUX_CONFIG_SION, 0x08A4, 0, 0) ++ ++#define _MX6Q_PAD_EIM_D17__WEIM_WEIM_D_17 \ ++ IOMUX_PAD(0x03A8, 0x0094, 0, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_D17__ECSPI1_MISO \ ++ IOMUX_PAD(0x03A8, 0x0094, 1, 0x07F8, 0, 0) ++#define _MX6Q_PAD_EIM_D17__IPU1_DI0_PIN6 \ ++ IOMUX_PAD(0x03A8, 0x0094, 2, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_D17__IPU2_CSI1_PIXCLK \ ++ IOMUX_PAD(0x03A8, 0x0094, 3, 0x08E0, 0, 0) ++#define _MX6Q_PAD_EIM_D17__DCIC1_DCIC_OUT \ ++ IOMUX_PAD(0x03A8, 0x0094, 4, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_D17__GPIO_3_17 \ ++ IOMUX_PAD(0x03A8, 0x0094, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_D17__I2C3_SCL \ ++ IOMUX_PAD(0x03A8, 0x0094, 6 | IOMUX_CONFIG_SION, 0x08A8, 0, 0) ++#define _MX6Q_PAD_EIM_D17__PL301_MX6QPER1_HBURST_1 \ ++ IOMUX_PAD(0x03A8, 0x0094, 7, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_EIM_D18__WEIM_WEIM_D_18 \ ++ IOMUX_PAD(0x03AC, 0x0098, 0, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_D18__ECSPI1_MOSI \ ++ IOMUX_PAD(0x03AC, 0x0098, 1, 0x07FC, 0, 0) ++#define _MX6Q_PAD_EIM_D18__IPU1_DI0_PIN7 \ ++ IOMUX_PAD(0x03AC, 0x0098, 2, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_D18__IPU2_CSI1_D_17 \ ++ IOMUX_PAD(0x03AC, 0x0098, 3, 0x08CC, 0, 0) ++#define _MX6Q_PAD_EIM_D18__IPU1_DI1_D0_CS \ ++ IOMUX_PAD(0x03AC, 0x0098, 4, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_D18__GPIO_3_18 \ ++ IOMUX_PAD(0x03AC, 0x0098, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_D18__I2C3_SDA \ ++ IOMUX_PAD(0x03AC, 0x0098, 6 | IOMUX_CONFIG_SION, 0x08AC, 0, 0) ++#define _MX6Q_PAD_EIM_D18__PL301_MX6QPER1_HBURST_2 \ ++ IOMUX_PAD(0x03AC, 0x0098, 7, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_EIM_D19__WEIM_WEIM_D_19 \ ++ IOMUX_PAD(0x03B0, 0x009C, 0, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_D19__ECSPI1_SS1 \ ++ IOMUX_PAD(0x03B0, 0x009C, 1, 0x0804, 0, 0) ++#define _MX6Q_PAD_EIM_D19__IPU1_DI0_PIN8 \ ++ IOMUX_PAD(0x03B0, 0x009C, 2, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_D19__IPU2_CSI1_D_16 \ ++ IOMUX_PAD(0x03B0, 0x009C, 3, 0x08C8, 0, 0) ++#define _MX6Q_PAD_EIM_D19__UART1_CTS \ ++ IOMUX_PAD(0x03B0, 0x009C, 4, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_D19__UART1_RTS \ ++ IOMUX_PAD(0x03B0, 0x009C, 4, 0x091C, 0, 0) ++#define _MX6Q_PAD_EIM_D19__GPIO_3_19 \ ++ IOMUX_PAD(0x03B0, 0x009C, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_D19__EPIT1_EPITO \ ++ IOMUX_PAD(0x03B0, 0x009C, 6, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_D19__PL301_MX6QPER1_HRESP \ ++ IOMUX_PAD(0x03B0, 0x009C, 7, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_EIM_D20__WEIM_WEIM_D_20 \ ++ IOMUX_PAD(0x03B4, 0x00A0, 0, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_D20__ECSPI4_SS0 \ ++ IOMUX_PAD(0x03B4, 0x00A0, 1, 0x0824, 0, 0) ++#define _MX6Q_PAD_EIM_D20__IPU1_DI0_PIN16 \ ++ IOMUX_PAD(0x03B4, 0x00A0, 2, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_D20__IPU2_CSI1_D_15 \ ++ IOMUX_PAD(0x03B4, 0x00A0, 3, 0x08C4, 0, 0) ++#define _MX6Q_PAD_EIM_D20__UART1_CTS \ ++ IOMUX_PAD(0x03B4, 0x00A0, 4, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_D20__UART1_RTS \ ++ IOMUX_PAD(0x03B4, 0x00A0, 4, 0x091C, 1, 0) ++#define _MX6Q_PAD_EIM_D20__GPIO_3_20 \ ++ IOMUX_PAD(0x03B4, 0x00A0, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_D20__EPIT2_EPITO \ ++ IOMUX_PAD(0x03B4, 0x00A0, 6, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_EIM_D21__WEIM_WEIM_D_21 \ ++ IOMUX_PAD(0x03B8, 0x00A4, 0, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_D21__ECSPI4_SCLK \ ++ IOMUX_PAD(0x03B8, 0x00A4, 1, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_D21__IPU1_DI0_PIN17 \ ++ IOMUX_PAD(0x03B8, 0x00A4, 2, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_D21__IPU2_CSI1_D_11 \ ++ IOMUX_PAD(0x03B8, 0x00A4, 3, 0x08B4, 0, 0) ++#define _MX6Q_PAD_EIM_D21__USBOH3_USBOTG_OC \ ++ IOMUX_PAD(0x03B8, 0x00A4, 4, 0x0944, 0, 0) ++#define _MX6Q_PAD_EIM_D21__GPIO_3_21 \ ++ IOMUX_PAD(0x03B8, 0x00A4, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_D21__I2C1_SCL \ ++ IOMUX_PAD(0x03B8, 0x00A4, 6 | IOMUX_CONFIG_SION, 0x0898, 0, 0) ++#define _MX6Q_PAD_EIM_D21__SPDIF_IN1 \ ++ IOMUX_PAD(0x03B8, 0x00A4, 7, 0x0914, 0, 0) ++ ++#define _MX6Q_PAD_EIM_D22__WEIM_WEIM_D_22 \ ++ IOMUX_PAD(0x03BC, 0x00A8, 0, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_D22__ECSPI4_MISO \ ++ IOMUX_PAD(0x03BC, 0x00A8, 1, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_D22__IPU1_DI0_PIN1 \ ++ IOMUX_PAD(0x03BC, 0x00A8, 2, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_D22__IPU2_CSI1_D_10 \ ++ IOMUX_PAD(0x03BC, 0x00A8, 3, 0x08B0, 0, 0) ++#define _MX6Q_PAD_EIM_D22__USBOH3_USBOTG_PWR \ ++ IOMUX_PAD(0x03BC, 0x00A8, 4, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_D22__GPIO_3_22 \ ++ IOMUX_PAD(0x03BC, 0x00A8, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_D22__SPDIF_OUT1 \ ++ IOMUX_PAD(0x03BC, 0x00A8, 6, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_D22__PL301_MX6QPER1_HWRITE \ ++ IOMUX_PAD(0x03BC, 0x00A8, 7, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_EIM_D23__WEIM_WEIM_D_23 \ ++ IOMUX_PAD(0x03C0, 0x00AC, 0, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_D23__IPU1_DI0_D0_CS \ ++ IOMUX_PAD(0x03C0, 0x00AC, 1, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_D23__UART3_CTS \ ++ IOMUX_PAD(0x03C0, 0x00AC, 2, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_D23__UART3_RTS \ ++ IOMUX_PAD(0x03C0, 0x00AC, 2, 0x092C, 0, 0) ++#define _MX6Q_PAD_EIM_D23__UART1_DCD \ ++ IOMUX_PAD(0x03C0, 0x00AC, 3, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_D23__IPU2_CSI1_DATA_EN \ ++ IOMUX_PAD(0x03C0, 0x00AC, 4, 0x08D8, 0, 0) ++#define _MX6Q_PAD_EIM_D23__GPIO_3_23 \ ++ IOMUX_PAD(0x03C0, 0x00AC, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_D23__IPU1_DI1_PIN2 \ ++ IOMUX_PAD(0x03C0, 0x00AC, 6, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_D23__IPU1_DI1_PIN14 \ ++ IOMUX_PAD(0x03C0, 0x00AC, 7, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_EIM_EB3__WEIM_WEIM_EB_3 \ ++ IOMUX_PAD(0x03C4, 0x00B0, 0, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_EB3__ECSPI4_RDY \ ++ IOMUX_PAD(0x03C4, 0x00B0, 1, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_EB3__UART3_CTS \ ++ IOMUX_PAD(0x03C4, 0x00B0, 2, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_EB3__UART3_RTS \ ++ IOMUX_PAD(0x03C4, 0x00B0, 2, 0x092C, 1, 0) ++#define _MX6Q_PAD_EIM_EB3__UART1_RI \ ++ IOMUX_PAD(0x03C4, 0x00B0, 3, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_EB3__IPU2_CSI1_HSYNC \ ++ IOMUX_PAD(0x03C4, 0x00B0, 4, 0x08DC, 0, 0) ++#define _MX6Q_PAD_EIM_EB3__GPIO_2_31 \ ++ IOMUX_PAD(0x03C4, 0x00B0, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_EB3__IPU1_DI1_PIN3 \ ++ IOMUX_PAD(0x03C4, 0x00B0, 6, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_EB3__SRC_BT_CFG_31 \ ++ IOMUX_PAD(0x03C4, 0x00B0, 7, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_EIM_D24__WEIM_WEIM_D_24 \ ++ IOMUX_PAD(0x03C8, 0x00B4, 0, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_D24__ECSPI4_SS2 \ ++ IOMUX_PAD(0x03C8, 0x00B4, 1, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_D24__UART3_TXD \ ++ IOMUX_PAD(0x03C8, 0x00B4, 2, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_D24__UART3_RXD \ ++ IOMUX_PAD(0x03C8, 0x00B4, 2, 0x0930, 0, 0) ++#define _MX6Q_PAD_EIM_D24__ECSPI1_SS2 \ ++ IOMUX_PAD(0x03C8, 0x00B4, 3, 0x0808, 0, 0) ++#define _MX6Q_PAD_EIM_D24__ECSPI2_SS2 \ ++ IOMUX_PAD(0x03C8, 0x00B4, 4, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_D24__GPIO_3_24 \ ++ IOMUX_PAD(0x03C8, 0x00B4, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_D24__AUDMUX_AUD5_RXFS \ ++ IOMUX_PAD(0x03C8, 0x00B4, 6, 0x07D8, 0, 0) ++#define _MX6Q_PAD_EIM_D24__UART1_DTR \ ++ IOMUX_PAD(0x03C8, 0x00B4, 7, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_EIM_D25__WEIM_WEIM_D_25 \ ++ IOMUX_PAD(0x03CC, 0x00B8, 0, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_D25__ECSPI4_SS3 \ ++ IOMUX_PAD(0x03CC, 0x00B8, 1, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_D25__UART3_TXD \ ++ IOMUX_PAD(0x03CC, 0x00B8, 2, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_D25__UART3_RXD \ ++ IOMUX_PAD(0x03CC, 0x00B8, 2, 0x0930, 1, 0) ++#define _MX6Q_PAD_EIM_D25__ECSPI1_SS3 \ ++ IOMUX_PAD(0x03CC, 0x00B8, 3, 0x080C, 0, 0) ++#define _MX6Q_PAD_EIM_D25__ECSPI2_SS3 \ ++ IOMUX_PAD(0x03CC, 0x00B8, 4, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_D25__GPIO_3_25 \ ++ IOMUX_PAD(0x03CC, 0x00B8, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_D25__AUDMUX_AUD5_RXC \ ++ IOMUX_PAD(0x03CC, 0x00B8, 6, 0x07D4, 0, 0) ++#define _MX6Q_PAD_EIM_D25__UART1_DSR \ ++ IOMUX_PAD(0x03CC, 0x00B8, 7, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_EIM_D26__WEIM_WEIM_D_26 \ ++ IOMUX_PAD(0x03D0, 0x00BC, 0, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_D26__IPU1_DI1_PIN11 \ ++ IOMUX_PAD(0x03D0, 0x00BC, 1, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_D26__IPU1_CSI0_D_1 \ ++ IOMUX_PAD(0x03D0, 0x00BC, 2, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_D26__IPU2_CSI1_D_14 \ ++ IOMUX_PAD(0x03D0, 0x00BC, 3, 0x08C0, 0, 0) ++#define _MX6Q_PAD_EIM_D26__UART2_TXD \ ++ IOMUX_PAD(0x03D0, 0x00BC, 4, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_D26__UART2_RXD \ ++ IOMUX_PAD(0x03D0, 0x00BC, 4, 0x0928, 0, 0) ++#define _MX6Q_PAD_EIM_D26__GPIO_3_26 \ ++ IOMUX_PAD(0x03D0, 0x00BC, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_D26__IPU1_SISG_2 \ ++ IOMUX_PAD(0x03D0, 0x00BC, 6, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_D26__IPU1_DISP1_DAT_22 \ ++ IOMUX_PAD(0x03D0, 0x00BC, 7, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_EIM_D27__WEIM_WEIM_D_27 \ ++ IOMUX_PAD(0x03D4, 0x00C0, 0, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_D27__IPU1_DI1_PIN13 \ ++ IOMUX_PAD(0x03D4, 0x00C0, 1, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_D27__IPU1_CSI0_D_0 \ ++ IOMUX_PAD(0x03D4, 0x00C0, 2, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_D27__IPU2_CSI1_D_13 \ ++ IOMUX_PAD(0x03D4, 0x00C0, 3, 0x08BC, 0, 0) ++#define _MX6Q_PAD_EIM_D27__UART2_TXD \ ++ IOMUX_PAD(0x03D4, 0x00C0, 4, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_D27__UART2_RXD \ ++ IOMUX_PAD(0x03D4, 0x00C0, 4, 0x0928, 1, 0) ++#define _MX6Q_PAD_EIM_D27__GPIO_3_27 \ ++ IOMUX_PAD(0x03D4, 0x00C0, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_D27__IPU1_SISG_3 \ ++ IOMUX_PAD(0x03D4, 0x00C0, 6, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_D27__IPU1_DISP1_DAT_23 \ ++ IOMUX_PAD(0x03D4, 0x00C0, 7, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_EIM_D28__WEIM_WEIM_D_28 \ ++ IOMUX_PAD(0x03D8, 0x00C4, 0, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_D28__I2C1_SDA \ ++ IOMUX_PAD(0x03D8, 0x00C4, 1 | IOMUX_CONFIG_SION, 0x089C, 0, 0) ++#define _MX6Q_PAD_EIM_D28__ECSPI4_MOSI \ ++ IOMUX_PAD(0x03D8, 0x00C4, 2, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_D28__IPU2_CSI1_D_12 \ ++ IOMUX_PAD(0x03D8, 0x00C4, 3, 0x08B8, 0, 0) ++#define _MX6Q_PAD_EIM_D28__UART2_CTS \ ++ IOMUX_PAD(0x03D8, 0x00C4, 4, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_D28__UART2_RTS \ ++ IOMUX_PAD(0x03D8, 0x00C4, 4, 0x0924, 0, 0) ++#define _MX6Q_PAD_EIM_D28__GPIO_3_28 \ ++ IOMUX_PAD(0x03D8, 0x00C4, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_D28__IPU1_EXT_TRIG \ ++ IOMUX_PAD(0x03D8, 0x00C4, 6, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_D28__IPU1_DI0_PIN13 \ ++ IOMUX_PAD(0x03D8, 0x00C4, 7, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_EIM_D29__WEIM_WEIM_D_29 \ ++ IOMUX_PAD(0x03DC, 0x00C8, 0, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_D29__IPU1_DI1_PIN15 \ ++ IOMUX_PAD(0x03DC, 0x00C8, 1, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_D29__ECSPI4_SS0 \ ++ IOMUX_PAD(0x03DC, 0x00C8, 2, 0x0824, 1, 0) ++#define _MX6Q_PAD_EIM_D29__UART2_CTS \ ++ IOMUX_PAD(0x03DC, 0x00C8, 4, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_D29__UART2_RTS \ ++ IOMUX_PAD(0x03DC, 0x00C8, 4, 0x0924, 1, 0) ++#define _MX6Q_PAD_EIM_D29__GPIO_3_29 \ ++ IOMUX_PAD(0x03DC, 0x00C8, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_D29__IPU2_CSI1_VSYNC \ ++ IOMUX_PAD(0x03DC, 0x00C8, 6, 0x08E4, 0, 0) ++#define _MX6Q_PAD_EIM_D29__IPU1_DI0_PIN14 \ ++ IOMUX_PAD(0x03DC, 0x00C8, 7, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_EIM_D30__WEIM_WEIM_D_30 \ ++ IOMUX_PAD(0x03E0, 0x00CC, 0, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_D30__IPU1_DISP1_DAT_21 \ ++ IOMUX_PAD(0x03E0, 0x00CC, 1, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_D30__IPU1_DI0_PIN11 \ ++ IOMUX_PAD(0x03E0, 0x00CC, 2, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_D30__IPU1_CSI0_D_3 \ ++ IOMUX_PAD(0x03E0, 0x00CC, 3, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_D30__UART3_CTS \ ++ IOMUX_PAD(0x03E0, 0x00CC, 4, 0x0000, 2, 0) ++#define _MX6Q_PAD_EIM_D30__UART3_RTS \ ++ IOMUX_PAD(0x03E0, 0x00CC, 4, 0x092C, 2, 0) ++#define _MX6Q_PAD_EIM_D30__GPIO_3_30 \ ++ IOMUX_PAD(0x03E0, 0x00CC, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_D30__USBOH3_USBH1_OC \ ++ IOMUX_PAD(0x03E0, 0x00CC, 6, 0x0948, 0, 0) ++#define _MX6Q_PAD_EIM_D30__PL301_MX6QPER1_HPROT_0 \ ++ IOMUX_PAD(0x03E0, 0x00CC, 7, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_EIM_D31__WEIM_WEIM_D_31 \ ++ IOMUX_PAD(0x03E4, 0x00D0, 0, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_D31__IPU1_DISP1_DAT_20 \ ++ IOMUX_PAD(0x03E4, 0x00D0, 1, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_D31__IPU1_DI0_PIN12 \ ++ IOMUX_PAD(0x03E4, 0x00D0, 2, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_D31__IPU1_CSI0_D_2 \ ++ IOMUX_PAD(0x03E4, 0x00D0, 3, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_D31__UART3_CTS \ ++ IOMUX_PAD(0x03E4, 0x00D0, 4, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_D31__UART3_RTS \ ++ IOMUX_PAD(0x03E4, 0x00D0, 4, 0x092C, 3, 0) ++#define _MX6Q_PAD_EIM_D31__GPIO_3_31 \ ++ IOMUX_PAD(0x03E4, 0x00D0, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_D31__USBOH3_USBH1_PWR \ ++ IOMUX_PAD(0x03E4, 0x00D0, 6, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_D31__PL301_MX6QPER1_HPROT_1 \ ++ IOMUX_PAD(0x03E4, 0x00D0, 7, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_EIM_A24__WEIM_WEIM_A_24 \ ++ IOMUX_PAD(0x03E8, 0x00D4, 0, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_A24__IPU1_DISP1_DAT_19 \ ++ IOMUX_PAD(0x03E8, 0x00D4, 1, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_A24__IPU2_CSI1_D_19 \ ++ IOMUX_PAD(0x03E8, 0x00D4, 2, 0x08D4, 1, 0) ++#define _MX6Q_PAD_EIM_A24__IPU2_SISG_2 \ ++ IOMUX_PAD(0x03E8, 0x00D4, 3, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_A24__IPU1_SISG_2 \ ++ IOMUX_PAD(0x03E8, 0x00D4, 4, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_A24__GPIO_5_4 \ ++ IOMUX_PAD(0x03E8, 0x00D4, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_A24__PL301_MX6QPER1_HPROT_2 \ ++ IOMUX_PAD(0x03E8, 0x00D4, 6, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_A24__SRC_BT_CFG_24 \ ++ IOMUX_PAD(0x03E8, 0x00D4, 7, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_EIM_A23__WEIM_WEIM_A_23 \ ++ IOMUX_PAD(0x03EC, 0x00D8, 0, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_A23__IPU1_DISP1_DAT_18 \ ++ IOMUX_PAD(0x03EC, 0x00D8, 1, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_A23__IPU2_CSI1_D_18 \ ++ IOMUX_PAD(0x03EC, 0x00D8, 2, 0x08D0, 1, 0) ++#define _MX6Q_PAD_EIM_A23__IPU2_SISG_3 \ ++ IOMUX_PAD(0x03EC, 0x00D8, 3, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_A23__IPU1_SISG_3 \ ++ IOMUX_PAD(0x03EC, 0x00D8, 4, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_A23__GPIO_6_6 \ ++ IOMUX_PAD(0x03EC, 0x00D8, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_A23__PL301_MX6QPER1_HPROT_3 \ ++ IOMUX_PAD(0x03EC, 0x00D8, 6, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_A23__SRC_BT_CFG_23 \ ++ IOMUX_PAD(0x03EC, 0x00D8, 7, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_EIM_A22__WEIM_WEIM_A_22 \ ++ IOMUX_PAD(0x03F0, 0x00DC, 0, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_A22__IPU1_DISP1_DAT_17 \ ++ IOMUX_PAD(0x03F0, 0x00DC, 1, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_A22__IPU2_CSI1_D_17 \ ++ IOMUX_PAD(0x03F0, 0x00DC, 2, 0x08CC, 1, 0) ++#define _MX6Q_PAD_EIM_A22__GPIO_2_16 \ ++ IOMUX_PAD(0x03F0, 0x00DC, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_A22__TPSMP_HDATA_0 \ ++ IOMUX_PAD(0x03F0, 0x00DC, 6, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_A22__SRC_BT_CFG_22 \ ++ IOMUX_PAD(0x03F0, 0x00DC, 7, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_EIM_A21__WEIM_WEIM_A_21 \ ++ IOMUX_PAD(0x03F4, 0x00E0, 0, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_A21__IPU1_DISP1_DAT_16 \ ++ IOMUX_PAD(0x03F4, 0x00E0, 1, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_A21__IPU2_CSI1_D_16 \ ++ IOMUX_PAD(0x03F4, 0x00E0, 2, 0x08C8, 1, 0) ++#define _MX6Q_PAD_EIM_A21__MIPI_CORE_DPHY_TEST_OUT_18 \ ++ IOMUX_PAD(0x03F4, 0x00E0, 4, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_A21__GPIO_2_17 \ ++ IOMUX_PAD(0x03F4, 0x00E0, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_A21__TPSMP_HDATA_1 \ ++ IOMUX_PAD(0x03F4, 0x00E0, 6, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_A21__SRC_BT_CFG_21 \ ++ IOMUX_PAD(0x03F4, 0x00E0, 7, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_EIM_A20__WEIM_WEIM_A_20 \ ++ IOMUX_PAD(0x03F8, 0x00E4, 0, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_A20__IPU1_DISP1_DAT_15 \ ++ IOMUX_PAD(0x03F8, 0x00E4, 1, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_A20__IPU2_CSI1_D_15 \ ++ IOMUX_PAD(0x03F8, 0x00E4, 2, 0x08C4, 1, 0) ++#define _MX6Q_PAD_EIM_A20__MIPI_CORE_DPHY_TEST_OUT_19 \ ++ IOMUX_PAD(0x03F8, 0x00E4, 4, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_A20__GPIO_2_18 \ ++ IOMUX_PAD(0x03F8, 0x00E4, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_A20__TPSMP_HDATA_2 \ ++ IOMUX_PAD(0x03F8, 0x00E4, 6, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_A20__SRC_BT_CFG_20 \ ++ IOMUX_PAD(0x03F8, 0x00E4, 7, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_EIM_A19__WEIM_WEIM_A_19 \ ++ IOMUX_PAD(0x03FC, 0x00E8, 0, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_A19__IPU1_DISP1_DAT_14 \ ++ IOMUX_PAD(0x03FC, 0x00E8, 1, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_A19__IPU2_CSI1_D_14 \ ++ IOMUX_PAD(0x03FC, 0x00E8, 2, 0x08C0, 1, 0) ++#define _MX6Q_PAD_EIM_A19__MIPI_CORE_DPHY_TEST_OUT_20 \ ++ IOMUX_PAD(0x03FC, 0x00E8, 4, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_A19__GPIO_2_19 \ ++ IOMUX_PAD(0x03FC, 0x00E8, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_A19__TPSMP_HDATA_3 \ ++ IOMUX_PAD(0x03FC, 0x00E8, 6, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_A19__SRC_BT_CFG_19 \ ++ IOMUX_PAD(0x03FC, 0x00E8, 7, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_EIM_A18__WEIM_WEIM_A_18 \ ++ IOMUX_PAD(0x0400, 0x00EC, 0, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_A18__IPU1_DISP1_DAT_13 \ ++ IOMUX_PAD(0x0400, 0x00EC, 1, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_A18__IPU2_CSI1_D_13 \ ++ IOMUX_PAD(0x0400, 0x00EC, 2, 0x08BC, 1, 0) ++#define _MX6Q_PAD_EIM_A18__MIPI_CORE_DPHY_TEST_OUT_21 \ ++ IOMUX_PAD(0x0400, 0x00EC, 4, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_A18__GPIO_2_20 \ ++ IOMUX_PAD(0x0400, 0x00EC, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_A18__TPSMP_HDATA_4 \ ++ IOMUX_PAD(0x0400, 0x00EC, 6, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_A18__SRC_BT_CFG_18 \ ++ IOMUX_PAD(0x0400, 0x00EC, 7, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_EIM_A17__WEIM_WEIM_A_17 \ ++ IOMUX_PAD(0x0404, 0x00F0, 0, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_A17__IPU1_DISP1_DAT_12 \ ++ IOMUX_PAD(0x0404, 0x00F0, 1, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_A17__IPU2_CSI1_D_12 \ ++ IOMUX_PAD(0x0404, 0x00F0, 2, 0x08B8, 1, 0) ++#define _MX6Q_PAD_EIM_A17__MIPI_CORE_DPHY_TEST_OUT_22 \ ++ IOMUX_PAD(0x0404, 0x00F0, 4, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_A17__GPIO_2_21 \ ++ IOMUX_PAD(0x0404, 0x00F0, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_A17__TPSMP_HDATA_5 \ ++ IOMUX_PAD(0x0404, 0x00F0, 6, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_A17__SRC_BT_CFG_17 \ ++ IOMUX_PAD(0x0404, 0x00F0, 7, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_EIM_A16__WEIM_WEIM_A_16 \ ++ IOMUX_PAD(0x0408, 0x00F4, 0, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_A16__IPU1_DI1_DISP_CLK \ ++ IOMUX_PAD(0x0408, 0x00F4, 1, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_A16__IPU2_CSI1_PIXCLK \ ++ IOMUX_PAD(0x0408, 0x00F4, 2, 0x08E0, 1, 0) ++#define _MX6Q_PAD_EIM_A16__MIPI_CORE_DPHY_TEST_OUT_23 \ ++ IOMUX_PAD(0x0408, 0x00F4, 4, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_A16__GPIO_2_22 \ ++ IOMUX_PAD(0x0408, 0x00F4, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_A16__TPSMP_HDATA_6 \ ++ IOMUX_PAD(0x0408, 0x00F4, 6, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_A16__SRC_BT_CFG_16 \ ++ IOMUX_PAD(0x0408, 0x00F4, 7, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_EIM_CS0__WEIM_WEIM_CS_0 \ ++ IOMUX_PAD(0x040C, 0x00F8, 0, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_CS0__IPU1_DI1_PIN5 \ ++ IOMUX_PAD(0x040C, 0x00F8, 1, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_CS0__ECSPI2_SCLK \ ++ IOMUX_PAD(0x040C, 0x00F8, 2, 0x0810, 0, 0) ++#define _MX6Q_PAD_EIM_CS0__MIPI_CORE_DPHY_TEST_OUT_24 \ ++ IOMUX_PAD(0x040C, 0x00F8, 4, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_CS0__GPIO_2_23 \ ++ IOMUX_PAD(0x040C, 0x00F8, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_CS0__TPSMP_HDATA_7 \ ++ IOMUX_PAD(0x040C, 0x00F8, 6, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_EIM_CS1__WEIM_WEIM_CS_1 \ ++ IOMUX_PAD(0x0410, 0x00FC, 0, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_CS1__IPU1_DI1_PIN6 \ ++ IOMUX_PAD(0x0410, 0x00FC, 1, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_CS1__ECSPI2_MOSI \ ++ IOMUX_PAD(0x0410, 0x00FC, 2, 0x0818, 0, 0) ++#define _MX6Q_PAD_EIM_CS1__MIPI_CORE_DPHY_TEST_OUT_25 \ ++ IOMUX_PAD(0x0410, 0x00FC, 4, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_CS1__GPIO_2_24 \ ++ IOMUX_PAD(0x0410, 0x00FC, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_CS1__TPSMP_HDATA_8 \ ++ IOMUX_PAD(0x0410, 0x00FC, 6, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_EIM_OE__WEIM_WEIM_OE \ ++ IOMUX_PAD(0x0414, 0x0100, 0, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_OE__IPU1_DI1_PIN7 \ ++ IOMUX_PAD(0x0414, 0x0100, 1, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_OE__ECSPI2_MISO \ ++ IOMUX_PAD(0x0414, 0x0100, 2, 0x0814, 0, 0) ++#define _MX6Q_PAD_EIM_OE__MIPI_CORE_DPHY_TEST_OUT_26 \ ++ IOMUX_PAD(0x0414, 0x0100, 4, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_OE__GPIO_2_25 \ ++ IOMUX_PAD(0x0414, 0x0100, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_OE__TPSMP_HDATA_9 \ ++ IOMUX_PAD(0x0414, 0x0100, 6, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_EIM_RW__WEIM_WEIM_RW \ ++ IOMUX_PAD(0x0418, 0x0104, 0, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_RW__IPU1_DI1_PIN8 \ ++ IOMUX_PAD(0x0418, 0x0104, 1, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_RW__ECSPI2_SS0 \ ++ IOMUX_PAD(0x0418, 0x0104, 2, 0x081C, 0, 0) ++#define _MX6Q_PAD_EIM_RW__MIPI_CORE_DPHY_TEST_OUT_27 \ ++ IOMUX_PAD(0x0418, 0x0104, 4, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_RW__GPIO_2_26 \ ++ IOMUX_PAD(0x0418, 0x0104, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_RW__TPSMP_HDATA_10 \ ++ IOMUX_PAD(0x0418, 0x0104, 6, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_RW__SRC_BT_CFG_29 \ ++ IOMUX_PAD(0x0418, 0x0104, 7, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_EIM_LBA__WEIM_WEIM_LBA \ ++ IOMUX_PAD(0x041C, 0x0108, 0, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_LBA__IPU1_DI1_PIN17 \ ++ IOMUX_PAD(0x041C, 0x0108, 1, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_LBA__ECSPI2_SS1 \ ++ IOMUX_PAD(0x041C, 0x0108, 2, 0x0820, 0, 0) ++#define _MX6Q_PAD_EIM_LBA__GPIO_2_27 \ ++ IOMUX_PAD(0x041C, 0x0108, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_LBA__TPSMP_HDATA_11 \ ++ IOMUX_PAD(0x041C, 0x0108, 6, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_LBA__SRC_BT_CFG_26 \ ++ IOMUX_PAD(0x041C, 0x0108, 7, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_EIM_EB0__WEIM_WEIM_EB_0 \ ++ IOMUX_PAD(0x0420, 0x010C, 0, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_EB0__IPU1_DISP1_DAT_11 \ ++ IOMUX_PAD(0x0420, 0x010C, 1, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_EB0__IPU2_CSI1_D_11 \ ++ IOMUX_PAD(0x0420, 0x010C, 2, 0x08B4, 1, 0) ++#define _MX6Q_PAD_EIM_EB0__MIPI_CORE_DPHY_TEST_OUT_0 \ ++ IOMUX_PAD(0x0420, 0x010C, 3, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_EB0__CCM_PMIC_RDY \ ++ IOMUX_PAD(0x0420, 0x010C, 4, 0x07F0, 0, 0) ++#define _MX6Q_PAD_EIM_EB0__GPIO_2_28 \ ++ IOMUX_PAD(0x0420, 0x010C, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_EB0__TPSMP_HDATA_12 \ ++ IOMUX_PAD(0x0420, 0x010C, 6, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_EB0__SRC_BT_CFG_27 \ ++ IOMUX_PAD(0x0420, 0x010C, 7, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_EIM_EB1__WEIM_WEIM_EB_1 \ ++ IOMUX_PAD(0x0424, 0x0110, 0, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_EB1__IPU1_DISP1_DAT_10 \ ++ IOMUX_PAD(0x0424, 0x0110, 1, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_EB1__IPU2_CSI1_D_10 \ ++ IOMUX_PAD(0x0424, 0x0110, 2, 0x08B0, 1, 0) ++#define _MX6Q_PAD_EIM_EB1__MIPI_CORE_DPHY_TEST_OUT_1 \ ++ IOMUX_PAD(0x0424, 0x0110, 3, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_EB1__GPIO_2_29 \ ++ IOMUX_PAD(0x0424, 0x0110, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_EB1__TPSMP_HDATA_13 \ ++ IOMUX_PAD(0x0424, 0x0110, 6, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_EB1__SRC_BT_CFG_28 \ ++ IOMUX_PAD(0x0424, 0x0110, 7, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_EIM_DA0__WEIM_WEIM_DA_A_0 \ ++ IOMUX_PAD(0x0428, 0x0114, 0, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_DA0__IPU1_DISP1_DAT_9 \ ++ IOMUX_PAD(0x0428, 0x0114, 1, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_DA0__IPU2_CSI1_D_9 \ ++ IOMUX_PAD(0x0428, 0x0114, 2, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_DA0__MIPI_CORE_DPHY_TEST_OUT_2 \ ++ IOMUX_PAD(0x0428, 0x0114, 3, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_DA0__GPIO_3_0 \ ++ IOMUX_PAD(0x0428, 0x0114, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_DA0__TPSMP_HDATA_14 \ ++ IOMUX_PAD(0x0428, 0x0114, 6, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_DA0__SRC_BT_CFG_0 \ ++ IOMUX_PAD(0x0428, 0x0114, 7, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_EIM_DA1__WEIM_WEIM_DA_A_1 \ ++ IOMUX_PAD(0x042C, 0x0118, 0, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_DA1__IPU1_DISP1_DAT_8 \ ++ IOMUX_PAD(0x042C, 0x0118, 1, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_DA1__IPU2_CSI1_D_8 \ ++ IOMUX_PAD(0x042C, 0x0118, 2, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_DA1__MIPI_CORE_DPHY_TEST_OUT_3 \ ++ IOMUX_PAD(0x042C, 0x0118, 3, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_DA1__ANATOP_USBPHY1_TSTI_TX_LS_MODE \ ++ IOMUX_PAD(0x042C, 0x0118, 4, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_DA1__GPIO_3_1 \ ++ IOMUX_PAD(0x042C, 0x0118, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_DA1__TPSMP_HDATA_15 \ ++ IOMUX_PAD(0x042C, 0x0118, 6, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_DA1__SRC_BT_CFG_1 \ ++ IOMUX_PAD(0x042C, 0x0118, 7, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_EIM_DA2__WEIM_WEIM_DA_A_2 \ ++ IOMUX_PAD(0x0430, 0x011C, 0, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_DA2__IPU1_DISP1_DAT_7 \ ++ IOMUX_PAD(0x0430, 0x011C, 1, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_DA2__IPU2_CSI1_D_7 \ ++ IOMUX_PAD(0x0430, 0x011C, 2, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_DA2__MIPI_CORE_DPHY_TEST_OUT_4 \ ++ IOMUX_PAD(0x0430, 0x011C, 3, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_DA2__ANATOP_USBPHY1_TSTI_TX_HS_MODE \ ++ IOMUX_PAD(0x0430, 0x011C, 4, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_DA2__GPIO_3_2 \ ++ IOMUX_PAD(0x0430, 0x011C, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_DA2__TPSMP_HDATA_16 \ ++ IOMUX_PAD(0x0430, 0x011C, 6, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_DA2__SRC_BT_CFG_2 \ ++ IOMUX_PAD(0x0430, 0x011C, 7, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_EIM_DA3__WEIM_WEIM_DA_A_3 \ ++ IOMUX_PAD(0x0434, 0x0120, 0, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_DA3__IPU1_DISP1_DAT_6 \ ++ IOMUX_PAD(0x0434, 0x0120, 1, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_DA3__IPU2_CSI1_D_6 \ ++ IOMUX_PAD(0x0434, 0x0120, 2, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_DA3__MIPI_CORE_DPHY_TEST_OUT_5 \ ++ IOMUX_PAD(0x0434, 0x0120, 3, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_DA3__ANATOP_USBPHY1_TSTI_TX_HIZ \ ++ IOMUX_PAD(0x0434, 0x0120, 4, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_DA3__GPIO_3_3 \ ++ IOMUX_PAD(0x0434, 0x0120, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_DA3__TPSMP_HDATA_17 \ ++ IOMUX_PAD(0x0434, 0x0120, 6, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_DA3__SRC_BT_CFG_3 \ ++ IOMUX_PAD(0x0434, 0x0120, 7, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_EIM_DA4__WEIM_WEIM_DA_A_4 \ ++ IOMUX_PAD(0x0438, 0x0124, 0, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_DA4__IPU1_DISP1_DAT_5 \ ++ IOMUX_PAD(0x0438, 0x0124, 1, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_DA4__IPU2_CSI1_D_5 \ ++ IOMUX_PAD(0x0438, 0x0124, 2, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_DA4__MIPI_CORE_DPHY_TEST_OUT_6 \ ++ IOMUX_PAD(0x0438, 0x0124, 3, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_DA4__ANATOP_USBPHY1_TSTI_TX_EN \ ++ IOMUX_PAD(0x0438, 0x0124, 4, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_DA4__GPIO_3_4 \ ++ IOMUX_PAD(0x0438, 0x0124, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_DA4__TPSMP_HDATA_18 \ ++ IOMUX_PAD(0x0438, 0x0124, 6, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_DA4__SRC_BT_CFG_4 \ ++ IOMUX_PAD(0x0438, 0x0124, 7, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_EIM_DA5__WEIM_WEIM_DA_A_5 \ ++ IOMUX_PAD(0x043C, 0x0128, 0, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_DA5__IPU1_DISP1_DAT_4 \ ++ IOMUX_PAD(0x043C, 0x0128, 1, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_DA5__IPU2_CSI1_D_4 \ ++ IOMUX_PAD(0x043C, 0x0128, 2, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_DA5__MIPI_CORE_DPHY_TEST_OUT_7 \ ++ IOMUX_PAD(0x043C, 0x0128, 3, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_DA5__ANATOP_USBPHY1_TSTI_TX_DP \ ++ IOMUX_PAD(0x043C, 0x0128, 4, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_DA5__GPIO_3_5 \ ++ IOMUX_PAD(0x043C, 0x0128, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_DA5__TPSMP_HDATA_19 \ ++ IOMUX_PAD(0x043C, 0x0128, 6, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_DA5__SRC_BT_CFG_5 \ ++ IOMUX_PAD(0x043C, 0x0128, 7, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_EIM_DA6__WEIM_WEIM_DA_A_6 \ ++ IOMUX_PAD(0x0440, 0x012C, 0, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_DA6__IPU1_DISP1_DAT_3 \ ++ IOMUX_PAD(0x0440, 0x012C, 1, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_DA6__IPU2_CSI1_D_3 \ ++ IOMUX_PAD(0x0440, 0x012C, 2, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_DA6__MIPI_CORE_DPHY_TEST_OUT_8 \ ++ IOMUX_PAD(0x0440, 0x012C, 3, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_DA6__ANATOP_USBPHY1_TSTI_TX_DN \ ++ IOMUX_PAD(0x0440, 0x012C, 4, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_DA6__GPIO_3_6 \ ++ IOMUX_PAD(0x0440, 0x012C, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_DA6__TPSMP_HDATA_20 \ ++ IOMUX_PAD(0x0440, 0x012C, 6, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_DA6__SRC_BT_CFG_6 \ ++ IOMUX_PAD(0x0440, 0x012C, 7, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_EIM_DA7__WEIM_WEIM_DA_A_7 \ ++ IOMUX_PAD(0x0444, 0x0130, 0, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_DA7__IPU1_DISP1_DAT_2 \ ++ IOMUX_PAD(0x0444, 0x0130, 1, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_DA7__IPU2_CSI1_D_2 \ ++ IOMUX_PAD(0x0444, 0x0130, 2, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_DA7__MIPI_CORE_DPHY_TEST_OUT_9 \ ++ IOMUX_PAD(0x0444, 0x0130, 3, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_DA7__GPIO_3_7 \ ++ IOMUX_PAD(0x0444, 0x0130, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_DA7__TPSMP_HDATA_21 \ ++ IOMUX_PAD(0x0444, 0x0130, 6, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_DA7__SRC_BT_CFG_7 \ ++ IOMUX_PAD(0x0444, 0x0130, 7, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_EIM_DA8__WEIM_WEIM_DA_A_8 \ ++ IOMUX_PAD(0x0448, 0x0134, 0, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_DA8__IPU1_DISP1_DAT_1 \ ++ IOMUX_PAD(0x0448, 0x0134, 1, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_DA8__IPU2_CSI1_D_1 \ ++ IOMUX_PAD(0x0448, 0x0134, 2, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_DA8__MIPI_CORE_DPHY_TEST_OUT_10 \ ++ IOMUX_PAD(0x0448, 0x0134, 3, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_DA8__GPIO_3_8 \ ++ IOMUX_PAD(0x0448, 0x0134, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_DA8__TPSMP_HDATA_22 \ ++ IOMUX_PAD(0x0448, 0x0134, 6, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_DA8__SRC_BT_CFG_8 \ ++ IOMUX_PAD(0x0448, 0x0134, 7, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_EIM_DA9__WEIM_WEIM_DA_A_9 \ ++ IOMUX_PAD(0x044C, 0x0138, 0, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_DA9__IPU1_DISP1_DAT_0 \ ++ IOMUX_PAD(0x044C, 0x0138, 1, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_DA9__IPU2_CSI1_D_0 \ ++ IOMUX_PAD(0x044C, 0x0138, 2, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_DA9__MIPI_CORE_DPHY_TEST_OUT_11 \ ++ IOMUX_PAD(0x044C, 0x0138, 3, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_DA9__GPIO_3_9 \ ++ IOMUX_PAD(0x044C, 0x0138, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_DA9__TPSMP_HDATA_23 \ ++ IOMUX_PAD(0x044C, 0x0138, 6, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_DA9__SRC_BT_CFG_9 \ ++ IOMUX_PAD(0x044C, 0x0138, 7, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_EIM_DA10__WEIM_WEIM_DA_A_10 \ ++ IOMUX_PAD(0x0450, 0x013C, 0, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_DA10__IPU1_DI1_PIN15 \ ++ IOMUX_PAD(0x0450, 0x013C, 1, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_DA10__IPU2_CSI1_DATA_EN \ ++ IOMUX_PAD(0x0450, 0x013C, 2, 0x08D8, 1, 0) ++#define _MX6Q_PAD_EIM_DA10__MIPI_CORE_DPHY_TEST_OUT_12 \ ++ IOMUX_PAD(0x0450, 0x013C, 3, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_DA10__GPIO_3_10 \ ++ IOMUX_PAD(0x0450, 0x013C, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_DA10__TPSMP_HDATA_24 \ ++ IOMUX_PAD(0x0450, 0x013C, 6, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_DA10__SRC_BT_CFG_10 \ ++ IOMUX_PAD(0x0450, 0x013C, 7, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_EIM_DA11__WEIM_WEIM_DA_A_11 \ ++ IOMUX_PAD(0x0454, 0x0140, 0, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_DA11__IPU1_DI1_PIN2 \ ++ IOMUX_PAD(0x0454, 0x0140, 1, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_DA11__IPU2_CSI1_HSYNC \ ++ IOMUX_PAD(0x0454, 0x0140, 2, 0x08DC, 1, 0) ++#define _MX6Q_PAD_EIM_DA11__MIPI_CORE_DPHY_TEST_OUT_13 \ ++ IOMUX_PAD(0x0454, 0x0140, 3, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_DA11__SDMA_DEBUG_EVT_CHN_LINES_6 \ ++ IOMUX_PAD(0x0454, 0x0140, 4, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_DA11__GPIO_3_11 \ ++ IOMUX_PAD(0x0454, 0x0140, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_DA11__TPSMP_HDATA_25 \ ++ IOMUX_PAD(0x0454, 0x0140, 6, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_DA11__SRC_BT_CFG_11 \ ++ IOMUX_PAD(0x0454, 0x0140, 7, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_EIM_DA12__WEIM_WEIM_DA_A_12 \ ++ IOMUX_PAD(0x0458, 0x0144, 0, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_DA12__IPU1_DI1_PIN3 \ ++ IOMUX_PAD(0x0458, 0x0144, 1, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_DA12__IPU2_CSI1_VSYNC \ ++ IOMUX_PAD(0x0458, 0x0144, 2, 0x08E4, 1, 0) ++#define _MX6Q_PAD_EIM_DA12__MIPI_CORE_DPHY_TEST_OUT_14 \ ++ IOMUX_PAD(0x0458, 0x0144, 3, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_DA12__SDMA_DEBUG_EVT_CHN_LINES_3 \ ++ IOMUX_PAD(0x0458, 0x0144, 4, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_DA12__GPIO_3_12 \ ++ IOMUX_PAD(0x0458, 0x0144, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_DA12__TPSMP_HDATA_26 \ ++ IOMUX_PAD(0x0458, 0x0144, 6, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_DA12__SRC_BT_CFG_12 \ ++ IOMUX_PAD(0x0458, 0x0144, 7, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_EIM_DA13__WEIM_WEIM_DA_A_13 \ ++ IOMUX_PAD(0x045C, 0x0148, 0, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_DA13__IPU1_DI1_D0_CS \ ++ IOMUX_PAD(0x045C, 0x0148, 1, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_DA13__CCM_DI1_EXT_CLK \ ++ IOMUX_PAD(0x045C, 0x0148, 2, 0x07EC, 1, 0) ++#define _MX6Q_PAD_EIM_DA13__MIPI_CORE_DPHY_TEST_OUT_15 \ ++ IOMUX_PAD(0x045C, 0x0148, 3, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_DA13__SDMA_DEBUG_EVT_CHN_LINES_4 \ ++ IOMUX_PAD(0x045C, 0x0148, 4, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_DA13__GPIO_3_13 \ ++ IOMUX_PAD(0x045C, 0x0148, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_DA13__TPSMP_HDATA_27 \ ++ IOMUX_PAD(0x045C, 0x0148, 6, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_DA13__SRC_BT_CFG_13 \ ++ IOMUX_PAD(0x045C, 0x0148, 7, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_EIM_DA14__WEIM_WEIM_DA_A_14 \ ++ IOMUX_PAD(0x0460, 0x014C, 0, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_DA14__IPU1_DI1_D1_CS \ ++ IOMUX_PAD(0x0460, 0x014C, 1, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_DA14__CCM_DI0_EXT_CLK \ ++ IOMUX_PAD(0x0460, 0x014C, 2, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_DA14__MIPI_CORE_DPHY_TEST_OUT_16 \ ++ IOMUX_PAD(0x0460, 0x014C, 3, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_DA14__SDMA_DEBUG_EVT_CHN_LINES_5 \ ++ IOMUX_PAD(0x0460, 0x014C, 4, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_DA14__GPIO_3_14 \ ++ IOMUX_PAD(0x0460, 0x014C, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_DA14__TPSMP_HDATA_28 \ ++ IOMUX_PAD(0x0460, 0x014C, 6, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_DA14__SRC_BT_CFG_14 \ ++ IOMUX_PAD(0x0460, 0x014C, 7, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_EIM_DA15__WEIM_WEIM_DA_A_15 \ ++ IOMUX_PAD(0x0464, 0x0150, 0, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_DA15__IPU1_DI1_PIN1 \ ++ IOMUX_PAD(0x0464, 0x0150, 1, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_DA15__IPU1_DI1_PIN4 \ ++ IOMUX_PAD(0x0464, 0x0150, 2, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_DA15__MIPI_CORE_DPHY_TEST_OUT_17 \ ++ IOMUX_PAD(0x0464, 0x0150, 3, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_DA15__GPIO_3_15 \ ++ IOMUX_PAD(0x0464, 0x0150, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_DA15__TPSMP_HDATA_29 \ ++ IOMUX_PAD(0x0464, 0x0150, 6, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_DA15__SRC_BT_CFG_15 \ ++ IOMUX_PAD(0x0464, 0x0150, 7, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_EIM_WAIT__WEIM_WEIM_WAIT \ ++ IOMUX_PAD(0x0468, 0x0154, 0, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_WAIT__WEIM_WEIM_DTACK_B \ ++ IOMUX_PAD(0x0468, 0x0154, 1, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_WAIT__GPIO_5_0 \ ++ IOMUX_PAD(0x0468, 0x0154, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_WAIT__TPSMP_HDATA_30 \ ++ IOMUX_PAD(0x0468, 0x0154, 6, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_WAIT__SRC_BT_CFG_25 \ ++ IOMUX_PAD(0x0468, 0x0154, 7, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_EIM_BCLK__WEIM_WEIM_BCLK \ ++ IOMUX_PAD(0x046C, 0x0158, 0, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_BCLK__IPU1_DI1_PIN16 \ ++ IOMUX_PAD(0x046C, 0x0158, 1, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_BCLK__GPIO_6_31 \ ++ IOMUX_PAD(0x046C, 0x0158, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_EIM_BCLK__TPSMP_HDATA_31 \ ++ IOMUX_PAD(0x046C, 0x0158, 6, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK \ ++ IOMUX_PAD(0x0470, 0x015C, 0, 0x0000, 0, 0) ++#define _MX6Q_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK \ ++ IOMUX_PAD(0x0470, 0x015C, 1, 0x0000, 0, 0) ++#define _MX6Q_PAD_DI0_DISP_CLK__MIPI_CORE_DPHY_TEST_OUT_28 \ ++ IOMUX_PAD(0x0470, 0x015C, 3, 0x0000, 0, 0) ++#define _MX6Q_PAD_DI0_DISP_CLK__SDMA_DEBUG_CORE_STATE_0 \ ++ IOMUX_PAD(0x0470, 0x015C, 4, 0x0000, 0, 0) ++#define _MX6Q_PAD_DI0_DISP_CLK__GPIO_4_16 \ ++ IOMUX_PAD(0x0470, 0x015C, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_DI0_DISP_CLK__MMDC_MMDC_DEBUG_0 \ ++ IOMUX_PAD(0x0470, 0x015C, 6, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_DI0_PIN15__IPU1_DI0_PIN15 \ ++ IOMUX_PAD(0x0474, 0x0160, 0, 0x0000, 0, 0) ++#define _MX6Q_PAD_DI0_PIN15__IPU2_DI0_PIN15 \ ++ IOMUX_PAD(0x0474, 0x0160, 1, 0x0000, 0, 0) ++#define _MX6Q_PAD_DI0_PIN15__AUDMUX_AUD6_TXC \ ++ IOMUX_PAD(0x0474, 0x0160, 2, 0x0000, 0, 0) ++#define _MX6Q_PAD_DI0_PIN15__MIPI_CORE_DPHY_TEST_OUT_29 \ ++ IOMUX_PAD(0x0474, 0x0160, 3, 0x0000, 0, 0) ++#define _MX6Q_PAD_DI0_PIN15__SDMA_DEBUG_CORE_STATE_1 \ ++ IOMUX_PAD(0x0474, 0x0160, 4, 0x0000, 0, 0) ++#define _MX6Q_PAD_DI0_PIN15__GPIO_4_17 \ ++ IOMUX_PAD(0x0474, 0x0160, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_DI0_PIN15__MMDC_MMDC_DEBUG_1 \ ++ IOMUX_PAD(0x0474, 0x0160, 6, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_DI0_PIN2__IPU1_DI0_PIN2 \ ++ IOMUX_PAD(0x0478, 0x0164, 0, 0x0000, 0, 0) ++#define _MX6Q_PAD_DI0_PIN2__IPU2_DI0_PIN2 \ ++ IOMUX_PAD(0x0478, 0x0164, 1, 0x0000, 0, 0) ++#define _MX6Q_PAD_DI0_PIN2__AUDMUX_AUD6_TXD \ ++ IOMUX_PAD(0x0478, 0x0164, 2, 0x0000, 0, 0) ++#define _MX6Q_PAD_DI0_PIN2__MIPI_CORE_DPHY_TEST_OUT_30 \ ++ IOMUX_PAD(0x0478, 0x0164, 3, 0x0000, 0, 0) ++#define _MX6Q_PAD_DI0_PIN2__SDMA_DEBUG_CORE_STATE_2 \ ++ IOMUX_PAD(0x0478, 0x0164, 4, 0x0000, 0, 0) ++#define _MX6Q_PAD_DI0_PIN2__GPIO_4_18 \ ++ IOMUX_PAD(0x0478, 0x0164, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_DI0_PIN2__MMDC_MMDC_DEBUG_2 \ ++ IOMUX_PAD(0x0478, 0x0164, 6, 0x0000, 0, 0) ++#define _MX6Q_PAD_DI0_PIN2__PL301_MX6QPER1_HADDR_9 \ ++ IOMUX_PAD(0x0478, 0x0164, 7, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_DI0_PIN3__IPU1_DI0_PIN3 \ ++ IOMUX_PAD(0x047C, 0x0168, 0, 0x0000, 0, 0) ++#define _MX6Q_PAD_DI0_PIN3__IPU2_DI0_PIN3 \ ++ IOMUX_PAD(0x047C, 0x0168, 1, 0x0000, 0, 0) ++#define _MX6Q_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS \ ++ IOMUX_PAD(0x047C, 0x0168, 2, 0x0000, 0, 0) ++#define _MX6Q_PAD_DI0_PIN3__MIPI_CORE_DPHY_TEST_OUT_31 \ ++ IOMUX_PAD(0x047C, 0x0168, 3, 0x0000, 0, 0) ++#define _MX6Q_PAD_DI0_PIN3__SDMA_DEBUG_CORE_STATE_3 \ ++ IOMUX_PAD(0x047C, 0x0168, 4, 0x0000, 0, 0) ++#define _MX6Q_PAD_DI0_PIN3__GPIO_4_19 \ ++ IOMUX_PAD(0x047C, 0x0168, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_DI0_PIN3__MMDC_MMDC_DEBUG_3 \ ++ IOMUX_PAD(0x047C, 0x0168, 6, 0x0000, 0, 0) ++#define _MX6Q_PAD_DI0_PIN3__PL301_MX6QPER1_HADDR_10 \ ++ IOMUX_PAD(0x047C, 0x0168, 7, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_DI0_PIN4__IPU1_DI0_PIN4 \ ++ IOMUX_PAD(0x0480, 0x016C, 0, 0x0000, 0, 0) ++#define _MX6Q_PAD_DI0_PIN4__IPU2_DI0_PIN4 \ ++ IOMUX_PAD(0x0480, 0x016C, 1, 0x0000, 0, 0) ++#define _MX6Q_PAD_DI0_PIN4__AUDMUX_AUD6_RXD \ ++ IOMUX_PAD(0x0480, 0x016C, 2, 0x0000, 0, 0) ++#define _MX6Q_PAD_DI0_PIN4__USDHC1_WP \ ++ IOMUX_PAD(0x0480, 0x016C, 3, 0x094C, 0, 0) ++#define _MX6Q_PAD_DI0_PIN4__SDMA_DEBUG_YIELD \ ++ IOMUX_PAD(0x0480, 0x016C, 4, 0x0000, 0, 0) ++#define _MX6Q_PAD_DI0_PIN4__GPIO_4_20 \ ++ IOMUX_PAD(0x0480, 0x016C, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_DI0_PIN4__MMDC_MMDC_DEBUG_4 \ ++ IOMUX_PAD(0x0480, 0x016C, 6, 0x0000, 0, 0) ++#define _MX6Q_PAD_DI0_PIN4__PL301_MX6QPER1_HADDR_11 \ ++ IOMUX_PAD(0x0480, 0x016C, 7, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0 \ ++ IOMUX_PAD(0x0484, 0x0170, 0, 0x0000, 0, 0) ++#define _MX6Q_PAD_DISP0_DAT0__IPU2_DISP0_DAT_0 \ ++ IOMUX_PAD(0x0484, 0x0170, 1, 0x0000, 0, 0) ++#define _MX6Q_PAD_DISP0_DAT0__ECSPI3_SCLK \ ++ IOMUX_PAD(0x0484, 0x0170, 2, 0x0000, 0, 0) ++#define _MX6Q_PAD_DISP0_DAT0__USDHC1_USDHC_DEBUG_0 \ ++ IOMUX_PAD(0x0484, 0x0170, 3, 0x0000, 0, 0) ++#define _MX6Q_PAD_DISP0_DAT0__SDMA_DEBUG_CORE_RUN \ ++ IOMUX_PAD(0x0484, 0x0170, 4, 0x0000, 0, 0) ++#define _MX6Q_PAD_DISP0_DAT0__GPIO_4_21 \ ++ IOMUX_PAD(0x0484, 0x0170, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_DISP0_DAT0__MMDC_MMDC_DEBUG_5 \ ++ IOMUX_PAD(0x0484, 0x0170, 6, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1 \ ++ IOMUX_PAD(0x0488, 0x0174, 0, 0x0000, 0, 0) ++#define _MX6Q_PAD_DISP0_DAT1__IPU2_DISP0_DAT_1 \ ++ IOMUX_PAD(0x0488, 0x0174, 1, 0x0000, 0, 0) ++#define _MX6Q_PAD_DISP0_DAT1__ECSPI3_MOSI \ ++ IOMUX_PAD(0x0488, 0x0174, 2, 0x0000, 0, 0) ++#define _MX6Q_PAD_DISP0_DAT1__USDHC1_USDHC_DEBUG_1 \ ++ IOMUX_PAD(0x0488, 0x0174, 3, 0x0000, 0, 0) ++#define _MX6Q_PAD_DISP0_DAT1__SDMA_DEBUG_EVENT_CHANNEL_SEL \ ++ IOMUX_PAD(0x0488, 0x0174, 4, 0x0000, 0, 0) ++#define _MX6Q_PAD_DISP0_DAT1__GPIO_4_22 \ ++ IOMUX_PAD(0x0488, 0x0174, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_DISP0_DAT1__MMDC_MMDC_DEBUG_6 \ ++ IOMUX_PAD(0x0488, 0x0174, 6, 0x0000, 0, 0) ++#define _MX6Q_PAD_DISP0_DAT1__PL301_MX6QPER1_HADDR_12 \ ++ IOMUX_PAD(0x0488, 0x0174, 7, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2 \ ++ IOMUX_PAD(0x048C, 0x0178, 0, 0x0000, 0, 0) ++#define _MX6Q_PAD_DISP0_DAT2__IPU2_DISP0_DAT_2 \ ++ IOMUX_PAD(0x048C, 0x0178, 1, 0x0000, 0, 0) ++#define _MX6Q_PAD_DISP0_DAT2__ECSPI3_MISO \ ++ IOMUX_PAD(0x048C, 0x0178, 2, 0x0000, 0, 0) ++#define _MX6Q_PAD_DISP0_DAT2__USDHC1_USDHC_DEBUG_2 \ ++ IOMUX_PAD(0x048C, 0x0178, 3, 0x0000, 0, 0) ++#define _MX6Q_PAD_DISP0_DAT2__SDMA_DEBUG_MODE \ ++ IOMUX_PAD(0x048C, 0x0178, 4, 0x0000, 0, 0) ++#define _MX6Q_PAD_DISP0_DAT2__GPIO_4_23 \ ++ IOMUX_PAD(0x048C, 0x0178, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_DISP0_DAT2__MMDC_MMDC_DEBUG_7 \ ++ IOMUX_PAD(0x048C, 0x0178, 6, 0x0000, 0, 0) ++#define _MX6Q_PAD_DISP0_DAT2__PL301_MX6QPER1_HADDR_13 \ ++ IOMUX_PAD(0x048C, 0x0178, 7, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3 \ ++ IOMUX_PAD(0x0490, 0x017C, 0, 0x0000, 0, 0) ++#define _MX6Q_PAD_DISP0_DAT3__IPU2_DISP0_DAT_3 \ ++ IOMUX_PAD(0x0490, 0x017C, 1, 0x0000, 0, 0) ++#define _MX6Q_PAD_DISP0_DAT3__ECSPI3_SS0 \ ++ IOMUX_PAD(0x0490, 0x017C, 2, 0x0000, 0, 0) ++#define _MX6Q_PAD_DISP0_DAT3__USDHC1_USDHC_DEBUG_3 \ ++ IOMUX_PAD(0x0490, 0x017C, 3, 0x0000, 0, 0) ++#define _MX6Q_PAD_DISP0_DAT3__SDMA_DEBUG_BUS_ERROR \ ++ IOMUX_PAD(0x0490, 0x017C, 4, 0x0000, 0, 0) ++#define _MX6Q_PAD_DISP0_DAT3__GPIO_4_24 \ ++ IOMUX_PAD(0x0490, 0x017C, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_DISP0_DAT3__MMDC_MMDC_DEBUG_8 \ ++ IOMUX_PAD(0x0490, 0x017C, 6, 0x0000, 0, 0) ++#define _MX6Q_PAD_DISP0_DAT3__PL301_MX6QPER1_HADDR_14 \ ++ IOMUX_PAD(0x0490, 0x017C, 7, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4 \ ++ IOMUX_PAD(0x0494, 0x0180, 0, 0x0000, 0, 0) ++#define _MX6Q_PAD_DISP0_DAT4__IPU2_DISP0_DAT_4 \ ++ IOMUX_PAD(0x0494, 0x0180, 1, 0x0000, 0, 0) ++#define _MX6Q_PAD_DISP0_DAT4__ECSPI3_SS1 \ ++ IOMUX_PAD(0x0494, 0x0180, 2, 0x0000, 0, 0) ++#define _MX6Q_PAD_DISP0_DAT4__USDHC1_USDHC_DEBUG_4 \ ++ IOMUX_PAD(0x0494, 0x0180, 3, 0x0000, 0, 0) ++#define _MX6Q_PAD_DISP0_DAT4__SDMA_DEBUG_BUS_RWB \ ++ IOMUX_PAD(0x0494, 0x0180, 4, 0x0000, 0, 0) ++#define _MX6Q_PAD_DISP0_DAT4__GPIO_4_25 \ ++ IOMUX_PAD(0x0494, 0x0180, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_DISP0_DAT4__MMDC_MMDC_DEBUG_9 \ ++ IOMUX_PAD(0x0494, 0x0180, 6, 0x0000, 0, 0) ++#define _MX6Q_PAD_DISP0_DAT4__PL301_MX6QPER1_HADDR_15 \ ++ IOMUX_PAD(0x0494, 0x0180, 7, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5 \ ++ IOMUX_PAD(0x0498, 0x0184, 0, 0x0000, 0, 0) ++#define _MX6Q_PAD_DISP0_DAT5__IPU2_DISP0_DAT_5 \ ++ IOMUX_PAD(0x0498, 0x0184, 1, 0x0000, 0, 0) ++#define _MX6Q_PAD_DISP0_DAT5__ECSPI3_SS2 \ ++ IOMUX_PAD(0x0498, 0x0184, 2, 0x0000, 0, 0) ++#define _MX6Q_PAD_DISP0_DAT5__AUDMUX_AUD6_RXFS \ ++ IOMUX_PAD(0x0498, 0x0184, 3, 0x0000, 0, 0) ++#define _MX6Q_PAD_DISP0_DAT5__SDMA_DEBUG_MATCHED_DMBUS \ ++ IOMUX_PAD(0x0498, 0x0184, 4, 0x0000, 0, 0) ++#define _MX6Q_PAD_DISP0_DAT5__GPIO_4_26 \ ++ IOMUX_PAD(0x0498, 0x0184, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_DISP0_DAT5__MMDC_MMDC_DEBUG_10 \ ++ IOMUX_PAD(0x0498, 0x0184, 6, 0x0000, 0, 0) ++#define _MX6Q_PAD_DISP0_DAT5__PL301_MX6QPER1_HADDR_16 \ ++ IOMUX_PAD(0x0498, 0x0184, 7, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6 \ ++ IOMUX_PAD(0x049C, 0x0188, 0, 0x0000, 0, 0) ++#define _MX6Q_PAD_DISP0_DAT6__IPU2_DISP0_DAT_6 \ ++ IOMUX_PAD(0x049C, 0x0188, 1, 0x0000, 0, 0) ++#define _MX6Q_PAD_DISP0_DAT6__ECSPI3_SS3 \ ++ IOMUX_PAD(0x049C, 0x0188, 2, 0x0000, 0, 0) ++#define _MX6Q_PAD_DISP0_DAT6__AUDMUX_AUD6_RXC \ ++ IOMUX_PAD(0x049C, 0x0188, 3, 0x0000, 0, 0) ++#define _MX6Q_PAD_DISP0_DAT6__SDMA_DEBUG_RTBUFFER_WRITE \ ++ IOMUX_PAD(0x049C, 0x0188, 4, 0x0000, 0, 0) ++#define _MX6Q_PAD_DISP0_DAT6__GPIO_4_27 \ ++ IOMUX_PAD(0x049C, 0x0188, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_DISP0_DAT6__MMDC_MMDC_DEBUG_11 \ ++ IOMUX_PAD(0x049C, 0x0188, 6, 0x0000, 0, 0) ++#define _MX6Q_PAD_DISP0_DAT6__PL301_MX6QPER1_HADDR_17 \ ++ IOMUX_PAD(0x049C, 0x0188, 7, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7 \ ++ IOMUX_PAD(0x04A0, 0x018C, 0, 0x0000, 0, 0) ++#define _MX6Q_PAD_DISP0_DAT7__IPU2_DISP0_DAT_7 \ ++ IOMUX_PAD(0x04A0, 0x018C, 1, 0x0000, 0, 0) ++#define _MX6Q_PAD_DISP0_DAT7__ECSPI3_RDY \ ++ IOMUX_PAD(0x04A0, 0x018C, 2, 0x0000, 0, 0) ++#define _MX6Q_PAD_DISP0_DAT7__USDHC1_USDHC_DEBUG_5 \ ++ IOMUX_PAD(0x04A0, 0x018C, 3, 0x0000, 0, 0) ++#define _MX6Q_PAD_DISP0_DAT7__SDMA_DEBUG_EVENT_CHANNEL_0 \ ++ IOMUX_PAD(0x04A0, 0x018C, 4, 0x0000, 0, 0) ++#define _MX6Q_PAD_DISP0_DAT7__GPIO_4_28 \ ++ IOMUX_PAD(0x04A0, 0x018C, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_DISP0_DAT7__MMDC_MMDC_DEBUG_12 \ ++ IOMUX_PAD(0x04A0, 0x018C, 6, 0x0000, 0, 0) ++#define _MX6Q_PAD_DISP0_DAT7__PL301_MX6QPER1_HADDR_18 \ ++ IOMUX_PAD(0x04A0, 0x018C, 7, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8 \ ++ IOMUX_PAD(0x04A4, 0x0190, 0, 0x0000, 0, 0) ++#define _MX6Q_PAD_DISP0_DAT8__IPU2_DISP0_DAT_8 \ ++ IOMUX_PAD(0x04A4, 0x0190, 1, 0x0000, 0, 0) ++#define _MX6Q_PAD_DISP0_DAT8__PWM1_PWMO \ ++ IOMUX_PAD(0x04A4, 0x0190, 2, 0x0000, 0, 0) ++#define _MX6Q_PAD_DISP0_DAT8__WDOG1_WDOG_B \ ++ IOMUX_PAD(0x04A4, 0x0190, 3, 0x0000, 0, 0) ++#define _MX6Q_PAD_DISP0_DAT8__SDMA_DEBUG_EVENT_CHANNEL_1 \ ++ IOMUX_PAD(0x04A4, 0x0190, 4, 0x0000, 0, 0) ++#define _MX6Q_PAD_DISP0_DAT8__GPIO_4_29 \ ++ IOMUX_PAD(0x04A4, 0x0190, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_DISP0_DAT8__MMDC_MMDC_DEBUG_13 \ ++ IOMUX_PAD(0x04A4, 0x0190, 6, 0x0000, 0, 0) ++#define _MX6Q_PAD_DISP0_DAT8__PL301_MX6QPER1_HADDR_19 \ ++ IOMUX_PAD(0x04A4, 0x0190, 7, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9 \ ++ IOMUX_PAD(0x04A8, 0x0194, 0, 0x0000, 0, 0) ++#define _MX6Q_PAD_DISP0_DAT9__IPU2_DISP0_DAT_9 \ ++ IOMUX_PAD(0x04A8, 0x0194, 1, 0x0000, 0, 0) ++#define _MX6Q_PAD_DISP0_DAT9__PWM2_PWMO \ ++ IOMUX_PAD(0x04A8, 0x0194, 2, 0x0000, 0, 0) ++#define _MX6Q_PAD_DISP0_DAT9__WDOG2_WDOG_B \ ++ IOMUX_PAD(0x04A8, 0x0194, 3, 0x0000, 0, 0) ++#define _MX6Q_PAD_DISP0_DAT9__SDMA_DEBUG_EVENT_CHANNEL_2 \ ++ IOMUX_PAD(0x04A8, 0x0194, 4, 0x0000, 0, 0) ++#define _MX6Q_PAD_DISP0_DAT9__GPIO_4_30 \ ++ IOMUX_PAD(0x04A8, 0x0194, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_DISP0_DAT9__MMDC_MMDC_DEBUG_14 \ ++ IOMUX_PAD(0x04A8, 0x0194, 6, 0x0000, 0, 0) ++#define _MX6Q_PAD_DISP0_DAT9__PL301_MX6QPER1_HADDR_20 \ ++ IOMUX_PAD(0x04A8, 0x0194, 7, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10 \ ++ IOMUX_PAD(0x04AC, 0x0198, 0, 0x0000, 0, 0) ++#define _MX6Q_PAD_DISP0_DAT10__IPU2_DISP0_DAT_10 \ ++ IOMUX_PAD(0x04AC, 0x0198, 1, 0x0000, 0, 0) ++#define _MX6Q_PAD_DISP0_DAT10__USDHC1_USDHC_DEBUG_6 \ ++ IOMUX_PAD(0x04AC, 0x0198, 3, 0x0000, 0, 0) ++#define _MX6Q_PAD_DISP0_DAT10__SDMA_DEBUG_EVENT_CHANNEL_3 \ ++ IOMUX_PAD(0x04AC, 0x0198, 4, 0x0000, 0, 0) ++#define _MX6Q_PAD_DISP0_DAT10__GPIO_4_31 \ ++ IOMUX_PAD(0x04AC, 0x0198, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_DISP0_DAT10__MMDC_MMDC_DEBUG_15 \ ++ IOMUX_PAD(0x04AC, 0x0198, 6, 0x0000, 0, 0) ++#define _MX6Q_PAD_DISP0_DAT10__PL301_MX6QPER1_HADDR_21 \ ++ IOMUX_PAD(0x04AC, 0x0198, 7, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11 \ ++ IOMUX_PAD(0x04B0, 0x019C, 0, 0x0000, 0, 0) ++#define _MX6Q_PAD_DISP0_DAT11__IPU2_DISP0_DAT_11 \ ++ IOMUX_PAD(0x04B0, 0x019C, 1, 0x0000, 0, 0) ++#define _MX6Q_PAD_DISP0_DAT11__USDHC1_USDHC_DEBUG_7 \ ++ IOMUX_PAD(0x04B0, 0x019C, 3, 0x0000, 0, 0) ++#define _MX6Q_PAD_DISP0_DAT11__SDMA_DEBUG_EVENT_CHANNEL_4 \ ++ IOMUX_PAD(0x04B0, 0x019C, 4, 0x0000, 0, 0) ++#define _MX6Q_PAD_DISP0_DAT11__GPIO_5_5 \ ++ IOMUX_PAD(0x04B0, 0x019C, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_DISP0_DAT11__MMDC_MMDC_DEBUG_16 \ ++ IOMUX_PAD(0x04B0, 0x019C, 6, 0x0000, 0, 0) ++#define _MX6Q_PAD_DISP0_DAT11__PL301_MX6QPER1_HADDR_22 \ ++ IOMUX_PAD(0x04B0, 0x019C, 7, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12 \ ++ IOMUX_PAD(0x04B4, 0x01A0, 0, 0x0000, 0, 0) ++#define _MX6Q_PAD_DISP0_DAT12__IPU2_DISP0_DAT_12 \ ++ IOMUX_PAD(0x04B4, 0x01A0, 1, 0x0000, 0, 0) ++#define _MX6Q_PAD_DISP0_DAT12__SDMA_DEBUG_EVENT_CHANNEL_5 \ ++ IOMUX_PAD(0x04B4, 0x01A0, 4, 0x0000, 0, 0) ++#define _MX6Q_PAD_DISP0_DAT12__GPIO_5_6 \ ++ IOMUX_PAD(0x04B4, 0x01A0, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_DISP0_DAT12__MMDC_MMDC_DEBUG_17 \ ++ IOMUX_PAD(0x04B4, 0x01A0, 6, 0x0000, 0, 0) ++#define _MX6Q_PAD_DISP0_DAT12__PL301_MX6QPER1_HADDR_23 \ ++ IOMUX_PAD(0x04B4, 0x01A0, 7, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13 \ ++ IOMUX_PAD(0x04B8, 0x01A4, 0, 0x0000, 0, 0) ++#define _MX6Q_PAD_DISP0_DAT13__IPU2_DISP0_DAT_13 \ ++ IOMUX_PAD(0x04B8, 0x01A4, 1, 0x0000, 0, 0) ++#define _MX6Q_PAD_DISP0_DAT13__AUDMUX_AUD5_RXFS \ ++ IOMUX_PAD(0x04B8, 0x01A4, 3, 0x07D8, 1, 0) ++#define _MX6Q_PAD_DISP0_DAT13__SDMA_DEBUG_EVT_CHN_LINES_0 \ ++ IOMUX_PAD(0x04B8, 0x01A4, 4, 0x0000, 0, 0) ++#define _MX6Q_PAD_DISP0_DAT13__GPIO_5_7 \ ++ IOMUX_PAD(0x04B8, 0x01A4, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_DISP0_DAT13__MMDC_MMDC_DEBUG_18 \ ++ IOMUX_PAD(0x04B8, 0x01A4, 6, 0x0000, 0, 0) ++#define _MX6Q_PAD_DISP0_DAT13__PL301_MX6QPER1_HADDR_24 \ ++ IOMUX_PAD(0x04B8, 0x01A4, 7, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14 \ ++ IOMUX_PAD(0x04BC, 0x01A8, 0, 0x0000, 0, 0) ++#define _MX6Q_PAD_DISP0_DAT14__IPU2_DISP0_DAT_14 \ ++ IOMUX_PAD(0x04BC, 0x01A8, 1, 0x0000, 0, 0) ++#define _MX6Q_PAD_DISP0_DAT14__AUDMUX_AUD5_RXC \ ++ IOMUX_PAD(0x04BC, 0x01A8, 3, 0x07D4, 1, 0) ++#define _MX6Q_PAD_DISP0_DAT14__SDMA_DEBUG_EVT_CHN_LINES_1 \ ++ IOMUX_PAD(0x04BC, 0x01A8, 4, 0x0000, 0, 0) ++#define _MX6Q_PAD_DISP0_DAT14__GPIO_5_8 \ ++ IOMUX_PAD(0x04BC, 0x01A8, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_DISP0_DAT14__MMDC_MMDC_DEBUG_19 \ ++ IOMUX_PAD(0x04BC, 0x01A8, 6, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15 \ ++ IOMUX_PAD(0x04C0, 0x01AC, 0, 0x0000, 0, 0) ++#define _MX6Q_PAD_DISP0_DAT15__IPU2_DISP0_DAT_15 \ ++ IOMUX_PAD(0x04C0, 0x01AC, 1, 0x0000, 0, 0) ++#define _MX6Q_PAD_DISP0_DAT15__ECSPI1_SS1 \ ++ IOMUX_PAD(0x04C0, 0x01AC, 2, 0x0804, 1, 0) ++#define _MX6Q_PAD_DISP0_DAT15__ECSPI2_SS1 \ ++ IOMUX_PAD(0x04C0, 0x01AC, 3, 0x0820, 1, 0) ++#define _MX6Q_PAD_DISP0_DAT15__SDMA_DEBUG_EVT_CHN_LINES_2 \ ++ IOMUX_PAD(0x04C0, 0x01AC, 4, 0x0000, 0, 0) ++#define _MX6Q_PAD_DISP0_DAT15__GPIO_5_9 \ ++ IOMUX_PAD(0x04C0, 0x01AC, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_DISP0_DAT15__MMDC_MMDC_DEBUG_20 \ ++ IOMUX_PAD(0x04C0, 0x01AC, 6, 0x0000, 0, 0) ++#define _MX6Q_PAD_DISP0_DAT15__PL301_MX6QPER1_HADDR_25 \ ++ IOMUX_PAD(0x04C0, 0x01AC, 7, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16 \ ++ IOMUX_PAD(0x04C4, 0x01B0, 0, 0x0000, 0, 0) ++#define _MX6Q_PAD_DISP0_DAT16__IPU2_DISP0_DAT_16 \ ++ IOMUX_PAD(0x04C4, 0x01B0, 1, 0x0000, 0, 0) ++#define _MX6Q_PAD_DISP0_DAT16__ECSPI2_MOSI \ ++ IOMUX_PAD(0x04C4, 0x01B0, 2, 0x0818, 1, 0) ++#define _MX6Q_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC \ ++ IOMUX_PAD(0x04C4, 0x01B0, 3, 0x07DC, 0, 0) ++#define _MX6Q_PAD_DISP0_DAT16__SDMA_SDMA_EXT_EVENT_0 \ ++ IOMUX_PAD(0x04C4, 0x01B0, 4, 0x090C, 0, 0) ++#define _MX6Q_PAD_DISP0_DAT16__GPIO_5_10 \ ++ IOMUX_PAD(0x04C4, 0x01B0, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_DISP0_DAT16__MMDC_MMDC_DEBUG_21 \ ++ IOMUX_PAD(0x04C4, 0x01B0, 6, 0x0000, 0, 0) ++#define _MX6Q_PAD_DISP0_DAT16__PL301_MX6QPER1_HADDR_26 \ ++ IOMUX_PAD(0x04C4, 0x01B0, 7, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17 \ ++ IOMUX_PAD(0x04C8, 0x01B4, 0, 0x0000, 0, 0) ++#define _MX6Q_PAD_DISP0_DAT17__IPU2_DISP0_DAT_17 \ ++ IOMUX_PAD(0x04C8, 0x01B4, 1, 0x0000, 0, 0) ++#define _MX6Q_PAD_DISP0_DAT17__ECSPI2_MISO \ ++ IOMUX_PAD(0x04C8, 0x01B4, 2, 0x0814, 1, 0) ++#define _MX6Q_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD \ ++ IOMUX_PAD(0x04C8, 0x01B4, 3, 0x07D0, 0, 0) ++#define _MX6Q_PAD_DISP0_DAT17__SDMA_SDMA_EXT_EVENT_1 \ ++ IOMUX_PAD(0x04C8, 0x01B4, 4, 0x0910, 0, 0) ++#define _MX6Q_PAD_DISP0_DAT17__GPIO_5_11 \ ++ IOMUX_PAD(0x04C8, 0x01B4, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_DISP0_DAT17__MMDC_MMDC_DEBUG_22 \ ++ IOMUX_PAD(0x04C8, 0x01B4, 6, 0x0000, 0, 0) ++#define _MX6Q_PAD_DISP0_DAT17__PL301_MX6QPER1_HADDR_27 \ ++ IOMUX_PAD(0x04C8, 0x01B4, 7, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18 \ ++ IOMUX_PAD(0x04CC, 0x01B8, 0, 0x0000, 0, 0) ++#define _MX6Q_PAD_DISP0_DAT18__IPU2_DISP0_DAT_18 \ ++ IOMUX_PAD(0x04CC, 0x01B8, 1, 0x0000, 0, 0) ++#define _MX6Q_PAD_DISP0_DAT18__ECSPI2_SS0 \ ++ IOMUX_PAD(0x04CC, 0x01B8, 2, 0x081C, 1, 0) ++#define _MX6Q_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS \ ++ IOMUX_PAD(0x04CC, 0x01B8, 3, 0x07E0, 0, 0) ++#define _MX6Q_PAD_DISP0_DAT18__AUDMUX_AUD4_RXFS \ ++ IOMUX_PAD(0x04CC, 0x01B8, 4, 0x07C0, 0, 0) ++#define _MX6Q_PAD_DISP0_DAT18__GPIO_5_12 \ ++ IOMUX_PAD(0x04CC, 0x01B8, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_DISP0_DAT18__MMDC_MMDC_DEBUG_23 \ ++ IOMUX_PAD(0x04CC, 0x01B8, 6, 0x0000, 0, 0) ++#define _MX6Q_PAD_DISP0_DAT18__WEIM_WEIM_CS_2 \ ++ IOMUX_PAD(0x04CC, 0x01B8, 7, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19 \ ++ IOMUX_PAD(0x04D0, 0x01BC, 0, 0x0000, 0, 0) ++#define _MX6Q_PAD_DISP0_DAT19__IPU2_DISP0_DAT_19 \ ++ IOMUX_PAD(0x04D0, 0x01BC, 1, 0x0000, 0, 0) ++#define _MX6Q_PAD_DISP0_DAT19__ECSPI2_SCLK \ ++ IOMUX_PAD(0x04D0, 0x01BC, 2, 0x0810, 1, 0) ++#define _MX6Q_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD \ ++ IOMUX_PAD(0x04D0, 0x01BC, 3, 0x07CC, 0, 0) ++#define _MX6Q_PAD_DISP0_DAT19__AUDMUX_AUD4_RXC \ ++ IOMUX_PAD(0x04D0, 0x01BC, 4, 0x07BC, 0, 0) ++#define _MX6Q_PAD_DISP0_DAT19__GPIO_5_13 \ ++ IOMUX_PAD(0x04D0, 0x01BC, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_DISP0_DAT19__MMDC_MMDC_DEBUG_24 \ ++ IOMUX_PAD(0x04D0, 0x01BC, 6, 0x0000, 0, 0) ++#define _MX6Q_PAD_DISP0_DAT19__WEIM_WEIM_CS_3 \ ++ IOMUX_PAD(0x04D0, 0x01BC, 7, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20 \ ++ IOMUX_PAD(0x04D4, 0x01C0, 0, 0x0000, 0, 0) ++#define _MX6Q_PAD_DISP0_DAT20__IPU2_DISP0_DAT_20 \ ++ IOMUX_PAD(0x04D4, 0x01C0, 1, 0x0000, 0, 0) ++#define _MX6Q_PAD_DISP0_DAT20__ECSPI1_SCLK \ ++ IOMUX_PAD(0x04D4, 0x01C0, 2, 0x07F4, 1, 0) ++#define _MX6Q_PAD_DISP0_DAT20__AUDMUX_AUD4_TXC \ ++ IOMUX_PAD(0x04D4, 0x01C0, 3, 0x07C4, 0, 0) ++#define _MX6Q_PAD_DISP0_DAT20__SDMA_DEBUG_EVT_CHN_LINES_7 \ ++ IOMUX_PAD(0x04D4, 0x01C0, 4, 0x0000, 0, 0) ++#define _MX6Q_PAD_DISP0_DAT20__GPIO_5_14 \ ++ IOMUX_PAD(0x04D4, 0x01C0, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_DISP0_DAT20__MMDC_MMDC_DEBUG_25 \ ++ IOMUX_PAD(0x04D4, 0x01C0, 6, 0x0000, 0, 0) ++#define _MX6Q_PAD_DISP0_DAT20__PL301_MX6QPER1_HADDR_28 \ ++ IOMUX_PAD(0x04D4, 0x01C0, 7, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21 \ ++ IOMUX_PAD(0x04D8, 0x01C4, 0, 0x0000, 0, 0) ++#define _MX6Q_PAD_DISP0_DAT21__IPU2_DISP0_DAT_21 \ ++ IOMUX_PAD(0x04D8, 0x01C4, 1, 0x0000, 0, 0) ++#define _MX6Q_PAD_DISP0_DAT21__ECSPI1_MOSI \ ++ IOMUX_PAD(0x04D8, 0x01C4, 2, 0x07FC, 1, 0) ++#define _MX6Q_PAD_DISP0_DAT21__AUDMUX_AUD4_TXD \ ++ IOMUX_PAD(0x04D8, 0x01C4, 3, 0x07B8, 1, 0) ++#define _MX6Q_PAD_DISP0_DAT21__SDMA_DEBUG_BUS_DEVICE_0 \ ++ IOMUX_PAD(0x04D8, 0x01C4, 4, 0x0000, 0, 0) ++#define _MX6Q_PAD_DISP0_DAT21__GPIO_5_15 \ ++ IOMUX_PAD(0x04D8, 0x01C4, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_DISP0_DAT21__MMDC_MMDC_DEBUG_26 \ ++ IOMUX_PAD(0x04D8, 0x01C4, 6, 0x0000, 0, 0) ++#define _MX6Q_PAD_DISP0_DAT21__PL301_MX6QPER1_HADDR_29 \ ++ IOMUX_PAD(0x04D8, 0x01C4, 7, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22 \ ++ IOMUX_PAD(0x04DC, 0x01C8, 0, 0x0000, 0, 0) ++#define _MX6Q_PAD_DISP0_DAT22__IPU2_DISP0_DAT_22 \ ++ IOMUX_PAD(0x04DC, 0x01C8, 1, 0x0000, 0, 0) ++#define _MX6Q_PAD_DISP0_DAT22__ECSPI1_MISO \ ++ IOMUX_PAD(0x04DC, 0x01C8, 2, 0x07F8, 1, 0) ++#define _MX6Q_PAD_DISP0_DAT22__AUDMUX_AUD4_TXFS \ ++ IOMUX_PAD(0x04DC, 0x01C8, 3, 0x07C8, 1, 0) ++#define _MX6Q_PAD_DISP0_DAT22__SDMA_DEBUG_BUS_DEVICE_1 \ ++ IOMUX_PAD(0x04DC, 0x01C8, 4, 0x0000, 0, 0) ++#define _MX6Q_PAD_DISP0_DAT22__GPIO_5_16 \ ++ IOMUX_PAD(0x04DC, 0x01C8, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_DISP0_DAT22__MMDC_MMDC_DEBUG_27 \ ++ IOMUX_PAD(0x04DC, 0x01C8, 6, 0x0000, 0, 0) ++#define _MX6Q_PAD_DISP0_DAT22__PL301_MX6QPER1_HADDR_30 \ ++ IOMUX_PAD(0x04DC, 0x01C8, 7, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23 \ ++ IOMUX_PAD(0x04E0, 0x01CC, 0, 0x0000, 0, 0) ++#define _MX6Q_PAD_DISP0_DAT23__IPU2_DISP0_DAT_23 \ ++ IOMUX_PAD(0x04E0, 0x01CC, 1, 0x0000, 0, 0) ++#define _MX6Q_PAD_DISP0_DAT23__ECSPI1_SS0 \ ++ IOMUX_PAD(0x04E0, 0x01CC, 2, 0x0800, 1, 0) ++#define _MX6Q_PAD_DISP0_DAT23__AUDMUX_AUD4_RXD \ ++ IOMUX_PAD(0x04E0, 0x01CC, 3, 0x07B4, 1, 0) ++#define _MX6Q_PAD_DISP0_DAT23__SDMA_DEBUG_BUS_DEVICE_2 \ ++ IOMUX_PAD(0x04E0, 0x01CC, 4, 0x0000, 0, 0) ++#define _MX6Q_PAD_DISP0_DAT23__GPIO_5_17 \ ++ IOMUX_PAD(0x04E0, 0x01CC, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_DISP0_DAT23__MMDC_MMDC_DEBUG_28 \ ++ IOMUX_PAD(0x04E0, 0x01CC, 6, 0x0000, 0, 0) ++#define _MX6Q_PAD_DISP0_DAT23__PL301_MX6QPER1_HADDR_31 \ ++ IOMUX_PAD(0x04E0, 0x01CC, 7, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_ENET_MDIO__ENET_MDIO \ ++ IOMUX_PAD(0x04E4, 0x01D0, 1, 0x0840, 0, 0) ++#define _MX6Q_PAD_ENET_MDIO__ESAI1_SCKR \ ++ IOMUX_PAD(0x04E4, 0x01D0, 2, 0x086C, 0, 0) ++#define _MX6Q_PAD_ENET_MDIO__SDMA_DEBUG_BUS_DEVICE_3 \ ++ IOMUX_PAD(0x04E4, 0x01D0, 3, 0x0000, 0, 0) ++#define _MX6Q_PAD_ENET_MDIO__ENET_1588_EVENT1_OUT \ ++ IOMUX_PAD(0x04E4, 0x01D0, 4, 0x0000, 0, 0) ++#define _MX6Q_PAD_ENET_MDIO__GPIO_1_22 \ ++ IOMUX_PAD(0x04E4, 0x01D0, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_ENET_MDIO__SPDIF_PLOCK \ ++ IOMUX_PAD(0x04E4, 0x01D0, 6, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK \ ++ IOMUX_PAD(0x04E8, 0x01D4, 1, 0x0000, 0, 0) ++#define _MX6Q_PAD_ENET_REF_CLK__ESAI1_FSR \ ++ IOMUX_PAD(0x04E8, 0x01D4, 2, 0x085C, 0, 0) ++#define _MX6Q_PAD_ENET_REF_CLK__SDMA_DEBUG_BUS_DEVICE_4 \ ++ IOMUX_PAD(0x04E8, 0x01D4, 3, 0x0000, 0, 0) ++#define _MX6Q_PAD_ENET_REF_CLK__GPIO_1_23 \ ++ IOMUX_PAD(0x04E8, 0x01D4, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_ENET_REF_CLK__SPDIF_SRCLK \ ++ IOMUX_PAD(0x04E8, 0x01D4, 6, 0x0000, 0, 0) ++#define _MX6Q_PAD_ENET_REF_CLK__ANATOP_USBPHY1_TSTO_RX_SQUELCH \ ++ IOMUX_PAD(0x04E8, 0x01D4, 7, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_ENET_RX_ER__ENET_RX_ER \ ++ IOMUX_PAD(0x04EC, 0x01D8, 1, 0x0000, 0, 0) ++#define _MX6Q_PAD_ENET_RX_ER__ESAI1_HCKR \ ++ IOMUX_PAD(0x04EC, 0x01D8, 2, 0x0864, 0, 0) ++#define _MX6Q_PAD_ENET_RX_ER__SPDIF_IN1 \ ++ IOMUX_PAD(0x04EC, 0x01D8, 3, 0x0914, 1, 0) ++#define _MX6Q_PAD_ENET_RX_ER__ENET_1588_EVENT2_OUT \ ++ IOMUX_PAD(0x04EC, 0x01D8, 4, 0x0000, 0, 0) ++#define _MX6Q_PAD_ENET_RX_ER__GPIO_1_24 \ ++ IOMUX_PAD(0x04EC, 0x01D8, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_ENET_RX_ER__PHY_TDI \ ++ IOMUX_PAD(0x04EC, 0x01D8, 6, 0x0000, 0, 0) ++#define _MX6Q_PAD_ENET_RX_ER__ANATOP_USBPHY1_TSTO_RX_HS_RXD \ ++ IOMUX_PAD(0x04EC, 0x01D8, 7, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_ENET_CRS_DV__ENET_RX_EN \ ++ IOMUX_PAD(0x04F0, 0x01DC, 1, 0x0858, 1, 0) ++#define _MX6Q_PAD_ENET_CRS_DV__ESAI1_SCKT \ ++ IOMUX_PAD(0x04F0, 0x01DC, 2, 0x0870, 0, 0) ++#define _MX6Q_PAD_ENET_CRS_DV__SPDIF_SPDIF_EXTCLK \ ++ IOMUX_PAD(0x04F0, 0x01DC, 3, 0x0918, 1, 0) ++#define _MX6Q_PAD_ENET_CRS_DV__GPIO_1_25 \ ++ IOMUX_PAD(0x04F0, 0x01DC, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_ENET_CRS_DV__PHY_TDO \ ++ IOMUX_PAD(0x04F0, 0x01DC, 6, 0x0000, 0, 0) ++#define _MX6Q_PAD_ENET_CRS_DV__ANATOP_USBPHY1_TSTO_RX_FS_RXD \ ++ IOMUX_PAD(0x04F0, 0x01DC, 7, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_ENET_RXD1__MLB_MLBSIG \ ++ IOMUX_PAD(0x04F4, 0x01E0, 0, 0x0908, 0, 0) ++#define _MX6Q_PAD_ENET_RXD1__ENET_RDATA_1 \ ++ IOMUX_PAD(0x04F4, 0x01E0, 1, 0x084C, 1, 0) ++#define _MX6Q_PAD_ENET_RXD1__ESAI1_FST \ ++ IOMUX_PAD(0x04F4, 0x01E0, 2, 0x0860, 0, 0) ++#define _MX6Q_PAD_ENET_RXD1__ENET_1588_EVENT3_OUT \ ++ IOMUX_PAD(0x04F4, 0x01E0, 4, 0x0000, 0, 0) ++#define _MX6Q_PAD_ENET_RXD1__GPIO_1_26 \ ++ IOMUX_PAD(0x04F4, 0x01E0, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_ENET_RXD1__PHY_TCK \ ++ IOMUX_PAD(0x04F4, 0x01E0, 6, 0x0000, 0, 0) ++#define _MX6Q_PAD_ENET_RXD1__ANATOP_USBPHY1_TSTO_RX_DISCON_DET \ ++ IOMUX_PAD(0x04F4, 0x01E0, 7, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_ENET_RXD0__OSC32K_32K_OUT \ ++ IOMUX_PAD(0x04F8, 0x01E4, 0, 0x0000, 0, 0) ++#define _MX6Q_PAD_ENET_RXD0__ENET_RDATA_0 \ ++ IOMUX_PAD(0x04F8, 0x01E4, 1, 0x0848, 1, 0) ++#define _MX6Q_PAD_ENET_RXD0__ESAI1_HCKT \ ++ IOMUX_PAD(0x04F8, 0x01E4, 2, 0x0868, 0, 0) ++#define _MX6Q_PAD_ENET_RXD0__SPDIF_OUT1 \ ++ IOMUX_PAD(0x04F8, 0x01E4, 3, 0x0000, 0, 0) ++#define _MX6Q_PAD_ENET_RXD0__GPIO_1_27 \ ++ IOMUX_PAD(0x04F8, 0x01E4, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_ENET_RXD0__PHY_TMS \ ++ IOMUX_PAD(0x04F8, 0x01E4, 6, 0x0000, 0, 0) ++#define _MX6Q_PAD_ENET_RXD0__ANATOP_USBPHY1_TSTO_PLL_CLK20DIV \ ++ IOMUX_PAD(0x04F8, 0x01E4, 7, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_ENET_TX_EN__ENET_TX_EN \ ++ IOMUX_PAD(0x04FC, 0x01E8, 1, 0x0000, 0, 0) ++#define _MX6Q_PAD_ENET_TX_EN__ESAI1_TX3_RX2 \ ++ IOMUX_PAD(0x04FC, 0x01E8, 2, 0x0880, 0, 0) ++#define _MX6Q_PAD_ENET_TX_EN__GPIO_1_28 \ ++ IOMUX_PAD(0x04FC, 0x01E8, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_ENET_TX_EN__SATA_PHY_TDI \ ++ IOMUX_PAD(0x04FC, 0x01E8, 6, 0x0000, 0, 0) ++#define _MX6Q_PAD_ENET_TX_EN__ANATOP_USBPHY2_TSTO_RX_SQUELCH \ ++ IOMUX_PAD(0x04FC, 0x01E8, 7, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_ENET_TXD1__MLB_MLBCLK \ ++ IOMUX_PAD(0x0500, 0x01EC, 0, 0x0900, 0, 0) ++#define _MX6Q_PAD_ENET_TXD1__ENET_TDATA_1 \ ++ IOMUX_PAD(0x0500, 0x01EC, 1, 0x0000, 0, 0) ++#define _MX6Q_PAD_ENET_TXD1__ESAI1_TX2_RX3 \ ++ IOMUX_PAD(0x0500, 0x01EC, 2, 0x087C, 0, 0) ++#define _MX6Q_PAD_ENET_TXD1__ENET_1588_EVENT0_IN \ ++ IOMUX_PAD(0x0500, 0x01EC, 4, 0x0000, 0, 0) ++#define _MX6Q_PAD_ENET_TXD1__GPIO_1_29 \ ++ IOMUX_PAD(0x0500, 0x01EC, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_ENET_TXD1__SATA_PHY_TDO \ ++ IOMUX_PAD(0x0500, 0x01EC, 6, 0x0000, 0, 0) ++#define _MX6Q_PAD_ENET_TXD1__ANATOP_USBPHY2_TSTO_RX_HS_RXD \ ++ IOMUX_PAD(0x0500, 0x01EC, 7, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_ENET_TXD0__ENET_TDATA_0 \ ++ IOMUX_PAD(0x0504, 0x01F0, 1, 0x0000, 0, 0) ++#define _MX6Q_PAD_ENET_TXD0__ESAI1_TX4_RX1 \ ++ IOMUX_PAD(0x0504, 0x01F0, 2, 0x0884, 0, 0) ++#define _MX6Q_PAD_ENET_TXD0__GPIO_1_30 \ ++ IOMUX_PAD(0x0504, 0x01F0, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_ENET_TXD0__SATA_PHY_TCK \ ++ IOMUX_PAD(0x0504, 0x01F0, 6, 0x0000, 0, 0) ++#define _MX6Q_PAD_ENET_TXD0__ANATOP_USBPHY2_TSTO_RX_FS_RXD \ ++ IOMUX_PAD(0x0504, 0x01F0, 7, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_ENET_MDC__MLB_MLBDAT \ ++ IOMUX_PAD(0x0508, 0x01F4, 0, 0x0904, 0, 0) ++#define _MX6Q_PAD_ENET_MDC__ENET_MDC \ ++ IOMUX_PAD(0x0508, 0x01F4, 1, 0x0000, 0, 0) ++#define _MX6Q_PAD_ENET_MDC__ESAI1_TX5_RX0 \ ++ IOMUX_PAD(0x0508, 0x01F4, 2, 0x0888, 0, 0) ++#define _MX6Q_PAD_ENET_MDC__ENET_1588_EVENT1_IN \ ++ IOMUX_PAD(0x0508, 0x01F4, 4, 0x0000, 0, 0) ++#define _MX6Q_PAD_ENET_MDC__GPIO_1_31 \ ++ IOMUX_PAD(0x0508, 0x01F4, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_ENET_MDC__SATA_PHY_TMS \ ++ IOMUX_PAD(0x0508, 0x01F4, 6, 0x0000, 0, 0) ++#define _MX6Q_PAD_ENET_MDC__ANATOP_USBPHY2_TSTO_RX_DISCON_DET \ ++ IOMUX_PAD(0x0508, 0x01F4, 7, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_DRAM_D40__MMDC_DRAM_D_40 \ ++ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_DRAM_D41__MMDC_DRAM_D_41 \ ++ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_DRAM_D42__MMDC_DRAM_D_42 \ ++ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_DRAM_D43__MMDC_DRAM_D_43 \ ++ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_DRAM_D44__MMDC_DRAM_D_44 \ ++ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_DRAM_D45__MMDC_DRAM_D_45 \ ++ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_DRAM_D46__MMDC_DRAM_D_46 \ ++ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_DRAM_D47__MMDC_DRAM_D_47 \ ++ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_DRAM_SDQS5__MMDC_DRAM_SDQS_5 \ ++ IOMUX_PAD(0x050C, NO_MUX_I, 0, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_DRAM_DQM5__MMDC_DRAM_DQM_5 \ ++ IOMUX_PAD(0x0510, NO_MUX_I, 0, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_DRAM_D32__MMDC_DRAM_D_32 \ ++ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_DRAM_D33__MMDC_DRAM_D_33 \ ++ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_DRAM_D34__MMDC_DRAM_D_34 \ ++ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_DRAM_D35__MMDC_DRAM_D_35 \ ++ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_DRAM_D36__MMDC_DRAM_D_36 \ ++ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_DRAM_D37__MMDC_DRAM_D_37 \ ++ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_DRAM_D38__MMDC_DRAM_D_38 \ ++ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_DRAM_D39__MMDC_DRAM_D_39 \ ++ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_DRAM_DQM4__MMDC_DRAM_DQM_4 \ ++ IOMUX_PAD(0x0514, NO_MUX_I, 0, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_DRAM_SDQS4__MMDC_DRAM_SDQS_4 \ ++ IOMUX_PAD(0x0518, NO_MUX_I, 0, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_DRAM_D24__MMDC_DRAM_D_24 \ ++ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_DRAM_D25__MMDC_DRAM_D_25 \ ++ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_DRAM_D26__MMDC_DRAM_D_26 \ ++ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_DRAM_D27__MMDC_DRAM_D_27 \ ++ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_DRAM_D28__MMDC_DRAM_D_28 \ ++ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_DRAM_D29__MMDC_DRAM_D_29 \ ++ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_DRAM_SDQS3__MMDC_DRAM_SDQS_3 \ ++ IOMUX_PAD(0x051C, NO_MUX_I, 0, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_DRAM_D30__MMDC_DRAM_D_30 \ ++ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_DRAM_D31__MMDC_DRAM_D_31 \ ++ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_DRAM_DQM3__MMDC_DRAM_DQM_3 \ ++ IOMUX_PAD(0x0520, NO_MUX_I, 0, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_DRAM_D16__MMDC_DRAM_D_16 \ ++ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_DRAM_D17__MMDC_DRAM_D_17 \ ++ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_DRAM_D18__MMDC_DRAM_D_18 \ ++ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_DRAM_D19__MMDC_DRAM_D_19 \ ++ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_DRAM_D20__MMDC_DRAM_D_20 \ ++ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_DRAM_D21__MMDC_DRAM_D_21 \ ++ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_DRAM_D22__MMDC_DRAM_D_22 \ ++ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_DRAM_SDQS2__MMDC_DRAM_SDQS_2 \ ++ IOMUX_PAD(0x0524, NO_MUX_I, 0, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_DRAM_D23__MMDC_DRAM_D_23 \ ++ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_DRAM_DQM2__MMDC_DRAM_DQM_2 \ ++ IOMUX_PAD(0x0528, NO_MUX_I, 0, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_DRAM_A0__MMDC_DRAM_A_0 \ ++ IOMUX_PAD(0x052C, NO_MUX_I, 0, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_DRAM_A1__MMDC_DRAM_A_1 \ ++ IOMUX_PAD(0x0530, NO_MUX_I, 0, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_DRAM_A2__MMDC_DRAM_A_2 \ ++ IOMUX_PAD(0x0534, NO_MUX_I, 0, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_DRAM_A3__MMDC_DRAM_A_3 \ ++ IOMUX_PAD(0x0538, NO_MUX_I, 0, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_DRAM_A4__MMDC_DRAM_A_4 \ ++ IOMUX_PAD(0x053C, NO_MUX_I, 0, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_DRAM_A5__MMDC_DRAM_A_5 \ ++ IOMUX_PAD(0x0540, NO_MUX_I, 0, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_DRAM_A6__MMDC_DRAM_A_6 \ ++ IOMUX_PAD(0x0544, NO_MUX_I, 0, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_DRAM_A7__MMDC_DRAM_A_7 \ ++ IOMUX_PAD(0x0548, NO_MUX_I, 0, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_DRAM_A8__MMDC_DRAM_A_8 \ ++ IOMUX_PAD(0x054C, NO_MUX_I, 0, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_DRAM_A9__MMDC_DRAM_A_9 \ ++ IOMUX_PAD(0x0550, NO_MUX_I, 0, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_DRAM_A10__MMDC_DRAM_A_10 \ ++ IOMUX_PAD(0x0554, NO_MUX_I, 0, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_DRAM_A11__MMDC_DRAM_A_11 \ ++ IOMUX_PAD(0x0558, NO_MUX_I, 0, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_DRAM_A12__MMDC_DRAM_A_12 \ ++ IOMUX_PAD(0x055C, NO_MUX_I, 0, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_DRAM_A13__MMDC_DRAM_A_13 \ ++ IOMUX_PAD(0x0560, NO_MUX_I, 0, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_DRAM_A14__MMDC_DRAM_A_14 \ ++ IOMUX_PAD(0x0564, NO_MUX_I, 0, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_DRAM_A15__MMDC_DRAM_A_15 \ ++ IOMUX_PAD(0x0568, NO_MUX_I, 0, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_DRAM_CAS__MMDC_DRAM_CAS \ ++ IOMUX_PAD(0x056C, NO_MUX_I, 0, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_DRAM_CS0__MMDC_DRAM_CS_0 \ ++ IOMUX_PAD(0x0570, NO_MUX_I, 0, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_DRAM_CS1__MMDC_DRAM_CS_1 \ ++ IOMUX_PAD(0x0574, NO_MUX_I, 0, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_DRAM_RAS__MMDC_DRAM_RAS \ ++ IOMUX_PAD(0x0578, NO_MUX_I, 0, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_DRAM_RESET__MMDC_DRAM_RESET \ ++ IOMUX_PAD(0x057C, NO_MUX_I, 0, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_DRAM_SDBA0__MMDC_DRAM_SDBA_0 \ ++ IOMUX_PAD(0x0580, NO_MUX_I, 0, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_DRAM_SDBA1__MMDC_DRAM_SDBA_1 \ ++ IOMUX_PAD(0x0584, NO_MUX_I, 0, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_DRAM_SDCLK_0__MMDC_DRAM_SDCLK0 \ ++ IOMUX_PAD(0x0588, NO_MUX_I, 0, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_DRAM_SDBA2__MMDC_DRAM_SDBA_2 \ ++ IOMUX_PAD(0x058C, NO_MUX_I, 0, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_DRAM_SDCKE0__MMDC_DRAM_SDCKE_0 \ ++ IOMUX_PAD(0x0590, NO_MUX_I, 0, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_DRAM_SDCLK_1__MMDC_DRAM_SDCLK1 \ ++ IOMUX_PAD(0x0594, NO_MUX_I, 0, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_DRAM_SDCKE1__MMDC_DRAM_SDCKE_1 \ ++ IOMUX_PAD(0x0598, NO_MUX_I, 0, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_DRAM_SDODT0__MMDC_DRAM_ODT_0 \ ++ IOMUX_PAD(0x059C, NO_MUX_I, 0, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_DRAM_SDODT1__MMDC_DRAM_ODT_1 \ ++ IOMUX_PAD(0x05A0, NO_MUX_I, 0, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_DRAM_SDWE__MMDC_DRAM_SDWE \ ++ IOMUX_PAD(0x05A4, NO_MUX_I, 0, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_DRAM_D0__MMDC_DRAM_D_0 \ ++ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_DRAM_D1__MMDC_DRAM_D_1 \ ++ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_DRAM_D2__MMDC_DRAM_D_2 \ ++ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_DRAM_D3__MMDC_DRAM_D_3 \ ++ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_DRAM_D4__MMDC_DRAM_D_4 \ ++ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_DRAM_D5__MMDC_DRAM_D_5 \ ++ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_DRAM_SDQS0__MMDC_DRAM_SDQS_0 \ ++ IOMUX_PAD(0x05A8, NO_MUX_I, 0, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_DRAM_D6__MMDC_DRAM_D_6 \ ++ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_DRAM_D7__MMDC_DRAM_D_7 \ ++ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_DRAM_DQM0__MMDC_DRAM_DQM_0 \ ++ IOMUX_PAD(0x05AC, NO_MUX_I, 0, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_DRAM_D8__MMDC_DRAM_D_8 \ ++ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_DRAM_D9__MMDC_DRAM_D_9 \ ++ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_DRAM_D10__MMDC_DRAM_D_10 \ ++ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_DRAM_D11__MMDC_DRAM_D_11 \ ++ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_DRAM_D12__MMDC_DRAM_D_12 \ ++ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_DRAM_D13__MMDC_DRAM_D_13 \ ++ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_DRAM_D14__MMDC_DRAM_D_14 \ ++ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_DRAM_SDQS1__MMDC_DRAM_SDQS_1 \ ++ IOMUX_PAD(0x05B0, NO_MUX_I, 0, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_DRAM_D15__MMDC_DRAM_D_15 \ ++ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_DRAM_DQM1__MMDC_DRAM_DQM_1 \ ++ IOMUX_PAD(0x05B4, NO_MUX_I, 0, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_DRAM_D48__MMDC_DRAM_D_48 \ ++ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_DRAM_D49__MMDC_DRAM_D_49 \ ++ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_DRAM_D50__MMDC_DRAM_D_50 \ ++ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_DRAM_D51__MMDC_DRAM_D_51 \ ++ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_DRAM_D52__MMDC_DRAM_D_52 \ ++ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_DRAM_D53__MMDC_DRAM_D_53 \ ++ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_DRAM_D54__MMDC_DRAM_D_54 \ ++ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_DRAM_D55__MMDC_DRAM_D_55 \ ++ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_DRAM_SDQS6__MMDC_DRAM_SDQS_6 \ ++ IOMUX_PAD(0x05B8, NO_MUX_I, 0, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_DRAM_DQM6__MMDC_DRAM_DQM_6 \ ++ IOMUX_PAD(0x05BC, NO_MUX_I, 0, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_DRAM_D56__MMDC_DRAM_D_56 \ ++ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_DRAM_SDQS7__MMDC_DRAM_SDQS_7 \ ++ IOMUX_PAD(0x05C0, NO_MUX_I, 0, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_DRAM_D57__MMDC_DRAM_D_57 \ ++ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_DRAM_D58__MMDC_DRAM_D_58 \ ++ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_DRAM_D59__MMDC_DRAM_D_59 \ ++ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_DRAM_D60__MMDC_DRAM_D_60 \ ++ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_DRAM_DQM7__MMDC_DRAM_DQM_7 \ ++ IOMUX_PAD(0x05C4, NO_MUX_I, 0, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_DRAM_D61__MMDC_DRAM_D_61 \ ++ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_DRAM_D62__MMDC_DRAM_D_62 \ ++ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_DRAM_D63__MMDC_DRAM_D_63 \ ++ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_KEY_COL0__ECSPI1_SCLK \ ++ IOMUX_PAD(0x05C8, 0x01F8, 0, 0x07F4, 2, 0) ++#define _MX6Q_PAD_KEY_COL0__ENET_RDATA_3 \ ++ IOMUX_PAD(0x05C8, 0x01F8, 1, 0x0854, 1, 0) ++#define _MX6Q_PAD_KEY_COL0__AUDMUX_AUD5_TXC \ ++ IOMUX_PAD(0x05C8, 0x01F8, 2, 0x07DC, 1, 0) ++#define _MX6Q_PAD_KEY_COL0__KPP_COL_0 \ ++ IOMUX_PAD(0x05C8, 0x01F8, 3, 0x0000, 0, 0) ++#define _MX6Q_PAD_KEY_COL0__UART4_TXD \ ++ IOMUX_PAD(0x05C8, 0x01F8, 4, 0x0000, 0, 0) ++#define _MX6Q_PAD_KEY_COL0__UART4_RXD \ ++ IOMUX_PAD(0x05C8, 0x01F8, 4, 0x0938, 0, 0) ++#define _MX6Q_PAD_KEY_COL0__GPIO_4_6 \ ++ IOMUX_PAD(0x05C8, 0x01F8, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_KEY_COL0__DCIC1_DCIC_OUT \ ++ IOMUX_PAD(0x05C8, 0x01F8, 6, 0x0000, 0, 0) ++#define _MX6Q_PAD_KEY_COL0__SRC_ANY_PU_RST \ ++ IOMUX_PAD(0x05C8, 0x01F8, 7, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_KEY_ROW0__ECSPI1_MOSI \ ++ IOMUX_PAD(0x05CC, 0x01FC, 0, 0x07FC, 2, 0) ++#define _MX6Q_PAD_KEY_ROW0__ENET_TDATA_3 \ ++ IOMUX_PAD(0x05CC, 0x01FC, 1, 0x0000, 0, 0) ++#define _MX6Q_PAD_KEY_ROW0__AUDMUX_AUD5_TXD \ ++ IOMUX_PAD(0x05CC, 0x01FC, 2, 0x07D0, 1, 0) ++#define _MX6Q_PAD_KEY_ROW0__KPP_ROW_0 \ ++ IOMUX_PAD(0x05CC, 0x01FC, 3, 0x0000, 0, 0) ++#define _MX6Q_PAD_KEY_ROW0__UART4_TXD \ ++ IOMUX_PAD(0x05CC, 0x01FC, 4, 0x0000, 0, 0) ++#define _MX6Q_PAD_KEY_ROW0__UART4_RXD \ ++ IOMUX_PAD(0x05CC, 0x01FC, 4, 0x0938, 1, 0) ++#define _MX6Q_PAD_KEY_ROW0__GPIO_4_7 \ ++ IOMUX_PAD(0x05CC, 0x01FC, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_KEY_ROW0__DCIC2_DCIC_OUT \ ++ IOMUX_PAD(0x05CC, 0x01FC, 6, 0x0000, 0, 0) ++#define _MX6Q_PAD_KEY_ROW0__PL301_MX6QPER1_HADDR_0 \ ++ IOMUX_PAD(0x05CC, 0x01FC, 7, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_KEY_COL1__ECSPI1_MISO \ ++ IOMUX_PAD(0x05D0, 0x0200, 0, 0x07F8, 2, 0) ++#define _MX6Q_PAD_KEY_COL1__ENET_MDIO \ ++ IOMUX_PAD(0x05D0, 0x0200, 1, 0x0840, 1, 0) ++#define _MX6Q_PAD_KEY_COL1__AUDMUX_AUD5_TXFS \ ++ IOMUX_PAD(0x05D0, 0x0200, 2, 0x07E0, 1, 0) ++#define _MX6Q_PAD_KEY_COL1__KPP_COL_1 \ ++ IOMUX_PAD(0x05D0, 0x0200, 3, 0x0000, 0, 0) ++#define _MX6Q_PAD_KEY_COL1__UART5_TXD \ ++ IOMUX_PAD(0x05D0, 0x0200, 4, 0x0000, 0, 0) ++#define _MX6Q_PAD_KEY_COL1__UART5_RXD \ ++ IOMUX_PAD(0x05D0, 0x0200, 4, 0x0940, 0, 0) ++#define _MX6Q_PAD_KEY_COL1__GPIO_4_8 \ ++ IOMUX_PAD(0x05D0, 0x0200, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_KEY_COL1__USDHC1_VSELECT \ ++ IOMUX_PAD(0x05D0, 0x0200, 6, 0x0000, 0, 0) ++#define _MX6Q_PAD_KEY_COL1__PL301_MX6QPER1_HADDR_1 \ ++ IOMUX_PAD(0x05D0, 0x0200, 7, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_KEY_ROW1__ECSPI1_SS0 \ ++ IOMUX_PAD(0x05D4, 0x0204, 0, 0x0800, 2, 0) ++#define _MX6Q_PAD_KEY_ROW1__ENET_COL \ ++ IOMUX_PAD(0x05D4, 0x0204, 1, 0x0000, 0, 0) ++#define _MX6Q_PAD_KEY_ROW1__AUDMUX_AUD5_RXD \ ++ IOMUX_PAD(0x05D4, 0x0204, 2, 0x07CC, 1, 0) ++#define _MX6Q_PAD_KEY_ROW1__KPP_ROW_1 \ ++ IOMUX_PAD(0x05D4, 0x0204, 3, 0x0000, 0, 0) ++#define _MX6Q_PAD_KEY_ROW1__UART5_TXD \ ++ IOMUX_PAD(0x05D4, 0x0204, 4, 0x0000, 0, 0) ++#define _MX6Q_PAD_KEY_ROW1__UART5_RXD \ ++ IOMUX_PAD(0x05D4, 0x0204, 4, 0x0940, 1, 0) ++#define _MX6Q_PAD_KEY_ROW1__GPIO_4_9 \ ++ IOMUX_PAD(0x05D4, 0x0204, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_KEY_ROW1__USDHC2_VSELECT \ ++ IOMUX_PAD(0x05D4, 0x0204, 6, 0x0000, 0, 0) ++#define _MX6Q_PAD_KEY_ROW1__PL301_MX6QPER1_HADDR_2 \ ++ IOMUX_PAD(0x05D4, 0x0204, 7, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_KEY_COL2__ECSPI1_SS1 \ ++ IOMUX_PAD(0x05D8, 0x0208, 0, 0x0804, 2, 0) ++#define _MX6Q_PAD_KEY_COL2__ENET_RDATA_2 \ ++ IOMUX_PAD(0x05D8, 0x0208, 1, 0x0850, 1, 0) ++#define _MX6Q_PAD_KEY_COL2__CAN1_TXCAN \ ++ IOMUX_PAD(0x05D8, 0x0208, 2, 0x0000, 0, 0) ++#define _MX6Q_PAD_KEY_COL2__KPP_COL_2 \ ++ IOMUX_PAD(0x05D8, 0x0208, 3, 0x0000, 0, 0) ++#define _MX6Q_PAD_KEY_COL2__ENET_MDC \ ++ IOMUX_PAD(0x05D8, 0x0208, 4, 0x0000, 0, 0) ++#define _MX6Q_PAD_KEY_COL2__GPIO_4_10 \ ++ IOMUX_PAD(0x05D8, 0x0208, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_KEY_COL2__USBOH3_H1USB_PWRCTL_WAKEUP \ ++ IOMUX_PAD(0x05D8, 0x0208, 6, 0x0000, 0, 0) ++#define _MX6Q_PAD_KEY_COL2__PL301_MX6QPER1_HADDR_3 \ ++ IOMUX_PAD(0x05D8, 0x0208, 7, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_KEY_ROW2__ECSPI1_SS2 \ ++ IOMUX_PAD(0x05DC, 0x020C, 0, 0x0808, 1, 0) ++#define _MX6Q_PAD_KEY_ROW2__ENET_TDATA_2 \ ++ IOMUX_PAD(0x05DC, 0x020C, 1, 0x0000, 0, 0) ++#define _MX6Q_PAD_KEY_ROW2__CAN1_RXCAN \ ++ IOMUX_PAD(0x05DC, 0x020C, 2, 0x07E4, 0, 0) ++#define _MX6Q_PAD_KEY_ROW2__KPP_ROW_2 \ ++ IOMUX_PAD(0x05DC, 0x020C, 3, 0x0000, 0, 0) ++#define _MX6Q_PAD_KEY_ROW2__USDHC2_VSELECT \ ++ IOMUX_PAD(0x05DC, 0x020C, 4, 0x0000, 0, 0) ++#define _MX6Q_PAD_KEY_ROW2__GPIO_4_11 \ ++ IOMUX_PAD(0x05DC, 0x020C, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_KEY_ROW2__HDMI_TX_CEC_LINE \ ++ IOMUX_PAD(0x05DC, 0x020C, 6, 0x088C, 1, 0) ++#define _MX6Q_PAD_KEY_ROW2__PL301_MX6QPER1_HADDR_4 \ ++ IOMUX_PAD(0x05DC, 0x020C, 7, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_KEY_COL3__ECSPI1_SS3 \ ++ IOMUX_PAD(0x05E0, 0x0210, 0, 0x080C, 1, 0) ++#define _MX6Q_PAD_KEY_COL3__ENET_CRS \ ++ IOMUX_PAD(0x05E0, 0x0210, 1, 0x0000, 0, 0) ++#define _MX6Q_PAD_KEY_COL3__HDMI_TX_DDC_SCL \ ++ IOMUX_PAD(0x05E0, 0x0210, 2, 0x0890, 1, 0) ++#define _MX6Q_PAD_KEY_COL3__KPP_COL_3 \ ++ IOMUX_PAD(0x05E0, 0x0210, 3, 0x0000, 0, 0) ++#define _MX6Q_PAD_KEY_COL3__I2C2_SCL \ ++ IOMUX_PAD(0x05E0, 0x0210, 4 | IOMUX_CONFIG_SION, 0x08A0, 1, 0) ++#define _MX6Q_PAD_KEY_COL3__GPIO_4_12 \ ++ IOMUX_PAD(0x05E0, 0x0210, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_KEY_COL3__SPDIF_IN1 \ ++ IOMUX_PAD(0x05E0, 0x0210, 6, 0x0914, 2, 0) ++#define _MX6Q_PAD_KEY_COL3__PL301_MX6QPER1_HADDR_5 \ ++ IOMUX_PAD(0x05E0, 0x0210, 7, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_KEY_ROW3__OSC32K_32K_OUT \ ++ IOMUX_PAD(0x05E4, 0x0214, 0, 0x0000, 0, 0) ++#define _MX6Q_PAD_KEY_ROW3__ASRC_ASRC_EXT_CLK \ ++ IOMUX_PAD(0x05E4, 0x0214, 1, 0x07B0, 0, 0) ++#define _MX6Q_PAD_KEY_ROW3__HDMI_TX_DDC_SDA \ ++ IOMUX_PAD(0x05E4, 0x0214, 2, 0x0894, 1, 0) ++#define _MX6Q_PAD_KEY_ROW3__KPP_ROW_3 \ ++ IOMUX_PAD(0x05E4, 0x0214, 3, 0x0000, 0, 0) ++#define _MX6Q_PAD_KEY_ROW3__I2C2_SDA \ ++ IOMUX_PAD(0x05E4, 0x0214, 4 | IOMUX_CONFIG_SION, 0x08A4, 1, 0) ++#define _MX6Q_PAD_KEY_ROW3__GPIO_4_13 \ ++ IOMUX_PAD(0x05E4, 0x0214, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_KEY_ROW3__USDHC1_VSELECT \ ++ IOMUX_PAD(0x05E4, 0x0214, 6, 0x0000, 0, 0) ++#define _MX6Q_PAD_KEY_ROW3__PL301_MX6QPER1_HADDR_6 \ ++ IOMUX_PAD(0x05E4, 0x0214, 7, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_KEY_COL4__CAN2_TXCAN \ ++ IOMUX_PAD(0x05E8, 0x0218, 0, 0x0000, 0, 0) ++#define _MX6Q_PAD_KEY_COL4__IPU1_SISG_4 \ ++ IOMUX_PAD(0x05E8, 0x0218, 1, 0x0000, 0, 0) ++#define _MX6Q_PAD_KEY_COL4__USBOH3_USBOTG_OC \ ++ IOMUX_PAD(0x05E8, 0x0218, 2, 0x0944, 1, 0) ++#define _MX6Q_PAD_KEY_COL4__KPP_COL_4 \ ++ IOMUX_PAD(0x05E8, 0x0218, 3, 0x0000, 0, 0) ++#define _MX6Q_PAD_KEY_COL4__UART5_CTS \ ++ IOMUX_PAD(0x05E8, 0x0218, 4, 0x0000, 0, 0) ++#define _MX6Q_PAD_KEY_COL4__UART5_RTS \ ++ IOMUX_PAD(0x05E8, 0x0218, 4, 0x093C, 0, 0) ++#define _MX6Q_PAD_KEY_COL4__GPIO_4_14 \ ++ IOMUX_PAD(0x05E8, 0x0218, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_KEY_COL4__MMDC_MMDC_DEBUG_49 \ ++ IOMUX_PAD(0x05E8, 0x0218, 6, 0x0000, 0, 0) ++#define _MX6Q_PAD_KEY_COL4__PL301_MX6QPER1_HADDR_7 \ ++ IOMUX_PAD(0x05E8, 0x0218, 7, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_KEY_ROW4__CAN2_RXCAN \ ++ IOMUX_PAD(0x05EC, 0x021C, 0, 0x07E8, 0, 0) ++#define _MX6Q_PAD_KEY_ROW4__IPU1_SISG_5 \ ++ IOMUX_PAD(0x05EC, 0x021C, 1, 0x0000, 0, 0) ++#define _MX6Q_PAD_KEY_ROW4__USBOH3_USBOTG_PWR \ ++ IOMUX_PAD(0x05EC, 0x021C, 2, 0x0000, 0, 0) ++#define _MX6Q_PAD_KEY_ROW4__KPP_ROW_4 \ ++ IOMUX_PAD(0x05EC, 0x021C, 3, 0x0000, 0, 0) ++#define _MX6Q_PAD_KEY_ROW4__UART5_CTS \ ++ IOMUX_PAD(0x05EC, 0x021C, 4, 0x0000, 1, 0) ++#define _MX6Q_PAD_KEY_ROW4__UART5_RTS \ ++ IOMUX_PAD(0x05EC, 0x021C, 4, 0x093C, 1, 0) ++#define _MX6Q_PAD_KEY_ROW4__GPIO_4_15 \ ++ IOMUX_PAD(0x05EC, 0x021C, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_KEY_ROW4__MMDC_MMDC_DEBUG_50 \ ++ IOMUX_PAD(0x05EC, 0x021C, 6, 0x0000, 0, 0) ++#define _MX6Q_PAD_KEY_ROW4__PL301_MX6QPER1_HADDR_8 \ ++ IOMUX_PAD(0x05EC, 0x021C, 7, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_GPIO_0__CCM_CLKO \ ++ IOMUX_PAD(0x05F0, 0x0220, 0, 0x0000, 0, 0) ++#define _MX6Q_PAD_GPIO_0__KPP_COL_5 \ ++ IOMUX_PAD(0x05F0, 0x0220, 2, 0x08E8, 0, 0) ++#define _MX6Q_PAD_GPIO_0__ASRC_ASRC_EXT_CLK \ ++ IOMUX_PAD(0x05F0, 0x0220, 3, 0x07B0, 1, 0) ++#define _MX6Q_PAD_GPIO_0__EPIT1_EPITO \ ++ IOMUX_PAD(0x05F0, 0x0220, 4, 0x0000, 0, 0) ++#define _MX6Q_PAD_GPIO_0__GPIO_1_0 \ ++ IOMUX_PAD(0x05F0, 0x0220, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_GPIO_0__USBOH3_USBH1_PWR \ ++ IOMUX_PAD(0x05F0, 0x0220, 6, 0x0000, 0, 0) ++#define _MX6Q_PAD_GPIO_0__SNVS_HP_WRAPPER_SNVS_VIO_5 \ ++ IOMUX_PAD(0x05F0, 0x0220, 7, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_GPIO_1__ESAI1_SCKR \ ++ IOMUX_PAD(0x05F4, 0x0224, 0, 0x086C, 1, 0) ++#define _MX6Q_PAD_GPIO_1__WDOG2_WDOG_B \ ++ IOMUX_PAD(0x05F4, 0x0224, 1, 0x0000, 0, 0) ++#define _MX6Q_PAD_GPIO_1__KPP_ROW_5 \ ++ IOMUX_PAD(0x05F4, 0x0224, 2, 0x08F4, 0, 0) ++#define _MX6Q_PAD_GPIO_1__PWM2_PWMO \ ++ IOMUX_PAD(0x05F4, 0x0224, 4, 0x0000, 0, 0) ++#define _MX6Q_PAD_GPIO_1__GPIO_1_1 \ ++ IOMUX_PAD(0x05F4, 0x0224, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_GPIO_1__USDHC1_CD \ ++ IOMUX_PAD(0x05F4, 0x0224, 6, 0x0000, 0, 0) ++#define _MX6Q_PAD_GPIO_1__SRC_TESTER_ACK \ ++ IOMUX_PAD(0x05F4, 0x0224, 7, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_GPIO_9__ESAI1_FSR \ ++ IOMUX_PAD(0x05F8, 0x0228, 0, 0x085C, 1, 0) ++#define _MX6Q_PAD_GPIO_9__WDOG1_WDOG_B \ ++ IOMUX_PAD(0x05F8, 0x0228, 1, 0x0000, 0, 0) ++#define _MX6Q_PAD_GPIO_9__KPP_COL_6 \ ++ IOMUX_PAD(0x05F8, 0x0228, 2, 0x08EC, 0, 0) ++#define _MX6Q_PAD_GPIO_9__CCM_REF_EN_B \ ++ IOMUX_PAD(0x05F8, 0x0228, 3, 0x0000, 0, 0) ++#define _MX6Q_PAD_GPIO_9__PWM1_PWMO \ ++ IOMUX_PAD(0x05F8, 0x0228, 4, 0x0000, 0, 0) ++#define _MX6Q_PAD_GPIO_9__GPIO_1_9 \ ++ IOMUX_PAD(0x05F8, 0x0228, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_GPIO_9__USDHC1_WP \ ++ IOMUX_PAD(0x05F8, 0x0228, 6, 0x094C, 1, 0) ++#define _MX6Q_PAD_GPIO_9__SRC_EARLY_RST \ ++ IOMUX_PAD(0x05F8, 0x0228, 7, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_GPIO_3__ESAI1_HCKR \ ++ IOMUX_PAD(0x05FC, 0x022C, 0, 0x0864, 1, 0) ++#define _MX6Q_PAD_GPIO_3__OBSERVE_MUX_OBSRV_INT_OUT0 \ ++ IOMUX_PAD(0x05FC, 0x022C, 1, 0x0000, 0, 0) ++#define _MX6Q_PAD_GPIO_3__I2C3_SCL \ ++ IOMUX_PAD(0x05FC, 0x022C, 2 | IOMUX_CONFIG_SION, 0x08A8, 1, 0) ++#define _MX6Q_PAD_GPIO_3__ANATOP_ANATOP_24M_OUT \ ++ IOMUX_PAD(0x05FC, 0x022C, 3, 0x0000, 0, 0) ++#define _MX6Q_PAD_GPIO_3__CCM_CLKO2 \ ++ IOMUX_PAD(0x05FC, 0x022C, 4, 0x0000, 0, 0) ++#define _MX6Q_PAD_GPIO_3__GPIO_1_3 \ ++ IOMUX_PAD(0x05FC, 0x022C, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_GPIO_3__USBOH3_USBH1_OC \ ++ IOMUX_PAD(0x05FC, 0x022C, 6, 0x0948, 1, 0) ++#define _MX6Q_PAD_GPIO_3__MLB_MLBCLK \ ++ IOMUX_PAD(0x05FC, 0x022C, 7, 0x0900, 1, 0) ++ ++#define _MX6Q_PAD_GPIO_6__ESAI1_SCKT \ ++ IOMUX_PAD(0x0600, 0x0230, 0, 0x0870, 1, 0) ++#define _MX6Q_PAD_GPIO_6__OBSERVE_MUX_OBSRV_INT_OUT1 \ ++ IOMUX_PAD(0x0600, 0x0230, 1, 0x0000, 0, 0) ++#define _MX6Q_PAD_GPIO_6__I2C3_SDA \ ++ IOMUX_PAD(0x0600, 0x0230, 2 | IOMUX_CONFIG_SION, 0x08AC, 1, 0) ++#define _MX6Q_PAD_GPIO_6__CCM_CCM_OUT_0 \ ++ IOMUX_PAD(0x0600, 0x0230, 3, 0x0000, 0, 0) ++#define _MX6Q_PAD_GPIO_6__CSU_CSU_INT_DEB \ ++ IOMUX_PAD(0x0600, 0x0230, 4, 0x0000, 0, 0) ++#define _MX6Q_PAD_GPIO_6__GPIO_1_6 \ ++ IOMUX_PAD(0x0600, 0x0230, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_GPIO_6__USDHC2_LCTL \ ++ IOMUX_PAD(0x0600, 0x0230, 6, 0x0000, 0, 0) ++#define _MX6Q_PAD_GPIO_6__MLB_MLBSIG \ ++ IOMUX_PAD(0x0600, 0x0230, 7, 0x0908, 1, 0) ++ ++#define _MX6Q_PAD_GPIO_2__ESAI1_FST \ ++ IOMUX_PAD(0x0604, 0x0234, 0, 0x0860, 1, 0) ++#define _MX6Q_PAD_GPIO_2__OBSERVE_MUX_OBSRV_INT_OUT2 \ ++ IOMUX_PAD(0x0604, 0x0234, 1, 0x0000, 0, 0) ++#define _MX6Q_PAD_GPIO_2__KPP_ROW_6 \ ++ IOMUX_PAD(0x0604, 0x0234, 2, 0x08F8, 1, 0) ++#define _MX6Q_PAD_GPIO_2__CCM_CCM_OUT_1 \ ++ IOMUX_PAD(0x0604, 0x0234, 3, 0x0000, 0, 0) ++#define _MX6Q_PAD_GPIO_2__CSU_CSU_ALARM_AUT_0 \ ++ IOMUX_PAD(0x0604, 0x0234, 4, 0x0000, 0, 0) ++#define _MX6Q_PAD_GPIO_2__GPIO_1_2 \ ++ IOMUX_PAD(0x0604, 0x0234, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_GPIO_2__USDHC2_WP \ ++ IOMUX_PAD(0x0604, 0x0234, 6, 0x0000, 0, 0) ++#define _MX6Q_PAD_GPIO_2__MLB_MLBDAT \ ++ IOMUX_PAD(0x0604, 0x0234, 7, 0x0904, 1, 0) ++ ++#define _MX6Q_PAD_GPIO_4__ESAI1_HCKT \ ++ IOMUX_PAD(0x0608, 0x0238, 0, 0x0868, 1, 0) ++#define _MX6Q_PAD_GPIO_4__OBSERVE_MUX_OBSRV_INT_OUT3 \ ++ IOMUX_PAD(0x0608, 0x0238, 1, 0x0000, 0, 0) ++#define _MX6Q_PAD_GPIO_4__KPP_COL_7 \ ++ IOMUX_PAD(0x0608, 0x0238, 2, 0x08F0, 1, 0) ++#define _MX6Q_PAD_GPIO_4__CCM_CCM_OUT_2 \ ++ IOMUX_PAD(0x0608, 0x0238, 3, 0x0000, 0, 0) ++#define _MX6Q_PAD_GPIO_4__CSU_CSU_ALARM_AUT_1 \ ++ IOMUX_PAD(0x0608, 0x0238, 4, 0x0000, 0, 0) ++#define _MX6Q_PAD_GPIO_4__GPIO_1_4 \ ++ IOMUX_PAD(0x0608, 0x0238, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_GPIO_4__USDHC2_CD \ ++ IOMUX_PAD(0x0608, 0x0238, 6, 0x0000, 0, 0) ++#define _MX6Q_PAD_GPIO_4__OCOTP_CTRL_WRAPPER_FUSE_LATCHED \ ++ IOMUX_PAD(0x0608, 0x0238, 7, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_GPIO_5__ESAI1_TX2_RX3 \ ++ IOMUX_PAD(0x060C, 0x023C, 0, 0x087C, 1, 0) ++#define _MX6Q_PAD_GPIO_5__OBSERVE_MUX_OBSRV_INT_OUT4 \ ++ IOMUX_PAD(0x060C, 0x023C, 1, 0x0000, 0, 0) ++#define _MX6Q_PAD_GPIO_5__KPP_ROW_7 \ ++ IOMUX_PAD(0x060C, 0x023C, 2, 0x08FC, 1, 0) ++#define _MX6Q_PAD_GPIO_5__CCM_CLKO \ ++ IOMUX_PAD(0x060C, 0x023C, 3, 0x0000, 0, 0) ++#define _MX6Q_PAD_GPIO_5__CSU_CSU_ALARM_AUT_2 \ ++ IOMUX_PAD(0x060C, 0x023C, 4, 0x0000, 0, 0) ++#define _MX6Q_PAD_GPIO_5__GPIO_1_5 \ ++ IOMUX_PAD(0x060C, 0x023C, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_GPIO_5__I2C3_SCL \ ++ IOMUX_PAD(0x060C, 0x023C, 6 | IOMUX_CONFIG_SION, 0x08A8, 2, 0) ++#define _MX6Q_PAD_GPIO_5__CHEETAH_EVENTI \ ++ IOMUX_PAD(0x060C, 0x023C, 7, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_GPIO_7__ESAI1_TX4_RX1 \ ++ IOMUX_PAD(0x0610, 0x0240, 0, 0x0884, 1, 0) ++#define _MX6Q_PAD_GPIO_7__ECSPI5_RDY \ ++ IOMUX_PAD(0x0610, 0x0240, 1, 0x0000, 0, 0) ++#define _MX6Q_PAD_GPIO_7__EPIT1_EPITO \ ++ IOMUX_PAD(0x0610, 0x0240, 2, 0x0000, 0, 0) ++#define _MX6Q_PAD_GPIO_7__CAN1_TXCAN \ ++ IOMUX_PAD(0x0610, 0x0240, 3, 0x0000, 0, 0) ++#define _MX6Q_PAD_GPIO_7__UART2_TXD \ ++ IOMUX_PAD(0x0610, 0x0240, 4, 0x0000, 0, 0) ++#define _MX6Q_PAD_GPIO_7__UART2_RXD \ ++ IOMUX_PAD(0x0610, 0x0240, 4, 0x0928, 2, 0) ++#define _MX6Q_PAD_GPIO_7__GPIO_1_7 \ ++ IOMUX_PAD(0x0610, 0x0240, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_GPIO_7__SPDIF_PLOCK \ ++ IOMUX_PAD(0x0610, 0x0240, 6, 0x0000, 0, 0) ++#define _MX6Q_PAD_GPIO_7__USBOH3_OTGUSB_HOST_MODE \ ++ IOMUX_PAD(0x0610, 0x0240, 7, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_GPIO_8__ESAI1_TX5_RX0 \ ++ IOMUX_PAD(0x0614, 0x0244, 0, 0x0888, 1, 0) ++#define _MX6Q_PAD_GPIO_8__ANATOP_ANATOP_32K_OUT \ ++ IOMUX_PAD(0x0614, 0x0244, 1, 0x0000, 0, 0) ++#define _MX6Q_PAD_GPIO_8__EPIT2_EPITO \ ++ IOMUX_PAD(0x0614, 0x0244, 2, 0x0000, 0, 0) ++#define _MX6Q_PAD_GPIO_8__CAN1_RXCAN \ ++ IOMUX_PAD(0x0614, 0x0244, 3, 0x07E4, 1, 0) ++#define _MX6Q_PAD_GPIO_8__UART2_TXD \ ++ IOMUX_PAD(0x0614, 0x0244, 4, 0x0000, 0, 0) ++#define _MX6Q_PAD_GPIO_8__UART2_RXD \ ++ IOMUX_PAD(0x0614, 0x0244, 4, 0x0928, 3, 0) ++#define _MX6Q_PAD_GPIO_8__GPIO_1_8 \ ++ IOMUX_PAD(0x0614, 0x0244, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_GPIO_8__SPDIF_SRCLK \ ++ IOMUX_PAD(0x0614, 0x0244, 6, 0x0000, 0, 0) ++#define _MX6Q_PAD_GPIO_8__USBOH3_OTGUSB_PWRCTL_WAKEUP \ ++ IOMUX_PAD(0x0614, 0x0244, 7, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_GPIO_16__ESAI1_TX3_RX2 \ ++ IOMUX_PAD(0x0618, 0x0248, 0, 0x0880, 1, 0) ++#define _MX6Q_PAD_GPIO_16__ENET_1588_EVENT2_IN \ ++ IOMUX_PAD(0x0618, 0x0248, 1, 0x0000, 0, 0) ++#define _MX6Q_PAD_GPIO_16__ENET_ANATOP_ETHERNET_REF_OUT \ ++ IOMUX_PAD(0x0618, 0x0248, 0x12, 0x083C, 1, 0) ++#define _MX6Q_PAD_GPIO_16__USDHC1_LCTL \ ++ IOMUX_PAD(0x0618, 0x0248, 3, 0x0000, 0, 0) ++#define _MX6Q_PAD_GPIO_16__SPDIF_IN1 \ ++ IOMUX_PAD(0x0618, 0x0248, 4, 0x0914, 3, 0) ++#define _MX6Q_PAD_GPIO_16__GPIO_7_11 \ ++ IOMUX_PAD(0x0618, 0x0248, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_GPIO_16__I2C3_SDA \ ++ IOMUX_PAD(0x0618, 0x0248, 6 | IOMUX_CONFIG_SION, 0x08AC, 2, 0) ++#define _MX6Q_PAD_GPIO_16__SJC_DE_B \ ++ IOMUX_PAD(0x0618, 0x0248, 7, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_GPIO_17__ESAI1_TX0 \ ++ IOMUX_PAD(0x061C, 0x024C, 0, 0x0874, 0, 0) ++#define _MX6Q_PAD_GPIO_17__ENET_1588_EVENT3_IN \ ++ IOMUX_PAD(0x061C, 0x024C, 1, 0x0000, 0, 0) ++#define _MX6Q_PAD_GPIO_17__CCM_PMIC_RDY \ ++ IOMUX_PAD(0x061C, 0x024C, 2, 0x07F0, 1, 0) ++#define _MX6Q_PAD_GPIO_17__SDMA_SDMA_EXT_EVENT_0 \ ++ IOMUX_PAD(0x061C, 0x024C, 3, 0x090C, 1, 0) ++#define _MX6Q_PAD_GPIO_17__SPDIF_OUT1 \ ++ IOMUX_PAD(0x061C, 0x024C, 4, 0x0000, 0, 0) ++#define _MX6Q_PAD_GPIO_17__GPIO_7_12 \ ++ IOMUX_PAD(0x061C, 0x024C, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_GPIO_17__SJC_JTAG_ACT \ ++ IOMUX_PAD(0x061C, 0x024C, 7, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_GPIO_18__ESAI1_TX1 \ ++ IOMUX_PAD(0x0620, 0x0250, 0, 0x0878, 0, 0) ++#define _MX6Q_PAD_GPIO_18__ENET_RX_CLK \ ++ IOMUX_PAD(0x0620, 0x0250, 1, 0x0844, 1, 0) ++#define _MX6Q_PAD_GPIO_18__USDHC3_VSELECT \ ++ IOMUX_PAD(0x0620, 0x0250, 2, 0x0000, 0, 0) ++#define _MX6Q_PAD_GPIO_18__SDMA_SDMA_EXT_EVENT_1 \ ++ IOMUX_PAD(0x0620, 0x0250, 3, 0x0910, 1, 0) ++#define _MX6Q_PAD_GPIO_18__ASRC_ASRC_EXT_CLK \ ++ IOMUX_PAD(0x0620, 0x0250, 4, 0x07B0, 2, 0) ++#define _MX6Q_PAD_GPIO_18__GPIO_7_13 \ ++ IOMUX_PAD(0x0620, 0x0250, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_GPIO_18__SNVS_HP_WRAPPER_SNVS_VIO_5_CTL \ ++ IOMUX_PAD(0x0620, 0x0250, 6, 0x0000, 0, 0) ++#define _MX6Q_PAD_GPIO_18__SRC_SYSTEM_RST \ ++ IOMUX_PAD(0x0620, 0x0250, 7, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_GPIO_19__KPP_COL_5 \ ++ IOMUX_PAD(0x0624, 0x0254, 0, 0x08E8, 1, 0) ++#define _MX6Q_PAD_GPIO_19__ENET_1588_EVENT0_OUT \ ++ IOMUX_PAD(0x0624, 0x0254, 1, 0x0000, 0, 0) ++#define _MX6Q_PAD_GPIO_19__SPDIF_OUT1 \ ++ IOMUX_PAD(0x0624, 0x0254, 2, 0x0000, 0, 0) ++#define _MX6Q_PAD_GPIO_19__CCM_CLKO \ ++ IOMUX_PAD(0x0624, 0x0254, 3, 0x0000, 0, 0) ++#define _MX6Q_PAD_GPIO_19__ECSPI1_RDY \ ++ IOMUX_PAD(0x0624, 0x0254, 4, 0x0000, 0, 0) ++#define _MX6Q_PAD_GPIO_19__GPIO_4_5 \ ++ IOMUX_PAD(0x0624, 0x0254, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_GPIO_19__ENET_TX_ER \ ++ IOMUX_PAD(0x0624, 0x0254, 6, 0x0000, 0, 0) ++#define _MX6Q_PAD_GPIO_19__SRC_INT_BOOT \ ++ IOMUX_PAD(0x0624, 0x0254, 7, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK \ ++ IOMUX_PAD(0x0628, 0x0258, 0, 0x0000, 0, 0) ++#define _MX6Q_PAD_CSI0_PIXCLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_12 \ ++ IOMUX_PAD(0x0628, 0x0258, 2, 0x0000, 0, 0) ++#define _MX6Q_PAD_CSI0_PIXCLK__SDMA_DEBUG_PC_0 \ ++ IOMUX_PAD(0x0628, 0x0258, 4, 0x0000, 0, 0) ++#define _MX6Q_PAD_CSI0_PIXCLK__GPIO_5_18 \ ++ IOMUX_PAD(0x0628, 0x0258, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_CSI0_PIXCLK__MMDC_MMDC_DEBUG_29 \ ++ IOMUX_PAD(0x0628, 0x0258, 6, 0x0000, 0, 0) ++#define _MX6Q_PAD_CSI0_PIXCLK__CHEETAH_EVENTO \ ++ IOMUX_PAD(0x0628, 0x0258, 7, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC \ ++ IOMUX_PAD(0x062C, 0x025C, 0, 0x0000, 0, 0) ++#define _MX6Q_PAD_CSI0_MCLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_13 \ ++ IOMUX_PAD(0x062C, 0x025C, 2, 0x0000, 0, 0) ++#define _MX6Q_PAD_CSI0_MCLK__CCM_CLKO \ ++ IOMUX_PAD(0x062C, 0x025C, 3, 0x0000, 0, 0) ++#define _MX6Q_PAD_CSI0_MCLK__SDMA_DEBUG_PC_1 \ ++ IOMUX_PAD(0x062C, 0x025C, 4, 0x0000, 0, 0) ++#define _MX6Q_PAD_CSI0_MCLK__GPIO_5_19 \ ++ IOMUX_PAD(0x062C, 0x025C, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_CSI0_MCLK__MMDC_MMDC_DEBUG_30 \ ++ IOMUX_PAD(0x062C, 0x025C, 6, 0x0000, 0, 0) ++#define _MX6Q_PAD_CSI0_MCLK__CHEETAH_TRCTL \ ++ IOMUX_PAD(0x062C, 0x025C, 7, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN \ ++ IOMUX_PAD(0x0630, 0x0260, 0, 0x0000, 0, 0) ++#define _MX6Q_PAD_CSI0_DATA_EN__WEIM_WEIM_D_0 \ ++ IOMUX_PAD(0x0630, 0x0260, 1, 0x0000, 0, 0) ++#define _MX6Q_PAD_CSI0_DATA_EN__PCIE_CTRL_DIAG_STATUS_BUS_MUX_14 \ ++ IOMUX_PAD(0x0630, 0x0260, 2, 0x0000, 0, 0) ++#define _MX6Q_PAD_CSI0_DATA_EN__SDMA_DEBUG_PC_2 \ ++ IOMUX_PAD(0x0630, 0x0260, 4, 0x0000, 0, 0) ++#define _MX6Q_PAD_CSI0_DATA_EN__GPIO_5_20 \ ++ IOMUX_PAD(0x0630, 0x0260, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_CSI0_DATA_EN__MMDC_MMDC_DEBUG_31 \ ++ IOMUX_PAD(0x0630, 0x0260, 6, 0x0000, 0, 0) ++#define _MX6Q_PAD_CSI0_DATA_EN__CHEETAH_TRCLK \ ++ IOMUX_PAD(0x0630, 0x0260, 7, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC \ ++ IOMUX_PAD(0x0634, 0x0264, 0, 0x0000, 0, 0) ++#define _MX6Q_PAD_CSI0_VSYNC__WEIM_WEIM_D_1 \ ++ IOMUX_PAD(0x0634, 0x0264, 1, 0x0000, 0, 0) ++#define _MX6Q_PAD_CSI0_VSYNC__PCIE_CTRL_DIAG_STATUS_BUS_MUX_15 \ ++ IOMUX_PAD(0x0634, 0x0264, 2, 0x0000, 0, 0) ++#define _MX6Q_PAD_CSI0_VSYNC__SDMA_DEBUG_PC_3 \ ++ IOMUX_PAD(0x0634, 0x0264, 4, 0x0000, 0, 0) ++#define _MX6Q_PAD_CSI0_VSYNC__GPIO_5_21 \ ++ IOMUX_PAD(0x0634, 0x0264, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_CSI0_VSYNC__MMDC_MMDC_DEBUG_32 \ ++ IOMUX_PAD(0x0634, 0x0264, 6, 0x0000, 0, 0) ++#define _MX6Q_PAD_CSI0_VSYNC__CHEETAH_TRACE_0 \ ++ IOMUX_PAD(0x0634, 0x0264, 7, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_CSI0_DAT4__IPU1_CSI0_D_4 \ ++ IOMUX_PAD(0x0638, 0x0268, 0, 0x0000, 0, 0) ++#define _MX6Q_PAD_CSI0_DAT4__WEIM_WEIM_D_2 \ ++ IOMUX_PAD(0x0638, 0x0268, 1, 0x0000, 0, 0) ++#define _MX6Q_PAD_CSI0_DAT4__ECSPI1_SCLK \ ++ IOMUX_PAD(0x0638, 0x0268, 2, 0x07F4, 3, 0) ++#define _MX6Q_PAD_CSI0_DAT4__KPP_COL_5 \ ++ IOMUX_PAD(0x0638, 0x0268, 3, 0x08E8, 2, 0) ++#define _MX6Q_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC \ ++ IOMUX_PAD(0x0638, 0x0268, 4, 0x0000, 0, 0) ++#define _MX6Q_PAD_CSI0_DAT4__GPIO_5_22 \ ++ IOMUX_PAD(0x0638, 0x0268, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_CSI0_DAT4__MMDC_MMDC_DEBUG_43 \ ++ IOMUX_PAD(0x0638, 0x0268, 6, 0x0000, 0, 0) ++#define _MX6Q_PAD_CSI0_DAT4__CHEETAH_TRACE_1 \ ++ IOMUX_PAD(0x0638, 0x0268, 7, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_CSI0_DAT5__IPU1_CSI0_D_5 \ ++ IOMUX_PAD(0x063C, 0x026C, 0, 0x0000, 0, 0) ++#define _MX6Q_PAD_CSI0_DAT5__WEIM_WEIM_D_3 \ ++ IOMUX_PAD(0x063C, 0x026C, 1, 0x0000, 0, 0) ++#define _MX6Q_PAD_CSI0_DAT5__ECSPI1_MOSI \ ++ IOMUX_PAD(0x063C, 0x026C, 2, 0x07FC, 3, 0) ++#define _MX6Q_PAD_CSI0_DAT5__KPP_ROW_5 \ ++ IOMUX_PAD(0x063C, 0x026C, 3, 0x08F4, 1, 0) ++#define _MX6Q_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD \ ++ IOMUX_PAD(0x063C, 0x026C, 4, 0x0000, 0, 0) ++#define _MX6Q_PAD_CSI0_DAT5__GPIO_5_23 \ ++ IOMUX_PAD(0x063C, 0x026C, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_CSI0_DAT5__MMDC_MMDC_DEBUG_44 \ ++ IOMUX_PAD(0x063C, 0x026C, 6, 0x0000, 0, 0) ++#define _MX6Q_PAD_CSI0_DAT5__CHEETAH_TRACE_2 \ ++ IOMUX_PAD(0x063C, 0x026C, 7, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_CSI0_DAT6__IPU1_CSI0_D_6 \ ++ IOMUX_PAD(0x0640, 0x0270, 0, 0x0000, 0, 0) ++#define _MX6Q_PAD_CSI0_DAT6__WEIM_WEIM_D_4 \ ++ IOMUX_PAD(0x0640, 0x0270, 1, 0x0000, 0, 0) ++#define _MX6Q_PAD_CSI0_DAT6__ECSPI1_MISO \ ++ IOMUX_PAD(0x0640, 0x0270, 2, 0x07F8, 3, 0) ++#define _MX6Q_PAD_CSI0_DAT6__KPP_COL_6 \ ++ IOMUX_PAD(0x0640, 0x0270, 3, 0x08EC, 1, 0) ++#define _MX6Q_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS \ ++ IOMUX_PAD(0x0640, 0x0270, 4, 0x0000, 0, 0) ++#define _MX6Q_PAD_CSI0_DAT6__GPIO_5_24 \ ++ IOMUX_PAD(0x0640, 0x0270, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_CSI0_DAT6__MMDC_MMDC_DEBUG_45 \ ++ IOMUX_PAD(0x0640, 0x0270, 6, 0x0000, 0, 0) ++#define _MX6Q_PAD_CSI0_DAT6__CHEETAH_TRACE_3 \ ++ IOMUX_PAD(0x0640, 0x0270, 7, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_CSI0_DAT7__IPU1_CSI0_D_7 \ ++ IOMUX_PAD(0x0644, 0x0274, 0, 0x0000, 0, 0) ++#define _MX6Q_PAD_CSI0_DAT7__WEIM_WEIM_D_5 \ ++ IOMUX_PAD(0x0644, 0x0274, 1, 0x0000, 0, 0) ++#define _MX6Q_PAD_CSI0_DAT7__ECSPI1_SS0 \ ++ IOMUX_PAD(0x0644, 0x0274, 2, 0x0800, 3, 0) ++#define _MX6Q_PAD_CSI0_DAT7__KPP_ROW_6 \ ++ IOMUX_PAD(0x0644, 0x0274, 3, 0x08F8, 2, 0) ++#define _MX6Q_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD \ ++ IOMUX_PAD(0x0644, 0x0274, 4, 0x0000, 0, 0) ++#define _MX6Q_PAD_CSI0_DAT7__GPIO_5_25 \ ++ IOMUX_PAD(0x0644, 0x0274, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_CSI0_DAT7__MMDC_MMDC_DEBUG_46 \ ++ IOMUX_PAD(0x0644, 0x0274, 6, 0x0000, 0, 0) ++#define _MX6Q_PAD_CSI0_DAT7__CHEETAH_TRACE_4 \ ++ IOMUX_PAD(0x0644, 0x0274, 7, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_CSI0_DAT8__IPU1_CSI0_D_8 \ ++ IOMUX_PAD(0x0648, 0x0278, 0, 0x0000, 0, 0) ++#define _MX6Q_PAD_CSI0_DAT8__WEIM_WEIM_D_6 \ ++ IOMUX_PAD(0x0648, 0x0278, 1, 0x0000, 0, 0) ++#define _MX6Q_PAD_CSI0_DAT8__ECSPI2_SCLK \ ++ IOMUX_PAD(0x0648, 0x0278, 2, 0x0810, 2, 0) ++#define _MX6Q_PAD_CSI0_DAT8__KPP_COL_7 \ ++ IOMUX_PAD(0x0648, 0x0278, 3, 0x08F0, 2, 0) ++#define _MX6Q_PAD_CSI0_DAT8__I2C1_SDA \ ++ IOMUX_PAD(0x0648, 0x0278, 4 | IOMUX_CONFIG_SION, 0x089C, 1, 0) ++#define _MX6Q_PAD_CSI0_DAT8__GPIO_5_26 \ ++ IOMUX_PAD(0x0648, 0x0278, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_CSI0_DAT8__MMDC_MMDC_DEBUG_47 \ ++ IOMUX_PAD(0x0648, 0x0278, 6, 0x0000, 0, 0) ++#define _MX6Q_PAD_CSI0_DAT8__CHEETAH_TRACE_5 \ ++ IOMUX_PAD(0x0648, 0x0278, 7, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_CSI0_DAT9__IPU1_CSI0_D_9 \ ++ IOMUX_PAD(0x064C, 0x027C, 0, 0x0000, 0, 0) ++#define _MX6Q_PAD_CSI0_DAT9__WEIM_WEIM_D_7 \ ++ IOMUX_PAD(0x064C, 0x027C, 1, 0x0000, 0, 0) ++#define _MX6Q_PAD_CSI0_DAT9__ECSPI2_MOSI \ ++ IOMUX_PAD(0x064C, 0x027C, 2, 0x0818, 2, 0) ++#define _MX6Q_PAD_CSI0_DAT9__KPP_ROW_7 \ ++ IOMUX_PAD(0x064C, 0x027C, 3, 0x08FC, 2, 0) ++#define _MX6Q_PAD_CSI0_DAT9__I2C1_SCL \ ++ IOMUX_PAD(0x064C, 0x027C, 4 | IOMUX_CONFIG_SION, 0x0898, 1, 0) ++#define _MX6Q_PAD_CSI0_DAT9__GPIO_5_27 \ ++ IOMUX_PAD(0x064C, 0x027C, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_CSI0_DAT9__MMDC_MMDC_DEBUG_48 \ ++ IOMUX_PAD(0x064C, 0x027C, 6, 0x0000, 0, 0) ++#define _MX6Q_PAD_CSI0_DAT9__CHEETAH_TRACE_6 \ ++ IOMUX_PAD(0x064C, 0x027C, 7, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_CSI0_DAT10__IPU1_CSI0_D_10 \ ++ IOMUX_PAD(0x0650, 0x0280, 0, 0x0000, 0, 0) ++#define _MX6Q_PAD_CSI0_DAT10__AUDMUX_AUD3_RXC \ ++ IOMUX_PAD(0x0650, 0x0280, 1, 0x0000, 0, 0) ++#define _MX6Q_PAD_CSI0_DAT10__ECSPI2_MISO \ ++ IOMUX_PAD(0x0650, 0x0280, 2, 0x0814, 2, 0) ++#define _MX6Q_PAD_CSI0_DAT10__UART1_TXD \ ++ IOMUX_PAD(0x0650, 0x0280, 3, 0x0000, 0, 0) ++#define _MX6Q_PAD_CSI0_DAT10__UART1_RXD \ ++ IOMUX_PAD(0x0650, 0x0280, 3, 0x0920, 0, 0) ++#define _MX6Q_PAD_CSI0_DAT10__SDMA_DEBUG_PC_4 \ ++ IOMUX_PAD(0x0650, 0x0280, 4, 0x0000, 0, 0) ++#define _MX6Q_PAD_CSI0_DAT10__GPIO_5_28 \ ++ IOMUX_PAD(0x0650, 0x0280, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_CSI0_DAT10__MMDC_MMDC_DEBUG_33 \ ++ IOMUX_PAD(0x0650, 0x0280, 6, 0x0000, 0, 0) ++#define _MX6Q_PAD_CSI0_DAT10__CHEETAH_TRACE_7 \ ++ IOMUX_PAD(0x0650, 0x0280, 7, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_CSI0_DAT11__IPU1_CSI0_D_11 \ ++ IOMUX_PAD(0x0654, 0x0284, 0, 0x0000, 0, 0) ++#define _MX6Q_PAD_CSI0_DAT11__AUDMUX_AUD3_RXFS \ ++ IOMUX_PAD(0x0654, 0x0284, 1, 0x0000, 0, 0) ++#define _MX6Q_PAD_CSI0_DAT11__ECSPI2_SS0 \ ++ IOMUX_PAD(0x0654, 0x0284, 2, 0x081C, 2, 0) ++#define _MX6Q_PAD_CSI0_DAT11__UART1_TXD \ ++ IOMUX_PAD(0x0654, 0x0284, 3, 0x0000, 0, 0) ++#define _MX6Q_PAD_CSI0_DAT11__UART1_RXD \ ++ IOMUX_PAD(0x0654, 0x0284, 3, 0x0920, 1, 0) ++#define _MX6Q_PAD_CSI0_DAT11__SDMA_DEBUG_PC_5 \ ++ IOMUX_PAD(0x0654, 0x0284, 4, 0x0000, 0, 0) ++#define _MX6Q_PAD_CSI0_DAT11__GPIO_5_29 \ ++ IOMUX_PAD(0x0654, 0x0284, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_CSI0_DAT11__MMDC_MMDC_DEBUG_34 \ ++ IOMUX_PAD(0x0654, 0x0284, 6, 0x0000, 0, 0) ++#define _MX6Q_PAD_CSI0_DAT11__CHEETAH_TRACE_8 \ ++ IOMUX_PAD(0x0654, 0x0284, 7, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_CSI0_DAT12__IPU1_CSI0_D_12 \ ++ IOMUX_PAD(0x0658, 0x0288, 0, 0x0000, 0, 0) ++#define _MX6Q_PAD_CSI0_DAT12__WEIM_WEIM_D_8 \ ++ IOMUX_PAD(0x0658, 0x0288, 1, 0x0000, 0, 0) ++#define _MX6Q_PAD_CSI0_DAT12__PCIE_CTRL_DIAG_STATUS_BUS_MUX_16 \ ++ IOMUX_PAD(0x0658, 0x0288, 2, 0x0000, 0, 0) ++#define _MX6Q_PAD_CSI0_DAT12__UART4_TXD \ ++ IOMUX_PAD(0x0658, 0x0288, 3, 0x0000, 0, 0) ++#define _MX6Q_PAD_CSI0_DAT12__UART4_RXD \ ++ IOMUX_PAD(0x0658, 0x0288, 3, 0x0938, 2, 0) ++#define _MX6Q_PAD_CSI0_DAT12__SDMA_DEBUG_PC_6 \ ++ IOMUX_PAD(0x0658, 0x0288, 4, 0x0000, 0, 0) ++#define _MX6Q_PAD_CSI0_DAT12__GPIO_5_30 \ ++ IOMUX_PAD(0x0658, 0x0288, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_CSI0_DAT12__MMDC_MMDC_DEBUG_35 \ ++ IOMUX_PAD(0x0658, 0x0288, 6, 0x0000, 0, 0) ++#define _MX6Q_PAD_CSI0_DAT12__CHEETAH_TRACE_9 \ ++ IOMUX_PAD(0x0658, 0x0288, 7, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_CSI0_DAT13__IPU1_CSI0_D_13 \ ++ IOMUX_PAD(0x065C, 0x028C, 0, 0x0000, 0, 0) ++#define _MX6Q_PAD_CSI0_DAT13__WEIM_WEIM_D_9 \ ++ IOMUX_PAD(0x065C, 0x028C, 1, 0x0000, 0, 0) ++#define _MX6Q_PAD_CSI0_DAT13__PCIE_CTRL_DIAG_STATUS_BUS_MUX_17 \ ++ IOMUX_PAD(0x065C, 0x028C, 2, 0x0000, 0, 0) ++#define _MX6Q_PAD_CSI0_DAT13__UART4_TXD \ ++ IOMUX_PAD(0x065C, 0x028C, 3, 0x0000, 0, 0) ++#define _MX6Q_PAD_CSI0_DAT13__UART4_RXD \ ++ IOMUX_PAD(0x065C, 0x028C, 3, 0x0938, 3, 0) ++#define _MX6Q_PAD_CSI0_DAT13__SDMA_DEBUG_PC_7 \ ++ IOMUX_PAD(0x065C, 0x028C, 4, 0x0000, 0, 0) ++#define _MX6Q_PAD_CSI0_DAT13__GPIO_5_31 \ ++ IOMUX_PAD(0x065C, 0x028C, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_CSI0_DAT13__MMDC_MMDC_DEBUG_36 \ ++ IOMUX_PAD(0x065C, 0x028C, 6, 0x0000, 0, 0) ++#define _MX6Q_PAD_CSI0_DAT13__CHEETAH_TRACE_10 \ ++ IOMUX_PAD(0x065C, 0x028C, 7, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_CSI0_DAT14__IPU1_CSI0_D_14 \ ++ IOMUX_PAD(0x0660, 0x0290, 0, 0x0000, 0, 0) ++#define _MX6Q_PAD_CSI0_DAT14__WEIM_WEIM_D_10 \ ++ IOMUX_PAD(0x0660, 0x0290, 1, 0x0000, 0, 0) ++#define _MX6Q_PAD_CSI0_DAT14__PCIE_CTRL_DIAG_STATUS_BUS_MUX_18 \ ++ IOMUX_PAD(0x0660, 0x0290, 2, 0x0000, 0, 0) ++#define _MX6Q_PAD_CSI0_DAT14__UART5_TXD \ ++ IOMUX_PAD(0x0660, 0x0290, 3, 0x0000, 0, 0) ++#define _MX6Q_PAD_CSI0_DAT14__UART5_RXD \ ++ IOMUX_PAD(0x0660, 0x0290, 3, 0x0940, 2, 0) ++#define _MX6Q_PAD_CSI0_DAT14__SDMA_DEBUG_PC_8 \ ++ IOMUX_PAD(0x0660, 0x0290, 4, 0x0000, 0, 0) ++#define _MX6Q_PAD_CSI0_DAT14__GPIO_6_0 \ ++ IOMUX_PAD(0x0660, 0x0290, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_CSI0_DAT14__MMDC_MMDC_DEBUG_37 \ ++ IOMUX_PAD(0x0660, 0x0290, 6, 0x0000, 0, 0) ++#define _MX6Q_PAD_CSI0_DAT14__CHEETAH_TRACE_11 \ ++ IOMUX_PAD(0x0660, 0x0290, 7, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_CSI0_DAT15__IPU1_CSI0_D_15 \ ++ IOMUX_PAD(0x0664, 0x0294, 0, 0x0000, 0, 0) ++#define _MX6Q_PAD_CSI0_DAT15__WEIM_WEIM_D_11 \ ++ IOMUX_PAD(0x0664, 0x0294, 1, 0x0000, 0, 0) ++#define _MX6Q_PAD_CSI0_DAT15__PCIE_CTRL_DIAG_STATUS_BUS_MUX_19 \ ++ IOMUX_PAD(0x0664, 0x0294, 2, 0x0000, 0, 0) ++#define _MX6Q_PAD_CSI0_DAT15__UART5_TXD \ ++ IOMUX_PAD(0x0664, 0x0294, 3, 0x0000, 0, 0) ++#define _MX6Q_PAD_CSI0_DAT15__UART5_RXD \ ++ IOMUX_PAD(0x0664, 0x0294, 3, 0x0940, 3, 0) ++#define _MX6Q_PAD_CSI0_DAT15__SDMA_DEBUG_PC_9 \ ++ IOMUX_PAD(0x0664, 0x0294, 4, 0x0000, 0, 0) ++#define _MX6Q_PAD_CSI0_DAT15__GPIO_6_1 \ ++ IOMUX_PAD(0x0664, 0x0294, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_CSI0_DAT15__MMDC_MMDC_DEBUG_38 \ ++ IOMUX_PAD(0x0664, 0x0294, 6, 0x0000, 0, 0) ++#define _MX6Q_PAD_CSI0_DAT15__CHEETAH_TRACE_12 \ ++ IOMUX_PAD(0x0664, 0x0294, 7, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_CSI0_DAT16__IPU1_CSI0_D_16 \ ++ IOMUX_PAD(0x0668, 0x0298, 0, 0x0000, 0, 0) ++#define _MX6Q_PAD_CSI0_DAT16__WEIM_WEIM_D_12 \ ++ IOMUX_PAD(0x0668, 0x0298, 1, 0x0000, 0, 0) ++#define _MX6Q_PAD_CSI0_DAT16__PCIE_CTRL_DIAG_STATUS_BUS_MUX_20 \ ++ IOMUX_PAD(0x0668, 0x0298, 2, 0x0000, 0, 0) ++#define _MX6Q_PAD_CSI0_DAT16__UART4_CTS \ ++ IOMUX_PAD(0x0668, 0x0298, 3, 0x0000, 0, 0) ++#define _MX6Q_PAD_CSI0_DAT16__UART4_RTS \ ++ IOMUX_PAD(0x0668, 0x0298, 3, 0x0934, 0, 0) ++#define _MX6Q_PAD_CSI0_DAT16__SDMA_DEBUG_PC_10 \ ++ IOMUX_PAD(0x0668, 0x0298, 4, 0x0000, 0, 0) ++#define _MX6Q_PAD_CSI0_DAT16__GPIO_6_2 \ ++ IOMUX_PAD(0x0668, 0x0298, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_CSI0_DAT16__MMDC_MMDC_DEBUG_39 \ ++ IOMUX_PAD(0x0668, 0x0298, 6, 0x0000, 0, 0) ++#define _MX6Q_PAD_CSI0_DAT16__CHEETAH_TRACE_13 \ ++ IOMUX_PAD(0x0668, 0x0298, 7, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_CSI0_DAT17__IPU1_CSI0_D_17 \ ++ IOMUX_PAD(0x066C, 0x029C, 0, 0x0000, 0, 0) ++#define _MX6Q_PAD_CSI0_DAT17__WEIM_WEIM_D_13 \ ++ IOMUX_PAD(0x066C, 0x029C, 1, 0x0000, 0, 0) ++#define _MX6Q_PAD_CSI0_DAT17__PCIE_CTRL_DIAG_STATUS_BUS_MUX_21 \ ++ IOMUX_PAD(0x066C, 0x029C, 2, 0x0000, 0, 0) ++#define _MX6Q_PAD_CSI0_DAT17__UART4_CTS \ ++ IOMUX_PAD(0x066C, 0x029C, 3, 0x0000, 1, 0) ++#define _MX6Q_PAD_CSI0_DAT17__UART4_RTS \ ++ IOMUX_PAD(0x066C, 0x029C, 3, 0x0934, 1, 0) ++#define _MX6Q_PAD_CSI0_DAT17__SDMA_DEBUG_PC_11 \ ++ IOMUX_PAD(0x066C, 0x029C, 4, 0x0000, 0, 0) ++#define _MX6Q_PAD_CSI0_DAT17__GPIO_6_3 \ ++ IOMUX_PAD(0x066C, 0x029C, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_CSI0_DAT17__MMDC_MMDC_DEBUG_40 \ ++ IOMUX_PAD(0x066C, 0x029C, 6, 0x0000, 0, 0) ++#define _MX6Q_PAD_CSI0_DAT17__CHEETAH_TRACE_14 \ ++ IOMUX_PAD(0x066C, 0x029C, 7, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_CSI0_DAT18__IPU1_CSI0_D_18 \ ++ IOMUX_PAD(0x0670, 0x02A0, 0, 0x0000, 0, 0) ++#define _MX6Q_PAD_CSI0_DAT18__WEIM_WEIM_D_14 \ ++ IOMUX_PAD(0x0670, 0x02A0, 1, 0x0000, 0, 0) ++#define _MX6Q_PAD_CSI0_DAT18__PCIE_CTRL_DIAG_STATUS_BUS_MUX_22 \ ++ IOMUX_PAD(0x0670, 0x02A0, 2, 0x0000, 0, 0) ++#define _MX6Q_PAD_CSI0_DAT18__UART5_CTS \ ++ IOMUX_PAD(0x0670, 0x02A0, 3, 0x0000, 0, 0) ++#define _MX6Q_PAD_CSI0_DAT18__UART5_RTS \ ++ IOMUX_PAD(0x0670, 0x02A0, 3, 0x093C, 2, 0) ++#define _MX6Q_PAD_CSI0_DAT18__SDMA_DEBUG_PC_12 \ ++ IOMUX_PAD(0x0670, 0x02A0, 4, 0x0000, 0, 0) ++#define _MX6Q_PAD_CSI0_DAT18__GPIO_6_4 \ ++ IOMUX_PAD(0x0670, 0x02A0, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_CSI0_DAT18__MMDC_MMDC_DEBUG_41 \ ++ IOMUX_PAD(0x0670, 0x02A0, 6, 0x0000, 0, 0) ++#define _MX6Q_PAD_CSI0_DAT18__CHEETAH_TRACE_15 \ ++ IOMUX_PAD(0x0670, 0x02A0, 7, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_CSI0_DAT19__IPU1_CSI0_D_19 \ ++ IOMUX_PAD(0x0674, 0x02A4, 0, 0x0000, 0, 0) ++#define _MX6Q_PAD_CSI0_DAT19__WEIM_WEIM_D_15 \ ++ IOMUX_PAD(0x0674, 0x02A4, 1, 0x0000, 0, 0) ++#define _MX6Q_PAD_CSI0_DAT19__PCIE_CTRL_DIAG_STATUS_BUS_MUX_23 \ ++ IOMUX_PAD(0x0674, 0x02A4, 2, 0x0000, 0, 0) ++#define _MX6Q_PAD_CSI0_DAT19__UART5_CTS \ ++ IOMUX_PAD(0x0674, 0x02A4, 3, 0x0000, 3, 0) ++#define _MX6Q_PAD_CSI0_DAT19__UART5_RTS \ ++ IOMUX_PAD(0x0674, 0x02A4, 3, 0x093C, 3, 0) ++#define _MX6Q_PAD_CSI0_DAT19__SDMA_DEBUG_PC_13 \ ++ IOMUX_PAD(0x0674, 0x02A4, 4, 0x0000, 0, 0) ++#define _MX6Q_PAD_CSI0_DAT19__GPIO_6_5 \ ++ IOMUX_PAD(0x0674, 0x02A4, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_CSI0_DAT19__MMDC_MMDC_DEBUG_42 \ ++ IOMUX_PAD(0x0674, 0x02A4, 6, 0x0000, 0, 0) ++#define _MX6Q_PAD_CSI0_DAT19__ANATOP_ANATOP_TESTO_9 \ ++ IOMUX_PAD(0x0674, 0x02A4, 7, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_JTAG_TMS__SJC_TMS \ ++ IOMUX_PAD(0x0678, NO_MUX_I, 0, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_JTAG_MOD__SJC_MOD \ ++ IOMUX_PAD(0x067C, NO_MUX_I, 0, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_JTAG_TRSTB__SJC_TRSTB \ ++ IOMUX_PAD(0x0680, NO_MUX_I, 0, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_JTAG_TDI__SJC_TDI \ ++ IOMUX_PAD(0x0684, NO_MUX_I, 0, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_JTAG_TCK__SJC_TCK \ ++ IOMUX_PAD(0x0688, NO_MUX_I, 0, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_JTAG_TDO__SJC_TDO \ ++ IOMUX_PAD(0x068C, NO_MUX_I, 0, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 \ ++ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 \ ++ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK \ ++ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 \ ++ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 \ ++ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 \ ++ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK \ ++ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 \ ++ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 \ ++ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 \ ++ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_TAMPER__SNVS_LP_WRAPPER_SNVS_TD1 \ ++ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_PMIC_ON_REQ__SNVS_LP_WRAPPER_SNVS_WAKEUP_ALARM \ ++ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_PMIC_STBY_REQ__CCM_PMIC_VSTBY_REQ \ ++ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_POR_B__SRC_POR_B \ ++ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_BOOT_MODE1__SRC_BOOT_MODE_1 \ ++ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_RESET_IN_B__SRC_RESET_B \ ++ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_BOOT_MODE0__SRC_BOOT_MODE_0 \ ++ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_TEST_MODE__TCU_TEST_MODE \ ++ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_SD3_DAT7__USDHC3_DAT7 \ ++ IOMUX_PAD(0x0690, 0x02A8, 0, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD3_DAT7__UART1_TXD \ ++ IOMUX_PAD(0x0690, 0x02A8, 1, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD3_DAT7__UART1_RXD \ ++ IOMUX_PAD(0x0690, 0x02A8, 1, 0x0920, 2, 0) ++#define _MX6Q_PAD_SD3_DAT7__PCIE_CTRL_DIAG_STATUS_BUS_MUX_24 \ ++ IOMUX_PAD(0x0690, 0x02A8, 2, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD3_DAT7__USBOH3_UH3_DFD_OUT_0 \ ++ IOMUX_PAD(0x0690, 0x02A8, 3, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD3_DAT7__USBOH3_UH2_DFD_OUT_0 \ ++ IOMUX_PAD(0x0690, 0x02A8, 4, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD3_DAT7__GPIO_6_17 \ ++ IOMUX_PAD(0x0690, 0x02A8, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD3_DAT7__MIPI_CORE_DPHY_TEST_IN_12 \ ++ IOMUX_PAD(0x0690, 0x02A8, 6, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD3_DAT7__ANATOP_USBPHY2_TSTO_PLL_CLK20DIV \ ++ IOMUX_PAD(0x0690, 0x02A8, 7, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_SD3_DAT6__USDHC3_DAT6 \ ++ IOMUX_PAD(0x0694, 0x02AC, 0, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD3_DAT6__UART1_TXD \ ++ IOMUX_PAD(0x0694, 0x02AC, 1, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD3_DAT6__UART1_RXD \ ++ IOMUX_PAD(0x0694, 0x02AC, 1, 0x0920, 3, 0) ++#define _MX6Q_PAD_SD3_DAT6__PCIE_CTRL_DIAG_STATUS_BUS_MUX_25 \ ++ IOMUX_PAD(0x0694, 0x02AC, 2, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD3_DAT6__USBOH3_UH3_DFD_OUT_1 \ ++ IOMUX_PAD(0x0694, 0x02AC, 3, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD3_DAT6__USBOH3_UH2_DFD_OUT_1 \ ++ IOMUX_PAD(0x0694, 0x02AC, 4, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD3_DAT6__GPIO_6_18 \ ++ IOMUX_PAD(0x0694, 0x02AC, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD3_DAT6__MIPI_CORE_DPHY_TEST_IN_13 \ ++ IOMUX_PAD(0x0694, 0x02AC, 6, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD3_DAT6__ANATOP_ANATOP_TESTO_10 \ ++ IOMUX_PAD(0x0694, 0x02AC, 7, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_SD3_DAT5__USDHC3_DAT5 \ ++ IOMUX_PAD(0x0698, 0x02B0, 0, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD3_DAT5__UART2_TXD \ ++ IOMUX_PAD(0x0698, 0x02B0, 1, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD3_DAT5__UART2_RXD \ ++ IOMUX_PAD(0x0698, 0x02B0, 1, 0x0928, 4, 0) ++#define _MX6Q_PAD_SD3_DAT5__PCIE_CTRL_DIAG_STATUS_BUS_MUX_26 \ ++ IOMUX_PAD(0x0698, 0x02B0, 2, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD3_DAT5__USBOH3_UH3_DFD_OUT_2 \ ++ IOMUX_PAD(0x0698, 0x02B0, 3, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD3_DAT5__USBOH3_UH2_DFD_OUT_2 \ ++ IOMUX_PAD(0x0698, 0x02B0, 4, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD3_DAT5__GPIO_7_0 \ ++ IOMUX_PAD(0x0698, 0x02B0, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD3_DAT5__MIPI_CORE_DPHY_TEST_IN_14 \ ++ IOMUX_PAD(0x0698, 0x02B0, 6, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD3_DAT5__ANATOP_ANATOP_TESTO_11 \ ++ IOMUX_PAD(0x0698, 0x02B0, 7, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_SD3_DAT4__USDHC3_DAT4 \ ++ IOMUX_PAD(0x069C, 0x02B4, 0, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD3_DAT4__UART2_TXD \ ++ IOMUX_PAD(0x069C, 0x02B4, 1, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD3_DAT4__UART2_RXD \ ++ IOMUX_PAD(0x069C, 0x02B4, 1, 0x0928, 5, 0) ++#define _MX6Q_PAD_SD3_DAT4__PCIE_CTRL_DIAG_STATUS_BUS_MUX_27 \ ++ IOMUX_PAD(0x069C, 0x02B4, 2, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD3_DAT4__USBOH3_UH3_DFD_OUT_3 \ ++ IOMUX_PAD(0x069C, 0x02B4, 3, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD3_DAT4__USBOH3_UH2_DFD_OUT_3 \ ++ IOMUX_PAD(0x069C, 0x02B4, 4, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD3_DAT4__GPIO_7_1 \ ++ IOMUX_PAD(0x069C, 0x02B4, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD3_DAT4__MIPI_CORE_DPHY_TEST_IN_15 \ ++ IOMUX_PAD(0x069C, 0x02B4, 6, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD3_DAT4__ANATOP_ANATOP_TESTO_12 \ ++ IOMUX_PAD(0x069C, 0x02B4, 7, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_SD3_CMD__USDHC3_CMD \ ++ IOMUX_PAD(0x06A0, 0x02B8, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD3_CMD__UART2_CTS \ ++ IOMUX_PAD(0x06A0, 0x02B8, 1, 0x0000, 2, 0) ++#define _MX6Q_PAD_SD3_CMD__UART2_RTS \ ++ IOMUX_PAD(0x06A0, 0x02B8, 1, 0x0924, 2, 0) ++#define _MX6Q_PAD_SD3_CMD__CAN1_TXCAN \ ++ IOMUX_PAD(0x06A0, 0x02B8, 2, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD3_CMD__USBOH3_UH3_DFD_OUT_4 \ ++ IOMUX_PAD(0x06A0, 0x02B8, 3, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD3_CMD__USBOH3_UH2_DFD_OUT_4 \ ++ IOMUX_PAD(0x06A0, 0x02B8, 4, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD3_CMD__GPIO_7_2 \ ++ IOMUX_PAD(0x06A0, 0x02B8, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD3_CMD__MIPI_CORE_DPHY_TEST_IN_16 \ ++ IOMUX_PAD(0x06A0, 0x02B8, 6, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD3_CMD__ANATOP_ANATOP_TESTO_13 \ ++ IOMUX_PAD(0x06A0, 0x02B8, 7, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_SD3_CLK__USDHC3_CLK \ ++ IOMUX_PAD(0x06A4, 0x02BC, 0, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD3_CLK__UART2_CTS \ ++ IOMUX_PAD(0x06A4, 0x02BC, 1, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD3_CLK__UART2_RTS \ ++ IOMUX_PAD(0x06A4, 0x02BC, 1, 0x0924, 3, 0) ++#define _MX6Q_PAD_SD3_CLK__CAN1_RXCAN \ ++ IOMUX_PAD(0x06A4, 0x02BC, 2, 0x07E4, 2, 0) ++#define _MX6Q_PAD_SD3_CLK__USBOH3_UH3_DFD_OUT_5 \ ++ IOMUX_PAD(0x06A4, 0x02BC, 3, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD3_CLK__USBOH3_UH2_DFD_OUT_5 \ ++ IOMUX_PAD(0x06A4, 0x02BC, 4, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD3_CLK__GPIO_7_3 \ ++ IOMUX_PAD(0x06A4, 0x02BC, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD3_CLK__MIPI_CORE_DPHY_TEST_IN_17 \ ++ IOMUX_PAD(0x06A4, 0x02BC, 6, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD3_CLK__ANATOP_ANATOP_TESTO_14 \ ++ IOMUX_PAD(0x06A4, 0x02BC, 7, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 \ ++ IOMUX_PAD(0x06A8, 0x02C0, 0, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD3_DAT0__UART1_CTS \ ++ IOMUX_PAD(0x06A8, 0x02C0, 1, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD3_DAT0__UART1_RTS \ ++ IOMUX_PAD(0x06A8, 0x02C0, 1, 0x091C, 2, 0) ++#define _MX6Q_PAD_SD3_DAT0__CAN2_TXCAN \ ++ IOMUX_PAD(0x06A8, 0x02C0, 2, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD3_DAT0__USBOH3_UH3_DFD_OUT_6 \ ++ IOMUX_PAD(0x06A8, 0x02C0, 3, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD3_DAT0__USBOH3_UH2_DFD_OUT_6 \ ++ IOMUX_PAD(0x06A8, 0x02C0, 4, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD3_DAT0__GPIO_7_4 \ ++ IOMUX_PAD(0x06A8, 0x02C0, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD3_DAT0__MIPI_CORE_DPHY_TEST_IN_18 \ ++ IOMUX_PAD(0x06A8, 0x02C0, 6, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD3_DAT0__ANATOP_ANATOP_TESTO_15 \ ++ IOMUX_PAD(0x06A8, 0x02C0, 7, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 \ ++ IOMUX_PAD(0x06AC, 0x02C4, 0, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD3_DAT1__UART1_CTS \ ++ IOMUX_PAD(0x06AC, 0x02C4, 1, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD3_DAT1__UART1_RTS \ ++ IOMUX_PAD(0x06AC, 0x02C4, 1, 0x091C, 3, 0) ++#define _MX6Q_PAD_SD3_DAT1__CAN2_RXCAN \ ++ IOMUX_PAD(0x06AC, 0x02C4, 2, 0x07E8, 1, 0) ++#define _MX6Q_PAD_SD3_DAT1__USBOH3_UH3_DFD_OUT_7 \ ++ IOMUX_PAD(0x06AC, 0x02C4, 3, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD3_DAT1__USBOH3_UH2_DFD_OUT_7 \ ++ IOMUX_PAD(0x06AC, 0x02C4, 4, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD3_DAT1__GPIO_7_5 \ ++ IOMUX_PAD(0x06AC, 0x02C4, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD3_DAT1__MIPI_CORE_DPHY_TEST_IN_19 \ ++ IOMUX_PAD(0x06AC, 0x02C4, 6, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD3_DAT1__ANATOP_ANATOP_TESTI_0 \ ++ IOMUX_PAD(0x06AC, 0x02C4, 7, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 \ ++ IOMUX_PAD(0x06B0, 0x02C8, 0, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD3_DAT2__PCIE_CTRL_DIAG_STATUS_BUS_MUX_28 \ ++ IOMUX_PAD(0x06B0, 0x02C8, 2, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD3_DAT2__USBOH3_UH3_DFD_OUT_8 \ ++ IOMUX_PAD(0x06B0, 0x02C8, 3, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD3_DAT2__USBOH3_UH2_DFD_OUT_8 \ ++ IOMUX_PAD(0x06B0, 0x02C8, 4, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD3_DAT2__GPIO_7_6 \ ++ IOMUX_PAD(0x06B0, 0x02C8, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD3_DAT2__MIPI_CORE_DPHY_TEST_IN_20 \ ++ IOMUX_PAD(0x06B0, 0x02C8, 6, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD3_DAT2__ANATOP_ANATOP_TESTI_1 \ ++ IOMUX_PAD(0x06B0, 0x02C8, 7, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 \ ++ IOMUX_PAD(0x06B4, 0x02CC, 0, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD3_DAT3__UART3_CTS \ ++ IOMUX_PAD(0x06B4, 0x02CC, 1, 0x0000, 4, 0) ++#define _MX6Q_PAD_SD3_DAT3__UART3_RTS \ ++ IOMUX_PAD(0x06B4, 0x02CC, 1, 0x092C, 4, 0) ++#define _MX6Q_PAD_SD3_DAT3__PCIE_CTRL_DIAG_STATUS_BUS_MUX_29 \ ++ IOMUX_PAD(0x06B4, 0x02CC, 2, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD3_DAT3__USBOH3_UH3_DFD_OUT_9 \ ++ IOMUX_PAD(0x06B4, 0x02CC, 3, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD3_DAT3__USBOH3_UH2_DFD_OUT_9 \ ++ IOMUX_PAD(0x06B4, 0x02CC, 4, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD3_DAT3__GPIO_7_7 \ ++ IOMUX_PAD(0x06B4, 0x02CC, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD3_DAT3__MIPI_CORE_DPHY_TEST_IN_21 \ ++ IOMUX_PAD(0x06B4, 0x02CC, 6, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD3_DAT3__ANATOP_ANATOP_TESTI_2 \ ++ IOMUX_PAD(0x06B4, 0x02CC, 7, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_SD3_RST__USDHC3_RST \ ++ IOMUX_PAD(0x06B8, 0x02D0, 0, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD3_RST__UART3_CTS \ ++ IOMUX_PAD(0x06B8, 0x02D0, 1, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD3_RST__UART3_RTS \ ++ IOMUX_PAD(0x06B8, 0x02D0, 1, 0x092C, 5, 0) ++#define _MX6Q_PAD_SD3_RST__PCIE_CTRL_DIAG_STATUS_BUS_MUX_30 \ ++ IOMUX_PAD(0x06B8, 0x02D0, 2, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD3_RST__USBOH3_UH3_DFD_OUT_10 \ ++ IOMUX_PAD(0x06B8, 0x02D0, 3, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD3_RST__USBOH3_UH2_DFD_OUT_10 \ ++ IOMUX_PAD(0x06B8, 0x02D0, 4, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD3_RST__GPIO_7_8 \ ++ IOMUX_PAD(0x06B8, 0x02D0, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD3_RST__MIPI_CORE_DPHY_TEST_IN_22 \ ++ IOMUX_PAD(0x06B8, 0x02D0, 6, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD3_RST__ANATOP_ANATOP_TESTI_3 \ ++ IOMUX_PAD(0x06B8, 0x02D0, 7, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_NANDF_CLE__RAWNAND_CLE \ ++ IOMUX_PAD(0x06BC, 0x02D4, 0, 0x0000, 0, 0) ++#define _MX6Q_PAD_NANDF_CLE__IPU2_SISG_4 \ ++ IOMUX_PAD(0x06BC, 0x02D4, 1, 0x0000, 0, 0) ++#define _MX6Q_PAD_NANDF_CLE__PCIE_CTRL_DIAG_STATUS_BUS_MUX_31 \ ++ IOMUX_PAD(0x06BC, 0x02D4, 2, 0x0000, 0, 0) ++#define _MX6Q_PAD_NANDF_CLE__USBOH3_UH3_DFD_OUT_11 \ ++ IOMUX_PAD(0x06BC, 0x02D4, 3, 0x0000, 0, 0) ++#define _MX6Q_PAD_NANDF_CLE__USBOH3_UH2_DFD_OUT_11 \ ++ IOMUX_PAD(0x06BC, 0x02D4, 4, 0x0000, 0, 0) ++#define _MX6Q_PAD_NANDF_CLE__GPIO_6_7 \ ++ IOMUX_PAD(0x06BC, 0x02D4, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_NANDF_CLE__MIPI_CORE_DPHY_TEST_IN_23 \ ++ IOMUX_PAD(0x06BC, 0x02D4, 6, 0x0000, 0, 0) ++#define _MX6Q_PAD_NANDF_CLE__TPSMP_HTRANS_0 \ ++ IOMUX_PAD(0x06BC, 0x02D4, 7, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_NANDF_ALE__RAWNAND_ALE \ ++ IOMUX_PAD(0x06C0, 0x02D8, 0, 0x0000, 0, 0) ++#define _MX6Q_PAD_NANDF_ALE__USDHC4_RST \ ++ IOMUX_PAD(0x06C0, 0x02D8, 1, 0x0000, 0, 0) ++#define _MX6Q_PAD_NANDF_ALE__PCIE_CTRL_DIAG_STATUS_BUS_MUX_0 \ ++ IOMUX_PAD(0x06C0, 0x02D8, 2, 0x0000, 0, 0) ++#define _MX6Q_PAD_NANDF_ALE__USBOH3_UH3_DFD_OUT_12 \ ++ IOMUX_PAD(0x06C0, 0x02D8, 3, 0x0000, 0, 0) ++#define _MX6Q_PAD_NANDF_ALE__USBOH3_UH2_DFD_OUT_12 \ ++ IOMUX_PAD(0x06C0, 0x02D8, 4, 0x0000, 0, 0) ++#define _MX6Q_PAD_NANDF_ALE__GPIO_6_8 \ ++ IOMUX_PAD(0x06C0, 0x02D8, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_NANDF_ALE__MIPI_CORE_DPHY_TEST_IN_24 \ ++ IOMUX_PAD(0x06C0, 0x02D8, 6, 0x0000, 0, 0) ++#define _MX6Q_PAD_NANDF_ALE__TPSMP_HTRANS_1 \ ++ IOMUX_PAD(0x06C0, 0x02D8, 7, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_NANDF_WP_B__RAWNAND_RESETN \ ++ IOMUX_PAD(0x06C4, 0x02DC, 0, 0x0000, 0, 0) ++#define _MX6Q_PAD_NANDF_WP_B__IPU2_SISG_5 \ ++ IOMUX_PAD(0x06C4, 0x02DC, 1, 0x0000, 0, 0) ++#define _MX6Q_PAD_NANDF_WP_B__PCIE_CTRL_DIAG_STATUS_BUS_MUX_1 \ ++ IOMUX_PAD(0x06C4, 0x02DC, 2, 0x0000, 0, 0) ++#define _MX6Q_PAD_NANDF_WP_B__USBOH3_UH3_DFD_OUT_13 \ ++ IOMUX_PAD(0x06C4, 0x02DC, 3, 0x0000, 0, 0) ++#define _MX6Q_PAD_NANDF_WP_B__USBOH3_UH2_DFD_OUT_13 \ ++ IOMUX_PAD(0x06C4, 0x02DC, 4, 0x0000, 0, 0) ++#define _MX6Q_PAD_NANDF_WP_B__GPIO_6_9 \ ++ IOMUX_PAD(0x06C4, 0x02DC, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_NANDF_WP_B__MIPI_CORE_DPHY_TEST_OUT_32 \ ++ IOMUX_PAD(0x06C4, 0x02DC, 6, 0x0000, 0, 0) ++#define _MX6Q_PAD_NANDF_WP_B__PL301_MX6QPER1_HSIZE_0 \ ++ IOMUX_PAD(0x06C4, 0x02DC, 7, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_NANDF_RB0__RAWNAND_READY0 \ ++ IOMUX_PAD(0x06C8, 0x02E0, 0, 0x0000, 0, 0) ++#define _MX6Q_PAD_NANDF_RB0__IPU2_DI0_PIN1 \ ++ IOMUX_PAD(0x06C8, 0x02E0, 1, 0x0000, 0, 0) ++#define _MX6Q_PAD_NANDF_RB0__PCIE_CTRL_DIAG_STATUS_BUS_MUX_2 \ ++ IOMUX_PAD(0x06C8, 0x02E0, 2, 0x0000, 0, 0) ++#define _MX6Q_PAD_NANDF_RB0__USBOH3_UH3_DFD_OUT_14 \ ++ IOMUX_PAD(0x06C8, 0x02E0, 3, 0x0000, 0, 0) ++#define _MX6Q_PAD_NANDF_RB0__USBOH3_UH2_DFD_OUT_14 \ ++ IOMUX_PAD(0x06C8, 0x02E0, 4, 0x0000, 0, 0) ++#define _MX6Q_PAD_NANDF_RB0__GPIO_6_10 \ ++ IOMUX_PAD(0x06C8, 0x02E0, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_NANDF_RB0__MIPI_CORE_DPHY_TEST_OUT_33 \ ++ IOMUX_PAD(0x06C8, 0x02E0, 6, 0x0000, 0, 0) ++#define _MX6Q_PAD_NANDF_RB0__PL301_MX6QPER1_HSIZE_1 \ ++ IOMUX_PAD(0x06C8, 0x02E0, 7, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_NANDF_CS0__RAWNAND_CE0N \ ++ IOMUX_PAD(0x06CC, 0x02E4, 0, 0x0000, 0, 0) ++#define _MX6Q_PAD_NANDF_CS0__USBOH3_UH3_DFD_OUT_15 \ ++ IOMUX_PAD(0x06CC, 0x02E4, 3, 0x0000, 0, 0) ++#define _MX6Q_PAD_NANDF_CS0__USBOH3_UH2_DFD_OUT_15 \ ++ IOMUX_PAD(0x06CC, 0x02E4, 4, 0x0000, 0, 0) ++#define _MX6Q_PAD_NANDF_CS0__GPIO_6_11 \ ++ IOMUX_PAD(0x06CC, 0x02E4, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_NANDF_CS0__PL301_MX6QPER1_HSIZE_2 \ ++ IOMUX_PAD(0x06CC, 0x02E4, 7, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_NANDF_CS1__RAWNAND_CE1N \ ++ IOMUX_PAD(0x06D0, 0x02E8, 0, 0x0000, 0, 0) ++#define _MX6Q_PAD_NANDF_CS1__USDHC4_VSELECT \ ++ IOMUX_PAD(0x06D0, 0x02E8, 1, 0x0000, 0, 0) ++#define _MX6Q_PAD_NANDF_CS1__USDHC3_VSELECT \ ++ IOMUX_PAD(0x06D0, 0x02E8, 2, 0x0000, 0, 0) ++#define _MX6Q_PAD_NANDF_CS1__PCIE_CTRL_DIAG_STATUS_BUS_MUX_3 \ ++ IOMUX_PAD(0x06D0, 0x02E8, 4, 0x0000, 0, 0) ++#define _MX6Q_PAD_NANDF_CS1__GPIO_6_14 \ ++ IOMUX_PAD(0x06D0, 0x02E8, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_NANDF_CS1__PL301_MX6QPER1_HREADYOUT \ ++ IOMUX_PAD(0x06D0, 0x02E8, 7, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_NANDF_CS2__RAWNAND_CE2N \ ++ IOMUX_PAD(0x06D4, 0x02EC, 0, 0x0000, 0, 0) ++#define _MX6Q_PAD_NANDF_CS2__IPU1_SISG_0 \ ++ IOMUX_PAD(0x06D4, 0x02EC, 1, 0x0000, 0, 0) ++#define _MX6Q_PAD_NANDF_CS2__ESAI1_TX0 \ ++ IOMUX_PAD(0x06D4, 0x02EC, 2, 0x0874, 1, 0) ++#define _MX6Q_PAD_NANDF_CS2__WEIM_WEIM_CRE \ ++ IOMUX_PAD(0x06D4, 0x02EC, 3, 0x0000, 0, 0) ++#define _MX6Q_PAD_NANDF_CS2__CCM_CLKO2 \ ++ IOMUX_PAD(0x06D4, 0x02EC, 4, 0x0000, 0, 0) ++#define _MX6Q_PAD_NANDF_CS2__GPIO_6_15 \ ++ IOMUX_PAD(0x06D4, 0x02EC, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_NANDF_CS2__IPU2_SISG_0 \ ++ IOMUX_PAD(0x06D4, 0x02EC, 6, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_NANDF_CS3__RAWNAND_CE3N \ ++ IOMUX_PAD(0x06D8, 0x02F0, 0, 0x0000, 0, 0) ++#define _MX6Q_PAD_NANDF_CS3__IPU1_SISG_1 \ ++ IOMUX_PAD(0x06D8, 0x02F0, 1, 0x0000, 0, 0) ++#define _MX6Q_PAD_NANDF_CS3__ESAI1_TX1 \ ++ IOMUX_PAD(0x06D8, 0x02F0, 2, 0x0878, 1, 0) ++#define _MX6Q_PAD_NANDF_CS3__WEIM_WEIM_A_26 \ ++ IOMUX_PAD(0x06D8, 0x02F0, 3, 0x0000, 0, 0) ++#define _MX6Q_PAD_NANDF_CS3__PCIE_CTRL_DIAG_STATUS_BUS_MUX_4 \ ++ IOMUX_PAD(0x06D8, 0x02F0, 4, 0x0000, 0, 0) ++#define _MX6Q_PAD_NANDF_CS3__GPIO_6_16 \ ++ IOMUX_PAD(0x06D8, 0x02F0, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_NANDF_CS3__IPU2_SISG_1 \ ++ IOMUX_PAD(0x06D8, 0x02F0, 6, 0x0000, 0, 0) ++#define _MX6Q_PAD_NANDF_CS3__TPSMP_CLK \ ++ IOMUX_PAD(0x06D8, 0x02F0, 7, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_SD4_CMD__USDHC4_CMD \ ++ IOMUX_PAD(0x06DC, 0x02F4, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD4_CMD__RAWNAND_RDN \ ++ IOMUX_PAD(0x06DC, 0x02F4, 1, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD4_CMD__UART3_TXD \ ++ IOMUX_PAD(0x06DC, 0x02F4, 2, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD4_CMD__UART3_RXD \ ++ IOMUX_PAD(0x06DC, 0x02F4, 2, 0x0930, 2, 0) ++#define _MX6Q_PAD_SD4_CMD__PCIE_CTRL_DIAG_STATUS_BUS_MUX_5 \ ++ IOMUX_PAD(0x06DC, 0x02F4, 4, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD4_CMD__GPIO_7_9 \ ++ IOMUX_PAD(0x06DC, 0x02F4, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD4_CMD__TPSMP_HDATA_DIR \ ++ IOMUX_PAD(0x06DC, 0x02F4, 7, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_SD4_CLK__USDHC4_CLK \ ++ IOMUX_PAD(0x06E0, 0x02F8, 0, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD4_CLK__RAWNAND_WRN \ ++ IOMUX_PAD(0x06E0, 0x02F8, 1, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD4_CLK__UART3_TXD \ ++ IOMUX_PAD(0x06E0, 0x02F8, 2, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD4_CLK__UART3_RXD \ ++ IOMUX_PAD(0x06E0, 0x02F8, 2, 0x0930, 3, 0) ++#define _MX6Q_PAD_SD4_CLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_6 \ ++ IOMUX_PAD(0x06E0, 0x02F8, 4, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD4_CLK__GPIO_7_10 \ ++ IOMUX_PAD(0x06E0, 0x02F8, 5, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_NANDF_D0__RAWNAND_D0 \ ++ IOMUX_PAD(0x06E4, 0x02FC, 0, 0x0000, 0, 0) ++#define _MX6Q_PAD_NANDF_D0__USDHC1_DAT4 \ ++ IOMUX_PAD(0x06E4, 0x02FC, 1, 0x0000, 0, 0) ++#define _MX6Q_PAD_NANDF_D0__GPU3D_GPU_DEBUG_OUT_0 \ ++ IOMUX_PAD(0x06E4, 0x02FC, 2, 0x0000, 0, 0) ++#define _MX6Q_PAD_NANDF_D0__USBOH3_UH2_DFD_OUT_16 \ ++ IOMUX_PAD(0x06E4, 0x02FC, 3, 0x0000, 0, 0) ++#define _MX6Q_PAD_NANDF_D0__USBOH3_UH3_DFD_OUT_16 \ ++ IOMUX_PAD(0x06E4, 0x02FC, 4, 0x0000, 0, 0) ++#define _MX6Q_PAD_NANDF_D0__GPIO_2_0 \ ++ IOMUX_PAD(0x06E4, 0x02FC, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_NANDF_D0__IPU1_IPU_DIAG_BUS_0 \ ++ IOMUX_PAD(0x06E4, 0x02FC, 6, 0x0000, 0, 0) ++#define _MX6Q_PAD_NANDF_D0__IPU2_IPU_DIAG_BUS_0 \ ++ IOMUX_PAD(0x06E4, 0x02FC, 7, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_NANDF_D1__RAWNAND_D1 \ ++ IOMUX_PAD(0x06E8, 0x0300, 0, 0x0000, 0, 0) ++#define _MX6Q_PAD_NANDF_D1__USDHC1_DAT5 \ ++ IOMUX_PAD(0x06E8, 0x0300, 1, 0x0000, 0, 0) ++#define _MX6Q_PAD_NANDF_D1__GPU3D_GPU_DEBUG_OUT_1 \ ++ IOMUX_PAD(0x06E8, 0x0300, 2, 0x0000, 0, 0) ++#define _MX6Q_PAD_NANDF_D1__USBOH3_UH2_DFD_OUT_17 \ ++ IOMUX_PAD(0x06E8, 0x0300, 3, 0x0000, 0, 0) ++#define _MX6Q_PAD_NANDF_D1__USBOH3_UH3_DFD_OUT_17 \ ++ IOMUX_PAD(0x06E8, 0x0300, 4, 0x0000, 0, 0) ++#define _MX6Q_PAD_NANDF_D1__GPIO_2_1 \ ++ IOMUX_PAD(0x06E8, 0x0300, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_NANDF_D1__IPU1_IPU_DIAG_BUS_1 \ ++ IOMUX_PAD(0x06E8, 0x0300, 6, 0x0000, 0, 0) ++#define _MX6Q_PAD_NANDF_D1__IPU2_IPU_DIAG_BUS_1 \ ++ IOMUX_PAD(0x06E8, 0x0300, 7, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_NANDF_D2__RAWNAND_D2 \ ++ IOMUX_PAD(0x06EC, 0x0304, 0, 0x0000, 0, 0) ++#define _MX6Q_PAD_NANDF_D2__USDHC1_DAT6 \ ++ IOMUX_PAD(0x06EC, 0x0304, 1, 0x0000, 0, 0) ++#define _MX6Q_PAD_NANDF_D2__GPU3D_GPU_DEBUG_OUT_2 \ ++ IOMUX_PAD(0x06EC, 0x0304, 2, 0x0000, 0, 0) ++#define _MX6Q_PAD_NANDF_D2__USBOH3_UH2_DFD_OUT_18 \ ++ IOMUX_PAD(0x06EC, 0x0304, 3, 0x0000, 0, 0) ++#define _MX6Q_PAD_NANDF_D2__USBOH3_UH3_DFD_OUT_18 \ ++ IOMUX_PAD(0x06EC, 0x0304, 4, 0x0000, 0, 0) ++#define _MX6Q_PAD_NANDF_D2__GPIO_2_2 \ ++ IOMUX_PAD(0x06EC, 0x0304, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_NANDF_D2__IPU1_IPU_DIAG_BUS_2 \ ++ IOMUX_PAD(0x06EC, 0x0304, 6, 0x0000, 0, 0) ++#define _MX6Q_PAD_NANDF_D2__IPU2_IPU_DIAG_BUS_2 \ ++ IOMUX_PAD(0x06EC, 0x0304, 7, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_NANDF_D3__RAWNAND_D3 \ ++ IOMUX_PAD(0x06F0, 0x0308, 0, 0x0000, 0, 0) ++#define _MX6Q_PAD_NANDF_D3__USDHC1_DAT7 \ ++ IOMUX_PAD(0x06F0, 0x0308, 1, 0x0000, 0, 0) ++#define _MX6Q_PAD_NANDF_D3__GPU3D_GPU_DEBUG_OUT_3 \ ++ IOMUX_PAD(0x06F0, 0x0308, 2, 0x0000, 0, 0) ++#define _MX6Q_PAD_NANDF_D3__USBOH3_UH2_DFD_OUT_19 \ ++ IOMUX_PAD(0x06F0, 0x0308, 3, 0x0000, 0, 0) ++#define _MX6Q_PAD_NANDF_D3__USBOH3_UH3_DFD_OUT_19 \ ++ IOMUX_PAD(0x06F0, 0x0308, 4, 0x0000, 0, 0) ++#define _MX6Q_PAD_NANDF_D3__GPIO_2_3 \ ++ IOMUX_PAD(0x06F0, 0x0308, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_NANDF_D3__IPU1_IPU_DIAG_BUS_3 \ ++ IOMUX_PAD(0x06F0, 0x0308, 6, 0x0000, 0, 0) ++#define _MX6Q_PAD_NANDF_D3__IPU2_IPU_DIAG_BUS_3 \ ++ IOMUX_PAD(0x06F0, 0x0308, 7, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_NANDF_D4__RAWNAND_D4 \ ++ IOMUX_PAD(0x06F4, 0x030C, 0, 0x0000, 0, 0) ++#define _MX6Q_PAD_NANDF_D4__USDHC2_DAT4 \ ++ IOMUX_PAD(0x06F4, 0x030C, 1, 0x0000, 0, 0) ++#define _MX6Q_PAD_NANDF_D4__GPU3D_GPU_DEBUG_OUT_4 \ ++ IOMUX_PAD(0x06F4, 0x030C, 2, 0x0000, 0, 0) ++#define _MX6Q_PAD_NANDF_D4__USBOH3_UH2_DFD_OUT_20 \ ++ IOMUX_PAD(0x06F4, 0x030C, 3, 0x0000, 0, 0) ++#define _MX6Q_PAD_NANDF_D4__USBOH3_UH3_DFD_OUT_20 \ ++ IOMUX_PAD(0x06F4, 0x030C, 4, 0x0000, 0, 0) ++#define _MX6Q_PAD_NANDF_D4__GPIO_2_4 \ ++ IOMUX_PAD(0x06F4, 0x030C, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_NANDF_D4__IPU1_IPU_DIAG_BUS_4 \ ++ IOMUX_PAD(0x06F4, 0x030C, 6, 0x0000, 0, 0) ++#define _MX6Q_PAD_NANDF_D4__IPU2_IPU_DIAG_BUS_4 \ ++ IOMUX_PAD(0x06F4, 0x030C, 7, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_NANDF_D5__RAWNAND_D5 \ ++ IOMUX_PAD(0x06F8, 0x0310, 0, 0x0000, 0, 0) ++#define _MX6Q_PAD_NANDF_D5__USDHC2_DAT5 \ ++ IOMUX_PAD(0x06F8, 0x0310, 1, 0x0000, 0, 0) ++#define _MX6Q_PAD_NANDF_D5__GPU3D_GPU_DEBUG_OUT_5 \ ++ IOMUX_PAD(0x06F8, 0x0310, 2, 0x0000, 0, 0) ++#define _MX6Q_PAD_NANDF_D5__USBOH3_UH2_DFD_OUT_21 \ ++ IOMUX_PAD(0x06F8, 0x0310, 3, 0x0000, 0, 0) ++#define _MX6Q_PAD_NANDF_D5__USBOH3_UH3_DFD_OUT_21 \ ++ IOMUX_PAD(0x06F8, 0x0310, 4, 0x0000, 0, 0) ++#define _MX6Q_PAD_NANDF_D5__GPIO_2_5 \ ++ IOMUX_PAD(0x06F8, 0x0310, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_NANDF_D5__IPU1_IPU_DIAG_BUS_5 \ ++ IOMUX_PAD(0x06F8, 0x0310, 6, 0x0000, 0, 0) ++#define _MX6Q_PAD_NANDF_D5__IPU2_IPU_DIAG_BUS_5 \ ++ IOMUX_PAD(0x06F8, 0x0310, 7, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_NANDF_D6__RAWNAND_D6 \ ++ IOMUX_PAD(0x06FC, 0x0314, 0, 0x0000, 0, 0) ++#define _MX6Q_PAD_NANDF_D6__USDHC2_DAT6 \ ++ IOMUX_PAD(0x06FC, 0x0314, 1, 0x0000, 0, 0) ++#define _MX6Q_PAD_NANDF_D6__GPU3D_GPU_DEBUG_OUT_6 \ ++ IOMUX_PAD(0x06FC, 0x0314, 2, 0x0000, 0, 0) ++#define _MX6Q_PAD_NANDF_D6__USBOH3_UH2_DFD_OUT_22 \ ++ IOMUX_PAD(0x06FC, 0x0314, 3, 0x0000, 0, 0) ++#define _MX6Q_PAD_NANDF_D6__USBOH3_UH3_DFD_OUT_22 \ ++ IOMUX_PAD(0x06FC, 0x0314, 4, 0x0000, 0, 0) ++#define _MX6Q_PAD_NANDF_D6__GPIO_2_6 \ ++ IOMUX_PAD(0x06FC, 0x0314, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_NANDF_D6__IPU1_IPU_DIAG_BUS_6 \ ++ IOMUX_PAD(0x06FC, 0x0314, 6, 0x0000, 0, 0) ++#define _MX6Q_PAD_NANDF_D6__IPU2_IPU_DIAG_BUS_6 \ ++ IOMUX_PAD(0x06FC, 0x0314, 7, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_NANDF_D7__RAWNAND_D7 \ ++ IOMUX_PAD(0x0700, 0x0318, 0, 0x0000, 0, 0) ++#define _MX6Q_PAD_NANDF_D7__USDHC2_DAT7 \ ++ IOMUX_PAD(0x0700, 0x0318, 1, 0x0000, 0, 0) ++#define _MX6Q_PAD_NANDF_D7__GPU3D_GPU_DEBUG_OUT_7 \ ++ IOMUX_PAD(0x0700, 0x0318, 2, 0x0000, 0, 0) ++#define _MX6Q_PAD_NANDF_D7__USBOH3_UH2_DFD_OUT_23 \ ++ IOMUX_PAD(0x0700, 0x0318, 3, 0x0000, 0, 0) ++#define _MX6Q_PAD_NANDF_D7__USBOH3_UH3_DFD_OUT_23 \ ++ IOMUX_PAD(0x0700, 0x0318, 4, 0x0000, 0, 0) ++#define _MX6Q_PAD_NANDF_D7__GPIO_2_7 \ ++ IOMUX_PAD(0x0700, 0x0318, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_NANDF_D7__IPU1_IPU_DIAG_BUS_7 \ ++ IOMUX_PAD(0x0700, 0x0318, 6, 0x0000, 0, 0) ++#define _MX6Q_PAD_NANDF_D7__IPU2_IPU_DIAG_BUS_7 \ ++ IOMUX_PAD(0x0700, 0x0318, 7, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_SD4_DAT0__RAWNAND_D8 \ ++ IOMUX_PAD(0x0704, 0x031C, 0, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 \ ++ IOMUX_PAD(0x0704, 0x031C, 1, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD4_DAT0__RAWNAND_DQS \ ++ IOMUX_PAD(0x0704, 0x031C, 2, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD4_DAT0__USBOH3_UH2_DFD_OUT_24 \ ++ IOMUX_PAD(0x0704, 0x031C, 3, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD4_DAT0__USBOH3_UH3_DFD_OUT_24 \ ++ IOMUX_PAD(0x0704, 0x031C, 4, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD4_DAT0__GPIO_2_8 \ ++ IOMUX_PAD(0x0704, 0x031C, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD4_DAT0__IPU1_IPU_DIAG_BUS_8 \ ++ IOMUX_PAD(0x0704, 0x031C, 6, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD4_DAT0__IPU2_IPU_DIAG_BUS_8 \ ++ IOMUX_PAD(0x0704, 0x031C, 7, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_SD4_DAT1__RAWNAND_D9 \ ++ IOMUX_PAD(0x0708, 0x0320, 0, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 \ ++ IOMUX_PAD(0x0708, 0x0320, 1, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD4_DAT1__PWM3_PWMO \ ++ IOMUX_PAD(0x0708, 0x0320, 2, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD4_DAT1__USBOH3_UH2_DFD_OUT_25 \ ++ IOMUX_PAD(0x0708, 0x0320, 3, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD4_DAT1__USBOH3_UH3_DFD_OUT_25 \ ++ IOMUX_PAD(0x0708, 0x0320, 4, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD4_DAT1__GPIO_2_9 \ ++ IOMUX_PAD(0x0708, 0x0320, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD4_DAT1__IPU1_IPU_DIAG_BUS_9 \ ++ IOMUX_PAD(0x0708, 0x0320, 6, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD4_DAT1__IPU2_IPU_DIAG_BUS_9 \ ++ IOMUX_PAD(0x0708, 0x0320, 7, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_SD4_DAT2__RAWNAND_D10 \ ++ IOMUX_PAD(0x070C, 0x0324, 0, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 \ ++ IOMUX_PAD(0x070C, 0x0324, 1, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD4_DAT2__PWM4_PWMO \ ++ IOMUX_PAD(0x070C, 0x0324, 2, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD4_DAT2__USBOH3_UH2_DFD_OUT_26 \ ++ IOMUX_PAD(0x070C, 0x0324, 3, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD4_DAT2__USBOH3_UH3_DFD_OUT_26 \ ++ IOMUX_PAD(0x070C, 0x0324, 4, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD4_DAT2__GPIO_2_10 \ ++ IOMUX_PAD(0x070C, 0x0324, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD4_DAT2__IPU1_IPU_DIAG_BUS_10 \ ++ IOMUX_PAD(0x070C, 0x0324, 6, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD4_DAT2__IPU2_IPU_DIAG_BUS_10 \ ++ IOMUX_PAD(0x070C, 0x0324, 7, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_SD4_DAT3__RAWNAND_D11 \ ++ IOMUX_PAD(0x0710, 0x0328, 0, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 \ ++ IOMUX_PAD(0x0710, 0x0328, 1, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD4_DAT3__USBOH3_UH2_DFD_OUT_27 \ ++ IOMUX_PAD(0x0710, 0x0328, 3, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD4_DAT3__USBOH3_UH3_DFD_OUT_27 \ ++ IOMUX_PAD(0x0710, 0x0328, 4, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD4_DAT3__GPIO_2_11 \ ++ IOMUX_PAD(0x0710, 0x0328, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD4_DAT3__IPU1_IPU_DIAG_BUS_11 \ ++ IOMUX_PAD(0x0710, 0x0328, 6, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD4_DAT3__IPU2_IPU_DIAG_BUS_11 \ ++ IOMUX_PAD(0x0710, 0x0328, 7, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_SD4_DAT4__RAWNAND_D12 \ ++ IOMUX_PAD(0x0714, 0x032C, 0, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 \ ++ IOMUX_PAD(0x0714, 0x032C, 1, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD4_DAT4__UART2_TXD \ ++ IOMUX_PAD(0x0714, 0x032C, 2, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD4_DAT4__UART2_RXD \ ++ IOMUX_PAD(0x0714, 0x032C, 2, 0x0928, 6, 0) ++#define _MX6Q_PAD_SD4_DAT4__USBOH3_UH2_DFD_OUT_28 \ ++ IOMUX_PAD(0x0714, 0x032C, 3, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD4_DAT4__USBOH3_UH3_DFD_OUT_28 \ ++ IOMUX_PAD(0x0714, 0x032C, 4, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD4_DAT4__GPIO_2_12 \ ++ IOMUX_PAD(0x0714, 0x032C, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD4_DAT4__IPU1_IPU_DIAG_BUS_12 \ ++ IOMUX_PAD(0x0714, 0x032C, 6, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD4_DAT4__IPU2_IPU_DIAG_BUS_12 \ ++ IOMUX_PAD(0x0714, 0x032C, 7, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_SD4_DAT5__RAWNAND_D13 \ ++ IOMUX_PAD(0x0718, 0x0330, 0, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 \ ++ IOMUX_PAD(0x0718, 0x0330, 1, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD4_DAT5__UART2_CTS \ ++ IOMUX_PAD(0x0718, 0x0330, 2, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD4_DAT5__UART2_RTS \ ++ IOMUX_PAD(0x0718, 0x0330, 2, 0x0924, 4, 0) ++#define _MX6Q_PAD_SD4_DAT5__USBOH3_UH2_DFD_OUT_29 \ ++ IOMUX_PAD(0x0718, 0x0330, 3, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD4_DAT5__USBOH3_UH3_DFD_OUT_29 \ ++ IOMUX_PAD(0x0718, 0x0330, 4, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD4_DAT5__GPIO_2_13 \ ++ IOMUX_PAD(0x0718, 0x0330, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD4_DAT5__IPU1_IPU_DIAG_BUS_13 \ ++ IOMUX_PAD(0x0718, 0x0330, 6, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD4_DAT5__IPU2_IPU_DIAG_BUS_13 \ ++ IOMUX_PAD(0x0718, 0x0330, 7, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_SD4_DAT6__RAWNAND_D14 \ ++ IOMUX_PAD(0x071C, 0x0334, 0, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 \ ++ IOMUX_PAD(0x071C, 0x0334, 1, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD4_DAT6__UART2_CTS \ ++ IOMUX_PAD(0x071C, 0x0334, 2, 0x0000, 5, 0) ++#define _MX6Q_PAD_SD4_DAT6__UART2_RTS \ ++ IOMUX_PAD(0x071C, 0x0334, 2, 0x0924, 5, 0) ++#define _MX6Q_PAD_SD4_DAT6__USBOH3_UH2_DFD_OUT_30 \ ++ IOMUX_PAD(0x071C, 0x0334, 3, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD4_DAT6__USBOH3_UH3_DFD_OUT_30 \ ++ IOMUX_PAD(0x071C, 0x0334, 4, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD4_DAT6__GPIO_2_14 \ ++ IOMUX_PAD(0x071C, 0x0334, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD4_DAT6__IPU1_IPU_DIAG_BUS_14 \ ++ IOMUX_PAD(0x071C, 0x0334, 6, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD4_DAT6__IPU2_IPU_DIAG_BUS_14 \ ++ IOMUX_PAD(0x071C, 0x0334, 7, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_SD4_DAT7__RAWNAND_D15 \ ++ IOMUX_PAD(0x0720, 0x0338, 0, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 \ ++ IOMUX_PAD(0x0720, 0x0338, 1, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD4_DAT7__UART2_TXD \ ++ IOMUX_PAD(0x0720, 0x0338, 2, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD4_DAT7__UART2_RXD \ ++ IOMUX_PAD(0x0720, 0x0338, 2, 0x0928, 7, 0) ++#define _MX6Q_PAD_SD4_DAT7__USBOH3_UH2_DFD_OUT_31 \ ++ IOMUX_PAD(0x0720, 0x0338, 3, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD4_DAT7__USBOH3_UH3_DFD_OUT_31 \ ++ IOMUX_PAD(0x0720, 0x0338, 4, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD4_DAT7__GPIO_2_15 \ ++ IOMUX_PAD(0x0720, 0x0338, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD4_DAT7__IPU1_IPU_DIAG_BUS_15 \ ++ IOMUX_PAD(0x0720, 0x0338, 6, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD4_DAT7__IPU2_IPU_DIAG_BUS_15 \ ++ IOMUX_PAD(0x0720, 0x0338, 7, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_SD1_DAT1__USDHC1_DAT1 \ ++ IOMUX_PAD(0x0724, 0x033C, 0, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD1_DAT1__ECSPI5_SS0 \ ++ IOMUX_PAD(0x0724, 0x033C, 1, 0x0834, 1, 0) ++#define _MX6Q_PAD_SD1_DAT1__PWM3_PWMO \ ++ IOMUX_PAD(0x0724, 0x033C, 2, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD1_DAT1__GPT_CAPIN2 \ ++ IOMUX_PAD(0x0724, 0x033C, 3, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD1_DAT1__PCIE_CTRL_DIAG_STATUS_BUS_MUX_7 \ ++ IOMUX_PAD(0x0724, 0x033C, 4, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD1_DAT1__GPIO_1_17 \ ++ IOMUX_PAD(0x0724, 0x033C, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD1_DAT1__HDMI_TX_OPHYDTB_0 \ ++ IOMUX_PAD(0x0724, 0x033C, 6, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD1_DAT1__ANATOP_ANATOP_TESTO_8 \ ++ IOMUX_PAD(0x0724, 0x033C, 7, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_SD1_DAT0__USDHC1_DAT0 \ ++ IOMUX_PAD(0x0728, 0x0340, 0, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD1_DAT0__ECSPI5_MISO \ ++ IOMUX_PAD(0x0728, 0x0340, 1, 0x082C, 1, 0) ++#define _MX6Q_PAD_SD1_DAT0__CAAM_WRAPPER_RNG_OSC_OBS \ ++ IOMUX_PAD(0x0728, 0x0340, 2, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD1_DAT0__GPT_CAPIN1 \ ++ IOMUX_PAD(0x0728, 0x0340, 3, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD1_DAT0__PCIE_CTRL_DIAG_STATUS_BUS_MUX_8 \ ++ IOMUX_PAD(0x0728, 0x0340, 4, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD1_DAT0__GPIO_1_16 \ ++ IOMUX_PAD(0x0728, 0x0340, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD1_DAT0__HDMI_TX_OPHYDTB_1 \ ++ IOMUX_PAD(0x0728, 0x0340, 6, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD1_DAT0__ANATOP_ANATOP_TESTO_7 \ ++ IOMUX_PAD(0x0728, 0x0340, 7, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_SD1_DAT3__USDHC1_DAT3 \ ++ IOMUX_PAD(0x072C, 0x0344, 0, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD1_DAT3__ECSPI5_SS2 \ ++ IOMUX_PAD(0x072C, 0x0344, 1, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD1_DAT3__GPT_CMPOUT3 \ ++ IOMUX_PAD(0x072C, 0x0344, 2, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD1_DAT3__PWM1_PWMO \ ++ IOMUX_PAD(0x072C, 0x0344, 3, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD1_DAT3__WDOG2_WDOG_B \ ++ IOMUX_PAD(0x072C, 0x0344, 4, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD1_DAT3__GPIO_1_21 \ ++ IOMUX_PAD(0x072C, 0x0344, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD1_DAT3__WDOG2_WDOG_RST_B_DEB \ ++ IOMUX_PAD(0x072C, 0x0344, 6, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD1_DAT3__ANATOP_ANATOP_TESTO_6 \ ++ IOMUX_PAD(0x072C, 0x0344, 7, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_SD1_CMD__USDHC1_CMD \ ++ IOMUX_PAD(0x0730, 0x0348, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD1_CMD__ECSPI5_MOSI \ ++ IOMUX_PAD(0x0730, 0x0348, 1, 0x0830, 0, 0) ++#define _MX6Q_PAD_SD1_CMD__PWM4_PWMO \ ++ IOMUX_PAD(0x0730, 0x0348, 2, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD1_CMD__GPT_CMPOUT1 \ ++ IOMUX_PAD(0x0730, 0x0348, 3, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD1_CMD__GPIO_1_18 \ ++ IOMUX_PAD(0x0730, 0x0348, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD1_CMD__ANATOP_ANATOP_TESTO_5 \ ++ IOMUX_PAD(0x0730, 0x0348, 7, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_SD1_DAT2__USDHC1_DAT2 \ ++ IOMUX_PAD(0x0734, 0x034C, 0, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD1_DAT2__ECSPI5_SS1 \ ++ IOMUX_PAD(0x0734, 0x034C, 1, 0x0838, 1, 0) ++#define _MX6Q_PAD_SD1_DAT2__GPT_CMPOUT2 \ ++ IOMUX_PAD(0x0734, 0x034C, 2, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD1_DAT2__PWM2_PWMO \ ++ IOMUX_PAD(0x0734, 0x034C, 3, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD1_DAT2__WDOG1_WDOG_B \ ++ IOMUX_PAD(0x0734, 0x034C, 4, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD1_DAT2__GPIO_1_19 \ ++ IOMUX_PAD(0x0734, 0x034C, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD1_DAT2__WDOG1_WDOG_RST_B_DEB \ ++ IOMUX_PAD(0x0734, 0x034C, 6, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD1_DAT2__ANATOP_ANATOP_TESTO_4 \ ++ IOMUX_PAD(0x0734, 0x034C, 7, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_SD1_CLK__USDHC1_CLK \ ++ IOMUX_PAD(0x0738, 0x0350, 0, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD1_CLK__ECSPI5_SCLK \ ++ IOMUX_PAD(0x0738, 0x0350, 1, 0x0828, 0, 0) ++#define _MX6Q_PAD_SD1_CLK__OSC32K_32K_OUT \ ++ IOMUX_PAD(0x0738, 0x0350, 2, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD1_CLK__GPT_CLKIN \ ++ IOMUX_PAD(0x0738, 0x0350, 3, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD1_CLK__GPIO_1_20 \ ++ IOMUX_PAD(0x0738, 0x0350, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD1_CLK__PHY_DTB_0 \ ++ IOMUX_PAD(0x0738, 0x0350, 6, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD1_CLK__SATA_PHY_DTB_0 \ ++ IOMUX_PAD(0x0738, 0x0350, 7, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_SD2_CLK__USDHC2_CLK \ ++ IOMUX_PAD(0x073C, 0x0354, 0, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD2_CLK__ECSPI5_SCLK \ ++ IOMUX_PAD(0x073C, 0x0354, 1, 0x0828, 1, 0) ++#define _MX6Q_PAD_SD2_CLK__KPP_COL_5 \ ++ IOMUX_PAD(0x073C, 0x0354, 2, 0x08E8, 3, 0) ++#define _MX6Q_PAD_SD2_CLK__AUDMUX_AUD4_RXFS \ ++ IOMUX_PAD(0x073C, 0x0354, 3, 0x07C0, 1, 0) ++#define _MX6Q_PAD_SD2_CLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_9 \ ++ IOMUX_PAD(0x073C, 0x0354, 4, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD2_CLK__GPIO_1_10 \ ++ IOMUX_PAD(0x073C, 0x0354, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD2_CLK__PHY_DTB_1 \ ++ IOMUX_PAD(0x073C, 0x0354, 6, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD2_CLK__SATA_PHY_DTB_1 \ ++ IOMUX_PAD(0x073C, 0x0354, 7, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_SD2_CMD__USDHC2_CMD \ ++ IOMUX_PAD(0x0740, 0x0358, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD2_CMD__ECSPI5_MOSI \ ++ IOMUX_PAD(0x0740, 0x0358, 1, 0x0830, 1, 0) ++#define _MX6Q_PAD_SD2_CMD__KPP_ROW_5 \ ++ IOMUX_PAD(0x0740, 0x0358, 2, 0x08F4, 2, 0) ++#define _MX6Q_PAD_SD2_CMD__AUDMUX_AUD4_RXC \ ++ IOMUX_PAD(0x0740, 0x0358, 3, 0x07BC, 1, 0) ++#define _MX6Q_PAD_SD2_CMD__PCIE_CTRL_DIAG_STATUS_BUS_MUX_10 \ ++ IOMUX_PAD(0x0740, 0x0358, 4, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD2_CMD__GPIO_1_11 \ ++ IOMUX_PAD(0x0740, 0x0358, 5, 0x0000, 0, 0) ++ ++#define _MX6Q_PAD_SD2_DAT3__USDHC2_DAT3 \ ++ IOMUX_PAD(0x0744, 0x035C, 0, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD2_DAT3__ECSPI5_SS3 \ ++ IOMUX_PAD(0x0744, 0x035C, 1, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD2_DAT3__KPP_COL_6 \ ++ IOMUX_PAD(0x0744, 0x035C, 2, 0x08EC, 2, 0) ++#define _MX6Q_PAD_SD2_DAT3__AUDMUX_AUD4_TXC \ ++ IOMUX_PAD(0x0744, 0x035C, 3, 0x07C4, 1, 0) ++#define _MX6Q_PAD_SD2_DAT3__PCIE_CTRL_DIAG_STATUS_BUS_MUX_11 \ ++ IOMUX_PAD(0x0744, 0x035C, 4, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD2_DAT3__GPIO_1_12 \ ++ IOMUX_PAD(0x0744, 0x035C, 5, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD2_DAT3__SJC_DONE \ ++ IOMUX_PAD(0x0744, 0x035C, 6, 0x0000, 0, 0) ++#define _MX6Q_PAD_SD2_DAT3__ANATOP_ANATOP_TESTO_3 \ ++ IOMUX_PAD(0x0744, 0x035C, 7, 0x0000, 0, 0) ++ ++#define MX6Q_PAD_SD2_DAT1__USDHC2_DAT1 (_MX6Q_PAD_SD2_DAT1__USDHC2_DAT1 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) ++#define MX6Q_PAD_SD2_DAT1__ECSPI5_SS0 (_MX6Q_PAD_SD2_DAT1__ECSPI5_SS0) ++#define MX6Q_PAD_SD2_DAT1__WEIM_WEIM_CS_2 (_MX6Q_PAD_SD2_DAT1__WEIM_WEIM_CS_2) ++#define MX6Q_PAD_SD2_DAT1__AUDMUX_AUD4_TXFS (_MX6Q_PAD_SD2_DAT1__AUDMUX_AUD4_TXFS) ++#define MX6Q_PAD_SD2_DAT1__KPP_COL_7 (_MX6Q_PAD_SD2_DAT1__KPP_COL_7) ++#define MX6Q_PAD_SD2_DAT1__GPIO_1_14 (_MX6Q_PAD_SD2_DAT1__GPIO_1_14) ++#define MX6Q_PAD_SD2_DAT1__CCM_WAIT (_MX6Q_PAD_SD2_DAT1__CCM_WAIT) ++#define MX6Q_PAD_SD2_DAT1__ANATOP_ANATOP_TESTO_0 (_MX6Q_PAD_SD2_DAT1__ANATOP_ANATOP_TESTO_0) ++ ++#define MX6Q_PAD_SD2_DAT2__USDHC2_DAT2 (_MX6Q_PAD_SD2_DAT2__USDHC2_DAT2 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) ++#define MX6Q_PAD_SD2_DAT2__ECSPI5_SS1 (_MX6Q_PAD_SD2_DAT2__ECSPI5_SS1) ++#define MX6Q_PAD_SD2_DAT2__WEIM_WEIM_CS_3 (_MX6Q_PAD_SD2_DAT2__WEIM_WEIM_CS_3) ++#define MX6Q_PAD_SD2_DAT2__AUDMUX_AUD4_TXD (_MX6Q_PAD_SD2_DAT2__AUDMUX_AUD4_TXD) ++#define MX6Q_PAD_SD2_DAT2__KPP_ROW_6 (_MX6Q_PAD_SD2_DAT2__KPP_ROW_6) ++#define MX6Q_PAD_SD2_DAT2__GPIO_1_13 (_MX6Q_PAD_SD2_DAT2__GPIO_1_13) ++#define MX6Q_PAD_SD2_DAT2__CCM_STOP (_MX6Q_PAD_SD2_DAT2__CCM_STOP) ++#define MX6Q_PAD_SD2_DAT2__ANATOP_ANATOP_TESTO_1 (_MX6Q_PAD_SD2_DAT2__ANATOP_ANATOP_TESTO_1) ++ ++#define MX6Q_PAD_SD2_DAT0__USDHC2_DAT0 (_MX6Q_PAD_SD2_DAT0__USDHC2_DAT0 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) ++#define MX6Q_PAD_SD2_DAT0__ECSPI5_MISO (_MX6Q_PAD_SD2_DAT0__ECSPI5_MISO) ++#define MX6Q_PAD_SD2_DAT0__AUDMUX_AUD4_RXD (_MX6Q_PAD_SD2_DAT0__AUDMUX_AUD4_RXD) ++#define MX6Q_PAD_SD2_DAT0__KPP_ROW_7 (_MX6Q_PAD_SD2_DAT0__KPP_ROW_7) ++#define MX6Q_PAD_SD2_DAT0__GPIO_1_15 (_MX6Q_PAD_SD2_DAT0__GPIO_1_15) ++#define MX6Q_PAD_SD2_DAT0__DCIC2_DCIC_OUT (_MX6Q_PAD_SD2_DAT0__DCIC2_DCIC_OUT) ++#define MX6Q_PAD_SD2_DAT0__ANATOP_ANATOP_TESTO_2 (_MX6Q_PAD_SD2_DAT0__ANATOP_ANATOP_TESTO_2) ++ ++#define MX6Q_PAD_RGMII_TXC__USBOH3_H2_DATA (_MX6Q_PAD_RGMII_TXC__USBOH3_H2_DATA) ++#define MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC (_MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL)) ++#define MX6Q_PAD_RGMII_TXC__SPDIF_SPDIF_EXTCLK (_MX6Q_PAD_RGMII_TXC__SPDIF_SPDIF_EXTCLK) ++#define MX6Q_PAD_RGMII_TXC__GPIO_6_19 (_MX6Q_PAD_RGMII_TXC__GPIO_6_19) ++#define MX6Q_PAD_RGMII_TXC__MIPI_CORE_DPHY_TEST_IN_0 (_MX6Q_PAD_RGMII_TXC__MIPI_CORE_DPHY_TEST_IN_0) ++#define MX6Q_PAD_RGMII_TXC__ANATOP_ANATOP_24M_OUT (_MX6Q_PAD_RGMII_TXC__ANATOP_ANATOP_24M_OUT) ++ ++#define MX6Q_PAD_RGMII_TD0__MIPI_HSI_CTRL_TX_READY (_MX6Q_PAD_RGMII_TD0__MIPI_HSI_CTRL_TX_READY) ++#define MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 (_MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL)) ++#define MX6Q_PAD_RGMII_TD0__GPIO_6_20 (_MX6Q_PAD_RGMII_TD0__GPIO_6_20) ++#define MX6Q_PAD_RGMII_TD0__MIPI_CORE_DPHY_TEST_IN_1 (_MX6Q_PAD_RGMII_TD0__MIPI_CORE_DPHY_TEST_IN_1) ++ ++#define MX6Q_PAD_RGMII_TD1__MIPI_HSI_CTRL_RX_FLAG (_MX6Q_PAD_RGMII_TD1__MIPI_HSI_CTRL_RX_FLAG) ++#define MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 (_MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL)) ++#define MX6Q_PAD_RGMII_TD1__GPIO_6_21 (_MX6Q_PAD_RGMII_TD1__GPIO_6_21) ++#define MX6Q_PAD_RGMII_TD1__MIPI_CORE_DPHY_TEST_IN_2 (_MX6Q_PAD_RGMII_TD1__MIPI_CORE_DPHY_TEST_IN_2) ++#define MX6Q_PAD_RGMII_TD1__CCM_PLL3_BYP (_MX6Q_PAD_RGMII_TD1__CCM_PLL3_BYP) ++ ++#define MX6Q_PAD_RGMII_TD2__MIPI_HSI_CTRL_RX_DATA (_MX6Q_PAD_RGMII_TD2__MIPI_HSI_CTRL_RX_DATA) ++#define MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 (_MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL)) ++#define MX6Q_PAD_RGMII_TD2__GPIO_6_22 (_MX6Q_PAD_RGMII_TD2__GPIO_6_22) ++#define MX6Q_PAD_RGMII_TD2__MIPI_CORE_DPHY_TEST_IN_3 (_MX6Q_PAD_RGMII_TD2__MIPI_CORE_DPHY_TEST_IN_3) ++#define MX6Q_PAD_RGMII_TD2__CCM_PLL2_BYP (_MX6Q_PAD_RGMII_TD2__CCM_PLL2_BYP) ++ ++#define MX6Q_PAD_RGMII_TD3__MIPI_HSI_CTRL_RX_WAKE (_MX6Q_PAD_RGMII_TD3__MIPI_HSI_CTRL_RX_WAKE) ++#define MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 (_MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL)) ++#define MX6Q_PAD_RGMII_TD3__GPIO_6_23 (_MX6Q_PAD_RGMII_TD3__GPIO_6_23) ++#define MX6Q_PAD_RGMII_TD3__MIPI_CORE_DPHY_TEST_IN_4 (_MX6Q_PAD_RGMII_TD3__MIPI_CORE_DPHY_TEST_IN_4) ++ ++#define MX6Q_PAD_RGMII_RX_CTL__USBOH3_H3_DATA (_MX6Q_PAD_RGMII_RX_CTL__USBOH3_H3_DATA) ++#define MX6Q_PAD_RGMII_RX_CTL__ENET_RGMII_RX_CTL (_MX6Q_PAD_RGMII_RX_CTL__ENET_RGMII_RX_CTL | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL)) ++#define MX6Q_PAD_RGMII_RX_CTL__GPIO_6_24 (_MX6Q_PAD_RGMII_RX_CTL__GPIO_6_24) ++#define MX6Q_PAD_RGMII_RX_CTL__MIPI_CORE_DPHY_TEST_IN_5 (_MX6Q_PAD_RGMII_RX_CTL__MIPI_CORE_DPHY_TEST_IN_5) ++ ++#define MX6Q_PAD_RGMII_RD0__MIPI_HSI_CTRL_RX_READY (_MX6Q_PAD_RGMII_RD0__MIPI_HSI_CTRL_RX_READY) ++#define MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 (_MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL)) ++#define MX6Q_PAD_RGMII_RD0__GPIO_6_25 (_MX6Q_PAD_RGMII_RD0__GPIO_6_25) ++#define MX6Q_PAD_RGMII_RD0__MIPI_CORE_DPHY_TEST_IN_6 (_MX6Q_PAD_RGMII_RD0__MIPI_CORE_DPHY_TEST_IN_6) ++ ++#define MX6Q_PAD_RGMII_TX_CTL__USBOH3_H2_STROBE (_MX6Q_PAD_RGMII_TX_CTL__USBOH3_H2_STROBE) ++#define MX6Q_PAD_RGMII_TX_CTL__ENET_RGMII_TX_CTL (_MX6Q_PAD_RGMII_TX_CTL__ENET_RGMII_TX_CTL | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL)) ++#define MX6Q_PAD_RGMII_TX_CTL__GPIO_6_26 (_MX6Q_PAD_RGMII_TX_CTL__GPIO_6_26) ++#define MX6Q_PAD_RGMII_TX_CTL__MIPI_CORE_DPHY_TEST_IN_7 (_MX6Q_PAD_RGMII_TX_CTL__MIPI_CORE_DPHY_TEST_IN_7) ++#define MX6Q_PAD_RGMII_TX_CTL__ENET_ANATOP_ETHERNET_REF_OUT (_MX6Q_PAD_RGMII_TX_CTL__ENET_ANATOP_ETHERNET_REF_OUT) ++ ++#define MX6Q_PAD_RGMII_RD1__MIPI_HSI_CTRL_TX_FLAG (_MX6Q_PAD_RGMII_RD1__MIPI_HSI_CTRL_TX_FLAG) ++#define MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 (_MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL)) ++#define MX6Q_PAD_RGMII_RD1__GPIO_6_27 (_MX6Q_PAD_RGMII_RD1__GPIO_6_27) ++#define MX6Q_PAD_RGMII_RD1__MIPI_CORE_DPHY_TEST_IN_8 (_MX6Q_PAD_RGMII_RD1__MIPI_CORE_DPHY_TEST_IN_8) ++#define MX6Q_PAD_RGMII_RD1__SJC_FAIL (_MX6Q_PAD_RGMII_RD1__SJC_FAIL) ++ ++#define MX6Q_PAD_RGMII_RD2__MIPI_HSI_CTRL_TX_DATA (_MX6Q_PAD_RGMII_RD2__MIPI_HSI_CTRL_TX_DATA) ++#define MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 (_MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL)) ++#define MX6Q_PAD_RGMII_RD2__GPIO_6_28 (_MX6Q_PAD_RGMII_RD2__GPIO_6_28) ++#define MX6Q_PAD_RGMII_RD2__MIPI_CORE_DPHY_TEST_IN_9 (_MX6Q_PAD_RGMII_RD2__MIPI_CORE_DPHY_TEST_IN_9) ++ ++#define MX6Q_PAD_RGMII_RD3__MIPI_HSI_CTRL_TX_WAKE (_MX6Q_PAD_RGMII_RD3__MIPI_HSI_CTRL_TX_WAKE) ++#define MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 (_MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL)) ++#define MX6Q_PAD_RGMII_RD3__GPIO_6_29 (_MX6Q_PAD_RGMII_RD3__GPIO_6_29) ++#define MX6Q_PAD_RGMII_RD3__MIPI_CORE_DPHY_TEST_IN_10 (_MX6Q_PAD_RGMII_RD3__MIPI_CORE_DPHY_TEST_IN_10) ++ ++#define MX6Q_PAD_RGMII_RXC__USBOH3_H3_STROBE (_MX6Q_PAD_RGMII_RXC__USBOH3_H3_STROBE) ++#define MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC (_MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL)) ++#define MX6Q_PAD_RGMII_RXC__GPIO_6_30 (_MX6Q_PAD_RGMII_RXC__GPIO_6_30) ++#define MX6Q_PAD_RGMII_RXC__MIPI_CORE_DPHY_TEST_IN_11 (_MX6Q_PAD_RGMII_RXC__MIPI_CORE_DPHY_TEST_IN_11) ++ ++#define MX6Q_PAD_EIM_A25__WEIM_WEIM_A_25 (_MX6Q_PAD_EIM_A25__WEIM_WEIM_A_25) ++#define MX6Q_PAD_EIM_A25__ECSPI4_SS1 (_MX6Q_PAD_EIM_A25__ECSPI4_SS1) ++#define MX6Q_PAD_EIM_A25__ECSPI2_RDY (_MX6Q_PAD_EIM_A25__ECSPI2_RDY) ++#define MX6Q_PAD_EIM_A25__IPU1_DI1_PIN12 (_MX6Q_PAD_EIM_A25__IPU1_DI1_PIN12) ++#define MX6Q_PAD_EIM_A25__IPU1_DI0_D1_CS (_MX6Q_PAD_EIM_A25__IPU1_DI0_D1_CS) ++#define MX6Q_PAD_EIM_A25__GPIO_5_2 (_MX6Q_PAD_EIM_A25__GPIO_5_2) ++#define MX6Q_PAD_EIM_A25__HDMI_TX_CEC_LINE (_MX6Q_PAD_EIM_A25__HDMI_TX_CEC_LINE) ++#define MX6Q_PAD_EIM_A25__PL301_MX6QPER1_HBURST_0 (_MX6Q_PAD_EIM_A25__PL301_MX6QPER1_HBURST_0) ++ ++#define MX6Q_PAD_EIM_EB2__WEIM_WEIM_EB_2 (_MX6Q_PAD_EIM_EB2__WEIM_WEIM_EB_2) ++#define MX6Q_PAD_EIM_EB2__ECSPI1_SS0 (_MX6Q_PAD_EIM_EB2__ECSPI1_SS0 | MUX_PAD_CTRL(MX6Q_ECSPI_PAD_CTRL)) ++#define MX6Q_PAD_EIM_EB2__CCM_DI1_EXT_CLK (_MX6Q_PAD_EIM_EB2__CCM_DI1_EXT_CLK) ++#define MX6Q_PAD_EIM_EB2__IPU2_CSI1_D_19 (_MX6Q_PAD_EIM_EB2__IPU2_CSI1_D_19) ++#define MX6Q_PAD_EIM_EB2__HDMI_TX_DDC_SCL (_MX6Q_PAD_EIM_EB2__HDMI_TX_DDC_SCL) ++#define MX6Q_PAD_EIM_EB2__GPIO_2_30 (_MX6Q_PAD_EIM_EB2__GPIO_2_30) ++#define MX6Q_PAD_EIM_EB2__I2C2_SCL (_MX6Q_PAD_EIM_EB2__I2C2_SCL | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL)) ++#define MX6Q_PAD_EIM_EB2__SRC_BT_CFG_30 (_MX6Q_PAD_EIM_EB2__SRC_BT_CFG_30) ++ ++#define MX6Q_PAD_EIM_D16__WEIM_WEIM_D_16 (_MX6Q_PAD_EIM_D16__WEIM_WEIM_D_16) ++#define MX6Q_PAD_EIM_D16__ECSPI1_SCLK (_MX6Q_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(MX6Q_ECSPI_PAD_CTRL)) ++#define MX6Q_PAD_EIM_D16__IPU1_DI0_PIN5 (_MX6Q_PAD_EIM_D16__IPU1_DI0_PIN5) ++#define MX6Q_PAD_EIM_D16__IPU2_CSI1_D_18 (_MX6Q_PAD_EIM_D16__IPU2_CSI1_D_18) ++#define MX6Q_PAD_EIM_D16__HDMI_TX_DDC_SDA (_MX6Q_PAD_EIM_D16__HDMI_TX_DDC_SDA) ++#define MX6Q_PAD_EIM_D16__GPIO_3_16 (_MX6Q_PAD_EIM_D16__GPIO_3_16) ++#define MX6Q_PAD_EIM_D16__I2C2_SDA (_MX6Q_PAD_EIM_D16__I2C2_SDA | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL)) ++ ++#define MX6Q_PAD_EIM_D17__WEIM_WEIM_D_17 (_MX6Q_PAD_EIM_D17__WEIM_WEIM_D_17) ++#define MX6Q_PAD_EIM_D17__ECSPI1_MISO (_MX6Q_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(MX6Q_ECSPI_PAD_CTRL)) ++#define MX6Q_PAD_EIM_D17__IPU1_DI0_PIN6 (_MX6Q_PAD_EIM_D17__IPU1_DI0_PIN6) ++#define MX6Q_PAD_EIM_D17__IPU2_CSI1_PIXCLK (_MX6Q_PAD_EIM_D17__IPU2_CSI1_PIXCLK) ++#define MX6Q_PAD_EIM_D17__DCIC1_DCIC_OUT (_MX6Q_PAD_EIM_D17__DCIC1_DCIC_OUT) ++#define MX6Q_PAD_EIM_D17__GPIO_3_17 (_MX6Q_PAD_EIM_D17__GPIO_3_17) ++#define MX6Q_PAD_EIM_D17__I2C3_SCL (_MX6Q_PAD_EIM_D17__I2C3_SCL | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL)) ++#define MX6Q_PAD_EIM_D17__PL301_MX6QPER1_HBURST_1 (_MX6Q_PAD_EIM_D17__PL301_MX6QPER1_HBURST_1) ++ ++#define MX6Q_PAD_EIM_D18__WEIM_WEIM_D_18 (_MX6Q_PAD_EIM_D18__WEIM_WEIM_D_18) ++#define MX6Q_PAD_EIM_D18__ECSPI1_MOSI (_MX6Q_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(MX6Q_ECSPI_PAD_CTRL)) ++#define MX6Q_PAD_EIM_D18__IPU1_DI0_PIN7 (_MX6Q_PAD_EIM_D18__IPU1_DI0_PIN7) ++#define MX6Q_PAD_EIM_D18__IPU2_CSI1_D_17 (_MX6Q_PAD_EIM_D18__IPU2_CSI1_D_17) ++#define MX6Q_PAD_EIM_D18__IPU1_DI1_D0_CS (_MX6Q_PAD_EIM_D18__IPU1_DI1_D0_CS) ++#define MX6Q_PAD_EIM_D18__GPIO_3_18 (_MX6Q_PAD_EIM_D18__GPIO_3_18) ++#define MX6Q_PAD_EIM_D18__I2C3_SDA (_MX6Q_PAD_EIM_D18__I2C3_SDA | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL)) ++#define MX6Q_PAD_EIM_D18__PL301_MX6QPER1_HBURST_2 (_MX6Q_PAD_EIM_D18__PL301_MX6QPER1_HBURST_2) ++ ++#define MX6Q_PAD_EIM_D19__WEIM_WEIM_D_19 (_MX6Q_PAD_EIM_D19__WEIM_WEIM_D_19) ++#define MX6Q_PAD_EIM_D19__ECSPI1_SS1 (_MX6Q_PAD_EIM_D19__ECSPI1_SS1 | MUX_PAD_CTRL(MX6Q_ECSPI_PAD_CTRL)) ++#define MX6Q_PAD_EIM_D19__IPU1_DI0_PIN8 (_MX6Q_PAD_EIM_D19__IPU1_DI0_PIN8) ++#define MX6Q_PAD_EIM_D19__IPU2_CSI1_D_16 (_MX6Q_PAD_EIM_D19__IPU2_CSI1_D_16) ++#define MX6Q_PAD_EIM_D19__UART1_CTS (_MX6Q_PAD_EIM_D19__UART1_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) ++#define MX6Q_PAD_EIM_D19__GPIO_3_19 (_MX6Q_PAD_EIM_D19__GPIO_3_19) ++#define MX6Q_PAD_EIM_D19__EPIT1_EPITO (_MX6Q_PAD_EIM_D19__EPIT1_EPITO) ++#define MX6Q_PAD_EIM_D19__PL301_MX6QPER1_HRESP (_MX6Q_PAD_EIM_D19__PL301_MX6QPER1_HRESP) ++ ++#define MX6Q_PAD_EIM_D20__WEIM_WEIM_D_20 (_MX6Q_PAD_EIM_D20__WEIM_WEIM_D_20) ++#define MX6Q_PAD_EIM_D20__ECSPI4_SS0 (_MX6Q_PAD_EIM_D20__ECSPI4_SS0) ++#define MX6Q_PAD_EIM_D20__IPU1_DI0_PIN16 (_MX6Q_PAD_EIM_D20__IPU1_DI0_PIN16) ++#define MX6Q_PAD_EIM_D20__IPU2_CSI1_D_15 (_MX6Q_PAD_EIM_D20__IPU2_CSI1_D_15) ++#define MX6Q_PAD_EIM_D20__UART1_CTS (_MX6Q_PAD_EIM_D20__UART1_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) ++#define MX6Q_PAD_EIM_D20__UART1_RTS (_MX6Q_PAD_EIM_D20__UART1_RTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) ++#define MX6Q_PAD_EIM_D20__GPIO_3_20 (_MX6Q_PAD_EIM_D20__GPIO_3_20) ++#define MX6Q_PAD_EIM_D20__EPIT2_EPITO (_MX6Q_PAD_EIM_D20__EPIT2_EPITO) ++ ++#define MX6Q_PAD_EIM_D21__WEIM_WEIM_D_21 (_MX6Q_PAD_EIM_D21__WEIM_WEIM_D_21) ++#define MX6Q_PAD_EIM_D21__ECSPI4_SCLK (_MX6Q_PAD_EIM_D21__ECSPI4_SCLK) ++#define MX6Q_PAD_EIM_D21__IPU1_DI0_PIN17 (_MX6Q_PAD_EIM_D21__IPU1_DI0_PIN17) ++#define MX6Q_PAD_EIM_D21__IPU2_CSI1_D_11 (_MX6Q_PAD_EIM_D21__IPU2_CSI1_D_11) ++#define MX6Q_PAD_EIM_D21__USBOH3_USBOTG_OC (_MX6Q_PAD_EIM_D21__USBOH3_USBOTG_OC) ++#define MX6Q_PAD_EIM_D21__GPIO_3_21 (_MX6Q_PAD_EIM_D21__GPIO_3_21) ++#define MX6Q_PAD_EIM_D21__I2C1_SCL (_MX6Q_PAD_EIM_D21__I2C1_SCL | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL)) ++#define MX6Q_PAD_EIM_D21__SPDIF_IN1 (_MX6Q_PAD_EIM_D21__SPDIF_IN1) ++ ++#define MX6Q_PAD_EIM_D22__WEIM_WEIM_D_22 (_MX6Q_PAD_EIM_D22__WEIM_WEIM_D_22) ++#define MX6Q_PAD_EIM_D22__ECSPI4_MISO (_MX6Q_PAD_EIM_D22__ECSPI4_MISO) ++#define MX6Q_PAD_EIM_D22__IPU1_DI0_PIN1 (_MX6Q_PAD_EIM_D22__IPU1_DI0_PIN1) ++#define MX6Q_PAD_EIM_D22__IPU2_CSI1_D_10 (_MX6Q_PAD_EIM_D22__IPU2_CSI1_D_10) ++#define MX6Q_PAD_EIM_D22__USBOH3_USBOTG_PWR (_MX6Q_PAD_EIM_D22__USBOH3_USBOTG_PWR) ++#define MX6Q_PAD_EIM_D22__GPIO_3_22 (_MX6Q_PAD_EIM_D22__GPIO_3_22) ++#define MX6Q_PAD_EIM_D22__SPDIF_OUT1 (_MX6Q_PAD_EIM_D22__SPDIF_OUT1) ++#define MX6Q_PAD_EIM_D22__PL301_MX6QPER1_HWRITE (_MX6Q_PAD_EIM_D22__PL301_MX6QPER1_HWRITE) ++ ++#define MX6Q_PAD_EIM_D23__WEIM_WEIM_D_23 (_MX6Q_PAD_EIM_D23__WEIM_WEIM_D_23) ++#define MX6Q_PAD_EIM_D23__IPU1_DI0_D0_CS (_MX6Q_PAD_EIM_D23__IPU1_DI0_D0_CS) ++#define MX6Q_PAD_EIM_D23__UART3_CTS (_MX6Q_PAD_EIM_D23__UART3_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) ++#define MX6Q_PAD_EIM_D23__UART1_DCD (_MX6Q_PAD_EIM_D23__UART1_DCD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) ++#define MX6Q_PAD_EIM_D23__IPU2_CSI1_DATA_EN (_MX6Q_PAD_EIM_D23__IPU2_CSI1_DATA_EN) ++#define MX6Q_PAD_EIM_D23__GPIO_3_23 (_MX6Q_PAD_EIM_D23__GPIO_3_23) ++#define MX6Q_PAD_EIM_D23__IPU1_DI1_PIN2 (_MX6Q_PAD_EIM_D23__IPU1_DI1_PIN2) ++#define MX6Q_PAD_EIM_D23__IPU1_DI1_PIN14 (_MX6Q_PAD_EIM_D23__IPU1_DI1_PIN14) ++ ++#define MX6Q_PAD_EIM_EB3__WEIM_WEIM_EB_3 (_MX6Q_PAD_EIM_EB3__WEIM_WEIM_EB_3) ++#define MX6Q_PAD_EIM_EB3__ECSPI4_RDY (_MX6Q_PAD_EIM_EB3__ECSPI4_RDY) ++#define MX6Q_PAD_EIM_EB3__UART3_CTS (_MX6Q_PAD_EIM_EB3__UART3_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) ++#define MX6Q_PAD_EIM_EB3__UART3_RTS (_MX6Q_PAD_EIM_EB3__UART3_RTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) ++#define MX6Q_PAD_EIM_EB3__UART1_RI (_MX6Q_PAD_EIM_EB3__UART1_RI | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) ++#define MX6Q_PAD_EIM_EB3__IPU2_CSI1_HSYNC (_MX6Q_PAD_EIM_EB3__IPU2_CSI1_HSYNC) ++#define MX6Q_PAD_EIM_EB3__GPIO_2_31 (_MX6Q_PAD_EIM_EB3__GPIO_2_31) ++#define MX6Q_PAD_EIM_EB3__IPU1_DI1_PIN3 (_MX6Q_PAD_EIM_EB3__IPU1_DI1_PIN3) ++#define MX6Q_PAD_EIM_EB3__SRC_BT_CFG_31 (_MX6Q_PAD_EIM_EB3__SRC_BT_CFG_31) ++ ++#define MX6Q_PAD_EIM_D24__WEIM_WEIM_D_24 (_MX6Q_PAD_EIM_D24__WEIM_WEIM_D_24) ++#define MX6Q_PAD_EIM_D24__ECSPI4_SS2 (_MX6Q_PAD_EIM_D24__ECSPI4_SS2) ++#define MX6Q_PAD_EIM_D24__UART3_TXD (_MX6Q_PAD_EIM_D24__UART3_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) ++#define MX6Q_PAD_EIM_D24__UART3_RXD (_MX6Q_PAD_EIM_D24__UART3_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) ++#define MX6Q_PAD_EIM_D24__ECSPI1_SS2 (_MX6Q_PAD_EIM_D24__ECSPI1_SS2) ++#define MX6Q_PAD_EIM_D24__ECSPI2_SS2 (_MX6Q_PAD_EIM_D24__ECSPI2_SS2) ++#define MX6Q_PAD_EIM_D24__GPIO_3_24 (_MX6Q_PAD_EIM_D24__GPIO_3_24) ++#define MX6Q_PAD_EIM_D24__AUDMUX_AUD5_RXFS (_MX6Q_PAD_EIM_D24__AUDMUX_AUD5_RXFS) ++#define MX6Q_PAD_EIM_D24__UART1_DTR (_MX6Q_PAD_EIM_D24__UART1_DTR | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) ++ ++#define MX6Q_PAD_EIM_D25__WEIM_WEIM_D_25 (_MX6Q_PAD_EIM_D25__WEIM_WEIM_D_25) ++#define MX6Q_PAD_EIM_D25__ECSPI4_SS3 (_MX6Q_PAD_EIM_D25__ECSPI4_SS3) ++#define MX6Q_PAD_EIM_D25__UART3_TXD (_MX6Q_PAD_EIM_D25__UART3_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) ++#define MX6Q_PAD_EIM_D25__UART3_RXD (_MX6Q_PAD_EIM_D25__UART3_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) ++#define MX6Q_PAD_EIM_D25__ECSPI1_SS3 (_MX6Q_PAD_EIM_D25__ECSPI1_SS3) ++#define MX6Q_PAD_EIM_D25__ECSPI2_SS3 (_MX6Q_PAD_EIM_D25__ECSPI2_SS3) ++#define MX6Q_PAD_EIM_D25__GPIO_3_25 (_MX6Q_PAD_EIM_D25__GPIO_3_25) ++#define MX6Q_PAD_EIM_D25__AUDMUX_AUD5_RXC (_MX6Q_PAD_EIM_D25__AUDMUX_AUD5_RXC) ++#define MX6Q_PAD_EIM_D25__UART1_DSR (_MX6Q_PAD_EIM_D25__UART1_DSR | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) ++ ++#define MX6Q_PAD_EIM_D26__WEIM_WEIM_D_26 (_MX6Q_PAD_EIM_D26__WEIM_WEIM_D_26) ++#define MX6Q_PAD_EIM_D26__IPU1_DI1_PIN11 (_MX6Q_PAD_EIM_D26__IPU1_DI1_PIN11) ++#define MX6Q_PAD_EIM_D26__IPU1_CSI0_D_1 (_MX6Q_PAD_EIM_D26__IPU1_CSI0_D_1) ++#define MX6Q_PAD_EIM_D26__IPU2_CSI1_D_14 (_MX6Q_PAD_EIM_D26__IPU2_CSI1_D_14) ++#define MX6Q_PAD_EIM_D26__UART2_TXD (_MX6Q_PAD_EIM_D26__UART2_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) ++#define MX6Q_PAD_EIM_D26__UART2_RXD (_MX6Q_PAD_EIM_D26__UART2_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) ++#define MX6Q_PAD_EIM_D26__GPIO_3_26 (_MX6Q_PAD_EIM_D26__GPIO_3_26) ++#define MX6Q_PAD_EIM_D26__IPU1_SISG_2 (_MX6Q_PAD_EIM_D26__IPU1_SISG_2) ++#define MX6Q_PAD_EIM_D26__IPU1_DISP1_DAT_22 (_MX6Q_PAD_EIM_D26__IPU1_DISP1_DAT_22) ++ ++#define MX6Q_PAD_EIM_D27__WEIM_WEIM_D_27 (_MX6Q_PAD_EIM_D27__WEIM_WEIM_D_27) ++#define MX6Q_PAD_EIM_D27__IPU1_DI1_PIN13 (_MX6Q_PAD_EIM_D27__IPU1_DI1_PIN13) ++#define MX6Q_PAD_EIM_D27__IPU1_CSI0_D_0 (_MX6Q_PAD_EIM_D27__IPU1_CSI0_D_0) ++#define MX6Q_PAD_EIM_D27__IPU2_CSI1_D_13 (_MX6Q_PAD_EIM_D27__IPU2_CSI1_D_13) ++#define MX6Q_PAD_EIM_D27__UART2_TXD (_MX6Q_PAD_EIM_D27__UART2_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) ++#define MX6Q_PAD_EIM_D27__UART2_RXD (_MX6Q_PAD_EIM_D27__UART2_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) ++#define MX6Q_PAD_EIM_D27__GPIO_3_27 (_MX6Q_PAD_EIM_D27__GPIO_3_27) ++#define MX6Q_PAD_EIM_D27__IPU1_SISG_3 (_MX6Q_PAD_EIM_D27__IPU1_SISG_3) ++#define MX6Q_PAD_EIM_D27__IPU1_DISP1_DAT_23 (_MX6Q_PAD_EIM_D27__IPU1_DISP1_DAT_23) ++ ++#define MX6Q_PAD_EIM_D28__WEIM_WEIM_D_28 (_MX6Q_PAD_EIM_D28__WEIM_WEIM_D_28) ++#define MX6Q_PAD_EIM_D28__I2C1_SDA (_MX6Q_PAD_EIM_D28__I2C1_SDA | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL)) ++#define MX6Q_PAD_EIM_D28__ECSPI4_MOSI (_MX6Q_PAD_EIM_D28__ECSPI4_MOSI) ++#define MX6Q_PAD_EIM_D28__IPU2_CSI1_D_12 (_MX6Q_PAD_EIM_D28__IPU2_CSI1_D_12) ++#define MX6Q_PAD_EIM_D28__UART2_CTS (_MX6Q_PAD_EIM_D28__UART2_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) ++#define MX6Q_PAD_EIM_D28__GPIO_3_28 (_MX6Q_PAD_EIM_D28__GPIO_3_28) ++#define MX6Q_PAD_EIM_D28__IPU1_EXT_TRIG (_MX6Q_PAD_EIM_D28__IPU1_EXT_TRIG) ++#define MX6Q_PAD_EIM_D28__IPU1_DI0_PIN13 (_MX6Q_PAD_EIM_D28__IPU1_DI0_PIN13) ++ ++#define MX6Q_PAD_EIM_D29__WEIM_WEIM_D_29 (_MX6Q_PAD_EIM_D29__WEIM_WEIM_D_29) ++#define MX6Q_PAD_EIM_D29__IPU1_DI1_PIN15 (_MX6Q_PAD_EIM_D29__IPU1_DI1_PIN15) ++#define MX6Q_PAD_EIM_D29__ECSPI4_SS0 (_MX6Q_PAD_EIM_D29__ECSPI4_SS0) ++#define MX6Q_PAD_EIM_D29__UART2_CTS (_MX6Q_PAD_EIM_D29__UART2_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) ++#define MX6Q_PAD_EIM_D29__UART2_RTS (_MX6Q_PAD_EIM_D29__UART2_RTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) ++#define MX6Q_PAD_EIM_D29__GPIO_3_29 (_MX6Q_PAD_EIM_D29__GPIO_3_29) ++#define MX6Q_PAD_EIM_D29__IPU2_CSI1_VSYNC (_MX6Q_PAD_EIM_D29__IPU2_CSI1_VSYNC) ++#define MX6Q_PAD_EIM_D29__IPU1_DI0_PIN14 (_MX6Q_PAD_EIM_D29__IPU1_DI0_PIN14) ++ ++#define MX6Q_PAD_EIM_D30__WEIM_WEIM_D_30 (_MX6Q_PAD_EIM_D30__WEIM_WEIM_D_30) ++#define MX6Q_PAD_EIM_D30__IPU1_DISP1_DAT_21 (_MX6Q_PAD_EIM_D30__IPU1_DISP1_DAT_21) ++#define MX6Q_PAD_EIM_D30__IPU1_DI0_PIN11 (_MX6Q_PAD_EIM_D30__IPU1_DI0_PIN11) ++#define MX6Q_PAD_EIM_D30__IPU1_CSI0_D_3 (_MX6Q_PAD_EIM_D30__IPU1_CSI0_D_3) ++#define MX6Q_PAD_EIM_D30__UART3_CTS (_MX6Q_PAD_EIM_D30__UART3_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) ++#define MX6Q_PAD_EIM_D30__GPIO_3_30 (_MX6Q_PAD_EIM_D30__GPIO_3_30) ++#define MX6Q_PAD_EIM_D30__USBOH3_USBH1_OC (_MX6Q_PAD_EIM_D30__USBOH3_USBH1_OC) ++#define MX6Q_PAD_EIM_D30__PL301_MX6QPER1_HPROT_0 (_MX6Q_PAD_EIM_D30__PL301_MX6QPER1_HPROT_0) ++ ++#define MX6Q_PAD_EIM_D31__WEIM_WEIM_D_31 (_MX6Q_PAD_EIM_D31__WEIM_WEIM_D_31) ++#define MX6Q_PAD_EIM_D31__IPU1_DISP1_DAT_20 (_MX6Q_PAD_EIM_D31__IPU1_DISP1_DAT_20) ++#define MX6Q_PAD_EIM_D31__IPU1_DI0_PIN12 (_MX6Q_PAD_EIM_D31__IPU1_DI0_PIN12) ++#define MX6Q_PAD_EIM_D31__IPU1_CSI0_D_2 (_MX6Q_PAD_EIM_D31__IPU1_CSI0_D_2) ++#define MX6Q_PAD_EIM_D31__UART3_CTS (_MX6Q_PAD_EIM_D31__UART3_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) ++#define MX6Q_PAD_EIM_D31__UART3_RTS (_MX6Q_PAD_EIM_D31__UART3_RTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) ++#define MX6Q_PAD_EIM_D31__GPIO_3_31 (_MX6Q_PAD_EIM_D31__GPIO_3_31) ++#define MX6Q_PAD_EIM_D31__USBOH3_USBH1_PWR (_MX6Q_PAD_EIM_D31__USBOH3_USBH1_PWR) ++#define MX6Q_PAD_EIM_D31__PL301_MX6QPER1_HPROT_1 (_MX6Q_PAD_EIM_D31__PL301_MX6QPER1_HPROT_1) ++ ++#define MX6Q_PAD_EIM_A24__WEIM_WEIM_A_24 (_MX6Q_PAD_EIM_A24__WEIM_WEIM_A_24) ++#define MX6Q_PAD_EIM_A24__IPU1_DISP1_DAT_19 (_MX6Q_PAD_EIM_A24__IPU1_DISP1_DAT_19) ++#define MX6Q_PAD_EIM_A24__IPU2_CSI1_D_19 (_MX6Q_PAD_EIM_A24__IPU2_CSI1_D_19) ++#define MX6Q_PAD_EIM_A24__IPU2_SISG_2 (_MX6Q_PAD_EIM_A24__IPU2_SISG_2) ++#define MX6Q_PAD_EIM_A24__IPU1_SISG_2 (_MX6Q_PAD_EIM_A24__IPU1_SISG_2) ++#define MX6Q_PAD_EIM_A24__GPIO_5_4 (_MX6Q_PAD_EIM_A24__GPIO_5_4) ++#define MX6Q_PAD_EIM_A24__PL301_MX6QPER1_HPROT_2 (_MX6Q_PAD_EIM_A24__PL301_MX6QPER1_HPROT_2) ++#define MX6Q_PAD_EIM_A24__SRC_BT_CFG_24 (_MX6Q_PAD_EIM_A24__SRC_BT_CFG_24) ++ ++#define MX6Q_PAD_EIM_A23__WEIM_WEIM_A_23 (_MX6Q_PAD_EIM_A23__WEIM_WEIM_A_23) ++#define MX6Q_PAD_EIM_A23__IPU1_DISP1_DAT_18 (_MX6Q_PAD_EIM_A23__IPU1_DISP1_DAT_18) ++#define MX6Q_PAD_EIM_A23__IPU2_CSI1_D_18 (_MX6Q_PAD_EIM_A23__IPU2_CSI1_D_18) ++#define MX6Q_PAD_EIM_A23__IPU2_SISG_3 (_MX6Q_PAD_EIM_A23__IPU2_SISG_3) ++#define MX6Q_PAD_EIM_A23__IPU1_SISG_3 (_MX6Q_PAD_EIM_A23__IPU1_SISG_3) ++#define MX6Q_PAD_EIM_A23__GPIO_6_6 (_MX6Q_PAD_EIM_A23__GPIO_6_6) ++#define MX6Q_PAD_EIM_A23__PL301_MX6QPER1_HPROT_3 (_MX6Q_PAD_EIM_A23__PL301_MX6QPER1_HPROT_3) ++#define MX6Q_PAD_EIM_A23__SRC_BT_CFG_23 (_MX6Q_PAD_EIM_A23__SRC_BT_CFG_23) ++ ++#define MX6Q_PAD_EIM_A22__WEIM_WEIM_A_22 (_MX6Q_PAD_EIM_A22__WEIM_WEIM_A_22) ++#define MX6Q_PAD_EIM_A22__IPU1_DISP1_DAT_17 (_MX6Q_PAD_EIM_A22__IPU1_DISP1_DAT_17) ++#define MX6Q_PAD_EIM_A22__IPU2_CSI1_D_17 (_MX6Q_PAD_EIM_A22__IPU2_CSI1_D_17) ++#define MX6Q_PAD_EIM_A22__GPIO_2_16 (_MX6Q_PAD_EIM_A22__GPIO_2_16) ++#define MX6Q_PAD_EIM_A22__TPSMP_HDATA_0 (_MX6Q_PAD_EIM_A22__TPSMP_HDATA_0) ++#define MX6Q_PAD_EIM_A22__SRC_BT_CFG_22 (_MX6Q_PAD_EIM_A22__SRC_BT_CFG_22) ++ ++#define MX6Q_PAD_EIM_A21__WEIM_WEIM_A_21 (_MX6Q_PAD_EIM_A21__WEIM_WEIM_A_21) ++#define MX6Q_PAD_EIM_A21__IPU1_DISP1_DAT_16 (_MX6Q_PAD_EIM_A21__IPU1_DISP1_DAT_16) ++#define MX6Q_PAD_EIM_A21__IPU2_CSI1_D_16 (_MX6Q_PAD_EIM_A21__IPU2_CSI1_D_16) ++#define MX6Q_PAD_EIM_A21__MIPI_CORE_DPHY_TEST_OUT_18 (_MX6Q_PAD_EIM_A21__MIPI_CORE_DPHY_TEST_OUT_18) ++#define MX6Q_PAD_EIM_A21__GPIO_2_17 (_MX6Q_PAD_EIM_A21__GPIO_2_17) ++#define MX6Q_PAD_EIM_A21__TPSMP_HDATA_1 (_MX6Q_PAD_EIM_A21__TPSMP_HDATA_1) ++#define MX6Q_PAD_EIM_A21__SRC_BT_CFG_21 (_MX6Q_PAD_EIM_A21__SRC_BT_CFG_21) ++ ++#define MX6Q_PAD_EIM_A20__WEIM_WEIM_A_20 (_MX6Q_PAD_EIM_A20__WEIM_WEIM_A_20) ++#define MX6Q_PAD_EIM_A20__IPU1_DISP1_DAT_15 (_MX6Q_PAD_EIM_A20__IPU1_DISP1_DAT_15) ++#define MX6Q_PAD_EIM_A20__IPU2_CSI1_D_15 (_MX6Q_PAD_EIM_A20__IPU2_CSI1_D_15) ++#define MX6Q_PAD_EIM_A20__MIPI_CORE_DPHY_TEST_OUT_19 (_MX6Q_PAD_EIM_A20__MIPI_CORE_DPHY_TEST_OUT_19) ++#define MX6Q_PAD_EIM_A20__GPIO_2_18 (_MX6Q_PAD_EIM_A20__GPIO_2_18) ++#define MX6Q_PAD_EIM_A20__TPSMP_HDATA_2 (_MX6Q_PAD_EIM_A20__TPSMP_HDATA_2) ++#define MX6Q_PAD_EIM_A20__SRC_BT_CFG_20 (_MX6Q_PAD_EIM_A20__SRC_BT_CFG_20) ++ ++#define MX6Q_PAD_EIM_A19__WEIM_WEIM_A_19 (_MX6Q_PAD_EIM_A19__WEIM_WEIM_A_19) ++#define MX6Q_PAD_EIM_A19__IPU1_DISP1_DAT_14 (_MX6Q_PAD_EIM_A19__IPU1_DISP1_DAT_14) ++#define MX6Q_PAD_EIM_A19__IPU2_CSI1_D_14 (_MX6Q_PAD_EIM_A19__IPU2_CSI1_D_14) ++#define MX6Q_PAD_EIM_A19__MIPI_CORE_DPHY_TEST_OUT_20 (_MX6Q_PAD_EIM_A19__MIPI_CORE_DPHY_TEST_OUT_20) ++#define MX6Q_PAD_EIM_A19__GPIO_2_19 (_MX6Q_PAD_EIM_A19__GPIO_2_19) ++#define MX6Q_PAD_EIM_A19__TPSMP_HDATA_3 (_MX6Q_PAD_EIM_A19__TPSMP_HDATA_3) ++#define MX6Q_PAD_EIM_A19__SRC_BT_CFG_19 (_MX6Q_PAD_EIM_A19__SRC_BT_CFG_19) ++ ++#define MX6Q_PAD_EIM_A18__WEIM_WEIM_A_18 (_MX6Q_PAD_EIM_A18__WEIM_WEIM_A_18) ++#define MX6Q_PAD_EIM_A18__IPU1_DISP1_DAT_13 (_MX6Q_PAD_EIM_A18__IPU1_DISP1_DAT_13) ++#define MX6Q_PAD_EIM_A18__IPU2_CSI1_D_13 (_MX6Q_PAD_EIM_A18__IPU2_CSI1_D_13) ++#define MX6Q_PAD_EIM_A18__MIPI_CORE_DPHY_TEST_OUT_21 (_MX6Q_PAD_EIM_A18__MIPI_CORE_DPHY_TEST_OUT_21) ++#define MX6Q_PAD_EIM_A18__GPIO_2_20 (_MX6Q_PAD_EIM_A18__GPIO_2_20) ++#define MX6Q_PAD_EIM_A18__TPSMP_HDATA_4 (_MX6Q_PAD_EIM_A18__TPSMP_HDATA_4) ++#define MX6Q_PAD_EIM_A18__SRC_BT_CFG_18 (_MX6Q_PAD_EIM_A18__SRC_BT_CFG_18) ++ ++#define MX6Q_PAD_EIM_A17__WEIM_WEIM_A_17 (_MX6Q_PAD_EIM_A17__WEIM_WEIM_A_17) ++#define MX6Q_PAD_EIM_A17__IPU1_DISP1_DAT_12 (_MX6Q_PAD_EIM_A17__IPU1_DISP1_DAT_12) ++#define MX6Q_PAD_EIM_A17__IPU2_CSI1_D_12 (_MX6Q_PAD_EIM_A17__IPU2_CSI1_D_12) ++#define MX6Q_PAD_EIM_A17__MIPI_CORE_DPHY_TEST_OUT_22 (_MX6Q_PAD_EIM_A17__MIPI_CORE_DPHY_TEST_OUT_22) ++#define MX6Q_PAD_EIM_A17__GPIO_2_21 (_MX6Q_PAD_EIM_A17__GPIO_2_21) ++#define MX6Q_PAD_EIM_A17__TPSMP_HDATA_5 (_MX6Q_PAD_EIM_A17__TPSMP_HDATA_5) ++#define MX6Q_PAD_EIM_A17__SRC_BT_CFG_17 (_MX6Q_PAD_EIM_A17__SRC_BT_CFG_17) ++ ++#define MX6Q_PAD_EIM_A16__WEIM_WEIM_A_16 (_MX6Q_PAD_EIM_A16__WEIM_WEIM_A_16) ++#define MX6Q_PAD_EIM_A16__IPU1_DI1_DISP_CLK (_MX6Q_PAD_EIM_A16__IPU1_DI1_DISP_CLK) ++#define MX6Q_PAD_EIM_A16__IPU2_CSI1_PIXCLK (_MX6Q_PAD_EIM_A16__IPU2_CSI1_PIXCLK) ++#define MX6Q_PAD_EIM_A16__MIPI_CORE_DPHY_TEST_OUT_23 (_MX6Q_PAD_EIM_A16__MIPI_CORE_DPHY_TEST_OUT_23) ++#define MX6Q_PAD_EIM_A16__GPIO_2_22 (_MX6Q_PAD_EIM_A16__GPIO_2_22) ++#define MX6Q_PAD_EIM_A16__TPSMP_HDATA_6 (_MX6Q_PAD_EIM_A16__TPSMP_HDATA_6) ++#define MX6Q_PAD_EIM_A16__SRC_BT_CFG_16 (_MX6Q_PAD_EIM_A16__SRC_BT_CFG_16) ++ ++#define MX6Q_PAD_EIM_CS0__WEIM_WEIM_CS_0 (_MX6Q_PAD_EIM_CS0__WEIM_WEIM_CS_0) ++#define MX6Q_PAD_EIM_CS0__IPU1_DI1_PIN5 (_MX6Q_PAD_EIM_CS0__IPU1_DI1_PIN5) ++#define MX6Q_PAD_EIM_CS0__ECSPI2_SCLK (_MX6Q_PAD_EIM_CS0__ECSPI2_SCLK) ++#define MX6Q_PAD_EIM_CS0__MIPI_CORE_DPHY_TEST_OUT_24 (_MX6Q_PAD_EIM_CS0__MIPI_CORE_DPHY_TEST_OUT_24) ++#define MX6Q_PAD_EIM_CS0__GPIO_2_23 (_MX6Q_PAD_EIM_CS0__GPIO_2_23) ++#define MX6Q_PAD_EIM_CS0__TPSMP_HDATA_7 (_MX6Q_PAD_EIM_CS0__TPSMP_HDATA_7) ++ ++#define MX6Q_PAD_EIM_CS1__WEIM_WEIM_CS_1 (_MX6Q_PAD_EIM_CS1__WEIM_WEIM_CS_1) ++#define MX6Q_PAD_EIM_CS1__IPU1_DI1_PIN6 (_MX6Q_PAD_EIM_CS1__IPU1_DI1_PIN6) ++#define MX6Q_PAD_EIM_CS1__ECSPI2_MOSI (_MX6Q_PAD_EIM_CS1__ECSPI2_MOSI) ++#define MX6Q_PAD_EIM_CS1__MIPI_CORE_DPHY_TEST_OUT_25 (_MX6Q_PAD_EIM_CS1__MIPI_CORE_DPHY_TEST_OUT_25) ++#define MX6Q_PAD_EIM_CS1__GPIO_2_24 (_MX6Q_PAD_EIM_CS1__GPIO_2_24) ++#define MX6Q_PAD_EIM_CS1__TPSMP_HDATA_8 (_MX6Q_PAD_EIM_CS1__TPSMP_HDATA_8) ++ ++#define MX6Q_PAD_EIM_OE__WEIM_WEIM_OE (_MX6Q_PAD_EIM_OE__WEIM_WEIM_OE) ++#define MX6Q_PAD_EIM_OE__IPU1_DI1_PIN7 (_MX6Q_PAD_EIM_OE__IPU1_DI1_PIN7) ++#define MX6Q_PAD_EIM_OE__ECSPI2_MISO (_MX6Q_PAD_EIM_OE__ECSPI2_MISO) ++#define MX6Q_PAD_EIM_OE__MIPI_CORE_DPHY_TEST_OUT_26 (_MX6Q_PAD_EIM_OE__MIPI_CORE_DPHY_TEST_OUT_26) ++#define MX6Q_PAD_EIM_OE__GPIO_2_25 (_MX6Q_PAD_EIM_OE__GPIO_2_25) ++#define MX6Q_PAD_EIM_OE__TPSMP_HDATA_9 (_MX6Q_PAD_EIM_OE__TPSMP_HDATA_9) ++ ++#define MX6Q_PAD_EIM_RW__WEIM_WEIM_RW (_MX6Q_PAD_EIM_RW__WEIM_WEIM_RW) ++#define MX6Q_PAD_EIM_RW__IPU1_DI1_PIN8 (_MX6Q_PAD_EIM_RW__IPU1_DI1_PIN8) ++#define MX6Q_PAD_EIM_RW__ECSPI2_SS0 (_MX6Q_PAD_EIM_RW__ECSPI2_SS0) ++#define MX6Q_PAD_EIM_RW__MIPI_CORE_DPHY_TEST_OUT_27 (_MX6Q_PAD_EIM_RW__MIPI_CORE_DPHY_TEST_OUT_27) ++#define MX6Q_PAD_EIM_RW__GPIO_2_26 (_MX6Q_PAD_EIM_RW__GPIO_2_26) ++#define MX6Q_PAD_EIM_RW__TPSMP_HDATA_10 (_MX6Q_PAD_EIM_RW__TPSMP_HDATA_10) ++#define MX6Q_PAD_EIM_RW__SRC_BT_CFG_29 (_MX6Q_PAD_EIM_RW__SRC_BT_CFG_29) ++ ++#define MX6Q_PAD_EIM_LBA__WEIM_WEIM_LBA (_MX6Q_PAD_EIM_LBA__WEIM_WEIM_LBA) ++#define MX6Q_PAD_EIM_LBA__IPU1_DI1_PIN17 (_MX6Q_PAD_EIM_LBA__IPU1_DI1_PIN17) ++#define MX6Q_PAD_EIM_LBA__ECSPI2_SS1 (_MX6Q_PAD_EIM_LBA__ECSPI2_SS1) ++#define MX6Q_PAD_EIM_LBA__GPIO_2_27 (_MX6Q_PAD_EIM_LBA__GPIO_2_27) ++#define MX6Q_PAD_EIM_LBA__TPSMP_HDATA_11 (_MX6Q_PAD_EIM_LBA__TPSMP_HDATA_11) ++#define MX6Q_PAD_EIM_LBA__SRC_BT_CFG_26 (_MX6Q_PAD_EIM_LBA__SRC_BT_CFG_26) ++ ++#define MX6Q_PAD_EIM_EB0__WEIM_WEIM_EB_0 (_MX6Q_PAD_EIM_EB0__WEIM_WEIM_EB_0) ++#define MX6Q_PAD_EIM_EB0__IPU1_DISP1_DAT_11 (_MX6Q_PAD_EIM_EB0__IPU1_DISP1_DAT_11) ++#define MX6Q_PAD_EIM_EB0__IPU2_CSI1_D_11 (_MX6Q_PAD_EIM_EB0__IPU2_CSI1_D_11) ++#define MX6Q_PAD_EIM_EB0__MIPI_CORE_DPHY_TEST_OUT_0 (_MX6Q_PAD_EIM_EB0__MIPI_CORE_DPHY_TEST_OUT_0) ++#define MX6Q_PAD_EIM_EB0__CCM_PMIC_RDY (_MX6Q_PAD_EIM_EB0__CCM_PMIC_RDY) ++#define MX6Q_PAD_EIM_EB0__GPIO_2_28 (_MX6Q_PAD_EIM_EB0__GPIO_2_28) ++#define MX6Q_PAD_EIM_EB0__TPSMP_HDATA_12 (_MX6Q_PAD_EIM_EB0__TPSMP_HDATA_12) ++#define MX6Q_PAD_EIM_EB0__SRC_BT_CFG_27 (_MX6Q_PAD_EIM_EB0__SRC_BT_CFG_27) ++ ++#define MX6Q_PAD_EIM_EB1__WEIM_WEIM_EB_1 (_MX6Q_PAD_EIM_EB1__WEIM_WEIM_EB_1) ++#define MX6Q_PAD_EIM_EB1__IPU1_DISP1_DAT_10 (_MX6Q_PAD_EIM_EB1__IPU1_DISP1_DAT_10) ++#define MX6Q_PAD_EIM_EB1__IPU2_CSI1_D_10 (_MX6Q_PAD_EIM_EB1__IPU2_CSI1_D_10) ++#define MX6Q_PAD_EIM_EB1__MIPI_CORE_DPHY_TEST_OUT_1 (_MX6Q_PAD_EIM_EB1__MIPI_CORE_DPHY_TEST_OUT_1) ++#define MX6Q_PAD_EIM_EB1__GPIO_2_29 (_MX6Q_PAD_EIM_EB1__GPIO_2_29) ++#define MX6Q_PAD_EIM_EB1__TPSMP_HDATA_13 (_MX6Q_PAD_EIM_EB1__TPSMP_HDATA_13) ++#define MX6Q_PAD_EIM_EB1__SRC_BT_CFG_28 (_MX6Q_PAD_EIM_EB1__SRC_BT_CFG_28) ++ ++#define MX6Q_PAD_EIM_DA0__WEIM_WEIM_DA_A_0 (_MX6Q_PAD_EIM_DA0__WEIM_WEIM_DA_A_0) ++#define MX6Q_PAD_EIM_DA0__IPU1_DISP1_DAT_9 (_MX6Q_PAD_EIM_DA0__IPU1_DISP1_DAT_9) ++#define MX6Q_PAD_EIM_DA0__IPU2_CSI1_D_9 (_MX6Q_PAD_EIM_DA0__IPU2_CSI1_D_9) ++#define MX6Q_PAD_EIM_DA0__MIPI_CORE_DPHY_TEST_OUT_2 (_MX6Q_PAD_EIM_DA0__MIPI_CORE_DPHY_TEST_OUT_2) ++#define MX6Q_PAD_EIM_DA0__GPIO_3_0 (_MX6Q_PAD_EIM_DA0__GPIO_3_0) ++#define MX6Q_PAD_EIM_DA0__TPSMP_HDATA_14 (_MX6Q_PAD_EIM_DA0__TPSMP_HDATA_14) ++#define MX6Q_PAD_EIM_DA0__SRC_BT_CFG_0 (_MX6Q_PAD_EIM_DA0__SRC_BT_CFG_0) ++ ++#define MX6Q_PAD_EIM_DA1__WEIM_WEIM_DA_A_1 (_MX6Q_PAD_EIM_DA1__WEIM_WEIM_DA_A_1) ++#define MX6Q_PAD_EIM_DA1__IPU1_DISP1_DAT_8 (_MX6Q_PAD_EIM_DA1__IPU1_DISP1_DAT_8) ++#define MX6Q_PAD_EIM_DA1__IPU2_CSI1_D_8 (_MX6Q_PAD_EIM_DA1__IPU2_CSI1_D_8) ++#define MX6Q_PAD_EIM_DA1__MIPI_CORE_DPHY_TEST_OUT_3 (_MX6Q_PAD_EIM_DA1__MIPI_CORE_DPHY_TEST_OUT_3) ++#define MX6Q_PAD_EIM_DA1__ANATOP_USBPHY1_TSTI_TX_LS_MODE (_MX6Q_PAD_EIM_DA1__ANATOP_USBPHY1_TSTI_TX_LS_MODE) ++#define MX6Q_PAD_EIM_DA1__GPIO_3_1 (_MX6Q_PAD_EIM_DA1__GPIO_3_1) ++#define MX6Q_PAD_EIM_DA1__TPSMP_HDATA_15 (_MX6Q_PAD_EIM_DA1__TPSMP_HDATA_15) ++#define MX6Q_PAD_EIM_DA1__SRC_BT_CFG_1 (_MX6Q_PAD_EIM_DA1__SRC_BT_CFG_1) ++ ++#define MX6Q_PAD_EIM_DA2__WEIM_WEIM_DA_A_2 (_MX6Q_PAD_EIM_DA2__WEIM_WEIM_DA_A_2) ++#define MX6Q_PAD_EIM_DA2__IPU1_DISP1_DAT_7 (_MX6Q_PAD_EIM_DA2__IPU1_DISP1_DAT_7) ++#define MX6Q_PAD_EIM_DA2__IPU2_CSI1_D_7 (_MX6Q_PAD_EIM_DA2__IPU2_CSI1_D_7) ++#define MX6Q_PAD_EIM_DA2__MIPI_CORE_DPHY_TEST_OUT_4 (_MX6Q_PAD_EIM_DA2__MIPI_CORE_DPHY_TEST_OUT_4) ++#define MX6Q_PAD_EIM_DA2__ANATOP_USBPHY1_TSTI_TX_HS_MODE (_MX6Q_PAD_EIM_DA2__ANATOP_USBPHY1_TSTI_TX_HS_MODE) ++#define MX6Q_PAD_EIM_DA2__GPIO_3_2 (_MX6Q_PAD_EIM_DA2__GPIO_3_2) ++#define MX6Q_PAD_EIM_DA2__TPSMP_HDATA_16 (_MX6Q_PAD_EIM_DA2__TPSMP_HDATA_16) ++#define MX6Q_PAD_EIM_DA2__SRC_BT_CFG_2 (_MX6Q_PAD_EIM_DA2__SRC_BT_CFG_2) ++ ++#define MX6Q_PAD_EIM_DA3__WEIM_WEIM_DA_A_3 (_MX6Q_PAD_EIM_DA3__WEIM_WEIM_DA_A_3) ++#define MX6Q_PAD_EIM_DA3__IPU1_DISP1_DAT_6 (_MX6Q_PAD_EIM_DA3__IPU1_DISP1_DAT_6) ++#define MX6Q_PAD_EIM_DA3__IPU2_CSI1_D_6 (_MX6Q_PAD_EIM_DA3__IPU2_CSI1_D_6) ++#define MX6Q_PAD_EIM_DA3__MIPI_CORE_DPHY_TEST_OUT_5 (_MX6Q_PAD_EIM_DA3__MIPI_CORE_DPHY_TEST_OUT_5) ++#define MX6Q_PAD_EIM_DA3__ANATOP_USBPHY1_TSTI_TX_HIZ (_MX6Q_PAD_EIM_DA3__ANATOP_USBPHY1_TSTI_TX_HIZ) ++#define MX6Q_PAD_EIM_DA3__GPIO_3_3 (_MX6Q_PAD_EIM_DA3__GPIO_3_3) ++#define MX6Q_PAD_EIM_DA3__TPSMP_HDATA_17 (_MX6Q_PAD_EIM_DA3__TPSMP_HDATA_17) ++#define MX6Q_PAD_EIM_DA3__SRC_BT_CFG_3 (_MX6Q_PAD_EIM_DA3__SRC_BT_CFG_3) ++ ++#define MX6Q_PAD_EIM_DA4__WEIM_WEIM_DA_A_4 (_MX6Q_PAD_EIM_DA4__WEIM_WEIM_DA_A_4) ++#define MX6Q_PAD_EIM_DA4__IPU1_DISP1_DAT_5 (_MX6Q_PAD_EIM_DA4__IPU1_DISP1_DAT_5) ++#define MX6Q_PAD_EIM_DA4__IPU2_CSI1_D_5 (_MX6Q_PAD_EIM_DA4__IPU2_CSI1_D_5) ++#define MX6Q_PAD_EIM_DA4__MIPI_CORE_DPHY_TEST_OUT_6 (_MX6Q_PAD_EIM_DA4__MIPI_CORE_DPHY_TEST_OUT_6) ++#define MX6Q_PAD_EIM_DA4__ANATOP_USBPHY1_TSTI_TX_EN (_MX6Q_PAD_EIM_DA4__ANATOP_USBPHY1_TSTI_TX_EN) ++#define MX6Q_PAD_EIM_DA4__GPIO_3_4 (_MX6Q_PAD_EIM_DA4__GPIO_3_4) ++#define MX6Q_PAD_EIM_DA4__TPSMP_HDATA_18 (_MX6Q_PAD_EIM_DA4__TPSMP_HDATA_18) ++#define MX6Q_PAD_EIM_DA4__SRC_BT_CFG_4 (_MX6Q_PAD_EIM_DA4__SRC_BT_CFG_4) ++ ++#define MX6Q_PAD_EIM_DA5__WEIM_WEIM_DA_A_5 (_MX6Q_PAD_EIM_DA5__WEIM_WEIM_DA_A_5) ++#define MX6Q_PAD_EIM_DA5__IPU1_DISP1_DAT_4 (_MX6Q_PAD_EIM_DA5__IPU1_DISP1_DAT_4) ++#define MX6Q_PAD_EIM_DA5__IPU2_CSI1_D_4 (_MX6Q_PAD_EIM_DA5__IPU2_CSI1_D_4) ++#define MX6Q_PAD_EIM_DA5__MIPI_CORE_DPHY_TEST_OUT_7 (_MX6Q_PAD_EIM_DA5__MIPI_CORE_DPHY_TEST_OUT_7) ++#define MX6Q_PAD_EIM_DA5__ANATOP_USBPHY1_TSTI_TX_DP (_MX6Q_PAD_EIM_DA5__ANATOP_USBPHY1_TSTI_TX_DP) ++#define MX6Q_PAD_EIM_DA5__GPIO_3_5 (_MX6Q_PAD_EIM_DA5__GPIO_3_5) ++#define MX6Q_PAD_EIM_DA5__TPSMP_HDATA_19 (_MX6Q_PAD_EIM_DA5__TPSMP_HDATA_19) ++#define MX6Q_PAD_EIM_DA5__SRC_BT_CFG_5 (_MX6Q_PAD_EIM_DA5__SRC_BT_CFG_5) ++ ++#define MX6Q_PAD_EIM_DA6__WEIM_WEIM_DA_A_6 (_MX6Q_PAD_EIM_DA6__WEIM_WEIM_DA_A_6) ++#define MX6Q_PAD_EIM_DA6__IPU1_DISP1_DAT_3 (_MX6Q_PAD_EIM_DA6__IPU1_DISP1_DAT_3) ++#define MX6Q_PAD_EIM_DA6__IPU2_CSI1_D_3 (_MX6Q_PAD_EIM_DA6__IPU2_CSI1_D_3) ++#define MX6Q_PAD_EIM_DA6__MIPI_CORE_DPHY_TEST_OUT_8 (_MX6Q_PAD_EIM_DA6__MIPI_CORE_DPHY_TEST_OUT_8) ++#define MX6Q_PAD_EIM_DA6__ANATOP_USBPHY1_TSTI_TX_DN (_MX6Q_PAD_EIM_DA6__ANATOP_USBPHY1_TSTI_TX_DN) ++#define MX6Q_PAD_EIM_DA6__GPIO_3_6 (_MX6Q_PAD_EIM_DA6__GPIO_3_6) ++#define MX6Q_PAD_EIM_DA6__TPSMP_HDATA_20 (_MX6Q_PAD_EIM_DA6__TPSMP_HDATA_20) ++#define MX6Q_PAD_EIM_DA6__SRC_BT_CFG_6 (_MX6Q_PAD_EIM_DA6__SRC_BT_CFG_6) ++ ++#define MX6Q_PAD_EIM_DA7__WEIM_WEIM_DA_A_7 (_MX6Q_PAD_EIM_DA7__WEIM_WEIM_DA_A_7) ++#define MX6Q_PAD_EIM_DA7__IPU1_DISP1_DAT_2 (_MX6Q_PAD_EIM_DA7__IPU1_DISP1_DAT_2) ++#define MX6Q_PAD_EIM_DA7__IPU2_CSI1_D_2 (_MX6Q_PAD_EIM_DA7__IPU2_CSI1_D_2) ++#define MX6Q_PAD_EIM_DA7__MIPI_CORE_DPHY_TEST_OUT_9 (_MX6Q_PAD_EIM_DA7__MIPI_CORE_DPHY_TEST_OUT_9) ++#define MX6Q_PAD_EIM_DA7__GPIO_3_7 (_MX6Q_PAD_EIM_DA7__GPIO_3_7) ++#define MX6Q_PAD_EIM_DA7__TPSMP_HDATA_21 (_MX6Q_PAD_EIM_DA7__TPSMP_HDATA_21) ++#define MX6Q_PAD_EIM_DA7__SRC_BT_CFG_7 (_MX6Q_PAD_EIM_DA7__SRC_BT_CFG_7) ++ ++#define MX6Q_PAD_EIM_DA8__WEIM_WEIM_DA_A_8 (_MX6Q_PAD_EIM_DA8__WEIM_WEIM_DA_A_8) ++#define MX6Q_PAD_EIM_DA8__IPU1_DISP1_DAT_1 (_MX6Q_PAD_EIM_DA8__IPU1_DISP1_DAT_1) ++#define MX6Q_PAD_EIM_DA8__IPU2_CSI1_D_1 (_MX6Q_PAD_EIM_DA8__IPU2_CSI1_D_1) ++#define MX6Q_PAD_EIM_DA8__MIPI_CORE_DPHY_TEST_OUT_10 (_MX6Q_PAD_EIM_DA8__MIPI_CORE_DPHY_TEST_OUT_10) ++#define MX6Q_PAD_EIM_DA8__GPIO_3_8 (_MX6Q_PAD_EIM_DA8__GPIO_3_8) ++#define MX6Q_PAD_EIM_DA8__TPSMP_HDATA_22 (_MX6Q_PAD_EIM_DA8__TPSMP_HDATA_22) ++#define MX6Q_PAD_EIM_DA8__SRC_BT_CFG_8 (_MX6Q_PAD_EIM_DA8__SRC_BT_CFG_8) ++ ++#define MX6Q_PAD_EIM_DA9__WEIM_WEIM_DA_A_9 (_MX6Q_PAD_EIM_DA9__WEIM_WEIM_DA_A_9) ++#define MX6Q_PAD_EIM_DA9__IPU1_DISP1_DAT_0 (_MX6Q_PAD_EIM_DA9__IPU1_DISP1_DAT_0) ++#define MX6Q_PAD_EIM_DA9__IPU2_CSI1_D_0 (_MX6Q_PAD_EIM_DA9__IPU2_CSI1_D_0) ++#define MX6Q_PAD_EIM_DA9__MIPI_CORE_DPHY_TEST_OUT_11 (_MX6Q_PAD_EIM_DA9__MIPI_CORE_DPHY_TEST_OUT_11) ++#define MX6Q_PAD_EIM_DA9__GPIO_3_9 (_MX6Q_PAD_EIM_DA9__GPIO_3_9) ++#define MX6Q_PAD_EIM_DA9__TPSMP_HDATA_23 (_MX6Q_PAD_EIM_DA9__TPSMP_HDATA_23) ++#define MX6Q_PAD_EIM_DA9__SRC_BT_CFG_9 (_MX6Q_PAD_EIM_DA9__SRC_BT_CFG_9) ++ ++#define MX6Q_PAD_EIM_DA10__WEIM_WEIM_DA_A_10 (_MX6Q_PAD_EIM_DA10__WEIM_WEIM_DA_A_10) ++#define MX6Q_PAD_EIM_DA10__IPU1_DI1_PIN15 (_MX6Q_PAD_EIM_DA10__IPU1_DI1_PIN15) ++#define MX6Q_PAD_EIM_DA10__IPU2_CSI1_DATA_EN (_MX6Q_PAD_EIM_DA10__IPU2_CSI1_DATA_EN) ++#define MX6Q_PAD_EIM_DA10__MIPI_CORE_DPHY_TEST_OUT_12 (_MX6Q_PAD_EIM_DA10__MIPI_CORE_DPHY_TEST_OUT_12) ++#define MX6Q_PAD_EIM_DA10__GPIO_3_10 (_MX6Q_PAD_EIM_DA10__GPIO_3_10) ++#define MX6Q_PAD_EIM_DA10__TPSMP_HDATA_24 (_MX6Q_PAD_EIM_DA10__TPSMP_HDATA_24) ++#define MX6Q_PAD_EIM_DA10__SRC_BT_CFG_10 (_MX6Q_PAD_EIM_DA10__SRC_BT_CFG_10) ++ ++#define MX6Q_PAD_EIM_DA11__WEIM_WEIM_DA_A_11 (_MX6Q_PAD_EIM_DA11__WEIM_WEIM_DA_A_11) ++#define MX6Q_PAD_EIM_DA11__IPU1_DI1_PIN2 (_MX6Q_PAD_EIM_DA11__IPU1_DI1_PIN2) ++#define MX6Q_PAD_EIM_DA11__IPU2_CSI1_HSYNC (_MX6Q_PAD_EIM_DA11__IPU2_CSI1_HSYNC) ++#define MX6Q_PAD_EIM_DA11__MIPI_CORE_DPHY_TEST_OUT_13 (_MX6Q_PAD_EIM_DA11__MIPI_CORE_DPHY_TEST_OUT_13) ++#define MX6Q_PAD_EIM_DA11__SDMA_DEBUG_EVT_CHN_LINES_6 (_MX6Q_PAD_EIM_DA11__SDMA_DEBUG_EVT_CHN_LINES_6) ++#define MX6Q_PAD_EIM_DA11__GPIO_3_11 (_MX6Q_PAD_EIM_DA11__GPIO_3_11) ++#define MX6Q_PAD_EIM_DA11__TPSMP_HDATA_25 (_MX6Q_PAD_EIM_DA11__TPSMP_HDATA_25) ++#define MX6Q_PAD_EIM_DA11__SRC_BT_CFG_11 (_MX6Q_PAD_EIM_DA11__SRC_BT_CFG_11) ++ ++#define MX6Q_PAD_EIM_DA12__WEIM_WEIM_DA_A_12 (_MX6Q_PAD_EIM_DA12__WEIM_WEIM_DA_A_12) ++#define MX6Q_PAD_EIM_DA12__IPU1_DI1_PIN3 (_MX6Q_PAD_EIM_DA12__IPU1_DI1_PIN3) ++#define MX6Q_PAD_EIM_DA12__IPU2_CSI1_VSYNC (_MX6Q_PAD_EIM_DA12__IPU2_CSI1_VSYNC) ++#define MX6Q_PAD_EIM_DA12__MIPI_CORE_DPHY_TEST_OUT_14 (_MX6Q_PAD_EIM_DA12__MIPI_CORE_DPHY_TEST_OUT_14) ++#define MX6Q_PAD_EIM_DA12__SDMA_DEBUG_EVT_CHN_LINES_3 (_MX6Q_PAD_EIM_DA12__SDMA_DEBUG_EVT_CHN_LINES_3) ++#define MX6Q_PAD_EIM_DA12__GPIO_3_12 (_MX6Q_PAD_EIM_DA12__GPIO_3_12) ++#define MX6Q_PAD_EIM_DA12__TPSMP_HDATA_26 (_MX6Q_PAD_EIM_DA12__TPSMP_HDATA_26) ++#define MX6Q_PAD_EIM_DA12__SRC_BT_CFG_12 (_MX6Q_PAD_EIM_DA12__SRC_BT_CFG_12) ++ ++#define MX6Q_PAD_EIM_DA13__WEIM_WEIM_DA_A_13 (_MX6Q_PAD_EIM_DA13__WEIM_WEIM_DA_A_13) ++#define MX6Q_PAD_EIM_DA13__IPU1_DI1_D0_CS (_MX6Q_PAD_EIM_DA13__IPU1_DI1_D0_CS) ++#define MX6Q_PAD_EIM_DA13__CCM_DI1_EXT_CLK (_MX6Q_PAD_EIM_DA13__CCM_DI1_EXT_CLK) ++#define MX6Q_PAD_EIM_DA13__MIPI_CORE_DPHY_TEST_OUT_15 (_MX6Q_PAD_EIM_DA13__MIPI_CORE_DPHY_TEST_OUT_15) ++#define MX6Q_PAD_EIM_DA13__SDMA_DEBUG_EVT_CHN_LINES_4 (_MX6Q_PAD_EIM_DA13__SDMA_DEBUG_EVT_CHN_LINES_4) ++#define MX6Q_PAD_EIM_DA13__GPIO_3_13 (_MX6Q_PAD_EIM_DA13__GPIO_3_13) ++#define MX6Q_PAD_EIM_DA13__TPSMP_HDATA_27 (_MX6Q_PAD_EIM_DA13__TPSMP_HDATA_27) ++#define MX6Q_PAD_EIM_DA13__SRC_BT_CFG_13 (_MX6Q_PAD_EIM_DA13__SRC_BT_CFG_13) ++ ++#define MX6Q_PAD_EIM_DA14__WEIM_WEIM_DA_A_14 (_MX6Q_PAD_EIM_DA14__WEIM_WEIM_DA_A_14) ++#define MX6Q_PAD_EIM_DA14__IPU1_DI1_D1_CS (_MX6Q_PAD_EIM_DA14__IPU1_DI1_D1_CS) ++#define MX6Q_PAD_EIM_DA14__CCM_DI0_EXT_CLK (_MX6Q_PAD_EIM_DA14__CCM_DI0_EXT_CLK) ++#define MX6Q_PAD_EIM_DA14__MIPI_CORE_DPHY_TEST_OUT_16 (_MX6Q_PAD_EIM_DA14__MIPI_CORE_DPHY_TEST_OUT_16) ++#define MX6Q_PAD_EIM_DA14__SDMA_DEBUG_EVT_CHN_LINES_5 (_MX6Q_PAD_EIM_DA14__SDMA_DEBUG_EVT_CHN_LINES_5) ++#define MX6Q_PAD_EIM_DA14__GPIO_3_14 (_MX6Q_PAD_EIM_DA14__GPIO_3_14) ++#define MX6Q_PAD_EIM_DA14__TPSMP_HDATA_28 (_MX6Q_PAD_EIM_DA14__TPSMP_HDATA_28) ++#define MX6Q_PAD_EIM_DA14__SRC_BT_CFG_14 (_MX6Q_PAD_EIM_DA14__SRC_BT_CFG_14) ++ ++#define MX6Q_PAD_EIM_DA15__WEIM_WEIM_DA_A_15 (_MX6Q_PAD_EIM_DA15__WEIM_WEIM_DA_A_15) ++#define MX6Q_PAD_EIM_DA15__IPU1_DI1_PIN1 (_MX6Q_PAD_EIM_DA15__IPU1_DI1_PIN1) ++#define MX6Q_PAD_EIM_DA15__IPU1_DI1_PIN4 (_MX6Q_PAD_EIM_DA15__IPU1_DI1_PIN4) ++#define MX6Q_PAD_EIM_DA15__MIPI_CORE_DPHY_TEST_OUT_17 (_MX6Q_PAD_EIM_DA15__MIPI_CORE_DPHY_TEST_OUT_17) ++#define MX6Q_PAD_EIM_DA15__GPIO_3_15 (_MX6Q_PAD_EIM_DA15__GPIO_3_15) ++#define MX6Q_PAD_EIM_DA15__TPSMP_HDATA_29 (_MX6Q_PAD_EIM_DA15__TPSMP_HDATA_29) ++#define MX6Q_PAD_EIM_DA15__SRC_BT_CFG_15 (_MX6Q_PAD_EIM_DA15__SRC_BT_CFG_15) ++ ++#define MX6Q_PAD_EIM_WAIT__WEIM_WEIM_WAIT (_MX6Q_PAD_EIM_WAIT__WEIM_WEIM_WAIT) ++#define MX6Q_PAD_EIM_WAIT__WEIM_WEIM_DTACK_B (_MX6Q_PAD_EIM_WAIT__WEIM_WEIM_DTACK_B) ++#define MX6Q_PAD_EIM_WAIT__GPIO_5_0 (_MX6Q_PAD_EIM_WAIT__GPIO_5_0) ++#define MX6Q_PAD_EIM_WAIT__TPSMP_HDATA_30 (_MX6Q_PAD_EIM_WAIT__TPSMP_HDATA_30) ++#define MX6Q_PAD_EIM_WAIT__SRC_BT_CFG_25 (_MX6Q_PAD_EIM_WAIT__SRC_BT_CFG_25) ++ ++#define MX6Q_PAD_EIM_BCLK__WEIM_WEIM_BCLK (_MX6Q_PAD_EIM_BCLK__WEIM_WEIM_BCLK) ++#define MX6Q_PAD_EIM_BCLK__IPU1_DI1_PIN16 (_MX6Q_PAD_EIM_BCLK__IPU1_DI1_PIN16) ++#define MX6Q_PAD_EIM_BCLK__GPIO_6_31 (_MX6Q_PAD_EIM_BCLK__GPIO_6_31) ++#define MX6Q_PAD_EIM_BCLK__TPSMP_HDATA_31 (_MX6Q_PAD_EIM_BCLK__TPSMP_HDATA_31) ++ ++#define MX6Q_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK (_MX6Q_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK) ++#define MX6Q_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK (_MX6Q_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK) ++#define MX6Q_PAD_DI0_DISP_CLK__MIPI_CORE_DPHY_TEST_OUT_28 (_MX6Q_PAD_DI0_DISP_CLK__MIPI_CORE_DPHY_TEST_OUT_28) ++#define MX6Q_PAD_DI0_DISP_CLK__SDMA_DEBUG_CORE_STATE_0 (_MX6Q_PAD_DI0_DISP_CLK__SDMA_DEBUG_CORE_STATE_0) ++#define MX6Q_PAD_DI0_DISP_CLK__GPIO_4_16 (_MX6Q_PAD_DI0_DISP_CLK__GPIO_4_16) ++#define MX6Q_PAD_DI0_DISP_CLK__MMDC_MMDC_DEBUG_0 (_MX6Q_PAD_DI0_DISP_CLK__MMDC_MMDC_DEBUG_0) ++ ++#define MX6Q_PAD_DI0_PIN15__IPU1_DI0_PIN15 (_MX6Q_PAD_DI0_PIN15__IPU1_DI0_PIN15) ++#define MX6Q_PAD_DI0_PIN15__IPU2_DI0_PIN15 (_MX6Q_PAD_DI0_PIN15__IPU2_DI0_PIN15) ++#define MX6Q_PAD_DI0_PIN15__AUDMUX_AUD6_TXC (_MX6Q_PAD_DI0_PIN15__AUDMUX_AUD6_TXC) ++#define MX6Q_PAD_DI0_PIN15__MIPI_CORE_DPHY_TEST_OUT_29 (_MX6Q_PAD_DI0_PIN15__MIPI_CORE_DPHY_TEST_OUT_29) ++#define MX6Q_PAD_DI0_PIN15__SDMA_DEBUG_CORE_STATE_1 (_MX6Q_PAD_DI0_PIN15__SDMA_DEBUG_CORE_STATE_1) ++#define MX6Q_PAD_DI0_PIN15__GPIO_4_17 (_MX6Q_PAD_DI0_PIN15__GPIO_4_17) ++#define MX6Q_PAD_DI0_PIN15__MMDC_MMDC_DEBUG_1 (_MX6Q_PAD_DI0_PIN15__MMDC_MMDC_DEBUG_1) ++ ++#define MX6Q_PAD_DI0_PIN2__IPU1_DI0_PIN2 (_MX6Q_PAD_DI0_PIN2__IPU1_DI0_PIN2) ++#define MX6Q_PAD_DI0_PIN2__IPU2_DI0_PIN2 (_MX6Q_PAD_DI0_PIN2__IPU2_DI0_PIN2) ++#define MX6Q_PAD_DI0_PIN2__AUDMUX_AUD6_TXD (_MX6Q_PAD_DI0_PIN2__AUDMUX_AUD6_TXD) ++#define MX6Q_PAD_DI0_PIN2__MIPI_CORE_DPHY_TEST_OUT_30 (_MX6Q_PAD_DI0_PIN2__MIPI_CORE_DPHY_TEST_OUT_30) ++#define MX6Q_PAD_DI0_PIN2__SDMA_DEBUG_CORE_STATE_2 (_MX6Q_PAD_DI0_PIN2__SDMA_DEBUG_CORE_STATE_2) ++#define MX6Q_PAD_DI0_PIN2__GPIO_4_18 (_MX6Q_PAD_DI0_PIN2__GPIO_4_18) ++#define MX6Q_PAD_DI0_PIN2__MMDC_MMDC_DEBUG_2 (_MX6Q_PAD_DI0_PIN2__MMDC_MMDC_DEBUG_2) ++#define MX6Q_PAD_DI0_PIN2__PL301_MX6QPER1_HADDR_9 (_MX6Q_PAD_DI0_PIN2__PL301_MX6QPER1_HADDR_9) ++ ++#define MX6Q_PAD_DI0_PIN3__IPU1_DI0_PIN3 (_MX6Q_PAD_DI0_PIN3__IPU1_DI0_PIN3) ++#define MX6Q_PAD_DI0_PIN3__IPU2_DI0_PIN3 (_MX6Q_PAD_DI0_PIN3__IPU2_DI0_PIN3) ++#define MX6Q_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS (_MX6Q_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS) ++#define MX6Q_PAD_DI0_PIN3__MIPI_CORE_DPHY_TEST_OUT_31 (_MX6Q_PAD_DI0_PIN3__MIPI_CORE_DPHY_TEST_OUT_31) ++#define MX6Q_PAD_DI0_PIN3__SDMA_DEBUG_CORE_STATE_3 (_MX6Q_PAD_DI0_PIN3__SDMA_DEBUG_CORE_STATE_3) ++#define MX6Q_PAD_DI0_PIN3__GPIO_4_19 (_MX6Q_PAD_DI0_PIN3__GPIO_4_19) ++#define MX6Q_PAD_DI0_PIN3__MMDC_MMDC_DEBUG_3 (_MX6Q_PAD_DI0_PIN3__MMDC_MMDC_DEBUG_3) ++#define MX6Q_PAD_DI0_PIN3__PL301_MX6QPER1_HADDR_10 (_MX6Q_PAD_DI0_PIN3__PL301_MX6QPER1_HADDR_10) ++ ++#define MX6Q_PAD_DI0_PIN4__IPU1_DI0_PIN4 (_MX6Q_PAD_DI0_PIN4__IPU1_DI0_PIN4) ++#define MX6Q_PAD_DI0_PIN4__IPU2_DI0_PIN4 (_MX6Q_PAD_DI0_PIN4__IPU2_DI0_PIN4) ++#define MX6Q_PAD_DI0_PIN4__AUDMUX_AUD6_RXD (_MX6Q_PAD_DI0_PIN4__AUDMUX_AUD6_RXD) ++#define MX6Q_PAD_DI0_PIN4__USDHC1_WP (_MX6Q_PAD_DI0_PIN4__USDHC1_WP | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) ++#define MX6Q_PAD_DI0_PIN4__SDMA_DEBUG_YIELD (_MX6Q_PAD_DI0_PIN4__SDMA_DEBUG_YIELD) ++#define MX6Q_PAD_DI0_PIN4__GPIO_4_20 (_MX6Q_PAD_DI0_PIN4__GPIO_4_20) ++#define MX6Q_PAD_DI0_PIN4__MMDC_MMDC_DEBUG_4 (_MX6Q_PAD_DI0_PIN4__MMDC_MMDC_DEBUG_4) ++#define MX6Q_PAD_DI0_PIN4__PL301_MX6QPER1_HADDR_11 (_MX6Q_PAD_DI0_PIN4__PL301_MX6QPER1_HADDR_11) ++ ++#define MX6Q_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0 (_MX6Q_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0) ++#define MX6Q_PAD_DISP0_DAT0__IPU2_DISP0_DAT_0 (_MX6Q_PAD_DISP0_DAT0__IPU2_DISP0_DAT_0) ++#define MX6Q_PAD_DISP0_DAT0__ECSPI3_SCLK (_MX6Q_PAD_DISP0_DAT0__ECSPI3_SCLK) ++#define MX6Q_PAD_DISP0_DAT0__USDHC1_USDHC_DEBUG_0 (_MX6Q_PAD_DISP0_DAT0__USDHC1_USDHC_DEBUG_0 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) ++#define MX6Q_PAD_DISP0_DAT0__SDMA_DEBUG_CORE_RUN (_MX6Q_PAD_DISP0_DAT0__SDMA_DEBUG_CORE_RUN) ++#define MX6Q_PAD_DISP0_DAT0__GPIO_4_21 (_MX6Q_PAD_DISP0_DAT0__GPIO_4_21) ++#define MX6Q_PAD_DISP0_DAT0__MMDC_MMDC_DEBUG_5 (_MX6Q_PAD_DISP0_DAT0__MMDC_MMDC_DEBUG_5) ++ ++#define MX6Q_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1 (_MX6Q_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1) ++#define MX6Q_PAD_DISP0_DAT1__IPU2_DISP0_DAT_1 (_MX6Q_PAD_DISP0_DAT1__IPU2_DISP0_DAT_1) ++#define MX6Q_PAD_DISP0_DAT1__ECSPI3_MOSI (_MX6Q_PAD_DISP0_DAT1__ECSPI3_MOSI) ++#define MX6Q_PAD_DISP0_DAT1__USDHC1_USDHC_DEBUG_1 (_MX6Q_PAD_DISP0_DAT1__USDHC1_USDHC_DEBUG_1 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) ++#define MX6Q_PAD_DISP0_DAT1__SDMA_DEBUG_EVENT_CHANNEL_SEL (_MX6Q_PAD_DISP0_DAT1__SDMA_DEBUG_EVENT_CHANNEL_SEL) ++#define MX6Q_PAD_DISP0_DAT1__GPIO_4_22 (_MX6Q_PAD_DISP0_DAT1__GPIO_4_22) ++#define MX6Q_PAD_DISP0_DAT1__MMDC_MMDC_DEBUG_6 (_MX6Q_PAD_DISP0_DAT1__MMDC_MMDC_DEBUG_6) ++#define MX6Q_PAD_DISP0_DAT1__PL301_MX6QPER1_HADDR_12 (_MX6Q_PAD_DISP0_DAT1__PL301_MX6QPER1_HADDR_12) ++ ++#define MX6Q_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2 (_MX6Q_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2) ++#define MX6Q_PAD_DISP0_DAT2__IPU2_DISP0_DAT_2 (_MX6Q_PAD_DISP0_DAT2__IPU2_DISP0_DAT_2) ++#define MX6Q_PAD_DISP0_DAT2__ECSPI3_MISO (_MX6Q_PAD_DISP0_DAT2__ECSPI3_MISO) ++#define MX6Q_PAD_DISP0_DAT2__USDHC1_USDHC_DEBUG_2 (_MX6Q_PAD_DISP0_DAT2__USDHC1_USDHC_DEBUG_2 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) ++#define MX6Q_PAD_DISP0_DAT2__SDMA_DEBUG_MODE (_MX6Q_PAD_DISP0_DAT2__SDMA_DEBUG_MODE) ++#define MX6Q_PAD_DISP0_DAT2__GPIO_4_23 (_MX6Q_PAD_DISP0_DAT2__GPIO_4_23) ++#define MX6Q_PAD_DISP0_DAT2__MMDC_MMDC_DEBUG_7 (_MX6Q_PAD_DISP0_DAT2__MMDC_MMDC_DEBUG_7) ++#define MX6Q_PAD_DISP0_DAT2__PL301_MX6QPER1_HADDR_13 (_MX6Q_PAD_DISP0_DAT2__PL301_MX6QPER1_HADDR_13) ++ ++#define MX6Q_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3 (_MX6Q_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3) ++#define MX6Q_PAD_DISP0_DAT3__IPU2_DISP0_DAT_3 (_MX6Q_PAD_DISP0_DAT3__IPU2_DISP0_DAT_3) ++#define MX6Q_PAD_DISP0_DAT3__ECSPI3_SS0 (_MX6Q_PAD_DISP0_DAT3__ECSPI3_SS0) ++#define MX6Q_PAD_DISP0_DAT3__USDHC1_USDHC_DEBUG_3 (_MX6Q_PAD_DISP0_DAT3__USDHC1_USDHC_DEBUG_3 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) ++#define MX6Q_PAD_DISP0_DAT3__SDMA_DEBUG_BUS_ERROR (_MX6Q_PAD_DISP0_DAT3__SDMA_DEBUG_BUS_ERROR) ++#define MX6Q_PAD_DISP0_DAT3__GPIO_4_24 (_MX6Q_PAD_DISP0_DAT3__GPIO_4_24) ++#define MX6Q_PAD_DISP0_DAT3__MMDC_MMDC_DEBUG_8 (_MX6Q_PAD_DISP0_DAT3__MMDC_MMDC_DEBUG_8) ++#define MX6Q_PAD_DISP0_DAT3__PL301_MX6QPER1_HADDR_14 (_MX6Q_PAD_DISP0_DAT3__PL301_MX6QPER1_HADDR_14) ++ ++#define MX6Q_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4 (_MX6Q_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4) ++#define MX6Q_PAD_DISP0_DAT4__IPU2_DISP0_DAT_4 (_MX6Q_PAD_DISP0_DAT4__IPU2_DISP0_DAT_4) ++#define MX6Q_PAD_DISP0_DAT4__ECSPI3_SS1 (_MX6Q_PAD_DISP0_DAT4__ECSPI3_SS1) ++#define MX6Q_PAD_DISP0_DAT4__USDHC1_USDHC_DEBUG_4 (_MX6Q_PAD_DISP0_DAT4__USDHC1_USDHC_DEBUG_4 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) ++#define MX6Q_PAD_DISP0_DAT4__SDMA_DEBUG_BUS_RWB (_MX6Q_PAD_DISP0_DAT4__SDMA_DEBUG_BUS_RWB) ++#define MX6Q_PAD_DISP0_DAT4__GPIO_4_25 (_MX6Q_PAD_DISP0_DAT4__GPIO_4_25) ++#define MX6Q_PAD_DISP0_DAT4__MMDC_MMDC_DEBUG_9 (_MX6Q_PAD_DISP0_DAT4__MMDC_MMDC_DEBUG_9) ++#define MX6Q_PAD_DISP0_DAT4__PL301_MX6QPER1_HADDR_15 (_MX6Q_PAD_DISP0_DAT4__PL301_MX6QPER1_HADDR_15) ++ ++#define MX6Q_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5 (_MX6Q_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5) ++#define MX6Q_PAD_DISP0_DAT5__IPU2_DISP0_DAT_5 (_MX6Q_PAD_DISP0_DAT5__IPU2_DISP0_DAT_5) ++#define MX6Q_PAD_DISP0_DAT5__ECSPI3_SS2 (_MX6Q_PAD_DISP0_DAT5__ECSPI3_SS2) ++#define MX6Q_PAD_DISP0_DAT5__AUDMUX_AUD6_RXFS (_MX6Q_PAD_DISP0_DAT5__AUDMUX_AUD6_RXFS) ++#define MX6Q_PAD_DISP0_DAT5__SDMA_DEBUG_MATCHED_DMBUS (_MX6Q_PAD_DISP0_DAT5__SDMA_DEBUG_MATCHED_DMBUS) ++#define MX6Q_PAD_DISP0_DAT5__GPIO_4_26 (_MX6Q_PAD_DISP0_DAT5__GPIO_4_26) ++#define MX6Q_PAD_DISP0_DAT5__MMDC_MMDC_DEBUG_10 (_MX6Q_PAD_DISP0_DAT5__MMDC_MMDC_DEBUG_10) ++#define MX6Q_PAD_DISP0_DAT5__PL301_MX6QPER1_HADDR_16 (_MX6Q_PAD_DISP0_DAT5__PL301_MX6QPER1_HADDR_16) ++ ++#define MX6Q_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6 (_MX6Q_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6) ++#define MX6Q_PAD_DISP0_DAT6__IPU2_DISP0_DAT_6 (_MX6Q_PAD_DISP0_DAT6__IPU2_DISP0_DAT_6) ++#define MX6Q_PAD_DISP0_DAT6__ECSPI3_SS3 (_MX6Q_PAD_DISP0_DAT6__ECSPI3_SS3) ++#define MX6Q_PAD_DISP0_DAT6__AUDMUX_AUD6_RXC (_MX6Q_PAD_DISP0_DAT6__AUDMUX_AUD6_RXC) ++#define MX6Q_PAD_DISP0_DAT6__SDMA_DEBUG_RTBUFFER_WRITE (_MX6Q_PAD_DISP0_DAT6__SDMA_DEBUG_RTBUFFER_WRITE) ++#define MX6Q_PAD_DISP0_DAT6__GPIO_4_27 (_MX6Q_PAD_DISP0_DAT6__GPIO_4_27) ++#define MX6Q_PAD_DISP0_DAT6__MMDC_MMDC_DEBUG_11 (_MX6Q_PAD_DISP0_DAT6__MMDC_MMDC_DEBUG_11) ++#define MX6Q_PAD_DISP0_DAT6__PL301_MX6QPER1_HADDR_17 (_MX6Q_PAD_DISP0_DAT6__PL301_MX6QPER1_HADDR_17) ++ ++#define MX6Q_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7 (_MX6Q_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7) ++#define MX6Q_PAD_DISP0_DAT7__IPU2_DISP0_DAT_7 (_MX6Q_PAD_DISP0_DAT7__IPU2_DISP0_DAT_7) ++#define MX6Q_PAD_DISP0_DAT7__ECSPI3_RDY (_MX6Q_PAD_DISP0_DAT7__ECSPI3_RDY) ++#define MX6Q_PAD_DISP0_DAT7__USDHC1_USDHC_DEBUG_5 (_MX6Q_PAD_DISP0_DAT7__USDHC1_USDHC_DEBUG_5 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) ++#define MX6Q_PAD_DISP0_DAT7__SDMA_DEBUG_EVENT_CHANNEL_0 (_MX6Q_PAD_DISP0_DAT7__SDMA_DEBUG_EVENT_CHANNEL_0) ++#define MX6Q_PAD_DISP0_DAT7__GPIO_4_28 (_MX6Q_PAD_DISP0_DAT7__GPIO_4_28) ++#define MX6Q_PAD_DISP0_DAT7__MMDC_MMDC_DEBUG_12 (_MX6Q_PAD_DISP0_DAT7__MMDC_MMDC_DEBUG_12) ++#define MX6Q_PAD_DISP0_DAT7__PL301_MX6QPER1_HADDR_18 (_MX6Q_PAD_DISP0_DAT7__PL301_MX6QPER1_HADDR_18) ++ ++#define MX6Q_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8 (_MX6Q_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8) ++#define MX6Q_PAD_DISP0_DAT8__IPU2_DISP0_DAT_8 (_MX6Q_PAD_DISP0_DAT8__IPU2_DISP0_DAT_8) ++#define MX6Q_PAD_DISP0_DAT8__PWM1_PWMO (_MX6Q_PAD_DISP0_DAT8__PWM1_PWMO) ++#define MX6Q_PAD_DISP0_DAT8__WDOG1_WDOG_B (_MX6Q_PAD_DISP0_DAT8__WDOG1_WDOG_B) ++#define MX6Q_PAD_DISP0_DAT8__SDMA_DEBUG_EVENT_CHANNEL_1 (_MX6Q_PAD_DISP0_DAT8__SDMA_DEBUG_EVENT_CHANNEL_1) ++#define MX6Q_PAD_DISP0_DAT8__GPIO_4_29 (_MX6Q_PAD_DISP0_DAT8__GPIO_4_29) ++#define MX6Q_PAD_DISP0_DAT8__MMDC_MMDC_DEBUG_13 (_MX6Q_PAD_DISP0_DAT8__MMDC_MMDC_DEBUG_13) ++#define MX6Q_PAD_DISP0_DAT8__PL301_MX6QPER1_HADDR_19 (_MX6Q_PAD_DISP0_DAT8__PL301_MX6QPER1_HADDR_19) ++ ++#define MX6Q_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9 (_MX6Q_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9) ++#define MX6Q_PAD_DISP0_DAT9__IPU2_DISP0_DAT_9 (_MX6Q_PAD_DISP0_DAT9__IPU2_DISP0_DAT_9) ++#define MX6Q_PAD_DISP0_DAT9__PWM2_PWMO (_MX6Q_PAD_DISP0_DAT9__PWM2_PWMO) ++#define MX6Q_PAD_DISP0_DAT9__WDOG2_WDOG_B (_MX6Q_PAD_DISP0_DAT9__WDOG2_WDOG_B) ++#define MX6Q_PAD_DISP0_DAT9__SDMA_DEBUG_EVENT_CHANNEL_2 (_MX6Q_PAD_DISP0_DAT9__SDMA_DEBUG_EVENT_CHANNEL_2) ++#define MX6Q_PAD_DISP0_DAT9__GPIO_4_30 (_MX6Q_PAD_DISP0_DAT9__GPIO_4_30) ++#define MX6Q_PAD_DISP0_DAT9__MMDC_MMDC_DEBUG_14 (_MX6Q_PAD_DISP0_DAT9__MMDC_MMDC_DEBUG_14) ++#define MX6Q_PAD_DISP0_DAT9__PL301_MX6QPER1_HADDR_20 (_MX6Q_PAD_DISP0_DAT9__PL301_MX6QPER1_HADDR_20) ++ ++#define MX6Q_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10 (_MX6Q_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10) ++#define MX6Q_PAD_DISP0_DAT10__IPU2_DISP0_DAT_10 (_MX6Q_PAD_DISP0_DAT10__IPU2_DISP0_DAT_10) ++#define MX6Q_PAD_DISP0_DAT10__USDHC1_USDHC_DEBUG_6 (_MX6Q_PAD_DISP0_DAT10__USDHC1_USDHC_DEBUG_6 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) ++#define MX6Q_PAD_DISP0_DAT10__SDMA_DEBUG_EVENT_CHANNEL_3 (_MX6Q_PAD_DISP0_DAT10__SDMA_DEBUG_EVENT_CHANNEL_3) ++#define MX6Q_PAD_DISP0_DAT10__GPIO_4_31 (_MX6Q_PAD_DISP0_DAT10__GPIO_4_31) ++#define MX6Q_PAD_DISP0_DAT10__MMDC_MMDC_DEBUG_15 (_MX6Q_PAD_DISP0_DAT10__MMDC_MMDC_DEBUG_15) ++#define MX6Q_PAD_DISP0_DAT10__PL301_MX6QPER1_HADDR_21 (_MX6Q_PAD_DISP0_DAT10__PL301_MX6QPER1_HADDR_21) ++ ++#define MX6Q_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11 (_MX6Q_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11) ++#define MX6Q_PAD_DISP0_DAT11__IPU2_DISP0_DAT_11 (_MX6Q_PAD_DISP0_DAT11__IPU2_DISP0_DAT_11) ++#define MX6Q_PAD_DISP0_DAT11__USDHC1_USDHC_DEBUG_7 (_MX6Q_PAD_DISP0_DAT11__USDHC1_USDHC_DEBUG_7 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) ++#define MX6Q_PAD_DISP0_DAT11__SDMA_DEBUG_EVENT_CHANNEL_4 (_MX6Q_PAD_DISP0_DAT11__SDMA_DEBUG_EVENT_CHANNEL_4) ++#define MX6Q_PAD_DISP0_DAT11__GPIO_5_5 (_MX6Q_PAD_DISP0_DAT11__GPIO_5_5) ++#define MX6Q_PAD_DISP0_DAT11__MMDC_MMDC_DEBUG_16 (_MX6Q_PAD_DISP0_DAT11__MMDC_MMDC_DEBUG_16) ++#define MX6Q_PAD_DISP0_DAT11__PL301_MX6QPER1_HADDR_22 (_MX6Q_PAD_DISP0_DAT11__PL301_MX6QPER1_HADDR_22) ++ ++#define MX6Q_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12 (_MX6Q_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12) ++#define MX6Q_PAD_DISP0_DAT12__IPU2_DISP0_DAT_12 (_MX6Q_PAD_DISP0_DAT12__IPU2_DISP0_DAT_12) ++#define MX6Q_PAD_DISP0_DAT12__SDMA_DEBUG_EVENT_CHANNEL_5 (_MX6Q_PAD_DISP0_DAT12__SDMA_DEBUG_EVENT_CHANNEL_5) ++#define MX6Q_PAD_DISP0_DAT12__GPIO_5_6 (_MX6Q_PAD_DISP0_DAT12__GPIO_5_6) ++#define MX6Q_PAD_DISP0_DAT12__MMDC_MMDC_DEBUG_17 (_MX6Q_PAD_DISP0_DAT12__MMDC_MMDC_DEBUG_17) ++#define MX6Q_PAD_DISP0_DAT12__PL301_MX6QPER1_HADDR_23 (_MX6Q_PAD_DISP0_DAT12__PL301_MX6QPER1_HADDR_23) ++ ++#define MX6Q_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13 (_MX6Q_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13) ++#define MX6Q_PAD_DISP0_DAT13__IPU2_DISP0_DAT_13 (_MX6Q_PAD_DISP0_DAT13__IPU2_DISP0_DAT_13) ++#define MX6Q_PAD_DISP0_DAT13__AUDMUX_AUD5_RXFS (_MX6Q_PAD_DISP0_DAT13__AUDMUX_AUD5_RXFS) ++#define MX6Q_PAD_DISP0_DAT13__SDMA_DEBUG_EVT_CHN_LINES_0 (_MX6Q_PAD_DISP0_DAT13__SDMA_DEBUG_EVT_CHN_LINES_0) ++#define MX6Q_PAD_DISP0_DAT13__GPIO_5_7 (_MX6Q_PAD_DISP0_DAT13__GPIO_5_7) ++#define MX6Q_PAD_DISP0_DAT13__MMDC_MMDC_DEBUG_18 (_MX6Q_PAD_DISP0_DAT13__MMDC_MMDC_DEBUG_18) ++#define MX6Q_PAD_DISP0_DAT13__PL301_MX6QPER1_HADDR_24 (_MX6Q_PAD_DISP0_DAT13__PL301_MX6QPER1_HADDR_24) ++ ++#define MX6Q_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14 (_MX6Q_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14) ++#define MX6Q_PAD_DISP0_DAT14__IPU2_DISP0_DAT_14 (_MX6Q_PAD_DISP0_DAT14__IPU2_DISP0_DAT_14) ++#define MX6Q_PAD_DISP0_DAT14__AUDMUX_AUD5_RXC (_MX6Q_PAD_DISP0_DAT14__AUDMUX_AUD5_RXC) ++#define MX6Q_PAD_DISP0_DAT14__SDMA_DEBUG_EVT_CHN_LINES_1 (_MX6Q_PAD_DISP0_DAT14__SDMA_DEBUG_EVT_CHN_LINES_1) ++#define MX6Q_PAD_DISP0_DAT14__GPIO_5_8 (_MX6Q_PAD_DISP0_DAT14__GPIO_5_8) ++#define MX6Q_PAD_DISP0_DAT14__MMDC_MMDC_DEBUG_19 (_MX6Q_PAD_DISP0_DAT14__MMDC_MMDC_DEBUG_19) ++ ++#define MX6Q_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15 (_MX6Q_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15) ++#define MX6Q_PAD_DISP0_DAT15__IPU2_DISP0_DAT_15 (_MX6Q_PAD_DISP0_DAT15__IPU2_DISP0_DAT_15) ++#define MX6Q_PAD_DISP0_DAT15__ECSPI1_SS1 (_MX6Q_PAD_DISP0_DAT15__ECSPI1_SS1) ++#define MX6Q_PAD_DISP0_DAT15__ECSPI2_SS1 (_MX6Q_PAD_DISP0_DAT15__ECSPI2_SS1) ++#define MX6Q_PAD_DISP0_DAT15__SDMA_DEBUG_EVT_CHN_LINES_2 (_MX6Q_PAD_DISP0_DAT15__SDMA_DEBUG_EVT_CHN_LINES_2) ++#define MX6Q_PAD_DISP0_DAT15__GPIO_5_9 (_MX6Q_PAD_DISP0_DAT15__GPIO_5_9) ++#define MX6Q_PAD_DISP0_DAT15__MMDC_MMDC_DEBUG_20 (_MX6Q_PAD_DISP0_DAT15__MMDC_MMDC_DEBUG_20) ++#define MX6Q_PAD_DISP0_DAT15__PL301_MX6QPER1_HADDR_25 (_MX6Q_PAD_DISP0_DAT15__PL301_MX6QPER1_HADDR_25) ++ ++#define MX6Q_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16 (_MX6Q_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16) ++#define MX6Q_PAD_DISP0_DAT16__IPU2_DISP0_DAT_16 (_MX6Q_PAD_DISP0_DAT16__IPU2_DISP0_DAT_16) ++#define MX6Q_PAD_DISP0_DAT16__ECSPI2_MOSI (_MX6Q_PAD_DISP0_DAT16__ECSPI2_MOSI) ++#define MX6Q_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC (_MX6Q_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC) ++#define MX6Q_PAD_DISP0_DAT16__SDMA_SDMA_EXT_EVENT_0 (_MX6Q_PAD_DISP0_DAT16__SDMA_SDMA_EXT_EVENT_0) ++#define MX6Q_PAD_DISP0_DAT16__GPIO_5_10 (_MX6Q_PAD_DISP0_DAT16__GPIO_5_10) ++#define MX6Q_PAD_DISP0_DAT16__MMDC_MMDC_DEBUG_21 (_MX6Q_PAD_DISP0_DAT16__MMDC_MMDC_DEBUG_21) ++#define MX6Q_PAD_DISP0_DAT16__PL301_MX6QPER1_HADDR_26 (_MX6Q_PAD_DISP0_DAT16__PL301_MX6QPER1_HADDR_26) ++ ++#define MX6Q_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17 (_MX6Q_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17) ++#define MX6Q_PAD_DISP0_DAT17__IPU2_DISP0_DAT_17 (_MX6Q_PAD_DISP0_DAT17__IPU2_DISP0_DAT_17) ++#define MX6Q_PAD_DISP0_DAT17__ECSPI2_MISO (_MX6Q_PAD_DISP0_DAT17__ECSPI2_MISO) ++#define MX6Q_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD (_MX6Q_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD) ++#define MX6Q_PAD_DISP0_DAT17__SDMA_SDMA_EXT_EVENT_1 (_MX6Q_PAD_DISP0_DAT17__SDMA_SDMA_EXT_EVENT_1) ++#define MX6Q_PAD_DISP0_DAT17__GPIO_5_11 (_MX6Q_PAD_DISP0_DAT17__GPIO_5_11) ++#define MX6Q_PAD_DISP0_DAT17__MMDC_MMDC_DEBUG_22 (_MX6Q_PAD_DISP0_DAT17__MMDC_MMDC_DEBUG_22) ++#define MX6Q_PAD_DISP0_DAT17__PL301_MX6QPER1_HADDR_27 (_MX6Q_PAD_DISP0_DAT17__PL301_MX6QPER1_HADDR_27) ++ ++#define MX6Q_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18 (_MX6Q_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18) ++#define MX6Q_PAD_DISP0_DAT18__IPU2_DISP0_DAT_18 (_MX6Q_PAD_DISP0_DAT18__IPU2_DISP0_DAT_18) ++#define MX6Q_PAD_DISP0_DAT18__ECSPI2_SS0 (_MX6Q_PAD_DISP0_DAT18__ECSPI2_SS0) ++#define MX6Q_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS (_MX6Q_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS) ++#define MX6Q_PAD_DISP0_DAT18__AUDMUX_AUD4_RXFS (_MX6Q_PAD_DISP0_DAT18__AUDMUX_AUD4_RXFS) ++#define MX6Q_PAD_DISP0_DAT18__GPIO_5_12 (_MX6Q_PAD_DISP0_DAT18__GPIO_5_12) ++#define MX6Q_PAD_DISP0_DAT18__MMDC_MMDC_DEBUG_23 (_MX6Q_PAD_DISP0_DAT18__MMDC_MMDC_DEBUG_23) ++#define MX6Q_PAD_DISP0_DAT18__WEIM_WEIM_CS_2 (_MX6Q_PAD_DISP0_DAT18__WEIM_WEIM_CS_2) ++ ++#define MX6Q_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19 (_MX6Q_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19) ++#define MX6Q_PAD_DISP0_DAT19__IPU2_DISP0_DAT_19 (_MX6Q_PAD_DISP0_DAT19__IPU2_DISP0_DAT_19) ++#define MX6Q_PAD_DISP0_DAT19__ECSPI2_SCLK (_MX6Q_PAD_DISP0_DAT19__ECSPI2_SCLK) ++#define MX6Q_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD (_MX6Q_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD) ++#define MX6Q_PAD_DISP0_DAT19__AUDMUX_AUD4_RXC (_MX6Q_PAD_DISP0_DAT19__AUDMUX_AUD4_RXC) ++#define MX6Q_PAD_DISP0_DAT19__GPIO_5_13 (_MX6Q_PAD_DISP0_DAT19__GPIO_5_13) ++#define MX6Q_PAD_DISP0_DAT19__MMDC_MMDC_DEBUG_24 (_MX6Q_PAD_DISP0_DAT19__MMDC_MMDC_DEBUG_24) ++#define MX6Q_PAD_DISP0_DAT19__WEIM_WEIM_CS_3 (_MX6Q_PAD_DISP0_DAT19__WEIM_WEIM_CS_3) ++ ++#define MX6Q_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20 (_MX6Q_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20) ++#define MX6Q_PAD_DISP0_DAT20__IPU2_DISP0_DAT_20 (_MX6Q_PAD_DISP0_DAT20__IPU2_DISP0_DAT_20) ++#define MX6Q_PAD_DISP0_DAT20__ECSPI1_SCLK (_MX6Q_PAD_DISP0_DAT20__ECSPI1_SCLK) ++#define MX6Q_PAD_DISP0_DAT20__AUDMUX_AUD4_TXC (_MX6Q_PAD_DISP0_DAT20__AUDMUX_AUD4_TXC) ++#define MX6Q_PAD_DISP0_DAT20__SDMA_DEBUG_EVT_CHN_LINES_7 (_MX6Q_PAD_DISP0_DAT20__SDMA_DEBUG_EVT_CHN_LINES_7) ++#define MX6Q_PAD_DISP0_DAT20__GPIO_5_14 (_MX6Q_PAD_DISP0_DAT20__GPIO_5_14) ++#define MX6Q_PAD_DISP0_DAT20__MMDC_MMDC_DEBUG_25 (_MX6Q_PAD_DISP0_DAT20__MMDC_MMDC_DEBUG_25) ++#define MX6Q_PAD_DISP0_DAT20__PL301_MX6QPER1_HADDR_28 (_MX6Q_PAD_DISP0_DAT20__PL301_MX6QPER1_HADDR_28) ++ ++#define MX6Q_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21 (_MX6Q_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21) ++#define MX6Q_PAD_DISP0_DAT21__IPU2_DISP0_DAT_21 (_MX6Q_PAD_DISP0_DAT21__IPU2_DISP0_DAT_21) ++#define MX6Q_PAD_DISP0_DAT21__ECSPI1_MOSI (_MX6Q_PAD_DISP0_DAT21__ECSPI1_MOSI) ++#define MX6Q_PAD_DISP0_DAT21__AUDMUX_AUD4_TXD (_MX6Q_PAD_DISP0_DAT21__AUDMUX_AUD4_TXD) ++#define MX6Q_PAD_DISP0_DAT21__SDMA_DEBUG_BUS_DEVICE_0 (_MX6Q_PAD_DISP0_DAT21__SDMA_DEBUG_BUS_DEVICE_0) ++#define MX6Q_PAD_DISP0_DAT21__GPIO_5_15 (_MX6Q_PAD_DISP0_DAT21__GPIO_5_15) ++#define MX6Q_PAD_DISP0_DAT21__MMDC_MMDC_DEBUG_26 (_MX6Q_PAD_DISP0_DAT21__MMDC_MMDC_DEBUG_26) ++#define MX6Q_PAD_DISP0_DAT21__PL301_MX6QPER1_HADDR_29 (_MX6Q_PAD_DISP0_DAT21__PL301_MX6QPER1_HADDR_29) ++ ++#define MX6Q_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22 (_MX6Q_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22) ++#define MX6Q_PAD_DISP0_DAT22__IPU2_DISP0_DAT_22 (_MX6Q_PAD_DISP0_DAT22__IPU2_DISP0_DAT_22) ++#define MX6Q_PAD_DISP0_DAT22__ECSPI1_MISO (_MX6Q_PAD_DISP0_DAT22__ECSPI1_MISO) ++#define MX6Q_PAD_DISP0_DAT22__AUDMUX_AUD4_TXFS (_MX6Q_PAD_DISP0_DAT22__AUDMUX_AUD4_TXFS) ++#define MX6Q_PAD_DISP0_DAT22__SDMA_DEBUG_BUS_DEVICE_1 (_MX6Q_PAD_DISP0_DAT22__SDMA_DEBUG_BUS_DEVICE_1) ++#define MX6Q_PAD_DISP0_DAT22__GPIO_5_16 (_MX6Q_PAD_DISP0_DAT22__GPIO_5_16) ++#define MX6Q_PAD_DISP0_DAT22__MMDC_MMDC_DEBUG_27 (_MX6Q_PAD_DISP0_DAT22__MMDC_MMDC_DEBUG_27) ++#define MX6Q_PAD_DISP0_DAT22__PL301_MX6QPER1_HADDR_30 (_MX6Q_PAD_DISP0_DAT22__PL301_MX6QPER1_HADDR_30) ++ ++#define MX6Q_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23 (_MX6Q_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23) ++#define MX6Q_PAD_DISP0_DAT23__IPU2_DISP0_DAT_23 (_MX6Q_PAD_DISP0_DAT23__IPU2_DISP0_DAT_23) ++#define MX6Q_PAD_DISP0_DAT23__ECSPI1_SS0 (_MX6Q_PAD_DISP0_DAT23__ECSPI1_SS0) ++#define MX6Q_PAD_DISP0_DAT23__AUDMUX_AUD4_RXD (_MX6Q_PAD_DISP0_DAT23__AUDMUX_AUD4_RXD) ++#define MX6Q_PAD_DISP0_DAT23__SDMA_DEBUG_BUS_DEVICE_2 (_MX6Q_PAD_DISP0_DAT23__SDMA_DEBUG_BUS_DEVICE_2) ++#define MX6Q_PAD_DISP0_DAT23__GPIO_5_17 (_MX6Q_PAD_DISP0_DAT23__GPIO_5_17) ++#define MX6Q_PAD_DISP0_DAT23__MMDC_MMDC_DEBUG_28 (_MX6Q_PAD_DISP0_DAT23__MMDC_MMDC_DEBUG_28) ++#define MX6Q_PAD_DISP0_DAT23__PL301_MX6QPER1_HADDR_31 (_MX6Q_PAD_DISP0_DAT23__PL301_MX6QPER1_HADDR_31) ++ ++#define MX6Q_PAD_ENET_MDIO__ENET_MDIO (_MX6Q_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL)) ++#define MX6Q_PAD_ENET_MDIO__ESAI1_SCKR (_MX6Q_PAD_ENET_MDIO__ESAI1_SCKR) ++#define MX6Q_PAD_ENET_MDIO__SDMA_DEBUG_BUS_DEVICE_3 (_MX6Q_PAD_ENET_MDIO__SDMA_DEBUG_BUS_DEVICE_3) ++#define MX6Q_PAD_ENET_MDIO__ENET_1588_EVENT1_OUT (_MX6Q_PAD_ENET_MDIO__ENET_1588_EVENT1_OUT) ++#define MX6Q_PAD_ENET_MDIO__GPIO_1_22 (_MX6Q_PAD_ENET_MDIO__GPIO_1_22) ++#define MX6Q_PAD_ENET_MDIO__SPDIF_PLOCK (_MX6Q_PAD_ENET_MDIO__SPDIF_PLOCK) ++ ++#define MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK (_MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL)) ++#define MX6Q_PAD_ENET_REF_CLK__ESAI1_FSR (_MX6Q_PAD_ENET_REF_CLK__ESAI1_FSR) ++#define MX6Q_PAD_ENET_REF_CLK__SDMA_DEBUG_BUS_DEVICE_4 (_MX6Q_PAD_ENET_REF_CLK__SDMA_DEBUG_BUS_DEVICE_4) ++#define MX6Q_PAD_ENET_REF_CLK__GPIO_1_23 (_MX6Q_PAD_ENET_REF_CLK__GPIO_1_23) ++#define MX6Q_PAD_ENET_REF_CLK__SPDIF_SRCLK (_MX6Q_PAD_ENET_REF_CLK__SPDIF_SRCLK) ++#define MX6Q_PAD_ENET_REF_CLK__ANATOP_USBPHY1_TSTO_RX_SQUELCH (_MX6Q_PAD_ENET_REF_CLK__ANATOP_USBPHY1_TSTO_RX_SQUELCH) ++ ++#define MX6Q_PAD_ENET_RX_ER__ENET_RX_ER (_MX6Q_PAD_ENET_RX_ER__ENET_RX_ER | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL)) ++#define MX6Q_PAD_ENET_RX_ER__ESAI1_HCKR (_MX6Q_PAD_ENET_RX_ER__ESAI1_HCKR) ++#define MX6Q_PAD_ENET_RX_ER__SPDIF_IN1 (_MX6Q_PAD_ENET_RX_ER__SPDIF_IN1) ++#define MX6Q_PAD_ENET_RX_ER__ENET_1588_EVENT2_OUT (_MX6Q_PAD_ENET_RX_ER__ENET_1588_EVENT2_OUT) ++#define MX6Q_PAD_ENET_RX_ER__GPIO_1_24 (_MX6Q_PAD_ENET_RX_ER__GPIO_1_24) ++#define MX6Q_PAD_ENET_RX_ER__PHY_TDI (_MX6Q_PAD_ENET_RX_ER__PHY_TDI) ++#define MX6Q_PAD_ENET_RX_ER__ANATOP_USBPHY1_TSTO_RX_HS_RXD (_MX6Q_PAD_ENET_RX_ER__ANATOP_USBPHY1_TSTO_RX_HS_RXD) ++ ++#define MX6Q_PAD_ENET_CRS_DV__ENET_RX_EN (_MX6Q_PAD_ENET_CRS_DV__ENET_RX_EN | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL)) ++#define MX6Q_PAD_ENET_CRS_DV__ESAI1_SCKT (_MX6Q_PAD_ENET_CRS_DV__ESAI1_SCKT) ++#define MX6Q_PAD_ENET_CRS_DV__SPDIF_SPDIF_EXTCLK (_MX6Q_PAD_ENET_CRS_DV__SPDIF_SPDIF_EXTCLK) ++#define MX6Q_PAD_ENET_CRS_DV__GPIO_1_25 (_MX6Q_PAD_ENET_CRS_DV__GPIO_1_25) ++#define MX6Q_PAD_ENET_CRS_DV__PHY_TDO (_MX6Q_PAD_ENET_CRS_DV__PHY_TDO) ++#define MX6Q_PAD_ENET_CRS_DV__ANATOP_USBPHY1_TSTO_RX_FS_RXD (_MX6Q_PAD_ENET_CRS_DV__ANATOP_USBPHY1_TSTO_RX_FS_RXD) ++ ++#define MX6Q_PAD_ENET_RXD1__MLB_MLBSIG (_MX6Q_PAD_ENET_RXD1__MLB_MLBSIG) ++#define MX6Q_PAD_ENET_RXD1__ENET_RDATA_1 (_MX6Q_PAD_ENET_RXD1__ENET_RDATA_1 | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL)) ++#define MX6Q_PAD_ENET_RXD1__ESAI1_FST (_MX6Q_PAD_ENET_RXD1__ESAI1_FST) ++#define MX6Q_PAD_ENET_RXD1__ENET_1588_EVENT3_OUT (_MX6Q_PAD_ENET_RXD1__ENET_1588_EVENT3_OUT) ++#define MX6Q_PAD_ENET_RXD1__GPIO_1_26 (_MX6Q_PAD_ENET_RXD1__GPIO_1_26) ++#define MX6Q_PAD_ENET_RXD1__PHY_TCK (_MX6Q_PAD_ENET_RXD1__PHY_TCK) ++#define MX6Q_PAD_ENET_RXD1__ANATOP_USBPHY1_TSTO_RX_DISCON_DET (_MX6Q_PAD_ENET_RXD1__ANATOP_USBPHY1_TSTO_RX_DISCON_DET) ++ ++#define MX6Q_PAD_ENET_RXD0__OSC32K_32K_OUT (_MX6Q_PAD_ENET_RXD0__OSC32K_32K_OUT) ++#define MX6Q_PAD_ENET_RXD0__ENET_RDATA_0 (_MX6Q_PAD_ENET_RXD0__ENET_RDATA_0 | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL)) ++#define MX6Q_PAD_ENET_RXD0__ESAI1_HCKT (_MX6Q_PAD_ENET_RXD0__ESAI1_HCKT) ++#define MX6Q_PAD_ENET_RXD0__SPDIF_OUT1 (_MX6Q_PAD_ENET_RXD0__SPDIF_OUT1) ++#define MX6Q_PAD_ENET_RXD0__GPIO_1_27 (_MX6Q_PAD_ENET_RXD0__GPIO_1_27) ++#define MX6Q_PAD_ENET_RXD0__PHY_TMS (_MX6Q_PAD_ENET_RXD0__PHY_TMS) ++#define MX6Q_PAD_ENET_RXD0__ANATOP_USBPHY1_TSTO_PLL_CLK20DIV (_MX6Q_PAD_ENET_RXD0__ANATOP_USBPHY1_TSTO_PLL_CLK20DIV) ++ ++#define MX6Q_PAD_ENET_TX_EN__ENET_TX_EN (_MX6Q_PAD_ENET_TX_EN__ENET_TX_EN | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL)) ++#define MX6Q_PAD_ENET_TX_EN__ESAI1_TX3_RX2 (_MX6Q_PAD_ENET_TX_EN__ESAI1_TX3_RX2) ++#define MX6Q_PAD_ENET_TX_EN__GPIO_1_28 (_MX6Q_PAD_ENET_TX_EN__GPIO_1_28) ++#define MX6Q_PAD_ENET_TX_EN__SATA_PHY_TDI (_MX6Q_PAD_ENET_TX_EN__SATA_PHY_TDI) ++#define MX6Q_PAD_ENET_TX_EN__ANATOP_USBPHY2_TSTO_RX_SQUELCH (_MX6Q_PAD_ENET_TX_EN__ANATOP_USBPHY2_TSTO_RX_SQUELCH) ++ ++#define MX6Q_PAD_ENET_TXD1__MLB_MLBCLK (_MX6Q_PAD_ENET_TXD1__MLB_MLBCLK) ++#define MX6Q_PAD_ENET_TXD1__ENET_TDATA_1 (_MX6Q_PAD_ENET_TXD1__ENET_TDATA_1 | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL)) ++#define MX6Q_PAD_ENET_TXD1__ESAI1_TX2_RX3 (_MX6Q_PAD_ENET_TXD1__ESAI1_TX2_RX3) ++#define MX6Q_PAD_ENET_TXD1__ENET_1588_EVENT0_IN (_MX6Q_PAD_ENET_TXD1__ENET_1588_EVENT0_IN) ++#define MX6Q_PAD_ENET_TXD1__GPIO_1_29 (_MX6Q_PAD_ENET_TXD1__GPIO_1_29) ++#define MX6Q_PAD_ENET_TXD1__SATA_PHY_TDO (_MX6Q_PAD_ENET_TXD1__SATA_PHY_TDO) ++#define MX6Q_PAD_ENET_TXD1__ANATOP_USBPHY2_TSTO_RX_HS_RXD (_MX6Q_PAD_ENET_TXD1__ANATOP_USBPHY2_TSTO_RX_HS_RXD) ++ ++#define MX6Q_PAD_ENET_TXD0__ENET_TDATA_0 (_MX6Q_PAD_ENET_TXD0__ENET_TDATA_0 | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL)) ++#define MX6Q_PAD_ENET_TXD0__ESAI1_TX4_RX1 (_MX6Q_PAD_ENET_TXD0__ESAI1_TX4_RX1) ++#define MX6Q_PAD_ENET_TXD0__GPIO_1_30 (_MX6Q_PAD_ENET_TXD0__GPIO_1_30) ++#define MX6Q_PAD_ENET_TXD0__SATA_PHY_TCK (_MX6Q_PAD_ENET_TXD0__SATA_PHY_TCK) ++#define MX6Q_PAD_ENET_TXD0__ANATOP_USBPHY2_TSTO_RX_FS_RXD (_MX6Q_PAD_ENET_TXD0__ANATOP_USBPHY2_TSTO_RX_FS_RXD) ++ ++#define MX6Q_PAD_ENET_MDC__MLB_MLBDAT (_MX6Q_PAD_ENET_MDC__MLB_MLBDAT) ++#define MX6Q_PAD_ENET_MDC__ENET_MDC (_MX6Q_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL)) ++#define MX6Q_PAD_ENET_MDC__ESAI1_TX5_RX0 (_MX6Q_PAD_ENET_MDC__ESAI1_TX5_RX0) ++#define MX6Q_PAD_ENET_MDC__ENET_1588_EVENT1_IN (_MX6Q_PAD_ENET_MDC__ENET_1588_EVENT1_IN) ++#define MX6Q_PAD_ENET_MDC__GPIO_1_31 (_MX6Q_PAD_ENET_MDC__GPIO_1_31) ++#define MX6Q_PAD_ENET_MDC__SATA_PHY_TMS (_MX6Q_PAD_ENET_MDC__SATA_PHY_TMS) ++#define MX6Q_PAD_ENET_MDC__ANATOP_USBPHY2_TSTO_RX_DISCON_DET (_MX6Q_PAD_ENET_MDC__ANATOP_USBPHY2_TSTO_RX_DISCON_DET) ++ ++#define MX6Q_PAD_DRAM_D40__MMDC_DRAM_D_40 (_MX6Q_PAD_DRAM_D40__MMDC_DRAM_D_40) ++#define MX6Q_PAD_DRAM_D41__MMDC_DRAM_D_41 (_MX6Q_PAD_DRAM_D41__MMDC_DRAM_D_41) ++#define MX6Q_PAD_DRAM_D42__MMDC_DRAM_D_42 (_MX6Q_PAD_DRAM_D42__MMDC_DRAM_D_42) ++#define MX6Q_PAD_DRAM_D43__MMDC_DRAM_D_43 (_MX6Q_PAD_DRAM_D43__MMDC_DRAM_D_43) ++#define MX6Q_PAD_DRAM_D44__MMDC_DRAM_D_44 (_MX6Q_PAD_DRAM_D44__MMDC_DRAM_D_44) ++#define MX6Q_PAD_DRAM_D45__MMDC_DRAM_D_45 (_MX6Q_PAD_DRAM_D45__MMDC_DRAM_D_45) ++#define MX6Q_PAD_DRAM_D46__MMDC_DRAM_D_46 (_MX6Q_PAD_DRAM_D46__MMDC_DRAM_D_46) ++#define MX6Q_PAD_DRAM_D47__MMDC_DRAM_D_47 (_MX6Q_PAD_DRAM_D47__MMDC_DRAM_D_47) ++ ++#define MX6Q_PAD_DRAM_SDQS5__MMDC_DRAM_SDQS_5 (_MX6Q_PAD_DRAM_SDQS5__MMDC_DRAM_SDQS_5) ++#define MX6Q_PAD_DRAM_DQM5__MMDC_DRAM_DQM_5 (_MX6Q_PAD_DRAM_DQM5__MMDC_DRAM_DQM_5) ++ ++#define MX6Q_PAD_DRAM_D32__MMDC_DRAM_D_32 (_MX6Q_PAD_DRAM_D32__MMDC_DRAM_D_32) ++#define MX6Q_PAD_DRAM_D33__MMDC_DRAM_D_33 (_MX6Q_PAD_DRAM_D33__MMDC_DRAM_D_33) ++#define MX6Q_PAD_DRAM_D34__MMDC_DRAM_D_34 (_MX6Q_PAD_DRAM_D34__MMDC_DRAM_D_34) ++#define MX6Q_PAD_DRAM_D35__MMDC_DRAM_D_35 (_MX6Q_PAD_DRAM_D35__MMDC_DRAM_D_35) ++#define MX6Q_PAD_DRAM_D36__MMDC_DRAM_D_36 (_MX6Q_PAD_DRAM_D36__MMDC_DRAM_D_36) ++#define MX6Q_PAD_DRAM_D37__MMDC_DRAM_D_37 (_MX6Q_PAD_DRAM_D37__MMDC_DRAM_D_37) ++#define MX6Q_PAD_DRAM_D38__MMDC_DRAM_D_38 (_MX6Q_PAD_DRAM_D38__MMDC_DRAM_D_38) ++#define MX6Q_PAD_DRAM_D39__MMDC_DRAM_D_39 (_MX6Q_PAD_DRAM_D39__MMDC_DRAM_D_39) ++#define MX6Q_PAD_DRAM_DQM4__MMDC_DRAM_DQM_4 (_MX6Q_PAD_DRAM_DQM4__MMDC_DRAM_DQM_4) ++#define MX6Q_PAD_DRAM_SDQS4__MMDC_DRAM_SDQS_4 (_MX6Q_PAD_DRAM_SDQS4__MMDC_DRAM_SDQS_4) ++#define MX6Q_PAD_DRAM_D24__MMDC_DRAM_D_24 (_MX6Q_PAD_DRAM_D24__MMDC_DRAM_D_24) ++#define MX6Q_PAD_DRAM_D25__MMDC_DRAM_D_25 (_MX6Q_PAD_DRAM_D25__MMDC_DRAM_D_25) ++#define MX6Q_PAD_DRAM_D26__MMDC_DRAM_D_26 (_MX6Q_PAD_DRAM_D26__MMDC_DRAM_D_26) ++#define MX6Q_PAD_DRAM_D27__MMDC_DRAM_D_27 (_MX6Q_PAD_DRAM_D27__MMDC_DRAM_D_27) ++#define MX6Q_PAD_DRAM_D28__MMDC_DRAM_D_28 (_MX6Q_PAD_DRAM_D28__MMDC_DRAM_D_28) ++#define MX6Q_PAD_DRAM_D29__MMDC_DRAM_D_29 (_MX6Q_PAD_DRAM_D29__MMDC_DRAM_D_29) ++#define MX6Q_PAD_DRAM_SDQS3__MMDC_DRAM_SDQS_3 (_MX6Q_PAD_DRAM_SDQS3__MMDC_DRAM_SDQS_3) ++#define MX6Q_PAD_DRAM_D30__MMDC_DRAM_D_30 (_MX6Q_PAD_DRAM_D30__MMDC_DRAM_D_30) ++#define MX6Q_PAD_DRAM_D31__MMDC_DRAM_D_31 (_MX6Q_PAD_DRAM_D31__MMDC_DRAM_D_31) ++#define MX6Q_PAD_DRAM_DQM3__MMDC_DRAM_DQM_3 (_MX6Q_PAD_DRAM_DQM3__MMDC_DRAM_DQM_3) ++#define MX6Q_PAD_DRAM_D16__MMDC_DRAM_D_16 (_MX6Q_PAD_DRAM_D16__MMDC_DRAM_D_16) ++#define MX6Q_PAD_DRAM_D17__MMDC_DRAM_D_17 (_MX6Q_PAD_DRAM_D17__MMDC_DRAM_D_17) ++#define MX6Q_PAD_DRAM_D18__MMDC_DRAM_D_18 (_MX6Q_PAD_DRAM_D18__MMDC_DRAM_D_18) ++#define MX6Q_PAD_DRAM_D19__MMDC_DRAM_D_19 (_MX6Q_PAD_DRAM_D19__MMDC_DRAM_D_19) ++#define MX6Q_PAD_DRAM_D20__MMDC_DRAM_D_20 (_MX6Q_PAD_DRAM_D20__MMDC_DRAM_D_20) ++#define MX6Q_PAD_DRAM_D21__MMDC_DRAM_D_21 (_MX6Q_PAD_DRAM_D21__MMDC_DRAM_D_21) ++#define MX6Q_PAD_DRAM_D22__MMDC_DRAM_D_22 (_MX6Q_PAD_DRAM_D22__MMDC_DRAM_D_22) ++#define MX6Q_PAD_DRAM_SDQS2__MMDC_DRAM_SDQS_2 (_MX6Q_PAD_DRAM_SDQS2__MMDC_DRAM_SDQS_2) ++#define MX6Q_PAD_DRAM_D23__MMDC_DRAM_D_23 (_MX6Q_PAD_DRAM_D23__MMDC_DRAM_D_23) ++#define MX6Q_PAD_DRAM_DQM2__MMDC_DRAM_DQM_2 (_MX6Q_PAD_DRAM_DQM2__MMDC_DRAM_DQM_2) ++#define MX6Q_PAD_DRAM_A0__MMDC_DRAM_A_0 (_MX6Q_PAD_DRAM_A0__MMDC_DRAM_A_0) ++#define MX6Q_PAD_DRAM_A1__MMDC_DRAM_A_1 (_MX6Q_PAD_DRAM_A1__MMDC_DRAM_A_1) ++#define MX6Q_PAD_DRAM_A2__MMDC_DRAM_A_2 (_MX6Q_PAD_DRAM_A2__MMDC_DRAM_A_2) ++#define MX6Q_PAD_DRAM_A3__MMDC_DRAM_A_3 (_MX6Q_PAD_DRAM_A3__MMDC_DRAM_A_3) ++#define MX6Q_PAD_DRAM_A4__MMDC_DRAM_A_4 (_MX6Q_PAD_DRAM_A4__MMDC_DRAM_A_4) ++#define MX6Q_PAD_DRAM_A5__MMDC_DRAM_A_5 (_MX6Q_PAD_DRAM_A5__MMDC_DRAM_A_5) ++#define MX6Q_PAD_DRAM_A6__MMDC_DRAM_A_6 (_MX6Q_PAD_DRAM_A6__MMDC_DRAM_A_6) ++#define MX6Q_PAD_DRAM_A7__MMDC_DRAM_A_7 (_MX6Q_PAD_DRAM_A7__MMDC_DRAM_A_7) ++#define MX6Q_PAD_DRAM_A8__MMDC_DRAM_A_8 (_MX6Q_PAD_DRAM_A8__MMDC_DRAM_A_8) ++#define MX6Q_PAD_DRAM_A9__MMDC_DRAM_A_9 (_MX6Q_PAD_DRAM_A9__MMDC_DRAM_A_9) ++#define MX6Q_PAD_DRAM_A10__MMDC_DRAM_A_10 (_MX6Q_PAD_DRAM_A10__MMDC_DRAM_A_10) ++#define MX6Q_PAD_DRAM_A11__MMDC_DRAM_A_11 (_MX6Q_PAD_DRAM_A11__MMDC_DRAM_A_11) ++#define MX6Q_PAD_DRAM_A12__MMDC_DRAM_A_12 (_MX6Q_PAD_DRAM_A12__MMDC_DRAM_A_12) ++#define MX6Q_PAD_DRAM_A13__MMDC_DRAM_A_13 (_MX6Q_PAD_DRAM_A13__MMDC_DRAM_A_13) ++#define MX6Q_PAD_DRAM_A14__MMDC_DRAM_A_14 (_MX6Q_PAD_DRAM_A14__MMDC_DRAM_A_14) ++#define MX6Q_PAD_DRAM_A15__MMDC_DRAM_A_15 (_MX6Q_PAD_DRAM_A15__MMDC_DRAM_A_15) ++#define MX6Q_PAD_DRAM_CAS__MMDC_DRAM_CAS (_MX6Q_PAD_DRAM_CAS__MMDC_DRAM_CAS) ++#define MX6Q_PAD_DRAM_CS0__MMDC_DRAM_CS_0 (_MX6Q_PAD_DRAM_CS0__MMDC_DRAM_CS_0) ++#define MX6Q_PAD_DRAM_CS1__MMDC_DRAM_CS_1 (_MX6Q_PAD_DRAM_CS1__MMDC_DRAM_CS_1) ++#define MX6Q_PAD_DRAM_RAS__MMDC_DRAM_RAS (_MX6Q_PAD_DRAM_RAS__MMDC_DRAM_RAS) ++#define MX6Q_PAD_DRAM_RESET__MMDC_DRAM_RESET (_MX6Q_PAD_DRAM_RESET__MMDC_DRAM_RESET) ++#define MX6Q_PAD_DRAM_SDBA0__MMDC_DRAM_SDBA_0 (_MX6Q_PAD_DRAM_SDBA0__MMDC_DRAM_SDBA_0) ++#define MX6Q_PAD_DRAM_SDBA1__MMDC_DRAM_SDBA_1 (_MX6Q_PAD_DRAM_SDBA1__MMDC_DRAM_SDBA_1) ++#define MX6Q_PAD_DRAM_SDCLK_0__MMDC_DRAM_SDCLK0 (_MX6Q_PAD_DRAM_SDCLK_0__MMDC_DRAM_SDCLK0) ++#define MX6Q_PAD_DRAM_SDBA2__MMDC_DRAM_SDBA_2 (_MX6Q_PAD_DRAM_SDBA2__MMDC_DRAM_SDBA_2) ++#define MX6Q_PAD_DRAM_SDCKE0__MMDC_DRAM_SDCKE_0 (_MX6Q_PAD_DRAM_SDCKE0__MMDC_DRAM_SDCKE_0) ++#define MX6Q_PAD_DRAM_SDCLK_1__MMDC_DRAM_SDCLK1 (_MX6Q_PAD_DRAM_SDCLK_1__MMDC_DRAM_SDCLK1) ++#define MX6Q_PAD_DRAM_SDCKE1__MMDC_DRAM_SDCKE_1 (_MX6Q_PAD_DRAM_SDCKE1__MMDC_DRAM_SDCKE_1) ++#define MX6Q_PAD_DRAM_SDODT0__MMDC_DRAM_ODT_0 (_MX6Q_PAD_DRAM_SDODT0__MMDC_DRAM_ODT_0) ++#define MX6Q_PAD_DRAM_SDODT1__MMDC_DRAM_ODT_1 (_MX6Q_PAD_DRAM_SDODT1__MMDC_DRAM_ODT_1) ++#define MX6Q_PAD_DRAM_SDWE__MMDC_DRAM_SDWE (_MX6Q_PAD_DRAM_SDWE__MMDC_DRAM_SDWE) ++#define MX6Q_PAD_DRAM_D0__MMDC_DRAM_D_0 (_MX6Q_PAD_DRAM_D0__MMDC_DRAM_D_0) ++#define MX6Q_PAD_DRAM_D1__MMDC_DRAM_D_1 (_MX6Q_PAD_DRAM_D1__MMDC_DRAM_D_1) ++#define MX6Q_PAD_DRAM_D2__MMDC_DRAM_D_2 (_MX6Q_PAD_DRAM_D2__MMDC_DRAM_D_2) ++#define MX6Q_PAD_DRAM_D3__MMDC_DRAM_D_3 (_MX6Q_PAD_DRAM_D3__MMDC_DRAM_D_3) ++#define MX6Q_PAD_DRAM_D4__MMDC_DRAM_D_4 (_MX6Q_PAD_DRAM_D4__MMDC_DRAM_D_4) ++#define MX6Q_PAD_DRAM_D5__MMDC_DRAM_D_5 (_MX6Q_PAD_DRAM_D5__MMDC_DRAM_D_5) ++#define MX6Q_PAD_DRAM_SDQS0__MMDC_DRAM_SDQS_0 (_MX6Q_PAD_DRAM_SDQS0__MMDC_DRAM_SDQS_0) ++#define MX6Q_PAD_DRAM_D6__MMDC_DRAM_D_6 (_MX6Q_PAD_DRAM_D6__MMDC_DRAM_D_6) ++#define MX6Q_PAD_DRAM_D7__MMDC_DRAM_D_7 (_MX6Q_PAD_DRAM_D7__MMDC_DRAM_D_7) ++#define MX6Q_PAD_DRAM_DQM0__MMDC_DRAM_DQM_0 (_MX6Q_PAD_DRAM_DQM0__MMDC_DRAM_DQM_0) ++#define MX6Q_PAD_DRAM_D8__MMDC_DRAM_D_8 (_MX6Q_PAD_DRAM_D8__MMDC_DRAM_D_8) ++#define MX6Q_PAD_DRAM_D9__MMDC_DRAM_D_9 (_MX6Q_PAD_DRAM_D9__MMDC_DRAM_D_9) ++#define MX6Q_PAD_DRAM_D10__MMDC_DRAM_D_10 (_MX6Q_PAD_DRAM_D10__MMDC_DRAM_D_10) ++#define MX6Q_PAD_DRAM_D11__MMDC_DRAM_D_11 (_MX6Q_PAD_DRAM_D11__MMDC_DRAM_D_11) ++#define MX6Q_PAD_DRAM_D12__MMDC_DRAM_D_12 (_MX6Q_PAD_DRAM_D12__MMDC_DRAM_D_12) ++#define MX6Q_PAD_DRAM_D13__MMDC_DRAM_D_13 (_MX6Q_PAD_DRAM_D13__MMDC_DRAM_D_13) ++#define MX6Q_PAD_DRAM_D14__MMDC_DRAM_D_14 (_MX6Q_PAD_DRAM_D14__MMDC_DRAM_D_14) ++#define MX6Q_PAD_DRAM_SDQS1__MMDC_DRAM_SDQS_1 (_MX6Q_PAD_DRAM_SDQS1__MMDC_DRAM_SDQS_1) ++#define MX6Q_PAD_DRAM_D15__MMDC_DRAM_D_15 (_MX6Q_PAD_DRAM_D15__MMDC_DRAM_D_15) ++#define MX6Q_PAD_DRAM_DQM1__MMDC_DRAM_DQM_1 (_MX6Q_PAD_DRAM_DQM1__MMDC_DRAM_DQM_1) ++#define MX6Q_PAD_DRAM_D48__MMDC_DRAM_D_48 (_MX6Q_PAD_DRAM_D48__MMDC_DRAM_D_48) ++#define MX6Q_PAD_DRAM_D49__MMDC_DRAM_D_49 (_MX6Q_PAD_DRAM_D49__MMDC_DRAM_D_49) ++#define MX6Q_PAD_DRAM_D50__MMDC_DRAM_D_50 (_MX6Q_PAD_DRAM_D50__MMDC_DRAM_D_50) ++#define MX6Q_PAD_DRAM_D51__MMDC_DRAM_D_51 (_MX6Q_PAD_DRAM_D51__MMDC_DRAM_D_51) ++#define MX6Q_PAD_DRAM_D52__MMDC_DRAM_D_52 (_MX6Q_PAD_DRAM_D52__MMDC_DRAM_D_52) ++#define MX6Q_PAD_DRAM_D53__MMDC_DRAM_D_53 (_MX6Q_PAD_DRAM_D53__MMDC_DRAM_D_53) ++#define MX6Q_PAD_DRAM_D54__MMDC_DRAM_D_54 (_MX6Q_PAD_DRAM_D54__MMDC_DRAM_D_54) ++#define MX6Q_PAD_DRAM_D55__MMDC_DRAM_D_55 (_MX6Q_PAD_DRAM_D55__MMDC_DRAM_D_55) ++#define MX6Q_PAD_DRAM_SDQS6__MMDC_DRAM_SDQS_6 (_MX6Q_PAD_DRAM_SDQS6__MMDC_DRAM_SDQS_6) ++#define MX6Q_PAD_DRAM_DQM6__MMDC_DRAM_DQM_6 (_MX6Q_PAD_DRAM_DQM6__MMDC_DRAM_DQM_6) ++#define MX6Q_PAD_DRAM_D56__MMDC_DRAM_D_56 (_MX6Q_PAD_DRAM_D56__MMDC_DRAM_D_56) ++#define MX6Q_PAD_DRAM_SDQS7__MMDC_DRAM_SDQS_7 (_MX6Q_PAD_DRAM_SDQS7__MMDC_DRAM_SDQS_7) ++#define MX6Q_PAD_DRAM_D57__MMDC_DRAM_D_57 (_MX6Q_PAD_DRAM_D57__MMDC_DRAM_D_57) ++#define MX6Q_PAD_DRAM_D58__MMDC_DRAM_D_58 (_MX6Q_PAD_DRAM_D58__MMDC_DRAM_D_58) ++#define MX6Q_PAD_DRAM_D59__MMDC_DRAM_D_59 (_MX6Q_PAD_DRAM_D59__MMDC_DRAM_D_59) ++#define MX6Q_PAD_DRAM_D60__MMDC_DRAM_D_60 (_MX6Q_PAD_DRAM_D60__MMDC_DRAM_D_60) ++#define MX6Q_PAD_DRAM_DQM7__MMDC_DRAM_DQM_7 (_MX6Q_PAD_DRAM_DQM7__MMDC_DRAM_DQM_7) ++#define MX6Q_PAD_DRAM_D61__MMDC_DRAM_D_61 (_MX6Q_PAD_DRAM_D61__MMDC_DRAM_D_61) ++#define MX6Q_PAD_DRAM_D62__MMDC_DRAM_D_62 (_MX6Q_PAD_DRAM_D62__MMDC_DRAM_D_62) ++#define MX6Q_PAD_DRAM_D63__MMDC_DRAM_D_63 (_MX6Q_PAD_DRAM_D63__MMDC_DRAM_D_63) ++ ++#define MX6Q_PAD_KEY_COL0__ECSPI1_SCLK (_MX6Q_PAD_KEY_COL0__ECSPI1_SCLK) ++#define MX6Q_PAD_KEY_COL0__ENET_RDATA_3 (_MX6Q_PAD_KEY_COL0__ENET_RDATA_3 | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL)) ++#define MX6Q_PAD_KEY_COL0__AUDMUX_AUD5_TXC (_MX6Q_PAD_KEY_COL0__AUDMUX_AUD5_TXC) ++#define MX6Q_PAD_KEY_COL0__KPP_COL_0 (_MX6Q_PAD_KEY_COL0__KPP_COL_0) ++#define MX6Q_PAD_KEY_COL0__UART4_TXD (_MX6Q_PAD_KEY_COL0__UART4_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) ++#define MX6Q_PAD_KEY_COL0__UART4_RXD (_MX6Q_PAD_KEY_COL0__UART4_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) ++#define MX6Q_PAD_KEY_COL0__GPIO_4_6 (_MX6Q_PAD_KEY_COL0__GPIO_4_6) ++#define MX6Q_PAD_KEY_COL0__DCIC1_DCIC_OUT (_MX6Q_PAD_KEY_COL0__DCIC1_DCIC_OUT) ++#define MX6Q_PAD_KEY_COL0__SRC_ANY_PU_RST (_MX6Q_PAD_KEY_COL0__SRC_ANY_PU_RST) ++ ++#define MX6Q_PAD_KEY_ROW0__ECSPI1_MOSI (_MX6Q_PAD_KEY_ROW0__ECSPI1_MOSI) ++#define MX6Q_PAD_KEY_ROW0__ENET_TDATA_3 (_MX6Q_PAD_KEY_ROW0__ENET_TDATA_3 | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL)) ++#define MX6Q_PAD_KEY_ROW0__AUDMUX_AUD5_TXD (_MX6Q_PAD_KEY_ROW0__AUDMUX_AUD5_TXD) ++#define MX6Q_PAD_KEY_ROW0__KPP_ROW_0 (_MX6Q_PAD_KEY_ROW0__KPP_ROW_0) ++#define MX6Q_PAD_KEY_ROW0__UART4_TXD (_MX6Q_PAD_KEY_ROW0__UART4_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) ++#define MX6Q_PAD_KEY_ROW0__UART4_RXD (_MX6Q_PAD_KEY_ROW0__UART4_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) ++#define MX6Q_PAD_KEY_ROW0__GPIO_4_7 (_MX6Q_PAD_KEY_ROW0__GPIO_4_7) ++#define MX6Q_PAD_KEY_ROW0__DCIC2_DCIC_OUT (_MX6Q_PAD_KEY_ROW0__DCIC2_DCIC_OUT) ++#define MX6Q_PAD_KEY_ROW0__PL301_MX6QPER1_HADDR_0 (_MX6Q_PAD_KEY_ROW0__PL301_MX6QPER1_HADDR_0) ++ ++#define MX6Q_PAD_KEY_COL1__ECSPI1_MISO (_MX6Q_PAD_KEY_COL1__ECSPI1_MISO) ++#define MX6Q_PAD_KEY_COL1__ENET_MDIO (_MX6Q_PAD_KEY_COL1__ENET_MDIO | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL)) ++#define MX6Q_PAD_KEY_COL1__AUDMUX_AUD5_TXFS (_MX6Q_PAD_KEY_COL1__AUDMUX_AUD5_TXFS) ++#define MX6Q_PAD_KEY_COL1__KPP_COL_1 (_MX6Q_PAD_KEY_COL1__KPP_COL_1) ++#define MX6Q_PAD_KEY_COL1__UART5_TXD (_MX6Q_PAD_KEY_COL1__UART5_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) ++#define MX6Q_PAD_KEY_COL1__UART5_RXD (_MX6Q_PAD_KEY_COL1__UART5_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) ++#define MX6Q_PAD_KEY_COL1__GPIO_4_8 (_MX6Q_PAD_KEY_COL1__GPIO_4_8) ++#define MX6Q_PAD_KEY_COL1__USDHC1_VSELECT (_MX6Q_PAD_KEY_COL1__USDHC1_VSELECT | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) ++#define MX6Q_PAD_KEY_COL1__PL301_MX6QPER1_HADDR_1 (_MX6Q_PAD_KEY_COL1__PL301_MX6QPER1_HADDR_1) ++ ++#define MX6Q_PAD_KEY_ROW1__ECSPI1_SS0 (_MX6Q_PAD_KEY_ROW1__ECSPI1_SS0) ++#define MX6Q_PAD_KEY_ROW1__ENET_COL (_MX6Q_PAD_KEY_ROW1__ENET_COL | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL)) ++#define MX6Q_PAD_KEY_ROW1__AUDMUX_AUD5_RXD (_MX6Q_PAD_KEY_ROW1__AUDMUX_AUD5_RXD) ++#define MX6Q_PAD_KEY_ROW1__KPP_ROW_1 (_MX6Q_PAD_KEY_ROW1__KPP_ROW_1) ++#define MX6Q_PAD_KEY_ROW1__UART5_TXD (_MX6Q_PAD_KEY_ROW1__UART5_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) ++#define MX6Q_PAD_KEY_ROW1__UART5_RXD (_MX6Q_PAD_KEY_ROW1__UART5_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) ++#define MX6Q_PAD_KEY_ROW1__GPIO_4_9 (_MX6Q_PAD_KEY_ROW1__GPIO_4_9) ++#define MX6Q_PAD_KEY_ROW1__USDHC2_VSELECT (_MX6Q_PAD_KEY_ROW1__USDHC2_VSELECT | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) ++#define MX6Q_PAD_KEY_ROW1__PL301_MX6QPER1_HADDR_2 (_MX6Q_PAD_KEY_ROW1__PL301_MX6QPER1_HADDR_2) ++ ++#define MX6Q_PAD_KEY_COL2__ECSPI1_SS1 (_MX6Q_PAD_KEY_COL2__ECSPI1_SS1) ++#define MX6Q_PAD_KEY_COL2__ENET_RDATA_2 (_MX6Q_PAD_KEY_COL2__ENET_RDATA_2 | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL)) ++#define MX6Q_PAD_KEY_COL2__CAN1_TXCAN (_MX6Q_PAD_KEY_COL2__CAN1_TXCAN) ++#define MX6Q_PAD_KEY_COL2__KPP_COL_2 (_MX6Q_PAD_KEY_COL2__KPP_COL_2) ++#define MX6Q_PAD_KEY_COL2__ENET_MDC (_MX6Q_PAD_KEY_COL2__ENET_MDC | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL)) ++#define MX6Q_PAD_KEY_COL2__GPIO_4_10 (_MX6Q_PAD_KEY_COL2__GPIO_4_10) ++#define MX6Q_PAD_KEY_COL2__USBOH3_H1USB_PWRCTL_WAKEUP (_MX6Q_PAD_KEY_COL2__USBOH3_H1USB_PWRCTL_WAKEUP) ++#define MX6Q_PAD_KEY_COL2__PL301_MX6QPER1_HADDR_3 (_MX6Q_PAD_KEY_COL2__PL301_MX6QPER1_HADDR_3) ++ ++#define MX6Q_PAD_KEY_ROW2__ECSPI1_SS2 (_MX6Q_PAD_KEY_ROW2__ECSPI1_SS2) ++#define MX6Q_PAD_KEY_ROW2__ENET_TDATA_2 (_MX6Q_PAD_KEY_ROW2__ENET_TDATA_2 | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL)) ++#define MX6Q_PAD_KEY_ROW2__CAN1_RXCAN (_MX6Q_PAD_KEY_ROW2__CAN1_RXCAN) ++#define MX6Q_PAD_KEY_ROW2__KPP_ROW_2 (_MX6Q_PAD_KEY_ROW2__KPP_ROW_2) ++#define MX6Q_PAD_KEY_ROW2__USDHC2_VSELECT (_MX6Q_PAD_KEY_ROW2__USDHC2_VSELECT | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) ++#define MX6Q_PAD_KEY_ROW2__GPIO_4_11 (_MX6Q_PAD_KEY_ROW2__GPIO_4_11) ++#define MX6Q_PAD_KEY_ROW2__HDMI_TX_CEC_LINE (_MX6Q_PAD_KEY_ROW2__HDMI_TX_CEC_LINE) ++#define MX6Q_PAD_KEY_ROW2__PL301_MX6QPER1_HADDR_4 (_MX6Q_PAD_KEY_ROW2__PL301_MX6QPER1_HADDR_4) ++ ++#define MX6Q_PAD_KEY_COL3__ECSPI1_SS3 (_MX6Q_PAD_KEY_COL3__ECSPI1_SS3) ++#define MX6Q_PAD_KEY_COL3__ENET_CRS (_MX6Q_PAD_KEY_COL3__ENET_CRS | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL)) ++#define MX6Q_PAD_KEY_COL3__HDMI_TX_DDC_SCL (_MX6Q_PAD_KEY_COL3__HDMI_TX_DDC_SCL) ++#define MX6Q_PAD_KEY_COL3__KPP_COL_3 (_MX6Q_PAD_KEY_COL3__KPP_COL_3) ++#define MX6Q_PAD_KEY_COL3__I2C2_SCL (_MX6Q_PAD_KEY_COL3__I2C2_SCL | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL)) ++#define MX6Q_PAD_KEY_COL3__GPIO_4_12 (_MX6Q_PAD_KEY_COL3__GPIO_4_12) ++#define MX6Q_PAD_KEY_COL3__SPDIF_IN1 (_MX6Q_PAD_KEY_COL3__SPDIF_IN1) ++#define MX6Q_PAD_KEY_COL3__PL301_MX6QPER1_HADDR_5 (_MX6Q_PAD_KEY_COL3__PL301_MX6QPER1_HADDR_5) ++ ++#define MX6Q_PAD_KEY_ROW3__OSC32K_32K_OUT (_MX6Q_PAD_KEY_ROW3__OSC32K_32K_OUT) ++#define MX6Q_PAD_KEY_ROW3__ASRC_ASRC_EXT_CLK (_MX6Q_PAD_KEY_ROW3__ASRC_ASRC_EXT_CLK) ++#define MX6Q_PAD_KEY_ROW3__HDMI_TX_DDC_SDA (_MX6Q_PAD_KEY_ROW3__HDMI_TX_DDC_SDA) ++#define MX6Q_PAD_KEY_ROW3__KPP_ROW_3 (_MX6Q_PAD_KEY_ROW3__KPP_ROW_3) ++#define MX6Q_PAD_KEY_ROW3__I2C2_SDA (_MX6Q_PAD_KEY_ROW3__I2C2_SDA | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL)) ++#define MX6Q_PAD_KEY_ROW3__GPIO_4_13 (_MX6Q_PAD_KEY_ROW3__GPIO_4_13) ++#define MX6Q_PAD_KEY_ROW3__USDHC1_VSELECT (_MX6Q_PAD_KEY_ROW3__USDHC1_VSELECT | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) ++#define MX6Q_PAD_KEY_ROW3__PL301_MX6QPER1_HADDR_6 (_MX6Q_PAD_KEY_ROW3__PL301_MX6QPER1_HADDR_6) ++ ++#define MX6Q_PAD_KEY_COL4__CAN2_TXCAN (_MX6Q_PAD_KEY_COL4__CAN2_TXCAN) ++#define MX6Q_PAD_KEY_COL4__IPU1_SISG_4 (_MX6Q_PAD_KEY_COL4__IPU1_SISG_4) ++#define MX6Q_PAD_KEY_COL4__USBOH3_USBOTG_OC (_MX6Q_PAD_KEY_COL4__USBOH3_USBOTG_OC) ++#define MX6Q_PAD_KEY_COL4__KPP_COL_4 (_MX6Q_PAD_KEY_COL4__KPP_COL_4) ++#define MX6Q_PAD_KEY_COL4__UART5_CTS (_MX6Q_PAD_KEY_COL4__UART5_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) ++#define MX6Q_PAD_KEY_COL4__UART5_RTS (_MX6Q_PAD_KEY_COL4__UART5_RTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) ++#define MX6Q_PAD_KEY_COL4__GPIO_4_14 (_MX6Q_PAD_KEY_COL4__GPIO_4_14) ++#define MX6Q_PAD_KEY_COL4__MMDC_MMDC_DEBUG_49 (_MX6Q_PAD_KEY_COL4__MMDC_MMDC_DEBUG_49) ++#define MX6Q_PAD_KEY_COL4__PL301_MX6QPER1_HADDR_7 (_MX6Q_PAD_KEY_COL4__PL301_MX6QPER1_HADDR_7) ++ ++#define MX6Q_PAD_KEY_ROW4__CAN2_RXCAN (_MX6Q_PAD_KEY_ROW4__CAN2_RXCAN) ++#define MX6Q_PAD_KEY_ROW4__IPU1_SISG_5 (_MX6Q_PAD_KEY_ROW4__IPU1_SISG_5) ++#define MX6Q_PAD_KEY_ROW4__USBOH3_USBOTG_PWR (_MX6Q_PAD_KEY_ROW4__USBOH3_USBOTG_PWR) ++#define MX6Q_PAD_KEY_ROW4__KPP_ROW_4 (_MX6Q_PAD_KEY_ROW4__KPP_ROW_4) ++#define MX6Q_PAD_KEY_ROW4__UART5_CTS (_MX6Q_PAD_KEY_ROW4__UART5_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) ++#define MX6Q_PAD_KEY_ROW4__GPIO_4_15 (_MX6Q_PAD_KEY_ROW4__GPIO_4_15) ++#define MX6Q_PAD_KEY_ROW4__MMDC_MMDC_DEBUG_50 (_MX6Q_PAD_KEY_ROW4__MMDC_MMDC_DEBUG_50) ++#define MX6Q_PAD_KEY_ROW4__PL301_MX6QPER1_HADDR_8 (_MX6Q_PAD_KEY_ROW4__PL301_MX6QPER1_HADDR_8) ++ ++#define MX6Q_PAD_GPIO_0__CCM_CLKO (_MX6Q_PAD_GPIO_0__CCM_CLKO) ++#define MX6Q_PAD_GPIO_0__KPP_COL_5 (_MX6Q_PAD_GPIO_0__KPP_COL_5) ++#define MX6Q_PAD_GPIO_0__ASRC_ASRC_EXT_CLK (_MX6Q_PAD_GPIO_0__ASRC_ASRC_EXT_CLK) ++#define MX6Q_PAD_GPIO_0__EPIT1_EPITO (_MX6Q_PAD_GPIO_0__EPIT1_EPITO) ++#define MX6Q_PAD_GPIO_0__GPIO_1_0 (_MX6Q_PAD_GPIO_0__GPIO_1_0) ++#define MX6Q_PAD_GPIO_0__USBOH3_USBH1_PWR (_MX6Q_PAD_GPIO_0__USBOH3_USBH1_PWR) ++#define MX6Q_PAD_GPIO_0__SNVS_HP_WRAPPER_SNVS_VIO_5 (_MX6Q_PAD_GPIO_0__SNVS_HP_WRAPPER_SNVS_VIO_5) ++ ++#define MX6Q_PAD_GPIO_1__ESAI1_SCKR (_MX6Q_PAD_GPIO_1__ESAI1_SCKR) ++#define MX6Q_PAD_GPIO_1__WDOG2_WDOG_B (_MX6Q_PAD_GPIO_1__WDOG2_WDOG_B) ++#define MX6Q_PAD_GPIO_1__KPP_ROW_5 (_MX6Q_PAD_GPIO_1__KPP_ROW_5) ++#define MX6Q_PAD_GPIO_1__PWM2_PWMO (_MX6Q_PAD_GPIO_1__PWM2_PWMO) ++#define MX6Q_PAD_GPIO_1__GPIO_1_1 (_MX6Q_PAD_GPIO_1__GPIO_1_1) ++#define MX6Q_PAD_GPIO_1__USDHC1_CD (_MX6Q_PAD_GPIO_1__USDHC1_CD | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) ++#define MX6Q_PAD_GPIO_1__SRC_TESTER_ACK (_MX6Q_PAD_GPIO_1__SRC_TESTER_ACK) ++ ++#define MX6Q_PAD_GPIO_9__ESAI1_FSR (_MX6Q_PAD_GPIO_9__ESAI1_FSR) ++#define MX6Q_PAD_GPIO_9__WDOG1_WDOG_B (_MX6Q_PAD_GPIO_9__WDOG1_WDOG_B) ++#define MX6Q_PAD_GPIO_9__KPP_COL_6 (_MX6Q_PAD_GPIO_9__KPP_COL_6) ++#define MX6Q_PAD_GPIO_9__CCM_REF_EN_B (_MX6Q_PAD_GPIO_9__CCM_REF_EN_B) ++#define MX6Q_PAD_GPIO_9__PWM1_PWMO (_MX6Q_PAD_GPIO_9__PWM1_PWMO | MUX_PAD_CTRL(MX6Q_PWM_PAD_CTRL)) ++#define MX6Q_PAD_GPIO_9__GPIO_1_9 (_MX6Q_PAD_GPIO_9__GPIO_1_9 | MUX_PAD_CTRL(MX6Q_HIGH_DRV)) ++#define MX6Q_PAD_GPIO_9__USDHC1_WP (_MX6Q_PAD_GPIO_9__USDHC1_WP | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) ++#define MX6Q_PAD_GPIO_9__SRC_EARLY_RST (_MX6Q_PAD_GPIO_9__SRC_EARLY_RST) ++ ++#define MX6Q_PAD_GPIO_3__ESAI1_HCKR (_MX6Q_PAD_GPIO_3__ESAI1_HCKR) ++#define MX6Q_PAD_GPIO_3__OBSERVE_MUX_OBSRV_INT_OUT0 (_MX6Q_PAD_GPIO_3__OBSERVE_MUX_OBSRV_INT_OUT0) ++#define MX6Q_PAD_GPIO_3__I2C3_SCL (_MX6Q_PAD_GPIO_3__I2C3_SCL | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL)) ++#define MX6Q_PAD_GPIO_3__ANATOP_ANATOP_24M_OUT (_MX6Q_PAD_GPIO_3__ANATOP_ANATOP_24M_OUT) ++#define MX6Q_PAD_GPIO_3__CCM_CLKO2 (_MX6Q_PAD_GPIO_3__CCM_CLKO2) ++#define MX6Q_PAD_GPIO_3__GPIO_1_3 (_MX6Q_PAD_GPIO_3__GPIO_1_3) ++#define MX6Q_PAD_GPIO_3__USBOH3_USBH1_OC (_MX6Q_PAD_GPIO_3__USBOH3_USBH1_OC) ++#define MX6Q_PAD_GPIO_3__MLB_MLBCLK (_MX6Q_PAD_GPIO_3__MLB_MLBCLK) ++ ++#define MX6Q_PAD_GPIO_6__ESAI1_SCKT (_MX6Q_PAD_GPIO_6__ESAI1_SCKT) ++#define MX6Q_PAD_GPIO_6__OBSERVE_MUX_OBSRV_INT_OUT1 (_MX6Q_PAD_GPIO_6__OBSERVE_MUX_OBSRV_INT_OUT1) ++#define MX6Q_PAD_GPIO_6__I2C3_SDA (_MX6Q_PAD_GPIO_6__I2C3_SDA | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL)) ++#define MX6Q_PAD_GPIO_6__CCM_CCM_OUT_0 (_MX6Q_PAD_GPIO_6__CCM_CCM_OUT_0) ++#define MX6Q_PAD_GPIO_6__CSU_CSU_INT_DEB (_MX6Q_PAD_GPIO_6__CSU_CSU_INT_DEB) ++#define MX6Q_PAD_GPIO_6__GPIO_1_6 (_MX6Q_PAD_GPIO_6__GPIO_1_6) ++#define MX6Q_PAD_GPIO_6__USDHC2_LCTL (_MX6Q_PAD_GPIO_6__USDHC2_LCTL | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) ++#define MX6Q_PAD_GPIO_6__MLB_MLBSIG (_MX6Q_PAD_GPIO_6__MLB_MLBSIG) ++ ++#define MX6Q_PAD_GPIO_2__ESAI1_FST (_MX6Q_PAD_GPIO_2__ESAI1_FST) ++#define MX6Q_PAD_GPIO_2__OBSERVE_MUX_OBSRV_INT_OUT2 (_MX6Q_PAD_GPIO_2__OBSERVE_MUX_OBSRV_INT_OUT2) ++#define MX6Q_PAD_GPIO_2__KPP_ROW_6 (_MX6Q_PAD_GPIO_2__KPP_ROW_6) ++#define MX6Q_PAD_GPIO_2__CCM_CCM_OUT_1 (_MX6Q_PAD_GPIO_2__CCM_CCM_OUT_1) ++#define MX6Q_PAD_GPIO_2__CSU_CSU_ALARM_AUT_0 (_MX6Q_PAD_GPIO_2__CSU_CSU_ALARM_AUT_0) ++#define MX6Q_PAD_GPIO_2__GPIO_1_2 (_MX6Q_PAD_GPIO_2__GPIO_1_2) ++#define MX6Q_PAD_GPIO_2__USDHC2_WP (_MX6Q_PAD_GPIO_2__USDHC2_WP | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) ++#define MX6Q_PAD_GPIO_2__MLB_MLBDAT (_MX6Q_PAD_GPIO_2__MLB_MLBDAT) ++ ++#define MX6Q_PAD_GPIO_4__ESAI1_HCKT (_MX6Q_PAD_GPIO_4__ESAI1_HCKT) ++#define MX6Q_PAD_GPIO_4__OBSERVE_MUX_OBSRV_INT_OUT3 (_MX6Q_PAD_GPIO_4__OBSERVE_MUX_OBSRV_INT_OUT3) ++#define MX6Q_PAD_GPIO_4__KPP_COL_7 (_MX6Q_PAD_GPIO_4__KPP_COL_7) ++#define MX6Q_PAD_GPIO_4__CCM_CCM_OUT_2 (_MX6Q_PAD_GPIO_4__CCM_CCM_OUT_2) ++#define MX6Q_PAD_GPIO_4__CSU_CSU_ALARM_AUT_1 (_MX6Q_PAD_GPIO_4__CSU_CSU_ALARM_AUT_1) ++#define MX6Q_PAD_GPIO_4__GPIO_1_4 (_MX6Q_PAD_GPIO_4__GPIO_1_4) ++#define MX6Q_PAD_GPIO_4__USDHC2_CD (_MX6Q_PAD_GPIO_4__USDHC2_CD | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) ++#define MX6Q_PAD_GPIO_4__OCOTP_CTRL_WRAPPER_FUSE_LATCHED (_MX6Q_PAD_GPIO_4__OCOTP_CTRL_WRAPPER_FUSE_LATCHED) ++ ++#define MX6Q_PAD_GPIO_5__ESAI1_TX2_RX3 (_MX6Q_PAD_GPIO_5__ESAI1_TX2_RX3) ++#define MX6Q_PAD_GPIO_5__OBSERVE_MUX_OBSRV_INT_OUT4 (_MX6Q_PAD_GPIO_5__OBSERVE_MUX_OBSRV_INT_OUT4) ++#define MX6Q_PAD_GPIO_5__KPP_ROW_7 (_MX6Q_PAD_GPIO_5__KPP_ROW_7) ++#define MX6Q_PAD_GPIO_5__CCM_CLKO (_MX6Q_PAD_GPIO_5__CCM_CLKO) ++#define MX6Q_PAD_GPIO_5__CSU_CSU_ALARM_AUT_2 (_MX6Q_PAD_GPIO_5__CSU_CSU_ALARM_AUT_2) ++#define MX6Q_PAD_GPIO_5__GPIO_1_5 (_MX6Q_PAD_GPIO_5__GPIO_1_5) ++#define MX6Q_PAD_GPIO_5__I2C3_SCL (_MX6Q_PAD_GPIO_5__I2C3_SCL | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL)) ++#define MX6Q_PAD_GPIO_5__CHEETAH_EVENTI (_MX6Q_PAD_GPIO_5__CHEETAH_EVENTI) ++ ++#define MX6Q_PAD_GPIO_7__ESAI1_TX4_RX1 (_MX6Q_PAD_GPIO_7__ESAI1_TX4_RX1) ++#define MX6Q_PAD_GPIO_7__ECSPI5_RDY (_MX6Q_PAD_GPIO_7__ECSPI5_RDY) ++#define MX6Q_PAD_GPIO_7__EPIT1_EPITO (_MX6Q_PAD_GPIO_7__EPIT1_EPITO) ++#define MX6Q_PAD_GPIO_7__CAN1_TXCAN (_MX6Q_PAD_GPIO_7__CAN1_TXCAN) ++#define MX6Q_PAD_GPIO_7__UART2_TXD (_MX6Q_PAD_GPIO_7__UART2_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) ++#define MX6Q_PAD_GPIO_7__UART2_RXD (_MX6Q_PAD_GPIO_7__UART2_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) ++#define MX6Q_PAD_GPIO_7__GPIO_1_7 (_MX6Q_PAD_GPIO_7__GPIO_1_7) ++#define MX6Q_PAD_GPIO_7__SPDIF_PLOCK (_MX6Q_PAD_GPIO_7__SPDIF_PLOCK) ++#define MX6Q_PAD_GPIO_7__USBOH3_OTGUSB_HOST_MODE (_MX6Q_PAD_GPIO_7__USBOH3_OTGUSB_HOST_MODE) ++ ++#define MX6Q_PAD_GPIO_8__ESAI1_TX5_RX0 (_MX6Q_PAD_GPIO_8__ESAI1_TX5_RX0) ++#define MX6Q_PAD_GPIO_8__ANATOP_ANATOP_32K_OUT (_MX6Q_PAD_GPIO_8__ANATOP_ANATOP_32K_OUT) ++#define MX6Q_PAD_GPIO_8__EPIT2_EPITO (_MX6Q_PAD_GPIO_8__EPIT2_EPITO) ++#define MX6Q_PAD_GPIO_8__CAN1_RXCAN (_MX6Q_PAD_GPIO_8__CAN1_RXCAN) ++#define MX6Q_PAD_GPIO_8__UART2_TXD (_MX6Q_PAD_GPIO_8__UART2_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) ++#define MX6Q_PAD_GPIO_8__UART2_RXD (_MX6Q_PAD_GPIO_8__UART2_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) ++#define MX6Q_PAD_GPIO_8__GPIO_1_8 (_MX6Q_PAD_GPIO_8__GPIO_1_8) ++#define MX6Q_PAD_GPIO_8__SPDIF_SRCLK (_MX6Q_PAD_GPIO_8__SPDIF_SRCLK) ++#define MX6Q_PAD_GPIO_8__USBOH3_OTGUSB_PWRCTL_WAKEUP (_MX6Q_PAD_GPIO_8__USBOH3_OTGUSB_PWRCTL_WAKEUP) ++ ++#define MX6Q_PAD_GPIO_16__ESAI1_TX3_RX2 (_MX6Q_PAD_GPIO_16__ESAI1_TX3_RX2) ++#define MX6Q_PAD_GPIO_16__ENET_1588_EVENT2_IN (_MX6Q_PAD_GPIO_16__ENET_1588_EVENT2_IN) ++#define MX6Q_PAD_GPIO_16__ENET_ANATOP_ETHERNET_REF_OUT (_MX6Q_PAD_GPIO_16__ENET_ANATOP_ETHERNET_REF_OUT) ++#define MX6Q_PAD_GPIO_16__USDHC1_LCTL (_MX6Q_PAD_GPIO_16__USDHC1_LCTL | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) ++#define MX6Q_PAD_GPIO_16__SPDIF_IN1 (_MX6Q_PAD_GPIO_16__SPDIF_IN1) ++#define MX6Q_PAD_GPIO_16__GPIO_7_11 (_MX6Q_PAD_GPIO_16__GPIO_7_11) ++#define MX6Q_PAD_GPIO_16__I2C3_SDA (_MX6Q_PAD_GPIO_16__I2C3_SDA | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL)) ++#define MX6Q_PAD_GPIO_16__SJC_DE_B (_MX6Q_PAD_GPIO_16__SJC_DE_B) ++ ++#define MX6Q_PAD_GPIO_17__ESAI1_TX0 (_MX6Q_PAD_GPIO_17__ESAI1_TX0) ++#define MX6Q_PAD_GPIO_17__ENET_1588_EVENT3_IN (_MX6Q_PAD_GPIO_17__ENET_1588_EVENT3_IN) ++#define MX6Q_PAD_GPIO_17__CCM_PMIC_RDY (_MX6Q_PAD_GPIO_17__CCM_PMIC_RDY) ++#define MX6Q_PAD_GPIO_17__SDMA_SDMA_EXT_EVENT_0 (_MX6Q_PAD_GPIO_17__SDMA_SDMA_EXT_EVENT_0) ++#define MX6Q_PAD_GPIO_17__SPDIF_OUT1 (_MX6Q_PAD_GPIO_17__SPDIF_OUT1) ++#define MX6Q_PAD_GPIO_17__GPIO_7_12 (_MX6Q_PAD_GPIO_17__GPIO_7_12) ++#define MX6Q_PAD_GPIO_17__SJC_JTAG_ACT (_MX6Q_PAD_GPIO_17__SJC_JTAG_ACT) ++ ++#define MX6Q_PAD_GPIO_18__ESAI1_TX1 (_MX6Q_PAD_GPIO_18__ESAI1_TX1) ++#define MX6Q_PAD_GPIO_18__ENET_RX_CLK (_MX6Q_PAD_GPIO_18__ENET_RX_CLK | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL)) ++#define MX6Q_PAD_GPIO_18__USDHC3_VSELECT (_MX6Q_PAD_GPIO_18__USDHC3_VSELECT | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) ++#define MX6Q_PAD_GPIO_18__SDMA_SDMA_EXT_EVENT_1 (_MX6Q_PAD_GPIO_18__SDMA_SDMA_EXT_EVENT_1) ++#define MX6Q_PAD_GPIO_18__ASRC_ASRC_EXT_CLK (_MX6Q_PAD_GPIO_18__ASRC_ASRC_EXT_CLK) ++#define MX6Q_PAD_GPIO_18__GPIO_7_13 (_MX6Q_PAD_GPIO_18__GPIO_7_13) ++#define MX6Q_PAD_GPIO_18__SNVS_HP_WRAPPER_SNVS_VIO_5_CTL (_MX6Q_PAD_GPIO_18__SNVS_HP_WRAPPER_SNVS_VIO_5_CTL) ++#define MX6Q_PAD_GPIO_18__SRC_SYSTEM_RST (_MX6Q_PAD_GPIO_18__SRC_SYSTEM_RST) ++ ++#define MX6Q_PAD_GPIO_19__KPP_COL_5 (_MX6Q_PAD_GPIO_19__KPP_COL_5) ++#define MX6Q_PAD_GPIO_19__ENET_1588_EVENT0_OUT (_MX6Q_PAD_GPIO_19__ENET_1588_EVENT0_OUT) ++#define MX6Q_PAD_GPIO_19__SPDIF_OUT1 (_MX6Q_PAD_GPIO_19__SPDIF_OUT1) ++#define MX6Q_PAD_GPIO_19__CCM_CLKO (_MX6Q_PAD_GPIO_19__CCM_CLKO) ++#define MX6Q_PAD_GPIO_19__ECSPI1_RDY (_MX6Q_PAD_GPIO_19__ECSPI1_RDY) ++#define MX6Q_PAD_GPIO_19__GPIO_4_5 (_MX6Q_PAD_GPIO_19__GPIO_4_5) ++#define MX6Q_PAD_GPIO_19__ENET_TX_ER (_MX6Q_PAD_GPIO_19__ENET_TX_ER | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL)) ++#define MX6Q_PAD_GPIO_19__SRC_INT_BOOT (_MX6Q_PAD_GPIO_19__SRC_INT_BOOT) ++ ++#define MX6Q_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK (_MX6Q_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK) ++#define MX6Q_PAD_CSI0_PIXCLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_12 (_MX6Q_PAD_CSI0_PIXCLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_12) ++#define MX6Q_PAD_CSI0_PIXCLK__SDMA_DEBUG_PC_0 (_MX6Q_PAD_CSI0_PIXCLK__SDMA_DEBUG_PC_0) ++#define MX6Q_PAD_CSI0_PIXCLK__GPIO_5_18 (_MX6Q_PAD_CSI0_PIXCLK__GPIO_5_18) ++#define MX6Q_PAD_CSI0_PIXCLK__MMDC_MMDC_DEBUG_29 (_MX6Q_PAD_CSI0_PIXCLK__MMDC_MMDC_DEBUG_29) ++#define MX6Q_PAD_CSI0_PIXCLK__CHEETAH_EVENTO (_MX6Q_PAD_CSI0_PIXCLK__CHEETAH_EVENTO) ++ ++#define MX6Q_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC (_MX6Q_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC) ++#define MX6Q_PAD_CSI0_MCLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_13 (_MX6Q_PAD_CSI0_MCLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_13) ++#define MX6Q_PAD_CSI0_MCLK__CCM_CLKO (_MX6Q_PAD_CSI0_MCLK__CCM_CLKO) ++#define MX6Q_PAD_CSI0_MCLK__SDMA_DEBUG_PC_1 (_MX6Q_PAD_CSI0_MCLK__SDMA_DEBUG_PC_1) ++#define MX6Q_PAD_CSI0_MCLK__GPIO_5_19 (_MX6Q_PAD_CSI0_MCLK__GPIO_5_19) ++#define MX6Q_PAD_CSI0_MCLK__MMDC_MMDC_DEBUG_30 (_MX6Q_PAD_CSI0_MCLK__MMDC_MMDC_DEBUG_30) ++#define MX6Q_PAD_CSI0_MCLK__CHEETAH_TRCTL (_MX6Q_PAD_CSI0_MCLK__CHEETAH_TRCTL) ++ ++#define MX6Q_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN (_MX6Q_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN) ++#define MX6Q_PAD_CSI0_DATA_EN__WEIM_WEIM_D_0 (_MX6Q_PAD_CSI0_DATA_EN__WEIM_WEIM_D_0) ++#define MX6Q_PAD_CSI0_DATA_EN__PCIE_CTRL_DIAG_STATUS_BUS_MUX_14 (_MX6Q_PAD_CSI0_DATA_EN__PCIE_CTRL_DIAG_STATUS_BUS_MUX_14) ++#define MX6Q_PAD_CSI0_DATA_EN__SDMA_DEBUG_PC_2 (_MX6Q_PAD_CSI0_DATA_EN__SDMA_DEBUG_PC_2) ++#define MX6Q_PAD_CSI0_DATA_EN__GPIO_5_20 (_MX6Q_PAD_CSI0_DATA_EN__GPIO_5_20) ++#define MX6Q_PAD_CSI0_DATA_EN__MMDC_MMDC_DEBUG_31 (_MX6Q_PAD_CSI0_DATA_EN__MMDC_MMDC_DEBUG_31) ++#define MX6Q_PAD_CSI0_DATA_EN__CHEETAH_TRCLK (_MX6Q_PAD_CSI0_DATA_EN__CHEETAH_TRCLK) ++ ++#define MX6Q_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC (_MX6Q_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC) ++#define MX6Q_PAD_CSI0_VSYNC__WEIM_WEIM_D_1 (_MX6Q_PAD_CSI0_VSYNC__WEIM_WEIM_D_1) ++#define MX6Q_PAD_CSI0_VSYNC__PCIE_CTRL_DIAG_STATUS_BUS_MUX_15 (_MX6Q_PAD_CSI0_VSYNC__PCIE_CTRL_DIAG_STATUS_BUS_MUX_15) ++#define MX6Q_PAD_CSI0_VSYNC__SDMA_DEBUG_PC_3 (_MX6Q_PAD_CSI0_VSYNC__SDMA_DEBUG_PC_3) ++#define MX6Q_PAD_CSI0_VSYNC__GPIO_5_21 (_MX6Q_PAD_CSI0_VSYNC__GPIO_5_21) ++#define MX6Q_PAD_CSI0_VSYNC__MMDC_MMDC_DEBUG_32 (_MX6Q_PAD_CSI0_VSYNC__MMDC_MMDC_DEBUG_32) ++#define MX6Q_PAD_CSI0_VSYNC__CHEETAH_TRACE_0 (_MX6Q_PAD_CSI0_VSYNC__CHEETAH_TRACE_0) ++ ++#define MX6Q_PAD_CSI0_DAT4__IPU1_CSI0_D_4 (_MX6Q_PAD_CSI0_DAT4__IPU1_CSI0_D_4) ++#define MX6Q_PAD_CSI0_DAT4__WEIM_WEIM_D_2 (_MX6Q_PAD_CSI0_DAT4__WEIM_WEIM_D_2) ++#define MX6Q_PAD_CSI0_DAT4__ECSPI1_SCLK (_MX6Q_PAD_CSI0_DAT4__ECSPI1_SCLK) ++#define MX6Q_PAD_CSI0_DAT4__KPP_COL_5 (_MX6Q_PAD_CSI0_DAT4__KPP_COL_5) ++#define MX6Q_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC (_MX6Q_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC) ++#define MX6Q_PAD_CSI0_DAT4__GPIO_5_22 (_MX6Q_PAD_CSI0_DAT4__GPIO_5_22) ++#define MX6Q_PAD_CSI0_DAT4__MMDC_MMDC_DEBUG_43 (_MX6Q_PAD_CSI0_DAT4__MMDC_MMDC_DEBUG_43) ++#define MX6Q_PAD_CSI0_DAT4__CHEETAH_TRACE_1 (_MX6Q_PAD_CSI0_DAT4__CHEETAH_TRACE_1) ++ ++#define MX6Q_PAD_CSI0_DAT5__IPU1_CSI0_D_5 (_MX6Q_PAD_CSI0_DAT5__IPU1_CSI0_D_5) ++#define MX6Q_PAD_CSI0_DAT5__WEIM_WEIM_D_3 (_MX6Q_PAD_CSI0_DAT5__WEIM_WEIM_D_3) ++#define MX6Q_PAD_CSI0_DAT5__ECSPI1_MOSI (_MX6Q_PAD_CSI0_DAT5__ECSPI1_MOSI) ++#define MX6Q_PAD_CSI0_DAT5__KPP_ROW_5 (_MX6Q_PAD_CSI0_DAT5__KPP_ROW_5) ++#define MX6Q_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD (_MX6Q_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD) ++#define MX6Q_PAD_CSI0_DAT5__GPIO_5_23 (_MX6Q_PAD_CSI0_DAT5__GPIO_5_23) ++#define MX6Q_PAD_CSI0_DAT5__MMDC_MMDC_DEBUG_44 (_MX6Q_PAD_CSI0_DAT5__MMDC_MMDC_DEBUG_44) ++#define MX6Q_PAD_CSI0_DAT5__CHEETAH_TRACE_2 (_MX6Q_PAD_CSI0_DAT5__CHEETAH_TRACE_2) ++ ++#define MX6Q_PAD_CSI0_DAT6__IPU1_CSI0_D_6 (_MX6Q_PAD_CSI0_DAT6__IPU1_CSI0_D_6) ++#define MX6Q_PAD_CSI0_DAT6__WEIM_WEIM_D_4 (_MX6Q_PAD_CSI0_DAT6__WEIM_WEIM_D_4) ++#define MX6Q_PAD_CSI0_DAT6__ECSPI1_MISO (_MX6Q_PAD_CSI0_DAT6__ECSPI1_MISO) ++#define MX6Q_PAD_CSI0_DAT6__KPP_COL_6 (_MX6Q_PAD_CSI0_DAT6__KPP_COL_6) ++#define MX6Q_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS (_MX6Q_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS) ++#define MX6Q_PAD_CSI0_DAT6__GPIO_5_24 (_MX6Q_PAD_CSI0_DAT6__GPIO_5_24) ++#define MX6Q_PAD_CSI0_DAT6__MMDC_MMDC_DEBUG_45 (_MX6Q_PAD_CSI0_DAT6__MMDC_MMDC_DEBUG_45) ++#define MX6Q_PAD_CSI0_DAT6__CHEETAH_TRACE_3 (_MX6Q_PAD_CSI0_DAT6__CHEETAH_TRACE_3) ++ ++#define MX6Q_PAD_CSI0_DAT7__IPU1_CSI0_D_7 (_MX6Q_PAD_CSI0_DAT7__IPU1_CSI0_D_7) ++#define MX6Q_PAD_CSI0_DAT7__WEIM_WEIM_D_5 (_MX6Q_PAD_CSI0_DAT7__WEIM_WEIM_D_5) ++#define MX6Q_PAD_CSI0_DAT7__ECSPI1_SS0 (_MX6Q_PAD_CSI0_DAT7__ECSPI1_SS0) ++#define MX6Q_PAD_CSI0_DAT7__KPP_ROW_6 (_MX6Q_PAD_CSI0_DAT7__KPP_ROW_6) ++#define MX6Q_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD (_MX6Q_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD) ++#define MX6Q_PAD_CSI0_DAT7__GPIO_5_25 (_MX6Q_PAD_CSI0_DAT7__GPIO_5_25) ++#define MX6Q_PAD_CSI0_DAT7__MMDC_MMDC_DEBUG_46 (_MX6Q_PAD_CSI0_DAT7__MMDC_MMDC_DEBUG_46) ++#define MX6Q_PAD_CSI0_DAT7__CHEETAH_TRACE_4 (_MX6Q_PAD_CSI0_DAT7__CHEETAH_TRACE_4) ++ ++#define MX6Q_PAD_CSI0_DAT8__IPU1_CSI0_D_8 (_MX6Q_PAD_CSI0_DAT8__IPU1_CSI0_D_8) ++#define MX6Q_PAD_CSI0_DAT8__WEIM_WEIM_D_6 (_MX6Q_PAD_CSI0_DAT8__WEIM_WEIM_D_6) ++#define MX6Q_PAD_CSI0_DAT8__ECSPI2_SCLK (_MX6Q_PAD_CSI0_DAT8__ECSPI2_SCLK) ++#define MX6Q_PAD_CSI0_DAT8__KPP_COL_7 (_MX6Q_PAD_CSI0_DAT8__KPP_COL_7) ++#define MX6Q_PAD_CSI0_DAT8__I2C1_SDA (_MX6Q_PAD_CSI0_DAT8__I2C1_SDA | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL)) ++#define MX6Q_PAD_CSI0_DAT8__GPIO_5_26 (_MX6Q_PAD_CSI0_DAT8__GPIO_5_26) ++#define MX6Q_PAD_CSI0_DAT8__MMDC_MMDC_DEBUG_47 (_MX6Q_PAD_CSI0_DAT8__MMDC_MMDC_DEBUG_47) ++#define MX6Q_PAD_CSI0_DAT8__CHEETAH_TRACE_5 (_MX6Q_PAD_CSI0_DAT8__CHEETAH_TRACE_5) ++ ++#define MX6Q_PAD_CSI0_DAT9__IPU1_CSI0_D_9 (_MX6Q_PAD_CSI0_DAT9__IPU1_CSI0_D_9) ++#define MX6Q_PAD_CSI0_DAT9__WEIM_WEIM_D_7 (_MX6Q_PAD_CSI0_DAT9__WEIM_WEIM_D_7) ++#define MX6Q_PAD_CSI0_DAT9__ECSPI2_MOSI (_MX6Q_PAD_CSI0_DAT9__ECSPI2_MOSI) ++#define MX6Q_PAD_CSI0_DAT9__KPP_ROW_7 (_MX6Q_PAD_CSI0_DAT9__KPP_ROW_7) ++#define MX6Q_PAD_CSI0_DAT9__I2C1_SCL (_MX6Q_PAD_CSI0_DAT9__I2C1_SCL | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL)) ++#define MX6Q_PAD_CSI0_DAT9__GPIO_5_27 (_MX6Q_PAD_CSI0_DAT9__GPIO_5_27) ++#define MX6Q_PAD_CSI0_DAT9__MMDC_MMDC_DEBUG_48 (_MX6Q_PAD_CSI0_DAT9__MMDC_MMDC_DEBUG_48) ++#define MX6Q_PAD_CSI0_DAT9__CHEETAH_TRACE_6 (_MX6Q_PAD_CSI0_DAT9__CHEETAH_TRACE_6) ++ ++#define MX6Q_PAD_CSI0_DAT10__IPU1_CSI0_D_10 (_MX6Q_PAD_CSI0_DAT10__IPU1_CSI0_D_10) ++#define MX6Q_PAD_CSI0_DAT10__AUDMUX_AUD3_RXC (_MX6Q_PAD_CSI0_DAT10__AUDMUX_AUD3_RXC) ++#define MX6Q_PAD_CSI0_DAT10__ECSPI2_MISO (_MX6Q_PAD_CSI0_DAT10__ECSPI2_MISO) ++#define MX6Q_PAD_CSI0_DAT10__UART1_TXD (_MX6Q_PAD_CSI0_DAT10__UART1_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) ++#define MX6Q_PAD_CSI0_DAT10__UART1_RXD (_MX6Q_PAD_CSI0_DAT10__UART1_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) ++#define MX6Q_PAD_CSI0_DAT10__SDMA_DEBUG_PC_4 (_MX6Q_PAD_CSI0_DAT10__SDMA_DEBUG_PC_4) ++#define MX6Q_PAD_CSI0_DAT10__GPIO_5_28 (_MX6Q_PAD_CSI0_DAT10__GPIO_5_28) ++#define MX6Q_PAD_CSI0_DAT10__MMDC_MMDC_DEBUG_33 (_MX6Q_PAD_CSI0_DAT10__MMDC_MMDC_DEBUG_33) ++#define MX6Q_PAD_CSI0_DAT10__CHEETAH_TRACE_7 (_MX6Q_PAD_CSI0_DAT10__CHEETAH_TRACE_7) ++ ++#define MX6Q_PAD_CSI0_DAT11__IPU1_CSI0_D_11 (_MX6Q_PAD_CSI0_DAT11__IPU1_CSI0_D_11) ++#define MX6Q_PAD_CSI0_DAT11__AUDMUX_AUD3_RXFS (_MX6Q_PAD_CSI0_DAT11__AUDMUX_AUD3_RXFS) ++#define MX6Q_PAD_CSI0_DAT11__ECSPI2_SS0 (_MX6Q_PAD_CSI0_DAT11__ECSPI2_SS0) ++#define MX6Q_PAD_CSI0_DAT11__UART1_TXD (_MX6Q_PAD_CSI0_DAT11__UART1_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) ++#define MX6Q_PAD_CSI0_DAT11__UART1_RXD (_MX6Q_PAD_CSI0_DAT11__UART1_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) ++#define MX6Q_PAD_CSI0_DAT11__SDMA_DEBUG_PC_5 (_MX6Q_PAD_CSI0_DAT11__SDMA_DEBUG_PC_5) ++#define MX6Q_PAD_CSI0_DAT11__GPIO_5_29 (_MX6Q_PAD_CSI0_DAT11__GPIO_5_29) ++#define MX6Q_PAD_CSI0_DAT11__MMDC_MMDC_DEBUG_34 (_MX6Q_PAD_CSI0_DAT11__MMDC_MMDC_DEBUG_34) ++#define MX6Q_PAD_CSI0_DAT11__CHEETAH_TRACE_8 (_MX6Q_PAD_CSI0_DAT11__CHEETAH_TRACE_8) ++ ++#define MX6Q_PAD_CSI0_DAT12__IPU1_CSI0_D_12 (_MX6Q_PAD_CSI0_DAT12__IPU1_CSI0_D_12) ++#define MX6Q_PAD_CSI0_DAT12__WEIM_WEIM_D_8 (_MX6Q_PAD_CSI0_DAT12__WEIM_WEIM_D_8) ++#define MX6Q_PAD_CSI0_DAT12__PCIE_CTRL_DIAG_STATUS_BUS_MUX_16 (_MX6Q_PAD_CSI0_DAT12__PCIE_CTRL_DIAG_STATUS_BUS_MUX_16) ++#define MX6Q_PAD_CSI0_DAT12__UART4_TXD (_MX6Q_PAD_CSI0_DAT12__UART4_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) ++#define MX6Q_PAD_CSI0_DAT12__UART4_RXD (_MX6Q_PAD_CSI0_DAT12__UART4_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) ++#define MX6Q_PAD_CSI0_DAT12__SDMA_DEBUG_PC_6 (_MX6Q_PAD_CSI0_DAT12__SDMA_DEBUG_PC_6) ++#define MX6Q_PAD_CSI0_DAT12__GPIO_5_30 (_MX6Q_PAD_CSI0_DAT12__GPIO_5_30) ++#define MX6Q_PAD_CSI0_DAT12__MMDC_MMDC_DEBUG_35 (_MX6Q_PAD_CSI0_DAT12__MMDC_MMDC_DEBUG_35) ++#define MX6Q_PAD_CSI0_DAT12__CHEETAH_TRACE_9 (_MX6Q_PAD_CSI0_DAT12__CHEETAH_TRACE_9) ++ ++#define MX6Q_PAD_CSI0_DAT13__IPU1_CSI0_D_13 (_MX6Q_PAD_CSI0_DAT13__IPU1_CSI0_D_13) ++#define MX6Q_PAD_CSI0_DAT13__WEIM_WEIM_D_9 (_MX6Q_PAD_CSI0_DAT13__WEIM_WEIM_D_9) ++#define MX6Q_PAD_CSI0_DAT13__PCIE_CTRL_DIAG_STATUS_BUS_MUX_17 (_MX6Q_PAD_CSI0_DAT13__PCIE_CTRL_DIAG_STATUS_BUS_MUX_17) ++#define MX6Q_PAD_CSI0_DAT13__UART4_TXD (_MX6Q_PAD_CSI0_DAT13__UART4_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) ++#define MX6Q_PAD_CSI0_DAT13__UART4_RXD (_MX6Q_PAD_CSI0_DAT13__UART4_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) ++#define MX6Q_PAD_CSI0_DAT13__SDMA_DEBUG_PC_7 (_MX6Q_PAD_CSI0_DAT13__SDMA_DEBUG_PC_7) ++#define MX6Q_PAD_CSI0_DAT13__GPIO_5_31 (_MX6Q_PAD_CSI0_DAT13__GPIO_5_31) ++#define MX6Q_PAD_CSI0_DAT13__MMDC_MMDC_DEBUG_36 (_MX6Q_PAD_CSI0_DAT13__MMDC_MMDC_DEBUG_36) ++#define MX6Q_PAD_CSI0_DAT13__CHEETAH_TRACE_10 (_MX6Q_PAD_CSI0_DAT13__CHEETAH_TRACE_10) ++ ++#define MX6Q_PAD_CSI0_DAT14__IPU1_CSI0_D_14 (_MX6Q_PAD_CSI0_DAT14__IPU1_CSI0_D_14) ++#define MX6Q_PAD_CSI0_DAT14__WEIM_WEIM_D_10 (_MX6Q_PAD_CSI0_DAT14__WEIM_WEIM_D_10) ++#define MX6Q_PAD_CSI0_DAT14__PCIE_CTRL_DIAG_STATUS_BUS_MUX_18 (_MX6Q_PAD_CSI0_DAT14__PCIE_CTRL_DIAG_STATUS_BUS_MUX_18) ++#define MX6Q_PAD_CSI0_DAT14__UART5_TXD (_MX6Q_PAD_CSI0_DAT14__UART5_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) ++#define MX6Q_PAD_CSI0_DAT14__UART5_RXD (_MX6Q_PAD_CSI0_DAT14__UART5_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) ++#define MX6Q_PAD_CSI0_DAT14__SDMA_DEBUG_PC_8 (_MX6Q_PAD_CSI0_DAT14__SDMA_DEBUG_PC_8) ++#define MX6Q_PAD_CSI0_DAT14__GPIO_6_0 (_MX6Q_PAD_CSI0_DAT14__GPIO_6_0) ++#define MX6Q_PAD_CSI0_DAT14__MMDC_MMDC_DEBUG_37 (_MX6Q_PAD_CSI0_DAT14__MMDC_MMDC_DEBUG_37) ++#define MX6Q_PAD_CSI0_DAT14__CHEETAH_TRACE_11 (_MX6Q_PAD_CSI0_DAT14__CHEETAH_TRACE_11) ++ ++#define MX6Q_PAD_CSI0_DAT15__IPU1_CSI0_D_15 (_MX6Q_PAD_CSI0_DAT15__IPU1_CSI0_D_15) ++#define MX6Q_PAD_CSI0_DAT15__WEIM_WEIM_D_11 (_MX6Q_PAD_CSI0_DAT15__WEIM_WEIM_D_11) ++#define MX6Q_PAD_CSI0_DAT15__PCIE_CTRL_DIAG_STATUS_BUS_MUX_19 (_MX6Q_PAD_CSI0_DAT15__PCIE_CTRL_DIAG_STATUS_BUS_MUX_19) ++#define MX6Q_PAD_CSI0_DAT15__UART5_TXD (_MX6Q_PAD_CSI0_DAT15__UART5_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) ++#define MX6Q_PAD_CSI0_DAT15__UART5_RXD (_MX6Q_PAD_CSI0_DAT15__UART5_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) ++#define MX6Q_PAD_CSI0_DAT15__SDMA_DEBUG_PC_9 (_MX6Q_PAD_CSI0_DAT15__SDMA_DEBUG_PC_9) ++#define MX6Q_PAD_CSI0_DAT15__GPIO_6_1 (_MX6Q_PAD_CSI0_DAT15__GPIO_6_1) ++#define MX6Q_PAD_CSI0_DAT15__MMDC_MMDC_DEBUG_38 (_MX6Q_PAD_CSI0_DAT15__MMDC_MMDC_DEBUG_38) ++#define MX6Q_PAD_CSI0_DAT15__CHEETAH_TRACE_12 (_MX6Q_PAD_CSI0_DAT15__CHEETAH_TRACE_12) ++ ++#define MX6Q_PAD_CSI0_DAT16__IPU1_CSI0_D_16 (_MX6Q_PAD_CSI0_DAT16__IPU1_CSI0_D_16) ++#define MX6Q_PAD_CSI0_DAT16__WEIM_WEIM_D_12 (_MX6Q_PAD_CSI0_DAT16__WEIM_WEIM_D_12) ++#define MX6Q_PAD_CSI0_DAT16__PCIE_CTRL_DIAG_STATUS_BUS_MUX_20 (_MX6Q_PAD_CSI0_DAT16__PCIE_CTRL_DIAG_STATUS_BUS_MUX_20) ++#define MX6Q_PAD_CSI0_DAT16__UART4_CTS (_MX6Q_PAD_CSI0_DAT16__UART4_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) ++#define MX6Q_PAD_CSI0_DAT16__UART4_RTS (_MX6Q_PAD_CSI0_DAT16__UART4_RTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) ++#define MX6Q_PAD_CSI0_DAT16__SDMA_DEBUG_PC_10 (_MX6Q_PAD_CSI0_DAT16__SDMA_DEBUG_PC_10) ++#define MX6Q_PAD_CSI0_DAT16__GPIO_6_2 (_MX6Q_PAD_CSI0_DAT16__GPIO_6_2) ++#define MX6Q_PAD_CSI0_DAT16__MMDC_MMDC_DEBUG_39 (_MX6Q_PAD_CSI0_DAT16__MMDC_MMDC_DEBUG_39) ++#define MX6Q_PAD_CSI0_DAT16__CHEETAH_TRACE_13 (_MX6Q_PAD_CSI0_DAT16__CHEETAH_TRACE_13) ++ ++#define MX6Q_PAD_CSI0_DAT17__IPU1_CSI0_D_17 (_MX6Q_PAD_CSI0_DAT17__IPU1_CSI0_D_17) ++#define MX6Q_PAD_CSI0_DAT17__WEIM_WEIM_D_13 (_MX6Q_PAD_CSI0_DAT17__WEIM_WEIM_D_13) ++#define MX6Q_PAD_CSI0_DAT17__PCIE_CTRL_DIAG_STATUS_BUS_MUX_21 (_MX6Q_PAD_CSI0_DAT17__PCIE_CTRL_DIAG_STATUS_BUS_MUX_21) ++#define MX6Q_PAD_CSI0_DAT17__UART4_CTS (_MX6Q_PAD_CSI0_DAT17__UART4_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) ++#define MX6Q_PAD_CSI0_DAT17__SDMA_DEBUG_PC_11 (_MX6Q_PAD_CSI0_DAT17__SDMA_DEBUG_PC_11) ++#define MX6Q_PAD_CSI0_DAT17__GPIO_6_3 (_MX6Q_PAD_CSI0_DAT17__GPIO_6_3) ++#define MX6Q_PAD_CSI0_DAT17__MMDC_MMDC_DEBUG_40 (_MX6Q_PAD_CSI0_DAT17__MMDC_MMDC_DEBUG_40) ++#define MX6Q_PAD_CSI0_DAT17__CHEETAH_TRACE_14 (_MX6Q_PAD_CSI0_DAT17__CHEETAH_TRACE_14) ++ ++#define MX6Q_PAD_CSI0_DAT18__IPU1_CSI0_D_18 (_MX6Q_PAD_CSI0_DAT18__IPU1_CSI0_D_18) ++#define MX6Q_PAD_CSI0_DAT18__WEIM_WEIM_D_14 (_MX6Q_PAD_CSI0_DAT18__WEIM_WEIM_D_14) ++#define MX6Q_PAD_CSI0_DAT18__PCIE_CTRL_DIAG_STATUS_BUS_MUX_22 (_MX6Q_PAD_CSI0_DAT18__PCIE_CTRL_DIAG_STATUS_BUS_MUX_22) ++#define MX6Q_PAD_CSI0_DAT18__UART5_CTS (_MX6Q_PAD_CSI0_DAT18__UART5_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) ++#define MX6Q_PAD_CSI0_DAT18__UART5_RTS (_MX6Q_PAD_CSI0_DAT18__UART5_RTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) ++#define MX6Q_PAD_CSI0_DAT18__SDMA_DEBUG_PC_12 (_MX6Q_PAD_CSI0_DAT18__SDMA_DEBUG_PC_12) ++#define MX6Q_PAD_CSI0_DAT18__GPIO_6_4 (_MX6Q_PAD_CSI0_DAT18__GPIO_6_4) ++#define MX6Q_PAD_CSI0_DAT18__MMDC_MMDC_DEBUG_41 (_MX6Q_PAD_CSI0_DAT18__MMDC_MMDC_DEBUG_41) ++#define MX6Q_PAD_CSI0_DAT18__CHEETAH_TRACE_15 (_MX6Q_PAD_CSI0_DAT18__CHEETAH_TRACE_15) ++ ++#define MX6Q_PAD_CSI0_DAT19__IPU1_CSI0_D_19 (_MX6Q_PAD_CSI0_DAT19__IPU1_CSI0_D_19) ++#define MX6Q_PAD_CSI0_DAT19__WEIM_WEIM_D_15 (_MX6Q_PAD_CSI0_DAT19__WEIM_WEIM_D_15) ++#define MX6Q_PAD_CSI0_DAT19__PCIE_CTRL_DIAG_STATUS_BUS_MUX_23 (_MX6Q_PAD_CSI0_DAT19__PCIE_CTRL_DIAG_STATUS_BUS_MUX_23) ++#define MX6Q_PAD_CSI0_DAT19__UART5_CTS (_MX6Q_PAD_CSI0_DAT19__UART5_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) ++#define MX6Q_PAD_CSI0_DAT19__SDMA_DEBUG_PC_13 (_MX6Q_PAD_CSI0_DAT19__SDMA_DEBUG_PC_13) ++#define MX6Q_PAD_CSI0_DAT19__GPIO_6_5 (_MX6Q_PAD_CSI0_DAT19__GPIO_6_5) ++#define MX6Q_PAD_CSI0_DAT19__MMDC_MMDC_DEBUG_42 (_MX6Q_PAD_CSI0_DAT19__MMDC_MMDC_DEBUG_42) ++#define MX6Q_PAD_CSI0_DAT19__ANATOP_ANATOP_TESTO_9 (_MX6Q_PAD_CSI0_DAT19__ANATOP_ANATOP_TESTO_9) ++ ++#define MX6Q_PAD_JTAG_TMS__SJC_TMS (_MX6Q_PAD_JTAG_TMS__SJC_TMS) ++ ++#define MX6Q_PAD_JTAG_MOD__SJC_MOD (_MX6Q_PAD_JTAG_MOD__SJC_MOD) ++ ++#define MX6Q_PAD_JTAG_TRSTB__SJC_TRSTB (_MX6Q_PAD_JTAG_TRSTB__SJC_TRSTB) ++ ++#define MX6Q_PAD_JTAG_TDI__SJC_TDI (_MX6Q_PAD_JTAG_TDI__SJC_TDI) ++ ++#define MX6Q_PAD_JTAG_TCK__SJC_TCK (_MX6Q_PAD_JTAG_TCK__SJC_TCK) ++ ++#define MX6Q_PAD_JTAG_TDO__SJC_TDO (_MX6Q_PAD_JTAG_TDO__SJC_TDO) ++ ++#define MX6Q_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 (_MX6Q_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3) ++ ++#define MX6Q_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 (_MX6Q_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2) ++ ++#define MX6Q_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK (_MX6Q_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK) ++ ++#define MX6Q_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 (_MX6Q_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1) ++ ++#define MX6Q_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 (_MX6Q_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0) ++ ++#define MX6Q_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 (_MX6Q_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3) ++ ++#define MX6Q_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK (_MX6Q_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK) ++ ++#define MX6Q_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 (_MX6Q_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2) ++ ++#define MX6Q_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 (_MX6Q_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1) ++ ++#define MX6Q_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 (_MX6Q_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0) ++ ++#define MX6Q_PAD_TAMPER__SNVS_LP_WRAPPER_SNVS_TD1 (_MX6Q_PAD_TAMPER__SNVS_LP_WRAPPER_SNVS_TD1) ++ ++#define MX6Q_PAD_PMIC_ON_REQ__SNVS_LP_WRAPPER_SNVS_WAKEUP_ALARM (_MX6Q_PAD_PMIC_ON_REQ__SNVS_LP_WRAPPER_SNVS_WAKEUP_ALARM) ++ ++#define MX6Q_PAD_PMIC_STBY_REQ__CCM_PMIC_VSTBY_REQ (_MX6Q_PAD_PMIC_STBY_REQ__CCM_PMIC_VSTBY_REQ) ++ ++#define MX6Q_PAD_POR_B__SRC_POR_B (_MX6Q_PAD_POR_B__SRC_POR_B) ++ ++#define MX6Q_PAD_BOOT_MODE1__SRC_BOOT_MODE_1 (_MX6Q_PAD_BOOT_MODE1__SRC_BOOT_MODE_1) ++ ++#define MX6Q_PAD_RESET_IN_B__SRC_RESET_B (_MX6Q_PAD_RESET_IN_B__SRC_RESET_B) ++ ++#define MX6Q_PAD_BOOT_MODE0__SRC_BOOT_MODE_0 (_MX6Q_PAD_BOOT_MODE0__SRC_BOOT_MODE_0) ++ ++#define MX6Q_PAD_TEST_MODE__TCU_TEST_MODE (_MX6Q_PAD_TEST_MODE__TCU_TEST_MODE) ++ ++#define MX6Q_PAD_SD3_DAT7__USDHC3_DAT7 (_MX6Q_PAD_SD3_DAT7__USDHC3_DAT7 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) ++#define MX6Q_PAD_SD3_DAT7__UART1_TXD (_MX6Q_PAD_SD3_DAT7__UART1_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) ++#define MX6Q_PAD_SD3_DAT7__UART1_RXD (_MX6Q_PAD_SD3_DAT7__UART1_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) ++#define MX6Q_PAD_SD3_DAT7__PCIE_CTRL_DIAG_STATUS_BUS_MUX_24 (_MX6Q_PAD_SD3_DAT7__PCIE_CTRL_DIAG_STATUS_BUS_MUX_24) ++#define MX6Q_PAD_SD3_DAT7__USBOH3_UH3_DFD_OUT_0 (_MX6Q_PAD_SD3_DAT7__USBOH3_UH3_DFD_OUT_0) ++#define MX6Q_PAD_SD3_DAT7__USBOH3_UH2_DFD_OUT_0 (_MX6Q_PAD_SD3_DAT7__USBOH3_UH2_DFD_OUT_0) ++#define MX6Q_PAD_SD3_DAT7__GPIO_6_17 (_MX6Q_PAD_SD3_DAT7__GPIO_6_17) ++#define MX6Q_PAD_SD3_DAT7__MIPI_CORE_DPHY_TEST_IN_12 (_MX6Q_PAD_SD3_DAT7__MIPI_CORE_DPHY_TEST_IN_12) ++#define MX6Q_PAD_SD3_DAT7__ANATOP_USBPHY2_TSTO_PLL_CLK20DIV (_MX6Q_PAD_SD3_DAT7__ANATOP_USBPHY2_TSTO_PLL_CLK20DIV) ++ ++#define MX6Q_PAD_SD3_DAT6__USDHC3_DAT6 (_MX6Q_PAD_SD3_DAT6__USDHC3_DAT6 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) ++#define MX6Q_PAD_SD3_DAT6__UART1_TXD (_MX6Q_PAD_SD3_DAT6__UART1_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) ++#define MX6Q_PAD_SD3_DAT6__UART1_RXD (_MX6Q_PAD_SD3_DAT6__UART1_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) ++#define MX6Q_PAD_SD3_DAT6__PCIE_CTRL_DIAG_STATUS_BUS_MUX_25 (_MX6Q_PAD_SD3_DAT6__PCIE_CTRL_DIAG_STATUS_BUS_MUX_25) ++#define MX6Q_PAD_SD3_DAT6__USBOH3_UH3_DFD_OUT_1 (_MX6Q_PAD_SD3_DAT6__USBOH3_UH3_DFD_OUT_1) ++#define MX6Q_PAD_SD3_DAT6__USBOH3_UH2_DFD_OUT_1 (_MX6Q_PAD_SD3_DAT6__USBOH3_UH2_DFD_OUT_1) ++#define MX6Q_PAD_SD3_DAT6__GPIO_6_18 (_MX6Q_PAD_SD3_DAT6__GPIO_6_18) ++#define MX6Q_PAD_SD3_DAT6__MIPI_CORE_DPHY_TEST_IN_13 (_MX6Q_PAD_SD3_DAT6__MIPI_CORE_DPHY_TEST_IN_13) ++#define MX6Q_PAD_SD3_DAT6__ANATOP_ANATOP_TESTO_10 (_MX6Q_PAD_SD3_DAT6__ANATOP_ANATOP_TESTO_10) ++ ++#define MX6Q_PAD_SD3_DAT5__USDHC3_DAT5 (_MX6Q_PAD_SD3_DAT5__USDHC3_DAT5 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) ++#define MX6Q_PAD_SD3_DAT5__UART2_TXD (_MX6Q_PAD_SD3_DAT5__UART2_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) ++#define MX6Q_PAD_SD3_DAT5__UART2_RXD (_MX6Q_PAD_SD3_DAT5__UART2_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) ++#define MX6Q_PAD_SD3_DAT5__PCIE_CTRL_DIAG_STATUS_BUS_MUX_26 (_MX6Q_PAD_SD3_DAT5__PCIE_CTRL_DIAG_STATUS_BUS_MUX_26) ++#define MX6Q_PAD_SD3_DAT5__USBOH3_UH3_DFD_OUT_2 (_MX6Q_PAD_SD3_DAT5__USBOH3_UH3_DFD_OUT_2) ++#define MX6Q_PAD_SD3_DAT5__USBOH3_UH2_DFD_OUT_2 (_MX6Q_PAD_SD3_DAT5__USBOH3_UH2_DFD_OUT_2) ++#define MX6Q_PAD_SD3_DAT5__GPIO_7_0 (_MX6Q_PAD_SD3_DAT5__GPIO_7_0) ++#define MX6Q_PAD_SD3_DAT5__MIPI_CORE_DPHY_TEST_IN_14 (_MX6Q_PAD_SD3_DAT5__MIPI_CORE_DPHY_TEST_IN_14) ++#define MX6Q_PAD_SD3_DAT5__ANATOP_ANATOP_TESTO_11 (_MX6Q_PAD_SD3_DAT5__ANATOP_ANATOP_TESTO_11) ++ ++#define MX6Q_PAD_SD3_DAT4__USDHC3_DAT4 (_MX6Q_PAD_SD3_DAT4__USDHC3_DAT4 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) ++#define MX6Q_PAD_SD3_DAT4__UART2_TXD (_MX6Q_PAD_SD3_DAT4__UART2_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) ++#define MX6Q_PAD_SD3_DAT4__UART2_RXD (_MX6Q_PAD_SD3_DAT4__UART2_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) ++#define MX6Q_PAD_SD3_DAT4__PCIE_CTRL_DIAG_STATUS_BUS_MUX_27 (_MX6Q_PAD_SD3_DAT4__PCIE_CTRL_DIAG_STATUS_BUS_MUX_27) ++#define MX6Q_PAD_SD3_DAT4__USBOH3_UH3_DFD_OUT_3 (_MX6Q_PAD_SD3_DAT4__USBOH3_UH3_DFD_OUT_3) ++#define MX6Q_PAD_SD3_DAT4__USBOH3_UH2_DFD_OUT_3 (_MX6Q_PAD_SD3_DAT4__USBOH3_UH2_DFD_OUT_3) ++#define MX6Q_PAD_SD3_DAT4__GPIO_7_1 (_MX6Q_PAD_SD3_DAT4__GPIO_7_1) ++#define MX6Q_PAD_SD3_DAT4__MIPI_CORE_DPHY_TEST_IN_15 (_MX6Q_PAD_SD3_DAT4__MIPI_CORE_DPHY_TEST_IN_15) ++#define MX6Q_PAD_SD3_DAT4__ANATOP_ANATOP_TESTO_12 (_MX6Q_PAD_SD3_DAT4__ANATOP_ANATOP_TESTO_12) ++ ++#define MX6Q_PAD_SD3_CMD__USDHC3_CMD (_MX6Q_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) ++#define MX6Q_PAD_SD3_CMD__UART2_CTS (_MX6Q_PAD_SD3_CMD__UART2_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) ++#define MX6Q_PAD_SD3_CMD__CAN1_TXCAN (_MX6Q_PAD_SD3_CMD__CAN1_TXCAN) ++#define MX6Q_PAD_SD3_CMD__USBOH3_UH3_DFD_OUT_4 (_MX6Q_PAD_SD3_CMD__USBOH3_UH3_DFD_OUT_4) ++#define MX6Q_PAD_SD3_CMD__USBOH3_UH2_DFD_OUT_4 (_MX6Q_PAD_SD3_CMD__USBOH3_UH2_DFD_OUT_4) ++#define MX6Q_PAD_SD3_CMD__GPIO_7_2 (_MX6Q_PAD_SD3_CMD__GPIO_7_2) ++#define MX6Q_PAD_SD3_CMD__MIPI_CORE_DPHY_TEST_IN_16 (_MX6Q_PAD_SD3_CMD__MIPI_CORE_DPHY_TEST_IN_16) ++#define MX6Q_PAD_SD3_CMD__ANATOP_ANATOP_TESTO_13 (_MX6Q_PAD_SD3_CMD__ANATOP_ANATOP_TESTO_13) ++ ++#define MX6Q_PAD_SD3_CLK__USDHC3_CLK (_MX6Q_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) ++#define MX6Q_PAD_SD3_CLK__UART2_CTS (_MX6Q_PAD_SD3_CLK__UART2_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) ++#define MX6Q_PAD_SD3_CLK__UART2_RTS (_MX6Q_PAD_SD3_CLK__UART2_RTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) ++#define MX6Q_PAD_SD3_CLK__CAN1_RXCAN (_MX6Q_PAD_SD3_CLK__CAN1_RXCAN) ++#define MX6Q_PAD_SD3_CLK__USBOH3_UH3_DFD_OUT_5 (_MX6Q_PAD_SD3_CLK__USBOH3_UH3_DFD_OUT_5) ++#define MX6Q_PAD_SD3_CLK__USBOH3_UH2_DFD_OUT_5 (_MX6Q_PAD_SD3_CLK__USBOH3_UH2_DFD_OUT_5) ++#define MX6Q_PAD_SD3_CLK__GPIO_7_3 (_MX6Q_PAD_SD3_CLK__GPIO_7_3) ++#define MX6Q_PAD_SD3_CLK__MIPI_CORE_DPHY_TEST_IN_17 (_MX6Q_PAD_SD3_CLK__MIPI_CORE_DPHY_TEST_IN_17) ++#define MX6Q_PAD_SD3_CLK__ANATOP_ANATOP_TESTO_14 (_MX6Q_PAD_SD3_CLK__ANATOP_ANATOP_TESTO_14) ++ ++#define MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 (_MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) ++#define MX6Q_PAD_SD3_DAT0__UART1_CTS (_MX6Q_PAD_SD3_DAT0__UART1_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) ++#define MX6Q_PAD_SD3_DAT0__CAN2_TXCAN (_MX6Q_PAD_SD3_DAT0__CAN2_TXCAN) ++#define MX6Q_PAD_SD3_DAT0__USBOH3_UH3_DFD_OUT_6 (_MX6Q_PAD_SD3_DAT0__USBOH3_UH3_DFD_OUT_6) ++#define MX6Q_PAD_SD3_DAT0__USBOH3_UH2_DFD_OUT_6 (_MX6Q_PAD_SD3_DAT0__USBOH3_UH2_DFD_OUT_6) ++#define MX6Q_PAD_SD3_DAT0__GPIO_7_4 (_MX6Q_PAD_SD3_DAT0__GPIO_7_4) ++#define MX6Q_PAD_SD3_DAT0__MIPI_CORE_DPHY_TEST_IN_18 (_MX6Q_PAD_SD3_DAT0__MIPI_CORE_DPHY_TEST_IN_18) ++#define MX6Q_PAD_SD3_DAT0__ANATOP_ANATOP_TESTO_15 (_MX6Q_PAD_SD3_DAT0__ANATOP_ANATOP_TESTO_15) ++ ++#define MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 (_MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) ++#define MX6Q_PAD_SD3_DAT1__UART1_CTS (_MX6Q_PAD_SD3_DAT1__UART1_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) ++#define MX6Q_PAD_SD3_DAT1__UART1_RTS (_MX6Q_PAD_SD3_DAT1__UART1_RTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) ++#define MX6Q_PAD_SD3_DAT1__CAN2_RXCAN (_MX6Q_PAD_SD3_DAT1__CAN2_RXCAN) ++#define MX6Q_PAD_SD3_DAT1__USBOH3_UH3_DFD_OUT_7 (_MX6Q_PAD_SD3_DAT1__USBOH3_UH3_DFD_OUT_7) ++#define MX6Q_PAD_SD3_DAT1__USBOH3_UH2_DFD_OUT_7 (_MX6Q_PAD_SD3_DAT1__USBOH3_UH2_DFD_OUT_7) ++#define MX6Q_PAD_SD3_DAT1__GPIO_7_5 (_MX6Q_PAD_SD3_DAT1__GPIO_7_5) ++#define MX6Q_PAD_SD3_DAT1__MIPI_CORE_DPHY_TEST_IN_19 (_MX6Q_PAD_SD3_DAT1__MIPI_CORE_DPHY_TEST_IN_19) ++#define MX6Q_PAD_SD3_DAT1__ANATOP_ANATOP_TESTI_0 (_MX6Q_PAD_SD3_DAT1__ANATOP_ANATOP_TESTI_0) ++ ++#define MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 (_MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) ++#define MX6Q_PAD_SD3_DAT2__PCIE_CTRL_DIAG_STATUS_BUS_MUX_28 (_MX6Q_PAD_SD3_DAT2__PCIE_CTRL_DIAG_STATUS_BUS_MUX_28) ++#define MX6Q_PAD_SD3_DAT2__USBOH3_UH3_DFD_OUT_8 (_MX6Q_PAD_SD3_DAT2__USBOH3_UH3_DFD_OUT_8) ++#define MX6Q_PAD_SD3_DAT2__USBOH3_UH2_DFD_OUT_8 (_MX6Q_PAD_SD3_DAT2__USBOH3_UH2_DFD_OUT_8) ++#define MX6Q_PAD_SD3_DAT2__GPIO_7_6 (_MX6Q_PAD_SD3_DAT2__GPIO_7_6) ++#define MX6Q_PAD_SD3_DAT2__MIPI_CORE_DPHY_TEST_IN_20 (_MX6Q_PAD_SD3_DAT2__MIPI_CORE_DPHY_TEST_IN_20) ++#define MX6Q_PAD_SD3_DAT2__ANATOP_ANATOP_TESTI_1 (_MX6Q_PAD_SD3_DAT2__ANATOP_ANATOP_TESTI_1) ++ ++#define MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 (_MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) ++#define MX6Q_PAD_SD3_DAT3__UART3_CTS (_MX6Q_PAD_SD3_DAT3__UART3_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) ++#define MX6Q_PAD_SD3_DAT3__PCIE_CTRL_DIAG_STATUS_BUS_MUX_29 (_MX6Q_PAD_SD3_DAT3__PCIE_CTRL_DIAG_STATUS_BUS_MUX_29) ++#define MX6Q_PAD_SD3_DAT3__USBOH3_UH3_DFD_OUT_9 (_MX6Q_PAD_SD3_DAT3__USBOH3_UH3_DFD_OUT_9) ++#define MX6Q_PAD_SD3_DAT3__USBOH3_UH2_DFD_OUT_9 (_MX6Q_PAD_SD3_DAT3__USBOH3_UH2_DFD_OUT_9) ++#define MX6Q_PAD_SD3_DAT3__GPIO_7_7 (_MX6Q_PAD_SD3_DAT3__GPIO_7_7) ++#define MX6Q_PAD_SD3_DAT3__MIPI_CORE_DPHY_TEST_IN_21 (_MX6Q_PAD_SD3_DAT3__MIPI_CORE_DPHY_TEST_IN_21) ++#define MX6Q_PAD_SD3_DAT3__ANATOP_ANATOP_TESTI_2 (_MX6Q_PAD_SD3_DAT3__ANATOP_ANATOP_TESTI_2) ++ ++#define MX6Q_PAD_SD3_RST__USDHC3_RST (_MX6Q_PAD_SD3_RST__USDHC3_RST | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) ++#define MX6Q_PAD_SD3_RST__UART3_CTS (_MX6Q_PAD_SD3_RST__UART3_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) ++#define MX6Q_PAD_SD3_RST__UART3_RTS (_MX6Q_PAD_SD3_RST__UART3_RTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) ++#define MX6Q_PAD_SD3_RST__PCIE_CTRL_DIAG_STATUS_BUS_MUX_30 (_MX6Q_PAD_SD3_RST__PCIE_CTRL_DIAG_STATUS_BUS_MUX_30) ++#define MX6Q_PAD_SD3_RST__USBOH3_UH3_DFD_OUT_10 (_MX6Q_PAD_SD3_RST__USBOH3_UH3_DFD_OUT_10) ++#define MX6Q_PAD_SD3_RST__USBOH3_UH2_DFD_OUT_10 (_MX6Q_PAD_SD3_RST__USBOH3_UH2_DFD_OUT_10) ++#define MX6Q_PAD_SD3_RST__GPIO_7_8 (_MX6Q_PAD_SD3_RST__GPIO_7_8) ++#define MX6Q_PAD_SD3_RST__MIPI_CORE_DPHY_TEST_IN_22 (_MX6Q_PAD_SD3_RST__MIPI_CORE_DPHY_TEST_IN_22) ++#define MX6Q_PAD_SD3_RST__ANATOP_ANATOP_TESTI_3 (_MX6Q_PAD_SD3_RST__ANATOP_ANATOP_TESTI_3) ++ ++#define MX6Q_PAD_NANDF_CLE__RAWNAND_CLE (_MX6Q_PAD_NANDF_CLE__RAWNAND_CLE) ++#define MX6Q_PAD_NANDF_CLE__IPU2_SISG_4 (_MX6Q_PAD_NANDF_CLE__IPU2_SISG_4) ++#define MX6Q_PAD_NANDF_CLE__PCIE_CTRL_DIAG_STATUS_BUS_MUX_31 (_MX6Q_PAD_NANDF_CLE__PCIE_CTRL_DIAG_STATUS_BUS_MUX_31) ++#define MX6Q_PAD_NANDF_CLE__USBOH3_UH3_DFD_OUT_11 (_MX6Q_PAD_NANDF_CLE__USBOH3_UH3_DFD_OUT_11) ++#define MX6Q_PAD_NANDF_CLE__USBOH3_UH2_DFD_OUT_11 (_MX6Q_PAD_NANDF_CLE__USBOH3_UH2_DFD_OUT_11) ++#define MX6Q_PAD_NANDF_CLE__GPIO_6_7 (_MX6Q_PAD_NANDF_CLE__GPIO_6_7) ++#define MX6Q_PAD_NANDF_CLE__MIPI_CORE_DPHY_TEST_IN_23 (_MX6Q_PAD_NANDF_CLE__MIPI_CORE_DPHY_TEST_IN_23) ++#define MX6Q_PAD_NANDF_CLE__TPSMP_HTRANS_0 (_MX6Q_PAD_NANDF_CLE__TPSMP_HTRANS_0) ++ ++#define MX6Q_PAD_NANDF_ALE__RAWNAND_ALE (_MX6Q_PAD_NANDF_ALE__RAWNAND_ALE) ++#define MX6Q_PAD_NANDF_ALE__USDHC4_RST (_MX6Q_PAD_NANDF_ALE__USDHC4_RST | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) ++#define MX6Q_PAD_NANDF_ALE__PCIE_CTRL_DIAG_STATUS_BUS_MUX_0 (_MX6Q_PAD_NANDF_ALE__PCIE_CTRL_DIAG_STATUS_BUS_MUX_0) ++#define MX6Q_PAD_NANDF_ALE__USBOH3_UH3_DFD_OUT_12 (_MX6Q_PAD_NANDF_ALE__USBOH3_UH3_DFD_OUT_12) ++#define MX6Q_PAD_NANDF_ALE__USBOH3_UH2_DFD_OUT_12 (_MX6Q_PAD_NANDF_ALE__USBOH3_UH2_DFD_OUT_12) ++#define MX6Q_PAD_NANDF_ALE__GPIO_6_8 (_MX6Q_PAD_NANDF_ALE__GPIO_6_8) ++#define MX6Q_PAD_NANDF_ALE__MIPI_CORE_DPHY_TEST_IN_24 (_MX6Q_PAD_NANDF_ALE__MIPI_CORE_DPHY_TEST_IN_24) ++#define MX6Q_PAD_NANDF_ALE__TPSMP_HTRANS_1 (_MX6Q_PAD_NANDF_ALE__TPSMP_HTRANS_1) ++ ++#define MX6Q_PAD_NANDF_WP_B__RAWNAND_RESETN (_MX6Q_PAD_NANDF_WP_B__RAWNAND_RESETN) ++#define MX6Q_PAD_NANDF_WP_B__IPU2_SISG_5 (_MX6Q_PAD_NANDF_WP_B__IPU2_SISG_5) ++#define MX6Q_PAD_NANDF_WP_B__PCIE_CTRL_DIAG_STATUS_BUS_MUX_1 (_MX6Q_PAD_NANDF_WP_B__PCIE_CTRL_DIAG_STATUS_BUS_MUX_1) ++#define MX6Q_PAD_NANDF_WP_B__USBOH3_UH3_DFD_OUT_13 (_MX6Q_PAD_NANDF_WP_B__USBOH3_UH3_DFD_OUT_13) ++#define MX6Q_PAD_NANDF_WP_B__USBOH3_UH2_DFD_OUT_13 (_MX6Q_PAD_NANDF_WP_B__USBOH3_UH2_DFD_OUT_13) ++#define MX6Q_PAD_NANDF_WP_B__GPIO_6_9 (_MX6Q_PAD_NANDF_WP_B__GPIO_6_9) ++#define MX6Q_PAD_NANDF_WP_B__MIPI_CORE_DPHY_TEST_OUT_32 (_MX6Q_PAD_NANDF_WP_B__MIPI_CORE_DPHY_TEST_OUT_32) ++#define MX6Q_PAD_NANDF_WP_B__PL301_MX6QPER1_HSIZE_0 (_MX6Q_PAD_NANDF_WP_B__PL301_MX6QPER1_HSIZE_0) ++ ++#define MX6Q_PAD_NANDF_RB0__RAWNAND_READY0 (_MX6Q_PAD_NANDF_RB0__RAWNAND_READY0) ++#define MX6Q_PAD_NANDF_RB0__IPU2_DI0_PIN1 (_MX6Q_PAD_NANDF_RB0__IPU2_DI0_PIN1) ++#define MX6Q_PAD_NANDF_RB0__PCIE_CTRL_DIAG_STATUS_BUS_MUX_2 (_MX6Q_PAD_NANDF_RB0__PCIE_CTRL_DIAG_STATUS_BUS_MUX_2) ++#define MX6Q_PAD_NANDF_RB0__USBOH3_UH3_DFD_OUT_14 (_MX6Q_PAD_NANDF_RB0__USBOH3_UH3_DFD_OUT_14) ++#define MX6Q_PAD_NANDF_RB0__USBOH3_UH2_DFD_OUT_14 (_MX6Q_PAD_NANDF_RB0__USBOH3_UH2_DFD_OUT_14) ++#define MX6Q_PAD_NANDF_RB0__GPIO_6_10 (_MX6Q_PAD_NANDF_RB0__GPIO_6_10) ++#define MX6Q_PAD_NANDF_RB0__MIPI_CORE_DPHY_TEST_OUT_33 (_MX6Q_PAD_NANDF_RB0__MIPI_CORE_DPHY_TEST_OUT_33) ++#define MX6Q_PAD_NANDF_RB0__PL301_MX6QPER1_HSIZE_1 (_MX6Q_PAD_NANDF_RB0__PL301_MX6QPER1_HSIZE_1) ++ ++#define MX6Q_PAD_NANDF_CS0__RAWNAND_CE0N (_MX6Q_PAD_NANDF_CS0__RAWNAND_CE0N) ++#define MX6Q_PAD_NANDF_CS0__USBOH3_UH3_DFD_OUT_15 (_MX6Q_PAD_NANDF_CS0__USBOH3_UH3_DFD_OUT_15) ++#define MX6Q_PAD_NANDF_CS0__USBOH3_UH2_DFD_OUT_15 (_MX6Q_PAD_NANDF_CS0__USBOH3_UH2_DFD_OUT_15) ++#define MX6Q_PAD_NANDF_CS0__GPIO_6_11 (_MX6Q_PAD_NANDF_CS0__GPIO_6_11) ++#define MX6Q_PAD_NANDF_CS0__PL301_MX6QPER1_HSIZE_2 (_MX6Q_PAD_NANDF_CS0__PL301_MX6QPER1_HSIZE_2) ++ ++#define MX6Q_PAD_NANDF_CS1__RAWNAND_CE1N (_MX6Q_PAD_NANDF_CS1__RAWNAND_CE1N) ++#define MX6Q_PAD_NANDF_CS1__USDHC4_VSELECT (_MX6Q_PAD_NANDF_CS1__USDHC4_VSELECT | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) ++#define MX6Q_PAD_NANDF_CS1__USDHC3_VSELECT (_MX6Q_PAD_NANDF_CS1__USDHC3_VSELECT | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) ++#define MX6Q_PAD_NANDF_CS1__PCIE_CTRL_DIAG_STATUS_BUS_MUX_3 (_MX6Q_PAD_NANDF_CS1__PCIE_CTRL_DIAG_STATUS_BUS_MUX_3) ++#define MX6Q_PAD_NANDF_CS1__GPIO_6_14 (_MX6Q_PAD_NANDF_CS1__GPIO_6_14) ++#define MX6Q_PAD_NANDF_CS1__PL301_MX6QPER1_HREADYOUT (_MX6Q_PAD_NANDF_CS1__PL301_MX6QPER1_HREADYOUT) ++ ++#define MX6Q_PAD_NANDF_CS2__RAWNAND_CE2N (_MX6Q_PAD_NANDF_CS2__RAWNAND_CE2N) ++#define MX6Q_PAD_NANDF_CS2__IPU1_SISG_0 (_MX6Q_PAD_NANDF_CS2__IPU1_SISG_0) ++#define MX6Q_PAD_NANDF_CS2__ESAI1_TX0 (_MX6Q_PAD_NANDF_CS2__ESAI1_TX0) ++#define MX6Q_PAD_NANDF_CS2__WEIM_WEIM_CRE (_MX6Q_PAD_NANDF_CS2__WEIM_WEIM_CRE) ++#define MX6Q_PAD_NANDF_CS2__CCM_CLKO2 (_MX6Q_PAD_NANDF_CS2__CCM_CLKO2) ++#define MX6Q_PAD_NANDF_CS2__GPIO_6_15 (_MX6Q_PAD_NANDF_CS2__GPIO_6_15) ++#define MX6Q_PAD_NANDF_CS2__IPU2_SISG_0 (_MX6Q_PAD_NANDF_CS2__IPU2_SISG_0) ++ ++#define MX6Q_PAD_NANDF_CS3__RAWNAND_CE3N (_MX6Q_PAD_NANDF_CS3__RAWNAND_CE3N) ++#define MX6Q_PAD_NANDF_CS3__IPU1_SISG_1 (_MX6Q_PAD_NANDF_CS3__IPU1_SISG_1) ++#define MX6Q_PAD_NANDF_CS3__ESAI1_TX1 (_MX6Q_PAD_NANDF_CS3__ESAI1_TX1) ++#define MX6Q_PAD_NANDF_CS3__WEIM_WEIM_A_26 (_MX6Q_PAD_NANDF_CS3__WEIM_WEIM_A_26) ++#define MX6Q_PAD_NANDF_CS3__PCIE_CTRL_DIAG_STATUS_BUS_MUX_4 (_MX6Q_PAD_NANDF_CS3__PCIE_CTRL_DIAG_STATUS_BUS_MUX_4) ++#define MX6Q_PAD_NANDF_CS3__GPIO_6_16 (_MX6Q_PAD_NANDF_CS3__GPIO_6_16) ++#define MX6Q_PAD_NANDF_CS3__IPU2_SISG_1 (_MX6Q_PAD_NANDF_CS3__IPU2_SISG_1) ++#define MX6Q_PAD_NANDF_CS3__TPSMP_CLK (_MX6Q_PAD_NANDF_CS3__TPSMP_CLK) ++ ++#define MX6Q_PAD_SD4_CMD__USDHC4_CMD (_MX6Q_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) ++#define MX6Q_PAD_SD4_CMD__RAWNAND_RDN (_MX6Q_PAD_SD4_CMD__RAWNAND_RDN) ++#define MX6Q_PAD_SD4_CMD__UART3_TXD (_MX6Q_PAD_SD4_CMD__UART3_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) ++#define MX6Q_PAD_SD4_CMD__UART3_RXD (_MX6Q_PAD_SD4_CMD__UART3_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) ++#define MX6Q_PAD_SD4_CMD__PCIE_CTRL_DIAG_STATUS_BUS_MUX_5 (_MX6Q_PAD_SD4_CMD__PCIE_CTRL_DIAG_STATUS_BUS_MUX_5) ++#define MX6Q_PAD_SD4_CMD__GPIO_7_9 (_MX6Q_PAD_SD4_CMD__GPIO_7_9) ++#define MX6Q_PAD_SD4_CMD__TPSMP_HDATA_DIR (_MX6Q_PAD_SD4_CMD__TPSMP_HDATA_DIR) ++ ++#define MX6Q_PAD_SD4_CLK__USDHC4_CLK (_MX6Q_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) ++#define MX6Q_PAD_SD4_CLK__RAWNAND_WRN (_MX6Q_PAD_SD4_CLK__RAWNAND_WRN) ++#define MX6Q_PAD_SD4_CLK__UART3_TXD (_MX6Q_PAD_SD4_CLK__UART3_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) ++#define MX6Q_PAD_SD4_CLK__UART3_RXD (_MX6Q_PAD_SD4_CLK__UART3_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) ++#define MX6Q_PAD_SD4_CLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_6 (_MX6Q_PAD_SD4_CLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_6) ++#define MX6Q_PAD_SD4_CLK__GPIO_7_10 (_MX6Q_PAD_SD4_CLK__GPIO_7_10) ++ ++#define MX6Q_PAD_NANDF_D0__RAWNAND_D0 (_MX6Q_PAD_NANDF_D0__RAWNAND_D0) ++#define MX6Q_PAD_NANDF_D0__USDHC1_DAT4 (_MX6Q_PAD_NANDF_D0__USDHC1_DAT4 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) ++#define MX6Q_PAD_NANDF_D0__GPU3D_GPU_DEBUG_OUT_0 (_MX6Q_PAD_NANDF_D0__GPU3D_GPU_DEBUG_OUT_0) ++#define MX6Q_PAD_NANDF_D0__USBOH3_UH2_DFD_OUT_16 (_MX6Q_PAD_NANDF_D0__USBOH3_UH2_DFD_OUT_16) ++#define MX6Q_PAD_NANDF_D0__USBOH3_UH3_DFD_OUT_16 (_MX6Q_PAD_NANDF_D0__USBOH3_UH3_DFD_OUT_16) ++#define MX6Q_PAD_NANDF_D0__GPIO_2_0 (_MX6Q_PAD_NANDF_D0__GPIO_2_0) ++#define MX6Q_PAD_NANDF_D0__IPU1_IPU_DIAG_BUS_0 (_MX6Q_PAD_NANDF_D0__IPU1_IPU_DIAG_BUS_0) ++#define MX6Q_PAD_NANDF_D0__IPU2_IPU_DIAG_BUS_0 (_MX6Q_PAD_NANDF_D0__IPU2_IPU_DIAG_BUS_0) ++ ++#define MX6Q_PAD_NANDF_D1__RAWNAND_D1 (_MX6Q_PAD_NANDF_D1__RAWNAND_D1) ++#define MX6Q_PAD_NANDF_D1__USDHC1_DAT5 (_MX6Q_PAD_NANDF_D1__USDHC1_DAT5 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) ++#define MX6Q_PAD_NANDF_D1__GPU3D_GPU_DEBUG_OUT_1 (_MX6Q_PAD_NANDF_D1__GPU3D_GPU_DEBUG_OUT_1) ++#define MX6Q_PAD_NANDF_D1__USBOH3_UH2_DFD_OUT_17 (_MX6Q_PAD_NANDF_D1__USBOH3_UH2_DFD_OUT_17) ++#define MX6Q_PAD_NANDF_D1__USBOH3_UH3_DFD_OUT_17 (_MX6Q_PAD_NANDF_D1__USBOH3_UH3_DFD_OUT_17) ++#define MX6Q_PAD_NANDF_D1__GPIO_2_1 (_MX6Q_PAD_NANDF_D1__GPIO_2_1) ++#define MX6Q_PAD_NANDF_D1__IPU1_IPU_DIAG_BUS_1 (_MX6Q_PAD_NANDF_D1__IPU1_IPU_DIAG_BUS_1) ++#define MX6Q_PAD_NANDF_D1__IPU2_IPU_DIAG_BUS_1 (_MX6Q_PAD_NANDF_D1__IPU2_IPU_DIAG_BUS_1) ++ ++#define MX6Q_PAD_NANDF_D2__RAWNAND_D2 (_MX6Q_PAD_NANDF_D2__RAWNAND_D2) ++#define MX6Q_PAD_NANDF_D2__USDHC1_DAT6 (_MX6Q_PAD_NANDF_D2__USDHC1_DAT6 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) ++#define MX6Q_PAD_NANDF_D2__GPU3D_GPU_DEBUG_OUT_2 (_MX6Q_PAD_NANDF_D2__GPU3D_GPU_DEBUG_OUT_2) ++#define MX6Q_PAD_NANDF_D2__USBOH3_UH2_DFD_OUT_18 (_MX6Q_PAD_NANDF_D2__USBOH3_UH2_DFD_OUT_18) ++#define MX6Q_PAD_NANDF_D2__USBOH3_UH3_DFD_OUT_18 (_MX6Q_PAD_NANDF_D2__USBOH3_UH3_DFD_OUT_18) ++#define MX6Q_PAD_NANDF_D2__GPIO_2_2 (_MX6Q_PAD_NANDF_D2__GPIO_2_2) ++#define MX6Q_PAD_NANDF_D2__IPU1_IPU_DIAG_BUS_2 (_MX6Q_PAD_NANDF_D2__IPU1_IPU_DIAG_BUS_2) ++#define MX6Q_PAD_NANDF_D2__IPU2_IPU_DIAG_BUS_2 (_MX6Q_PAD_NANDF_D2__IPU2_IPU_DIAG_BUS_2) ++ ++#define MX6Q_PAD_NANDF_D3__RAWNAND_D3 (_MX6Q_PAD_NANDF_D3__RAWNAND_D3) ++#define MX6Q_PAD_NANDF_D3__USDHC1_DAT7 (_MX6Q_PAD_NANDF_D3__USDHC1_DAT7 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) ++#define MX6Q_PAD_NANDF_D3__GPU3D_GPU_DEBUG_OUT_3 (_MX6Q_PAD_NANDF_D3__GPU3D_GPU_DEBUG_OUT_3) ++#define MX6Q_PAD_NANDF_D3__USBOH3_UH2_DFD_OUT_19 (_MX6Q_PAD_NANDF_D3__USBOH3_UH2_DFD_OUT_19) ++#define MX6Q_PAD_NANDF_D3__USBOH3_UH3_DFD_OUT_19 (_MX6Q_PAD_NANDF_D3__USBOH3_UH3_DFD_OUT_19) ++#define MX6Q_PAD_NANDF_D3__GPIO_2_3 (_MX6Q_PAD_NANDF_D3__GPIO_2_3) ++#define MX6Q_PAD_NANDF_D3__IPU1_IPU_DIAG_BUS_3 (_MX6Q_PAD_NANDF_D3__IPU1_IPU_DIAG_BUS_3) ++#define MX6Q_PAD_NANDF_D3__IPU2_IPU_DIAG_BUS_3 (_MX6Q_PAD_NANDF_D3__IPU2_IPU_DIAG_BUS_3) ++ ++#define MX6Q_PAD_NANDF_D4__RAWNAND_D4 (_MX6Q_PAD_NANDF_D4__RAWNAND_D4) ++#define MX6Q_PAD_NANDF_D4__USDHC2_DAT4 (_MX6Q_PAD_NANDF_D4__USDHC2_DAT4 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) ++#define MX6Q_PAD_NANDF_D4__GPU3D_GPU_DEBUG_OUT_4 (_MX6Q_PAD_NANDF_D4__GPU3D_GPU_DEBUG_OUT_4) ++#define MX6Q_PAD_NANDF_D4__USBOH3_UH2_DFD_OUT_20 (_MX6Q_PAD_NANDF_D4__USBOH3_UH2_DFD_OUT_20) ++#define MX6Q_PAD_NANDF_D4__USBOH3_UH3_DFD_OUT_20 (_MX6Q_PAD_NANDF_D4__USBOH3_UH3_DFD_OUT_20) ++#define MX6Q_PAD_NANDF_D4__GPIO_2_4 (_MX6Q_PAD_NANDF_D4__GPIO_2_4) ++#define MX6Q_PAD_NANDF_D4__IPU1_IPU_DIAG_BUS_4 (_MX6Q_PAD_NANDF_D4__IPU1_IPU_DIAG_BUS_4) ++#define MX6Q_PAD_NANDF_D4__IPU2_IPU_DIAG_BUS_4 (_MX6Q_PAD_NANDF_D4__IPU2_IPU_DIAG_BUS_4) ++ ++#define MX6Q_PAD_NANDF_D5__RAWNAND_D5 (_MX6Q_PAD_NANDF_D5__RAWNAND_D5) ++#define MX6Q_PAD_NANDF_D5__USDHC2_DAT5 (_MX6Q_PAD_NANDF_D5__USDHC2_DAT5 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) ++#define MX6Q_PAD_NANDF_D5__GPU3D_GPU_DEBUG_OUT_5 (_MX6Q_PAD_NANDF_D5__GPU3D_GPU_DEBUG_OUT_5) ++#define MX6Q_PAD_NANDF_D5__USBOH3_UH2_DFD_OUT_21 (_MX6Q_PAD_NANDF_D5__USBOH3_UH2_DFD_OUT_21) ++#define MX6Q_PAD_NANDF_D5__USBOH3_UH3_DFD_OUT_21 (_MX6Q_PAD_NANDF_D5__USBOH3_UH3_DFD_OUT_21) ++#define MX6Q_PAD_NANDF_D5__GPIO_2_5 (_MX6Q_PAD_NANDF_D5__GPIO_2_5) ++#define MX6Q_PAD_NANDF_D5__IPU1_IPU_DIAG_BUS_5 (_MX6Q_PAD_NANDF_D5__IPU1_IPU_DIAG_BUS_5) ++#define MX6Q_PAD_NANDF_D5__IPU2_IPU_DIAG_BUS_5 (_MX6Q_PAD_NANDF_D5__IPU2_IPU_DIAG_BUS_5) ++ ++#define MX6Q_PAD_NANDF_D6__RAWNAND_D6 (_MX6Q_PAD_NANDF_D6__RAWNAND_D6) ++#define MX6Q_PAD_NANDF_D6__USDHC2_DAT6 (_MX6Q_PAD_NANDF_D6__USDHC2_DAT6 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) ++#define MX6Q_PAD_NANDF_D6__GPU3D_GPU_DEBUG_OUT_6 (_MX6Q_PAD_NANDF_D6__GPU3D_GPU_DEBUG_OUT_6) ++#define MX6Q_PAD_NANDF_D6__USBOH3_UH2_DFD_OUT_22 (_MX6Q_PAD_NANDF_D6__USBOH3_UH2_DFD_OUT_22) ++#define MX6Q_PAD_NANDF_D6__USBOH3_UH3_DFD_OUT_22 (_MX6Q_PAD_NANDF_D6__USBOH3_UH3_DFD_OUT_22) ++#define MX6Q_PAD_NANDF_D6__GPIO_2_6 (_MX6Q_PAD_NANDF_D6__GPIO_2_6) ++#define MX6Q_PAD_NANDF_D6__IPU1_IPU_DIAG_BUS_6 (_MX6Q_PAD_NANDF_D6__IPU1_IPU_DIAG_BUS_6) ++#define MX6Q_PAD_NANDF_D6__IPU2_IPU_DIAG_BUS_6 (_MX6Q_PAD_NANDF_D6__IPU2_IPU_DIAG_BUS_6) ++ ++#define MX6Q_PAD_NANDF_D7__RAWNAND_D7 (_MX6Q_PAD_NANDF_D7__RAWNAND_D7) ++#define MX6Q_PAD_NANDF_D7__USDHC2_DAT7 (_MX6Q_PAD_NANDF_D7__USDHC2_DAT7 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) ++#define MX6Q_PAD_NANDF_D7__GPU3D_GPU_DEBUG_OUT_7 (_MX6Q_PAD_NANDF_D7__GPU3D_GPU_DEBUG_OUT_7) ++#define MX6Q_PAD_NANDF_D7__USBOH3_UH2_DFD_OUT_23 (_MX6Q_PAD_NANDF_D7__USBOH3_UH2_DFD_OUT_23) ++#define MX6Q_PAD_NANDF_D7__USBOH3_UH3_DFD_OUT_23 (_MX6Q_PAD_NANDF_D7__USBOH3_UH3_DFD_OUT_23) ++#define MX6Q_PAD_NANDF_D7__GPIO_2_7 (_MX6Q_PAD_NANDF_D7__GPIO_2_7) ++#define MX6Q_PAD_NANDF_D7__IPU1_IPU_DIAG_BUS_7 (_MX6Q_PAD_NANDF_D7__IPU1_IPU_DIAG_BUS_7) ++#define MX6Q_PAD_NANDF_D7__IPU2_IPU_DIAG_BUS_7 (_MX6Q_PAD_NANDF_D7__IPU2_IPU_DIAG_BUS_7) ++ ++#define MX6Q_PAD_SD4_DAT0__RAWNAND_D8 (_MX6Q_PAD_SD4_DAT0__RAWNAND_D8) ++#define MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 (_MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) ++#define MX6Q_PAD_SD4_DAT0__RAWNAND_DQS (_MX6Q_PAD_SD4_DAT0__RAWNAND_DQS) ++#define MX6Q_PAD_SD4_DAT0__USBOH3_UH2_DFD_OUT_24 (_MX6Q_PAD_SD4_DAT0__USBOH3_UH2_DFD_OUT_24) ++#define MX6Q_PAD_SD4_DAT0__USBOH3_UH3_DFD_OUT_24 (_MX6Q_PAD_SD4_DAT0__USBOH3_UH3_DFD_OUT_24) ++#define MX6Q_PAD_SD4_DAT0__GPIO_2_8 (_MX6Q_PAD_SD4_DAT0__GPIO_2_8) ++#define MX6Q_PAD_SD4_DAT0__IPU1_IPU_DIAG_BUS_8 (_MX6Q_PAD_SD4_DAT0__IPU1_IPU_DIAG_BUS_8) ++#define MX6Q_PAD_SD4_DAT0__IPU2_IPU_DIAG_BUS_8 (_MX6Q_PAD_SD4_DAT0__IPU2_IPU_DIAG_BUS_8) ++ ++#define MX6Q_PAD_SD4_DAT1__RAWNAND_D9 (_MX6Q_PAD_SD4_DAT1__RAWNAND_D9) ++#define MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 (_MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) ++#define MX6Q_PAD_SD4_DAT1__PWM3_PWMO (_MX6Q_PAD_SD4_DAT1__PWM3_PWMO) ++#define MX6Q_PAD_SD4_DAT1__USBOH3_UH2_DFD_OUT_25 (_MX6Q_PAD_SD4_DAT1__USBOH3_UH2_DFD_OUT_25) ++#define MX6Q_PAD_SD4_DAT1__USBOH3_UH3_DFD_OUT_25 (_MX6Q_PAD_SD4_DAT1__USBOH3_UH3_DFD_OUT_25) ++#define MX6Q_PAD_SD4_DAT1__GPIO_2_9 (_MX6Q_PAD_SD4_DAT1__GPIO_2_9) ++#define MX6Q_PAD_SD4_DAT1__IPU1_IPU_DIAG_BUS_9 (_MX6Q_PAD_SD4_DAT1__IPU1_IPU_DIAG_BUS_9) ++#define MX6Q_PAD_SD4_DAT1__IPU2_IPU_DIAG_BUS_9 (_MX6Q_PAD_SD4_DAT1__IPU2_IPU_DIAG_BUS_9) ++ ++#define MX6Q_PAD_SD4_DAT2__RAWNAND_D10 (_MX6Q_PAD_SD4_DAT2__RAWNAND_D10) ++#define MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 (_MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) ++#define MX6Q_PAD_SD4_DAT2__PWM4_PWMO (_MX6Q_PAD_SD4_DAT2__PWM4_PWMO) ++#define MX6Q_PAD_SD4_DAT2__USBOH3_UH2_DFD_OUT_26 (_MX6Q_PAD_SD4_DAT2__USBOH3_UH2_DFD_OUT_26) ++#define MX6Q_PAD_SD4_DAT2__USBOH3_UH3_DFD_OUT_26 (_MX6Q_PAD_SD4_DAT2__USBOH3_UH3_DFD_OUT_26) ++#define MX6Q_PAD_SD4_DAT2__GPIO_2_10 (_MX6Q_PAD_SD4_DAT2__GPIO_2_10) ++#define MX6Q_PAD_SD4_DAT2__IPU1_IPU_DIAG_BUS_10 (_MX6Q_PAD_SD4_DAT2__IPU1_IPU_DIAG_BUS_10) ++#define MX6Q_PAD_SD4_DAT2__IPU2_IPU_DIAG_BUS_10 (_MX6Q_PAD_SD4_DAT2__IPU2_IPU_DIAG_BUS_10) ++ ++#define MX6Q_PAD_SD4_DAT3__RAWNAND_D11 (_MX6Q_PAD_SD4_DAT3__RAWNAND_D11) ++#define MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 (_MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) ++#define MX6Q_PAD_SD4_DAT3__USBOH3_UH2_DFD_OUT_27 (_MX6Q_PAD_SD4_DAT3__USBOH3_UH2_DFD_OUT_27) ++#define MX6Q_PAD_SD4_DAT3__USBOH3_UH3_DFD_OUT_27 (_MX6Q_PAD_SD4_DAT3__USBOH3_UH3_DFD_OUT_27) ++#define MX6Q_PAD_SD4_DAT3__GPIO_2_11 (_MX6Q_PAD_SD4_DAT3__GPIO_2_11) ++#define MX6Q_PAD_SD4_DAT3__IPU1_IPU_DIAG_BUS_11 (_MX6Q_PAD_SD4_DAT3__IPU1_IPU_DIAG_BUS_11) ++#define MX6Q_PAD_SD4_DAT3__IPU2_IPU_DIAG_BUS_11 (_MX6Q_PAD_SD4_DAT3__IPU2_IPU_DIAG_BUS_11) ++ ++#define MX6Q_PAD_SD4_DAT4__RAWNAND_D12 (_MX6Q_PAD_SD4_DAT4__RAWNAND_D12) ++#define MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 (_MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) ++#define MX6Q_PAD_SD4_DAT4__UART2_TXD (_MX6Q_PAD_SD4_DAT4__UART2_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) ++#define MX6Q_PAD_SD4_DAT4__UART2_RXD (_MX6Q_PAD_SD4_DAT4__UART2_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) ++#define MX6Q_PAD_SD4_DAT4__USBOH3_UH2_DFD_OUT_28 (_MX6Q_PAD_SD4_DAT4__USBOH3_UH2_DFD_OUT_28) ++#define MX6Q_PAD_SD4_DAT4__USBOH3_UH3_DFD_OUT_28 (_MX6Q_PAD_SD4_DAT4__USBOH3_UH3_DFD_OUT_28) ++#define MX6Q_PAD_SD4_DAT4__GPIO_2_12 (_MX6Q_PAD_SD4_DAT4__GPIO_2_12) ++#define MX6Q_PAD_SD4_DAT4__IPU1_IPU_DIAG_BUS_12 (_MX6Q_PAD_SD4_DAT4__IPU1_IPU_DIAG_BUS_12) ++#define MX6Q_PAD_SD4_DAT4__IPU2_IPU_DIAG_BUS_12 (_MX6Q_PAD_SD4_DAT4__IPU2_IPU_DIAG_BUS_12) ++ ++#define MX6Q_PAD_SD4_DAT5__RAWNAND_D13 (_MX6Q_PAD_SD4_DAT5__RAWNAND_D13) ++#define MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 (_MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) ++#define MX6Q_PAD_SD4_DAT5__UART2_CTS (_MX6Q_PAD_SD4_DAT5__UART2_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) ++#define MX6Q_PAD_SD4_DAT5__UART2_RTS (_MX6Q_PAD_SD4_DAT5__UART2_RTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) ++#define MX6Q_PAD_SD4_DAT5__USBOH3_UH2_DFD_OUT_29 (_MX6Q_PAD_SD4_DAT5__USBOH3_UH2_DFD_OUT_29) ++#define MX6Q_PAD_SD4_DAT5__USBOH3_UH3_DFD_OUT_29 (_MX6Q_PAD_SD4_DAT5__USBOH3_UH3_DFD_OUT_29) ++#define MX6Q_PAD_SD4_DAT5__GPIO_2_13 (_MX6Q_PAD_SD4_DAT5__GPIO_2_13) ++#define MX6Q_PAD_SD4_DAT5__IPU1_IPU_DIAG_BUS_13 (_MX6Q_PAD_SD4_DAT5__IPU1_IPU_DIAG_BUS_13) ++#define MX6Q_PAD_SD4_DAT5__IPU2_IPU_DIAG_BUS_13 (_MX6Q_PAD_SD4_DAT5__IPU2_IPU_DIAG_BUS_13) ++ ++#define MX6Q_PAD_SD4_DAT6__RAWNAND_D14 (_MX6Q_PAD_SD4_DAT6__RAWNAND_D14) ++#define MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 (_MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) ++#define MX6Q_PAD_SD4_DAT6__UART2_CTS (_MX6Q_PAD_SD4_DAT6__UART2_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) ++#define MX6Q_PAD_SD4_DAT6__USBOH3_UH2_DFD_OUT_30 (_MX6Q_PAD_SD4_DAT6__USBOH3_UH2_DFD_OUT_30) ++#define MX6Q_PAD_SD4_DAT6__USBOH3_UH3_DFD_OUT_30 (_MX6Q_PAD_SD4_DAT6__USBOH3_UH3_DFD_OUT_30) ++#define MX6Q_PAD_SD4_DAT6__GPIO_2_14 (_MX6Q_PAD_SD4_DAT6__GPIO_2_14) ++#define MX6Q_PAD_SD4_DAT6__IPU1_IPU_DIAG_BUS_14 (_MX6Q_PAD_SD4_DAT6__IPU1_IPU_DIAG_BUS_14) ++#define MX6Q_PAD_SD4_DAT6__IPU2_IPU_DIAG_BUS_14 (_MX6Q_PAD_SD4_DAT6__IPU2_IPU_DIAG_BUS_14) ++ ++#define MX6Q_PAD_SD4_DAT7__RAWNAND_D15 (_MX6Q_PAD_SD4_DAT7__RAWNAND_D15) ++#define MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 (_MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) ++#define MX6Q_PAD_SD4_DAT7__UART2_TXD (_MX6Q_PAD_SD4_DAT7__UART2_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) ++#define MX6Q_PAD_SD4_DAT7__UART2_RXD (_MX6Q_PAD_SD4_DAT7__UART2_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) ++#define MX6Q_PAD_SD4_DAT7__USBOH3_UH2_DFD_OUT_31 (_MX6Q_PAD_SD4_DAT7__USBOH3_UH2_DFD_OUT_31) ++#define MX6Q_PAD_SD4_DAT7__USBOH3_UH3_DFD_OUT_31 (_MX6Q_PAD_SD4_DAT7__USBOH3_UH3_DFD_OUT_31) ++#define MX6Q_PAD_SD4_DAT7__GPIO_2_15 (_MX6Q_PAD_SD4_DAT7__GPIO_2_15) ++#define MX6Q_PAD_SD4_DAT7__IPU1_IPU_DIAG_BUS_15 (_MX6Q_PAD_SD4_DAT7__IPU1_IPU_DIAG_BUS_15) ++#define MX6Q_PAD_SD4_DAT7__IPU2_IPU_DIAG_BUS_15 (_MX6Q_PAD_SD4_DAT7__IPU2_IPU_DIAG_BUS_15) ++ ++#define MX6Q_PAD_SD1_DAT1__USDHC1_DAT1 (_MX6Q_PAD_SD1_DAT1__USDHC1_DAT1 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) ++#define MX6Q_PAD_SD1_DAT1__ECSPI5_SS0 (_MX6Q_PAD_SD1_DAT1__ECSPI5_SS0) ++#define MX6Q_PAD_SD1_DAT1__PWM3_PWMO (_MX6Q_PAD_SD1_DAT1__PWM3_PWMO) ++#define MX6Q_PAD_SD1_DAT1__GPT_CAPIN2 (_MX6Q_PAD_SD1_DAT1__GPT_CAPIN2) ++#define MX6Q_PAD_SD1_DAT1__PCIE_CTRL_DIAG_STATUS_BUS_MUX_7 (_MX6Q_PAD_SD1_DAT1__PCIE_CTRL_DIAG_STATUS_BUS_MUX_7) ++#define MX6Q_PAD_SD1_DAT1__GPIO_1_17 (_MX6Q_PAD_SD1_DAT1__GPIO_1_17) ++#define MX6Q_PAD_SD1_DAT1__HDMI_TX_OPHYDTB_0 (_MX6Q_PAD_SD1_DAT1__HDMI_TX_OPHYDTB_0) ++#define MX6Q_PAD_SD1_DAT1__ANATOP_ANATOP_TESTO_8 (_MX6Q_PAD_SD1_DAT1__ANATOP_ANATOP_TESTO_8) ++ ++#define MX6Q_PAD_SD1_DAT0__USDHC1_DAT0 (_MX6Q_PAD_SD1_DAT0__USDHC1_DAT0 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) ++#define MX6Q_PAD_SD1_DAT0__ECSPI5_MISO (_MX6Q_PAD_SD1_DAT0__ECSPI5_MISO) ++#define MX6Q_PAD_SD1_DAT0__CAAM_WRAPPER_RNG_OSC_OBS (_MX6Q_PAD_SD1_DAT0__CAAM_WRAPPER_RNG_OSC_OBS) ++#define MX6Q_PAD_SD1_DAT0__GPT_CAPIN1 (_MX6Q_PAD_SD1_DAT0__GPT_CAPIN1) ++#define MX6Q_PAD_SD1_DAT0__PCIE_CTRL_DIAG_STATUS_BUS_MUX_8 (_MX6Q_PAD_SD1_DAT0__PCIE_CTRL_DIAG_STATUS_BUS_MUX_8) ++#define MX6Q_PAD_SD1_DAT0__GPIO_1_16 (_MX6Q_PAD_SD1_DAT0__GPIO_1_16) ++#define MX6Q_PAD_SD1_DAT0__HDMI_TX_OPHYDTB_1 (_MX6Q_PAD_SD1_DAT0__HDMI_TX_OPHYDTB_1) ++#define MX6Q_PAD_SD1_DAT0__ANATOP_ANATOP_TESTO_7 (_MX6Q_PAD_SD1_DAT0__ANATOP_ANATOP_TESTO_7) ++ ++#define MX6Q_PAD_SD1_DAT3__USDHC1_DAT3 (_MX6Q_PAD_SD1_DAT3__USDHC1_DAT3 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) ++#define MX6Q_PAD_SD1_DAT3__ECSPI5_SS2 (_MX6Q_PAD_SD1_DAT3__ECSPI5_SS2) ++#define MX6Q_PAD_SD1_DAT3__GPT_CMPOUT3 (_MX6Q_PAD_SD1_DAT3__GPT_CMPOUT3) ++#define MX6Q_PAD_SD1_DAT3__PWM1_PWMO (_MX6Q_PAD_SD1_DAT3__PWM1_PWMO) ++#define MX6Q_PAD_SD1_DAT3__WDOG2_WDOG_B (_MX6Q_PAD_SD1_DAT3__WDOG2_WDOG_B) ++#define MX6Q_PAD_SD1_DAT3__GPIO_1_21 (_MX6Q_PAD_SD1_DAT3__GPIO_1_21) ++#define MX6Q_PAD_SD1_DAT3__WDOG2_WDOG_RST_B_DEB (_MX6Q_PAD_SD1_DAT3__WDOG2_WDOG_RST_B_DEB) ++#define MX6Q_PAD_SD1_DAT3__ANATOP_ANATOP_TESTO_6 (_MX6Q_PAD_SD1_DAT3__ANATOP_ANATOP_TESTO_6) ++ ++#define MX6Q_PAD_SD1_CMD__USDHC1_CMD (_MX6Q_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) ++#define MX6Q_PAD_SD1_CMD__ECSPI5_MOSI (_MX6Q_PAD_SD1_CMD__ECSPI5_MOSI) ++#define MX6Q_PAD_SD1_CMD__PWM4_PWMO (_MX6Q_PAD_SD1_CMD__PWM4_PWMO) ++#define MX6Q_PAD_SD1_CMD__GPT_CMPOUT1 (_MX6Q_PAD_SD1_CMD__GPT_CMPOUT1) ++#define MX6Q_PAD_SD1_CMD__GPIO_1_18 (_MX6Q_PAD_SD1_CMD__GPIO_1_18) ++#define MX6Q_PAD_SD1_CMD__ANATOP_ANATOP_TESTO_5 (_MX6Q_PAD_SD1_CMD__ANATOP_ANATOP_TESTO_5) ++ ++#define MX6Q_PAD_SD1_DAT2__USDHC1_DAT2 (_MX6Q_PAD_SD1_DAT2__USDHC1_DAT2 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) ++#define MX6Q_PAD_SD1_DAT2__ECSPI5_SS1 (_MX6Q_PAD_SD1_DAT2__ECSPI5_SS1) ++#define MX6Q_PAD_SD1_DAT2__GPT_CMPOUT2 (_MX6Q_PAD_SD1_DAT2__GPT_CMPOUT2) ++#define MX6Q_PAD_SD1_DAT2__PWM2_PWMO (_MX6Q_PAD_SD1_DAT2__PWM2_PWMO) ++#define MX6Q_PAD_SD1_DAT2__WDOG1_WDOG_B (_MX6Q_PAD_SD1_DAT2__WDOG1_WDOG_B) ++#define MX6Q_PAD_SD1_DAT2__GPIO_1_19 (_MX6Q_PAD_SD1_DAT2__GPIO_1_19) ++#define MX6Q_PAD_SD1_DAT2__WDOG1_WDOG_RST_B_DEB (_MX6Q_PAD_SD1_DAT2__WDOG1_WDOG_RST_B_DEB) ++#define MX6Q_PAD_SD1_DAT2__ANATOP_ANATOP_TESTO_4 (_MX6Q_PAD_SD1_DAT2__ANATOP_ANATOP_TESTO_4) ++ ++#define MX6Q_PAD_SD1_CLK__USDHC1_CLK (_MX6Q_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) ++#define MX6Q_PAD_SD1_CLK__ECSPI5_SCLK (_MX6Q_PAD_SD1_CLK__ECSPI5_SCLK) ++#define MX6Q_PAD_SD1_CLK__OSC32K_32K_OUT (_MX6Q_PAD_SD1_CLK__OSC32K_32K_OUT) ++#define MX6Q_PAD_SD1_CLK__GPT_CLKIN (_MX6Q_PAD_SD1_CLK__GPT_CLKIN) ++#define MX6Q_PAD_SD1_CLK__GPIO_1_20 (_MX6Q_PAD_SD1_CLK__GPIO_1_20) ++#define MX6Q_PAD_SD1_CLK__PHY_DTB_0 (_MX6Q_PAD_SD1_CLK__PHY_DTB_0) ++#define MX6Q_PAD_SD1_CLK__SATA_PHY_DTB_0 (_MX6Q_PAD_SD1_CLK__SATA_PHY_DTB_0) ++ ++#define MX6Q_PAD_SD2_CLK__USDHC2_CLK (_MX6Q_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) ++#define MX6Q_PAD_SD2_CLK__ECSPI5_SCLK (_MX6Q_PAD_SD2_CLK__ECSPI5_SCLK) ++#define MX6Q_PAD_SD2_CLK__KPP_COL_5 (_MX6Q_PAD_SD2_CLK__KPP_COL_5) ++#define MX6Q_PAD_SD2_CLK__AUDMUX_AUD4_RXFS (_MX6Q_PAD_SD2_CLK__AUDMUX_AUD4_RXFS) ++#define MX6Q_PAD_SD2_CLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_9 (_MX6Q_PAD_SD2_CLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_9) ++#define MX6Q_PAD_SD2_CLK__GPIO_1_10 (_MX6Q_PAD_SD2_CLK__GPIO_1_10) ++#define MX6Q_PAD_SD2_CLK__PHY_DTB_1 (_MX6Q_PAD_SD2_CLK__PHY_DTB_1) ++#define MX6Q_PAD_SD2_CLK__SATA_PHY_DTB_1 (_MX6Q_PAD_SD2_CLK__SATA_PHY_DTB_1) ++ ++#define MX6Q_PAD_SD2_CMD__USDHC2_CMD (_MX6Q_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) ++#define MX6Q_PAD_SD2_CMD__ECSPI5_MOSI (_MX6Q_PAD_SD2_CMD__ECSPI5_MOSI) ++#define MX6Q_PAD_SD2_CMD__KPP_ROW_5 (_MX6Q_PAD_SD2_CMD__KPP_ROW_5) ++#define MX6Q_PAD_SD2_CMD__AUDMUX_AUD4_RXC (_MX6Q_PAD_SD2_CMD__AUDMUX_AUD4_RXC) ++#define MX6Q_PAD_SD2_CMD__PCIE_CTRL_DIAG_STATUS_BUS_MUX_10 (_MX6Q_PAD_SD2_CMD__PCIE_CTRL_DIAG_STATUS_BUS_MUX_10) ++#define MX6Q_PAD_SD2_CMD__GPIO_1_11 (_MX6Q_PAD_SD2_CMD__GPIO_1_11) ++ ++#define MX6Q_PAD_SD2_DAT3__USDHC2_DAT3 (_MX6Q_PAD_SD2_DAT3__USDHC2_DAT3 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) ++#define MX6Q_PAD_SD2_DAT3__ECSPI5_SS3 (_MX6Q_PAD_SD2_DAT3__ECSPI5_SS3) ++#define MX6Q_PAD_SD2_DAT3__KPP_COL_6 (_MX6Q_PAD_SD2_DAT3__KPP_COL_6) ++#define MX6Q_PAD_SD2_DAT3__AUDMUX_AUD4_TXC (_MX6Q_PAD_SD2_DAT3__AUDMUX_AUD4_TXC) ++#define MX6Q_PAD_SD2_DAT3__PCIE_CTRL_DIAG_STATUS_BUS_MUX_11 (_MX6Q_PAD_SD2_DAT3__PCIE_CTRL_DIAG_STATUS_BUS_MUX_11) ++#define MX6Q_PAD_SD2_DAT3__GPIO_1_12 (_MX6Q_PAD_SD2_DAT3__GPIO_1_12) ++#define MX6Q_PAD_SD2_DAT3__SJC_DONE (_MX6Q_PAD_SD2_DAT3__SJC_DONE) ++#define MX6Q_PAD_SD2_DAT3__ANATOP_ANATOP_TESTO_3 (_MX6Q_PAD_SD2_DAT3__ANATOP_ANATOP_TESTO_3) ++ ++#endif diff --cc arch/arm/include/asm/arch-mx6/iomux-v3.h index 788b413219,0000000000..bf394370c7 mode 100644,000000..100644 --- a/arch/arm/include/asm/arch-mx6/iomux-v3.h +++ b/arch/arm/include/asm/arch-mx6/iomux-v3.h @@@ -1,214 -1,0 +1,219 @@@ +/* + * Based on Linux i.MX iomux-v3.h file: + * Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH, + * + * + * Copyright (C) 2011 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301, USA. + */ + +#ifndef __MACH_IOMUX_V3_H__ +#define __MACH_IOMUX_V3_H__ + +/* + * build IOMUX_PAD structure + * + * This iomux scheme is based around pads, which are the physical balls + * on the processor. + * + * - Each pad has a pad control register (IOMUXC_SW_PAD_CTRL_x) which controls + * things like driving strength and pullup/pulldown. + * - Each pad can have but not necessarily does have an output routing register + * (IOMUXC_SW_MUX_CTL_PAD_x). + * - Each pad can have but not necessarily does have an input routing register + * (IOMUXC_x_SELECT_INPUT) + * + * The three register sets do not have a fixed offset to each other, + * hence we order this table by pad control registers (which all pads + * have) and put the optional i/o routing registers into additional + * fields. + * + * The naming convention for the pad modes is SOC_PAD___ + * If or refers to a GPIO, it is named GPIO__ + * + * IOMUX/PAD Bit field definitions + * - * MUX_CTRL_OFS: 0..11 (12) - * PAD_CTRL_OFS: 12..23 (12) - * SEL_INPUT_OFS: 24..35 (12) - * MUX_MODE + SION: 36..40 (5) - * PAD_CTRL + NO_PAD_CTRL: 41..58 (18) - * SEL_INP: 59..62 (4) - * reserved: 63 (1) ++ * MUX_CTRL_OFS: 0..11 (12) ++ * PAD_CTRL_OFS: 12..23 (12) ++ * SEL_INPUT_OFS: 24..35 (12) ++ * MUX_MODE + SION: 36..40 (5) ++ * PAD_CTRL + PAD_CTRL_VALID: 41..58 (18) ++ * SEL_INP: 59..61 (3) ++ * reserved: 62..63 (2) +*/ + +typedef u64 iomux_v3_cfg_t; + +#define MUX_CTRL_OFS_SHIFT 0 +#define MUX_CTRL_OFS_MASK ((iomux_v3_cfg_t)0xfff << MUX_CTRL_OFS_SHIFT) +#define MUX_PAD_CTRL_OFS_SHIFT 12 +#define MUX_PAD_CTRL_OFS_MASK ((iomux_v3_cfg_t)0xfff << \ + MUX_PAD_CTRL_OFS_SHIFT) +#define MUX_SEL_INPUT_OFS_SHIFT 24 +#define MUX_SEL_INPUT_OFS_MASK ((iomux_v3_cfg_t)0xfff << \ + MUX_SEL_INPUT_OFS_SHIFT) + +#define MUX_MODE_SHIFT 36 +#define MUX_MODE_MASK ((iomux_v3_cfg_t)0x1f << MUX_MODE_SHIFT) +#define MUX_PAD_CTRL_SHIFT 41 - #define MUX_PAD_CTRL_MASK ((iomux_v3_cfg_t)0x3ffff << MUX_PAD_CTRL_SHIFT) ++#define MUX_PAD_CTRL_MASK ((iomux_v3_cfg_t)0x1ffff << MUX_PAD_CTRL_SHIFT) +#define MUX_SEL_INPUT_SHIFT 59 - #define MUX_SEL_INPUT_MASK ((iomux_v3_cfg_t)0xf << MUX_SEL_INPUT_SHIFT) ++#define MUX_SEL_INPUT_MASK ((iomux_v3_cfg_t)0x7 << MUX_SEL_INPUT_SHIFT) + - #define MUX_PAD_CTRL(x) ((iomux_v3_cfg_t)(x) << MUX_PAD_CTRL_SHIFT) ++#define MUX_PAD_CTRL(x) (((iomux_v3_cfg_t)(x) << MUX_PAD_CTRL_SHIFT) | \ ++ PAD_CTRL_VALID) + +#define IOMUX_PAD(pad_ctrl_ofs, mux_ctrl_ofs, mux_mode, sel_input_ofs, \ + sel_input, pad_ctrl) \ + (((iomux_v3_cfg_t)(mux_ctrl_ofs) << MUX_CTRL_OFS_SHIFT) | \ + ((iomux_v3_cfg_t)(mux_mode) << MUX_MODE_SHIFT) | \ + ((iomux_v3_cfg_t)(pad_ctrl_ofs) << MUX_PAD_CTRL_OFS_SHIFT) | \ + ((iomux_v3_cfg_t)(pad_ctrl) << MUX_PAD_CTRL_SHIFT) | \ + ((iomux_v3_cfg_t)(sel_input_ofs) << MUX_SEL_INPUT_OFS_SHIFT)| \ + ((iomux_v3_cfg_t)(sel_input) << MUX_SEL_INPUT_SHIFT)) + - #define NO_PAD_CTRL (1 << 17) - #define GPIO_PIN_MASK 0x1f ++#define NO_MUX_I 0 ++#define NO_PAD_I 0 ++ ++#define PAD_CTRL_VALID ((iomux_v3_cfg_t)1 << (MUX_PAD_CTRL_SHIFT + 17)) ++ ++#define GPIO_PIN_MASK 0xf +#define GPIO_PORT_SHIFT 5 +#define GPIO_PORT_MASK (0x7 << GPIO_PORT_SHIFT) +#define GPIO_PORTA (0 << GPIO_PORT_SHIFT) +#define GPIO_PORTB (1 << GPIO_PORT_SHIFT) +#define GPIO_PORTC (2 << GPIO_PORT_SHIFT) +#define GPIO_PORTD (3 << GPIO_PORT_SHIFT) +#define GPIO_PORTE (4 << GPIO_PORT_SHIFT) +#define GPIO_PORTF (5 << GPIO_PORT_SHIFT) + - #define MUX_CONFIG_SION (0x1 << 4) ++#define IOMUX_CONFIG_SION (0x1 << 4) + +int imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad); - int imx_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t *pad_list, unsigned count); ++int imx_iomux_v3_setup_multiple_pads(const iomux_v3_cfg_t *pad_list, unsigned count); + +/* + * IOMUXC_GPR13 bit fields + */ - #define IOMUXC_GPR13_SDMA_STOP_REQ (1<<30) - #define IOMUXC_GPR13_CAN2_STOP_REQ (1<<29) - #define IOMUXC_GPR13_CAN1_STOP_REQ (1<<28) - #define IOMUXC_GPR13_ENET_STOP_REQ (1<<27) - #define IOMUXC_GPR13_SATA_PHY_8_MASK (7<<24) - #define IOMUXC_GPR13_SATA_PHY_7_MASK (0x1f<<19) ++#define IOMUXC_GPR13_SDMA_STOP_REQ (1 << 30) ++#define IOMUXC_GPR13_CAN2_STOP_REQ (1 << 29) ++#define IOMUXC_GPR13_CAN1_STOP_REQ (1 << 28) ++#define IOMUXC_GPR13_ENET_STOP_REQ (1 << 27) ++#define IOMUXC_GPR13_SATA_PHY_8_MASK (7 << 24) ++#define IOMUXC_GPR13_SATA_PHY_7_MASK (0x1f << 19) +#define IOMUXC_GPR13_SATA_PHY_6_SHIFT 16 - #define IOMUXC_GPR13_SATA_PHY_6_MASK (7< -#include -- --/* Use to set PAD control */ --#define PAD_CTL_HYS (1 << 16) --#define PAD_CTL_PUS_100K_DOWN (0 << 14) --#define PAD_CTL_PUS_47K_UP (1 << 14) --#define PAD_CTL_PUS_100K_UP (2 << 14) --#define PAD_CTL_PUS_22K_UP (3 << 14) -- --#define PAD_CTL_PUE (1 << 13) --#define PAD_CTL_PKE (1 << 12) --#define PAD_CTL_ODE (1 << 11) --#define PAD_CTL_SPEED_LOW (1 << 6) --#define PAD_CTL_SPEED_MED (2 << 6) --#define PAD_CTL_SPEED_HIGH (3 << 6) --#define PAD_CTL_DSE_DISABLE (0 << 3) --#define PAD_CTL_DSE_240ohm (1 << 3) --#define PAD_CTL_DSE_120ohm (2 << 3) --#define PAD_CTL_DSE_80ohm (3 << 3) --#define PAD_CTL_DSE_60ohm (4 << 3) --#define PAD_CTL_DSE_48ohm (5 << 3) --#define PAD_CTL_DSE_40ohm (6 << 3) --#define PAD_CTL_DSE_34ohm (7 << 3) --#define PAD_CTL_SRE_FAST (1 << 0) --#define PAD_CTL_SRE_SLOW (0 << 0) -- - #define NO_MUX_I 0x3FF - #define NO_PAD_I 0x7FF -#define NO_MUX_I 0 -#define NO_PAD_I 0 -- --enum { -- MX6Q_PAD_SD2_DAT1__USDHC2_DAT1 = IOMUX_PAD(0x0360, 0x004C, 0, 0x0000, 0, 0), -- MX6Q_PAD_SD2_DAT1__ECSPI5_SS0 = IOMUX_PAD(0x0360, 0x004C, 1, 0x0834, 0, 0), -- MX6Q_PAD_SD2_DAT1__WEIM_WEIM_CS_2 = IOMUX_PAD(0x0360, 0x004C, 2, 0x0000, 0, 0), -- MX6Q_PAD_SD2_DAT1__AUDMUX_AUD4_TXFS = IOMUX_PAD(0x0360, 0x004C, 3, 0x07C8, 0, 0), -- MX6Q_PAD_SD2_DAT1__KPP_COL_7 = IOMUX_PAD(0x0360, 0x004C, 4, 0x08F0, 0, 0), -- MX6Q_PAD_SD2_DAT1__GPIO_1_14 = IOMUX_PAD(0x0360, 0x004C, 5, 0x0000, 0, 0), -- MX6Q_PAD_SD2_DAT1__CCM_WAIT = IOMUX_PAD(0x0360, 0x004C, 6, 0x0000, 0, 0), -- MX6Q_PAD_SD2_DAT1__ANATOP_TESTO_0 = IOMUX_PAD(0x0360, 0x004C, 7, 0x0000, 0, 0), -- MX6Q_PAD_SD2_DAT2__USDHC2_DAT2 = IOMUX_PAD(0x0364, 0x0050, 0, 0x0000, 0, 0), -- MX6Q_PAD_SD2_DAT2__ECSPI5_SS1 = IOMUX_PAD(0x0364, 0x0050, 1, 0x0838, 0, 0), -- MX6Q_PAD_SD2_DAT2__WEIM_WEIM_CS_3 = IOMUX_PAD(0x0364, 0x0050, 2, 0x0000, 0, 0), -- MX6Q_PAD_SD2_DAT2__AUDMUX_AUD4_TXD = IOMUX_PAD(0x0364, 0x0050, 3, 0x07B8, 0, 0), -- MX6Q_PAD_SD2_DAT2__KPP_ROW_6 = IOMUX_PAD(0x0364, 0x0050, 4, 0x08F8, 0, 0), -- MX6Q_PAD_SD2_DAT2__GPIO_1_13 = IOMUX_PAD(0x0364, 0x0050, 5, 0x0000, 0, 0), -- MX6Q_PAD_SD2_DAT2__CCM_STOP = IOMUX_PAD(0x0364, 0x0050, 6, 0x0000, 0, 0), -- MX6Q_PAD_SD2_DAT2__ANATOP_TESTO_1 = IOMUX_PAD(0x0364, 0x0050, 7, 0x0000, 0, 0), -- MX6Q_PAD_SD2_DAT0__USDHC2_DAT0 = IOMUX_PAD(0x0368, 0x0054, 0, 0x0000, 0, 0), -- MX6Q_PAD_SD2_DAT0__ECSPI5_MISO = IOMUX_PAD(0x0368, 0x0054, 1, 0x082C, 0, 0), -- MX6Q_PAD_SD2_DAT0__AUDMUX_AUD4_RXD = IOMUX_PAD(0x0368, 0x0054, 3, 0x07B4, 0, 0), -- MX6Q_PAD_SD2_DAT0__KPP_ROW_7 = IOMUX_PAD(0x0368, 0x0054, 4, 0x08FC, 0, 0), -- MX6Q_PAD_SD2_DAT0__GPIO_1_15 = IOMUX_PAD(0x0368, 0x0054, 5, 0x0000, 0, 0), -- MX6Q_PAD_SD2_DAT0__DCIC2_DCIC_OUT = IOMUX_PAD(0x0368, 0x0054, 6, 0x0000, 0, 0), -- MX6Q_PAD_SD2_DAT0__TESTO_2 = IOMUX_PAD(0x0368, 0x0054, 7, 0x0000, 0, 0), -- MX6Q_PAD_RGMII_TXC__USBOH3_H2_DATA = IOMUX_PAD(0x036C, 0x0058, 0, 0x0000, 0, 0), -- MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC = IOMUX_PAD(0x036C, 0x0058, 1, 0x0000, 0, 0), -- MX6Q_PAD_RGMII_TXC__SPDIF_SPDIF_EXTCLK = IOMUX_PAD(0x036C, 0x0058, 2, 0x0918, 0, 0), -- MX6Q_PAD_RGMII_TXC__GPIO_6_19 = IOMUX_PAD(0x036C, 0x0058, 5, 0x0000, 0, 0), -- MX6Q_PAD_RGMII_TXC__MIPI_CORE_DPHY_IN_0 = IOMUX_PAD(0x036C, 0x0058, 6, 0x0000, 0, 0), -- MX6Q_PAD_RGMII_TXC__ANATOP_24M_OUT = IOMUX_PAD(0x036C, 0x0058, 7, 0x0000, 0, 0), -- MX6Q_PAD_RGMII_TD0__MIPI_HSI_CRL_TX_RDY = IOMUX_PAD(0x0370, 0x005C, 0, 0x0000, 0, 0), -- MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 = IOMUX_PAD(0x0370, 0x005C, 1, 0x0000, 0, 0), -- MX6Q_PAD_RGMII_TD0__GPIO_6_20 = IOMUX_PAD(0x0370, 0x005C, 5, 0x0000, 0, 0), -- MX6Q_PAD_RGMII_TD0__MIPI_CORE_DPHY_IN_1 = IOMUX_PAD(0x0370, 0x005C, 6, 0x0000, 0, 0), -- MX6Q_PAD_RGMII_TD1__MIPI_HSI_CRL_RX_FLG = IOMUX_PAD(0x0374, 0x0060, 0, 0x0000, 0, 0), -- MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 = IOMUX_PAD(0x0374, 0x0060, 1, 0x0000, 0, 0), -- MX6Q_PAD_RGMII_TD1__GPIO_6_21 = IOMUX_PAD(0x0374, 0x0060, 5, 0x0000, 0, 0), -- MX6Q_PAD_RGMII_TD1__MIPI_CORE_DPHY_IN_2 = IOMUX_PAD(0x0374, 0x0060, 6, 0x0000, 0, 0), -- MX6Q_PAD_RGMII_TD1__CCM_PLL3_BYP = IOMUX_PAD(0x0374, 0x0060, 7, 0x0000, 0, 0), -- MX6Q_PAD_RGMII_TD2__MIPI_HSI_CRL_RX_DTA = IOMUX_PAD(0x0378, 0x0064, 0, 0x0000, 0, 0), -- MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 = IOMUX_PAD(0x0378, 0x0064, 1, 0x0000, 0, 0), -- MX6Q_PAD_RGMII_TD2__GPIO_6_22 = IOMUX_PAD(0x0378, 0x0064, 5, 0x0000, 0, 0), -- MX6Q_PAD_RGMII_TD2__MIPI_CORE_DPHY_IN_3 = IOMUX_PAD(0x0378, 0x0064, 6, 0x0000, 0, 0), -- MX6Q_PAD_RGMII_TD2__CCM_PLL2_BYP = IOMUX_PAD(0x0378, 0x0064, 7, 0x0000, 0, 0), -- MX6Q_PAD_RGMII_TD3__MIPI_HSI_CRL_RX_WAK = IOMUX_PAD(0x037C, 0x0068, 0, 0x0000, 0, 0), -- MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 = IOMUX_PAD(0x037C, 0x0068, 1, 0x0000, 0, 0), -- MX6Q_PAD_RGMII_TD3__GPIO_6_23 = IOMUX_PAD(0x037C, 0x0068, 5, 0x0000, 0, 0), -- MX6Q_PAD_RGMII_TD3__MIPI_CORE_DPHY_IN_4 = IOMUX_PAD(0x037C, 0x0068, 6, 0x0000, 0, 0), -- MX6Q_PAD_RGMII_RX_CTL__USBOH3_H3_DATA = IOMUX_PAD(0x0380, 0x006C, 0, 0x0000, 0, 0), -- MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL = IOMUX_PAD(0x0380, 0x006C, 1, 0x0858, 0, 0), -- MX6Q_PAD_RGMII_RX_CTL__GPIO_6_24 = IOMUX_PAD(0x0380, 0x006C, 5, 0x0000, 0, 0), -- MX6Q_PAD_RGMII_RX_CTL__MIPI_DPHY_IN_5 = IOMUX_PAD(0x0380, 0x006C, 6, 0x0000, 0, 0), -- MX6Q_PAD_RGMII_RD0__MIPI_HSI_CRL_RX_RDY = IOMUX_PAD(0x0384, 0x0070, 0, 0x0000, 0, 0), -- MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 = IOMUX_PAD(0x0384, 0x0070, 1, 0x0848, 0, 0), -- MX6Q_PAD_RGMII_RD0__GPIO_6_25 = IOMUX_PAD(0x0384, 0x0070, 5, 0x0000, 0, 0), -- MX6Q_PAD_RGMII_RD0__MIPI_CORE_DPHY_IN_6 = IOMUX_PAD(0x0384, 0x0070, 6, 0x0000, 0, 0), -- MX6Q_PAD_RGMII_TX_CTL__USBOH3_H2_STROBE = IOMUX_PAD(0x0388, 0x0074, 0, 0x0000, 0, 0), -- MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL = IOMUX_PAD(0x0388, 0x0074, 1, 0x0000, 0, 0), -- MX6Q_PAD_RGMII_TX_CTL__GPIO_6_26 = IOMUX_PAD(0x0388, 0x0074, 5, 0x0000, 0, 0), -- MX6Q_PAD_RGMII_TX_CTL__CORE_DPHY_IN_7 = IOMUX_PAD(0x0388, 0x0074, 6, 0x0000, 0, 0), -- MX6Q_PAD_RGMII_TX_CTL__ANATOP_REF_OUT = IOMUX_PAD(0x0388, 0x0074, 7, 0x083C, 0, 0), -- MX6Q_PAD_RGMII_RD1__MIPI_HSI_CTRL_TX_FL = IOMUX_PAD(0x038C, 0x0078, 0, 0x0000, 0, 0), -- MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 = IOMUX_PAD(0x038C, 0x0078, 1, 0x084C, 0, 0), -- MX6Q_PAD_RGMII_RD1__GPIO_6_27 = IOMUX_PAD(0x038C, 0x0078, 5, 0x0000, 0, 0), -- MX6Q_PAD_RGMII_RD1__CORE_DPHY_TEST_IN_8 = IOMUX_PAD(0x038C, 0x0078, 6, 0x0000, 0, 0), -- MX6Q_PAD_RGMII_RD1__SJC_FAIL = IOMUX_PAD(0x038C, 0x0078, 7, 0x0000, 0, 0), -- MX6Q_PAD_RGMII_RD2__MIPI_HSI_CRL_TX_DTA = IOMUX_PAD(0x0390, 0x007C, 0, 0x0000, 0, 0), -- MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 = IOMUX_PAD(0x0390, 0x007C, 1, 0x0850, 0, 0), -- MX6Q_PAD_RGMII_RD2__GPIO_6_28 = IOMUX_PAD(0x0390, 0x007C, 5, 0x0000, 0, 0), -- MX6Q_PAD_RGMII_RD2__MIPI_CORE_DPHY_IN_9 = IOMUX_PAD(0x0390, 0x007C, 6, 0x0000, 0, 0), -- MX6Q_PAD_RGMII_RD3__MIPI_HSI_CRL_TX_WAK = IOMUX_PAD(0x0394, 0x0080, 0, 0x0000, 0, 0), -- MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 = IOMUX_PAD(0x0394, 0x0080, 1, 0x0854, 0, 0), -- MX6Q_PAD_RGMII_RD3__GPIO_6_29 = IOMUX_PAD(0x0394, 0x0080, 5, 0x0000, 0, 0), -- MX6Q_PAD_RGMII_RD3__MIPI_CORE_DPHY_IN10 = IOMUX_PAD(0x0394, 0x0080, 6, 0x0000, 0, 0), -- MX6Q_PAD_RGMII_RXC__USBOH3_H3_STROBE = IOMUX_PAD(0x0398, 0x0084, 0, 0x0000, 0, 0), -- MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC = IOMUX_PAD(0x0398, 0x0084, 1, 0x0844, 0, 0), -- MX6Q_PAD_RGMII_RXC__GPIO_6_30 = IOMUX_PAD(0x0398, 0x0084, 5, 0x0000, 0, 0), -- MX6Q_PAD_RGMII_RXC__MIPI_CORE_DPHY_IN11 = IOMUX_PAD(0x0398, 0x0084, 6, 0x0000, 0, 0), -- MX6Q_PAD_EIM_A25__WEIM_WEIM_A_25 = IOMUX_PAD(0x039C, 0x0088, 0, 0x0000, 0, 0), -- MX6Q_PAD_EIM_A25__ECSPI4_SS1 = IOMUX_PAD(0x039C, 0x0088, 1, 0x0000, 0, 0), -- MX6Q_PAD_EIM_A25__ECSPI2_RDY = IOMUX_PAD(0x039C, 0x0088, 2, 0x0000, 0, 0), -- MX6Q_PAD_EIM_A25__IPU1_DI1_PIN12 = IOMUX_PAD(0x039C, 0x0088, 3, 0x0000, 0, 0), -- MX6Q_PAD_EIM_A25__IPU1_DI0_D1_CS = IOMUX_PAD(0x039C, 0x0088, 4, 0x0000, 0, 0), -- MX6Q_PAD_EIM_A25__GPIO_5_2 = IOMUX_PAD(0x039C, 0x0088, 5, 0x0000, 0, 0), -- MX6Q_PAD_EIM_A25__HDMI_TX_CEC_LINE = IOMUX_PAD(0x039C, 0x0088, 6, 0x088C, 0, 0), -- MX6Q_PAD_EIM_A25__PL301_PER1_HBURST_0 = IOMUX_PAD(0x039C, 0x0088, 7, 0x0000, 0, 0), -- MX6Q_PAD_EIM_EB2__WEIM_WEIM_EB_2 = IOMUX_PAD(0x03A0, 0x008C, 0, 0x0000, 0, 0), -- MX6Q_PAD_EIM_EB2__ECSPI1_SS0 = IOMUX_PAD(0x03A0, 0x008C, 1, 0x0800, 0, 0), -- MX6Q_PAD_EIM_EB2__CCM_DI1_EXT_CLK = IOMUX_PAD(0x03A0, 0x008C, 2, 0x07EC, 0, 0), -- MX6Q_PAD_EIM_EB2__IPU2_CSI1_D_19 = IOMUX_PAD(0x03A0, 0x008C, 3, 0x08D4, 0, 0), -- MX6Q_PAD_EIM_EB2__HDMI_TX_DDC_SCL = IOMUX_PAD(0x03A0, 0x008C, 4, 0x0890, 0, 0), -- MX6Q_PAD_EIM_EB2__GPIO_2_30 = IOMUX_PAD(0x03A0, 0x008C, 5, 0x0000, 0, 0), -- MX6Q_PAD_EIM_EB2__I2C2_SCL = IOMUX_PAD(0x03A0, 0x008C, 22, 0x08A0, 0, 0), -- MX6Q_PAD_EIM_EB2__SRC_BT_CFG_30 = IOMUX_PAD(0x03A0, 0x008C, 7, 0x0000, 0, 0), -- MX6Q_PAD_EIM_D16__WEIM_WEIM_D_16 = IOMUX_PAD(0x03A4, 0x0090, 0, 0x0000, 0, 0), -- MX6Q_PAD_EIM_D16__ECSPI1_SCLK = IOMUX_PAD(0x03A4, 0x0090, 1, 0x07F4, 0, 0), -- MX6Q_PAD_EIM_D16__IPU1_DI0_PIN5 = IOMUX_PAD(0x03A4, 0x0090, 2, 0x0000, 0, 0), -- MX6Q_PAD_EIM_D16__IPU2_CSI1_D_18 = IOMUX_PAD(0x03A4, 0x0090, 3, 0x08D0, 0, 0), -- MX6Q_PAD_EIM_D16__HDMI_TX_DDC_SDA = IOMUX_PAD(0x03A4, 0x0090, 4, 0x0894, 0, 0), -- MX6Q_PAD_EIM_D16__GPIO_3_16 = IOMUX_PAD(0x03A4, 0x0090, 5, 0x0000, 0, 0), -- MX6Q_PAD_EIM_D16__I2C2_SDA = IOMUX_PAD(0x03A4, 0x0090, 22, 0x08A4, 0, 0), -- MX6Q_PAD_EIM_D17__WEIM_WEIM_D_17 = IOMUX_PAD(0x03A8, 0x0094, 0, 0x0000, 0, 0), -- MX6Q_PAD_EIM_D17__ECSPI1_MISO = IOMUX_PAD(0x03A8, 0x0094, 1, 0x07F8, 0, 0), -- MX6Q_PAD_EIM_D17__IPU1_DI0_PIN6 = IOMUX_PAD(0x03A8, 0x0094, 2, 0x0000, 0, 0), -- MX6Q_PAD_EIM_D17__IPU2_CSI1_PIXCLK = IOMUX_PAD(0x03A8, 0x0094, 3, 0x08E0, 0, 0), -- MX6Q_PAD_EIM_D17__DCIC1_DCIC_OUT = IOMUX_PAD(0x03A8, 0x0094, 4, 0x0000, 0, 0), -- MX6Q_PAD_EIM_D17__GPIO_3_17 = IOMUX_PAD(0x03A8, 0x0094, 5, 0x0000, 0, 0), -- MX6Q_PAD_EIM_D17__I2C3_SCL = IOMUX_PAD(0x03A8, 0x0094, 22, 0x08A8, 0, 0), -- MX6Q_PAD_EIM_D17__PL301_PER1_HBURST_1 = IOMUX_PAD(0x03A8, 0x0094, 7, 0x0000, 0, 0), -- MX6Q_PAD_EIM_D18__WEIM_WEIM_D_18 = IOMUX_PAD(0x03AC, 0x0098, 0, 0x0000, 0, 0), -- MX6Q_PAD_EIM_D18__ECSPI1_MOSI = IOMUX_PAD(0x03AC, 0x0098, 1, 0x07FC, 0, 0), -- MX6Q_PAD_EIM_D18__IPU1_DI0_PIN7 = IOMUX_PAD(0x03AC, 0x0098, 2, 0x0000, 0, 0), -- MX6Q_PAD_EIM_D18__IPU2_CSI1_D_17 = IOMUX_PAD(0x03AC, 0x0098, 3, 0x08CC, 0, 0), -- MX6Q_PAD_EIM_D18__IPU1_DI1_D0_CS = IOMUX_PAD(0x03AC, 0x0098, 4, 0x0000, 0, 0), -- MX6Q_PAD_EIM_D18__GPIO_3_18 = IOMUX_PAD(0x03AC, 0x0098, 5, 0x0000, 0, 0), -- MX6Q_PAD_EIM_D18__I2C3_SDA = IOMUX_PAD(0x03AC, 0x0098, 22, 0x08AC, 0, 0), -- MX6Q_PAD_EIM_D18__PL301_PER1_HBURST_2 = IOMUX_PAD(0x03AC, 0x0098, 7, 0x0000, 0, 0), -- MX6Q_PAD_EIM_D19__WEIM_WEIM_D_19 = IOMUX_PAD(0x03B0, 0x009C, 0, 0x0000, 0, 0), -- MX6Q_PAD_EIM_D19__ECSPI1_SS1 = IOMUX_PAD(0x03B0, 0x009C, 1, 0x0804, 0, 0), -- MX6Q_PAD_EIM_D19__IPU1_DI0_PIN8 = IOMUX_PAD(0x03B0, 0x009C, 2, 0x0000, 0, 0), -- MX6Q_PAD_EIM_D19__IPU2_CSI1_D_16 = IOMUX_PAD(0x03B0, 0x009C, 3, 0x08C8, 0, 0), -- MX6Q_PAD_EIM_D19__UART1_CTS = IOMUX_PAD(0x03B0, 0x009C, 4, 0x091C, 0, 0), -- MX6Q_PAD_EIM_D19__GPIO_3_19 = IOMUX_PAD(0x03B0, 0x009C, 5, 0x0000, 0, 0), -- MX6Q_PAD_EIM_D19__EPIT1_EPITO = IOMUX_PAD(0x03B0, 0x009C, 6, 0x0000, 0, 0), -- MX6Q_PAD_EIM_D19__PL301MX6QPER1_HRESP = IOMUX_PAD(0x03B0, 0x009C, 7, 0x0000, 0, 0), -- MX6Q_PAD_EIM_D20__WEIM_WEIM_D_20 = IOMUX_PAD(0x03B4, 0x00A0, 0, 0x0000, 0, 0), -- MX6Q_PAD_EIM_D20__ECSPI4_SS0 = IOMUX_PAD(0x03B4, 0x00A0, 1, 0x0824, 0, 0), -- MX6Q_PAD_EIM_D20__IPU1_DI0_PIN16 = IOMUX_PAD(0x03B4, 0x00A0, 2, 0x0000, 0, 0), -- MX6Q_PAD_EIM_D20__IPU2_CSI1_D_15 = IOMUX_PAD(0x03B4, 0x00A0, 3, 0x08C4, 0, 0), -- MX6Q_PAD_EIM_D20__UART1_CTS = IOMUX_PAD(0x03B4, 0x00A0, 4, 0x0000, 0, 0), -- MX6Q_PAD_EIM_D20__UART1_RTS = IOMUX_PAD(0x03B4, 0x00A0, 4, 0x091C, 1, 0), -- MX6Q_PAD_EIM_D20__GPIO_3_20 = IOMUX_PAD(0x03B4, 0x00A0, 5, 0x0000, 0, 0), -- MX6Q_PAD_EIM_D20__EPIT2_EPITO = IOMUX_PAD(0x03B4, 0x00A0, 6, 0x0000, 0, 0), -- MX6Q_PAD_EIM_D21__WEIM_WEIM_D_21 = IOMUX_PAD(0x03B8, 0x00A4, 0, 0x0000, 0, 0), -- MX6Q_PAD_EIM_D21__ECSPI4_SCLK = IOMUX_PAD(0x03B8, 0x00A4, 1, 0x0000, 0, 0), -- MX6Q_PAD_EIM_D21__IPU1_DI0_PIN17 = IOMUX_PAD(0x03B8, 0x00A4, 2, 0x0000, 0, 0), -- MX6Q_PAD_EIM_D21__IPU2_CSI1_D_11 = IOMUX_PAD(0x03B8, 0x00A4, 3, 0x08B4, 0, 0), -- MX6Q_PAD_EIM_D21__USBOH3_USBOTG_OC = IOMUX_PAD(0x03B8, 0x00A4, 4, 0x0944, 0, 0), -- MX6Q_PAD_EIM_D21__GPIO_3_21 = IOMUX_PAD(0x03B8, 0x00A4, 5, 0x0000, 0, 0), -- MX6Q_PAD_EIM_D21__I2C1_SCL = IOMUX_PAD(0x03B8, 0x00A4, 22, 0x0898, 0, 0), -- MX6Q_PAD_EIM_D21__SPDIF_IN1 = IOMUX_PAD(0x03B8, 0x00A4, 7, 0x0914, 0, 0), -- MX6Q_PAD_EIM_D22__WEIM_WEIM_D_22 = IOMUX_PAD(0x03BC, 0x00A8, 0, 0x0000, 0, 0), -- MX6Q_PAD_EIM_D22__ECSPI4_MISO = IOMUX_PAD(0x03BC, 0x00A8, 1, 0x0000, 0, 0), -- MX6Q_PAD_EIM_D22__IPU1_DI0_PIN1 = IOMUX_PAD(0x03BC, 0x00A8, 2, 0x0000, 0, 0), -- MX6Q_PAD_EIM_D22__IPU2_CSI1_D_10 = IOMUX_PAD(0x03BC, 0x00A8, 3, 0x08B0, 0, 0), -- MX6Q_PAD_EIM_D22__USBOH3_USBOTG_PWR = IOMUX_PAD(0x03BC, 0x00A8, 4, 0x0000, 0, 0), -- MX6Q_PAD_EIM_D22__GPIO_3_22 = IOMUX_PAD(0x03BC, 0x00A8, 5, 0x0000, 0, 0), -- MX6Q_PAD_EIM_D22__SPDIF_OUT1 = IOMUX_PAD(0x03BC, 0x00A8, 6, 0x0000, 0, 0), -- MX6Q_PAD_EIM_D22__PL301MX6QPER1_HWRITE = IOMUX_PAD(0x03BC, 0x00A8, 7, 0x0000, 0, 0), -- MX6Q_PAD_EIM_D23__WEIM_WEIM_D_23 = IOMUX_PAD(0x03C0, 0x00AC, 0, 0x0000, 0, 0), -- MX6Q_PAD_EIM_D23__IPU1_DI0_D0_CS = IOMUX_PAD(0x03C0, 0x00AC, 1, 0x0000, 0, 0), -- MX6Q_PAD_EIM_D23__UART3_CTS = IOMUX_PAD(0x03C0, 0x00AC, 2, 0x092C, 0, 0), -- MX6Q_PAD_EIM_D23__UART1_DCD = IOMUX_PAD(0x03C0, 0x00AC, 3, 0x0000, 0, 0), -- MX6Q_PAD_EIM_D23__IPU2_CSI1_DATA_EN = IOMUX_PAD(0x03C0, 0x00AC, 4, 0x08D8, 0, 0), -- MX6Q_PAD_EIM_D23__GPIO_3_23 = IOMUX_PAD(0x03C0, 0x00AC, 5, 0x0000, 0, 0), -- MX6Q_PAD_EIM_D23__IPU1_DI1_PIN2 = IOMUX_PAD(0x03C0, 0x00AC, 6, 0x0000, 0, 0), -- MX6Q_PAD_EIM_D23__IPU1_DI1_PIN14 = IOMUX_PAD(0x03C0, 0x00AC, 7, 0x0000, 0, 0), -- MX6Q_PAD_EIM_EB3__WEIM_WEIM_EB_3 = IOMUX_PAD(0x03C4, 0x00B0, 0, 0x0000, 0, 0), -- MX6Q_PAD_EIM_EB3__ECSPI4_RDY = IOMUX_PAD(0x03C4, 0x00B0, 1, 0x0000, 0, 0), -- MX6Q_PAD_EIM_EB3__UART3_CTS = IOMUX_PAD(0x03C4, 0x00B0, 2, 0x0000, 0, 0), -- MX6Q_PAD_EIM_EB3__UART3_RTS = IOMUX_PAD(0x03C4, 0x00B0, 2, 0x092C, 1, 0), -- MX6Q_PAD_EIM_EB3__UART1_RI = IOMUX_PAD(0x03C4, 0x00B0, 3, 0x0000, 0, 0), -- MX6Q_PAD_EIM_EB3__IPU2_CSI1_HSYNC = IOMUX_PAD(0x03C4, 0x00B0, 4, 0x08DC, 0, 0), -- MX6Q_PAD_EIM_EB3__GPIO_2_31 = IOMUX_PAD(0x03C4, 0x00B0, 5, 0x0000, 0, 0), -- MX6Q_PAD_EIM_EB3__IPU1_DI1_PIN3 = IOMUX_PAD(0x03C4, 0x00B0, 6, 0x0000, 0, 0), -- MX6Q_PAD_EIM_EB3__SRC_BT_CFG_31 = IOMUX_PAD(0x03C4, 0x00B0, 7, 0x0000, 0, 0), -- MX6Q_PAD_EIM_D24__WEIM_WEIM_D_24 = IOMUX_PAD(0x03C8, 0x00B4, 0, 0x0000, 0, 0), -- MX6Q_PAD_EIM_D24__ECSPI4_SS2 = IOMUX_PAD(0x03C8, 0x00B4, 1, 0x0000, 0, 0), -- MX6Q_PAD_EIM_D24__UART3_TXD = IOMUX_PAD(0x03C8, 0x00B4, 2, 0x0000, 0, 0), -- MX6Q_PAD_EIM_D24__UART3_TXD_RXD = IOMUX_PAD(0x03C8, 0x00B4, 2, 0x0930, 0, 0), -- MX6Q_PAD_EIM_D24__ECSPI1_SS2 = IOMUX_PAD(0x03C8, 0x00B4, 3, 0x0808, 0, 0), -- MX6Q_PAD_EIM_D24__ECSPI2_SS2 = IOMUX_PAD(0x03C8, 0x00B4, 4, 0x0000, 0, 0), -- MX6Q_PAD_EIM_D24__GPIO_3_24 = IOMUX_PAD(0x03C8, 0x00B4, 5, 0x0000, 0, 0), -- MX6Q_PAD_EIM_D24__AUDMUX_AUD5_RXFS = IOMUX_PAD(0x03C8, 0x00B4, 6, 0x07D8, 0, 0), -- MX6Q_PAD_EIM_D24__UART1_DTR = IOMUX_PAD(0x03C8, 0x00B4, 7, 0x0000, 0, 0), -- MX6Q_PAD_EIM_D25__WEIM_WEIM_D_25 = IOMUX_PAD(0x03CC, 0x00B8, 0, 0x0000, 0, 0), -- MX6Q_PAD_EIM_D25__ECSPI4_SS3 = IOMUX_PAD(0x03CC, 0x00B8, 1, 0x0000, 0, 0), -- MX6Q_PAD_EIM_D25__UART3_RXD = IOMUX_PAD(0x03CC, 0x00B8, 2, 0x0930, 1, 0), -- MX6Q_PAD_EIM_D25__ECSPI1_SS3 = IOMUX_PAD(0x03CC, 0x00B8, 3, 0x080C, 0, 0), -- MX6Q_PAD_EIM_D25__ECSPI2_SS3 = IOMUX_PAD(0x03CC, 0x00B8, 4, 0x0000, 0, 0), -- MX6Q_PAD_EIM_D25__GPIO_3_25 = IOMUX_PAD(0x03CC, 0x00B8, 5, 0x0000, 0, 0), -- MX6Q_PAD_EIM_D25__AUDMUX_AUD5_RXC = IOMUX_PAD(0x03CC, 0x00B8, 6, 0x07D4, 0, 0), -- MX6Q_PAD_EIM_D25__UART1_DSR = IOMUX_PAD(0x03CC, 0x00B8, 7, 0x0000, 0, 0), -- MX6Q_PAD_EIM_D26__WEIM_WEIM_D_26 = IOMUX_PAD(0x03D0, 0x00BC, 0, 0x0000, 0, 0), -- MX6Q_PAD_EIM_D26__IPU1_DI1_PIN11 = IOMUX_PAD(0x03D0, 0x00BC, 1, 0x0000, 0, 0), -- MX6Q_PAD_EIM_D26__IPU1_CSI0_D_1 = IOMUX_PAD(0x03D0, 0x00BC, 2, 0x0000, 0, 0), -- MX6Q_PAD_EIM_D26__IPU2_CSI1_D_14 = IOMUX_PAD(0x03D0, 0x00BC, 3, 0x08C0, 0, 0), -- MX6Q_PAD_EIM_D26__UART2_TXD = IOMUX_PAD(0x03D0, 0x00BC, 4, 0x0000, 0, 0), -- MX6Q_PAD_EIM_D26__UART2_TXD_RXD = IOMUX_PAD(0x03D0, 0x00BC, 4, 0x0928, 0, 0), -- MX6Q_PAD_EIM_D26__GPIO_3_26 = IOMUX_PAD(0x03D0, 0x00BC, 5, 0x0000, 0, 0), -- MX6Q_PAD_EIM_D26__IPU1_SISG_2 = IOMUX_PAD(0x03D0, 0x00BC, 6, 0x0000, 0, 0), -- MX6Q_PAD_EIM_D26__IPU1_DISP1_DAT_22 = IOMUX_PAD(0x03D0, 0x00BC, 7, 0x0000, 0, 0), -- MX6Q_PAD_EIM_D27__WEIM_WEIM_D_27 = IOMUX_PAD(0x03D4, 0x00C0, 0, 0x0000, 0, 0), -- MX6Q_PAD_EIM_D27__IPU1_DI1_PIN13 = IOMUX_PAD(0x03D4, 0x00C0, 1, 0x0000, 0, 0), -- MX6Q_PAD_EIM_D27__IPU1_CSI0_D_0 = IOMUX_PAD(0x03D4, 0x00C0, 2, 0x0000, 0, 0), -- MX6Q_PAD_EIM_D27__IPU2_CSI1_D_13 = IOMUX_PAD(0x03D4, 0x00C0, 3, 0x08BC, 0, 0), -- MX6Q_PAD_EIM_D27__UART2_RXD = IOMUX_PAD(0x03D4, 0x00C0, 4, 0x0928, 1, 0), -- MX6Q_PAD_EIM_D27__GPIO_3_27 = IOMUX_PAD(0x03D4, 0x00C0, 5, 0x0000, 0, 0), -- MX6Q_PAD_EIM_D27__IPU1_SISG_3 = IOMUX_PAD(0x03D4, 0x00C0, 6, 0x0000, 0, 0), -- MX6Q_PAD_EIM_D27__IPU1_DISP1_DAT_23 = IOMUX_PAD(0x03D4, 0x00C0, 7, 0x0000, 0, 0), -- MX6Q_PAD_EIM_D28__WEIM_WEIM_D_28 = IOMUX_PAD(0x03D8, 0x00C4, 0, 0x0000, 0, 0), -- MX6Q_PAD_EIM_D28__I2C1_SDA = IOMUX_PAD(0x03D8, 0x00C4, 17, 0x089C, 0, 0), -- MX6Q_PAD_EIM_D28__ECSPI4_MOSI = IOMUX_PAD(0x03D8, 0x00C4, 2, 0x0000, 0, 0), -- MX6Q_PAD_EIM_D28__IPU2_CSI1_D_12 = IOMUX_PAD(0x03D8, 0x00C4, 3, 0x08B8, 0, 0), -- MX6Q_PAD_EIM_D28__UART2_CTS = IOMUX_PAD(0x03D8, 0x00C4, 4, 0x0924, 0, 0), -- MX6Q_PAD_EIM_D28__GPIO_3_28 = IOMUX_PAD(0x03D8, 0x00C4, 5, 0x0000, 0, 0), -- MX6Q_PAD_EIM_D28__IPU1_EXT_TRIG = IOMUX_PAD(0x03D8, 0x00C4, 6, 0x0000, 0, 0), -- MX6Q_PAD_EIM_D28__IPU1_DI0_PIN13 = IOMUX_PAD(0x03D8, 0x00C4, 7, 0x0000, 0, 0), -- MX6Q_PAD_EIM_D29__WEIM_WEIM_D_29 = IOMUX_PAD(0x03DC, 0x00C8, 0, 0x0000, 0, 0), -- MX6Q_PAD_EIM_D29__IPU1_DI1_PIN15 = IOMUX_PAD(0x03DC, 0x00C8, 1, 0x0000, 0, 0), -- MX6Q_PAD_EIM_D29__ECSPI4_SS0 = IOMUX_PAD(0x03DC, 0x00C8, 2, 0x0824, 1, 0), -- MX6Q_PAD_EIM_D29__UART2_CTS = IOMUX_PAD(0x03DC, 0x00C8, 4, 0x0000, 0, 0), -- MX6Q_PAD_EIM_D29__UART2_RTS = IOMUX_PAD(0x03DC, 0x00C8, 4, 0x0924, 1, 0), -- MX6Q_PAD_EIM_D29__GPIO_3_29 = IOMUX_PAD(0x03DC, 0x00C8, 5, 0x0000, 0, 0), -- MX6Q_PAD_EIM_D29__IPU2_CSI1_VSYNC = IOMUX_PAD(0x03DC, 0x00C8, 6, 0x08E4, 0, 0), -- MX6Q_PAD_EIM_D29__IPU1_DI0_PIN14 = IOMUX_PAD(0x03DC, 0x00C8, 7, 0x0000, 0, 0), -- MX6Q_PAD_EIM_D30__WEIM_WEIM_D_30 = IOMUX_PAD(0x03E0, 0x00CC, 0, 0x0000, 0, 0), -- MX6Q_PAD_EIM_D30__IPU1_DISP1_DAT_21 = IOMUX_PAD(0x03E0, 0x00CC, 1, 0x0000, 0, 0), -- MX6Q_PAD_EIM_D30__IPU1_DI0_PIN11 = IOMUX_PAD(0x03E0, 0x00CC, 2, 0x0000, 0, 0), -- MX6Q_PAD_EIM_D30__IPU1_CSI0_D_3 = IOMUX_PAD(0x03E0, 0x00CC, 3, 0x0000, 0, 0), -- MX6Q_PAD_EIM_D30__UART3_CTS = IOMUX_PAD(0x03E0, 0x00CC, 4, 0x092C, 2, 0), -- MX6Q_PAD_EIM_D30__GPIO_3_30 = IOMUX_PAD(0x03E0, 0x00CC, 5, 0x0000, 0, 0), -- MX6Q_PAD_EIM_D30__USBOH3_USBH1_OC = IOMUX_PAD(0x03E0, 0x00CC, 6, 0x0948, 0, 0), -- MX6Q_PAD_EIM_D30__PL301MX6QPER1_HPROT_0 = IOMUX_PAD(0x03E0, 0x00CC, 7, 0x0000, 0, 0), -- MX6Q_PAD_EIM_D31__WEIM_WEIM_D_31 = IOMUX_PAD(0x03E4, 0x00D0, 0, 0x0000, 0, 0), -- MX6Q_PAD_EIM_D31__IPU1_DISP1_DAT_20 = IOMUX_PAD(0x03E4, 0x00D0, 1, 0x0000, 0, 0), -- MX6Q_PAD_EIM_D31__IPU1_DI0_PIN12 = IOMUX_PAD(0x03E4, 0x00D0, 2, 0x0000, 0, 0), -- MX6Q_PAD_EIM_D31__IPU1_CSI0_D_2 = IOMUX_PAD(0x03E4, 0x00D0, 3, 0x0000, 0, 0), -- MX6Q_PAD_EIM_D31__UART3_CTS = IOMUX_PAD(0x03E4, 0x00D0, 4, 0x0000, 0, 0), -- MX6Q_PAD_EIM_D31__UART3_RTS = IOMUX_PAD(0x03E4, 0x00D0, 4, 0x092C, 3, 0), -- MX6Q_PAD_EIM_D31__GPIO_3_31 = IOMUX_PAD(0x03E4, 0x00D0, 5, 0x0000, 0, 0), -- MX6Q_PAD_EIM_D31__USBOH3_USBH1_PWR = IOMUX_PAD(0x03E4, 0x00D0, 6, 0x0000, 0, 0), -- MX6Q_PAD_EIM_D31__PL301MX6QPER1_HPROT_1 = IOMUX_PAD(0x03E4, 0x00D0, 7, 0x0000, 0, 0), -- MX6Q_PAD_EIM_A24__WEIM_WEIM_A_24 = IOMUX_PAD(0x03E8, 0x00D4, 0, 0x0000, 0, 0), -- MX6Q_PAD_EIM_A24__IPU1_DISP1_DAT_19 = IOMUX_PAD(0x03E8, 0x00D4, 1, 0x0000, 0, 0), -- MX6Q_PAD_EIM_A24__IPU2_CSI1_D_19 = IOMUX_PAD(0x03E8, 0x00D4, 2, 0x08D4, 1, 0), -- MX6Q_PAD_EIM_A24__IPU2_SISG_2 = IOMUX_PAD(0x03E8, 0x00D4, 3, 0x0000, 0, 0), -- MX6Q_PAD_EIM_A24__IPU1_SISG_2 = IOMUX_PAD(0x03E8, 0x00D4, 4, 0x0000, 0, 0), -- MX6Q_PAD_EIM_A24__GPIO_5_4 = IOMUX_PAD(0x03E8, 0x00D4, 5, 0x0000, 0, 0), -- MX6Q_PAD_EIM_A24__PL301MX6QPER1_HPROT_2 = IOMUX_PAD(0x03E8, 0x00D4, 6, 0x0000, 0, 0), -- MX6Q_PAD_EIM_A24__SRC_BT_CFG_24 = IOMUX_PAD(0x03E8, 0x00D4, 7, 0x0000, 0, 0), -- MX6Q_PAD_EIM_A23__WEIM_WEIM_A_23 = IOMUX_PAD(0x03EC, 0x00D8, 0, 0x0000, 0, 0), -- MX6Q_PAD_EIM_A23__IPU1_DISP1_DAT_18 = IOMUX_PAD(0x03EC, 0x00D8, 1, 0x0000, 0, 0), -- MX6Q_PAD_EIM_A23__IPU2_CSI1_D_18 = IOMUX_PAD(0x03EC, 0x00D8, 2, 0x08D0, 1, 0), -- MX6Q_PAD_EIM_A23__IPU2_SISG_3 = IOMUX_PAD(0x03EC, 0x00D8, 3, 0x0000, 0, 0), -- MX6Q_PAD_EIM_A23__IPU1_SISG_3 = IOMUX_PAD(0x03EC, 0x00D8, 4, 0x0000, 0, 0), -- MX6Q_PAD_EIM_A23__GPIO_6_6 = IOMUX_PAD(0x03EC, 0x00D8, 5, 0x0000, 0, 0), -- MX6Q_PAD_EIM_A23__PL301MX6QPER1_HPROT_3 = IOMUX_PAD(0x03EC, 0x00D8, 6, 0x0000, 0, 0), -- MX6Q_PAD_EIM_A23__SRC_BT_CFG_23 = IOMUX_PAD(0x03EC, 0x00D8, 7, 0x0000, 0, 0), -- MX6Q_PAD_EIM_A22__WEIM_WEIM_A_22 = IOMUX_PAD(0x03F0, 0x00DC, 0, 0x0000, 0, 0), -- MX6Q_PAD_EIM_A22__IPU1_DISP1_DAT_17 = IOMUX_PAD(0x03F0, 0x00DC, 1, 0x0000, 0, 0), -- MX6Q_PAD_EIM_A22__IPU2_CSI1_D_17 = IOMUX_PAD(0x03F0, 0x00DC, 2, 0x08CC, 1, 0), -- MX6Q_PAD_EIM_A22__GPIO_2_16 = IOMUX_PAD(0x03F0, 0x00DC, 5, 0x0000, 0, 0), -- MX6Q_PAD_EIM_A22__TPSMP_HDATA_0 = IOMUX_PAD(0x03F0, 0x00DC, 6, 0x0000, 0, 0), -- MX6Q_PAD_EIM_A22__SRC_BT_CFG_22 = IOMUX_PAD(0x03F0, 0x00DC, 7, 0x0000, 0, 0), -- MX6Q_PAD_EIM_A21__WEIM_WEIM_A_21 = IOMUX_PAD(0x03F4, 0x00E0, 0, 0x0000, 0, 0), -- MX6Q_PAD_EIM_A21__IPU1_DISP1_DAT_16 = IOMUX_PAD(0x03F4, 0x00E0, 1, 0x0000, 0, 0), -- MX6Q_PAD_EIM_A21__IPU2_CSI1_D_16 = IOMUX_PAD(0x03F4, 0x00E0, 2, 0x08C8, 1, 0), -- MX6Q_PAD_EIM_A21__RESERVED_RESERVED = IOMUX_PAD(0x03F4, 0x00E0, 3, 0x0000, 0, 0), -- MX6Q_PAD_EIM_A21__MIPI_CORE_DPHY_OUT_18 = IOMUX_PAD(0x03F4, 0x00E0, 4, 0x0000, 0, 0), -- MX6Q_PAD_EIM_A21__GPIO_2_17 = IOMUX_PAD(0x03F4, 0x00E0, 5, 0x0000, 0, 0), -- MX6Q_PAD_EIM_A21__TPSMP_HDATA_1 = IOMUX_PAD(0x03F4, 0x00E0, 6, 0x0000, 0, 0), -- MX6Q_PAD_EIM_A21__SRC_BT_CFG_21 = IOMUX_PAD(0x03F4, 0x00E0, 7, 0x0000, 0, 0), -- MX6Q_PAD_EIM_A20__WEIM_WEIM_A_20 = IOMUX_PAD(0x03F8, 0x00E4, 0, 0x0000, 0, 0), -- MX6Q_PAD_EIM_A20__IPU1_DISP1_DAT_15 = IOMUX_PAD(0x03F8, 0x00E4, 1, 0x0000, 0, 0), -- MX6Q_PAD_EIM_A20__IPU2_CSI1_D_15 = IOMUX_PAD(0x03F8, 0x00E4, 2, 0x08C4, 1, 0), -- MX6Q_PAD_EIM_A20__RESERVED_RESERVED = IOMUX_PAD(0x03F8, 0x00E4, 3, 0x0000, 0, 0), -- MX6Q_PAD_EIM_A20__MIPI_CORE_DPHY_OUT_19 = IOMUX_PAD(0x03F8, 0x00E4, 4, 0x0000, 0, 0), -- MX6Q_PAD_EIM_A20__GPIO_2_18 = IOMUX_PAD(0x03F8, 0x00E4, 5, 0x0000, 0, 0), -- MX6Q_PAD_EIM_A20__TPSMP_HDATA_2 = IOMUX_PAD(0x03F8, 0x00E4, 6, 0x0000, 0, 0), -- MX6Q_PAD_EIM_A20__SRC_BT_CFG_20 = IOMUX_PAD(0x03F8, 0x00E4, 7, 0x0000, 0, 0), -- MX6Q_PAD_EIM_A19__WEIM_WEIM_A_19 = IOMUX_PAD(0x03FC, 0x00E8, 0, 0x0000, 0, 0), -- MX6Q_PAD_EIM_A19__IPU1_DISP1_DAT_14 = IOMUX_PAD(0x03FC, 0x00E8, 1, 0x0000, 0, 0), -- MX6Q_PAD_EIM_A19__IPU2_CSI1_D_14 = IOMUX_PAD(0x03FC, 0x00E8, 2, 0x08C0, 1, 0), -- MX6Q_PAD_EIM_A19__RESERVED_RESERVED = IOMUX_PAD(0x03FC, 0x00E8, 3, 0x0000, 0, 0), -- MX6Q_PAD_EIM_A19__MIPI_CORE_DPHY_OUT_20 = IOMUX_PAD(0x03FC, 0x00E8, 4, 0x0000, 0, 0), -- MX6Q_PAD_EIM_A19__GPIO_2_19 = IOMUX_PAD(0x03FC, 0x00E8, 5, 0x0000, 0, 0), -- MX6Q_PAD_EIM_A19__TPSMP_HDATA_3 = IOMUX_PAD(0x03FC, 0x00E8, 6, 0x0000, 0, 0), -- MX6Q_PAD_EIM_A19__SRC_BT_CFG_19 = IOMUX_PAD(0x03FC, 0x00E8, 7, 0x0000, 0, 0), -- MX6Q_PAD_EIM_A18__WEIM_WEIM_A_18 = IOMUX_PAD(0x0400, 0x00EC, 0, 0x0000, 0, 0), -- MX6Q_PAD_EIM_A18__IPU1_DISP1_DAT_13 = IOMUX_PAD(0x0400, 0x00EC, 1, 0x0000, 0, 0), -- MX6Q_PAD_EIM_A18__IPU2_CSI1_D_13 = IOMUX_PAD(0x0400, 0x00EC, 2, 0x08BC, 1, 0), -- MX6Q_PAD_EIM_A18__RESERVED_RESERVED = IOMUX_PAD(0x0400, 0x00EC, 3, 0x0000, 0, 0), -- MX6Q_PAD_EIM_A18__MIPI_CORE_DPHY_OUT_21 = IOMUX_PAD(0x0400, 0x00EC, 4, 0x0000, 0, 0), -- MX6Q_PAD_EIM_A18__GPIO_2_20 = IOMUX_PAD(0x0400, 0x00EC, 5, 0x0000, 0, 0), -- MX6Q_PAD_EIM_A18__TPSMP_HDATA_4 = IOMUX_PAD(0x0400, 0x00EC, 6, 0x0000, 0, 0), -- MX6Q_PAD_EIM_A18__SRC_BT_CFG_18 = IOMUX_PAD(0x0400, 0x00EC, 7, 0x0000, 0, 0), -- MX6Q_PAD_EIM_A17__WEIM_WEIM_A_17 = IOMUX_PAD(0x0404, 0x00F0, 0, 0x0000, 0, 0), -- MX6Q_PAD_EIM_A17__IPU1_DISP1_DAT_12 = IOMUX_PAD(0x0404, 0x00F0, 1, 0x0000, 0, 0), -- MX6Q_PAD_EIM_A17__IPU2_CSI1_D_12 = IOMUX_PAD(0x0404, 0x00F0, 2, 0x08B8, 1, 0), -- MX6Q_PAD_EIM_A17__RESERVED_RESERVED = IOMUX_PAD(0x0404, 0x00F0, 3, 0x0000, 0, 0), -- MX6Q_PAD_EIM_A17__MIPI_CORE_DPHY_OUT_22 = IOMUX_PAD(0x0404, 0x00F0, 4, 0x0000, 0, 0), -- MX6Q_PAD_EIM_A17__GPIO_2_21 = IOMUX_PAD(0x0404, 0x00F0, 5, 0x0000, 0, 0), -- MX6Q_PAD_EIM_A17__TPSMP_HDATA_5 = IOMUX_PAD(0x0404, 0x00F0, 6, 0x0000, 0, 0), -- MX6Q_PAD_EIM_A17__SRC_BT_CFG_17 = IOMUX_PAD(0x0404, 0x00F0, 7, 0x0000, 0, 0), -- MX6Q_PAD_EIM_A16__WEIM_WEIM_A_16 = IOMUX_PAD(0x0408, 0x00F4, 0, 0x0000, 0, 0), -- MX6Q_PAD_EIM_A16__IPU1_DI1_DISP_CLK = IOMUX_PAD(0x0408, 0x00F4, 1, 0x0000, 0, 0), -- MX6Q_PAD_EIM_A16__IPU2_CSI1_PIXCLK = IOMUX_PAD(0x0408, 0x00F4, 2, 0x08E0, 1, 0), -- MX6Q_PAD_EIM_A16__MIPI_CORE_DPHY_OUT_23 = IOMUX_PAD(0x0408, 0x00F4, 4, 0x0000, 0, 0), -- MX6Q_PAD_EIM_A16__GPIO_2_22 = IOMUX_PAD(0x0408, 0x00F4, 5, 0x0000, 0, 0), -- MX6Q_PAD_EIM_A16__TPSMP_HDATA_6 = IOMUX_PAD(0x0408, 0x00F4, 6, 0x0000, 0, 0), -- MX6Q_PAD_EIM_A16__SRC_BT_CFG_16 = IOMUX_PAD(0x0408, 0x00F4, 7, 0x0000, 0, 0), -- MX6Q_PAD_EIM_CS0__WEIM_WEIM_CS_0 = IOMUX_PAD(0x040C, 0x00F8, 0, 0x0000, 0, 0), -- MX6Q_PAD_EIM_CS0__IPU1_DI1_PIN5 = IOMUX_PAD(0x040C, 0x00F8, 1, 0x0000, 0, 0), -- MX6Q_PAD_EIM_CS0__ECSPI2_SCLK = IOMUX_PAD(0x040C, 0x00F8, 2, 0x0810, 0, 0), -- MX6Q_PAD_EIM_CS0__MIPI_CORE_DPHY_OUT_24 = IOMUX_PAD(0x040C, 0x00F8, 4, 0x0000, 0, 0), -- MX6Q_PAD_EIM_CS0__GPIO_2_23 = IOMUX_PAD(0x040C, 0x00F8, 5, 0x0000, 0, 0), -- MX6Q_PAD_EIM_CS0__TPSMP_HDATA_7 = IOMUX_PAD(0x040C, 0x00F8, 6, 0x0000, 0, 0), -- MX6Q_PAD_EIM_CS1__WEIM_WEIM_CS_1 = IOMUX_PAD(0x0410, 0x00FC, 0, 0x0000, 0, 0), -- MX6Q_PAD_EIM_CS1__IPU1_DI1_PIN6 = IOMUX_PAD(0x0410, 0x00FC, 1, 0x0000, 0, 0), -- MX6Q_PAD_EIM_CS1__ECSPI2_MOSI = IOMUX_PAD(0x0410, 0x00FC, 2, 0x0818, 0, 0), -- MX6Q_PAD_EIM_CS1__MIPI_CORE_DPHY_OUT_25 = IOMUX_PAD(0x0410, 0x00FC, 4, 0x0000, 0, 0), -- MX6Q_PAD_EIM_CS1__GPIO_2_24 = IOMUX_PAD(0x0410, 0x00FC, 5, 0x0000, 0, 0), -- MX6Q_PAD_EIM_CS1__TPSMP_HDATA_8 = IOMUX_PAD(0x0410, 0x00FC, 6, 0x0000, 0, 0), -- MX6Q_PAD_EIM_OE__WEIM_WEIM_OE = IOMUX_PAD(0x0414, 0x0100, 0, 0x0000, 0, 0), -- MX6Q_PAD_EIM_OE__IPU1_DI1_PIN7 = IOMUX_PAD(0x0414, 0x0100, 1, 0x0000, 0, 0), -- MX6Q_PAD_EIM_OE__ECSPI2_MISO = IOMUX_PAD(0x0414, 0x0100, 2, 0x0814, 0, 0), -- MX6Q_PAD_EIM_OE__MIPI_CORE_DPHY_OUT_26 = IOMUX_PAD(0x0414, 0x0100, 4, 0x0000, 0, 0), -- MX6Q_PAD_EIM_OE__GPIO_2_25 = IOMUX_PAD(0x0414, 0x0100, 5, 0x0000, 0, 0), -- MX6Q_PAD_EIM_OE__TPSMP_HDATA_9 = IOMUX_PAD(0x0414, 0x0100, 6, 0x0000, 0, 0), -- MX6Q_PAD_EIM_RW__WEIM_WEIM_RW = IOMUX_PAD(0x0418, 0x0104, 0, 0x0000, 0, 0), -- MX6Q_PAD_EIM_RW__IPU1_DI1_PIN8 = IOMUX_PAD(0x0418, 0x0104, 1, 0x0000, 0, 0), -- MX6Q_PAD_EIM_RW__ECSPI2_SS0 = IOMUX_PAD(0x0418, 0x0104, 2, 0x081C, 0, 0), -- MX6Q_PAD_EIM_RW__MIPI_CORE_DPHY_OUT_27 = IOMUX_PAD(0x0418, 0x0104, 4, 0x0000, 0, 0), -- MX6Q_PAD_EIM_RW__GPIO_2_26 = IOMUX_PAD(0x0418, 0x0104, 5, 0x0000, 0, 0), -- MX6Q_PAD_EIM_RW__TPSMP_HDATA_10 = IOMUX_PAD(0x0418, 0x0104, 6, 0x0000, 0, 0), -- MX6Q_PAD_EIM_RW__SRC_BT_CFG_29 = IOMUX_PAD(0x0418, 0x0104, 7, 0x0000, 0, 0), -- MX6Q_PAD_EIM_LBA__WEIM_WEIM_LBA = IOMUX_PAD(0x041C, 0x0108, 0, 0x0000, 0, 0), -- MX6Q_PAD_EIM_LBA__IPU1_DI1_PIN17 = IOMUX_PAD(0x041C, 0x0108, 1, 0x0000, 0, 0), -- MX6Q_PAD_EIM_LBA__ECSPI2_SS1 = IOMUX_PAD(0x041C, 0x0108, 2, 0x0820, 0, 0), -- MX6Q_PAD_EIM_LBA__GPIO_2_27 = IOMUX_PAD(0x041C, 0x0108, 5, 0x0000, 0, 0), -- MX6Q_PAD_EIM_LBA__TPSMP_HDATA_11 = IOMUX_PAD(0x041C, 0x0108, 6, 0x0000, 0, 0), -- MX6Q_PAD_EIM_LBA__SRC_BT_CFG_26 = IOMUX_PAD(0x041C, 0x0108, 7, 0x0000, 0, 0), -- MX6Q_PAD_EIM_EB0__WEIM_WEIM_EB_0 = IOMUX_PAD(0x0420, 0x010C, 0, 0x0000, 0, 0), -- MX6Q_PAD_EIM_EB0__IPU1_DISP1_DAT_11 = IOMUX_PAD(0x0420, 0x010C, 1, 0x0000, 0, 0), -- MX6Q_PAD_EIM_EB0__IPU2_CSI1_D_11 = IOMUX_PAD(0x0420, 0x010C, 2, 0x08B4, 1, 0), -- MX6Q_PAD_EIM_EB0__MIPI_CORE_DPHY_OUT_0 = IOMUX_PAD(0x0420, 0x010C, 3, 0x0000, 0, 0), -- MX6Q_PAD_EIM_EB0__CCM_PMIC_RDY = IOMUX_PAD(0x0420, 0x010C, 4, 0x07F0, 0, 0), -- MX6Q_PAD_EIM_EB0__GPIO_2_28 = IOMUX_PAD(0x0420, 0x010C, 5, 0x0000, 0, 0), -- MX6Q_PAD_EIM_EB0__TPSMP_HDATA_12 = IOMUX_PAD(0x0420, 0x010C, 6, 0x0000, 0, 0), -- MX6Q_PAD_EIM_EB0__SRC_BT_CFG_27 = IOMUX_PAD(0x0420, 0x010C, 7, 0x0000, 0, 0), -- MX6Q_PAD_EIM_EB1__WEIM_WEIM_EB_1 = IOMUX_PAD(0x0424, 0x0110, 0, 0x0000, 0, 0), -- MX6Q_PAD_EIM_EB1__IPU1_DISP1_DAT_10 = IOMUX_PAD(0x0424, 0x0110, 1, 0x0000, 0, 0), -- MX6Q_PAD_EIM_EB1__IPU2_CSI1_D_10 = IOMUX_PAD(0x0424, 0x0110, 2, 0x08B0, 1, 0), -- MX6Q_PAD_EIM_EB1__MIPI_CORE_DPHY__OUT_1 = IOMUX_PAD(0x0424, 0x0110, 3, 0x0000, 0, 0), -- MX6Q_PAD_EIM_EB1__GPIO_2_29 = IOMUX_PAD(0x0424, 0x0110, 5, 0x0000, 0, 0), -- MX6Q_PAD_EIM_EB1__TPSMP_HDATA_13 = IOMUX_PAD(0x0424, 0x0110, 6, 0x0000, 0, 0), -- MX6Q_PAD_EIM_EB1__SRC_BT_CFG_28 = IOMUX_PAD(0x0424, 0x0110, 7, 0x0000, 0, 0), -- MX6Q_PAD_EIM_DA0__WEIM_WEIM_DA_A_0 = IOMUX_PAD(0x0428, 0x0114, 0, 0x0000, 0, 0), -- MX6Q_PAD_EIM_DA0__IPU1_DISP1_DAT_9 = IOMUX_PAD(0x0428, 0x0114, 1, 0x0000, 0, 0), -- MX6Q_PAD_EIM_DA0__IPU2_CSI1_D_9 = IOMUX_PAD(0x0428, 0x0114, 2, 0x0000, 0, 0), -- MX6Q_PAD_EIM_DA0__MIPI_CORE_DPHY__OUT_2 = IOMUX_PAD(0x0428, 0x0114, 3, 0x0000, 0, 0), -- MX6Q_PAD_EIM_DA0__GPIO_3_0 = IOMUX_PAD(0x0428, 0x0114, 5, 0x0000, 0, 0), -- MX6Q_PAD_EIM_DA0__TPSMP_HDATA_14 = IOMUX_PAD(0x0428, 0x0114, 6, 0x0000, 0, 0), -- MX6Q_PAD_EIM_DA0__SRC_BT_CFG_0 = IOMUX_PAD(0x0428, 0x0114, 7, 0x0000, 0, 0), -- MX6Q_PAD_EIM_DA1__WEIM_WEIM_DA_A_1 = IOMUX_PAD(0x042C, 0x0118, 0, 0x0000, 0, 0), -- MX6Q_PAD_EIM_DA1__IPU1_DISP1_DAT_8 = IOMUX_PAD(0x042C, 0x0118, 1, 0x0000, 0, 0), -- MX6Q_PAD_EIM_DA1__IPU2_CSI1_D_8 = IOMUX_PAD(0x042C, 0x0118, 2, 0x0000, 0, 0), -- MX6Q_PAD_EIM_DA1__MIPI_CORE_DPHY_OUT_3 = IOMUX_PAD(0x042C, 0x0118, 3, 0x0000, 0, 0), -- MX6Q_PAD_EIM_DA1__USBPHY1_TX_LS_MODE = IOMUX_PAD(0x042C, 0x0118, 4, 0x0000, 0, 0), -- MX6Q_PAD_EIM_DA1__GPIO_3_1 = IOMUX_PAD(0x042C, 0x0118, 5, 0x0000, 0, 0), -- MX6Q_PAD_EIM_DA1__TPSMP_HDATA_15 = IOMUX_PAD(0x042C, 0x0118, 6, 0x0000, 0, 0), -- MX6Q_PAD_EIM_DA1__SRC_BT_CFG_1 = IOMUX_PAD(0x042C, 0x0118, 7, 0x0000, 0, 0), -- MX6Q_PAD_EIM_DA2__WEIM_WEIM_DA_A_2 = IOMUX_PAD(0x0430, 0x011C, 0, 0x0000, 0, 0), -- MX6Q_PAD_EIM_DA2__IPU1_DISP1_DAT_7 = IOMUX_PAD(0x0430, 0x011C, 1, 0x0000, 0, 0), -- MX6Q_PAD_EIM_DA2__IPU2_CSI1_D_7 = IOMUX_PAD(0x0430, 0x011C, 2, 0x0000, 0, 0), -- MX6Q_PAD_EIM_DA2__MIPI_CORE_DPHY_OUT_4 = IOMUX_PAD(0x0430, 0x011C, 3, 0x0000, 0, 0), -- MX6Q_PAD_EIM_DA2__USBPHY1_TX_HS_MODE = IOMUX_PAD(0x0430, 0x011C, 4, 0x0000, 0, 0), -- MX6Q_PAD_EIM_DA2__GPIO_3_2 = IOMUX_PAD(0x0430, 0x011C, 5, 0x0000, 0, 0), -- MX6Q_PAD_EIM_DA2__TPSMP_HDATA_16 = IOMUX_PAD(0x0430, 0x011C, 6, 0x0000, 0, 0), -- MX6Q_PAD_EIM_DA2__SRC_BT_CFG_2 = IOMUX_PAD(0x0430, 0x011C, 7, 0x0000, 0, 0), -- MX6Q_PAD_EIM_DA3__WEIM_WEIM_DA_A_3 = IOMUX_PAD(0x0434, 0x0120, 0, 0x0000, 0, 0), -- MX6Q_PAD_EIM_DA3__IPU1_DISP1_DAT_6 = IOMUX_PAD(0x0434, 0x0120, 1, 0x0000, 0, 0), -- MX6Q_PAD_EIM_DA3__IPU2_CSI1_D_6 = IOMUX_PAD(0x0434, 0x0120, 2, 0x0000, 0, 0), -- MX6Q_PAD_EIM_DA3__MIPI_CORE_DPHY_OUT_5 = IOMUX_PAD(0x0434, 0x0120, 3, 0x0000, 0, 0), -- MX6Q_PAD_EIM_DA3__USBPHY1_TX_HIZ = IOMUX_PAD(0x0434, 0x0120, 4, 0x0000, 0, 0), -- MX6Q_PAD_EIM_DA3__GPIO_3_3 = IOMUX_PAD(0x0434, 0x0120, 5, 0x0000, 0, 0), -- MX6Q_PAD_EIM_DA3__TPSMP_HDATA_17 = IOMUX_PAD(0x0434, 0x0120, 6, 0x0000, 0, 0), -- MX6Q_PAD_EIM_DA3__SRC_BT_CFG_3 = IOMUX_PAD(0x0434, 0x0120, 7, 0x0000, 0, 0), -- MX6Q_PAD_EIM_DA4__WEIM_WEIM_DA_A_4 = IOMUX_PAD(0x0438, 0x0124, 0, 0x0000, 0, 0), -- MX6Q_PAD_EIM_DA4__IPU1_DISP1_DAT_5 = IOMUX_PAD(0x0438, 0x0124, 1, 0x0000, 0, 0), -- MX6Q_PAD_EIM_DA4__IPU2_CSI1_D_5 = IOMUX_PAD(0x0438, 0x0124, 2, 0x0000, 0, 0), -- MX6Q_PAD_EIM_DA4__MIPI_CORE_DPHY_OUT_6 = IOMUX_PAD(0x0438, 0x0124, 3, 0x0000, 0, 0), -- MX6Q_PAD_EIM_DA4__ANATOP_USBPHY1_TX_EN = IOMUX_PAD(0x0438, 0x0124, 4, 0x0000, 0, 0), -- MX6Q_PAD_EIM_DA4__GPIO_3_4 = IOMUX_PAD(0x0438, 0x0124, 5, 0x0000, 0, 0), -- MX6Q_PAD_EIM_DA4__TPSMP_HDATA_18 = IOMUX_PAD(0x0438, 0x0124, 6, 0x0000, 0, 0), -- MX6Q_PAD_EIM_DA4__SRC_BT_CFG_4 = IOMUX_PAD(0x0438, 0x0124, 7, 0x0000, 0, 0), -- MX6Q_PAD_EIM_DA5__WEIM_WEIM_DA_A_5 = IOMUX_PAD(0x043C, 0x0128, 0, 0x0000, 0, 0), -- MX6Q_PAD_EIM_DA5__IPU1_DISP1_DAT_4 = IOMUX_PAD(0x043C, 0x0128, 1, 0x0000, 0, 0), -- MX6Q_PAD_EIM_DA5__IPU2_CSI1_D_4 = IOMUX_PAD(0x043C, 0x0128, 2, 0x0000, 0, 0), -- MX6Q_PAD_EIM_DA5__MIPI_CORE_DPHY_OUT_7 = IOMUX_PAD(0x043C, 0x0128, 3, 0x0000, 0, 0), -- MX6Q_PAD_EIM_DA5__ANATOP_USBPHY1_TX_DP = IOMUX_PAD(0x043C, 0x0128, 4, 0x0000, 0, 0), -- MX6Q_PAD_EIM_DA5__GPIO_3_5 = IOMUX_PAD(0x043C, 0x0128, 5, 0x0000, 0, 0), -- MX6Q_PAD_EIM_DA5__TPSMP_HDATA_19 = IOMUX_PAD(0x043C, 0x0128, 6, 0x0000, 0, 0), -- MX6Q_PAD_EIM_DA5__SRC_BT_CFG_5 = IOMUX_PAD(0x043C, 0x0128, 7, 0x0000, 0, 0), -- MX6Q_PAD_EIM_DA6__WEIM_WEIM_DA_A_6 = IOMUX_PAD(0x0440, 0x012C, 0, 0x0000, 0, 0), -- MX6Q_PAD_EIM_DA6__IPU1_DISP1_DAT_3 = IOMUX_PAD(0x0440, 0x012C, 1, 0x0000, 0, 0), -- MX6Q_PAD_EIM_DA6__IPU2_CSI1_D_3 = IOMUX_PAD(0x0440, 0x012C, 2, 0x0000, 0, 0), -- MX6Q_PAD_EIM_DA6__MIPI_CORE_DPHY_OUT_8 = IOMUX_PAD(0x0440, 0x012C, 3, 0x0000, 0, 0), -- MX6Q_PAD_EIM_DA6__ANATOP_USBPHY1_TX_DN = IOMUX_PAD(0x0440, 0x012C, 4, 0x0000, 0, 0), -- MX6Q_PAD_EIM_DA6__GPIO_3_6 = IOMUX_PAD(0x0440, 0x012C, 5, 0x0000, 0, 0), -- MX6Q_PAD_EIM_DA6__TPSMP_HDATA_20 = IOMUX_PAD(0x0440, 0x012C, 6, 0x0000, 0, 0), -- MX6Q_PAD_EIM_DA6__SRC_BT_CFG_6 = IOMUX_PAD(0x0440, 0x012C, 7, 0x0000, 0, 0), -- MX6Q_PAD_EIM_DA7__WEIM_WEIM_DA_A_7 = IOMUX_PAD(0x0444, 0x0130, 0, 0x0000, 0, 0), -- MX6Q_PAD_EIM_DA7__IPU1_DISP1_DAT_2 = IOMUX_PAD(0x0444, 0x0130, 1, 0x0000, 0, 0), -- MX6Q_PAD_EIM_DA7__IPU2_CSI1_D_2 = IOMUX_PAD(0x0444, 0x0130, 2, 0x0000, 0, 0), -- MX6Q_PAD_EIM_DA7__MIPI_CORE_DPHY_OUT_9 = IOMUX_PAD(0x0444, 0x0130, 3, 0x0000, 0, 0), -- MX6Q_PAD_EIM_DA7__GPIO_3_7 = IOMUX_PAD(0x0444, 0x0130, 5, 0x0000, 0, 0), -- MX6Q_PAD_EIM_DA7__TPSMP_HDATA_21 = IOMUX_PAD(0x0444, 0x0130, 6, 0x0000, 0, 0), -- MX6Q_PAD_EIM_DA7__SRC_BT_CFG_7 = IOMUX_PAD(0x0444, 0x0130, 7, 0x0000, 0, 0), -- MX6Q_PAD_EIM_DA8__WEIM_WEIM_DA_A_8 = IOMUX_PAD(0x0448, 0x0134, 0, 0x0000, 0, 0), -- MX6Q_PAD_EIM_DA8__IPU1_DISP1_DAT_1 = IOMUX_PAD(0x0448, 0x0134, 1, 0x0000, 0, 0), -- MX6Q_PAD_EIM_DA8__IPU2_CSI1_D_1 = IOMUX_PAD(0x0448, 0x0134, 2, 0x0000, 0, 0), -- MX6Q_PAD_EIM_DA8__MIPI_CORE_DPHY_OUT_10 = IOMUX_PAD(0x0448, 0x0134, 3, 0x0000, 0, 0), -- MX6Q_PAD_EIM_DA8__GPIO_3_8 = IOMUX_PAD(0x0448, 0x0134, 5, 0x0000, 0, 0), -- MX6Q_PAD_EIM_DA8__TPSMP_HDATA_22 = IOMUX_PAD(0x0448, 0x0134, 6, 0x0000, 0, 0), -- MX6Q_PAD_EIM_DA8__SRC_BT_CFG_8 = IOMUX_PAD(0x0448, 0x0134, 7, 0x0000, 0, 0), -- MX6Q_PAD_EIM_DA9__WEIM_WEIM_DA_A_9 = IOMUX_PAD(0x044C, 0x0138, 0, 0x0000, 0, 0), -- MX6Q_PAD_EIM_DA9__IPU1_DISP1_DAT_0 = IOMUX_PAD(0x044C, 0x0138, 1, 0x0000, 0, 0), -- MX6Q_PAD_EIM_DA9__IPU2_CSI1_D_0 = IOMUX_PAD(0x044C, 0x0138, 2, 0x0000, 0, 0), -- MX6Q_PAD_EIM_DA9__MIPI_CORE_DPHY_OUT_11 = IOMUX_PAD(0x044C, 0x0138, 3, 0x0000, 0, 0), -- MX6Q_PAD_EIM_DA9__GPIO_3_9 = IOMUX_PAD(0x044C, 0x0138, 5, 0x0000, 0, 0), -- MX6Q_PAD_EIM_DA9__TPSMP_HDATA_23 = IOMUX_PAD(0x044C, 0x0138, 6, 0x0000, 0, 0), -- MX6Q_PAD_EIM_DA9__SRC_BT_CFG_9 = IOMUX_PAD(0x044C, 0x0138, 7, 0x0000, 0, 0), -- MX6Q_PAD_EIM_DA10__WEIM_WEIM_DA_A_10 = IOMUX_PAD(0x0450, 0x013C, 0, 0x0000, 0, 0), -- MX6Q_PAD_EIM_DA10__IPU1_DI1_PIN15 = IOMUX_PAD(0x0450, 0x013C, 1, 0x0000, 0, 0), -- MX6Q_PAD_EIM_DA10__IPU2_CSI1_DATA_EN = IOMUX_PAD(0x0450, 0x013C, 2, 0x08D8, 1, 0), -- MX6Q_PAD_EIM_DA10__MIPI_CORE_DPHY_OUT12 = IOMUX_PAD(0x0450, 0x013C, 3, 0x0000, 0, 0), -- MX6Q_PAD_EIM_DA10__GPIO_3_10 = IOMUX_PAD(0x0450, 0x013C, 5, 0x0000, 0, 0), -- MX6Q_PAD_EIM_DA10__TPSMP_HDATA_24 = IOMUX_PAD(0x0450, 0x013C, 6, 0x0000, 0, 0), -- MX6Q_PAD_EIM_DA10__SRC_BT_CFG_10 = IOMUX_PAD(0x0450, 0x013C, 7, 0x0000, 0, 0), -- MX6Q_PAD_EIM_DA11__WEIM_WEIM_DA_A_11 = IOMUX_PAD(0x0454, 0x0140, 0, 0x0000, 0, 0), -- MX6Q_PAD_EIM_DA11__IPU1_DI1_PIN2 = IOMUX_PAD(0x0454, 0x0140, 1, 0x0000, 0, 0), -- MX6Q_PAD_EIM_DA11__IPU2_CSI1_HSYNC = IOMUX_PAD(0x0454, 0x0140, 2, 0x08DC, 1, 0), -- MX6Q_PAD_EIM_DA11__MIPI_CORE_DPHY_OUT13 = IOMUX_PAD(0x0454, 0x0140, 3, 0x0000, 0, 0), -- MX6Q_PAD_EIM_DA11__SDMA_DBG_EVT_CHN_6 = IOMUX_PAD(0x0454, 0x0140, 4, 0x0000, 0, 0), -- MX6Q_PAD_EIM_DA11__GPIO_3_11 = IOMUX_PAD(0x0454, 0x0140, 5, 0x0000, 0, 0), -- MX6Q_PAD_EIM_DA11__TPSMP_HDATA_25 = IOMUX_PAD(0x0454, 0x0140, 6, 0x0000, 0, 0), -- MX6Q_PAD_EIM_DA11__SRC_BT_CFG_11 = IOMUX_PAD(0x0454, 0x0140, 7, 0x0000, 0, 0), -- MX6Q_PAD_EIM_DA12__WEIM_WEIM_DA_A_12 = IOMUX_PAD(0x0458, 0x0144, 0, 0x0000, 0, 0), -- MX6Q_PAD_EIM_DA12__IPU1_DI1_PIN3 = IOMUX_PAD(0x0458, 0x0144, 1, 0x0000, 0, 0), -- MX6Q_PAD_EIM_DA12__IPU2_CSI1_VSYNC = IOMUX_PAD(0x0458, 0x0144, 2, 0x08E4, 1, 0), -- MX6Q_PAD_EIM_DA12__MIPI_CORE_DPHY_OUT14 = IOMUX_PAD(0x0458, 0x0144, 3, 0x0000, 0, 0), -- MX6Q_PAD_EIM_DA12__SDMA_DEBUG_EVT_CHN_3 = IOMUX_PAD(0x0458, 0x0144, 4, 0x0000, 0, 0), -- MX6Q_PAD_EIM_DA12__GPIO_3_12 = IOMUX_PAD(0x0458, 0x0144, 5, 0x0000, 0, 0), -- MX6Q_PAD_EIM_DA12__TPSMP_HDATA_26 = IOMUX_PAD(0x0458, 0x0144, 6, 0x0000, 0, 0), -- MX6Q_PAD_EIM_DA12__SRC_BT_CFG_12 = IOMUX_PAD(0x0458, 0x0144, 7, 0x0000, 0, 0), -- MX6Q_PAD_EIM_DA13__WEIM_WEIM_DA_A_13 = IOMUX_PAD(0x045C, 0x0148, 0, 0x0000, 0, 0), -- MX6Q_PAD_EIM_DA13__IPU1_DI1_D0_CS = IOMUX_PAD(0x045C, 0x0148, 1, 0x0000, 0, 0), -- MX6Q_PAD_EIM_DA13__CCM_DI1_EXT_CLK = IOMUX_PAD(0x045C, 0x0148, 2, 0x07EC, 1, 0), -- MX6Q_PAD_EIM_DA13__MIPI_CORE_DPHY_OUT15 = IOMUX_PAD(0x045C, 0x0148, 3, 0x0000, 0, 0), -- MX6Q_PAD_EIM_DA13__SDMA_DEBUG_EVT_CHN_4 = IOMUX_PAD(0x045C, 0x0148, 4, 0x0000, 0, 0), -- MX6Q_PAD_EIM_DA13__GPIO_3_13 = IOMUX_PAD(0x045C, 0x0148, 5, 0x0000, 0, 0), -- MX6Q_PAD_EIM_DA13__TPSMP_HDATA_27 = IOMUX_PAD(0x045C, 0x0148, 6, 0x0000, 0, 0), -- MX6Q_PAD_EIM_DA13__SRC_BT_CFG_13 = IOMUX_PAD(0x045C, 0x0148, 7, 0x0000, 0, 0), -- MX6Q_PAD_EIM_DA14__WEIM_WEIM_DA_A_14 = IOMUX_PAD(0x0460, 0x014C, 0, 0x0000, 0, 0), -- MX6Q_PAD_EIM_DA14__IPU1_DI1_D1_CS = IOMUX_PAD(0x0460, 0x014C, 1, 0x0000, 0, 0), -- MX6Q_PAD_EIM_DA14__CCM_DI0_EXT_CLK = IOMUX_PAD(0x0460, 0x014C, 2, 0x0000, 0, 0), -- MX6Q_PAD_EIM_DA14__MIPI_CORE_DPHY_OUT16 = IOMUX_PAD(0x0460, 0x014C, 3, 0x0000, 0, 0), -- MX6Q_PAD_EIM_DA14__SDMA_DEBUG_EVT_CHN_5 = IOMUX_PAD(0x0460, 0x014C, 4, 0x0000, 0, 0), -- MX6Q_PAD_EIM_DA14__GPIO_3_14 = IOMUX_PAD(0x0460, 0x014C, 5, 0x0000, 0, 0), -- MX6Q_PAD_EIM_DA14__TPSMP_HDATA_28 = IOMUX_PAD(0x0460, 0x014C, 6, 0x0000, 0, 0), -- MX6Q_PAD_EIM_DA14__SRC_BT_CFG_14 = IOMUX_PAD(0x0460, 0x014C, 7, 0x0000, 0, 0), -- MX6Q_PAD_EIM_DA15__WEIM_WEIM_DA_A_15 = IOMUX_PAD(0x0464, 0x0150, 0, 0x0000, 0, 0), -- MX6Q_PAD_EIM_DA15__IPU1_DI1_PIN1 = IOMUX_PAD(0x0464, 0x0150, 1, 0x0000, 0, 0), -- MX6Q_PAD_EIM_DA15__IPU1_DI1_PIN4 = IOMUX_PAD(0x0464, 0x0150, 2, 0x0000, 0, 0), -- MX6Q_PAD_EIM_DA15__MIPI_CORE_DPHY_OUT17 = IOMUX_PAD(0x0464, 0x0150, 3, 0x0000, 0, 0), -- MX6Q_PAD_EIM_DA15__GPIO_3_15 = IOMUX_PAD(0x0464, 0x0150, 5, 0x0000, 0, 0), -- MX6Q_PAD_EIM_DA15__TPSMP_HDATA_29 = IOMUX_PAD(0x0464, 0x0150, 6, 0x0000, 0, 0), -- MX6Q_PAD_EIM_DA15__SRC_BT_CFG_15 = IOMUX_PAD(0x0464, 0x0150, 7, 0x0000, 0, 0), -- MX6Q_PAD_EIM_WAIT__WEIM_WEIM_WAIT = IOMUX_PAD(0x0468, 0x0154, 0, 0x0000, 0, 0), -- MX6Q_PAD_EIM_WAIT__WEIM_WEIM_DTACK_B = IOMUX_PAD(0x0468, 0x0154, 1, 0x0000, 0, 0), -- MX6Q_PAD_EIM_WAIT__GPIO_5_0 = IOMUX_PAD(0x0468, 0x0154, 5, 0x0000, 0, 0), -- MX6Q_PAD_EIM_WAIT__TPSMP_HDATA_30 = IOMUX_PAD(0x0468, 0x0154, 6, 0x0000, 0, 0), -- MX6Q_PAD_EIM_WAIT__SRC_BT_CFG_25 = IOMUX_PAD(0x0468, 0x0154, 7, 0x0000, 0, 0), -- MX6Q_PAD_EIM_BCLK__WEIM_WEIM_BCLK = IOMUX_PAD(0x046C, 0x0158, 0, 0x0000, 0, 0), -- MX6Q_PAD_EIM_BCLK__IPU1_DI1_PIN16 = IOMUX_PAD(0x046C, 0x0158, 1, 0x0000, 0, 0), -- MX6Q_PAD_EIM_BCLK__GPIO_6_31 = IOMUX_PAD(0x046C, 0x0158, 5, 0x0000, 0, 0), -- MX6Q_PAD_EIM_BCLK__TPSMP_HDATA_31 = IOMUX_PAD(0x046C, 0x0158, 6, 0x0000, 0, 0), - MX6Q_PAD_DI0_DISP_CLK__IPU1_DI0_DSP_CLK = IOMUX_PAD(0x0470, 0x015C, 0, 0x0000, 0, 0), - MX6Q_PAD_DI0_DISP_CLK__IPU2_DI0_DSP_CLK = IOMUX_PAD(0x0470, 0x015C, 1, 0x0000, 0, 0), - MX6Q_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK = IOMUX_PAD(0x0470, 0x015C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6Q_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK = IOMUX_PAD(0x0470, 0x015C, 1, 0x0000, 0, 0), -- MX6Q_PAD_DI0_DISP_CLK__MIPI_CR_DPY_OT28 = IOMUX_PAD(0x0470, 0x015C, 3, 0x0000, 0, 0), -- MX6Q_PAD_DI0_DISP_CLK__SDMA_DBG_CR_STA0 = IOMUX_PAD(0x0470, 0x015C, 4, 0x0000, 0, 0), -- MX6Q_PAD_DI0_DISP_CLK__GPIO_4_16 = IOMUX_PAD(0x0470, 0x015C, 5, 0x0000, 0, 0), -- MX6Q_PAD_DI0_DISP_CLK__MMDC_DEBUG_0 = IOMUX_PAD(0x0470, 0x015C, 6, 0x0000, 0, 0), - MX6Q_PAD_DI0_PIN15__IPU1_DI0_PIN15 = IOMUX_PAD(0x0474, 0x0160, 0, 0x0000, 0, 0), - MX6Q_PAD_DI0_PIN15__IPU1_DI0_PIN15 = IOMUX_PAD(0x0474, 0x0160, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), -- MX6Q_PAD_DI0_PIN15__IPU2_DI0_PIN15 = IOMUX_PAD(0x0474, 0x0160, 1, 0x0000, 0, 0), -- MX6Q_PAD_DI0_PIN15__AUDMUX_AUD6_TXC = IOMUX_PAD(0x0474, 0x0160, 2, 0x0000, 0, 0), -- MX6Q_PAD_DI0_PIN15__MIPI_CR_DPHY_OUT_29 = IOMUX_PAD(0x0474, 0x0160, 3, 0x0000, 0, 0), -- MX6Q_PAD_DI0_PIN15__SDMA_DBG_CORE_STA_1 = IOMUX_PAD(0x0474, 0x0160, 4, 0x0000, 0, 0), -- MX6Q_PAD_DI0_PIN15__GPIO_4_17 = IOMUX_PAD(0x0474, 0x0160, 5, 0x0000, 0, 0), -- MX6Q_PAD_DI0_PIN15__MMDC_MMDC_DEBUG_1 = IOMUX_PAD(0x0474, 0x0160, 6, 0x0000, 0, 0), - MX6Q_PAD_DI0_PIN2__IPU1_DI0_PIN2 = IOMUX_PAD(0x0478, 0x0164, 0, 0x0000, 0, 0), - MX6Q_PAD_DI0_PIN2__IPU1_DI0_PIN2 = IOMUX_PAD(0x0478, 0x0164, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), -- MX6Q_PAD_DI0_PIN2__IPU2_DI0_PIN2 = IOMUX_PAD(0x0478, 0x0164, 1, 0x0000, 0, 0), -- MX6Q_PAD_DI0_PIN2__AUDMUX_AUD6_TXD = IOMUX_PAD(0x0478, 0x0164, 2, 0x0000, 0, 0), -- MX6Q_PAD_DI0_PIN2__MIPI_CR_DPHY_OUT_30 = IOMUX_PAD(0x0478, 0x0164, 3, 0x0000, 0, 0), -- MX6Q_PAD_DI0_PIN2__SDMA_DBG_CORE_STA_2 = IOMUX_PAD(0x0478, 0x0164, 4, 0x0000, 0, 0), -- MX6Q_PAD_DI0_PIN2__GPIO_4_18 = IOMUX_PAD(0x0478, 0x0164, 5, 0x0000, 0, 0), -- MX6Q_PAD_DI0_PIN2__MMDC_DEBUG_2 = IOMUX_PAD(0x0478, 0x0164, 6, 0x0000, 0, 0), -- MX6Q_PAD_DI0_PIN2__PL301_PER1_HADDR_9 = IOMUX_PAD(0x0478, 0x0164, 7, 0x0000, 0, 0), - MX6Q_PAD_DI0_PIN3__IPU1_DI0_PIN3 = IOMUX_PAD(0x047C, 0x0168, 0, 0x0000, 0, 0), - MX6Q_PAD_DI0_PIN3__IPU1_DI0_PIN3 = IOMUX_PAD(0x047C, 0x0168, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), -- MX6Q_PAD_DI0_PIN3__IPU2_DI0_PIN3 = IOMUX_PAD(0x047C, 0x0168, 1, 0x0000, 0, 0), -- MX6Q_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS = IOMUX_PAD(0x047C, 0x0168, 2, 0x0000, 0, 0), -- MX6Q_PAD_DI0_PIN3__MIPI_CORE_DPHY_OUT31 = IOMUX_PAD(0x047C, 0x0168, 3, 0x0000, 0, 0), -- MX6Q_PAD_DI0_PIN3__SDMA_DBG_CORE_STA_3 = IOMUX_PAD(0x047C, 0x0168, 4, 0x0000, 0, 0), -- MX6Q_PAD_DI0_PIN3__GPIO_4_19 = IOMUX_PAD(0x047C, 0x0168, 5, 0x0000, 0, 0), -- MX6Q_PAD_DI0_PIN3__MMDC_MMDC_DEBUG_3 = IOMUX_PAD(0x047C, 0x0168, 6, 0x0000, 0, 0), -- MX6Q_PAD_DI0_PIN3__PL301_PER1_HADDR_10 = IOMUX_PAD(0x047C, 0x0168, 7, 0x0000, 0, 0), -- MX6Q_PAD_DI0_PIN4__IPU1_DI0_PIN4 = IOMUX_PAD(0x0480, 0x016C, 0, 0x0000, 0, 0), -- MX6Q_PAD_DI0_PIN4__IPU2_DI0_PIN4 = IOMUX_PAD(0x0480, 0x016C, 1, 0x0000, 0, 0), -- MX6Q_PAD_DI0_PIN4__AUDMUX_AUD6_RXD = IOMUX_PAD(0x0480, 0x016C, 2, 0x0000, 0, 0), -- MX6Q_PAD_DI0_PIN4__USDHC1_WP = IOMUX_PAD(0x0480, 0x016C, 3, 0x094C, 0, 0), -- MX6Q_PAD_DI0_PIN4__SDMA_DEBUG_YIELD = IOMUX_PAD(0x0480, 0x016C, 4, 0x0000, 0, 0), - MX6Q_PAD_DI0_PIN4__GPIO_4_20 = IOMUX_PAD(0x0480, 0x016C, 5, 0x0000, 0, 0), - MX6Q_PAD_DI0_PIN4__GPIO_4_20 = IOMUX_PAD(0x0480, 0x016C, 5, 0x0000, 0, PAD_CTL_DSE_120ohm), -- MX6Q_PAD_DI0_PIN4__MMDC_MMDC_DEBUG_4 = IOMUX_PAD(0x0480, 0x016C, 6, 0x0000, 0, 0), -- MX6Q_PAD_DI0_PIN4__PL301_PER1_HADDR_11 = IOMUX_PAD(0x0480, 0x016C, 7, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0 = IOMUX_PAD(0x0484, 0x0170, 0, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0 = IOMUX_PAD(0x0484, 0x0170, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), -- MX6Q_PAD_DISP0_DAT0__IPU2_DISP0_DAT_0 = IOMUX_PAD(0x0484, 0x0170, 1, 0x0000, 0, 0), -- MX6Q_PAD_DISP0_DAT0__ECSPI3_SCLK = IOMUX_PAD(0x0484, 0x0170, 2, 0x0000, 0, 0), -- MX6Q_PAD_DISP0_DAT0__USDHC1_USDHC_DBG_0 = IOMUX_PAD(0x0484, 0x0170, 3, 0x0000, 0, 0), -- MX6Q_PAD_DISP0_DAT0__SDMA_DBG_CORE_RUN = IOMUX_PAD(0x0484, 0x0170, 4, 0x0000, 0, 0), -- MX6Q_PAD_DISP0_DAT0__GPIO_4_21 = IOMUX_PAD(0x0484, 0x0170, 5, 0x0000, 0, 0), -- MX6Q_PAD_DISP0_DAT0__MMDC_MMDC_DEBUG_5 = IOMUX_PAD(0x0484, 0x0170, 6, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1 = IOMUX_PAD(0x0488, 0x0174, 0, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1 = IOMUX_PAD(0x0488, 0x0174, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), -- MX6Q_PAD_DISP0_DAT1__IPU2_DISP0_DAT_1 = IOMUX_PAD(0x0488, 0x0174, 1, 0x0000, 0, 0), -- MX6Q_PAD_DISP0_DAT1__ECSPI3_MOSI = IOMUX_PAD(0x0488, 0x0174, 2, 0x0000, 0, 0), -- MX6Q_PAD_DISP0_DAT1__USDHC1_USDHC_DBG_1 = IOMUX_PAD(0x0488, 0x0174, 3, 0x0000, 0, 0), -- MX6Q_PAD_DISP0_DAT1__SDMA_DBG_EVT_CHNSL = IOMUX_PAD(0x0488, 0x0174, 4, 0x0000, 0, 0), -- MX6Q_PAD_DISP0_DAT1__GPIO_4_22 = IOMUX_PAD(0x0488, 0x0174, 5, 0x0000, 0, 0), -- MX6Q_PAD_DISP0_DAT1__MMDC_DEBUG_6 = IOMUX_PAD(0x0488, 0x0174, 6, 0x0000, 0, 0), -- MX6Q_PAD_DISP0_DAT1__PL301_PER1_HADR_12 = IOMUX_PAD(0x0488, 0x0174, 7, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2 = IOMUX_PAD(0x048C, 0x0178, 0, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2 = IOMUX_PAD(0x048C, 0x0178, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), -- MX6Q_PAD_DISP0_DAT2__IPU2_DISP0_DAT_2 = IOMUX_PAD(0x048C, 0x0178, 1, 0x0000, 0, 0), -- MX6Q_PAD_DISP0_DAT2__ECSPI3_MISO = IOMUX_PAD(0x048C, 0x0178, 2, 0x0000, 0, 0), -- MX6Q_PAD_DISP0_DAT2__USDHC1_USDHC_DBG_2 = IOMUX_PAD(0x048C, 0x0178, 3, 0x0000, 0, 0), -- MX6Q_PAD_DISP0_DAT2__SDMA_DEBUG_MODE = IOMUX_PAD(0x048C, 0x0178, 4, 0x0000, 0, 0), -- MX6Q_PAD_DISP0_DAT2__GPIO_4_23 = IOMUX_PAD(0x048C, 0x0178, 5, 0x0000, 0, 0), -- MX6Q_PAD_DISP0_DAT2__MMDC_DEBUG_7 = IOMUX_PAD(0x048C, 0x0178, 6, 0x0000, 0, 0), -- MX6Q_PAD_DISP0_DAT2__PL301_PER1_HADR_13 = IOMUX_PAD(0x048C, 0x0178, 7, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3 = IOMUX_PAD(0x0490, 0x017C, 0, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3 = IOMUX_PAD(0x0490, 0x017C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), -- MX6Q_PAD_DISP0_DAT3__IPU2_DISP0_DAT_3 = IOMUX_PAD(0x0490, 0x017C, 1, 0x0000, 0, 0), -- MX6Q_PAD_DISP0_DAT3__ECSPI3_SS0 = IOMUX_PAD(0x0490, 0x017C, 2, 0x0000, 0, 0), -- MX6Q_PAD_DISP0_DAT3__USDHC1_USDHC_DBG_3 = IOMUX_PAD(0x0490, 0x017C, 3, 0x0000, 0, 0), -- MX6Q_PAD_DISP0_DAT3__SDMA_DBG_BUS_ERROR = IOMUX_PAD(0x0490, 0x017C, 4, 0x0000, 0, 0), -- MX6Q_PAD_DISP0_DAT3__GPIO_4_24 = IOMUX_PAD(0x0490, 0x017C, 5, 0x0000, 0, 0), -- MX6Q_PAD_DISP0_DAT3__MMDC_MMDC_DBG_8 = IOMUX_PAD(0x0490, 0x017C, 6, 0x0000, 0, 0), -- MX6Q_PAD_DISP0_DAT3__PL301_PER1_HADR_14 = IOMUX_PAD(0x0490, 0x017C, 7, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4 = IOMUX_PAD(0x0494, 0x0180, 0, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4 = IOMUX_PAD(0x0494, 0x0180, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), -- MX6Q_PAD_DISP0_DAT4__IPU2_DISP0_DAT_4 = IOMUX_PAD(0x0494, 0x0180, 1, 0x0000, 0, 0), -- MX6Q_PAD_DISP0_DAT4__ECSPI3_SS1 = IOMUX_PAD(0x0494, 0x0180, 2, 0x0000, 0, 0), -- MX6Q_PAD_DISP0_DAT4__USDHC1_USDHC_DBG_4 = IOMUX_PAD(0x0494, 0x0180, 3, 0x0000, 0, 0), -- MX6Q_PAD_DISP0_DAT4__SDMA_DEBUG_BUS_RWB = IOMUX_PAD(0x0494, 0x0180, 4, 0x0000, 0, 0), -- MX6Q_PAD_DISP0_DAT4__GPIO_4_25 = IOMUX_PAD(0x0494, 0x0180, 5, 0x0000, 0, 0), -- MX6Q_PAD_DISP0_DAT4__MMDC_MMDC_DEBUG_9 = IOMUX_PAD(0x0494, 0x0180, 6, 0x0000, 0, 0), -- MX6Q_PAD_DISP0_DAT4__PL301_PER1_HADR_15 = IOMUX_PAD(0x0494, 0x0180, 7, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5 = IOMUX_PAD(0x0498, 0x0184, 0, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5 = IOMUX_PAD(0x0498, 0x0184, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), -- MX6Q_PAD_DISP0_DAT5__IPU2_DISP0_DAT_5 = IOMUX_PAD(0x0498, 0x0184, 1, 0x0000, 0, 0), -- MX6Q_PAD_DISP0_DAT5__ECSPI3_SS2 = IOMUX_PAD(0x0498, 0x0184, 2, 0x0000, 0, 0), -- MX6Q_PAD_DISP0_DAT5__AUDMUX_AUD6_RXFS = IOMUX_PAD(0x0498, 0x0184, 3, 0x0000, 0, 0), -- MX6Q_PAD_DISP0_DAT5__SDMA_DBG_MCH_DMBUS = IOMUX_PAD(0x0498, 0x0184, 4, 0x0000, 0, 0), -- MX6Q_PAD_DISP0_DAT5__GPIO_4_26 = IOMUX_PAD(0x0498, 0x0184, 5, 0x0000, 0, 0), -- MX6Q_PAD_DISP0_DAT5__MMDC_DEBUG_10 = IOMUX_PAD(0x0498, 0x0184, 6, 0x0000, 0, 0), -- MX6Q_PAD_DISP0_DAT5__PL301_PER1_HADR_16 = IOMUX_PAD(0x0498, 0x0184, 7, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6 = IOMUX_PAD(0x049C, 0x0188, 0, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6 = IOMUX_PAD(0x049C, 0x0188, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), -- MX6Q_PAD_DISP0_DAT6__IPU2_DISP0_DAT_6 = IOMUX_PAD(0x049C, 0x0188, 1, 0x0000, 0, 0), -- MX6Q_PAD_DISP0_DAT6__ECSPI3_SS3 = IOMUX_PAD(0x049C, 0x0188, 2, 0x0000, 0, 0), -- MX6Q_PAD_DISP0_DAT6__AUDMUX_AUD6_RXC = IOMUX_PAD(0x049C, 0x0188, 3, 0x0000, 0, 0), -- MX6Q_PAD_DISP0_DAT6__SDMA_DBG_RTBUF_WRT = IOMUX_PAD(0x049C, 0x0188, 4, 0x0000, 0, 0), -- MX6Q_PAD_DISP0_DAT6__GPIO_4_27 = IOMUX_PAD(0x049C, 0x0188, 5, 0x0000, 0, 0), -- MX6Q_PAD_DISP0_DAT6__MMDC_DEBUG_11 = IOMUX_PAD(0x049C, 0x0188, 6, 0x0000, 0, 0), -- MX6Q_PAD_DISP0_DAT6__PL301_PER1_HADR_17 = IOMUX_PAD(0x049C, 0x0188, 7, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7 = IOMUX_PAD(0x04A0, 0x018C, 0, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7 = IOMUX_PAD(0x04A0, 0x018C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), -- MX6Q_PAD_DISP0_DAT7__IPU2_DISP0_DAT_7 = IOMUX_PAD(0x04A0, 0x018C, 1, 0x0000, 0, 0), -- MX6Q_PAD_DISP0_DAT7__ECSPI3_RDY = IOMUX_PAD(0x04A0, 0x018C, 2, 0x0000, 0, 0), -- MX6Q_PAD_DISP0_DAT7__USDHC1_USDHC_DBG_5 = IOMUX_PAD(0x04A0, 0x018C, 3, 0x0000, 0, 0), -- MX6Q_PAD_DISP0_DAT7__SDMA_DBG_EVT_CHN_0 = IOMUX_PAD(0x04A0, 0x018C, 4, 0x0000, 0, 0), -- MX6Q_PAD_DISP0_DAT7__GPIO_4_28 = IOMUX_PAD(0x04A0, 0x018C, 5, 0x0000, 0, 0), -- MX6Q_PAD_DISP0_DAT7__MMDC_DEBUG_12 = IOMUX_PAD(0x04A0, 0x018C, 6, 0x0000, 0, 0), -- MX6Q_PAD_DISP0_DAT7__PL301_PER1_HADR_18 = IOMUX_PAD(0x04A0, 0x018C, 7, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8 = IOMUX_PAD(0x04A4, 0x0190, 0, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8 = IOMUX_PAD(0x04A4, 0x0190, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), -- MX6Q_PAD_DISP0_DAT8__IPU2_DISP0_DAT_8 = IOMUX_PAD(0x04A4, 0x0190, 1, 0x0000, 0, 0), -- MX6Q_PAD_DISP0_DAT8__PWM1_PWMO = IOMUX_PAD(0x04A4, 0x0190, 2, 0x0000, 0, 0), -- MX6Q_PAD_DISP0_DAT8__WDOG1_WDOG_B = IOMUX_PAD(0x04A4, 0x0190, 3, 0x0000, 0, 0), -- MX6Q_PAD_DISP0_DAT8__SDMA_DBG_EVT_CHN_1 = IOMUX_PAD(0x04A4, 0x0190, 4, 0x0000, 0, 0), -- MX6Q_PAD_DISP0_DAT8__GPIO_4_29 = IOMUX_PAD(0x04A4, 0x0190, 5, 0x0000, 0, 0), -- MX6Q_PAD_DISP0_DAT8__MMDC_DEBUG_13 = IOMUX_PAD(0x04A4, 0x0190, 6, 0x0000, 0, 0), -- MX6Q_PAD_DISP0_DAT8__PL301_PER1_HADR_19 = IOMUX_PAD(0x04A4, 0x0190, 7, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9 = IOMUX_PAD(0x04A8, 0x0194, 0, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9 = IOMUX_PAD(0x04A8, 0x0194, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), -- MX6Q_PAD_DISP0_DAT9__IPU2_DISP0_DAT_9 = IOMUX_PAD(0x04A8, 0x0194, 1, 0x0000, 0, 0), -- MX6Q_PAD_DISP0_DAT9__PWM2_PWMO = IOMUX_PAD(0x04A8, 0x0194, 2, 0x0000, 0, 0), -- MX6Q_PAD_DISP0_DAT9__WDOG2_WDOG_B = IOMUX_PAD(0x04A8, 0x0194, 3, 0x0000, 0, 0), -- MX6Q_PAD_DISP0_DAT9__SDMA_DBG_EVT_CHN_2 = IOMUX_PAD(0x04A8, 0x0194, 4, 0x0000, 0, 0), -- MX6Q_PAD_DISP0_DAT9__GPIO_4_30 = IOMUX_PAD(0x04A8, 0x0194, 5, 0x0000, 0, 0), -- MX6Q_PAD_DISP0_DAT9__MMDC_DEBUG_14 = IOMUX_PAD(0x04A8, 0x0194, 6, 0x0000, 0, 0), -- MX6Q_PAD_DISP0_DAT9__PL301_PER1_HADR_20 = IOMUX_PAD(0x04A8, 0x0194, 7, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10 = IOMUX_PAD(0x04AC, 0x0198, 0, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10 = IOMUX_PAD(0x04AC, 0x0198, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), -- MX6Q_PAD_DISP0_DAT10__IPU2_DISP0_DAT_10 = IOMUX_PAD(0x04AC, 0x0198, 1, 0x0000, 0, 0), -- MX6Q_PAD_DISP0_DAT10__USDHC1_DBG_6 = IOMUX_PAD(0x04AC, 0x0198, 3, 0x0000, 0, 0), -- MX6Q_PAD_DISP0_DAT10__SDMA_DBG_EVT_CHN3 = IOMUX_PAD(0x04AC, 0x0198, 4, 0x0000, 0, 0), -- MX6Q_PAD_DISP0_DAT10__GPIO_4_31 = IOMUX_PAD(0x04AC, 0x0198, 5, 0x0000, 0, 0), -- MX6Q_PAD_DISP0_DAT10__MMDC_DEBUG_15 = IOMUX_PAD(0x04AC, 0x0198, 6, 0x0000, 0, 0), -- MX6Q_PAD_DISP0_DAT10__PL301_PER1_HADR21 = IOMUX_PAD(0x04AC, 0x0198, 7, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11 = IOMUX_PAD(0x04B0, 0x019C, 0, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11 = IOMUX_PAD(0x04B0, 0x019C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), -- MX6Q_PAD_DISP0_DAT11__IPU2_DISP0_DAT_11 = IOMUX_PAD(0x04B0, 0x019C, 1, 0x0000, 0, 0), -- MX6Q_PAD_DISP0_DAT11__USDHC1_USDHC_DBG7 = IOMUX_PAD(0x04B0, 0x019C, 3, 0x0000, 0, 0), -- MX6Q_PAD_DISP0_DAT11__SDMA_DBG_EVT_CHN4 = IOMUX_PAD(0x04B0, 0x019C, 4, 0x0000, 0, 0), -- MX6Q_PAD_DISP0_DAT11__GPIO_5_5 = IOMUX_PAD(0x04B0, 0x019C, 5, 0x0000, 0, 0), -- MX6Q_PAD_DISP0_DAT11__MMDC_DEBUG_16 = IOMUX_PAD(0x04B0, 0x019C, 6, 0x0000, 0, 0), -- MX6Q_PAD_DISP0_DAT11__PL301_PER1_HADR22 = IOMUX_PAD(0x04B0, 0x019C, 7, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12 = IOMUX_PAD(0x04B4, 0x01A0, 0, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12 = IOMUX_PAD(0x04B4, 0x01A0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), -- MX6Q_PAD_DISP0_DAT12__IPU2_DISP0_DAT_12 = IOMUX_PAD(0x04B4, 0x01A0, 1, 0x0000, 0, 0), -- MX6Q_PAD_DISP0_DAT12__RESERVED_RESERVED = IOMUX_PAD(0x04B4, 0x01A0, 3, 0x0000, 0, 0), -- MX6Q_PAD_DISP0_DAT12__SDMA_DBG_EVT_CHN5 = IOMUX_PAD(0x04B4, 0x01A0, 4, 0x0000, 0, 0), -- MX6Q_PAD_DISP0_DAT12__GPIO_5_6 = IOMUX_PAD(0x04B4, 0x01A0, 5, 0x0000, 0, 0), -- MX6Q_PAD_DISP0_DAT12__MMDC_DEBUG_17 = IOMUX_PAD(0x04B4, 0x01A0, 6, 0x0000, 0, 0), -- MX6Q_PAD_DISP0_DAT12__PL301_PER1_HADR23 = IOMUX_PAD(0x04B4, 0x01A0, 7, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13 = IOMUX_PAD(0x04B8, 0x01A4, 0, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13 = IOMUX_PAD(0x04B8, 0x01A4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), -- MX6Q_PAD_DISP0_DAT13__IPU2_DISP0_DAT_13 = IOMUX_PAD(0x04B8, 0x01A4, 1, 0x0000, 0, 0), -- MX6Q_PAD_DISP0_DAT13__AUDMUX_AUD5_RXFS = IOMUX_PAD(0x04B8, 0x01A4, 3, 0x07D8, 1, 0), -- MX6Q_PAD_DISP0_DAT13__SDMA_DBG_EVT_CHN0 = IOMUX_PAD(0x04B8, 0x01A4, 4, 0x0000, 0, 0), -- MX6Q_PAD_DISP0_DAT13__GPIO_5_7 = IOMUX_PAD(0x04B8, 0x01A4, 5, 0x0000, 0, 0), -- MX6Q_PAD_DISP0_DAT13__MMDC_DEBUG_18 = IOMUX_PAD(0x04B8, 0x01A4, 6, 0x0000, 0, 0), -- MX6Q_PAD_DISP0_DAT13__PL301_PER1_HADR24 = IOMUX_PAD(0x04B8, 0x01A4, 7, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14 = IOMUX_PAD(0x04BC, 0x01A8, 0, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14 = IOMUX_PAD(0x04BC, 0x01A8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), -- MX6Q_PAD_DISP0_DAT14__IPU2_DISP0_DAT_14 = IOMUX_PAD(0x04BC, 0x01A8, 1, 0x0000, 0, 0), -- MX6Q_PAD_DISP0_DAT14__AUDMUX_AUD5_RXC = IOMUX_PAD(0x04BC, 0x01A8, 3, 0x07D4, 1, 0), -- MX6Q_PAD_DISP0_DAT14__SDMA_DBG_EVT_CHN1 = IOMUX_PAD(0x04BC, 0x01A8, 4, 0x0000, 0, 0), -- MX6Q_PAD_DISP0_DAT14__GPIO_5_8 = IOMUX_PAD(0x04BC, 0x01A8, 5, 0x0000, 0, 0), -- MX6Q_PAD_DISP0_DAT14__MMDC_DEBUG_19 = IOMUX_PAD(0x04BC, 0x01A8, 6, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15 = IOMUX_PAD(0x04C0, 0x01AC, 0, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15 = IOMUX_PAD(0x04C0, 0x01AC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), -- MX6Q_PAD_DISP0_DAT15__IPU2_DISP0_DAT_15 = IOMUX_PAD(0x04C0, 0x01AC, 1, 0x0000, 0, 0), -- MX6Q_PAD_DISP0_DAT15__ECSPI1_SS1 = IOMUX_PAD(0x04C0, 0x01AC, 2, 0x0804, 1, 0), -- MX6Q_PAD_DISP0_DAT15__ECSPI2_SS1 = IOMUX_PAD(0x04C0, 0x01AC, 3, 0x0820, 1, 0), -- MX6Q_PAD_DISP0_DAT15__SDMA_DBG_EVT_CHN2 = IOMUX_PAD(0x04C0, 0x01AC, 4, 0x0000, 0, 0), -- MX6Q_PAD_DISP0_DAT15__GPIO_5_9 = IOMUX_PAD(0x04C0, 0x01AC, 5, 0x0000, 0, 0), -- MX6Q_PAD_DISP0_DAT15__MMDC_DEBUG_20 = IOMUX_PAD(0x04C0, 0x01AC, 6, 0x0000, 0, 0), -- MX6Q_PAD_DISP0_DAT15__PL301_PER1_HADR25 = IOMUX_PAD(0x04C0, 0x01AC, 7, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16 = IOMUX_PAD(0x04C4, 0x01B0, 0, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16 = IOMUX_PAD(0x04C4, 0x01B0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), -- MX6Q_PAD_DISP0_DAT16__IPU2_DISP0_DAT_16 = IOMUX_PAD(0x04C4, 0x01B0, 1, 0x0000, 0, 0), -- MX6Q_PAD_DISP0_DAT16__ECSPI2_MOSI = IOMUX_PAD(0x04C4, 0x01B0, 2, 0x0818, 1, 0), -- MX6Q_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC = IOMUX_PAD(0x04C4, 0x01B0, 3, 0x07DC, 0, 0), -- MX6Q_PAD_DISP0_DAT16__SDMA_EXT_EVENT_0 = IOMUX_PAD(0x04C4, 0x01B0, 4, 0x090C, 0, 0), -- MX6Q_PAD_DISP0_DAT16__GPIO_5_10 = IOMUX_PAD(0x04C4, 0x01B0, 5, 0x0000, 0, 0), -- MX6Q_PAD_DISP0_DAT16__MMDC_DEBUG_21 = IOMUX_PAD(0x04C4, 0x01B0, 6, 0x0000, 0, 0), -- MX6Q_PAD_DISP0_DAT16__PL301_PER1_HADR26 = IOMUX_PAD(0x04C4, 0x01B0, 7, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17 = IOMUX_PAD(0x04C8, 0x01B4, 0, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17 = IOMUX_PAD(0x04C8, 0x01B4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), -- MX6Q_PAD_DISP0_DAT17__IPU2_DISP0_DAT_17 = IOMUX_PAD(0x04C8, 0x01B4, 1, 0x0000, 0, 0), -- MX6Q_PAD_DISP0_DAT17__ECSPI2_MISO = IOMUX_PAD(0x04C8, 0x01B4, 2, 0x0814, 1, 0), -- MX6Q_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD = IOMUX_PAD(0x04C8, 0x01B4, 3, 0x07D0, 0, 0), -- MX6Q_PAD_DISP0_DAT17__SDMA_EXT_EVENT_1 = IOMUX_PAD(0x04C8, 0x01B4, 4, 0x0910, 0, 0), -- MX6Q_PAD_DISP0_DAT17__GPIO_5_11 = IOMUX_PAD(0x04C8, 0x01B4, 5, 0x0000, 0, 0), -- MX6Q_PAD_DISP0_DAT17__MMDC_DEBUG_22 = IOMUX_PAD(0x04C8, 0x01B4, 6, 0x0000, 0, 0), -- MX6Q_PAD_DISP0_DAT17__PL301_PER1_HADR27 = IOMUX_PAD(0x04C8, 0x01B4, 7, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18 = IOMUX_PAD(0x04CC, 0x01B8, 0, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18 = IOMUX_PAD(0x04CC, 0x01B8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), -- MX6Q_PAD_DISP0_DAT18__IPU2_DISP0_DAT_18 = IOMUX_PAD(0x04CC, 0x01B8, 1, 0x0000, 0, 0), -- MX6Q_PAD_DISP0_DAT18__ECSPI2_SS0 = IOMUX_PAD(0x04CC, 0x01B8, 2, 0x081C, 1, 0), -- MX6Q_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS = IOMUX_PAD(0x04CC, 0x01B8, 3, 0x07E0, 0, 0), -- MX6Q_PAD_DISP0_DAT18__AUDMUX_AUD4_RXFS = IOMUX_PAD(0x04CC, 0x01B8, 4, 0x07C0, 0, 0), -- MX6Q_PAD_DISP0_DAT18__GPIO_5_12 = IOMUX_PAD(0x04CC, 0x01B8, 5, 0x0000, 0, 0), -- MX6Q_PAD_DISP0_DAT18__MMDC_DEBUG_23 = IOMUX_PAD(0x04CC, 0x01B8, 6, 0x0000, 0, 0), -- MX6Q_PAD_DISP0_DAT18__WEIM_WEIM_CS_2 = IOMUX_PAD(0x04CC, 0x01B8, 7, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19 = IOMUX_PAD(0x04D0, 0x01BC, 0, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19 = IOMUX_PAD(0x04D0, 0x01BC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), -- MX6Q_PAD_DISP0_DAT19__IPU2_DISP0_DAT_19 = IOMUX_PAD(0x04D0, 0x01BC, 1, 0x0000, 0, 0), -- MX6Q_PAD_DISP0_DAT19__ECSPI2_SCLK = IOMUX_PAD(0x04D0, 0x01BC, 2, 0x0810, 1, 0), -- MX6Q_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD = IOMUX_PAD(0x04D0, 0x01BC, 3, 0x07CC, 0, 0), -- MX6Q_PAD_DISP0_DAT19__AUDMUX_AUD4_RXC = IOMUX_PAD(0x04D0, 0x01BC, 4, 0x07BC, 0, 0), -- MX6Q_PAD_DISP0_DAT19__GPIO_5_13 = IOMUX_PAD(0x04D0, 0x01BC, 5, 0x0000, 0, 0), -- MX6Q_PAD_DISP0_DAT19__MMDC_DEBUG_24 = IOMUX_PAD(0x04D0, 0x01BC, 6, 0x0000, 0, 0), -- MX6Q_PAD_DISP0_DAT19__WEIM_WEIM_CS_3 = IOMUX_PAD(0x04D0, 0x01BC, 7, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20 = IOMUX_PAD(0x04D4, 0x01C0, 0, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20 = IOMUX_PAD(0x04D4, 0x01C0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), -- MX6Q_PAD_DISP0_DAT20__IPU2_DISP0_DAT_20 = IOMUX_PAD(0x04D4, 0x01C0, 1, 0x0000, 0, 0), -- MX6Q_PAD_DISP0_DAT20__ECSPI1_SCLK = IOMUX_PAD(0x04D4, 0x01C0, 2, 0x07F4, 1, 0), -- MX6Q_PAD_DISP0_DAT20__AUDMUX_AUD4_TXC = IOMUX_PAD(0x04D4, 0x01C0, 3, 0x07C4, 0, 0), -- MX6Q_PAD_DISP0_DAT20__SDMA_DBG_EVT_CHN7 = IOMUX_PAD(0x04D4, 0x01C0, 4, 0x0000, 0, 0), -- MX6Q_PAD_DISP0_DAT20__GPIO_5_14 = IOMUX_PAD(0x04D4, 0x01C0, 5, 0x0000, 0, 0), -- MX6Q_PAD_DISP0_DAT20__MMDC_DEBUG_25 = IOMUX_PAD(0x04D4, 0x01C0, 6, 0x0000, 0, 0), -- MX6Q_PAD_DISP0_DAT20__PL301_PER1_HADR28 = IOMUX_PAD(0x04D4, 0x01C0, 7, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21 = IOMUX_PAD(0x04D8, 0x01C4, 0, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21 = IOMUX_PAD(0x04D8, 0x01C4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), -- MX6Q_PAD_DISP0_DAT21__IPU2_DISP0_DAT_21 = IOMUX_PAD(0x04D8, 0x01C4, 1, 0x0000, 0, 0), -- MX6Q_PAD_DISP0_DAT21__ECSPI1_MOSI = IOMUX_PAD(0x04D8, 0x01C4, 2, 0x07FC, 1, 0), -- MX6Q_PAD_DISP0_DAT21__AUDMUX_AUD4_TXD = IOMUX_PAD(0x04D8, 0x01C4, 3, 0x07B8, 1, 0), -- MX6Q_PAD_DISP0_DAT21__SDMA_DBG_BUS_DEV0 = IOMUX_PAD(0x04D8, 0x01C4, 4, 0x0000, 0, 0), -- MX6Q_PAD_DISP0_DAT21__GPIO_5_15 = IOMUX_PAD(0x04D8, 0x01C4, 5, 0x0000, 0, 0), -- MX6Q_PAD_DISP0_DAT21__MMDC_DEBUG_26 = IOMUX_PAD(0x04D8, 0x01C4, 6, 0x0000, 0, 0), -- MX6Q_PAD_DISP0_DAT21__PL301_PER1_HADR29 = IOMUX_PAD(0x04D8, 0x01C4, 7, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22 = IOMUX_PAD(0x04DC, 0x01C8, 0, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22 = IOMUX_PAD(0x04DC, 0x01C8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), -- MX6Q_PAD_DISP0_DAT22__IPU2_DISP0_DAT_22 = IOMUX_PAD(0x04DC, 0x01C8, 1, 0x0000, 0, 0), -- MX6Q_PAD_DISP0_DAT22__ECSPI1_MISO = IOMUX_PAD(0x04DC, 0x01C8, 2, 0x07F8, 1, 0), -- MX6Q_PAD_DISP0_DAT22__AUDMUX_AUD4_TXFS = IOMUX_PAD(0x04DC, 0x01C8, 3, 0x07C8, 1, 0), -- MX6Q_PAD_DISP0_DAT22__SDMA_DBG_BUS_DEV1 = IOMUX_PAD(0x04DC, 0x01C8, 4, 0x0000, 0, 0), -- MX6Q_PAD_DISP0_DAT22__GPIO_5_16 = IOMUX_PAD(0x04DC, 0x01C8, 5, 0x0000, 0, 0), -- MX6Q_PAD_DISP0_DAT22__MMDC_DEBUG_27 = IOMUX_PAD(0x04DC, 0x01C8, 6, 0x0000, 0, 0), -- MX6Q_PAD_DISP0_DAT22__PL301_PER1_HADR30 = IOMUX_PAD(0x04DC, 0x01C8, 7, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23 = IOMUX_PAD(0x04E0, 0x01CC, 0, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23 = IOMUX_PAD(0x04E0, 0x01CC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), -- MX6Q_PAD_DISP0_DAT23__IPU2_DISP0_DAT_23 = IOMUX_PAD(0x04E0, 0x01CC, 1, 0x0000, 0, 0), -- MX6Q_PAD_DISP0_DAT23__ECSPI1_SS0 = IOMUX_PAD(0x04E0, 0x01CC, 2, 0x0800, 1, 0), -- MX6Q_PAD_DISP0_DAT23__AUDMUX_AUD4_RXD = IOMUX_PAD(0x04E0, 0x01CC, 3, 0x07B4, 1, 0), -- MX6Q_PAD_DISP0_DAT23__SDMA_DBG_BUS_DEV2 = IOMUX_PAD(0x04E0, 0x01CC, 4, 0x0000, 0, 0), -- MX6Q_PAD_DISP0_DAT23__GPIO_5_17 = IOMUX_PAD(0x04E0, 0x01CC, 5, 0x0000, 0, 0), -- MX6Q_PAD_DISP0_DAT23__MMDC_DEBUG_28 = IOMUX_PAD(0x04E0, 0x01CC, 6, 0x0000, 0, 0), -- MX6Q_PAD_DISP0_DAT23__PL301_PER1_HADR31 = IOMUX_PAD(0x04E0, 0x01CC, 7, 0x0000, 0, 0), -- MX6Q_PAD_ENET_MDIO__RESERVED_RESERVED = IOMUX_PAD(0x04E4, 0x01D0, 0, 0x0000, 0, 0), -- MX6Q_PAD_ENET_MDIO__ENET_MDIO = IOMUX_PAD(0x04E4, 0x01D0, 1, 0x0840, 0, 0), -- MX6Q_PAD_ENET_MDIO__ESAI1_SCKR = IOMUX_PAD(0x04E4, 0x01D0, 2, 0x086C, 0, 0), -- MX6Q_PAD_ENET_MDIO__SDMA_DEBUG_BUS_DEV3 = IOMUX_PAD(0x04E4, 0x01D0, 3, 0x0000, 0, 0), -- MX6Q_PAD_ENET_MDIO__ENET_1588_EVT1_OUT = IOMUX_PAD(0x04E4, 0x01D0, 4, 0x0000, 0, 0), -- MX6Q_PAD_ENET_MDIO__GPIO_1_22 = IOMUX_PAD(0x04E4, 0x01D0, 5, 0x0000, 0, 0), -- MX6Q_PAD_ENET_MDIO__SPDIF_PLOCK = IOMUX_PAD(0x04E4, 0x01D0, 6, 0x0000, 0, 0), -- MX6Q_PAD_ENET_REF_CLK__RESERVED_RSRVED = IOMUX_PAD(0x04E8, 0x01D4, 0, 0x0000, 0, 0), -- MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK = IOMUX_PAD(0x04E8, 0x01D4, 1, 0x0000, 0, 0), -- MX6Q_PAD_ENET_REF_CLK__ESAI1_FSR = IOMUX_PAD(0x04E8, 0x01D4, 2, 0x085C, 0, 0), -- MX6Q_PAD_ENET_REF_CLK__SDMA_DBGBUS_DEV4 = IOMUX_PAD(0x04E8, 0x01D4, 3, 0x0000, 0, 0), -- MX6Q_PAD_ENET_REF_CLK__GPIO_1_23 = IOMUX_PAD(0x04E8, 0x01D4, 5, 0x0000, 0, 0), -- MX6Q_PAD_ENET_REF_CLK__SPDIF_SRCLK = IOMUX_PAD(0x04E8, 0x01D4, 6, 0x0000, 0, 0), -- MX6Q_PAD_ENET_REF_CLK__USBPHY1_RX_SQH = IOMUX_PAD(0x04E8, 0x01D4, 7, 0x0000, 0, 0), -- MX6Q_PAD_ENET_RX_ER__ENET_RX_ER = IOMUX_PAD(0x04EC, 0x01D8, 1, 0x0000, 0, 0), -- MX6Q_PAD_ENET_RX_ER__ESAI1_HCKR = IOMUX_PAD(0x04EC, 0x01D8, 2, 0x0864, 0, 0), -- MX6Q_PAD_ENET_RX_ER__SPDIF_IN1 = IOMUX_PAD(0x04EC, 0x01D8, 3, 0x0914, 1, 0), -- MX6Q_PAD_ENET_RX_ER__ENET_1588_EVT2_OUT = IOMUX_PAD(0x04EC, 0x01D8, 4, 0x0000, 0, 0), -- MX6Q_PAD_ENET_RX_ER__GPIO_1_24 = IOMUX_PAD(0x04EC, 0x01D8, 5, 0x0000, 0, 0), -- MX6Q_PAD_ENET_RX_ER__PHY_TDI = IOMUX_PAD(0x04EC, 0x01D8, 6, 0x0000, 0, 0), -- MX6Q_PAD_ENET_RX_ER__USBPHY1_RX_HS_RXD = IOMUX_PAD(0x04EC, 0x01D8, 7, 0x0000, 0, 0), -- MX6Q_PAD_ENET_CRS_DV__RESERVED_RSRVED = IOMUX_PAD(0x04F0, 0x01DC, 0, 0x0000, 0, 0), -- MX6Q_PAD_ENET_CRS_DV__ENET_RX_EN = IOMUX_PAD(0x04F0, 0x01DC, 1, 0x0858, 1, 0), -- MX6Q_PAD_ENET_CRS_DV__ESAI1_SCKT = IOMUX_PAD(0x04F0, 0x01DC, 2, 0x0870, 0, 0), -- MX6Q_PAD_ENET_CRS_DV__SPDIF_EXTCLK = IOMUX_PAD(0x04F0, 0x01DC, 3, 0x0918, 1, 0), -- MX6Q_PAD_ENET_CRS_DV__GPIO_1_25 = IOMUX_PAD(0x04F0, 0x01DC, 5, 0x0000, 0, 0), -- MX6Q_PAD_ENET_CRS_DV__PHY_TDO = IOMUX_PAD(0x04F0, 0x01DC, 6, 0x0000, 0, 0), -- MX6Q_PAD_ENET_CRS_DV__USBPHY1_RX_FS_RXD = IOMUX_PAD(0x04F0, 0x01DC, 7, 0x0000, 0, 0), -- MX6Q_PAD_ENET_RXD1__MLB_MLBSIG = IOMUX_PAD(0x04F4, 0x01E0, 0, 0x0908, 0, 0), -- MX6Q_PAD_ENET_RXD1__ENET_RDATA_1 = IOMUX_PAD(0x04F4, 0x01E0, 1, 0x084C, 1, 0), -- MX6Q_PAD_ENET_RXD1__ESAI1_FST = IOMUX_PAD(0x04F4, 0x01E0, 2, 0x0860, 0, 0), -- MX6Q_PAD_ENET_RXD1__ENET_1588_EVT3_OUT = IOMUX_PAD(0x04F4, 0x01E0, 4, 0x0000, 0, 0), -- MX6Q_PAD_ENET_RXD1__GPIO_1_26 = IOMUX_PAD(0x04F4, 0x01E0, 5, 0x0000, 0, 0), -- MX6Q_PAD_ENET_RXD1__PHY_TCK = IOMUX_PAD(0x04F4, 0x01E0, 6, 0x0000, 0, 0), -- MX6Q_PAD_ENET_RXD1__USBPHY1_RX_DISCON = IOMUX_PAD(0x04F4, 0x01E0, 7, 0x0000, 0, 0), -- MX6Q_PAD_ENET_RXD0__OSC32K_32K_OUT = IOMUX_PAD(0x04F8, 0x01E4, 0, 0x0000, 0, 0), -- MX6Q_PAD_ENET_RXD0__ENET_RDATA_0 = IOMUX_PAD(0x04F8, 0x01E4, 1, 0x0848, 1, 0), -- MX6Q_PAD_ENET_RXD0__ESAI1_HCKT = IOMUX_PAD(0x04F8, 0x01E4, 2, 0x0868, 0, 0), -- MX6Q_PAD_ENET_RXD0__SPDIF_OUT1 = IOMUX_PAD(0x04F8, 0x01E4, 3, 0x0000, 0, 0), -- MX6Q_PAD_ENET_RXD0__GPIO_1_27 = IOMUX_PAD(0x04F8, 0x01E4, 5, 0x0000, 0, 0), -- MX6Q_PAD_ENET_RXD0__PHY_TMS = IOMUX_PAD(0x04F8, 0x01E4, 6, 0x0000, 0, 0), -- MX6Q_PAD_ENET_RXD0__USBPHY1_PLL_CK20DIV = IOMUX_PAD(0x04F8, 0x01E4, 7, 0x0000, 0, 0), -- MX6Q_PAD_ENET_TX_EN__RESERVED_RSRVED = IOMUX_PAD(0x04FC, 0x01E8, 0, 0x0000, 0, 0), -- MX6Q_PAD_ENET_TX_EN__ENET_TX_EN = IOMUX_PAD(0x04FC, 0x01E8, 1, 0x0000, 0, 0), -- MX6Q_PAD_ENET_TX_EN__ESAI1_TX3_RX2 = IOMUX_PAD(0x04FC, 0x01E8, 2, 0x0880, 0, 0), -- MX6Q_PAD_ENET_TX_EN__GPIO_1_28 = IOMUX_PAD(0x04FC, 0x01E8, 5, 0x0000, 0, 0), -- MX6Q_PAD_ENET_TX_EN__SATA_PHY_TDI = IOMUX_PAD(0x04FC, 0x01E8, 6, 0x0000, 0, 0), -- MX6Q_PAD_ENET_TX_EN__USBPHY2_RX_SQH = IOMUX_PAD(0x04FC, 0x01E8, 7, 0x0000, 0, 0), -- MX6Q_PAD_ENET_TXD1__MLB_MLBCLK = IOMUX_PAD(0x0500, 0x01EC, 0, 0x0900, 0, 0), -- MX6Q_PAD_ENET_TXD1__ENET_TDATA_1 = IOMUX_PAD(0x0500, 0x01EC, 1, 0x0000, 0, 0), -- MX6Q_PAD_ENET_TXD1__ESAI1_TX2_RX3 = IOMUX_PAD(0x0500, 0x01EC, 2, 0x087C, 0, 0), -- MX6Q_PAD_ENET_TXD1__ENET_1588_EVENT0_IN = IOMUX_PAD(0x0500, 0x01EC, 4, 0x0000, 0, 0), -- MX6Q_PAD_ENET_TXD1__GPIO_1_29 = IOMUX_PAD(0x0500, 0x01EC, 5, 0x0000, 0, 0), -- MX6Q_PAD_ENET_TXD1__SATA_PHY_TDO = IOMUX_PAD(0x0500, 0x01EC, 6, 0x0000, 0, 0), -- MX6Q_PAD_ENET_TXD1__USBPHY2_RX_HS_RXD = IOMUX_PAD(0x0500, 0x01EC, 7, 0x0000, 0, 0), -- MX6Q_PAD_ENET_TXD0__RESERVED_RSRVED = IOMUX_PAD(0x0504, 0x01F0, 0, 0x0000, 0, 0), -- MX6Q_PAD_ENET_TXD0__ENET_TDATA_0 = IOMUX_PAD(0x0504, 0x01F0, 1, 0x0000, 0, 0), -- MX6Q_PAD_ENET_TXD0__ESAI1_TX4_RX1 = IOMUX_PAD(0x0504, 0x01F0, 2, 0x0884, 0, 0), -- MX6Q_PAD_ENET_TXD0__GPIO_1_30 = IOMUX_PAD(0x0504, 0x01F0, 5, 0x0000, 0, 0), -- MX6Q_PAD_ENET_TXD0__SATA_PHY_TCK = IOMUX_PAD(0x0504, 0x01F0, 6, 0x0000, 0, 0), -- MX6Q_PAD_ENET_TXD0__USBPHY2_RX_FS_RXD = IOMUX_PAD(0x0504, 0x01F0, 7, 0x0000, 0, 0), -- MX6Q_PAD_ENET_MDC__MLB_MLBDAT = IOMUX_PAD(0x0508, 0x01F4, 0, 0x0904, 0, 0), -- MX6Q_PAD_ENET_MDC__ENET_MDC = IOMUX_PAD(0x0508, 0x01F4, 1, 0x0000, 0, 0), -- MX6Q_PAD_ENET_MDC__ESAI1_TX5_RX0 = IOMUX_PAD(0x0508, 0x01F4, 2, 0x0888, 0, 0), -- MX6Q_PAD_ENET_MDC__ENET_1588_EVENT1_IN = IOMUX_PAD(0x0508, 0x01F4, 4, 0x0000, 0, 0), -- MX6Q_PAD_ENET_MDC__GPIO_1_31 = IOMUX_PAD(0x0508, 0x01F4, 5, 0x0000, 0, 0), -- MX6Q_PAD_ENET_MDC__SATA_PHY_TMS = IOMUX_PAD(0x0508, 0x01F4, 6, 0x0000, 0, 0), -- MX6Q_PAD_ENET_MDC__USBPHY2_RX_DISCON = IOMUX_PAD(0x0508, 0x01F4, 7, 0x0000, 0, 0), -- MX6Q_PAD_DRAM_D40__MMDC_DRAM_D_40 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), -- MX6Q_PAD_DRAM_D41__MMDC_DRAM_D_41 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), -- MX6Q_PAD_DRAM_D42__MMDC_DRAM_D_42 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), -- MX6Q_PAD_DRAM_D43__MMDC_DRAM_D_43 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), -- MX6Q_PAD_DRAM_D44__MMDC_DRAM_D_44 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), -- MX6Q_PAD_DRAM_D45__MMDC_DRAM_D_45 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), -- MX6Q_PAD_DRAM_D46__MMDC_DRAM_D_46 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), -- MX6Q_PAD_DRAM_D47__MMDC_DRAM_D_47 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), -- MX6Q_PAD_DRAM_SDQS5__MMDC_DRAM_SDQS_5 = IOMUX_PAD(0x050C, NO_MUX_I, 0, 0x0000, 0, 0), -- MX6Q_PAD_DRAM_DQM5__MMDC_DRAM_DQM_5 = IOMUX_PAD(0x0510, NO_MUX_I, 0, 0x0000, 0, 0), -- MX6Q_PAD_DRAM_D32__MMDC_DRAM_D_32 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), -- MX6Q_PAD_DRAM_D33__MMDC_DRAM_D_33 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), -- MX6Q_PAD_DRAM_D34__MMDC_DRAM_D_34 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), -- MX6Q_PAD_DRAM_D35__MMDC_DRAM_D_35 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), -- MX6Q_PAD_DRAM_D36__MMDC_DRAM_D_36 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), -- MX6Q_PAD_DRAM_D37__MMDC_DRAM_D_37 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), -- MX6Q_PAD_DRAM_D38__MMDC_DRAM_D_38 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), -- MX6Q_PAD_DRAM_D39__MMDC_DRAM_D_39 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), -- MX6Q_PAD_DRAM_DQM4__MMDC_DRAM_DQM_4 = IOMUX_PAD(0x0514, NO_MUX_I, 0, 0x0000, 0, 0), -- MX6Q_PAD_DRAM_SDQS4__MMDC_DRAM_SDQS_4 = IOMUX_PAD(0x0518, NO_MUX_I, 0, 0x0000, 0, 0), -- MX6Q_PAD_DRAM_D24__MMDC_DRAM_D_24 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), -- MX6Q_PAD_DRAM_D25__MMDC_DRAM_D_25 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), -- MX6Q_PAD_DRAM_D26__MMDC_DRAM_D_26 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), -- MX6Q_PAD_DRAM_D27__MMDC_DRAM_D_27 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), -- MX6Q_PAD_DRAM_D28__MMDC_DRAM_D_28 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), -- MX6Q_PAD_DRAM_D29__MMDC_DRAM_D_29 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), -- MX6Q_PAD_DRAM_SDQS3__MMDC_DRAM_SDQS_3 = IOMUX_PAD(0x051C, NO_MUX_I, 0, 0x0000, 0, 0), -- MX6Q_PAD_DRAM_D30__MMDC_DRAM_D_30 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), -- MX6Q_PAD_DRAM_D31__MMDC_DRAM_D_31 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), -- MX6Q_PAD_DRAM_DQM3__MMDC_DRAM_DQM_3 = IOMUX_PAD(0x0520, NO_MUX_I, 0, 0x0000, 0, 0), -- MX6Q_PAD_DRAM_D16__MMDC_DRAM_D_16 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), -- MX6Q_PAD_DRAM_D17__MMDC_DRAM_D_17 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), -- MX6Q_PAD_DRAM_D18__MMDC_DRAM_D_18 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), -- MX6Q_PAD_DRAM_D19__MMDC_DRAM_D_19 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), -- MX6Q_PAD_DRAM_D20__MMDC_DRAM_D_20 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), -- MX6Q_PAD_DRAM_D21__MMDC_DRAM_D_21 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), -- MX6Q_PAD_DRAM_D22__MMDC_DRAM_D_22 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), -- MX6Q_PAD_DRAM_SDQS2__MMDC_DRAM_SDQS_2 = IOMUX_PAD(0x0524, NO_MUX_I, 0, 0x0000, 0, 0), -- MX6Q_PAD_DRAM_D23__MMDC_DRAM_D_23 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), -- MX6Q_PAD_DRAM_DQM2__MMDC_DRAM_DQM_2 = IOMUX_PAD(0x0528, NO_MUX_I, 0, 0x0000, 0, 0), -- MX6Q_PAD_DRAM_A0__MMDC_DRAM_A_0 = IOMUX_PAD(0x052C, NO_MUX_I, 0, 0x0000, 0, 0), -- MX6Q_PAD_DRAM_A1__MMDC_DRAM_A_1 = IOMUX_PAD(0x0530, NO_MUX_I, 0, 0x0000, 0, 0), -- MX6Q_PAD_DRAM_A2__MMDC_DRAM_A_2 = IOMUX_PAD(0x0534, NO_MUX_I, 0, 0x0000, 0, 0), -- MX6Q_PAD_DRAM_A3__MMDC_DRAM_A_3 = IOMUX_PAD(0x0538, NO_MUX_I, 0, 0x0000, 0, 0), -- MX6Q_PAD_DRAM_A4__MMDC_DRAM_A_4 = IOMUX_PAD(0x053C, NO_MUX_I, 0, 0x0000, 0, 0), -- MX6Q_PAD_DRAM_A5__MMDC_DRAM_A_5 = IOMUX_PAD(0x0540, NO_MUX_I, 0, 0x0000, 0, 0), -- MX6Q_PAD_DRAM_A6__MMDC_DRAM_A_6 = IOMUX_PAD(0x0544, NO_MUX_I, 0, 0x0000, 0, 0), -- MX6Q_PAD_DRAM_A7__MMDC_DRAM_A_7 = IOMUX_PAD(0x0548, NO_MUX_I, 0, 0x0000, 0, 0), -- MX6Q_PAD_DRAM_A8__MMDC_DRAM_A_8 = IOMUX_PAD(0x054C, NO_MUX_I, 0, 0x0000, 0, 0), -- MX6Q_PAD_DRAM_A9__MMDC_DRAM_A_9 = IOMUX_PAD(0x0550, NO_MUX_I, 0, 0x0000, 0, 0), -- MX6Q_PAD_DRAM_A10__MMDC_DRAM_A_10 = IOMUX_PAD(0x0554, NO_MUX_I, 0, 0x0000, 0, 0), -- MX6Q_PAD_DRAM_A11__MMDC_DRAM_A_11 = IOMUX_PAD(0x0558, NO_MUX_I, 0, 0x0000, 0, 0), -- MX6Q_PAD_DRAM_A12__MMDC_DRAM_A_12 = IOMUX_PAD(0x055C, NO_MUX_I, 0, 0x0000, 0, 0), -- MX6Q_PAD_DRAM_A13__MMDC_DRAM_A_13 = IOMUX_PAD(0x0560, NO_MUX_I, 0, 0x0000, 0, 0), -- MX6Q_PAD_DRAM_A14__MMDC_DRAM_A_14 = IOMUX_PAD(0x0564, NO_MUX_I, 0, 0x0000, 0, 0), -- MX6Q_PAD_DRAM_A15__MMDC_DRAM_A_15 = IOMUX_PAD(0x0568, NO_MUX_I, 0, 0x0000, 0, 0), -- MX6Q_PAD_DRAM_CAS__MMDC_DRAM_CAS = IOMUX_PAD(0x056C, NO_MUX_I, 0, 0x0000, 0, 0), -- MX6Q_PAD_DRAM_CS0__MMDC_DRAM_CS_0 = IOMUX_PAD(0x0570, NO_MUX_I, 0, 0x0000, 0, 0), -- MX6Q_PAD_DRAM_CS1__MMDC_DRAM_CS_1 = IOMUX_PAD(0x0574, NO_MUX_I, 0, 0x0000, 0, 0), -- MX6Q_PAD_DRAM_RAS__MMDC_DRAM_RAS = IOMUX_PAD(0x0578, NO_MUX_I, 0, 0x0000, 0, 0), -- MX6Q_PAD_DRAM_RESET__MMDC_DRAM_RESET = IOMUX_PAD(0x057C, NO_MUX_I, 0, 0x0000, 0, 0), -- MX6Q_PAD_DRAM_SDBA0__MMDC_DRAM_SDBA_0 = IOMUX_PAD(0x0580, NO_MUX_I, 0, 0x0000, 0, 0), -- MX6Q_PAD_DRAM_SDBA1__MMDC_DRAM_SDBA_1 = IOMUX_PAD(0x0584, NO_MUX_I, 0, 0x0000, 0, 0), -- MX6Q_PAD_DRAM_SDCLK_0__MMDC_DRAM_SDCLK0 = IOMUX_PAD(0x0588, NO_MUX_I, 0, 0x0000, 0, 0), -- MX6Q_PAD_DRAM_SDBA2__MMDC_DRAM_SDBA_2 = IOMUX_PAD(0x058C, NO_MUX_I, 0, 0x0000, 0, 0), -- MX6Q_PAD_DRAM_SDCKE0__MMDC_DRAM_SDCKE_0 = IOMUX_PAD(0x0590, NO_MUX_I, 0, 0x0000, 0, 0), -- MX6Q_PAD_DRAM_SDCLK_1__MMDC_DRAM_SDCLK1 = IOMUX_PAD(0x0594, NO_MUX_I, 0, 0x0000, 0, 0), -- MX6Q_PAD_DRAM_SDCKE1__MMDC_DRAM_SDCKE_1 = IOMUX_PAD(0x0598, NO_MUX_I, 0, 0x0000, 0, 0), -- MX6Q_PAD_DRAM_SDODT0__MMDC_DRAM_ODT_0 = IOMUX_PAD(0x059C, NO_MUX_I, 0, 0x0000, 0, 0), -- MX6Q_PAD_DRAM_SDODT1__MMDC_DRAM_ODT_1 = IOMUX_PAD(0x05A0, NO_MUX_I, 0, 0x0000, 0, 0), -- MX6Q_PAD_DRAM_SDWE__MMDC_DRAM_SDWE = IOMUX_PAD(0x05A4, NO_MUX_I, 0, 0x0000, 0, 0), -- MX6Q_PAD_DRAM_D0__MMDC_DRAM_D_0 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), -- MX6Q_PAD_DRAM_D1__MMDC_DRAM_D_1 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), -- MX6Q_PAD_DRAM_D2__MMDC_DRAM_D_2 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), -- MX6Q_PAD_DRAM_D3__MMDC_DRAM_D_3 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), -- MX6Q_PAD_DRAM_D4__MMDC_DRAM_D_4 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), -- MX6Q_PAD_DRAM_D5__MMDC_DRAM_D_5 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), -- MX6Q_PAD_DRAM_SDQS0__MMDC_DRAM_SDQS_0 = IOMUX_PAD(0x05A8, NO_MUX_I, 0, 0x0000, 0, 0), -- MX6Q_PAD_DRAM_D6__MMDC_DRAM_D_6 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), -- MX6Q_PAD_DRAM_D7__MMDC_DRAM_D_7 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), -- MX6Q_PAD_DRAM_DQM0__MMDC_DRAM_DQM_0 = IOMUX_PAD(0x05AC, NO_MUX_I, 0, 0x0000, 0, 0), -- MX6Q_PAD_DRAM_D8__MMDC_DRAM_D_8 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), -- MX6Q_PAD_DRAM_D9__MMDC_DRAM_D_9 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), -- MX6Q_PAD_DRAM_D10__MMDC_DRAM_D_10 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), -- MX6Q_PAD_DRAM_D11__MMDC_DRAM_D_11 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), -- MX6Q_PAD_DRAM_D12__MMDC_DRAM_D_12 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), -- MX6Q_PAD_DRAM_D13__MMDC_DRAM_D_13 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), -- MX6Q_PAD_DRAM_D14__MMDC_DRAM_D_14 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), -- MX6Q_PAD_DRAM_SDQS1__MMDC_DRAM_SDQS_1 = IOMUX_PAD(0x05B0, NO_MUX_I, 0, 0x0000, 0, 0), -- MX6Q_PAD_DRAM_D15__MMDC_DRAM_D_15 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), -- MX6Q_PAD_DRAM_DQM1__MMDC_DRAM_DQM_1 = IOMUX_PAD(0x05B4, NO_MUX_I, 0, 0x0000, 0, 0), -- MX6Q_PAD_DRAM_D48__MMDC_DRAM_D_48 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), -- MX6Q_PAD_DRAM_D49__MMDC_DRAM_D_49 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), -- MX6Q_PAD_DRAM_D50__MMDC_DRAM_D_50 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), -- MX6Q_PAD_DRAM_D51__MMDC_DRAM_D_51 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), -- MX6Q_PAD_DRAM_D52__MMDC_DRAM_D_52 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), -- MX6Q_PAD_DRAM_D53__MMDC_DRAM_D_53 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), -- MX6Q_PAD_DRAM_D54__MMDC_DRAM_D_54 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), -- MX6Q_PAD_DRAM_D55__MMDC_DRAM_D_55 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), -- MX6Q_PAD_DRAM_SDQS6__MMDC_DRAM_SDQS_6 = IOMUX_PAD(0x05B8, NO_MUX_I, 0, 0x0000, 0, 0), -- MX6Q_PAD_DRAM_DQM6__MMDC_DRAM_DQM_6 = IOMUX_PAD(0x05BC, NO_MUX_I, 0, 0x0000, 0, 0), -- MX6Q_PAD_DRAM_D56__MMDC_DRAM_D_56 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), -- MX6Q_PAD_DRAM_SDQS7__MMDC_DRAM_SDQS_7 = IOMUX_PAD(0x05C0, NO_MUX_I, 0, 0x0000, 0, 0), -- MX6Q_PAD_DRAM_D57__MMDC_DRAM_D_57 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), -- MX6Q_PAD_DRAM_D58__MMDC_DRAM_D_58 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), -- MX6Q_PAD_DRAM_D59__MMDC_DRAM_D_59 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), -- MX6Q_PAD_DRAM_D60__MMDC_DRAM_D_60 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), -- MX6Q_PAD_DRAM_DQM7__MMDC_DRAM_DQM_7 = IOMUX_PAD(0x05C4, NO_MUX_I, 0, 0x0000, 0, 0), -- MX6Q_PAD_DRAM_D61__MMDC_DRAM_D_61 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), -- MX6Q_PAD_DRAM_D62__MMDC_DRAM_D_62 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), -- MX6Q_PAD_DRAM_D63__MMDC_DRAM_D_63 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), -- MX6Q_PAD_KEY_COL0__ECSPI1_SCLK = IOMUX_PAD(0x05C8, 0x01F8, 0, 0x07F4, 2, 0), -- MX6Q_PAD_KEY_COL0__ENET_RDATA_3 = IOMUX_PAD(0x05C8, 0x01F8, 1, 0x0854, 1, 0), -- MX6Q_PAD_KEY_COL0__AUDMUX_AUD5_TXC = IOMUX_PAD(0x05C8, 0x01F8, 2, 0x07DC, 1, 0), -- MX6Q_PAD_KEY_COL0__KPP_COL_0 = IOMUX_PAD(0x05C8, 0x01F8, 3, 0x0000, 0, 0), -- MX6Q_PAD_KEY_COL0__UART4_TXD = IOMUX_PAD(0x05C8, 0x01F8, 4, 0x0000, 0, 0), -- MX6Q_PAD_KEY_COL0__UART4_TXD_RXD = IOMUX_PAD(0x05C8, 0x01F8, 4, 0x0938, 0, 0), -- MX6Q_PAD_KEY_COL0__GPIO_4_6 = IOMUX_PAD(0x05C8, 0x01F8, 5, 0x0000, 0, 0), -- MX6Q_PAD_KEY_COL0__DCIC1_DCIC_OUT = IOMUX_PAD(0x05C8, 0x01F8, 6, 0x0000, 0, 0), -- MX6Q_PAD_KEY_COL0__SRC_ANY_PU_RST = IOMUX_PAD(0x05C8, 0x01F8, 7, 0x0000, 0, 0), -- MX6Q_PAD_KEY_ROW0__ECSPI1_MOSI = IOMUX_PAD(0x05CC, 0x01FC, 0, 0x07FC, 2, 0), -- MX6Q_PAD_KEY_ROW0__ENET_TDATA_3 = IOMUX_PAD(0x05CC, 0x01FC, 1, 0x0000, 0, 0), -- MX6Q_PAD_KEY_ROW0__AUDMUX_AUD5_TXD = IOMUX_PAD(0x05CC, 0x01FC, 2, 0x07D0, 1, 0), -- MX6Q_PAD_KEY_ROW0__KPP_ROW_0 = IOMUX_PAD(0x05CC, 0x01FC, 3, 0x0000, 0, 0), -- MX6Q_PAD_KEY_ROW0__UART4_RXD = IOMUX_PAD(0x05CC, 0x01FC, 4, 0x0938, 1, 0), -- MX6Q_PAD_KEY_ROW0__GPIO_4_7 = IOMUX_PAD(0x05CC, 0x01FC, 5, 0x0000, 0, 0), -- MX6Q_PAD_KEY_ROW0__DCIC2_DCIC_OUT = IOMUX_PAD(0x05CC, 0x01FC, 6, 0x0000, 0, 0), -- MX6Q_PAD_KEY_ROW0__PL301_PER1_HADR_0 = IOMUX_PAD(0x05CC, 0x01FC, 7, 0x0000, 0, 0), -- MX6Q_PAD_KEY_COL1__ECSPI1_MISO = IOMUX_PAD(0x05D0, 0x0200, 0, 0x07F8, 2, 0), -- MX6Q_PAD_KEY_COL1__ENET_MDIO = IOMUX_PAD(0x05D0, 0x0200, 1, 0x0840, 1, 0), -- MX6Q_PAD_KEY_COL1__AUDMUX_AUD5_TXFS = IOMUX_PAD(0x05D0, 0x0200, 2, 0x07E0, 1, 0), -- MX6Q_PAD_KEY_COL1__KPP_COL_1 = IOMUX_PAD(0x05D0, 0x0200, 3, 0x0000, 0, 0), -- MX6Q_PAD_KEY_COL1__UART5_TXD = IOMUX_PAD(0x05D0, 0x0200, 4, 0x0000, 0, 0), -- MX6Q_PAD_KEY_COL1__UART5_TXD_RXD = IOMUX_PAD(0x05D0, 0x0200, 4, 0x0940, 0, 0), -- MX6Q_PAD_KEY_COL1__GPIO_4_8 = IOMUX_PAD(0x05D0, 0x0200, 5, 0x0000, 0, 0), -- MX6Q_PAD_KEY_COL1__USDHC1_VSELECT = IOMUX_PAD(0x05D0, 0x0200, 6, 0x0000, 0, 0), -- MX6Q_PAD_KEY_COL1__PL301MX_PER1_HADR_1 = IOMUX_PAD(0x05D0, 0x0200, 7, 0x0000, 0, 0), -- MX6Q_PAD_KEY_ROW1__ECSPI1_SS0 = IOMUX_PAD(0x05D4, 0x0204, 0, 0x0800, 2, 0), -- MX6Q_PAD_KEY_ROW1__ENET_COL = IOMUX_PAD(0x05D4, 0x0204, 1, 0x0000, 0, 0), -- MX6Q_PAD_KEY_ROW1__AUDMUX_AUD5_RXD = IOMUX_PAD(0x05D4, 0x0204, 2, 0x07CC, 1, 0), -- MX6Q_PAD_KEY_ROW1__KPP_ROW_1 = IOMUX_PAD(0x05D4, 0x0204, 3, 0x0000, 0, 0), -- MX6Q_PAD_KEY_ROW1__UART5_RXD = IOMUX_PAD(0x05D4, 0x0204, 4, 0x0940, 1, 0), -- MX6Q_PAD_KEY_ROW1__GPIO_4_9 = IOMUX_PAD(0x05D4, 0x0204, 5, 0x0000, 0, 0), -- MX6Q_PAD_KEY_ROW1__USDHC2_VSELECT = IOMUX_PAD(0x05D4, 0x0204, 6, 0x0000, 0, 0), -- MX6Q_PAD_KEY_ROW1__PL301_PER1_HADDR_2 = IOMUX_PAD(0x05D4, 0x0204, 7, 0x0000, 0, 0), -- MX6Q_PAD_KEY_COL2__ECSPI1_SS1 = IOMUX_PAD(0x05D8, 0x0208, 0, 0x0804, 2, 0), -- MX6Q_PAD_KEY_COL2__ENET_RDATA_2 = IOMUX_PAD(0x05D8, 0x0208, 1, 0x0850, 1, 0), -- MX6Q_PAD_KEY_COL2__CAN1_TXCAN = IOMUX_PAD(0x05D8, 0x0208, 2, 0x0000, 0, 0), -- MX6Q_PAD_KEY_COL2__KPP_COL_2 = IOMUX_PAD(0x05D8, 0x0208, 3, 0x0000, 0, 0), -- MX6Q_PAD_KEY_COL2__ENET_MDC = IOMUX_PAD(0x05D8, 0x0208, 4, 0x0000, 0, 0), -- MX6Q_PAD_KEY_COL2__GPIO_4_10 = IOMUX_PAD(0x05D8, 0x0208, 5, 0x0000, 0, 0), -- MX6Q_PAD_KEY_COL2__USBOH3_H1_PWRCTL_WKP = IOMUX_PAD(0x05D8, 0x0208, 6, 0x0000, 0, 0), -- MX6Q_PAD_KEY_COL2__PL301_PER1_HADDR_3 = IOMUX_PAD(0x05D8, 0x0208, 7, 0x0000, 0, 0), -- MX6Q_PAD_KEY_ROW2__ECSPI1_SS2 = IOMUX_PAD(0x05DC, 0x020C, 0, 0x0808, 1, 0), -- MX6Q_PAD_KEY_ROW2__ENET_TDATA_2 = IOMUX_PAD(0x05DC, 0x020C, 1, 0x0000, 0, 0), -- MX6Q_PAD_KEY_ROW2__CAN1_RXCAN = IOMUX_PAD(0x05DC, 0x020C, 2, 0x07E4, 0, 0), -- MX6Q_PAD_KEY_ROW2__KPP_ROW_2 = IOMUX_PAD(0x05DC, 0x020C, 3, 0x0000, 0, 0), -- MX6Q_PAD_KEY_ROW2__USDHC2_VSELECT = IOMUX_PAD(0x05DC, 0x020C, 4, 0x0000, 0, 0), -- MX6Q_PAD_KEY_ROW2__GPIO_4_11 = IOMUX_PAD(0x05DC, 0x020C, 5, 0x0000, 0, 0), -- MX6Q_PAD_KEY_ROW2__HDMI_TX_CEC_LINE = IOMUX_PAD(0x05DC, 0x020C, 6, 0x088C, 1, 0), -- MX6Q_PAD_KEY_ROW2__PL301_PER1_HADR_4 = IOMUX_PAD(0x05DC, 0x020C, 7, 0x0000, 0, 0), -- MX6Q_PAD_KEY_COL3__ECSPI1_SS3 = IOMUX_PAD(0x05E0, 0x0210, 0, 0x080C, 1, 0), -- MX6Q_PAD_KEY_COL3__ENET_CRS = IOMUX_PAD(0x05E0, 0x0210, 1, 0x0000, 0, 0), -- MX6Q_PAD_KEY_COL3__HDMI_TX_DDC_SCL = IOMUX_PAD(0x05E0, 0x0210, 2, 0x0890, 1, 0), -- MX6Q_PAD_KEY_COL3__KPP_COL_3 = IOMUX_PAD(0x05E0, 0x0210, 3, 0x0000, 0, 0), -- MX6Q_PAD_KEY_COL3__I2C2_SCL = IOMUX_PAD(0x05E0, 0x0210, 20, 0x08A0, 1, 0), -- MX6Q_PAD_KEY_COL3__GPIO_4_12 = IOMUX_PAD(0x05E0, 0x0210, 5, 0x0000, 0, 0), -- MX6Q_PAD_KEY_COL3__SPDIF_IN1 = IOMUX_PAD(0x05E0, 0x0210, 6, 0x0914, 2, 0), -- MX6Q_PAD_KEY_COL3__PL301_PER1_HADR_5 = IOMUX_PAD(0x05E0, 0x0210, 7, 0x0000, 0, 0), -- MX6Q_PAD_KEY_ROW3__OSC32K_32K_OUT = IOMUX_PAD(0x05E4, 0x0214, 0, 0x0000, 0, 0), -- MX6Q_PAD_KEY_ROW3__ASRC_ASRC_EXT_CLK = IOMUX_PAD(0x05E4, 0x0214, 1, 0x07B0, 0, 0), -- MX6Q_PAD_KEY_ROW3__HDMI_TX_DDC_SDA = IOMUX_PAD(0x05E4, 0x0214, 2, 0x0894, 1, 0), -- MX6Q_PAD_KEY_ROW3__KPP_ROW_3 = IOMUX_PAD(0x05E4, 0x0214, 3, 0x0000, 0, 0), -- MX6Q_PAD_KEY_ROW3__I2C2_SDA = IOMUX_PAD(0x05E4, 0x0214, 20, 0x08A4, 1, 0), -- MX6Q_PAD_KEY_ROW3__GPIO_4_13 = IOMUX_PAD(0x05E4, 0x0214, 5, 0x0000, 0, 0), -- MX6Q_PAD_KEY_ROW3__USDHC1_VSELECT = IOMUX_PAD(0x05E4, 0x0214, 6, 0x0000, 0, 0), -- MX6Q_PAD_KEY_ROW3__PL301_PER1_HADR_6 = IOMUX_PAD(0x05E4, 0x0214, 7, 0x0000, 0, 0), -- MX6Q_PAD_KEY_COL4__CAN2_TXCAN = IOMUX_PAD(0x05E8, 0x0218, 0, 0x0000, 0, 0), -- MX6Q_PAD_KEY_COL4__IPU1_SISG_4 = IOMUX_PAD(0x05E8, 0x0218, 1, 0x0000, 0, 0), -- MX6Q_PAD_KEY_COL4__USBOH3_USBOTG_OC = IOMUX_PAD(0x05E8, 0x0218, 2, 0x0944, 1, 0), -- MX6Q_PAD_KEY_COL4__KPP_COL_4 = IOMUX_PAD(0x05E8, 0x0218, 3, 0x0000, 0, 0), -- MX6Q_PAD_KEY_COL4__UART5_CTS = IOMUX_PAD(0x05E8, 0x0218, 4, 0x0000, 0, 0), -- MX6Q_PAD_KEY_COL4__UART5_RTS = IOMUX_PAD(0x05E8, 0x0218, 4, 0x093C, 0, 0), -- MX6Q_PAD_KEY_COL4__GPIO_4_14 = IOMUX_PAD(0x05E8, 0x0218, 5, 0x0000, 0, 0), -- MX6Q_PAD_KEY_COL4__MMDC_DEBUG_49 = IOMUX_PAD(0x05E8, 0x0218, 6, 0x0000, 0, 0), -- MX6Q_PAD_KEY_COL4__PL301_PER1_HADDR_7 = IOMUX_PAD(0x05E8, 0x0218, 7, 0x0000, 0, 0), -- MX6Q_PAD_KEY_ROW4__CAN2_RXCAN = IOMUX_PAD(0x05EC, 0x021C, 0, 0x07E8, 0, 0), -- MX6Q_PAD_KEY_ROW4__IPU1_SISG_5 = IOMUX_PAD(0x05EC, 0x021C, 1, 0x0000, 0, 0), -- MX6Q_PAD_KEY_ROW4__USBOH3_USBOTG_PWR = IOMUX_PAD(0x05EC, 0x021C, 2, 0x0000, 0, 0), -- MX6Q_PAD_KEY_ROW4__KPP_ROW_4 = IOMUX_PAD(0x05EC, 0x021C, 3, 0x0000, 0, 0), -- MX6Q_PAD_KEY_ROW4__UART5_CTS = IOMUX_PAD(0x05EC, 0x021C, 4, 0x093C, 1, 0), -- MX6Q_PAD_KEY_ROW4__GPIO_4_15 = IOMUX_PAD(0x05EC, 0x021C, 5, 0x0000, 0, 0), -- MX6Q_PAD_KEY_ROW4__MMDC_DEBUG_50 = IOMUX_PAD(0x05EC, 0x021C, 6, 0x0000, 0, 0), -- MX6Q_PAD_KEY_ROW4__PL301_PER1_HADR_8 = IOMUX_PAD(0x05EC, 0x021C, 7, 0x0000, 0, 0), -- MX6Q_PAD_GPIO_0__CCM_CLKO = IOMUX_PAD(0x05F0, 0x0220, 0, 0x0000, 0, 0), -- MX6Q_PAD_GPIO_0__KPP_COL_5 = IOMUX_PAD(0x05F0, 0x0220, 2, 0x08E8, 0, 0), -- MX6Q_PAD_GPIO_0__ASRC_ASRC_EXT_CLK = IOMUX_PAD(0x05F0, 0x0220, 3, 0x07B0, 1, 0), -- MX6Q_PAD_GPIO_0__EPIT1_EPITO = IOMUX_PAD(0x05F0, 0x0220, 4, 0x0000, 0, 0), -- MX6Q_PAD_GPIO_0__GPIO_1_0 = IOMUX_PAD(0x05F0, 0x0220, 5, 0x0000, 0, 0), -- MX6Q_PAD_GPIO_0__USBOH3_USBH1_PWR = IOMUX_PAD(0x05F0, 0x0220, 6, 0x0000, 0, 0), -- MX6Q_PAD_GPIO_0__SNVS_HP_WRAP_SNVS_VIO5 = IOMUX_PAD(0x05F0, 0x0220, 7, 0x0000, 0, 0), -- MX6Q_PAD_GPIO_1__ESAI1_SCKR = IOMUX_PAD(0x05F4, 0x0224, 0, 0x086C, 1, 0), -- MX6Q_PAD_GPIO_1__WDOG2_WDOG_B = IOMUX_PAD(0x05F4, 0x0224, 1, 0x0000, 0, 0), -- MX6Q_PAD_GPIO_1__KPP_ROW_5 = IOMUX_PAD(0x05F4, 0x0224, 2, 0x08F4, 0, 0), -- MX6Q_PAD_GPIO_1__PWM2_PWMO = IOMUX_PAD(0x05F4, 0x0224, 4, 0x0000, 0, 0), -- MX6Q_PAD_GPIO_1__GPIO_1_1 = IOMUX_PAD(0x05F4, 0x0224, 5, 0x0000, 0, 0), -- MX6Q_PAD_GPIO_1__USDHC1_CD = IOMUX_PAD(0x05F4, 0x0224, 6, 0x0000, 0, 0), -- MX6Q_PAD_GPIO_1__SRC_TESTER_ACK = IOMUX_PAD(0x05F4, 0x0224, 7, 0x0000, 0, 0), -- MX6Q_PAD_GPIO_9__ESAI1_FSR = IOMUX_PAD(0x05F8, 0x0228, 0, 0x085C, 1, 0), -- MX6Q_PAD_GPIO_9__WDOG1_WDOG_B = IOMUX_PAD(0x05F8, 0x0228, 1, 0x0000, 0, 0), -- MX6Q_PAD_GPIO_9__KPP_COL_6 = IOMUX_PAD(0x05F8, 0x0228, 2, 0x08EC, 0, 0), -- MX6Q_PAD_GPIO_9__CCM_REF_EN_B = IOMUX_PAD(0x05F8, 0x0228, 3, 0x0000, 0, 0), -- MX6Q_PAD_GPIO_9__PWM1_PWMO = IOMUX_PAD(0x05F8, 0x0228, 4, 0x0000, 0, 0), -- MX6Q_PAD_GPIO_9__GPIO_1_9 = IOMUX_PAD(0x05F8, 0x0228, 5, 0x0000, 0, 0), -- MX6Q_PAD_GPIO_9__USDHC1_WP = IOMUX_PAD(0x05F8, 0x0228, 6, 0x094C, 1, 0), -- MX6Q_PAD_GPIO_9__SRC_EARLY_RST = IOMUX_PAD(0x05F8, 0x0228, 7, 0x0000, 0, 0), -- MX6Q_PAD_GPIO_3__ESAI1_HCKR = IOMUX_PAD(0x05FC, 0x022C, 0, 0x0864, 1, 0), -- MX6Q_PAD_GPIO_3__OBSERVE_MUX_INT_OUT0 = IOMUX_PAD(0x05FC, 0x022C, 1, 0x0000, 0, 0), -- MX6Q_PAD_GPIO_3__I2C3_SCL = IOMUX_PAD(0x05FC, 0x022C, 18, 0x08A8, 1, 0), -- MX6Q_PAD_GPIO_3__ANATOP_24M_OUT = IOMUX_PAD(0x05FC, 0x022C, 3, 0x0000, 0, 0), -- MX6Q_PAD_GPIO_3__CCM_CLKO2 = IOMUX_PAD(0x05FC, 0x022C, 4, 0x0000, 0, 0), -- MX6Q_PAD_GPIO_3__GPIO_1_3 = IOMUX_PAD(0x05FC, 0x022C, 5, 0x0000, 0, 0), -- MX6Q_PAD_GPIO_3__USBOH3_USBH1_OC = IOMUX_PAD(0x05FC, 0x022C, 6, 0x0948, 1, 0), -- MX6Q_PAD_GPIO_3__MLB_MLBCLK = IOMUX_PAD(0x05FC, 0x022C, 7, 0x0900, 1, 0), -- MX6Q_PAD_GPIO_6__ESAI1_SCKT = IOMUX_PAD(0x0600, 0x0230, 0, 0x0870, 1, 0), -- MX6Q_PAD_GPIO_6__OBSERVE_MUX_INT_OUT1 = IOMUX_PAD(0x0600, 0x0230, 1, 0x0000, 0, 0), -- MX6Q_PAD_GPIO_6__I2C3_SDA = IOMUX_PAD(0x0600, 0x0230, 18, 0x08AC, 1, 0), -- MX6Q_PAD_GPIO_6__CCM_CCM_OUT_0 = IOMUX_PAD(0x0600, 0x0230, 3, 0x0000, 0, 0), -- MX6Q_PAD_GPIO_6__CSU_CSU_INT_DEB = IOMUX_PAD(0x0600, 0x0230, 4, 0x0000, 0, 0), -- MX6Q_PAD_GPIO_6__GPIO_1_6 = IOMUX_PAD(0x0600, 0x0230, 5, 0x0000, 0, 0), -- MX6Q_PAD_GPIO_6__USDHC2_LCTL = IOMUX_PAD(0x0600, 0x0230, 6, 0x0000, 0, 0), -- MX6Q_PAD_GPIO_6__MLB_MLBSIG = IOMUX_PAD(0x0600, 0x0230, 7, 0x0908, 1, 0), -- MX6Q_PAD_GPIO_2__ESAI1_FST = IOMUX_PAD(0x0604, 0x0234, 0, 0x0860, 1, 0), -- MX6Q_PAD_GPIO_2__OBSERVE_MUX_INT_OUT2 = IOMUX_PAD(0x0604, 0x0234, 1, 0x0000, 0, 0), -- MX6Q_PAD_GPIO_2__KPP_ROW_6 = IOMUX_PAD(0x0604, 0x0234, 2, 0x08F8, 1, 0), -- MX6Q_PAD_GPIO_2__CCM_CCM_OUT_1 = IOMUX_PAD(0x0604, 0x0234, 3, 0x0000, 0, 0), -- MX6Q_PAD_GPIO_2__CSU_CSU_ALARM_AUT_0 = IOMUX_PAD(0x0604, 0x0234, 4, 0x0000, 0, 0), -- MX6Q_PAD_GPIO_2__GPIO_1_2 = IOMUX_PAD(0x0604, 0x0234, 5, 0x0000, 0, 0), -- MX6Q_PAD_GPIO_2__USDHC2_WP = IOMUX_PAD(0x0604, 0x0234, 6, 0x0000, 0, 0), -- MX6Q_PAD_GPIO_2__MLB_MLBDAT = IOMUX_PAD(0x0604, 0x0234, 7, 0x0904, 1, 0), -- MX6Q_PAD_GPIO_4__ESAI1_HCKT = IOMUX_PAD(0x0608, 0x0238, 0, 0x0868, 1, 0), -- MX6Q_PAD_GPIO_4__OBSERVE_MUX_INT_OUT3 = IOMUX_PAD(0x0608, 0x0238, 1, 0x0000, 0, 0), -- MX6Q_PAD_GPIO_4__KPP_COL_7 = IOMUX_PAD(0x0608, 0x0238, 2, 0x08F0, 1, 0), -- MX6Q_PAD_GPIO_4__CCM_CCM_OUT_2 = IOMUX_PAD(0x0608, 0x0238, 3, 0x0000, 0, 0), -- MX6Q_PAD_GPIO_4__CSU_CSU_ALARM_AUT_1 = IOMUX_PAD(0x0608, 0x0238, 4, 0x0000, 0, 0), -- MX6Q_PAD_GPIO_4__GPIO_1_4 = IOMUX_PAD(0x0608, 0x0238, 5, 0x0000, 0, 0), -- MX6Q_PAD_GPIO_4__USDHC2_CD = IOMUX_PAD(0x0608, 0x0238, 6, 0x0000, 0, 0), -- MX6Q_PAD_GPIO_4__OCOTP_CRL_WRAR_FUSE_LA = IOMUX_PAD(0x0608, 0x0238, 7, 0x0000, 0, 0), -- MX6Q_PAD_GPIO_5__ESAI1_TX2_RX3 = IOMUX_PAD(0x060C, 0x023C, 0, 0x087C, 1, 0), -- MX6Q_PAD_GPIO_5__OBSERVE_MUX_INT_OUT4 = IOMUX_PAD(0x060C, 0x023C, 1, 0x0000, 0, 0), -- MX6Q_PAD_GPIO_5__KPP_ROW_7 = IOMUX_PAD(0x060C, 0x023C, 2, 0x08FC, 1, 0), -- MX6Q_PAD_GPIO_5__CCM_CLKO = IOMUX_PAD(0x060C, 0x023C, 3, 0x0000, 0, 0), -- MX6Q_PAD_GPIO_5__CSU_CSU_ALARM_AUT_2 = IOMUX_PAD(0x060C, 0x023C, 4, 0x0000, 0, 0), -- MX6Q_PAD_GPIO_5__GPIO_1_5 = IOMUX_PAD(0x060C, 0x023C, 5, 0x0000, 0, 0), -- MX6Q_PAD_GPIO_5__I2C3_SCL = IOMUX_PAD(0x060C, 0x023C, 22, 0x08A8, 2, 0), -- MX6Q_PAD_GPIO_5__CHEETAH_EVENTI = IOMUX_PAD(0x060C, 0x023C, 7, 0x0000, 0, 0), -- MX6Q_PAD_GPIO_7__ESAI1_TX4_RX1 = IOMUX_PAD(0x0610, 0x0240, 0, 0x0884, 1, 0), -- MX6Q_PAD_GPIO_7__ECSPI5_RDY = IOMUX_PAD(0x0610, 0x0240, 1, 0x0000, 0, 0), -- MX6Q_PAD_GPIO_7__EPIT1_EPITO = IOMUX_PAD(0x0610, 0x0240, 2, 0x0000, 0, 0), -- MX6Q_PAD_GPIO_7__CAN1_TXCAN = IOMUX_PAD(0x0610, 0x0240, 3, 0x0000, 0, 0), -- MX6Q_PAD_GPIO_7__UART2_TXD = IOMUX_PAD(0x0610, 0x0240, 4, 0x0000, 0, 0), -- MX6Q_PAD_GPIO_7__UART2_TXD_RXD = IOMUX_PAD(0x0610, 0x0240, 4, 0x0928, 2, 0), -- MX6Q_PAD_GPIO_7__GPIO_1_7 = IOMUX_PAD(0x0610, 0x0240, 5, 0x0000, 0, 0), -- MX6Q_PAD_GPIO_7__SPDIF_PLOCK = IOMUX_PAD(0x0610, 0x0240, 6, 0x0000, 0, 0), -- MX6Q_PAD_GPIO_7__USBOH3_OTGUSB_HST_MODE = IOMUX_PAD(0x0610, 0x0240, 7, 0x0000, 0, 0), -- MX6Q_PAD_GPIO_8__ESAI1_TX5_RX0 = IOMUX_PAD(0x0614, 0x0244, 0, 0x0888, 1, 0), -- MX6Q_PAD_GPIO_8__ANATOP_ANATOP_32K_OUT = IOMUX_PAD(0x0614, 0x0244, 1, 0x0000, 0, 0), -- MX6Q_PAD_GPIO_8__EPIT2_EPITO = IOMUX_PAD(0x0614, 0x0244, 2, 0x0000, 0, 0), -- MX6Q_PAD_GPIO_8__CAN1_RXCAN = IOMUX_PAD(0x0614, 0x0244, 3, 0x07E4, 1, 0), -- MX6Q_PAD_GPIO_8__UART2_RXD = IOMUX_PAD(0x0614, 0x0244, 4, 0x0928, 3, 0), -- MX6Q_PAD_GPIO_8__GPIO_1_8 = IOMUX_PAD(0x0614, 0x0244, 5, 0x0000, 0, 0), -- MX6Q_PAD_GPIO_8__SPDIF_SRCLK = IOMUX_PAD(0x0614, 0x0244, 6, 0x0000, 0, 0), -- MX6Q_PAD_GPIO_8__USBOH3_OTG_PWRCTL_WAK = IOMUX_PAD(0x0614, 0x0244, 7, 0x0000, 0, 0), -- MX6Q_PAD_GPIO_16__ESAI1_TX3_RX2 = IOMUX_PAD(0x0618, 0x0248, 0, 0x0880, 1, 0), -- MX6Q_PAD_GPIO_16__ENET_1588_EVENT2_IN = IOMUX_PAD(0x0618, 0x0248, 1, 0x0000, 0, 0), -- MX6Q_PAD_GPIO_16__ENET_ETHERNET_REF_OUT = IOMUX_PAD(0x0618, 0x0248, 2, 0x083C, 1, 0), -- MX6Q_PAD_GPIO_16__USDHC1_LCTL = IOMUX_PAD(0x0618, 0x0248, 3, 0x0000, 0, 0), -- MX6Q_PAD_GPIO_16__SPDIF_IN1 = IOMUX_PAD(0x0618, 0x0248, 4, 0x0914, 3, 0), -- MX6Q_PAD_GPIO_16__GPIO_7_11 = IOMUX_PAD(0x0618, 0x0248, 5, 0x0000, 0, 0), -- MX6Q_PAD_GPIO_16__I2C3_SDA = IOMUX_PAD(0x0618, 0x0248, 22, 0x08AC, 2, 0), -- MX6Q_PAD_GPIO_16__SJC_DE_B = IOMUX_PAD(0x0618, 0x0248, 7, 0x0000, 0, 0), -- MX6Q_PAD_GPIO_17__ESAI1_TX0 = IOMUX_PAD(0x061C, 0x024C, 0, 0x0874, 0, 0), -- MX6Q_PAD_GPIO_17__ENET_1588_EVENT3_IN = IOMUX_PAD(0x061C, 0x024C, 1, 0x0000, 0, 0), -- MX6Q_PAD_GPIO_17__CCM_PMIC_RDY = IOMUX_PAD(0x061C, 0x024C, 2, 0x07F0, 1, 0), -- MX6Q_PAD_GPIO_17__SDMA_SDMA_EXT_EVENT_0 = IOMUX_PAD(0x061C, 0x024C, 3, 0x090C, 1, 0), -- MX6Q_PAD_GPIO_17__SPDIF_OUT1 = IOMUX_PAD(0x061C, 0x024C, 4, 0x0000, 0, 0), -- MX6Q_PAD_GPIO_17__GPIO_7_12 = IOMUX_PAD(0x061C, 0x024C, 5, 0x0000, 0, 0), -- MX6Q_PAD_GPIO_17__SJC_JTAG_ACT = IOMUX_PAD(0x061C, 0x024C, 7, 0x0000, 0, 0), -- MX6Q_PAD_GPIO_18__ESAI1_TX1 = IOMUX_PAD(0x0620, 0x0250, 0, 0x0878, 0, 0), -- MX6Q_PAD_GPIO_18__ENET_RX_CLK = IOMUX_PAD(0x0620, 0x0250, 1, 0x0844, 1, 0), -- MX6Q_PAD_GPIO_18__USDHC3_VSELECT = IOMUX_PAD(0x0620, 0x0250, 2, 0x0000, 0, 0), -- MX6Q_PAD_GPIO_18__SDMA_SDMA_EXT_EVENT_1 = IOMUX_PAD(0x0620, 0x0250, 3, 0x0910, 1, 0), -- MX6Q_PAD_GPIO_18__ASRC_ASRC_EXT_CLK = IOMUX_PAD(0x0620, 0x0250, 4, 0x07B0, 2, 0), -- MX6Q_PAD_GPIO_18__GPIO_7_13 = IOMUX_PAD(0x0620, 0x0250, 5, 0x0000, 0, 0), -- MX6Q_PAD_GPIO_18__SNVS_HP_WRA_SNVS_VIO5 = IOMUX_PAD(0x0620, 0x0250, 6, 0x0000, 0, 0), -- MX6Q_PAD_GPIO_18__SRC_SYSTEM_RST = IOMUX_PAD(0x0620, 0x0250, 7, 0x0000, 0, 0), -- MX6Q_PAD_GPIO_19__KPP_COL_5 = IOMUX_PAD(0x0624, 0x0254, 0, 0x08E8, 1, 0), -- MX6Q_PAD_GPIO_19__ENET_1588_EVENT0_OUT = IOMUX_PAD(0x0624, 0x0254, 1, 0x0000, 0, 0), -- MX6Q_PAD_GPIO_19__SPDIF_OUT1 = IOMUX_PAD(0x0624, 0x0254, 2, 0x0000, 0, 0), -- MX6Q_PAD_GPIO_19__CCM_CLKO = IOMUX_PAD(0x0624, 0x0254, 3, 0x0000, 0, 0), -- MX6Q_PAD_GPIO_19__ECSPI1_RDY = IOMUX_PAD(0x0624, 0x0254, 4, 0x0000, 0, 0), -- MX6Q_PAD_GPIO_19__GPIO_4_5 = IOMUX_PAD(0x0624, 0x0254, 5, 0x0000, 0, 0), -- MX6Q_PAD_GPIO_19__ENET_TX_ER = IOMUX_PAD(0x0624, 0x0254, 6, 0x0000, 0, 0), -- MX6Q_PAD_GPIO_19__SRC_INT_BOOT = IOMUX_PAD(0x0624, 0x0254, 7, 0x0000, 0, 0), -- MX6Q_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK = IOMUX_PAD(0x0628, 0x0258, 0, 0x0000, 0, 0), -- MX6Q_PAD_CSI0_PIXCLK__PCIE_CTRL_MUX_12 = IOMUX_PAD(0x0628, 0x0258, 2, 0x0000, 0, 0), -- MX6Q_PAD_CSI0_PIXCLK__SDMA_DEBUG_PC_0 = IOMUX_PAD(0x0628, 0x0258, 4, 0x0000, 0, 0), -- MX6Q_PAD_CSI0_PIXCLK__GPIO_5_18 = IOMUX_PAD(0x0628, 0x0258, 5, 0x0000, 0, 0), -- MX6Q_PAD_CSI0_PIXCLK___MMDC_DEBUG_29 = IOMUX_PAD(0x0628, 0x0258, 6, 0x0000, 0, 0), -- MX6Q_PAD_CSI0_PIXCLK__CHEETAH_EVENTO = IOMUX_PAD(0x0628, 0x0258, 7, 0x0000, 0, 0), -- MX6Q_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC = IOMUX_PAD(0x062C, 0x025C, 0, 0x0000, 0, 0), -- MX6Q_PAD_CSI0_MCLK__PCIE_CTRL_MUX_13 = IOMUX_PAD(0x062C, 0x025C, 2, 0x0000, 0, 0), -- MX6Q_PAD_CSI0_MCLK__CCM_CLKO = IOMUX_PAD(0x062C, 0x025C, 3, 0x0000, 0, 0), -- MX6Q_PAD_CSI0_MCLK__SDMA_DEBUG_PC_1 = IOMUX_PAD(0x062C, 0x025C, 4, 0x0000, 0, 0), -- MX6Q_PAD_CSI0_MCLK__GPIO_5_19 = IOMUX_PAD(0x062C, 0x025C, 5, 0x0000, 0, 0), -- MX6Q_PAD_CSI0_MCLK__MMDC_MMDC_DEBUG_30 = IOMUX_PAD(0x062C, 0x025C, 6, 0x0000, 0, 0), -- MX6Q_PAD_CSI0_MCLK__CHEETAH_TRCTL = IOMUX_PAD(0x062C, 0x025C, 7, 0x0000, 0, 0), -- MX6Q_PAD_CSI0_DATA_EN__IPU1_CSI0_DA_EN = IOMUX_PAD(0x0630, 0x0260, 0, 0x0000, 0, 0), -- MX6Q_PAD_CSI0_DATA_EN__WEIM_WEIM_D_0 = IOMUX_PAD(0x0630, 0x0260, 1, 0x0000, 0, 0), -- MX6Q_PAD_CSI0_DATA_EN__PCIE_CTRL_MUX_14 = IOMUX_PAD(0x0630, 0x0260, 2, 0x0000, 0, 0), -- MX6Q_PAD_CSI0_DATA_EN__SDMA_DEBUG_PC_2 = IOMUX_PAD(0x0630, 0x0260, 4, 0x0000, 0, 0), -- MX6Q_PAD_CSI0_DATA_EN__GPIO_5_20 = IOMUX_PAD(0x0630, 0x0260, 5, 0x0000, 0, 0), -- MX6Q_PAD_CSI0_DATA_EN__MMDC_DEBUG_31 = IOMUX_PAD(0x0630, 0x0260, 6, 0x0000, 0, 0), -- MX6Q_PAD_CSI0_DATA_EN__CHEETAH_TRCLK = IOMUX_PAD(0x0630, 0x0260, 7, 0x0000, 0, 0), -- MX6Q_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC = IOMUX_PAD(0x0634, 0x0264, 0, 0x0000, 0, 0), -- MX6Q_PAD_CSI0_VSYNC__WEIM_WEIM_D_1 = IOMUX_PAD(0x0634, 0x0264, 1, 0x0000, 0, 0), -- MX6Q_PAD_CSI0_VSYNC__PCIE_CTRL_MUX_15 = IOMUX_PAD(0x0634, 0x0264, 2, 0x0000, 0, 0), -- MX6Q_PAD_CSI0_VSYNC__SDMA_DEBUG_PC_3 = IOMUX_PAD(0x0634, 0x0264, 4, 0x0000, 0, 0), -- MX6Q_PAD_CSI0_VSYNC__GPIO_5_21 = IOMUX_PAD(0x0634, 0x0264, 5, 0x0000, 0, 0), -- MX6Q_PAD_CSI0_VSYNC__MMDC_DEBUG_32 = IOMUX_PAD(0x0634, 0x0264, 6, 0x0000, 0, 0), -- MX6Q_PAD_CSI0_VSYNC__CHEETAH_TRACE_0 = IOMUX_PAD(0x0634, 0x0264, 7, 0x0000, 0, 0), -- MX6Q_PAD_CSI0_DAT4__IPU1_CSI0_D_4 = IOMUX_PAD(0x0638, 0x0268, 0, 0x0000, 0, 0), -- MX6Q_PAD_CSI0_DAT4__WEIM_WEIM_D_2 = IOMUX_PAD(0x0638, 0x0268, 1, 0x0000, 0, 0), -- MX6Q_PAD_CSI0_DAT4__ECSPI1_SCLK = IOMUX_PAD(0x0638, 0x0268, 2, 0x07F4, 3, 0), -- MX6Q_PAD_CSI0_DAT4__KPP_COL_5 = IOMUX_PAD(0x0638, 0x0268, 3, 0x08E8, 2, 0), -- MX6Q_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC = IOMUX_PAD(0x0638, 0x0268, 4, 0x0000, 0, 0), -- MX6Q_PAD_CSI0_DAT4__GPIO_5_22 = IOMUX_PAD(0x0638, 0x0268, 5, 0x0000, 0, 0), -- MX6Q_PAD_CSI0_DAT4__MMDC_DEBUG_43 = IOMUX_PAD(0x0638, 0x0268, 6, 0x0000, 0, 0), -- MX6Q_PAD_CSI0_DAT4__CHEETAH_TRACE_1 = IOMUX_PAD(0x0638, 0x0268, 7, 0x0000, 0, 0), -- MX6Q_PAD_CSI0_DAT5__IPU1_CSI0_D_5 = IOMUX_PAD(0x063C, 0x026C, 0, 0x0000, 0, 0), -- MX6Q_PAD_CSI0_DAT5__WEIM_WEIM_D_3 = IOMUX_PAD(0x063C, 0x026C, 1, 0x0000, 0, 0), -- MX6Q_PAD_CSI0_DAT5__ECSPI1_MOSI = IOMUX_PAD(0x063C, 0x026C, 2, 0x07FC, 3, 0), -- MX6Q_PAD_CSI0_DAT5__KPP_ROW_5 = IOMUX_PAD(0x063C, 0x026C, 3, 0x08F4, 1, 0), -- MX6Q_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD = IOMUX_PAD(0x063C, 0x026C, 4, 0x0000, 0, 0), -- MX6Q_PAD_CSI0_DAT5__GPIO_5_23 = IOMUX_PAD(0x063C, 0x026C, 5, 0x0000, 0, 0), -- MX6Q_PAD_CSI0_DAT5__MMDC_MMDC_DEBUG_44 = IOMUX_PAD(0x063C, 0x026C, 6, 0x0000, 0, 0), -- MX6Q_PAD_CSI0_DAT5__CHEETAH_TRACE_2 = IOMUX_PAD(0x063C, 0x026C, 7, 0x0000, 0, 0), -- MX6Q_PAD_CSI0_DAT6__IPU1_CSI0_D_6 = IOMUX_PAD(0x0640, 0x0270, 0, 0x0000, 0, 0), -- MX6Q_PAD_CSI0_DAT6__WEIM_WEIM_D_4 = IOMUX_PAD(0x0640, 0x0270, 1, 0x0000, 0, 0), -- MX6Q_PAD_CSI0_DAT6__ECSPI1_MISO = IOMUX_PAD(0x0640, 0x0270, 2, 0x07F8, 3, 0), -- MX6Q_PAD_CSI0_DAT6__KPP_COL_6 = IOMUX_PAD(0x0640, 0x0270, 3, 0x08EC, 1, 0), -- MX6Q_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS = IOMUX_PAD(0x0640, 0x0270, 4, 0x0000, 0, 0), -- MX6Q_PAD_CSI0_DAT6__GPIO_5_24 = IOMUX_PAD(0x0640, 0x0270, 5, 0x0000, 0, 0), -- MX6Q_PAD_CSI0_DAT6__MMDC_MMDC_DEBUG_45 = IOMUX_PAD(0x0640, 0x0270, 6, 0x0000, 0, 0), -- MX6Q_PAD_CSI0_DAT6__CHEETAH_TRACE_3 = IOMUX_PAD(0x0640, 0x0270, 7, 0x0000, 0, 0), -- MX6Q_PAD_CSI0_DAT7__IPU1_CSI0_D_7 = IOMUX_PAD(0x0644, 0x0274, 0, 0x0000, 0, 0), -- MX6Q_PAD_CSI0_DAT7__WEIM_WEIM_D_5 = IOMUX_PAD(0x0644, 0x0274, 1, 0x0000, 0, 0), -- MX6Q_PAD_CSI0_DAT7__ECSPI1_SS0 = IOMUX_PAD(0x0644, 0x0274, 2, 0x0800, 3, 0), -- MX6Q_PAD_CSI0_DAT7__KPP_ROW_6 = IOMUX_PAD(0x0644, 0x0274, 3, 0x08F8, 2, 0), -- MX6Q_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD = IOMUX_PAD(0x0644, 0x0274, 4, 0x0000, 0, 0), -- MX6Q_PAD_CSI0_DAT7__GPIO_5_25 = IOMUX_PAD(0x0644, 0x0274, 5, 0x0000, 0, 0), -- MX6Q_PAD_CSI0_DAT7__MMDC_MMDC_DEBUG_46 = IOMUX_PAD(0x0644, 0x0274, 6, 0x0000, 0, 0), -- MX6Q_PAD_CSI0_DAT7__CHEETAH_TRACE_4 = IOMUX_PAD(0x0644, 0x0274, 7, 0x0000, 0, 0), -- MX6Q_PAD_CSI0_DAT8__IPU1_CSI0_D_8 = IOMUX_PAD(0x0648, 0x0278, 0, 0x0000, 0, 0), -- MX6Q_PAD_CSI0_DAT8__WEIM_WEIM_D_6 = IOMUX_PAD(0x0648, 0x0278, 1, 0x0000, 0, 0), -- MX6Q_PAD_CSI0_DAT8__ECSPI2_SCLK = IOMUX_PAD(0x0648, 0x0278, 2, 0x0810, 2, 0), -- MX6Q_PAD_CSI0_DAT8__KPP_COL_7 = IOMUX_PAD(0x0648, 0x0278, 3, 0x08F0, 2, 0), -- MX6Q_PAD_CSI0_DAT8__I2C1_SDA = IOMUX_PAD(0x0648, 0x0278, 20, 0x089C, 1, 0), -- MX6Q_PAD_CSI0_DAT8__GPIO_5_26 = IOMUX_PAD(0x0648, 0x0278, 5, 0x0000, 0, 0), -- MX6Q_PAD_CSI0_DAT8__MMDC_MMDC_DEBUG_47 = IOMUX_PAD(0x0648, 0x0278, 6, 0x0000, 0, 0), -- MX6Q_PAD_CSI0_DAT8__CHEETAH_TRACE_5 = IOMUX_PAD(0x0648, 0x0278, 7, 0x0000, 0, 0), -- MX6Q_PAD_CSI0_DAT9__IPU1_CSI0_D_9 = IOMUX_PAD(0x064C, 0x027C, 0, 0x0000, 0, 0), -- MX6Q_PAD_CSI0_DAT9__WEIM_WEIM_D_7 = IOMUX_PAD(0x064C, 0x027C, 1, 0x0000, 0, 0), -- MX6Q_PAD_CSI0_DAT9__ECSPI2_MOSI = IOMUX_PAD(0x064C, 0x027C, 2, 0x0818, 2, 0), -- MX6Q_PAD_CSI0_DAT9__KPP_ROW_7 = IOMUX_PAD(0x064C, 0x027C, 3, 0x08FC, 2, 0), -- MX6Q_PAD_CSI0_DAT9__I2C1_SCL = IOMUX_PAD(0x064C, 0x027C, 20, 0x0898, 1, 0), -- MX6Q_PAD_CSI0_DAT9__GPIO_5_27 = IOMUX_PAD(0x064C, 0x027C, 5, 0x0000, 0, 0), -- MX6Q_PAD_CSI0_DAT9__MMDC_MMDC_DEBUG_48 = IOMUX_PAD(0x064C, 0x027C, 6, 0x0000, 0, 0), -- MX6Q_PAD_CSI0_DAT9__CHEETAH_TRACE_6 = IOMUX_PAD(0x064C, 0x027C, 7, 0x0000, 0, 0), -- MX6Q_PAD_CSI0_DAT10__IPU1_CSI0_D_10 = IOMUX_PAD(0x0650, 0x0280, 0, 0x0000, 0, 0), -- MX6Q_PAD_CSI0_DAT10__AUDMUX_AUD3_RXC = IOMUX_PAD(0x0650, 0x0280, 1, 0x0000, 0, 0), -- MX6Q_PAD_CSI0_DAT10__ECSPI2_MISO = IOMUX_PAD(0x0650, 0x0280, 2, 0x0814, 2, 0), -- MX6Q_PAD_CSI0_DAT10__UART1_TXD = IOMUX_PAD(0x0650, 0x0280, 3, 0x0000, 0, 0), -- MX6Q_PAD_CSI0_DAT10__UART1_TXD_RXD = IOMUX_PAD(0x0650, 0x0280, 3, 0x0920, 0, 0), -- MX6Q_PAD_CSI0_DAT10__SDMA_DEBUG_PC_4 = IOMUX_PAD(0x0650, 0x0280, 4, 0x0000, 0, 0), -- MX6Q_PAD_CSI0_DAT10__GPIO_5_28 = IOMUX_PAD(0x0650, 0x0280, 5, 0x0000, 0, 0), -- MX6Q_PAD_CSI0_DAT10__MMDC_MMDC_DEBUG_33 = IOMUX_PAD(0x0650, 0x0280, 6, 0x0000, 0, 0), -- MX6Q_PAD_CSI0_DAT10__CHEETAH_TRACE_7 = IOMUX_PAD(0x0650, 0x0280, 7, 0x0000, 0, 0), -- MX6Q_PAD_CSI0_DAT11__IPU1_CSI0_D_11 = IOMUX_PAD(0x0654, 0x0284, 0, 0x0000, 0, 0), -- MX6Q_PAD_CSI0_DAT11__AUDMUX_AUD3_RXFS = IOMUX_PAD(0x0654, 0x0284, 1, 0x0000, 0, 0), -- MX6Q_PAD_CSI0_DAT11__ECSPI2_SS0 = IOMUX_PAD(0x0654, 0x0284, 2, 0x081C, 2, 0), -- MX6Q_PAD_CSI0_DAT11__UART1_RXD = IOMUX_PAD(0x0654, 0x0284, 3, 0x0920, 1, 0), -- MX6Q_PAD_CSI0_DAT11__SDMA_DEBUG_PC_5 = IOMUX_PAD(0x0654, 0x0284, 4, 0x0000, 0, 0), -- MX6Q_PAD_CSI0_DAT11__GPIO_5_29 = IOMUX_PAD(0x0654, 0x0284, 5, 0x0000, 0, 0), -- MX6Q_PAD_CSI0_DAT11__MMDC_MMDC_DEBUG_34 = IOMUX_PAD(0x0654, 0x0284, 6, 0x0000, 0, 0), -- MX6Q_PAD_CSI0_DAT11__CHEETAH_TRACE_8 = IOMUX_PAD(0x0654, 0x0284, 7, 0x0000, 0, 0), -- MX6Q_PAD_CSI0_DAT12__IPU1_CSI0_D_12 = IOMUX_PAD(0x0658, 0x0288, 0, 0x0000, 0, 0), -- MX6Q_PAD_CSI0_DAT12__WEIM_WEIM_D_8 = IOMUX_PAD(0x0658, 0x0288, 1, 0x0000, 0, 0), -- MX6Q_PAD_CSI0_DAT12__PCIE_CTRL_MUX_16 = IOMUX_PAD(0x0658, 0x0288, 2, 0x0000, 0, 0), -- MX6Q_PAD_CSI0_DAT12__UART4_TXD = IOMUX_PAD(0x0658, 0x0288, 3, 0x0000, 0, 0), -- MX6Q_PAD_CSI0_DAT12__UART4_TXD_RXD = IOMUX_PAD(0x0658, 0x0288, 3, 0x0938, 2, 0), -- MX6Q_PAD_CSI0_DAT12__SDMA_DEBUG_PC_6 = IOMUX_PAD(0x0658, 0x0288, 4, 0x0000, 0, 0), -- MX6Q_PAD_CSI0_DAT12__GPIO_5_30 = IOMUX_PAD(0x0658, 0x0288, 5, 0x0000, 0, 0), -- MX6Q_PAD_CSI0_DAT12__MMDC_MMDC_DEBUG_35 = IOMUX_PAD(0x0658, 0x0288, 6, 0x0000, 0, 0), -- MX6Q_PAD_CSI0_DAT12__CHEETAH_TRACE_9 = IOMUX_PAD(0x0658, 0x0288, 7, 0x0000, 0, 0), -- MX6Q_PAD_CSI0_DAT13__IPU1_CSI0_D_13 = IOMUX_PAD(0x065C, 0x028C, 0, 0x0000, 0, 0), -- MX6Q_PAD_CSI0_DAT13__WEIM_WEIM_D_9 = IOMUX_PAD(0x065C, 0x028C, 1, 0x0000, 0, 0), -- MX6Q_PAD_CSI0_DAT13__PCIE_CTRL_MUX_17 = IOMUX_PAD(0x065C, 0x028C, 2, 0x0000, 0, 0), -- MX6Q_PAD_CSI0_DAT13__UART4_RXD = IOMUX_PAD(0x065C, 0x028C, 3, 0x0938, 3, 0), -- MX6Q_PAD_CSI0_DAT13__SDMA_DEBUG_PC_7 = IOMUX_PAD(0x065C, 0x028C, 4, 0x0000, 0, 0), -- MX6Q_PAD_CSI0_DAT13__GPIO_5_31 = IOMUX_PAD(0x065C, 0x028C, 5, 0x0000, 0, 0), -- MX6Q_PAD_CSI0_DAT13__MMDC_MMDC_DEBUG_36 = IOMUX_PAD(0x065C, 0x028C, 6, 0x0000, 0, 0), -- MX6Q_PAD_CSI0_DAT13__CHEETAH_TRACE_10 = IOMUX_PAD(0x065C, 0x028C, 7, 0x0000, 0, 0), -- MX6Q_PAD_CSI0_DAT14__IPU1_CSI0_D_14 = IOMUX_PAD(0x0660, 0x0290, 0, 0x0000, 0, 0), -- MX6Q_PAD_CSI0_DAT14__WEIM_WEIM_D_10 = IOMUX_PAD(0x0660, 0x0290, 1, 0x0000, 0, 0), -- MX6Q_PAD_CSI0_DAT14__PCIE_CTRL_MUX_18 = IOMUX_PAD(0x0660, 0x0290, 2, 0x0000, 0, 0), -- MX6Q_PAD_CSI0_DAT14__UART5_TXD = IOMUX_PAD(0x0660, 0x0290, 3, 0x0000, 0, 0), -- MX6Q_PAD_CSI0_DAT14__UART5_TXD_RXD = IOMUX_PAD(0x0660, 0x0290, 3, 0x0940, 2, 0), -- MX6Q_PAD_CSI0_DAT14__SDMA_DEBUG_PC_8 = IOMUX_PAD(0x0660, 0x0290, 4, 0x0000, 0, 0), -- MX6Q_PAD_CSI0_DAT14__GPIO_6_0 = IOMUX_PAD(0x0660, 0x0290, 5, 0x0000, 0, 0), -- MX6Q_PAD_CSI0_DAT14__MMDC_MMDC_DEBUG_37 = IOMUX_PAD(0x0660, 0x0290, 6, 0x0000, 0, 0), -- MX6Q_PAD_CSI0_DAT14__CHEETAH_TRACE_11 = IOMUX_PAD(0x0660, 0x0290, 7, 0x0000, 0, 0), -- MX6Q_PAD_CSI0_DAT15__IPU1_CSI0_D_15 = IOMUX_PAD(0x0664, 0x0294, 0, 0x0000, 0, 0), -- MX6Q_PAD_CSI0_DAT15__WEIM_WEIM_D_11 = IOMUX_PAD(0x0664, 0x0294, 1, 0x0000, 0, 0), -- MX6Q_PAD_CSI0_DAT15__PCIE_CTRL_MUX_19 = IOMUX_PAD(0x0664, 0x0294, 2, 0x0000, 0, 0), -- MX6Q_PAD_CSI0_DAT15__UART5_RXD = IOMUX_PAD(0x0664, 0x0294, 3, 0x0940, 3, 0), -- MX6Q_PAD_CSI0_DAT15__SDMA_DEBUG_PC_9 = IOMUX_PAD(0x0664, 0x0294, 4, 0x0000, 0, 0), -- MX6Q_PAD_CSI0_DAT15__GPIO_6_1 = IOMUX_PAD(0x0664, 0x0294, 5, 0x0000, 0, 0), -- MX6Q_PAD_CSI0_DAT15__MMDC_MMDC_DEBUG_38 = IOMUX_PAD(0x0664, 0x0294, 6, 0x0000, 0, 0), -- MX6Q_PAD_CSI0_DAT15__CHEETAH_TRACE_12 = IOMUX_PAD(0x0664, 0x0294, 7, 0x0000, 0, 0), -- MX6Q_PAD_CSI0_DAT16__IPU1_CSI0_D_16 = IOMUX_PAD(0x0668, 0x0298, 0, 0x0000, 0, 0), -- MX6Q_PAD_CSI0_DAT16__WEIM_WEIM_D_12 = IOMUX_PAD(0x0668, 0x0298, 1, 0x0000, 0, 0), -- MX6Q_PAD_CSI0_DAT16__PCIE_CTRL_MUX_20 = IOMUX_PAD(0x0668, 0x0298, 2, 0x0000, 0, 0), -- MX6Q_PAD_CSI0_DAT16__UART4_CTS = IOMUX_PAD(0x0668, 0x0298, 3, 0x0000, 0, 0), -- MX6Q_PAD_CSI0_DAT16__UART4_RTS = IOMUX_PAD(0x0668, 0x0298, 3, 0x0934, 0, 0), -- MX6Q_PAD_CSI0_DAT16__SDMA_DEBUG_PC_10 = IOMUX_PAD(0x0668, 0x0298, 4, 0x0000, 0, 0), -- MX6Q_PAD_CSI0_DAT16__GPIO_6_2 = IOMUX_PAD(0x0668, 0x0298, 5, 0x0000, 0, 0), -- MX6Q_PAD_CSI0_DAT16__MMDC_MMDC_DEBUG_39 = IOMUX_PAD(0x0668, 0x0298, 6, 0x0000, 0, 0), -- MX6Q_PAD_CSI0_DAT16__CHEETAH_TRACE_13 = IOMUX_PAD(0x0668, 0x0298, 7, 0x0000, 0, 0), -- MX6Q_PAD_CSI0_DAT17__IPU1_CSI0_D_17 = IOMUX_PAD(0x066C, 0x029C, 0, 0x0000, 0, 0), -- MX6Q_PAD_CSI0_DAT17__WEIM_WEIM_D_13 = IOMUX_PAD(0x066C, 0x029C, 1, 0x0000, 0, 0), -- MX6Q_PAD_CSI0_DAT17__PCIE_CTRL_MUX_21 = IOMUX_PAD(0x066C, 0x029C, 2, 0x0000, 0, 0), -- MX6Q_PAD_CSI0_DAT17__UART4_CTS = IOMUX_PAD(0x066C, 0x029C, 3, 0x0934, 1, 0), -- MX6Q_PAD_CSI0_DAT17__SDMA_DEBUG_PC_11 = IOMUX_PAD(0x066C, 0x029C, 4, 0x0000, 0, 0), -- MX6Q_PAD_CSI0_DAT17__GPIO_6_3 = IOMUX_PAD(0x066C, 0x029C, 5, 0x0000, 0, 0), -- MX6Q_PAD_CSI0_DAT17__MMDC_MMDC_DEBUG_40 = IOMUX_PAD(0x066C, 0x029C, 6, 0x0000, 0, 0), -- MX6Q_PAD_CSI0_DAT17__CHEETAH_TRACE_14 = IOMUX_PAD(0x066C, 0x029C, 7, 0x0000, 0, 0), -- MX6Q_PAD_CSI0_DAT18__IPU1_CSI0_D_18 = IOMUX_PAD(0x0670, 0x02A0, 0, 0x0000, 0, 0), -- MX6Q_PAD_CSI0_DAT18__WEIM_WEIM_D_14 = IOMUX_PAD(0x0670, 0x02A0, 1, 0x0000, 0, 0), -- MX6Q_PAD_CSI0_DAT18__PCIE_CTRL_MUX_22 = IOMUX_PAD(0x0670, 0x02A0, 2, 0x0000, 0, 0), -- MX6Q_PAD_CSI0_DAT18__UART5_CTS = IOMUX_PAD(0x0670, 0x02A0, 3, 0x0000, 0, 0), -- MX6Q_PAD_CSI0_DAT18__UART5_RTS = IOMUX_PAD(0x0670, 0x02A0, 3, 0x093C, 2, 0), -- MX6Q_PAD_CSI0_DAT18__SDMA_DEBUG_PC_12 = IOMUX_PAD(0x0670, 0x02A0, 4, 0x0000, 0, 0), -- MX6Q_PAD_CSI0_DAT18__GPIO_6_4 = IOMUX_PAD(0x0670, 0x02A0, 5, 0x0000, 0, 0), -- MX6Q_PAD_CSI0_DAT18__MMDC_MMDC_DEBUG_41 = IOMUX_PAD(0x0670, 0x02A0, 6, 0x0000, 0, 0), -- MX6Q_PAD_CSI0_DAT18__CHEETAH_TRACE_15 = IOMUX_PAD(0x0670, 0x02A0, 7, 0x0000, 0, 0), -- MX6Q_PAD_CSI0_DAT19__IPU1_CSI0_D_19 = IOMUX_PAD(0x0674, 0x02A4, 0, 0x0000, 0, 0), -- MX6Q_PAD_CSI0_DAT19__WEIM_WEIM_D_15 = IOMUX_PAD(0x0674, 0x02A4, 1, 0x0000, 0, 0), -- MX6Q_PAD_CSI0_DAT19__PCIE_CTRL_MUX_23 = IOMUX_PAD(0x0674, 0x02A4, 2, 0x0000, 0, 0), -- MX6Q_PAD_CSI0_DAT19__UART5_CTS = IOMUX_PAD(0x0674, 0x02A4, 3, 0x093C, 3, 0), -- MX6Q_PAD_CSI0_DAT19__SDMA_DEBUG_PC_13 = IOMUX_PAD(0x0674, 0x02A4, 4, 0x0000, 0, 0), -- MX6Q_PAD_CSI0_DAT19__GPIO_6_5 = IOMUX_PAD(0x0674, 0x02A4, 5, 0x0000, 0, 0), -- MX6Q_PAD_CSI0_DAT19__MMDC_MMDC_DEBUG_42 = IOMUX_PAD(0x0674, 0x02A4, 6, 0x0000, 0, 0), -- MX6Q_PAD_CSI0_DAT19__ANATOP_TESTO_9 = IOMUX_PAD(0x0674, 0x02A4, 7, 0x0000, 0, 0), -- MX6Q_PAD_JTAG_TMS__SJC_TMS = IOMUX_PAD(0x0678, NO_MUX_I, 0, 0x0000, 0, 0), -- MX6Q_PAD_JTAG_MOD__SJC_MOD = IOMUX_PAD(0x067C, NO_MUX_I, 0, 0x0000, 0, 0), -- MX6Q_PAD_JTAG_TRSTB__SJC_TRSTB = IOMUX_PAD(0x0680, NO_MUX_I, 0, 0x0000, 0, 0), -- MX6Q_PAD_JTAG_TDI__SJC_TDI = IOMUX_PAD(0x0684, NO_MUX_I, 0, 0x0000, 0, 0), -- MX6Q_PAD_JTAG_TCK__SJC_TCK = IOMUX_PAD(0x0688, NO_MUX_I, 0, 0x0000, 0, 0), -- MX6Q_PAD_JTAG_TDO__SJC_TDO = IOMUX_PAD(0x068C, NO_MUX_I, 0, 0x0000, 0, 0), -- MX6Q_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), -- MX6Q_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), -- MX6Q_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), -- MX6Q_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), -- MX6Q_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), -- MX6Q_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), -- MX6Q_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), -- MX6Q_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), -- MX6Q_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), -- MX6Q_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), -- MX6Q_PAD_TAMPER__SNVS_LP_WRAP_SNVS_TD1 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), -- MX6Q_PAD_PMIC_ON_REQ__SNVS_LPWRAP_WKALM = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), -- MX6Q_PAD_PMIC_STBY_REQ__CCM_PMIC_STBYRQ = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), -- MX6Q_PAD_POR_B__SRC_POR_B = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), -- MX6Q_PAD_BOOT_MODE1__SRC_BOOT_MODE_1 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), -- MX6Q_PAD_RESET_IN_B__SRC_RESET_B = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), -- MX6Q_PAD_BOOT_MODE0__SRC_BOOT_MODE_0 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), -- MX6Q_PAD_TEST_MODE__TCU_TEST_MODE = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), -- MX6Q_PAD_SD3_DAT7__USDHC3_DAT7 = IOMUX_PAD(0x0690, 0x02A8, 0, 0x0000, 0, 0), -- MX6Q_PAD_SD3_DAT7__UART1_TXD = IOMUX_PAD(0x0690, 0x02A8, 1, 0x0000, 0, 0), -- MX6Q_PAD_SD3_DAT7__UART1_TXD_RXD = IOMUX_PAD(0x0690, 0x02A8, 1, 0x0920, 2, 0), -- MX6Q_PAD_SD3_DAT7__PCIE_CTRL_MUX_24 = IOMUX_PAD(0x0690, 0x02A8, 2, 0x0000, 0, 0), -- MX6Q_PAD_SD3_DAT7__USBOH3_UH3_DFD_OUT_0 = IOMUX_PAD(0x0690, 0x02A8, 3, 0x0000, 0, 0), -- MX6Q_PAD_SD3_DAT7__USBOH3_UH2_DFD_OUT_0 = IOMUX_PAD(0x0690, 0x02A8, 4, 0x0000, 0, 0), -- MX6Q_PAD_SD3_DAT7__GPIO_6_17 = IOMUX_PAD(0x0690, 0x02A8, 5, 0x0000, 0, 0), -- MX6Q_PAD_SD3_DAT7__MIPI_CORE_DPHY_IN_12 = IOMUX_PAD(0x0690, 0x02A8, 6, 0x0000, 0, 0), -- MX6Q_PAD_SD3_DAT7__USBPHY2_CLK20DIV = IOMUX_PAD(0x0690, 0x02A8, 7, 0x0000, 0, 0), -- MX6Q_PAD_SD3_DAT6__USDHC3_DAT6 = IOMUX_PAD(0x0694, 0x02AC, 0, 0x0000, 0, 0), -- MX6Q_PAD_SD3_DAT6__UART1_RXD = IOMUX_PAD(0x0694, 0x02AC, 1, 0x0920, 3, 0), -- MX6Q_PAD_SD3_DAT6__PCIE_CTRL_MUX_25 = IOMUX_PAD(0x0694, 0x02AC, 2, 0x0000, 0, 0), -- MX6Q_PAD_SD3_DAT6__USBOH3_UH3_DFD_OUT_1 = IOMUX_PAD(0x0694, 0x02AC, 3, 0x0000, 0, 0), -- MX6Q_PAD_SD3_DAT6__USBOH3_UH2_DFD_OUT_1 = IOMUX_PAD(0x0694, 0x02AC, 4, 0x0000, 0, 0), -- MX6Q_PAD_SD3_DAT6__GPIO_6_18 = IOMUX_PAD(0x0694, 0x02AC, 5, 0x0000, 0, 0), -- MX6Q_PAD_SD3_DAT6__MIPI_CORE_DPHY_IN_13 = IOMUX_PAD(0x0694, 0x02AC, 6, 0x0000, 0, 0), -- MX6Q_PAD_SD3_DAT6__ANATOP_TESTO_10 = IOMUX_PAD(0x0694, 0x02AC, 7, 0x0000, 0, 0), -- MX6Q_PAD_SD3_DAT5__USDHC3_DAT5 = IOMUX_PAD(0x0698, 0x02B0, 0, 0x0000, 0, 0), -- MX6Q_PAD_SD3_DAT5__UART2_TXD = IOMUX_PAD(0x0698, 0x02B0, 1, 0x0000, 0, 0), -- MX6Q_PAD_SD3_DAT5__UART2_TXD_RXD = IOMUX_PAD(0x0698, 0x02B0, 1, 0x0928, 4, 0), -- MX6Q_PAD_SD3_DAT5__PCIE_CTRL_MUX_26 = IOMUX_PAD(0x0698, 0x02B0, 2, 0x0000, 0, 0), -- MX6Q_PAD_SD3_DAT5__USBOH3_UH3_DFD_OUT_2 = IOMUX_PAD(0x0698, 0x02B0, 3, 0x0000, 0, 0), -- MX6Q_PAD_SD3_DAT5__USBOH3_UH2_DFD_OUT_2 = IOMUX_PAD(0x0698, 0x02B0, 4, 0x0000, 0, 0), -- MX6Q_PAD_SD3_DAT5__GPIO_7_0 = IOMUX_PAD(0x0698, 0x02B0, 5, 0x0000, 0, 0), -- MX6Q_PAD_SD3_DAT5__MIPI_CORE_DPHY_IN_14 = IOMUX_PAD(0x0698, 0x02B0, 6, 0x0000, 0, 0), -- MX6Q_PAD_SD3_DAT5__ANATOP_TESTO_11 = IOMUX_PAD(0x0698, 0x02B0, 7, 0x0000, 0, 0), -- MX6Q_PAD_SD3_DAT4__USDHC3_DAT4 = IOMUX_PAD(0x069C, 0x02B4, 0, 0x0000, 0, 0), -- MX6Q_PAD_SD3_DAT4__UART2_RXD = IOMUX_PAD(0x069C, 0x02B4, 1, 0x0928, 5, 0), -- MX6Q_PAD_SD3_DAT4__PCIE_CTRL_MUX_27 = IOMUX_PAD(0x069C, 0x02B4, 2, 0x0000, 0, 0), -- MX6Q_PAD_SD3_DAT4__USBOH3_UH3_DFD_OUT_3 = IOMUX_PAD(0x069C, 0x02B4, 3, 0x0000, 0, 0), -- MX6Q_PAD_SD3_DAT4__USBOH3_UH2_DFD_OUT_3 = IOMUX_PAD(0x069C, 0x02B4, 4, 0x0000, 0, 0), -- MX6Q_PAD_SD3_DAT4__GPIO_7_1 = IOMUX_PAD(0x069C, 0x02B4, 5, 0x0000, 0, 0), -- MX6Q_PAD_SD3_DAT4__MIPI_CORE_DPHY_IN_15 = IOMUX_PAD(0x069C, 0x02B4, 6, 0x0000, 0, 0), -- MX6Q_PAD_SD3_DAT4__ANATOP_TESTO_12 = IOMUX_PAD(0x069C, 0x02B4, 7, 0x0000, 0, 0), -- MX6Q_PAD_SD3_CMD__USDHC3_CMD = IOMUX_PAD(0x06A0, 0x02B8, 16, 0x0000, 0, 0), -- MX6Q_PAD_SD3_CMD__UART2_CTS = IOMUX_PAD(0x06A0, 0x02B8, 1, 0x0924, 2, 0), -- MX6Q_PAD_SD3_CMD__CAN1_TXCAN = IOMUX_PAD(0x06A0, 0x02B8, 2, 0x0000, 0, 0), -- MX6Q_PAD_SD3_CMD__USBOH3_UH3_DFD_OUT_4 = IOMUX_PAD(0x06A0, 0x02B8, 3, 0x0000, 0, 0), -- MX6Q_PAD_SD3_CMD__USBOH3_UH2_DFD_OUT_4 = IOMUX_PAD(0x06A0, 0x02B8, 4, 0x0000, 0, 0), -- MX6Q_PAD_SD3_CMD__GPIO_7_2 = IOMUX_PAD(0x06A0, 0x02B8, 5, 0x0000, 0, 0), -- MX6Q_PAD_SD3_CMD__MIPI_CORE_DPHY_IN_16 = IOMUX_PAD(0x06A0, 0x02B8, 6, 0x0000, 0, 0), -- MX6Q_PAD_SD3_CMD__ANATOP_TESTO_13 = IOMUX_PAD(0x06A0, 0x02B8, 7, 0x0000, 0, 0), -- MX6Q_PAD_SD3_CLK__USDHC3_CLK = IOMUX_PAD(0x06A4, 0x02BC, 0, 0x0000, 0, 0), -- MX6Q_PAD_SD3_CLK__UART2_CTS = IOMUX_PAD(0x06A4, 0x02BC, 1, 0x0000, 0, 0), -- MX6Q_PAD_SD3_CLK__UART2_RTS = IOMUX_PAD(0x06A4, 0x02BC, 1, 0x0924, 3, 0), -- MX6Q_PAD_SD3_CLK__CAN1_RXCAN = IOMUX_PAD(0x06A4, 0x02BC, 2, 0x07E4, 2, 0), -- MX6Q_PAD_SD3_CLK__USBOH3_UH3_DFD_OUT_5 = IOMUX_PAD(0x06A4, 0x02BC, 3, 0x0000, 0, 0), -- MX6Q_PAD_SD3_CLK__USBOH3_UH2_DFD_OUT_5 = IOMUX_PAD(0x06A4, 0x02BC, 4, 0x0000, 0, 0), -- MX6Q_PAD_SD3_CLK__GPIO_7_3 = IOMUX_PAD(0x06A4, 0x02BC, 5, 0x0000, 0, 0), -- MX6Q_PAD_SD3_CLK__MIPI_CORE_DPHY_IN_17 = IOMUX_PAD(0x06A4, 0x02BC, 6, 0x0000, 0, 0), -- MX6Q_PAD_SD3_CLK__ANATOP_TESTO_14 = IOMUX_PAD(0x06A4, 0x02BC, 7, 0x0000, 0, 0), -- MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 = IOMUX_PAD(0x06A8, 0x02C0, 0, 0x0000, 0, 0), -- MX6Q_PAD_SD3_DAT0__UART1_CTS = IOMUX_PAD(0x06A8, 0x02C0, 1, 0x091C, 2, 0), -- MX6Q_PAD_SD3_DAT0__CAN2_TXCAN = IOMUX_PAD(0x06A8, 0x02C0, 2, 0x0000, 0, 0), -- MX6Q_PAD_SD3_DAT0__USBOH3_UH3_DFD_OUT_6 = IOMUX_PAD(0x06A8, 0x02C0, 3, 0x0000, 0, 0), -- MX6Q_PAD_SD3_DAT0__USBOH3_UH2_DFD_OUT_6 = IOMUX_PAD(0x06A8, 0x02C0, 4, 0x0000, 0, 0), -- MX6Q_PAD_SD3_DAT0__GPIO_7_4 = IOMUX_PAD(0x06A8, 0x02C0, 5, 0x0000, 0, 0), -- MX6Q_PAD_SD3_DAT0__MIPI_CORE_DPHY_IN_18 = IOMUX_PAD(0x06A8, 0x02C0, 6, 0x0000, 0, 0), -- MX6Q_PAD_SD3_DAT0__ANATOP_TESTO_15 = IOMUX_PAD(0x06A8, 0x02C0, 7, 0x0000, 0, 0), -- MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 = IOMUX_PAD(0x06AC, 0x02C4, 0, 0x0000, 0, 0), -- MX6Q_PAD_SD3_DAT1__UART1_CTS = IOMUX_PAD(0x06AC, 0x02C4, 1, 0x0000, 0, 0), -- MX6Q_PAD_SD3_DAT1__UART1_RTS = IOMUX_PAD(0x06AC, 0x02C4, 1, 0x091C, 3, 0), -- MX6Q_PAD_SD3_DAT1__CAN2_RXCAN = IOMUX_PAD(0x06AC, 0x02C4, 2, 0x07E8, 1, 0), -- MX6Q_PAD_SD3_DAT1__USBOH3_UH3_DFD_OUT_7 = IOMUX_PAD(0x06AC, 0x02C4, 3, 0x0000, 0, 0), -- MX6Q_PAD_SD3_DAT1__USBOH3_UH2_DFD_OUT_7 = IOMUX_PAD(0x06AC, 0x02C4, 4, 0x0000, 0, 0), -- MX6Q_PAD_SD3_DAT1__GPIO_7_5 = IOMUX_PAD(0x06AC, 0x02C4, 5, 0x0000, 0, 0), -- MX6Q_PAD_SD3_DAT1__MIPI_CORE_DPHY_IN_19 = IOMUX_PAD(0x06AC, 0x02C4, 6, 0x0000, 0, 0), -- MX6Q_PAD_SD3_DAT1__ANATOP_TESTI_0 = IOMUX_PAD(0x06AC, 0x02C4, 7, 0x0000, 0, 0), -- MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 = IOMUX_PAD(0x06B0, 0x02C8, 0, 0x0000, 0, 0), -- MX6Q_PAD_SD3_DAT2__PCIE_CTRL_MUX_28 = IOMUX_PAD(0x06B0, 0x02C8, 2, 0x0000, 0, 0), -- MX6Q_PAD_SD3_DAT2__USBOH3_UH3_DFD_OUT_8 = IOMUX_PAD(0x06B0, 0x02C8, 3, 0x0000, 0, 0), -- MX6Q_PAD_SD3_DAT2__USBOH3_UH2_DFD_OUT_8 = IOMUX_PAD(0x06B0, 0x02C8, 4, 0x0000, 0, 0), -- MX6Q_PAD_SD3_DAT2__GPIO_7_6 = IOMUX_PAD(0x06B0, 0x02C8, 5, 0x0000, 0, 0), -- MX6Q_PAD_SD3_DAT2__MIPI_CORE_DPHY_IN_20 = IOMUX_PAD(0x06B0, 0x02C8, 6, 0x0000, 0, 0), -- MX6Q_PAD_SD3_DAT2__ANATOP_TESTI_1 = IOMUX_PAD(0x06B0, 0x02C8, 7, 0x0000, 0, 0), -- MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 = IOMUX_PAD(0x06B4, 0x02CC, 0, 0x0000, 0, 0), -- MX6Q_PAD_SD3_DAT3__UART3_CTS = IOMUX_PAD(0x06B4, 0x02CC, 1, 0x092C, 4, 0), -- MX6Q_PAD_SD3_DAT3__PCIE_CTRL_MUX_29 = IOMUX_PAD(0x06B4, 0x02CC, 2, 0x0000, 0, 0), -- MX6Q_PAD_SD3_DAT3__USBOH3_UH3_DFD_OUT_9 = IOMUX_PAD(0x06B4, 0x02CC, 3, 0x0000, 0, 0), -- MX6Q_PAD_SD3_DAT3__USBOH3_UH2_DFD_OUT_9 = IOMUX_PAD(0x06B4, 0x02CC, 4, 0x0000, 0, 0), -- MX6Q_PAD_SD3_DAT3__GPIO_7_7 = IOMUX_PAD(0x06B4, 0x02CC, 5, 0x0000, 0, 0), -- MX6Q_PAD_SD3_DAT3__MIPI_CORE_DPHY_IN_21 = IOMUX_PAD(0x06B4, 0x02CC, 6, 0x0000, 0, 0), -- MX6Q_PAD_SD3_DAT3__ANATOP_TESTI_2 = IOMUX_PAD(0x06B4, 0x02CC, 7, 0x0000, 0, 0), -- MX6Q_PAD_SD3_RST__USDHC3_RST = IOMUX_PAD(0x06B8, 0x02D0, 0, 0x0000, 0, 0), -- MX6Q_PAD_SD3_RST__UART3_CTS = IOMUX_PAD(0x06B8, 0x02D0, 1, 0x0000, 0, 0), -- MX6Q_PAD_SD3_RST__UART3_RTS = IOMUX_PAD(0x06B8, 0x02D0, 1, 0x092C, 5, 0), -- MX6Q_PAD_SD3_RST__PCIE_CTRL_MUX_30 = IOMUX_PAD(0x06B8, 0x02D0, 2, 0x0000, 0, 0), -- MX6Q_PAD_SD3_RST__USBOH3_UH3_DFD_OUT_10 = IOMUX_PAD(0x06B8, 0x02D0, 3, 0x0000, 0, 0), -- MX6Q_PAD_SD3_RST__USBOH3_UH2_DFD_OUT_10 = IOMUX_PAD(0x06B8, 0x02D0, 4, 0x0000, 0, 0), -- MX6Q_PAD_SD3_RST__GPIO_7_8 = IOMUX_PAD(0x06B8, 0x02D0, 5, 0x0000, 0, 0), -- MX6Q_PAD_SD3_RST__MIPI_CORE_DPHY_IN_22 = IOMUX_PAD(0x06B8, 0x02D0, 6, 0x0000, 0, 0), -- MX6Q_PAD_SD3_RST__ANATOP_ANATOP_TESTI_3 = IOMUX_PAD(0x06B8, 0x02D0, 7, 0x0000, 0, 0), -- MX6Q_PAD_NANDF_CLE__RAWNAND_CLE = IOMUX_PAD(0x06BC, 0x02D4, 0, 0x0000, 0, 0), -- MX6Q_PAD_NANDF_CLE__IPU2_SISG_4 = IOMUX_PAD(0x06BC, 0x02D4, 1, 0x0000, 0, 0), -- MX6Q_PAD_NANDF_CLE__PCIE_CTRL_MUX_31 = IOMUX_PAD(0x06BC, 0x02D4, 2, 0x0000, 0, 0), -- MX6Q_PAD_NANDF_CLE__USBOH3_UH3_DFD_OT11 = IOMUX_PAD(0x06BC, 0x02D4, 3, 0x0000, 0, 0), -- MX6Q_PAD_NANDF_CLE__USBOH3_UH2_DFD_OT11 = IOMUX_PAD(0x06BC, 0x02D4, 4, 0x0000, 0, 0), -- MX6Q_PAD_NANDF_CLE__GPIO_6_7 = IOMUX_PAD(0x06BC, 0x02D4, 5, 0x0000, 0, 0), -- MX6Q_PAD_NANDF_CLE__MIPI_CORE_DPHY_IN23 = IOMUX_PAD(0x06BC, 0x02D4, 6, 0x0000, 0, 0), -- MX6Q_PAD_NANDF_CLE__TPSMP_HTRANS_0 = IOMUX_PAD(0x06BC, 0x02D4, 7, 0x0000, 0, 0), -- MX6Q_PAD_NANDF_ALE__RAWNAND_ALE = IOMUX_PAD(0x06C0, 0x02D8, 0, 0x0000, 0, 0), -- MX6Q_PAD_NANDF_ALE__USDHC4_RST = IOMUX_PAD(0x06C0, 0x02D8, 1, 0x0000, 0, 0), -- MX6Q_PAD_NANDF_ALE__PCIE_CTRL_MUX_0 = IOMUX_PAD(0x06C0, 0x02D8, 2, 0x0000, 0, 0), -- MX6Q_PAD_NANDF_ALE__USBOH3_UH3_DFD_OT12 = IOMUX_PAD(0x06C0, 0x02D8, 3, 0x0000, 0, 0), -- MX6Q_PAD_NANDF_ALE__USBOH3_UH2_DFD_OT12 = IOMUX_PAD(0x06C0, 0x02D8, 4, 0x0000, 0, 0), -- MX6Q_PAD_NANDF_ALE__GPIO_6_8 = IOMUX_PAD(0x06C0, 0x02D8, 5, 0x0000, 0, 0), -- MX6Q_PAD_NANDF_ALE__MIPI_CR_DPHY_IN_24 = IOMUX_PAD(0x06C0, 0x02D8, 6, 0x0000, 0, 0), -- MX6Q_PAD_NANDF_ALE__TPSMP_HTRANS_1 = IOMUX_PAD(0x06C0, 0x02D8, 7, 0x0000, 0, 0), -- MX6Q_PAD_NANDF_WP_B__RAWNAND_RESETN = IOMUX_PAD(0x06C4, 0x02DC, 0, 0x0000, 0, 0), -- MX6Q_PAD_NANDF_WP_B__IPU2_SISG_5 = IOMUX_PAD(0x06C4, 0x02DC, 1, 0x0000, 0, 0), -- MX6Q_PAD_NANDF_WP_B__PCIE_CTRL__MUX_1 = IOMUX_PAD(0x06C4, 0x02DC, 2, 0x0000, 0, 0), -- MX6Q_PAD_NANDF_WP_B__USBOH3_UH3_DFDOT13 = IOMUX_PAD(0x06C4, 0x02DC, 3, 0x0000, 0, 0), -- MX6Q_PAD_NANDF_WP_B__USBOH3_UH2_DFDOT13 = IOMUX_PAD(0x06C4, 0x02DC, 4, 0x0000, 0, 0), -- MX6Q_PAD_NANDF_WP_B__GPIO_6_9 = IOMUX_PAD(0x06C4, 0x02DC, 5, 0x0000, 0, 0), -- MX6Q_PAD_NANDF_WP_B__MIPI_CR_DPHY_OUT32 = IOMUX_PAD(0x06C4, 0x02DC, 6, 0x0000, 0, 0), -- MX6Q_PAD_NANDF_WP_B__PL301_PER1_HSIZE_0 = IOMUX_PAD(0x06C4, 0x02DC, 7, 0x0000, 0, 0), -- MX6Q_PAD_NANDF_RB0__RAWNAND_READY0 = IOMUX_PAD(0x06C8, 0x02E0, 0, 0x0000, 0, 0), -- MX6Q_PAD_NANDF_RB0__IPU2_DI0_PIN1 = IOMUX_PAD(0x06C8, 0x02E0, 1, 0x0000, 0, 0), -- MX6Q_PAD_NANDF_RB0__PCIE_CTRL_MUX_2 = IOMUX_PAD(0x06C8, 0x02E0, 2, 0x0000, 0, 0), -- MX6Q_PAD_NANDF_RB0__USBOH3_UH3_DFD_OT14 = IOMUX_PAD(0x06C8, 0x02E0, 3, 0x0000, 0, 0), -- MX6Q_PAD_NANDF_RB0__USBOH3_UH2_DFD_OT14 = IOMUX_PAD(0x06C8, 0x02E0, 4, 0x0000, 0, 0), -- MX6Q_PAD_NANDF_RB0__GPIO_6_10 = IOMUX_PAD(0x06C8, 0x02E0, 5, 0x0000, 0, 0), -- MX6Q_PAD_NANDF_RB0__MIPI_CR_DPHY_OUT_33 = IOMUX_PAD(0x06C8, 0x02E0, 6, 0x0000, 0, 0), -- MX6Q_PAD_NANDF_RB0__PL301_PER1_HSIZE_1 = IOMUX_PAD(0x06C8, 0x02E0, 7, 0x0000, 0, 0), -- MX6Q_PAD_NANDF_CS0__RAWNAND_CE0N = IOMUX_PAD(0x06CC, 0x02E4, 0, 0x0000, 0, 0), -- MX6Q_PAD_NANDF_CS0__USBOH3_UH3_DFD_OT15 = IOMUX_PAD(0x06CC, 0x02E4, 3, 0x0000, 0, 0), -- MX6Q_PAD_NANDF_CS0__USBOH3_UH2_DFD_OT15 = IOMUX_PAD(0x06CC, 0x02E4, 4, 0x0000, 0, 0), -- MX6Q_PAD_NANDF_CS0__GPIO_6_11 = IOMUX_PAD(0x06CC, 0x02E4, 5, 0x0000, 0, 0), -- MX6Q_PAD_NANDF_CS0__PL301_PER1_HSIZE_2 = IOMUX_PAD(0x06CC, 0x02E4, 7, 0x0000, 0, 0), -- MX6Q_PAD_NANDF_CS1__RAWNAND_CE1N = IOMUX_PAD(0x06D0, 0x02E8, 0, 0x0000, 0, 0), -- MX6Q_PAD_NANDF_CS1__USDHC4_VSELECT = IOMUX_PAD(0x06D0, 0x02E8, 1, 0x0000, 0, 0), -- MX6Q_PAD_NANDF_CS1__USDHC3_VSELECT = IOMUX_PAD(0x06D0, 0x02E8, 2, 0x0000, 0, 0), -- MX6Q_PAD_NANDF_CS1__PCIE_CTRL_MUX_3 = IOMUX_PAD(0x06D0, 0x02E8, 4, 0x0000, 0, 0), -- MX6Q_PAD_NANDF_CS1__GPIO_6_14 = IOMUX_PAD(0x06D0, 0x02E8, 5, 0x0000, 0, 0), -- MX6Q_PAD_NANDF_CS1__PL301_PER1_HRDYOUT = IOMUX_PAD(0x06D0, 0x02E8, 7, 0x0000, 0, 0), -- MX6Q_PAD_NANDF_CS2__RAWNAND_CE2N = IOMUX_PAD(0x06D4, 0x02EC, 0, 0x0000, 0, 0), -- MX6Q_PAD_NANDF_CS2__IPU1_SISG_0 = IOMUX_PAD(0x06D4, 0x02EC, 1, 0x0000, 0, 0), -- MX6Q_PAD_NANDF_CS2__ESAI1_TX0 = IOMUX_PAD(0x06D4, 0x02EC, 2, 0x0874, 1, 0), -- MX6Q_PAD_NANDF_CS2__WEIM_WEIM_CRE = IOMUX_PAD(0x06D4, 0x02EC, 3, 0x0000, 0, 0), -- MX6Q_PAD_NANDF_CS2__CCM_CLKO2 = IOMUX_PAD(0x06D4, 0x02EC, 4, 0x0000, 0, 0), -- MX6Q_PAD_NANDF_CS2__GPIO_6_15 = IOMUX_PAD(0x06D4, 0x02EC, 5, 0x0000, 0, 0), -- MX6Q_PAD_NANDF_CS2__IPU2_SISG_0 = IOMUX_PAD(0x06D4, 0x02EC, 6, 0x0000, 0, 0), -- MX6Q_PAD_NANDF_CS3__RAWNAND_CE3N = IOMUX_PAD(0x06D8, 0x02F0, 0, 0x0000, 0, 0), -- MX6Q_PAD_NANDF_CS3__IPU1_SISG_1 = IOMUX_PAD(0x06D8, 0x02F0, 1, 0x0000, 0, 0), -- MX6Q_PAD_NANDF_CS3__ESAI1_TX1 = IOMUX_PAD(0x06D8, 0x02F0, 2, 0x0878, 1, 0), -- MX6Q_PAD_NANDF_CS3__WEIM_WEIM_A_26 = IOMUX_PAD(0x06D8, 0x02F0, 3, 0x0000, 0, 0), -- MX6Q_PAD_NANDF_CS3__PCIE_CTRL_MUX_4 = IOMUX_PAD(0x06D8, 0x02F0, 4, 0x0000, 0, 0), -- MX6Q_PAD_NANDF_CS3__GPIO_6_16 = IOMUX_PAD(0x06D8, 0x02F0, 5, 0x0000, 0, 0), -- MX6Q_PAD_NANDF_CS3__IPU2_SISG_1 = IOMUX_PAD(0x06D8, 0x02F0, 6, 0x0000, 0, 0), -- MX6Q_PAD_NANDF_CS3__TPSMP_CLK = IOMUX_PAD(0x06D8, 0x02F0, 7, 0x0000, 0, 0), -- MX6Q_PAD_SD4_CMD__USDHC4_CMD = IOMUX_PAD(0x06DC, 0x02F4, 16, 0x0000, 0, 0), -- MX6Q_PAD_SD4_CMD__RAWNAND_RDN = IOMUX_PAD(0x06DC, 0x02F4, 1, 0x0000, 0, 0), -- MX6Q_PAD_SD4_CMD__UART3_TXD = IOMUX_PAD(0x06DC, 0x02F4, 2, 0x0000, 0, 0), -- MX6Q_PAD_SD4_CMD__UART3_TXD_RXD = IOMUX_PAD(0x06DC, 0x02F4, 2, 0x0930, 2, 0), -- MX6Q_PAD_SD4_CMD__PCIE_CTRL_MUX_5 = IOMUX_PAD(0x06DC, 0x02F4, 4, 0x0000, 0, 0), -- MX6Q_PAD_SD4_CMD__GPIO_7_9 = IOMUX_PAD(0x06DC, 0x02F4, 5, 0x0000, 0, 0), -- MX6Q_PAD_SD4_CMD__TPSMP_HDATA_DIR = IOMUX_PAD(0x06DC, 0x02F4, 7, 0x0000, 0, 0), -- MX6Q_PAD_SD4_CLK__USDHC4_CLK = IOMUX_PAD(0x06E0, 0x02F8, 0, 0x0000, 0, 0), -- MX6Q_PAD_SD4_CLK__RAWNAND_WRN = IOMUX_PAD(0x06E0, 0x02F8, 1, 0x0000, 0, 0), -- MX6Q_PAD_SD4_CLK__UART3_RXD = IOMUX_PAD(0x06E0, 0x02F8, 2, 0x0930, 3, 0), -- MX6Q_PAD_SD4_CLK__PCIE_CTRL_MUX_6 = IOMUX_PAD(0x06E0, 0x02F8, 4, 0x0000, 0, 0), -- MX6Q_PAD_SD4_CLK__GPIO_7_10 = IOMUX_PAD(0x06E0, 0x02F8, 5, 0x0000, 0, 0), -- MX6Q_PAD_NANDF_D0__RAWNAND_D0 = IOMUX_PAD(0x06E4, 0x02FC, 0, 0x0000, 0, 0), -- MX6Q_PAD_NANDF_D0__USDHC1_DAT4 = IOMUX_PAD(0x06E4, 0x02FC, 1, 0x0000, 0, 0), -- MX6Q_PAD_NANDF_D0__GPU3D_GPU_DBG_OUT_0 = IOMUX_PAD(0x06E4, 0x02FC, 2, 0x0000, 0, 0), -- MX6Q_PAD_NANDF_D0__USBOH3_UH2_DFD_OUT16 = IOMUX_PAD(0x06E4, 0x02FC, 3, 0x0000, 0, 0), -- MX6Q_PAD_NANDF_D0__USBOH3_UH3_DFD_OUT16 = IOMUX_PAD(0x06E4, 0x02FC, 4, 0x0000, 0, 0), -- MX6Q_PAD_NANDF_D0__GPIO_2_0 = IOMUX_PAD(0x06E4, 0x02FC, 5, 0x0000, 0, 0), -- MX6Q_PAD_NANDF_D0__IPU1_IPU_DIAG_BUS_0 = IOMUX_PAD(0x06E4, 0x02FC, 6, 0x0000, 0, 0), -- MX6Q_PAD_NANDF_D0__IPU2_IPU_DIAG_BUS_0 = IOMUX_PAD(0x06E4, 0x02FC, 7, 0x0000, 0, 0), -- MX6Q_PAD_NANDF_D1__RAWNAND_D1 = IOMUX_PAD(0x06E8, 0x0300, 0, 0x0000, 0, 0), -- MX6Q_PAD_NANDF_D1__USDHC1_DAT5 = IOMUX_PAD(0x06E8, 0x0300, 1, 0x0000, 0, 0), -- MX6Q_PAD_NANDF_D1__GPU3D_GPU_DEBUG_OUT1 = IOMUX_PAD(0x06E8, 0x0300, 2, 0x0000, 0, 0), -- MX6Q_PAD_NANDF_D1__USBOH3_UH2_DFD_OUT17 = IOMUX_PAD(0x06E8, 0x0300, 3, 0x0000, 0, 0), -- MX6Q_PAD_NANDF_D1__USBOH3_UH3_DFD_OUT17 = IOMUX_PAD(0x06E8, 0x0300, 4, 0x0000, 0, 0), -- MX6Q_PAD_NANDF_D1__GPIO_2_1 = IOMUX_PAD(0x06E8, 0x0300, 5, 0x0000, 0, 0), -- MX6Q_PAD_NANDF_D1__IPU1_IPU_DIAG_BUS_1 = IOMUX_PAD(0x06E8, 0x0300, 6, 0x0000, 0, 0), -- MX6Q_PAD_NANDF_D1__IPU2_IPU_DIAG_BUS_1 = IOMUX_PAD(0x06E8, 0x0300, 7, 0x0000, 0, 0), -- MX6Q_PAD_NANDF_D2__RAWNAND_D2 = IOMUX_PAD(0x06EC, 0x0304, 0, 0x0000, 0, 0), -- MX6Q_PAD_NANDF_D2__USDHC1_DAT6 = IOMUX_PAD(0x06EC, 0x0304, 1, 0x0000, 0, 0), -- MX6Q_PAD_NANDF_D2__GPU3D_GPU_DBG_OUT_2 = IOMUX_PAD(0x06EC, 0x0304, 2, 0x0000, 0, 0), -- MX6Q_PAD_NANDF_D2__USBOH3_UH2_DFD_OUT18 = IOMUX_PAD(0x06EC, 0x0304, 3, 0x0000, 0, 0), -- MX6Q_PAD_NANDF_D2__USBOH3_UH3_DFD_OUT18 = IOMUX_PAD(0x06EC, 0x0304, 4, 0x0000, 0, 0), -- MX6Q_PAD_NANDF_D2__GPIO_2_2 = IOMUX_PAD(0x06EC, 0x0304, 5, 0x0000, 0, 0), -- MX6Q_PAD_NANDF_D2__IPU1_IPU_DIAG_BUS_2 = IOMUX_PAD(0x06EC, 0x0304, 6, 0x0000, 0, 0), -- MX6Q_PAD_NANDF_D2__IPU2_IPU_DIAG_BUS_2 = IOMUX_PAD(0x06EC, 0x0304, 7, 0x0000, 0, 0), -- MX6Q_PAD_NANDF_D3__RAWNAND_D3 = IOMUX_PAD(0x06F0, 0x0308, 0, 0x0000, 0, 0), -- MX6Q_PAD_NANDF_D3__USDHC1_DAT7 = IOMUX_PAD(0x06F0, 0x0308, 1, 0x0000, 0, 0), -- MX6Q_PAD_NANDF_D3__GPU3D_GPU_DBG_OUT_3 = IOMUX_PAD(0x06F0, 0x0308, 2, 0x0000, 0, 0), -- MX6Q_PAD_NANDF_D3__USBOH3_UH2_DFD_OUT19 = IOMUX_PAD(0x06F0, 0x0308, 3, 0x0000, 0, 0), -- MX6Q_PAD_NANDF_D3__USBOH3_UH3_DFD_OUT19 = IOMUX_PAD(0x06F0, 0x0308, 4, 0x0000, 0, 0), -- MX6Q_PAD_NANDF_D3__GPIO_2_3 = IOMUX_PAD(0x06F0, 0x0308, 5, 0x0000, 0, 0), -- MX6Q_PAD_NANDF_D3__IPU1_IPU_DIAG_BUS_3 = IOMUX_PAD(0x06F0, 0x0308, 6, 0x0000, 0, 0), -- MX6Q_PAD_NANDF_D3__IPU2_IPU_DIAG_BUS_3 = IOMUX_PAD(0x06F0, 0x0308, 7, 0x0000, 0, 0), -- MX6Q_PAD_NANDF_D4__RAWNAND_D4 = IOMUX_PAD(0x06F4, 0x030C, 0, 0x0000, 0, 0), -- MX6Q_PAD_NANDF_D4__USDHC2_DAT4 = IOMUX_PAD(0x06F4, 0x030C, 1, 0x0000, 0, 0), -- MX6Q_PAD_NANDF_D4__GPU3D_GPU_DBG_OUT_4 = IOMUX_PAD(0x06F4, 0x030C, 2, 0x0000, 0, 0), -- MX6Q_PAD_NANDF_D4__USBOH3_UH2_DFD_OUT20 = IOMUX_PAD(0x06F4, 0x030C, 3, 0x0000, 0, 0), -- MX6Q_PAD_NANDF_D4__USBOH3_UH3_DFD_OUT20 = IOMUX_PAD(0x06F4, 0x030C, 4, 0x0000, 0, 0), -- MX6Q_PAD_NANDF_D4__GPIO_2_4 = IOMUX_PAD(0x06F4, 0x030C, 5, 0x0000, 0, 0), -- MX6Q_PAD_NANDF_D4__IPU1_IPU_DIAG_BUS_4 = IOMUX_PAD(0x06F4, 0x030C, 6, 0x0000, 0, 0), -- MX6Q_PAD_NANDF_D4__IPU2_IPU_DIAG_BUS_4 = IOMUX_PAD(0x06F4, 0x030C, 7, 0x0000, 0, 0), -- MX6Q_PAD_NANDF_D5__RAWNAND_D5 = IOMUX_PAD(0x06F8, 0x0310, 0, 0x0000, 0, 0), -- MX6Q_PAD_NANDF_D5__USDHC2_DAT5 = IOMUX_PAD(0x06F8, 0x0310, 1, 0x0000, 0, 0), -- MX6Q_PAD_NANDF_D5__GPU3D_GPU_DBG_OUT_5 = IOMUX_PAD(0x06F8, 0x0310, 2, 0x0000, 0, 0), -- MX6Q_PAD_NANDF_D5__USBOH3_UH2_DFD_OUT21 = IOMUX_PAD(0x06F8, 0x0310, 3, 0x0000, 0, 0), -- MX6Q_PAD_NANDF_D5__USBOH3_UH3_DFD_OUT21 = IOMUX_PAD(0x06F8, 0x0310, 4, 0x0000, 0, 0), -- MX6Q_PAD_NANDF_D5__GPIO_2_5 = IOMUX_PAD(0x06F8, 0x0310, 5, 0x0000, 0, 0), -- MX6Q_PAD_NANDF_D5__IPU1_IPU_DIAG_BUS_5 = IOMUX_PAD(0x06F8, 0x0310, 6, 0x0000, 0, 0), -- MX6Q_PAD_NANDF_D5__IPU2_IPU_DIAG_BUS_5 = IOMUX_PAD(0x06F8, 0x0310, 7, 0x0000, 0, 0), -- MX6Q_PAD_NANDF_D6__RAWNAND_D6 = IOMUX_PAD(0x06FC, 0x0314, 0, 0x0000, 0, 0), -- MX6Q_PAD_NANDF_D6__USDHC2_DAT6 = IOMUX_PAD(0x06FC, 0x0314, 1, 0x0000, 0, 0), -- MX6Q_PAD_NANDF_D6__GPU3D_GPU_DBG_OUT_6 = IOMUX_PAD(0x06FC, 0x0314, 2, 0x0000, 0, 0), -- MX6Q_PAD_NANDF_D6__USBOH3_UH2_DFD_OUT22 = IOMUX_PAD(0x06FC, 0x0314, 3, 0x0000, 0, 0), -- MX6Q_PAD_NANDF_D6__USBOH3_UH3_DFD_OUT22 = IOMUX_PAD(0x06FC, 0x0314, 4, 0x0000, 0, 0), -- MX6Q_PAD_NANDF_D6__GPIO_2_6 = IOMUX_PAD(0x06FC, 0x0314, 5, 0x0000, 0, 0), -- MX6Q_PAD_NANDF_D6__IPU1_IPU_DIAG_BUS_6 = IOMUX_PAD(0x06FC, 0x0314, 6, 0x0000, 0, 0), -- MX6Q_PAD_NANDF_D6__IPU2_IPU_DIAG_BUS_6 = IOMUX_PAD(0x06FC, 0x0314, 7, 0x0000, 0, 0), -- MX6Q_PAD_NANDF_D7__RAWNAND_D7 = IOMUX_PAD(0x0700, 0x0318, 0, 0x0000, 0, 0), -- MX6Q_PAD_NANDF_D7__USDHC2_DAT7 = IOMUX_PAD(0x0700, 0x0318, 1, 0x0000, 0, 0), -- MX6Q_PAD_NANDF_D7__GPU3D_GPU_DBG_OUT_7 = IOMUX_PAD(0x0700, 0x0318, 2, 0x0000, 0, 0), -- MX6Q_PAD_NANDF_D7__USBOH3_UH2_DFD_OUT23 = IOMUX_PAD(0x0700, 0x0318, 3, 0x0000, 0, 0), -- MX6Q_PAD_NANDF_D7__USBOH3_UH3_DFD_OUT23 = IOMUX_PAD(0x0700, 0x0318, 4, 0x0000, 0, 0), -- MX6Q_PAD_NANDF_D7__GPIO_2_7 = IOMUX_PAD(0x0700, 0x0318, 5, 0x0000, 0, 0), -- MX6Q_PAD_NANDF_D7__IPU1_IPU_DIAG_BUS_7 = IOMUX_PAD(0x0700, 0x0318, 6, 0x0000, 0, 0), -- MX6Q_PAD_NANDF_D7__IPU2_IPU_DIAG_BUS_7 = IOMUX_PAD(0x0700, 0x0318, 7, 0x0000, 0, 0), -- MX6Q_PAD_SD4_DAT0__RAWNAND_D8 = IOMUX_PAD(0x0704, 0x031C, 0, 0x0000, 0, 0), -- MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 = IOMUX_PAD(0x0704, 0x031C, 1, 0x0000, 0, 0), -- MX6Q_PAD_SD4_DAT0__RAWNAND_DQS = IOMUX_PAD(0x0704, 0x031C, 2, 0x0000, 0, 0), -- MX6Q_PAD_SD4_DAT0__USBOH3_UH2_DFD_OUT24 = IOMUX_PAD(0x0704, 0x031C, 3, 0x0000, 0, 0), -- MX6Q_PAD_SD4_DAT0__USBOH3_UH3_DFD_OUT24 = IOMUX_PAD(0x0704, 0x031C, 4, 0x0000, 0, 0), -- MX6Q_PAD_SD4_DAT0__GPIO_2_8 = IOMUX_PAD(0x0704, 0x031C, 5, 0x0000, 0, 0), -- MX6Q_PAD_SD4_DAT0__IPU1_IPU_DIAG_BUS_8 = IOMUX_PAD(0x0704, 0x031C, 6, 0x0000, 0, 0), -- MX6Q_PAD_SD4_DAT0__IPU2_IPU_DIAG_BUS_8 = IOMUX_PAD(0x0704, 0x031C, 7, 0x0000, 0, 0), -- MX6Q_PAD_SD4_DAT1__RAWNAND_D9 = IOMUX_PAD(0x0708, 0x0320, 0, 0x0000, 0, 0), -- MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 = IOMUX_PAD(0x0708, 0x0320, 1, 0x0000, 0, 0), -- MX6Q_PAD_SD4_DAT1__PWM3_PWMO = IOMUX_PAD(0x0708, 0x0320, 2, 0x0000, 0, 0), -- MX6Q_PAD_SD4_DAT1__USBOH3_UH2_DFD_OUT25 = IOMUX_PAD(0x0708, 0x0320, 3, 0x0000, 0, 0), -- MX6Q_PAD_SD4_DAT1__USBOH3_UH3_DFD_OUT25 = IOMUX_PAD(0x0708, 0x0320, 4, 0x0000, 0, 0), -- MX6Q_PAD_SD4_DAT1__GPIO_2_9 = IOMUX_PAD(0x0708, 0x0320, 5, 0x0000, 0, 0), -- MX6Q_PAD_SD4_DAT1__IPU1_IPU_DIAG_BUS_9 = IOMUX_PAD(0x0708, 0x0320, 6, 0x0000, 0, 0), -- MX6Q_PAD_SD4_DAT1__IPU2_IPU_DIAG_BUS_9 = IOMUX_PAD(0x0708, 0x0320, 7, 0x0000, 0, 0), -- MX6Q_PAD_SD4_DAT2__RAWNAND_D10 = IOMUX_PAD(0x070C, 0x0324, 0, 0x0000, 0, 0), -- MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 = IOMUX_PAD(0x070C, 0x0324, 1, 0x0000, 0, 0), -- MX6Q_PAD_SD4_DAT2__PWM4_PWMO = IOMUX_PAD(0x070C, 0x0324, 2, 0x0000, 0, 0), -- MX6Q_PAD_SD4_DAT2__USBOH3_UH2_DFD_OUT26 = IOMUX_PAD(0x070C, 0x0324, 3, 0x0000, 0, 0), -- MX6Q_PAD_SD4_DAT2__USBOH3_UH3_DFD_OUT26 = IOMUX_PAD(0x070C, 0x0324, 4, 0x0000, 0, 0), -- MX6Q_PAD_SD4_DAT2__GPIO_2_10 = IOMUX_PAD(0x070C, 0x0324, 5, 0x0000, 0, 0), -- MX6Q_PAD_SD4_DAT2__IPU1_IPU_DIAG_BUS_10 = IOMUX_PAD(0x070C, 0x0324, 6, 0x0000, 0, 0), -- MX6Q_PAD_SD4_DAT2__IPU2_IPU_DIAG_BUS_10 = IOMUX_PAD(0x070C, 0x0324, 7, 0x0000, 0, 0), -- MX6Q_PAD_SD4_DAT3__RAWNAND_D11 = IOMUX_PAD(0x0710, 0x0328, 0, 0x0000, 0, 0), -- MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 = IOMUX_PAD(0x0710, 0x0328, 1, 0x0000, 0, 0), -- MX6Q_PAD_SD4_DAT3__USBOH3_UH2_DFD_OUT27 = IOMUX_PAD(0x0710, 0x0328, 3, 0x0000, 0, 0), -- MX6Q_PAD_SD4_DAT3__USBOH3_UH3_DFD_OUT27 = IOMUX_PAD(0x0710, 0x0328, 4, 0x0000, 0, 0), -- MX6Q_PAD_SD4_DAT3__GPIO_2_11 = IOMUX_PAD(0x0710, 0x0328, 5, 0x0000, 0, 0), -- MX6Q_PAD_SD4_DAT3__IPU1_IPU_DIAG_BUS_11 = IOMUX_PAD(0x0710, 0x0328, 6, 0x0000, 0, 0), -- MX6Q_PAD_SD4_DAT3__IPU2_IPU_DIAG_BUS_11 = IOMUX_PAD(0x0710, 0x0328, 7, 0x0000, 0, 0), -- MX6Q_PAD_SD4_DAT4__RAWNAND_D12 = IOMUX_PAD(0x0714, 0x032C, 0, 0x0000, 0, 0), -- MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 = IOMUX_PAD(0x0714, 0x032C, 1, 0x0000, 0, 0), -- MX6Q_PAD_SD4_DAT4__UART2_RXD = IOMUX_PAD(0x0714, 0x032C, 2, 0x0928, 6, 0), -- MX6Q_PAD_SD4_DAT4__USBOH3_UH2_DFD_OUT28 = IOMUX_PAD(0x0714, 0x032C, 3, 0x0000, 0, 0), -- MX6Q_PAD_SD4_DAT4__USBOH3_UH3_DFD_OUT28 = IOMUX_PAD(0x0714, 0x032C, 4, 0x0000, 0, 0), -- MX6Q_PAD_SD4_DAT4__GPIO_2_12 = IOMUX_PAD(0x0714, 0x032C, 5, 0x0000, 0, 0), -- MX6Q_PAD_SD4_DAT4__IPU1_IPU_DIAG_BUS_12 = IOMUX_PAD(0x0714, 0x032C, 6, 0x0000, 0, 0), -- MX6Q_PAD_SD4_DAT4__IPU2_IPU_DIAG_BUS_12 = IOMUX_PAD(0x0714, 0x032C, 7, 0x0000, 0, 0), -- MX6Q_PAD_SD4_DAT5__RAWNAND_D13 = IOMUX_PAD(0x0718, 0x0330, 0, 0x0000, 0, 0), -- MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 = IOMUX_PAD(0x0718, 0x0330, 1, 0x0000, 0, 0), -- MX6Q_PAD_SD4_DAT5__UART2_CTS = IOMUX_PAD(0x0718, 0x0330, 2, 0x0000, 0, 0), -- MX6Q_PAD_SD4_DAT5__UART2_RTS = IOMUX_PAD(0x0718, 0x0330, 2, 0x0924, 4, 0), -- MX6Q_PAD_SD4_DAT5__USBOH3_UH2_DFD_OUT29 = IOMUX_PAD(0x0718, 0x0330, 3, 0x0000, 0, 0), -- MX6Q_PAD_SD4_DAT5__USBOH3_UH3_DFD_OUT29 = IOMUX_PAD(0x0718, 0x0330, 4, 0x0000, 0, 0), -- MX6Q_PAD_SD4_DAT5__GPIO_2_13 = IOMUX_PAD(0x0718, 0x0330, 5, 0x0000, 0, 0), -- MX6Q_PAD_SD4_DAT5__IPU1_IPU_DIAG_BUS_13 = IOMUX_PAD(0x0718, 0x0330, 6, 0x0000, 0, 0), -- MX6Q_PAD_SD4_DAT5__IPU2_IPU_DIAG_BUS_13 = IOMUX_PAD(0x0718, 0x0330, 7, 0x0000, 0, 0), -- MX6Q_PAD_SD4_DAT6__RAWNAND_D14 = IOMUX_PAD(0x071C, 0x0334, 0, 0x0000, 0, 0), -- MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 = IOMUX_PAD(0x071C, 0x0334, 1, 0x0000, 0, 0), -- MX6Q_PAD_SD4_DAT6__UART2_CTS = IOMUX_PAD(0x071C, 0x0334, 2, 0x0924, 5, 0), -- MX6Q_PAD_SD4_DAT6__USBOH3_UH2_DFD_OUT30 = IOMUX_PAD(0x071C, 0x0334, 3, 0x0000, 0, 0), -- MX6Q_PAD_SD4_DAT6__USBOH3_UH3_DFD_OUT30 = IOMUX_PAD(0x071C, 0x0334, 4, 0x0000, 0, 0), -- MX6Q_PAD_SD4_DAT6__GPIO_2_14 = IOMUX_PAD(0x071C, 0x0334, 5, 0x0000, 0, 0), -- MX6Q_PAD_SD4_DAT6__IPU1_IPU_DIAG_BUS_14 = IOMUX_PAD(0x071C, 0x0334, 6, 0x0000, 0, 0), -- MX6Q_PAD_SD4_DAT6__IPU2_IPU_DIAG_BUS_14 = IOMUX_PAD(0x071C, 0x0334, 7, 0x0000, 0, 0), -- MX6Q_PAD_SD4_DAT7__RAWNAND_D15 = IOMUX_PAD(0x0720, 0x0338, 0, 0x0000, 0, 0), -- MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 = IOMUX_PAD(0x0720, 0x0338, 1, 0x0000, 0, 0), -- MX6Q_PAD_SD4_DAT7__UART2_TXD = IOMUX_PAD(0x0720, 0x0338, 2, 0x0000, 0, 0), -- MX6Q_PAD_SD4_DAT7__UART2_TXD_RXD = IOMUX_PAD(0x0720, 0x0338, 2, 0x0928, 7, 0), -- MX6Q_PAD_SD4_DAT7__USBOH3_UH2_DFD_OUT31 = IOMUX_PAD(0x0720, 0x0338, 3, 0x0000, 0, 0), -- MX6Q_PAD_SD4_DAT7__USBOH3_UH3_DFD_OUT31 = IOMUX_PAD(0x0720, 0x0338, 4, 0x0000, 0, 0), -- MX6Q_PAD_SD4_DAT7__GPIO_2_15 = IOMUX_PAD(0x0720, 0x0338, 5, 0x0000, 0, 0), -- MX6Q_PAD_SD4_DAT7__IPU1_IPU_DIAG_BUS_15 = IOMUX_PAD(0x0720, 0x0338, 6, 0x0000, 0, 0), -- MX6Q_PAD_SD4_DAT7__IPU2_IPU_DIAG_BUS_15 = IOMUX_PAD(0x0720, 0x0338, 7, 0x0000, 0, 0), -- MX6Q_PAD_SD1_DAT1__USDHC1_DAT1 = IOMUX_PAD(0x0724, 0x033C, 0, 0x0000, 0, 0), -- MX6Q_PAD_SD1_DAT1__ECSPI5_SS0 = IOMUX_PAD(0x0724, 0x033C, 1, 0x0834, 1, 0), -- MX6Q_PAD_SD1_DAT1__PWM3_PWMO = IOMUX_PAD(0x0724, 0x033C, 2, 0x0000, 0, 0), -- MX6Q_PAD_SD1_DAT1__GPT_CAPIN2 = IOMUX_PAD(0x0724, 0x033C, 3, 0x0000, 0, 0), -- MX6Q_PAD_SD1_DAT1__PCIE_CTRL_MUX_7 = IOMUX_PAD(0x0724, 0x033C, 4, 0x0000, 0, 0), -- MX6Q_PAD_SD1_DAT1__GPIO_1_17 = IOMUX_PAD(0x0724, 0x033C, 5, 0x0000, 0, 0), -- MX6Q_PAD_SD1_DAT1__HDMI_TX_OPHYDTB_0 = IOMUX_PAD(0x0724, 0x033C, 6, 0x0000, 0, 0), -- MX6Q_PAD_SD1_DAT1__ANATOP_TESTO_8 = IOMUX_PAD(0x0724, 0x033C, 7, 0x0000, 0, 0), -- MX6Q_PAD_SD1_DAT0__USDHC1_DAT0 = IOMUX_PAD(0x0728, 0x0340, 0, 0x0000, 0, 0), -- MX6Q_PAD_SD1_DAT0__ECSPI5_MISO = IOMUX_PAD(0x0728, 0x0340, 1, 0x082C, 1, 0), -- MX6Q_PAD_SD1_DAT0__CAAM_WRAP_RNG_OSCOBS = IOMUX_PAD(0x0728, 0x0340, 2, 0x0000, 0, 0), -- MX6Q_PAD_SD1_DAT0__GPT_CAPIN1 = IOMUX_PAD(0x0728, 0x0340, 3, 0x0000, 0, 0), -- MX6Q_PAD_SD1_DAT0__PCIE_CTRL_MUX_8 = IOMUX_PAD(0x0728, 0x0340, 4, 0x0000, 0, 0), -- MX6Q_PAD_SD1_DAT0__GPIO_1_16 = IOMUX_PAD(0x0728, 0x0340, 5, 0x0000, 0, 0), -- MX6Q_PAD_SD1_DAT0__HDMI_TX_OPHYDTB_1 = IOMUX_PAD(0x0728, 0x0340, 6, 0x0000, 0, 0), -- MX6Q_PAD_SD1_DAT0__ANATOP_TESTO_7 = IOMUX_PAD(0x0728, 0x0340, 7, 0x0000, 0, 0), -- MX6Q_PAD_SD1_DAT3__USDHC1_DAT3 = IOMUX_PAD(0x072C, 0x0344, 0, 0x0000, 0, 0), -- MX6Q_PAD_SD1_DAT3__ECSPI5_SS2 = IOMUX_PAD(0x072C, 0x0344, 1, 0x0000, 0, 0), -- MX6Q_PAD_SD1_DAT3__GPT_CMPOUT3 = IOMUX_PAD(0x072C, 0x0344, 2, 0x0000, 0, 0), -- MX6Q_PAD_SD1_DAT3__PWM1_PWMO = IOMUX_PAD(0x072C, 0x0344, 3, 0x0000, 0, 0), -- MX6Q_PAD_SD1_DAT3__WDOG2_WDOG_B = IOMUX_PAD(0x072C, 0x0344, 4, 0x0000, 0, 0), -- MX6Q_PAD_SD1_DAT3__GPIO_1_21 = IOMUX_PAD(0x072C, 0x0344, 5, 0x0000, 0, 0), -- MX6Q_PAD_SD1_DAT3__WDOG2_WDOG_RST_B_DEB = IOMUX_PAD(0x072C, 0x0344, 6, 0x0000, 0, 0), -- MX6Q_PAD_SD1_DAT3__ANATOP_TESTO_6 = IOMUX_PAD(0x072C, 0x0344, 7, 0x0000, 0, 0), -- MX6Q_PAD_SD1_CMD__USDHC1_CMD = IOMUX_PAD(0x0730, 0x0348, 16, 0x0000, 0, 0), -- MX6Q_PAD_SD1_CMD__ECSPI5_MOSI = IOMUX_PAD(0x0730, 0x0348, 1, 0x0830, 0, 0), -- MX6Q_PAD_SD1_CMD__PWM4_PWMO = IOMUX_PAD(0x0730, 0x0348, 2, 0x0000, 0, 0), -- MX6Q_PAD_SD1_CMD__GPT_CMPOUT1 = IOMUX_PAD(0x0730, 0x0348, 3, 0x0000, 0, 0), -- MX6Q_PAD_SD1_CMD__GPIO_1_18 = IOMUX_PAD(0x0730, 0x0348, 5, 0x0000, 0, 0), -- MX6Q_PAD_SD1_CMD__ANATOP_TESTO_5 = IOMUX_PAD(0x0730, 0x0348, 7, 0x0000, 0, 0), -- MX6Q_PAD_SD1_DAT2__USDHC1_DAT2 = IOMUX_PAD(0x0734, 0x034C, 0, 0x0000, 0, 0), -- MX6Q_PAD_SD1_DAT2__ECSPI5_SS1 = IOMUX_PAD(0x0734, 0x034C, 1, 0x0838, 1, 0), -- MX6Q_PAD_SD1_DAT2__GPT_CMPOUT2 = IOMUX_PAD(0x0734, 0x034C, 2, 0x0000, 0, 0), -- MX6Q_PAD_SD1_DAT2__PWM2_PWMO = IOMUX_PAD(0x0734, 0x034C, 3, 0x0000, 0, 0), -- MX6Q_PAD_SD1_DAT2__WDOG1_WDOG_B = IOMUX_PAD(0x0734, 0x034C, 4, 0x0000, 0, 0), -- MX6Q_PAD_SD1_DAT2__GPIO_1_19 = IOMUX_PAD(0x0734, 0x034C, 5, 0x0000, 0, 0), -- MX6Q_PAD_SD1_DAT2__WDOG1_WDOG_RST_B_DEB = IOMUX_PAD(0x0734, 0x034C, 6, 0x0000, 0, 0), -- MX6Q_PAD_SD1_DAT2__ANATOP_TESTO_4 = IOMUX_PAD(0x0734, 0x034C, 7, 0x0000, 0, 0), -- MX6Q_PAD_SD1_CLK__USDHC1_CLK = IOMUX_PAD(0x0738, 0x0350, 0, 0x0000, 0, 0), -- MX6Q_PAD_SD1_CLK__ECSPI5_SCLK = IOMUX_PAD(0x0738, 0x0350, 1, 0x0828, 0, 0), -- MX6Q_PAD_SD1_CLK__OSC32K_32K_OUT = IOMUX_PAD(0x0738, 0x0350, 2, 0x0000, 0, 0), -- MX6Q_PAD_SD1_CLK__GPT_CLKIN = IOMUX_PAD(0x0738, 0x0350, 3, 0x0000, 0, 0), -- MX6Q_PAD_SD1_CLK__GPIO_1_20 = IOMUX_PAD(0x0738, 0x0350, 5, 0x0000, 0, 0), -- MX6Q_PAD_SD1_CLK__PHY_DTB_0 = IOMUX_PAD(0x0738, 0x0350, 6, 0x0000, 0, 0), -- MX6Q_PAD_SD1_CLK__SATA_PHY_DTB_0 = IOMUX_PAD(0x0738, 0x0350, 7, 0x0000, 0, 0), -- MX6Q_PAD_SD2_CLK__USDHC2_CLK = IOMUX_PAD(0x073C, 0x0354, 0, 0x0000, 0, 0), -- MX6Q_PAD_SD2_CLK__ECSPI5_SCLK = IOMUX_PAD(0x073C, 0x0354, 1, 0x0828, 1, 0), -- MX6Q_PAD_SD2_CLK__KPP_COL_5 = IOMUX_PAD(0x073C, 0x0354, 2, 0x08E8, 3, 0), -- MX6Q_PAD_SD2_CLK__AUDMUX_AUD4_RXFS = IOMUX_PAD(0x073C, 0x0354, 3, 0x07C0, 1, 0), -- MX6Q_PAD_SD2_CLK__PCIE_CTRL_MUX_9 = IOMUX_PAD(0x073C, 0x0354, 4, 0x0000, 0, 0), -- MX6Q_PAD_SD2_CLK__GPIO_1_10 = IOMUX_PAD(0x073C, 0x0354, 5, 0x0000, 0, 0), -- MX6Q_PAD_SD2_CLK__PHY_DTB_1 = IOMUX_PAD(0x073C, 0x0354, 6, 0x0000, 0, 0), -- MX6Q_PAD_SD2_CLK__SATA_PHY_DTB_1 = IOMUX_PAD(0x073C, 0x0354, 7, 0x0000, 0, 0), -- MX6Q_PAD_SD2_CMD__USDHC2_CMD = IOMUX_PAD(0x0740, 0x0358, 16, 0x0000, 0, 0), -- MX6Q_PAD_SD2_CMD__ECSPI5_MOSI = IOMUX_PAD(0x0740, 0x0358, 1, 0x0830, 1, 0), -- MX6Q_PAD_SD2_CMD__KPP_ROW_5 = IOMUX_PAD(0x0740, 0x0358, 2, 0x08F4, 2, 0), -- MX6Q_PAD_SD2_CMD__AUDMUX_AUD4_RXC = IOMUX_PAD(0x0740, 0x0358, 3, 0x07BC, 1, 0), -- MX6Q_PAD_SD2_CMD__PCIE_CTRL_MUX_10 = IOMUX_PAD(0x0740, 0x0358, 4, 0x0000, 0, 0), -- MX6Q_PAD_SD2_CMD__GPIO_1_11 = IOMUX_PAD(0x0740, 0x0358, 5, 0x0000, 0, 0), -- MX6Q_PAD_SD2_DAT3__USDHC2_DAT3 = IOMUX_PAD(0x0744, 0x035C, 0, 0x0000, 0, 0), -- MX6Q_PAD_SD2_DAT3__ECSPI5_SS3 = IOMUX_PAD(0x0744, 0x035C, 1, 0x0000, 0, 0), -- MX6Q_PAD_SD2_DAT3__KPP_COL_6 = IOMUX_PAD(0x0744, 0x035C, 2, 0x08EC, 2, 0), -- MX6Q_PAD_SD2_DAT3__AUDMUX_AUD4_TXC = IOMUX_PAD(0x0744, 0x035C, 3, 0x07C4, 1, 0), -- MX6Q_PAD_SD2_DAT3__PCIE_CTRL_MUX_11 = IOMUX_PAD(0x0744, 0x035C, 4, 0x0000, 0, 0), -- MX6Q_PAD_SD2_DAT3__GPIO_1_12 = IOMUX_PAD(0x0744, 0x035C, 5, 0x0000, 0, 0), -- MX6Q_PAD_SD2_DAT3__SJC_DONE = IOMUX_PAD(0x0744, 0x035C, 6, 0x0000, 0, 0), -- MX6Q_PAD_SD2_DAT3__ANATOP_TESTO_3 = IOMUX_PAD(0x0744, 0x035C, 7, 0x0000, 0, 0), --}; -- --#endif /* __ASM_ARCH_MX6_MX6X_PINS_H__ */ diff --cc arch/arm/include/asm/arch-mx6/regs-apbh.h index 0000000000,0000000000..76cb0f0e22 new file mode 100644 --- /dev/null +++ b/arch/arm/include/asm/arch-mx6/regs-apbh.h @@@ -1,0 -1,0 +1,469 @@@ ++/* ++ * Freescale i.MX6Q APBH Register Definitions ++ * ++ * Copyright (C) 2012 Lothar Waßmann ++ * based on: arch/arm/include/arch-mx28/apbh-regs.h by Marek Vasut ++ * on behalf of DENX Software Engineering GmbH ++ * ++ * Based on code from LTIB: ++ * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ * ++ */ ++ ++#ifndef __REGS_APBH_H__ ++#define __REGS_APBH_H__ ++ ++#include ++ ++#define MXS_APBH_BASE 0x00110000 ++ ++#ifndef __ASSEMBLY__ ++struct apbh_regs { ++ mx6_reg_32(hw_apbh_ctrl0); /* 0x000 */ ++ mx6_reg_32(hw_apbh_ctrl1); /* 0x010 */ ++ mx6_reg_32(hw_apbh_ctrl2); /* 0x020 */ ++ mx6_reg_32(hw_apbh_channel_ctrl); /* 0x030 */ ++ reg_32(hw_apbh_devsel); /* 0x040 */ ++ reg_32(hw_apbh_dma_burst_size); /* 0x050 */ ++ reg_32(hw_apbh_debug); /* 0x060 */ ++ ++ reg_32(reserved[9]); /* 0x064-0x0fc */ ++ ++ union { ++ struct { ++ reg_32(hw_apbh_ch_curcmdar); ++ reg_32(hw_apbh_ch_nxtcmdar); ++ reg_32(hw_apbh_ch_cmd); ++ reg_32(hw_apbh_ch_bar); ++ reg_32(hw_apbh_ch_sema); ++ reg_32(hw_apbh_ch_debug1); ++ reg_32(hw_apbh_ch_debug2); ++ } ch[16]; ++ struct { ++ reg_32(hw_apbh_ch0_curcmdar); /* 0x100 */ ++ reg_32(hw_apbh_ch0_nxtcmdar); /* 0x110 */ ++ reg_32(hw_apbh_ch0_cmd); /* 0x120 */ ++ reg_32(hw_apbh_ch0_bar); /* 0x130 */ ++ reg_32(hw_apbh_ch0_sema); /* 0x140 */ ++ reg_32(hw_apbh_ch0_debug1); /* 0x150 */ ++ reg_32(hw_apbh_ch0_debug2); /* 0x160 */ ++ reg_32(hw_apbh_ch1_curcmdar); /* 0x170 */ ++ reg_32(hw_apbh_ch1_nxtcmdar); /* 0x180 */ ++ reg_32(hw_apbh_ch1_cmd); /* 0x190 */ ++ reg_32(hw_apbh_ch1_bar); /* 0x1a0 */ ++ reg_32(hw_apbh_ch1_sema); /* 0x1b0 */ ++ reg_32(hw_apbh_ch1_debug1); /* 0x1c0 */ ++ reg_32(hw_apbh_ch1_debug2); /* 0x1d0 */ ++ reg_32(hw_apbh_ch2_curcmdar); /* 0x1e0 */ ++ reg_32(hw_apbh_ch2_nxtcmdar); /* 0x1f0 */ ++ reg_32(hw_apbh_ch2_cmd); /* 0x200 */ ++ reg_32(hw_apbh_ch2_bar); /* 0x210 */ ++ reg_32(hw_apbh_ch2_sema); /* 0x220 */ ++ reg_32(hw_apbh_ch2_debug1); /* 0x230 */ ++ reg_32(hw_apbh_ch2_debug2); /* 0x240 */ ++ reg_32(hw_apbh_ch3_curcmdar); /* 0x250 */ ++ reg_32(hw_apbh_ch3_nxtcmdar); /* 0x260 */ ++ reg_32(hw_apbh_ch3_cmd); /* 0x270 */ ++ reg_32(hw_apbh_ch3_bar); /* 0x280 */ ++ reg_32(hw_apbh_ch3_sema); /* 0x290 */ ++ reg_32(hw_apbh_ch3_debug1); /* 0x2a0 */ ++ reg_32(hw_apbh_ch3_debug2); /* 0x2b0 */ ++ reg_32(hw_apbh_ch4_curcmdar); /* 0x2c0 */ ++ reg_32(hw_apbh_ch4_nxtcmdar); /* 0x2d0 */ ++ reg_32(hw_apbh_ch4_cmd); /* 0x2e0 */ ++ reg_32(hw_apbh_ch4_bar); /* 0x2f0 */ ++ reg_32(hw_apbh_ch4_sema); /* 0x300 */ ++ reg_32(hw_apbh_ch4_debug1); /* 0x310 */ ++ reg_32(hw_apbh_ch4_debug2); /* 0x320 */ ++ reg_32(hw_apbh_ch5_curcmdar); /* 0x330 */ ++ reg_32(hw_apbh_ch5_nxtcmdar); /* 0x340 */ ++ reg_32(hw_apbh_ch5_cmd); /* 0x350 */ ++ reg_32(hw_apbh_ch5_bar); /* 0x360 */ ++ reg_32(hw_apbh_ch5_sema); /* 0x370 */ ++ reg_32(hw_apbh_ch5_debug1); /* 0x380 */ ++ reg_32(hw_apbh_ch5_debug2); /* 0x390 */ ++ reg_32(hw_apbh_ch6_curcmdar); /* 0x3a0 */ ++ reg_32(hw_apbh_ch6_nxtcmdar); /* 0x3b0 */ ++ reg_32(hw_apbh_ch6_cmd); /* 0x3c0 */ ++ reg_32(hw_apbh_ch6_bar); /* 0x3d0 */ ++ reg_32(hw_apbh_ch6_sema); /* 0x3e0 */ ++ reg_32(hw_apbh_ch6_debug1); /* 0x3f0 */ ++ reg_32(hw_apbh_ch6_debug2); /* 0x400 */ ++ reg_32(hw_apbh_ch7_curcmdar); /* 0x410 */ ++ reg_32(hw_apbh_ch7_nxtcmdar); /* 0x420 */ ++ reg_32(hw_apbh_ch7_cmd); /* 0x430 */ ++ reg_32(hw_apbh_ch7_bar); /* 0x440 */ ++ reg_32(hw_apbh_ch7_sema); /* 0x450 */ ++ reg_32(hw_apbh_ch7_debug1); /* 0x460 */ ++ reg_32(hw_apbh_ch7_debug2); /* 0x470 */ ++ reg_32(hw_apbh_ch8_curcmdar); /* 0x480 */ ++ reg_32(hw_apbh_ch8_nxtcmdar); /* 0x490 */ ++ reg_32(hw_apbh_ch8_cmd); /* 0x4a0 */ ++ reg_32(hw_apbh_ch8_bar); /* 0x4b0 */ ++ reg_32(hw_apbh_ch8_sema); /* 0x4c0 */ ++ reg_32(hw_apbh_ch8_debug1); /* 0x4d0 */ ++ reg_32(hw_apbh_ch8_debug2); /* 0x4e0 */ ++ reg_32(hw_apbh_ch9_curcmdar); /* 0x4f0 */ ++ reg_32(hw_apbh_ch9_nxtcmdar); /* 0x500 */ ++ reg_32(hw_apbh_ch9_cmd); /* 0x510 */ ++ reg_32(hw_apbh_ch9_bar); /* 0x520 */ ++ reg_32(hw_apbh_ch9_sema); /* 0x530 */ ++ reg_32(hw_apbh_ch9_debug1); /* 0x540 */ ++ reg_32(hw_apbh_ch9_debug2); /* 0x550 */ ++ reg_32(hw_apbh_ch10_curcmdar); /* 0x560 */ ++ reg_32(hw_apbh_ch10_nxtcmdar); /* 0x570 */ ++ reg_32(hw_apbh_ch10_cmd); /* 0x580 */ ++ reg_32(hw_apbh_ch10_bar); /* 0x590 */ ++ reg_32(hw_apbh_ch10_sema); /* 0x5a0 */ ++ reg_32(hw_apbh_ch10_debug1); /* 0x5b0 */ ++ reg_32(hw_apbh_ch10_debug2); /* 0x5c0 */ ++ reg_32(hw_apbh_ch11_curcmdar); /* 0x5d0 */ ++ reg_32(hw_apbh_ch11_nxtcmdar); /* 0x5e0 */ ++ reg_32(hw_apbh_ch11_cmd); /* 0x5f0 */ ++ reg_32(hw_apbh_ch11_bar); /* 0x600 */ ++ reg_32(hw_apbh_ch11_sema); /* 0x610 */ ++ reg_32(hw_apbh_ch11_debug1); /* 0x620 */ ++ reg_32(hw_apbh_ch11_debug2); /* 0x630 */ ++ reg_32(hw_apbh_ch12_curcmdar); /* 0x640 */ ++ reg_32(hw_apbh_ch12_nxtcmdar); /* 0x650 */ ++ reg_32(hw_apbh_ch12_cmd); /* 0x660 */ ++ reg_32(hw_apbh_ch12_bar); /* 0x670 */ ++ reg_32(hw_apbh_ch12_sema); /* 0x680 */ ++ reg_32(hw_apbh_ch12_debug1); /* 0x690 */ ++ reg_32(hw_apbh_ch12_debug2); /* 0x6a0 */ ++ reg_32(hw_apbh_ch13_curcmdar); /* 0x6b0 */ ++ reg_32(hw_apbh_ch13_nxtcmdar); /* 0x6c0 */ ++ reg_32(hw_apbh_ch13_cmd); /* 0x6d0 */ ++ reg_32(hw_apbh_ch13_bar); /* 0x6e0 */ ++ reg_32(hw_apbh_ch13_sema); /* 0x6f0 */ ++ reg_32(hw_apbh_ch13_debug1); /* 0x700 */ ++ reg_32(hw_apbh_ch13_debug2); /* 0x710 */ ++ reg_32(hw_apbh_ch14_curcmdar); /* 0x720 */ ++ reg_32(hw_apbh_ch14_nxtcmdar); /* 0x730 */ ++ reg_32(hw_apbh_ch14_cmd); /* 0x740 */ ++ reg_32(hw_apbh_ch14_bar); /* 0x750 */ ++ reg_32(hw_apbh_ch14_sema); /* 0x760 */ ++ reg_32(hw_apbh_ch14_debug1); /* 0x770 */ ++ reg_32(hw_apbh_ch14_debug2); /* 0x780 */ ++ reg_32(hw_apbh_ch15_curcmdar); /* 0x790 */ ++ reg_32(hw_apbh_ch15_nxtcmdar); /* 0x7a0 */ ++ reg_32(hw_apbh_ch15_cmd); /* 0x7b0 */ ++ reg_32(hw_apbh_ch15_bar); /* 0x7c0 */ ++ reg_32(hw_apbh_ch15_sema); /* 0x7d0 */ ++ reg_32(hw_apbh_ch15_debug1); /* 0x7e0 */ ++ reg_32(hw_apbh_ch15_debug2); /* 0x7f0 */ ++ }; ++ }; ++ mx6_reg_32(hw_apbh_version); /* 0x800 */ ++}; ++#endif ++ ++#define APBH_CTRL0_SFTRST (1 << 31) ++#define APBH_CTRL0_CLKGATE (1 << 30) ++#define APBH_CTRL0_AHB_BURST8_EN (1 << 29) ++#define APBH_CTRL0_APB_BURST_EN (1 << 28) ++#define APBH_CTRL0_RSVD0_MASK (0xfff << 16) ++#define APBH_CTRL0_RSVD0_OFFSET 16 ++#define APBH_CTRL0_CLKGATE_CHANNEL_MASK 0xffff ++#define APBH_CTRL0_CLKGATE_CHANNEL_OFFSET 0 ++#define APBH_CTRL0_CLKGATE_CHANNEL_SSP0 0x0001 ++#define APBH_CTRL0_CLKGATE_CHANNEL_SSP1 0x0002 ++#define APBH_CTRL0_CLKGATE_CHANNEL_SSP2 0x0004 ++#define APBH_CTRL0_CLKGATE_CHANNEL_SSP3 0x0008 ++#define APBH_CTRL0_CLKGATE_CHANNEL_NAND0 0x0010 ++#define APBH_CTRL0_CLKGATE_CHANNEL_NAND1 0x0020 ++#define APBH_CTRL0_CLKGATE_CHANNEL_NAND2 0x0040 ++#define APBH_CTRL0_CLKGATE_CHANNEL_NAND3 0x0080 ++#define APBH_CTRL0_CLKGATE_CHANNEL_NAND4 0x0100 ++#define APBH_CTRL0_CLKGATE_CHANNEL_NAND5 0x0200 ++#define APBH_CTRL0_CLKGATE_CHANNEL_NAND6 0x0400 ++#define APBH_CTRL0_CLKGATE_CHANNEL_NAND7 0x0800 ++#define APBH_CTRL0_CLKGATE_CHANNEL_HSADC 0x1000 ++#define APBH_CTRL0_CLKGATE_CHANNEL_LCDIF 0x2000 ++ ++#define APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN (1 << 31) ++#define APBH_CTRL1_CH14_CMDCMPLT_IRQ_EN (1 << 30) ++#define APBH_CTRL1_CH13_CMDCMPLT_IRQ_EN (1 << 29) ++#define APBH_CTRL1_CH12_CMDCMPLT_IRQ_EN (1 << 28) ++#define APBH_CTRL1_CH11_CMDCMPLT_IRQ_EN (1 << 27) ++#define APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN (1 << 26) ++#define APBH_CTRL1_CH9_CMDCMPLT_IRQ_EN (1 << 25) ++#define APBH_CTRL1_CH8_CMDCMPLT_IRQ_EN (1 << 24) ++#define APBH_CTRL1_CH7_CMDCMPLT_IRQ_EN (1 << 23) ++#define APBH_CTRL1_CH6_CMDCMPLT_IRQ_EN (1 << 22) ++#define APBH_CTRL1_CH5_CMDCMPLT_IRQ_EN (1 << 21) ++#define APBH_CTRL1_CH4_CMDCMPLT_IRQ_EN (1 << 20) ++#define APBH_CTRL1_CH3_CMDCMPLT_IRQ_EN (1 << 19) ++#define APBH_CTRL1_CH2_CMDCMPLT_IRQ_EN (1 << 18) ++#define APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN (1 << 17) ++#define APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN (1 << 16) ++#define APBH_CTRL1_CH_CMDCMPLT_IRQ_EN_OFFSET 16 ++#define APBH_CTRL1_CH_CMDCMPLT_IRQ_EN_MASK (0xffff << 16) ++#define APBH_CTRL1_CH15_CMDCMPLT_IRQ (1 << 15) ++#define APBH_CTRL1_CH14_CMDCMPLT_IRQ (1 << 14) ++#define APBH_CTRL1_CH13_CMDCMPLT_IRQ (1 << 13) ++#define APBH_CTRL1_CH12_CMDCMPLT_IRQ (1 << 12) ++#define APBH_CTRL1_CH11_CMDCMPLT_IRQ (1 << 11) ++#define APBH_CTRL1_CH10_CMDCMPLT_IRQ (1 << 10) ++#define APBH_CTRL1_CH9_CMDCMPLT_IRQ (1 << 9) ++#define APBH_CTRL1_CH8_CMDCMPLT_IRQ (1 << 8) ++#define APBH_CTRL1_CH7_CMDCMPLT_IRQ (1 << 7) ++#define APBH_CTRL1_CH6_CMDCMPLT_IRQ (1 << 6) ++#define APBH_CTRL1_CH5_CMDCMPLT_IRQ (1 << 5) ++#define APBH_CTRL1_CH4_CMDCMPLT_IRQ (1 << 4) ++#define APBH_CTRL1_CH3_CMDCMPLT_IRQ (1 << 3) ++#define APBH_CTRL1_CH2_CMDCMPLT_IRQ (1 << 2) ++#define APBH_CTRL1_CH1_CMDCMPLT_IRQ (1 << 1) ++#define APBH_CTRL1_CH0_CMDCMPLT_IRQ (1 << 0) ++ ++#define APBH_CTRL2_CH15_ERROR_STATUS (1 << 31) ++#define APBH_CTRL2_CH14_ERROR_STATUS (1 << 30) ++#define APBH_CTRL2_CH13_ERROR_STATUS (1 << 29) ++#define APBH_CTRL2_CH12_ERROR_STATUS (1 << 28) ++#define APBH_CTRL2_CH11_ERROR_STATUS (1 << 27) ++#define APBH_CTRL2_CH10_ERROR_STATUS (1 << 26) ++#define APBH_CTRL2_CH9_ERROR_STATUS (1 << 25) ++#define APBH_CTRL2_CH8_ERROR_STATUS (1 << 24) ++#define APBH_CTRL2_CH7_ERROR_STATUS (1 << 23) ++#define APBH_CTRL2_CH6_ERROR_STATUS (1 << 22) ++#define APBH_CTRL2_CH5_ERROR_STATUS (1 << 21) ++#define APBH_CTRL2_CH4_ERROR_STATUS (1 << 20) ++#define APBH_CTRL2_CH3_ERROR_STATUS (1 << 19) ++#define APBH_CTRL2_CH2_ERROR_STATUS (1 << 18) ++#define APBH_CTRL2_CH1_ERROR_STATUS (1 << 17) ++#define APBH_CTRL2_CH0_ERROR_STATUS (1 << 16) ++#define APBH_CTRL2_CH15_ERROR_IRQ (1 << 15) ++#define APBH_CTRL2_CH14_ERROR_IRQ (1 << 14) ++#define APBH_CTRL2_CH13_ERROR_IRQ (1 << 13) ++#define APBH_CTRL2_CH12_ERROR_IRQ (1 << 12) ++#define APBH_CTRL2_CH11_ERROR_IRQ (1 << 11) ++#define APBH_CTRL2_CH10_ERROR_IRQ (1 << 10) ++#define APBH_CTRL2_CH9_ERROR_IRQ (1 << 9) ++#define APBH_CTRL2_CH8_ERROR_IRQ (1 << 8) ++#define APBH_CTRL2_CH7_ERROR_IRQ (1 << 7) ++#define APBH_CTRL2_CH6_ERROR_IRQ (1 << 6) ++#define APBH_CTRL2_CH5_ERROR_IRQ (1 << 5) ++#define APBH_CTRL2_CH4_ERROR_IRQ (1 << 4) ++#define APBH_CTRL2_CH3_ERROR_IRQ (1 << 3) ++#define APBH_CTRL2_CH2_ERROR_IRQ (1 << 2) ++#define APBH_CTRL2_CH1_ERROR_IRQ (1 << 1) ++#define APBH_CTRL2_CH0_ERROR_IRQ (1 << 0) ++ ++#define APBH_CHANNEL_CTRL_RESET_CHANNEL_MASK (0xffff << 16) ++#define APBH_CHANNEL_CTRL_RESET_CHANNEL_OFFSET 16 ++#define APBH_CHANNEL_CTRL_RESET_CHANNEL_SSP0 (0x0001 << 16) ++#define APBH_CHANNEL_CTRL_RESET_CHANNEL_SSP1 (0x0002 << 16) ++#define APBH_CHANNEL_CTRL_RESET_CHANNEL_SSP2 (0x0004 << 16) ++#define APBH_CHANNEL_CTRL_RESET_CHANNEL_SSP3 (0x0008 << 16) ++#define APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND0 (0x0010 << 16) ++#define APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND1 (0x0020 << 16) ++#define APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND2 (0x0040 << 16) ++#define APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND3 (0x0080 << 16) ++#define APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND4 (0x0100 << 16) ++#define APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND5 (0x0200 << 16) ++#define APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND6 (0x0400 << 16) ++#define APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND7 (0x0800 << 16) ++#define APBH_CHANNEL_CTRL_RESET_CHANNEL_HSADC (0x1000 << 16) ++#define APBH_CHANNEL_CTRL_RESET_CHANNEL_LCDIF (0x2000 << 16) ++#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_MASK 0xffff ++#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_OFFSET 0 ++#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_SSP0 0x0001 ++#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_SSP1 0x0002 ++#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_SSP2 0x0004 ++#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_SSP3 0x0008 ++#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND0 0x0010 ++#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND1 0x0020 ++#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND2 0x0040 ++#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND3 0x0080 ++#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND4 0x0100 ++#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND5 0x0200 ++#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND6 0x0400 ++#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND7 0x0800 ++#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_HSADC 0x1000 ++#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_LCDIF 0x2000 ++ ++#define APBH_DEVSEL_CH15_MASK (0x3 << 30) ++#define APBH_DEVSEL_CH15_OFFSET 30 ++#define APBH_DEVSEL_CH14_MASK (0x3 << 28) ++#define APBH_DEVSEL_CH14_OFFSET 28 ++#define APBH_DEVSEL_CH13_MASK (0x3 << 26) ++#define APBH_DEVSEL_CH13_OFFSET 26 ++#define APBH_DEVSEL_CH12_MASK (0x3 << 24) ++#define APBH_DEVSEL_CH12_OFFSET 24 ++#define APBH_DEVSEL_CH11_MASK (0x3 << 22) ++#define APBH_DEVSEL_CH11_OFFSET 22 ++#define APBH_DEVSEL_CH10_MASK (0x3 << 20) ++#define APBH_DEVSEL_CH10_OFFSET 20 ++#define APBH_DEVSEL_CH9_MASK (0x3 << 18) ++#define APBH_DEVSEL_CH9_OFFSET 18 ++#define APBH_DEVSEL_CH8_MASK (0x3 << 16) ++#define APBH_DEVSEL_CH8_OFFSET 16 ++#define APBH_DEVSEL_CH7_MASK (0x3 << 14) ++#define APBH_DEVSEL_CH7_OFFSET 14 ++#define APBH_DEVSEL_CH6_MASK (0x3 << 12) ++#define APBH_DEVSEL_CH6_OFFSET 12 ++#define APBH_DEVSEL_CH5_MASK (0x3 << 10) ++#define APBH_DEVSEL_CH5_OFFSET 10 ++#define APBH_DEVSEL_CH4_MASK (0x3 << 8) ++#define APBH_DEVSEL_CH4_OFFSET 8 ++#define APBH_DEVSEL_CH3_MASK (0x3 << 6) ++#define APBH_DEVSEL_CH3_OFFSET 6 ++#define APBH_DEVSEL_CH2_MASK (0x3 << 4) ++#define APBH_DEVSEL_CH2_OFFSET 4 ++#define APBH_DEVSEL_CH1_MASK (0x3 << 2) ++#define APBH_DEVSEL_CH1_OFFSET 2 ++#define APBH_DEVSEL_CH0_MASK (0x3 << 0) ++#define APBH_DEVSEL_CH0_OFFSET 0 ++ ++#define APBH_DMA_BURST_SIZE_CH15_MASK (0x3 << 30) ++#define APBH_DMA_BURST_SIZE_CH15_OFFSET 30 ++#define APBH_DMA_BURST_SIZE_CH14_MASK (0x3 << 28) ++#define APBH_DMA_BURST_SIZE_CH14_OFFSET 28 ++#define APBH_DMA_BURST_SIZE_CH13_MASK (0x3 << 26) ++#define APBH_DMA_BURST_SIZE_CH13_OFFSET 26 ++#define APBH_DMA_BURST_SIZE_CH12_MASK (0x3 << 24) ++#define APBH_DMA_BURST_SIZE_CH12_OFFSET 24 ++#define APBH_DMA_BURST_SIZE_CH11_MASK (0x3 << 22) ++#define APBH_DMA_BURST_SIZE_CH11_OFFSET 22 ++#define APBH_DMA_BURST_SIZE_CH10_MASK (0x3 << 20) ++#define APBH_DMA_BURST_SIZE_CH10_OFFSET 20 ++#define APBH_DMA_BURST_SIZE_CH9_MASK (0x3 << 18) ++#define APBH_DMA_BURST_SIZE_CH9_OFFSET 18 ++#define APBH_DMA_BURST_SIZE_CH8_MASK (0x3 << 16) ++#define APBH_DMA_BURST_SIZE_CH8_OFFSET 16 ++#define APBH_DMA_BURST_SIZE_CH8_BURST0 (0x0 << 16) ++#define APBH_DMA_BURST_SIZE_CH8_BURST4 (0x1 << 16) ++#define APBH_DMA_BURST_SIZE_CH8_BURST8 (0x2 << 16) ++#define APBH_DMA_BURST_SIZE_CH7_MASK (0x3 << 14) ++#define APBH_DMA_BURST_SIZE_CH7_OFFSET 14 ++#define APBH_DMA_BURST_SIZE_CH6_MASK (0x3 << 12) ++#define APBH_DMA_BURST_SIZE_CH6_OFFSET 12 ++#define APBH_DMA_BURST_SIZE_CH5_MASK (0x3 << 10) ++#define APBH_DMA_BURST_SIZE_CH5_OFFSET 10 ++#define APBH_DMA_BURST_SIZE_CH4_MASK (0x3 << 8) ++#define APBH_DMA_BURST_SIZE_CH4_OFFSET 8 ++#define APBH_DMA_BURST_SIZE_CH3_MASK (0x3 << 6) ++#define APBH_DMA_BURST_SIZE_CH3_OFFSET 6 ++#define APBH_DMA_BURST_SIZE_CH3_BURST0 (0x0 << 6) ++#define APBH_DMA_BURST_SIZE_CH3_BURST4 (0x1 << 6) ++#define APBH_DMA_BURST_SIZE_CH3_BURST8 (0x2 << 6) ++ ++#define APBH_DMA_BURST_SIZE_CH2_MASK (0x3 << 4) ++#define APBH_DMA_BURST_SIZE_CH2_OFFSET 4 ++#define APBH_DMA_BURST_SIZE_CH2_BURST0 (0x0 << 4) ++#define APBH_DMA_BURST_SIZE_CH2_BURST4 (0x1 << 4) ++#define APBH_DMA_BURST_SIZE_CH2_BURST8 (0x2 << 4) ++#define APBH_DMA_BURST_SIZE_CH1_MASK (0x3 << 2) ++#define APBH_DMA_BURST_SIZE_CH1_OFFSET 2 ++#define APBH_DMA_BURST_SIZE_CH1_BURST0 (0x0 << 2) ++#define APBH_DMA_BURST_SIZE_CH1_BURST4 (0x1 << 2) ++#define APBH_DMA_BURST_SIZE_CH1_BURST8 (0x2 << 2) ++ ++#define APBH_DMA_BURST_SIZE_CH0_MASK 0x3 ++#define APBH_DMA_BURST_SIZE_CH0_OFFSET 0 ++#define APBH_DMA_BURST_SIZE_CH0_BURST0 0x0 ++#define APBH_DMA_BURST_SIZE_CH0_BURST4 0x1 ++#define APBH_DMA_BURST_SIZE_CH0_BURST8 0x2 ++ ++#define APBH_DEBUG_GPMI_ONE_FIFO (1 << 0) ++ ++#define APBH_CHn_CURCMDAR_CMD_ADDR_MASK 0xffffffff ++#define APBH_CHn_CURCMDAR_CMD_ADDR_OFFSET 0 ++ ++#define APBH_CHn_NXTCMDAR_CMD_ADDR_MASK 0xffffffff ++#define APBH_CHn_NXTCMDAR_CMD_ADDR_OFFSET 0 ++ ++#define APBH_CHn_CMD_XFER_COUNT_MASK (0xffff << 16) ++#define APBH_CHn_CMD_XFER_COUNT_OFFSET 16 ++#define APBH_CHn_CMD_CMDWORDS_MASK (0xf << 12) ++#define APBH_CHn_CMD_CMDWORDS_OFFSET 12 ++#define APBH_CHn_CMD_HALTONTERMINATE (1 << 8) ++#define APBH_CHn_CMD_WAIT4ENDCMD (1 << 7) ++#define APBH_CHn_CMD_SEMAPHORE (1 << 6) ++#define APBH_CHn_CMD_NANDWAIT4READY (1 << 5) ++#define APBH_CHn_CMD_NANDLOCK (1 << 4) ++#define APBH_CHn_CMD_IRQONCMPLT (1 << 3) ++#define APBH_CHn_CMD_CHAIN (1 << 2) ++#define APBH_CHn_CMD_COMMAND_MASK 0x3 ++#define APBH_CHn_CMD_COMMAND_OFFSET 0 ++#define APBH_CHn_CMD_COMMAND_NO_DMA_XFER 0x0 ++#define APBH_CHn_CMD_COMMAND_DMA_WRITE 0x1 ++#define APBH_CHn_CMD_COMMAND_DMA_READ 0x2 ++#define APBH_CHn_CMD_COMMAND_DMA_SENSE 0x3 ++ ++#define APBH_CHn_BAR_ADDRESS_MASK 0xffffffff ++#define APBH_CHn_BAR_ADDRESS_OFFSET 0 ++ ++#define APBH_CHn_SEMA_RSVD2_MASK (0xff << 24) ++#define APBH_CHn_SEMA_RSVD2_OFFSET 24 ++#define APBH_CHn_SEMA_PHORE_MASK (0xff << 16) ++#define APBH_CHn_SEMA_PHORE_OFFSET 16 ++#define APBH_CHn_SEMA_RSVD1_MASK (0xff << 8) ++#define APBH_CHn_SEMA_RSVD1_OFFSET 8 ++#define APBH_CHn_SEMA_INCREMENT_SEMA_MASK (0xff << 0) ++#define APBH_CHn_SEMA_INCREMENT_SEMA_OFFSET 0 ++ ++#define APBH_CHn_DEBUG1_REQ (1 << 31) ++#define APBH_CHn_DEBUG1_BURST (1 << 30) ++#define APBH_CHn_DEBUG1_KICK (1 << 29) ++#define APBH_CHn_DEBUG1_END (1 << 28) ++#define APBH_CHn_DEBUG1_SENSE (1 << 27) ++#define APBH_CHn_DEBUG1_READY (1 << 26) ++#define APBH_CHn_DEBUG1_LOCK (1 << 25) ++#define APBH_CHn_DEBUG1_NEXTCMDADDRVALID (1 << 24) ++#define APBH_CHn_DEBUG1_RD_FIFO_EMPTY (1 << 23) ++#define APBH_CHn_DEBUG1_RD_FIFO_FULL (1 << 22) ++#define APBH_CHn_DEBUG1_WR_FIFO_EMPTY (1 << 21) ++#define APBH_CHn_DEBUG1_WR_FIFO_FULL (1 << 20) ++#define APBH_CHn_DEBUG1_RSVD1_MASK (0x7fff << 5) ++#define APBH_CHn_DEBUG1_RSVD1_OFFSET 5 ++#define APBH_CHn_DEBUG1_STATEMACHINE_MASK 0x1f ++#define APBH_CHn_DEBUG1_STATEMACHINE_OFFSET 0 ++#define APBH_CHn_DEBUG1_STATEMACHINE_IDLE 0x00 ++#define APBH_CHn_DEBUG1_STATEMACHINE_REQ_CMD1 0x01 ++#define APBH_CHn_DEBUG1_STATEMACHINE_REQ_CMD3 0x02 ++#define APBH_CHn_DEBUG1_STATEMACHINE_REQ_CMD2 0x03 ++#define APBH_CHn_DEBUG1_STATEMACHINE_XFER_DECODE 0x04 ++#define APBH_CHn_DEBUG1_STATEMACHINE_REQ_WAIT 0x05 ++#define APBH_CHn_DEBUG1_STATEMACHINE_REQ_CMD4 0x06 ++#define APBH_CHn_DEBUG1_STATEMACHINE_PIO_REQ 0x07 ++#define APBH_CHn_DEBUG1_STATEMACHINE_READ_FLUSH 0x08 ++#define APBH_CHn_DEBUG1_STATEMACHINE_READ_WAIT 0x09 ++#define APBH_CHn_DEBUG1_STATEMACHINE_WRITE 0x0c ++#define APBH_CHn_DEBUG1_STATEMACHINE_READ_REQ 0x0d ++#define APBH_CHn_DEBUG1_STATEMACHINE_CHECK_CHAIN 0x0e ++#define APBH_CHn_DEBUG1_STATEMACHINE_XFER_COMPLETE 0x0f ++#define APBH_CHn_DEBUG1_STATEMACHINE_TERMINATE 0x14 ++#define APBH_CHn_DEBUG1_STATEMACHINE_WAIT_END 0x15 ++#define APBH_CHn_DEBUG1_STATEMACHINE_WRITE_WAIT 0x1c ++#define APBH_CHn_DEBUG1_STATEMACHINE_HALT_AFTER_TERM 0x1d ++#define APBH_CHn_DEBUG1_STATEMACHINE_CHECK_WAIT 0x1e ++#define APBH_CHn_DEBUG1_STATEMACHINE_WAIT_READY 0x1f ++ ++#define APBH_CHn_DEBUG2_APB_BYTES_MASK (0xffff << 16) ++#define APBH_CHn_DEBUG2_APB_BYTES_OFFSET 16 ++#define APBH_CHn_DEBUG2_AHB_BYTES_MASK 0xffff ++#define APBH_CHn_DEBUG2_AHB_BYTES_OFFSET 0 ++ ++#define APBH_VERSION_MAJOR_MASK (0xff << 24) ++#define APBH_VERSION_MAJOR_OFFSET 24 ++#define APBH_VERSION_MINOR_MASK (0xff << 16) ++#define APBH_VERSION_MINOR_OFFSET 16 ++#define APBH_VERSION_STEP_MASK 0xffff ++#define APBH_VERSION_STEP_OFFSET 0 ++ ++#endif /* __REGS_APBH_H__ */ diff --cc arch/arm/include/asm/arch-mx6/regs-bch.h index 0000000000,0000000000..c2a7b7d7cc new file mode 100644 --- /dev/null +++ b/arch/arm/include/asm/arch-mx6/regs-bch.h @@@ -1,0 -1,0 +1,235 @@@ ++/* ++ * Freescale i.MX6 BCH Register Definitions ++ * ++ * Copyright (C) 2012 Lothar Waßmann ++ * based on: mx28/regs-bch.h ++ * Copyright (C) 2011 Marek Vasut ++ * on behalf of DENX Software Engineering GmbH ++ * ++ * Based on code from LTIB: ++ * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. ++ * ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ * ++ */ ++ ++#ifndef __MX6_REGS_BCH_H__ ++#define __MX6_REGS_BCH_H__ ++ ++//#include ++ ++#define GPMI_BASE_ADDRESS 0x00112000 ++#define BCH_BASE_ADDRESS 0x00114000 ++ ++#ifndef __ASSEMBLY__ ++struct bch_regs { ++ mx6_reg_32(hw_bch_ctrl); /* 0x000 */ ++ mx6_reg_32(hw_bch_status0); /* 0x010 */ ++ mx6_reg_32(hw_bch_mode); /* 0x020 */ ++ reg_32(hw_bch_encodeptr); /* 0x030 */ ++ reg_32(hw_bch_dataptr); /* 0x040 */ ++ reg_32(hw_bch_metaptr); /* 0x050 */ ++ reg_32(reserved); /* 0x060 */ ++ mx6_reg_32(hw_bch_layoutselect); /* 0x070 */ ++ reg_32(hw_bch_flash0layout0); /* 0x080 */ ++ reg_32(hw_bch_flash0layout1); /* 0x090 */ ++ reg_32(hw_bch_flash1layout0); /* 0x0a0 */ ++ reg_32(hw_bch_flash1layout1); /* 0x0b0 */ ++ reg_32(hw_bch_flash2layout0); /* 0x0c0 */ ++ reg_32(hw_bch_flash2layout1); /* 0x0d0 */ ++ reg_32(hw_bch_flash3layout0); /* 0x0e0 */ ++ reg_32(hw_bch_flash3layout1); /* 0x0f0 */ ++ reg_32(hw_bch_debug0); /* 0x100 */ ++ reg_32(hw_bch_dbgkesread); /* 0x110 */ ++ reg_32(hw_bch_dbgcsferead); /* 0x120 */ ++ reg_32(hw_bch_dbgsyndegread); /* 0x130 */ ++ reg_32(hw_bch_dbgahbmread); /* 0x140 */ ++ reg_32(hw_bch_blockname); /* 0x150 */ ++ reg_32(hw_bch_version); /* 0x160 */ ++}; ++#endif ++ ++#define BCH_CTRL_SFTRST (1 << 31) ++#define BCH_CTRL_CLKGATE (1 << 30) ++#define BCH_CTRL_DEBUGSYNDROME (1 << 22) ++#define BCH_CTRL_M2M_LAYOUT_MASK (0x3 << 18) ++#define BCH_CTRL_M2M_LAYOUT_OFFSET 18 ++#define BCH_CTRL_M2M_ENCODE (1 << 17) ++#define BCH_CTRL_M2M_ENABLE (1 << 16) ++#define BCH_CTRL_DEBUG_STALL_IRQ_EN (1 << 10) ++#define BCH_CTRL_COMPLETE_IRQ_EN (1 << 8) ++#define BCH_CTRL_BM_ERROR_IRQ (1 << 3) ++#define BCH_CTRL_DEBUG_STALL_IRQ (1 << 2) ++#define BCH_CTRL_COMPLETE_IRQ (1 << 0) ++ ++#define BCH_STATUS0_HANDLE_MASK (0xfff << 20) ++#define BCH_STATUS0_HANDLE_OFFSET 20 ++#define BCH_STATUS0_COMPLETED_CE_MASK (0xf << 16) ++#define BCH_STATUS0_COMPLETED_CE_OFFSET 16 ++#define BCH_STATUS0_STATUS_BLK0_MASK (0xff << 8) ++#define BCH_STATUS0_STATUS_BLK0_OFFSET 8 ++#define BCH_STATUS0_STATUS_BLK0_ZERO (0x00 << 8) ++#define BCH_STATUS0_STATUS_BLK0_ERROR1 (0x01 << 8) ++#define BCH_STATUS0_STATUS_BLK0_ERROR2 (0x02 << 8) ++#define BCH_STATUS0_STATUS_BLK0_ERROR3 (0x03 << 8) ++#define BCH_STATUS0_STATUS_BLK0_ERROR4 (0x04 << 8) ++#define BCH_STATUS0_STATUS_BLK0_UNCORRECTABLE (0xfe << 8) ++#define BCH_STATUS0_STATUS_BLK0_ERASED (0xff << 8) ++#define BCH_STATUS0_ALLONES (1 << 4) ++#define BCH_STATUS0_CORRECTED (1 << 3) ++#define BCH_STATUS0_UNCORRECTABLE (1 << 2) ++ ++#define BCH_MODE_ERASE_THRESHOLD_MASK 0xff ++#define BCH_MODE_ERASE_THRESHOLD_OFFSET 0 ++ ++#define BCH_ENCODEPTR_ADDR_MASK 0xffffffff ++#define BCH_ENCODEPTR_ADDR_OFFSET 0 ++ ++#define BCH_DATAPTR_ADDR_MASK 0xffffffff ++#define BCH_DATAPTR_ADDR_OFFSET 0 ++ ++#define BCH_METAPTR_ADDR_MASK 0xffffffff ++#define BCH_METAPTR_ADDR_OFFSET 0 ++ ++#define BCH_LAYOUTSELECT_CS15_SELECT_MASK (0x3 << BCH_LAYOUTSELECT_CS15_SELECT_OFFSET) ++#define BCH_LAYOUTSELECT_CS15_SELECT_OFFSET 30 ++#define BCH_LAYOUTSELECT_CS14_SELECT_MASK (0x3 << BCH_LAYOUTSELECT_CS14_SELECT_OFFSET) ++#define BCH_LAYOUTSELECT_CS14_SELECT_OFFSET 28 ++#define BCH_LAYOUTSELECT_CS13_SELECT_MASK (0x3 << BCH_LAYOUTSELECT_CS13_SELECT_OFFSET) ++#define BCH_LAYOUTSELECT_CS13_SELECT_OFFSET 26 ++#define BCH_LAYOUTSELECT_CS12_SELECT_MASK (0x3 << BCH_LAYOUTSELECT_CS12_SELECT_OFFSET) ++#define BCH_LAYOUTSELECT_CS12_SELECT_OFFSET 24 ++#define BCH_LAYOUTSELECT_CS11_SELECT_MASK (0x3 << BCH_LAYOUTSELECT_CS11_SELECT_OFFSET) ++#define BCH_LAYOUTSELECT_CS11_SELECT_OFFSET 22 ++#define BCH_LAYOUTSELECT_CS10_SELECT_MASK (0x3 << BCH_LAYOUTSELECT_CS10_SELECT_OFFSET) ++#define BCH_LAYOUTSELECT_CS10_SELECT_OFFSET 20 ++#define BCH_LAYOUTSELECT_CS9_SELECT_MASK (0x3 << BCH_LAYOUTSELECT_CS9_SELECT_OFFSET) ++#define BCH_LAYOUTSELECT_CS9_SELECT_OFFSET 18 ++#define BCH_LAYOUTSELECT_CS8_SELECT_MASK (0x3 << BCH_LAYOUTSELECT_CS8_SELECT_OFFSET) ++#define BCH_LAYOUTSELECT_CS8_SELECT_OFFSET 16 ++#define BCH_LAYOUTSELECT_CS7_SELECT_MASK (0x3 << BCH_LAYOUTSELECT_CS7_SELECT_OFFSET) ++#define BCH_LAYOUTSELECT_CS7_SELECT_OFFSET 14 ++#define BCH_LAYOUTSELECT_CS6_SELECT_MASK (0x3 << BCH_LAYOUTSELECT_CS6_SELECT_OFFSET) ++#define BCH_LAYOUTSELECT_CS6_SELECT_OFFSET 12 ++#define BCH_LAYOUTSELECT_CS5_SELECT_MASK (0x3 << BCH_LAYOUTSELECT_CS5_SELECT_OFFSET) ++#define BCH_LAYOUTSELECT_CS5_SELECT_OFFSET 10 ++#define BCH_LAYOUTSELECT_CS4_SELECT_MASK (0x3 << BCH_LAYOUTSELECT_CS4_SELECT_OFFSET) ++#define BCH_LAYOUTSELECT_CS4_SELECT_OFFSET 8 ++#define BCH_LAYOUTSELECT_CS3_SELECT_MASK (0x3 << BCH_LAYOUTSELECT_CS3_SELECT_OFFSET) ++#define BCH_LAYOUTSELECT_CS3_SELECT_OFFSET 6 ++#define BCH_LAYOUTSELECT_CS2_SELECT_MASK (0x3 << BCH_LAYOUTSELECT_CS2_SELECT_OFFSET) ++#define BCH_LAYOUTSELECT_CS2_SELECT_OFFSET 4 ++#define BCH_LAYOUTSELECT_CS1_SELECT_MASK (0x3 << BCH_LAYOUTSELECT_CS1_SELECT_OFFSET) ++#define BCH_LAYOUTSELECT_CS1_SELECT_OFFSET 2 ++#define BCH_LAYOUTSELECT_CS0_SELECT_MASK (0x3 << BCH_LAYOUTSELECT_CS0_SELECT_OFFSET) ++#define BCH_LAYOUTSELECT_CS0_SELECT_OFFSET 0 ++ ++#define BCH_FLASHLAYOUT0_NBLOCKS_MASK (0xff << BCH_FLASHLAYOUT0_NBLOCKS_OFFSET) ++#define BCH_FLASHLAYOUT0_NBLOCKS_OFFSET 24 ++#define BCH_FLASHLAYOUT0_META_SIZE_MASK (0xff << BCH_FLASHLAYOUT0_META_SIZE_OFFSET) ++#define BCH_FLASHLAYOUT0_META_SIZE_OFFSET 16 ++#define BCH_FLASHLAYOUT0_ECC0_MASK (0x1f << BCH_FLASHLAYOUT0_ECC0_OFFSET) ++#define BCH_FLASHLAYOUT0_ECC0_OFFSET 11 ++#define BCH_FLASHLAYOUT0_ECC0_NONE (0x0 << BCH_FLASHLAYOUT0_ECC0_OFFSET) ++#define BCH_FLASHLAYOUT0_ECC0_ECC2 (0x1 << BCH_FLASHLAYOUT0_ECC0_OFFSET) ++#define BCH_FLASHLAYOUT0_ECC0_ECC4 (0x2 << BCH_FLASHLAYOUT0_ECC0_OFFSET) ++#define BCH_FLASHLAYOUT0_ECC0_ECC6 (0x3 << BCH_FLASHLAYOUT0_ECC0_OFFSET) ++#define BCH_FLASHLAYOUT0_ECC0_ECC8 (0x4 << BCH_FLASHLAYOUT0_ECC0_OFFSET) ++#define BCH_FLASHLAYOUT0_ECC0_ECC10 (0x5 << BCH_FLASHLAYOUT0_ECC0_OFFSET) ++#define BCH_FLASHLAYOUT0_ECC0_ECC12 (0x6 << BCH_FLASHLAYOUT0_ECC0_OFFSET) ++#define BCH_FLASHLAYOUT0_ECC0_ECC14 (0x7 << BCH_FLASHLAYOUT0_ECC0_OFFSET) ++#define BCH_FLASHLAYOUT0_ECC0_ECC16 (0x8 << BCH_FLASHLAYOUT0_ECC0_OFFSET) ++#define BCH_FLASHLAYOUT0_ECC0_ECC18 (0x9 << BCH_FLASHLAYOUT0_ECC0_OFFSET) ++#define BCH_FLASHLAYOUT0_ECC0_ECC20 (0xa << BCH_FLASHLAYOUT0_ECC0_OFFSET) ++#define BCH_FLASHLAYOUT0_ECC0_ECC22 (0xb << BCH_FLASHLAYOUT0_ECC0_OFFSET) ++#define BCH_FLASHLAYOUT0_ECC0_ECC24 (0xc << BCH_FLASHLAYOUT0_ECC0_OFFSET) ++#define BCH_FLASHLAYOUT0_ECC0_ECC26 (0xd << BCH_FLASHLAYOUT0_ECC0_OFFSET) ++#define BCH_FLASHLAYOUT0_ECC0_ECC28 (0xe << BCH_FLASHLAYOUT0_ECC0_OFFSET) ++#define BCH_FLASHLAYOUT0_ECC0_ECC30 (0xf << BCH_FLASHLAYOUT0_ECC0_OFFSET) ++#define BCH_FLASHLAYOUT0_ECC0_ECC32 (0x10 << BCH_FLASHLAYOUT0_ECC0_OFFSET) ++#define BCH_FLASHLAYOUT0_GF13_0_GF14_1 (1 << 10) ++#define BCH_FLASHLAYOUT0_DATA0_SIZE_MASK 0x3ff ++#define BCH_FLASHLAYOUT0_DATA0_SIZE_OFFSET 0 ++ ++#define BCH_FLASHLAYOUT1_PAGE_SIZE_MASK (0xffff << BCH_FLASHLAYOUT1_PAGE_SIZE_OFFSET) ++#define BCH_FLASHLAYOUT1_PAGE_SIZE_OFFSET 16 ++#define BCH_FLASHLAYOUT1_ECCN_MASK (0x1f << BCH_FLASHLAYOUT1_ECCN_OFFSET) ++#define BCH_FLASHLAYOUT1_ECCN_OFFSET 11 ++#define BCH_FLASHLAYOUT1_ECCN_NONE (0x0 << BCH_FLASHLAYOUT1_ECCN_OFFSET) ++#define BCH_FLASHLAYOUT1_ECCN_ECC2 (0x1 << BCH_FLASHLAYOUT1_ECCN_OFFSET) ++#define BCH_FLASHLAYOUT1_ECCN_ECC4 (0x2 << BCH_FLASHLAYOUT1_ECCN_OFFSET) ++#define BCH_FLASHLAYOUT1_ECCN_ECC6 (0x3 << BCH_FLASHLAYOUT1_ECCN_OFFSET) ++#define BCH_FLASHLAYOUT1_ECCN_ECC8 (0x4 << BCH_FLASHLAYOUT1_ECCN_OFFSET) ++#define BCH_FLASHLAYOUT1_ECCN_ECC10 (0x5 << BCH_FLASHLAYOUT1_ECCN_OFFSET) ++#define BCH_FLASHLAYOUT1_ECCN_ECC12 (0x6 << BCH_FLASHLAYOUT1_ECCN_OFFSET) ++#define BCH_FLASHLAYOUT1_ECCN_ECC14 (0x7 << BCH_FLASHLAYOUT1_ECCN_OFFSET) ++#define BCH_FLASHLAYOUT1_ECCN_ECC16 (0x8 << BCH_FLASHLAYOUT1_ECCN_OFFSET) ++#define BCH_FLASHLAYOUT1_ECCN_ECC18 (0x9 << BCH_FLASHLAYOUT1_ECCN_OFFSET) ++#define BCH_FLASHLAYOUT1_ECCN_ECC20 (0xa << BCH_FLASHLAYOUT1_ECCN_OFFSET) ++#define BCH_FLASHLAYOUT1_ECCN_ECC22 (0xb << BCH_FLASHLAYOUT1_ECCN_OFFSET) ++#define BCH_FLASHLAYOUT1_ECCN_ECC24 (0xc << BCH_FLASHLAYOUT1_ECCN_OFFSET) ++#define BCH_FLASHLAYOUT1_ECCN_ECC26 (0xd << BCH_FLASHLAYOUT1_ECCN_OFFSET) ++#define BCH_FLASHLAYOUT1_ECCN_ECC28 (0xe << BCH_FLASHLAYOUT1_ECCN_OFFSET) ++#define BCH_FLASHLAYOUT1_ECCN_ECC30 (0xf << BCH_FLASHLAYOUT1_ECCN_OFFSET) ++#define BCH_FLASHLAYOUT1_ECCN_ECC32 (0x10 << BCH_FLASHLAYOUT1_ECCN_OFFSET) ++#define BCH_FLASHLAYOUT1_GF13_0_GF14_1 (1 << 10) ++#define BCH_FLASHLAYOUT1_DATAN_SIZE_MASK 0x3ff ++#define BCH_FLASHLAYOUT1_DATAN_SIZE_OFFSET 0 ++ ++#define BCH_DEBUG0_RSVD1_MASK (0x1f << 27) ++#define BCH_DEBUG0_RSVD1_OFFSET 27 ++#define BCH_DEBUG0_ROM_BIST_ENABLE (1 << 26) ++#define BCH_DEBUG0_ROM_BIST_COMPLETE (1 << 25) ++#define BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_MASK (0x1ff << 16) ++#define BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_OFFSET 16 ++#define BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_NORMAL (0x0 << 16) ++#define BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_TEST_MODE (0x1 << 16) ++#define BCH_DEBUG0_KES_DEBUG_SHIFT_SYND (1 << 15) ++#define BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG (1 << 14) ++#define BCH_DEBUG0_KES_DEBUG_MODE4K (1 << 13) ++#define BCH_DEBUG0_KES_DEBUG_KICK (1 << 12) ++#define BCH_DEBUG0_KES_STANDALONE (1 << 11) ++#define BCH_DEBUG0_KES_DEBUG_STEP (1 << 10) ++#define BCH_DEBUG0_KES_DEBUG_STALL (1 << 9) ++#define BCH_DEBUG0_BM_KES_TEST_BYPASS (1 << 8) ++#define BCH_DEBUG0_RSVD0_MASK (0x3 << 6) ++#define BCH_DEBUG0_RSVD0_OFFSET 6 ++#define BCH_DEBUG0_DEBUG_REG_SELECT_MASK 0x3f ++#define BCH_DEBUG0_DEBUG_REG_SELECT_OFFSET 0 ++ ++#define BCH_DBGKESREAD_VALUES_MASK 0xffffffff ++#define BCH_DBGKESREAD_VALUES_OFFSET 0 ++ ++#define BCH_DBGCSFEREAD_VALUES_MASK 0xffffffff ++#define BCH_DBGCSFEREAD_VALUES_OFFSET 0 ++ ++#define BCH_DBGSYNDGENREAD_VALUES_MASK 0xffffffff ++#define BCH_DBGSYNDGENREAD_VALUES_OFFSET 0 ++ ++#define BCH_DBGAHBMREAD_VALUES_MASK 0xffffffff ++#define BCH_DBGAHBMREAD_VALUES_OFFSET 0 ++ ++#define BCH_BLOCKNAME_NAME_MASK 0xffffffff ++#define BCH_BLOCKNAME_NAME_OFFSET 0 ++ ++#define BCH_VERSION_MAJOR_MASK (0xff << 24) ++#define BCH_VERSION_MAJOR_OFFSET 24 ++#define BCH_VERSION_MINOR_MASK (0xff << 16) ++#define BCH_VERSION_MINOR_OFFSET 16 ++#define BCH_VERSION_STEP_MASK 0xffff ++#define BCH_VERSION_STEP_OFFSET 0 ++ ++#endif /* __MX6_REGS_BCH_H__ */ diff --cc arch/arm/include/asm/arch-mx6/regs-gpmi.h index 0000000000,0000000000..5d0b2206f2 new file mode 100644 --- /dev/null +++ b/arch/arm/include/asm/arch-mx6/regs-gpmi.h @@@ -1,0 -1,0 +1,227 @@@ ++/* ++ * Freescale i.MX6Q GPMI Register Definitions ++ * ++ * Copyright (C) 2011 Marek Vasut ++ * on behalf of DENX Software Engineering GmbH ++ * ++ * Based on code from LTIB: ++ * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ * ++ */ ++ ++#ifndef __MX6Q_REGS_GPMI_H__ ++#define __MX6Q_REGS_GPMI_H__ ++ ++#define MXS_GPMI_BASE 0x00112000 ++ ++#ifndef __ASSEMBLY__ ++struct gpmi_regs { ++ mx6_reg_32(hw_gpmi_ctrl0); /* 0x000 */ ++ reg_32(hw_gpmi_compare); /* 0x010 */ ++ mx6_reg_32(hw_gpmi_eccctrl); /* 0x020 */ ++ reg_32(hw_gpmi_ecccount); /* 0x030 */ ++ reg_32(hw_gpmi_payload); /* 0x040 */ ++ reg_32(hw_gpmi_auxiliary); /* 0x050 */ ++ mx6_reg_32(hw_gpmi_ctrl1); /* 0x060 */ ++ reg_32(hw_gpmi_timing0); /* 0x070 */ ++ reg_32(hw_gpmi_timing1); /* 0x080 */ ++ reg_32(hw_gpmi_timing2); /* 0x090 */ ++ reg_32(hw_gpmi_data); /* 0x0a0 */ ++ reg_32(hw_gpmi_stat); /* 0x0b0 */ ++ reg_32(hw_gpmi_debug); /* 0x0c0 */ ++ reg_32(hw_gpmi_version); /* 0x0d0 */ ++ reg_32(hw_gpmi_debug2); /* 0x0e0 */ ++ reg_32(hw_gpmi_debug3); /* 0x0f0 */ ++ reg_32(hw_gpmi_rd_ddr_dll_ctrl); /* 0x100 */ ++ reg_32(hw_gpmi_wr_ddr_dll_ctrl); /* 0x110 */ ++ reg_32(hw_gpmi_rd_ddr_dll_sts); /* 0x120 */ ++ reg_32(hw_gpmi_wr_ddr_dll_sts); /* 0x130 */ ++ ++}; ++#endif ++ ++#define GPMI_CTRL0_SFTRST (1 << 31) ++#define GPMI_CTRL0_CLKGATE (1 << 30) ++#define GPMI_CTRL0_RUN (1 << 29) ++#define GPMI_CTRL0_DEV_IRQ_EN (1 << 28) ++#define GPMI_CTRL0_LOCK_CS (1 << 27) ++#define GPMI_CTRL0_UDMA (1 << 26) ++#define GPMI_CTRL0_COMMAND_MODE_MASK (0x3 << 24) ++#define GPMI_CTRL0_COMMAND_MODE_OFFSET 24 ++#define GPMI_CTRL0_COMMAND_MODE_WRITE (0x0 << 24) ++#define GPMI_CTRL0_COMMAND_MODE_READ (0x1 << 24) ++#define GPMI_CTRL0_COMMAND_MODE_READ_AND_COMPARE (0x2 << 24) ++#define GPMI_CTRL0_COMMAND_MODE_WAIT_FOR_READY (0x3 << 24) ++#define GPMI_CTRL0_WORD_LENGTH (1 << 23) ++#define GPMI_CTRL0_CS_MASK (0x7 << 20) ++#define GPMI_CTRL0_CS_OFFSET 20 ++#define GPMI_CTRL0_ADDRESS_MASK (0x7 << 17) ++#define GPMI_CTRL0_ADDRESS_OFFSET 17 ++#define GPMI_CTRL0_ADDRESS_NAND_DATA (0x0 << 17) ++#define GPMI_CTRL0_ADDRESS_NAND_CLE (0x1 << 17) ++#define GPMI_CTRL0_ADDRESS_NAND_ALE (0x2 << 17) ++#define GPMI_CTRL0_ADDRESS_INCREMENT (1 << 16) ++#define GPMI_CTRL0_XFER_COUNT_MASK 0xffff ++#define GPMI_CTRL0_XFER_COUNT_OFFSET 0 ++ ++#define GPMI_COMPARE_MASK_MASK (0xffff << 16) ++#define GPMI_COMPARE_MASK_OFFSET 16 ++#define GPMI_COMPARE_REFERENCE_MASK 0xffff ++#define GPMI_COMPARE_REFERENCE_OFFSET 0 ++ ++#define GPMI_ECCCTRL_HANDLE_MASK (0xffff << 16) ++#define GPMI_ECCCTRL_HANDLE_OFFSET 16 ++#define GPMI_ECCCTRL_ECC_CMD_MASK (0x3 << 13) ++#define GPMI_ECCCTRL_ECC_CMD_OFFSET 13 ++#define GPMI_ECCCTRL_ECC_CMD_DECODE (0x0 << 13) ++#define GPMI_ECCCTRL_ECC_CMD_ENCODE (0x1 << 13) ++#define GPMI_ECCCTRL_ENABLE_ECC (1 << 12) ++#define GPMI_ECCCTRL_BUFFER_MASK_MASK 0x1ff ++#define GPMI_ECCCTRL_BUFFER_MASK_OFFSET 0 ++#define GPMI_ECCCTRL_BUFFER_MASK_BCH_AUXONLY 0x100 ++#define GPMI_ECCCTRL_BUFFER_MASK_BCH_PAGE 0x1ff ++ ++#define GPMI_ECCCOUNT_COUNT_MASK 0xffff ++#define GPMI_ECCCOUNT_COUNT_OFFSET 0 ++ ++#define GPMI_PAYLOAD_ADDRESS_MASK (0x3fffffff << 2) ++#define GPMI_PAYLOAD_ADDRESS_OFFSET 2 ++ ++#define GPMI_AUXILIARY_ADDRESS_MASK (0x3fffffff << 2) ++#define GPMI_AUXILIARY_ADDRESS_OFFSET 2 ++ ++#define GPMI_CTRL1_DECOUPLE_CS (1 << 24) ++#define GPMI_CTRL1_WRN_DLY_SEL_MASK (0x3 << 22) ++#define GPMI_CTRL1_WRN_DLY_SEL_OFFSET 22 ++#define GPMI_CTRL1_TIMEOUT_IRQ_EN (1 << 20) ++#define GPMI_CTRL1_GANGED_RDYBUSY (1 << 19) ++#define GPMI_CTRL1_BCH_MODE (1 << 18) ++#define GPMI_CTRL1_DLL_ENABLE (1 << 17) ++#define GPMI_CTRL1_HALF_PERIOD (1 << 16) ++#define GPMI_CTRL1_RDN_DELAY_MASK (0xf << 12) ++#define GPMI_CTRL1_RDN_DELAY_OFFSET 12 ++#define GPMI_CTRL1_DMA2ECC_MODE (1 << 11) ++#define GPMI_CTRL1_DEV_IRQ (1 << 10) ++#define GPMI_CTRL1_TIMEOUT_IRQ (1 << 9) ++#define GPMI_CTRL1_BURST_EN (1 << 8) ++#define GPMI_CTRL1_ABORT_WAIT_REQUEST (1 << 7) ++#define GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL_MASK (0x7 << 4) ++#define GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL_OFFSET 4 ++#define GPMI_CTRL1_DEV_RESET (1 << 3) ++#define GPMI_CTRL1_ATA_IRQRDY_POLARITY (1 << 2) ++#define GPMI_CTRL1_CAMERA_MODE (1 << 1) ++#define GPMI_CTRL1_GPMI_MODE (1 << 0) ++ ++#define GPMI_TIMING0_ADDRESS_SETUP_MASK (0xff << 16) ++#define GPMI_TIMING0_ADDRESS_SETUP_OFFSET 16 ++#define GPMI_TIMING0_DATA_HOLD_MASK (0xff << 8) ++#define GPMI_TIMING0_DATA_HOLD_OFFSET 8 ++#define GPMI_TIMING0_DATA_SETUP_MASK 0xff ++#define GPMI_TIMING0_DATA_SETUP_OFFSET 0 ++ ++#define GPMI_TIMING1_DEVICE_BUSY_TIMEOUT_MASK (0xffff << 16) ++#define GPMI_TIMING1_DEVICE_BUSY_TIMEOUT_OFFSET 16 ++ ++#define GPMI_TIMING2_UDMA_TRP_MASK (0xff << 24) ++#define GPMI_TIMING2_UDMA_TRP_OFFSET 24 ++#define GPMI_TIMING2_UDMA_ENV_MASK (0xff << 16) ++#define GPMI_TIMING2_UDMA_ENV_OFFSET 16 ++#define GPMI_TIMING2_UDMA_HOLD_MASK (0xff << 8) ++#define GPMI_TIMING2_UDMA_HOLD_OFFSET 8 ++#define GPMI_TIMING2_UDMA_SETUP_MASK 0xff ++#define GPMI_TIMING2_UDMA_SETUP_OFFSET 0 ++ ++#define GPMI_DATA_DATA_MASK 0xffffffff ++#define GPMI_DATA_DATA_OFFSET 0 ++ ++#define GPMI_STAT_READY_BUSY_MASK (0xff << 24) ++#define GPMI_STAT_READY_BUSY_OFFSET 24 ++#define GPMI_STAT_RDY_TIMEOUT_MASK (0xff << 16) ++#define GPMI_STAT_RDY_TIMEOUT_OFFSET 16 ++#define GPMI_STAT_DEV7_ERROR (1 << 15) ++#define GPMI_STAT_DEV6_ERROR (1 << 14) ++#define GPMI_STAT_DEV5_ERROR (1 << 13) ++#define GPMI_STAT_DEV4_ERROR (1 << 12) ++#define GPMI_STAT_DEV3_ERROR (1 << 11) ++#define GPMI_STAT_DEV2_ERROR (1 << 10) ++#define GPMI_STAT_DEV1_ERROR (1 << 9) ++#define GPMI_STAT_DEV0_ERROR (1 << 8) ++#define GPMI_STAT_ATA_IRQ (1 << 4) ++#define GPMI_STAT_INVALID_BUFFER_MASK (1 << 3) ++#define GPMI_STAT_FIFO_EMPTY (1 << 2) ++#define GPMI_STAT_FIFO_FULL (1 << 1) ++#define GPMI_STAT_PRESENT (1 << 0) ++ ++#define GPMI_DEBUG_WAIT_FOR_READY_END_MASK (0xff << 24) ++#define GPMI_DEBUG_WAIT_FOR_READY_END_OFFSET 24 ++#define GPMI_DEBUG_DMA_SENSE_MASK (0xff << 16) ++#define GPMI_DEBUG_DMA_SENSE_OFFSET 16 ++#define GPMI_DEBUG_DMAREQ_MASK (0xff << 8) ++#define GPMI_DEBUG_DMAREQ_OFFSET 8 ++#define GPMI_DEBUG_CMD_END_MASK 0xff ++#define GPMI_DEBUG_CMD_END_OFFSET 0 ++ ++#define GPMI_VERSION_MAJOR_MASK (0xff << 24) ++#define GPMI_VERSION_MAJOR_OFFSET 24 ++#define GPMI_VERSION_MINOR_MASK (0xff << 16) ++#define GPMI_VERSION_MINOR_OFFSET 16 ++#define GPMI_VERSION_STEP_MASK 0xffff ++#define GPMI_VERSION_STEP_OFFSET 0 ++ ++#define GPMI_DEBUG2_UDMA_STATE_MASK (0xf << 24) ++#define GPMI_DEBUG2_UDMA_STATE_OFFSET 24 ++#define GPMI_DEBUG2_BUSY (1 << 23) ++#define GPMI_DEBUG2_PIN_STATE_MASK (0x7 << 20) ++#define GPMI_DEBUG2_PIN_STATE_OFFSET 20 ++#define GPMI_DEBUG2_PIN_STATE_PSM_IDLE (0x0 << 20) ++#define GPMI_DEBUG2_PIN_STATE_PSM_BYTCNT (0x1 << 20) ++#define GPMI_DEBUG2_PIN_STATE_PSM_ADDR (0x2 << 20) ++#define GPMI_DEBUG2_PIN_STATE_PSM_STALL (0x3 << 20) ++#define GPMI_DEBUG2_PIN_STATE_PSM_STROBE (0x4 << 20) ++#define GPMI_DEBUG2_PIN_STATE_PSM_ATARDY (0x5 << 20) ++#define GPMI_DEBUG2_PIN_STATE_PSM_DHOLD (0x6 << 20) ++#define GPMI_DEBUG2_PIN_STATE_PSM_DONE (0x7 << 20) ++#define GPMI_DEBUG2_MAIN_STATE_MASK (0xf << 16) ++#define GPMI_DEBUG2_MAIN_STATE_OFFSET 16 ++#define GPMI_DEBUG2_MAIN_STATE_MSM_IDLE (0x0 << 16) ++#define GPMI_DEBUG2_MAIN_STATE_MSM_BYTCNT (0x1 << 16) ++#define GPMI_DEBUG2_MAIN_STATE_MSM_WAITFE (0x2 << 16) ++#define GPMI_DEBUG2_MAIN_STATE_MSM_WAITFR (0x3 << 16) ++#define GPMI_DEBUG2_MAIN_STATE_MSM_DMAREQ (0x4 << 16) ++#define GPMI_DEBUG2_MAIN_STATE_MSM_DMAACK (0x5 << 16) ++#define GPMI_DEBUG2_MAIN_STATE_MSM_WAITFF (0x6 << 16) ++#define GPMI_DEBUG2_MAIN_STATE_MSM_LDFIFO (0x7 << 16) ++#define GPMI_DEBUG2_MAIN_STATE_MSM_LDDMAR (0x8 << 16) ++#define GPMI_DEBUG2_MAIN_STATE_MSM_RDCMP (0x9 << 16) ++#define GPMI_DEBUG2_MAIN_STATE_MSM_DONE (0xa << 16) ++#define GPMI_DEBUG2_SYND2GPMI_BE_MASK (0xf << 12) ++#define GPMI_DEBUG2_SYND2GPMI_BE_OFFSET 12 ++#define GPMI_DEBUG2_GPMI2SYND_VALID (1 << 11) ++#define GPMI_DEBUG2_GPMI2SYND_READY (1 << 10) ++#define GPMI_DEBUG2_SYND2GPMI_VALID (1 << 9) ++#define GPMI_DEBUG2_SYND2GPMI_READY (1 << 8) ++#define GPMI_DEBUG2_VIEW_DELAYED_RDN (1 << 7) ++#define GPMI_DEBUG2_UPDATE_WINDOW (1 << 6) ++#define GPMI_DEBUG2_RDN_TAP_MASK 0x3f ++#define GPMI_DEBUG2_RDN_TAP_OFFSET 0 ++ ++#define GPMI_DEBUG3_APB_WORD_CNTR_MASK (0xffff << 16) ++#define GPMI_DEBUG3_APB_WORD_CNTR_OFFSET 16 ++#define GPMI_DEBUG3_DEV_WORD_CNTR_MASK 0xffff ++#define GPMI_DEBUG3_DEV_WORD_CNTR_OFFSET 0 ++ ++#endif /* __MX6Q_REGS_GPMI_H__ */ diff --cc arch/arm/include/asm/arch-mx6/regs-ocotp.h index 0000000000,0000000000..57dc2f2aea new file mode 100644 --- /dev/null +++ b/arch/arm/include/asm/arch-mx6/regs-ocotp.h @@@ -1,0 -1,0 +1,113 @@@ ++/* ++ * Freescale i.MX6 OCOTP Register Definitions ++ * ++ * Copyright (C) 2012 Lothar Waßmann ++ * based on: ++ * Copyright (C) 2011 Marek Vasut ++ * on behalf of DENX Software Engineering GmbH ++ * ++ * Based on code from LTIB: ++ * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ * ++ */ ++ ++#ifndef __MX6_REGS_OCOTP_H__ ++#define __MX6_REGS_OCOTP_H__ ++ ++#ifndef __ASSEMBLY__ ++#define mx6_ocotp_reg_32(r) mx6_reg_32(hw_ocotp_##r) ++#define ocotp_reg_32(r) reg_32(hw_ocotp_##r) ++ ++struct mx6_ocotp_regs { ++ mx6_ocotp_reg_32(ctrl); /* 0x000 */ ++ ocotp_reg_32(timing); /* 0x010 */ ++ ocotp_reg_32(data); /* 0x020 */ ++ ocotp_reg_32(read_ctrl); /* 0x030 */ ++ ocotp_reg_32(read_fuse_data); /* 0x040 */ ++ ocotp_reg_32(sw_sticky); /* 0x050 */ ++ mx6_ocotp_reg_32(scs); /* 0x060 */ ++ reg_32(rsrvd1); /* 0x070 */ ++ reg_32(rsrvd2); /* 0x080 */ ++ ocotp_reg_32(version); /* 0x090 */ ++ ++ reg_32(rsrvd3[54]); /* 0x0a0 - 0x3ff */ ++ ++ /* bank 0 */ ++ ocotp_reg_32(lock); /* 0x400 */ ++ ocotp_reg_32(cfg0); /* 0x410 */ ++ ocotp_reg_32(cfg1); /* 0x420 */ ++ ocotp_reg_32(cfg2); /* 0x430 */ ++ ocotp_reg_32(cfg3); /* 0x440 */ ++ ocotp_reg_32(cfg4); /* 0x450 */ ++ ocotp_reg_32(cfg5); /* 0x460 */ ++ ocotp_reg_32(cfg6); /* 0x470 */ ++ ++ /* bank 1 */ ++ ocotp_reg_32(mem0); /* 0x480 */ ++ ocotp_reg_32(mem1); /* 0x490 */ ++ ocotp_reg_32(mem2); /* 0x4a0 */ ++ ocotp_reg_32(mem3); /* 0x4b0 */ ++ ocotp_reg_32(mem4); /* 0x4c0 */ ++ ocotp_reg_32(ana0); /* 0x4d0 */ ++ ocotp_reg_32(ana1); /* 0x4e0 */ ++ ocotp_reg_32(ana2); /* 0x4f0 */ ++ ++ /* bank 2 */ ++ reg_32(rsrvd4[8]); /* 0x500 - 0x57f */ ++ ++ /* bank 3 */ ++ ocotp_reg_32(srk0); /* 0x580 */ ++ ocotp_reg_32(srk1); /* 0x590 */ ++ ocotp_reg_32(srk2); /* 0x5a0 */ ++ ocotp_reg_32(srk3); /* 0x5b0 */ ++ ocotp_reg_32(srk4); /* 0x5c0 */ ++ ocotp_reg_32(srk5); /* 0x5d0 */ ++ ocotp_reg_32(srk6); /* 0x5e0 */ ++ ocotp_reg_32(srk7); /* 0x5f0 */ ++ ++ /* bank 4 */ ++ ocotp_reg_32(hsjc_resp0); /* 0x600 */ ++ ocotp_reg_32(hsjc_resp1); /* 0x610 */ ++ ocotp_reg_32(mac0); /* 0x620 */ ++ ocotp_reg_32(mac1); /* 0x630 */ ++ reg_32(rsrvd5[2]); /* 0x640 - 0x65f */ ++ ocotp_reg_32(gp1); /* 0x660 */ ++ ocotp_reg_32(gp2); /* 0x670 */ ++ ++ /* bank 5 */ ++ reg_32(rsrvd6[5]); /* 0x680 - 0x6cf */ ++ ocotp_reg_32(misc_conf); /* 0x6d0 */ ++ ocotp_reg_32(field_return); /* 0x6e0 */ ++ ocotp_reg_32(srk_revoke); /* 0x6f0 */ ++}; ++ ++#endif ++ ++#define OCOTP_CTRL_BUSY (1 << 8) ++#define OCOTP_CTRL_ERROR (1 << 9) ++#define OCOTP_CTRL_RELOAD_SHADOWS (1 << 10) ++ ++#define OCOTP_RD_CTRL_READ_FUSE (1 << 0) ++ ++#define OCOTP_VERSION_MAJOR_MASK (0xff << 24) ++#define OCOTP_VERSION_MAJOR_OFFSET 24 ++#define OCOTP_VERSION_MINOR_MASK (0xff << 16) ++#define OCOTP_VERSION_MINOR_OFFSET 16 ++#define OCOTP_VERSION_STEP_MASK 0xffff ++#define OCOTP_VERSION_STEP_OFFSET 0 ++ ++#endif /* __MX6_REGS_OCOTP_H__ */ diff --cc arch/arm/include/asm/arch-mx6/sys_proto.h index 711b30dfe2,3193297610..d386a94a7c --- a/arch/arm/include/asm/arch-mx6/sys_proto.h +++ b/arch/arm/include/asm/arch-mx6/sys_proto.h @@@ -24,11 -24,19 +24,30 @@@ #ifndef _SYS_PROTO_H_ #define _SYS_PROTO_H_ - #define is_soc_rev(rev) ((get_cpu_rev() & 0xFF) - rev) + #define MXC_CPU_MX51 0x51 + #define MXC_CPU_MX53 0x53 + #define MXC_CPU_MX6SL 0x60 + #define MXC_CPU_MX6DL 0x61 + #define MXC_CPU_MX6SOLO 0x62 + #define MXC_CPU_MX6Q 0x63 + #define is_soc_rev(rev) ((get_cpu_rev() & 0xFF) - rev) u32 get_cpu_rev(void); + const char *get_imx_type(u32 imxtype); + unsigned imx_ddr_size(void); + -void set_vddsoc(u32 mv); ++ ++struct mx6_register_32; ++ ++int mxs_reset_block(struct mx6_register_32 *reg); ++int mxs_wait_mask_set(struct mx6_register_32 *reg, ++ uint32_t mask, ++ unsigned long timeout); ++int mxs_wait_mask_clr(struct mx6_register_32 *reg, ++ uint32_t mask, ++ unsigned long timeout); + - void set_vddsoc(u32 mv); ++void imx_get_mac_from_fuse(int dev_id, unsigned char *mac); /* * Initializes on-chip ethernet controllers. diff --cc arch/arm/include/asm/arch-mxs/mxsfb.h index 16e82128c9,0000000000..16e82128c9 mode 100644,000000..100644 --- a/arch/arm/include/asm/arch-mxs/mxsfb.h +++ b/arch/arm/include/asm/arch-mxs/mxsfb.h diff --cc arch/arm/include/asm/arch-mxs/regs-apbh.h index 91d7bc8400,e18e677e33..7a09b6dfca --- a/arch/arm/include/asm/arch-mxs/regs-apbh.h +++ b/arch/arm/include/asm/arch-mxs/regs-apbh.h @@@ -29,14 -29,14 +29,14 @@@ #include #ifndef __ASSEMBLY__ - struct mx28_apbh_regs { - mx28_reg_32(hw_apbh_ctrl0) - mx28_reg_32(hw_apbh_ctrl1) - mx28_reg_32(hw_apbh_ctrl2) - mx28_reg_32(hw_apbh_channel_ctrl) - mx28_reg_32(hw_apbh_devsel) - mx28_reg_32(hw_apbh_dma_burst_size) - mx28_reg_32(hw_apbh_debug) -struct mxs_apbh_regs { ++struct apbh_regs { + mxs_reg_32(hw_apbh_ctrl0) + mxs_reg_32(hw_apbh_ctrl1) + mxs_reg_32(hw_apbh_ctrl2) + mxs_reg_32(hw_apbh_channel_ctrl) + mxs_reg_32(hw_apbh_devsel) + mxs_reg_32(hw_apbh_dma_burst_size) + mxs_reg_32(hw_apbh_debug) uint32_t reserved[36]; diff --cc arch/arm/include/asm/arch-mxs/regs-bch.h index 9243bdd1c0,40baa4d1f9..287ea91768 --- a/arch/arm/include/asm/arch-mxs/regs-bch.h +++ b/arch/arm/include/asm/arch-mxs/regs-bch.h @@@ -29,13 -29,13 +29,13 @@@ #include #ifndef __ASSEMBLY__ - struct mx28_bch_regs { - mx28_reg_32(hw_bch_ctrl) - mx28_reg_32(hw_bch_status0) - mx28_reg_32(hw_bch_mode) - mx28_reg_32(hw_bch_encodeptr) - mx28_reg_32(hw_bch_dataptr) - mx28_reg_32(hw_bch_metaptr) -struct mxs_bch_regs { ++struct bch_regs { + mxs_reg_32(hw_bch_ctrl) + mxs_reg_32(hw_bch_status0) + mxs_reg_32(hw_bch_mode) + mxs_reg_32(hw_bch_encodeptr) + mxs_reg_32(hw_bch_dataptr) + mxs_reg_32(hw_bch_metaptr) uint32_t reserved[4]; @@@ -57,6 -57,6 +57,8 @@@ }; #endif ++#define BCH_BASE_ADDRESS MXS_BCH_BASE ++ #define BCH_CTRL_SFTRST (1 << 31) #define BCH_CTRL_CLKGATE (1 << 30) #define BCH_CTRL_DEBUGSYNDROME (1 << 22) diff --cc arch/arm/include/asm/arch-mxs/regs-gpmi.h index 1b487f46c6,624d618560..cd630d336c --- a/arch/arm/include/asm/arch-mxs/regs-gpmi.h +++ b/arch/arm/include/asm/arch-mxs/regs-gpmi.h @@@ -29,16 -29,16 +29,16 @@@ #include #ifndef __ASSEMBLY__ - struct mx28_gpmi_regs { - mx28_reg_32(hw_gpmi_ctrl0) - mx28_reg_32(hw_gpmi_compare) - mx28_reg_32(hw_gpmi_eccctrl) - mx28_reg_32(hw_gpmi_ecccount) - mx28_reg_32(hw_gpmi_payload) - mx28_reg_32(hw_gpmi_auxiliary) - mx28_reg_32(hw_gpmi_ctrl1) - mx28_reg_32(hw_gpmi_timing0) - mx28_reg_32(hw_gpmi_timing1) -struct mxs_gpmi_regs { ++struct gpmi_regs { + mxs_reg_32(hw_gpmi_ctrl0) + mxs_reg_32(hw_gpmi_compare) + mxs_reg_32(hw_gpmi_eccctrl) + mxs_reg_32(hw_gpmi_ecccount) + mxs_reg_32(hw_gpmi_payload) + mxs_reg_32(hw_gpmi_auxiliary) + mxs_reg_32(hw_gpmi_ctrl1) + mxs_reg_32(hw_gpmi_timing0) + mxs_reg_32(hw_gpmi_timing1) uint32_t reserved[4]; @@@ -49,6 -49,6 +49,8 @@@ }; #endif ++#define GPMI_BASE_ADDRESS MXS_GPMI_BASE ++ #define GPMI_CTRL0_SFTRST (1 << 31) #define GPMI_CTRL0_CLKGATE (1 << 30) #define GPMI_CTRL0_RUN (1 << 29) diff --cc arch/arm/include/asm/arch-mxs/regs-lcdif.h index 0000000000,b90b2d437a..10b33dd4d9 mode 000000,100644..100644 --- a/arch/arm/include/asm/arch-mxs/regs-lcdif.h +++ b/arch/arm/include/asm/arch-mxs/regs-lcdif.h @@@ -1,0 -1,212 +1,234 @@@ + /* + * Freescale i.MX28 LCDIF Register Definitions + * + * Copyright (C) 2011 Marek Vasut + * on behalf of DENX Software Engineering GmbH + * + * Based on code from LTIB: + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + + #ifndef __MX28_REGS_LCDIF_H__ + #define __MX28_REGS_LCDIF_H__ + + #include + + #ifndef __ASSEMBLY__ + struct mxs_lcdif_regs { + mxs_reg_32(hw_lcdif_ctrl) /* 0x00 */ + mxs_reg_32(hw_lcdif_ctrl1) /* 0x10 */ + mxs_reg_32(hw_lcdif_ctrl2) /* 0x20 */ + mxs_reg_32(hw_lcdif_transfer_count) /* 0x30 */ + mxs_reg_32(hw_lcdif_cur_buf) /* 0x40 */ + mxs_reg_32(hw_lcdif_next_buf) /* 0x50 */ + mxs_reg_32(hw_lcdif_timing) /* 0x60 */ + mxs_reg_32(hw_lcdif_vdctrl0) /* 0x70 */ + mxs_reg_32(hw_lcdif_vdctrl1) /* 0x80 */ + mxs_reg_32(hw_lcdif_vdctrl2) /* 0x90 */ + mxs_reg_32(hw_lcdif_vdctrl3) /* 0xa0 */ + mxs_reg_32(hw_lcdif_vdctrl4) /* 0xb0 */ + mxs_reg_32(hw_lcdif_dvictrl0) /* 0xc0 */ + mxs_reg_32(hw_lcdif_dvictrl1) /* 0xd0 */ + mxs_reg_32(hw_lcdif_dvictrl2) /* 0xe0 */ + mxs_reg_32(hw_lcdif_dvictrl3) /* 0xf0 */ + mxs_reg_32(hw_lcdif_dvictrl4) /* 0x100 */ + mxs_reg_32(hw_lcdif_csc_coeffctrl0) /* 0x110 */ + mxs_reg_32(hw_lcdif_csc_coeffctrl1) /* 0x120 */ + mxs_reg_32(hw_lcdif_csc_coeffctrl2) /* 0x130 */ + mxs_reg_32(hw_lcdif_csc_coeffctrl3) /* 0x140 */ + mxs_reg_32(hw_lcdif_csc_coeffctrl4) /* 0x150 */ + mxs_reg_32(hw_lcdif_csc_offset) /* 0x160 */ + mxs_reg_32(hw_lcdif_csc_limit) /* 0x170 */ + mxs_reg_32(hw_lcdif_data) /* 0x180 */ + mxs_reg_32(hw_lcdif_bm_error_stat) /* 0x190 */ + mxs_reg_32(hw_lcdif_crc_stat) /* 0x1a0 */ + mxs_reg_32(hw_lcdif_lcdif_stat) /* 0x1b0 */ + mxs_reg_32(hw_lcdif_version) /* 0x1c0 */ + mxs_reg_32(hw_lcdif_debug0) /* 0x1d0 */ + mxs_reg_32(hw_lcdif_debug1) /* 0x1e0 */ + mxs_reg_32(hw_lcdif_debug2) /* 0x1f0 */ + }; + #endif + + #define LCDIF_CTRL_SFTRST (1 << 31) + #define LCDIF_CTRL_CLKGATE (1 << 30) + #define LCDIF_CTRL_YCBCR422_INPUT (1 << 29) + #define LCDIF_CTRL_READ_WRITEB (1 << 28) + #define LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE (1 << 27) + #define LCDIF_CTRL_DATA_SHIFT_DIR (1 << 26) + #define LCDIF_CTRL_SHIFT_NUM_BITS_MASK (0x1f << 21) + #define LCDIF_CTRL_SHIFT_NUM_BITS_OFFSET 21 + #define LCDIF_CTRL_DVI_MODE (1 << 20) + #define LCDIF_CTRL_BYPASS_COUNT (1 << 19) + #define LCDIF_CTRL_VSYNC_MODE (1 << 18) + #define LCDIF_CTRL_DOTCLK_MODE (1 << 17) + #define LCDIF_CTRL_DATA_SELECT (1 << 16) + #define LCDIF_CTRL_INPUT_DATA_SWIZZLE_MASK (0x3 << 14) + #define LCDIF_CTRL_INPUT_DATA_SWIZZLE_OFFSET 14 + #define LCDIF_CTRL_CSC_DATA_SWIZZLE_MASK (0x3 << 12) + #define LCDIF_CTRL_CSC_DATA_SWIZZLE_OFFSET 12 + #define LCDIF_CTRL_LCD_DATABUS_WIDTH_MASK (0x3 << 10) + #define LCDIF_CTRL_LCD_DATABUS_WIDTH_OFFSET 10 + #define LCDIF_CTRL_LCD_DATABUS_WIDTH_16BIT (0 << 10) + #define LCDIF_CTRL_LCD_DATABUS_WIDTH_8BIT (1 << 10) + #define LCDIF_CTRL_LCD_DATABUS_WIDTH_18BIT (2 << 10) + #define LCDIF_CTRL_LCD_DATABUS_WIDTH_24BIT (3 << 10) + #define LCDIF_CTRL_WORD_LENGTH_MASK (0x3 << 8) + #define LCDIF_CTRL_WORD_LENGTH_OFFSET 8 + #define LCDIF_CTRL_WORD_LENGTH_16BIT (0 << 8) + #define LCDIF_CTRL_WORD_LENGTH_8BIT (1 << 8) + #define LCDIF_CTRL_WORD_LENGTH_18BIT (2 << 8) + #define LCDIF_CTRL_WORD_LENGTH_24BIT (3 << 8) + #define LCDIF_CTRL_RGB_TO_YCBCR422_CSC (1 << 7) + #define LCDIF_CTRL_LCDIF_MASTER (1 << 5) + #define LCDIF_CTRL_DATA_FORMAT_16_BIT (1 << 3) + #define LCDIF_CTRL_DATA_FORMAT_18_BIT (1 << 2) + #define LCDIF_CTRL_DATA_FORMAT_24_BIT (1 << 1) + #define LCDIF_CTRL_RUN (1 << 0) + + #define LCDIF_CTRL1_COMBINE_MPU_WR_STRB (1 << 27) + #define LCDIF_CTRL1_BM_ERROR_IRQ_EN (1 << 26) + #define LCDIF_CTRL1_BM_ERROR_IRQ (1 << 25) + #define LCDIF_CTRL1_RECOVER_ON_UNDERFLOW (1 << 24) + #define LCDIF_CTRL1_INTERLACE_FIELDS (1 << 23) + #define LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD (1 << 22) + #define LCDIF_CTRL1_FIFO_CLEAR (1 << 21) + #define LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS (1 << 20) + #define LCDIF_CTRL1_BYTE_PACKING_FORMAT_MASK (0xf << 16) + #define LCDIF_CTRL1_BYTE_PACKING_FORMAT_OFFSET 16 ++#define LCDIF_CTRL1_BYTE_PACKING_FORMAT(n) (((n) << LCDIF_CTRL1_BYTE_PACKING_FORMAT_OFFSET) & \ ++ LCDIF_CTRL1_BYTE_PACKING_FORMAT_MASK) + #define LCDIF_CTRL1_OVERFLOW_IRQ_EN (1 << 15) + #define LCDIF_CTRL1_UNDERFLOW_IRQ_EN (1 << 14) + #define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN (1 << 13) + #define LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN (1 << 12) + #define LCDIF_CTRL1_OVERFLOW_IRQ (1 << 11) + #define LCDIF_CTRL1_UNDERFLOW_IRQ (1 << 10) + #define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ (1 << 9) + #define LCDIF_CTRL1_VSYNC_EDGE_IRQ (1 << 8) + #define LCDIF_CTRL1_BUSY_ENABLE (1 << 2) + #define LCDIF_CTRL1_MODE86 (1 << 1) + #define LCDIF_CTRL1_RESET (1 << 0) + + #define LCDIF_CTRL2_OUTSTANDING_REQS_MASK (0x7 << 21) + #define LCDIF_CTRL2_OUTSTANDING_REQS_OFFSET 21 + #define LCDIF_CTRL2_OUTSTANDING_REQS_REQ_1 (0x0 << 21) + #define LCDIF_CTRL2_OUTSTANDING_REQS_REQ_2 (0x1 << 21) + #define LCDIF_CTRL2_OUTSTANDING_REQS_REQ_4 (0x2 << 21) + #define LCDIF_CTRL2_OUTSTANDING_REQS_REQ_8 (0x3 << 21) + #define LCDIF_CTRL2_OUTSTANDING_REQS_REQ_16 (0x4 << 21) + #define LCDIF_CTRL2_BURST_LEN_8 (1 << 20) + #define LCDIF_CTRL2_ODD_LINE_PATTERN_MASK (0x7 << 16) + #define LCDIF_CTRL2_ODD_LINE_PATTERN_OFFSET 16 + #define LCDIF_CTRL2_ODD_LINE_PATTERN_RGB (0x0 << 16) + #define LCDIF_CTRL2_ODD_LINE_PATTERN_RBG (0x1 << 16) + #define LCDIF_CTRL2_ODD_LINE_PATTERN_GBR (0x2 << 16) + #define LCDIF_CTRL2_ODD_LINE_PATTERN_GRB (0x3 << 16) + #define LCDIF_CTRL2_ODD_LINE_PATTERN_BRG (0x4 << 16) + #define LCDIF_CTRL2_ODD_LINE_PATTERN_BGR (0x5 << 16) + #define LCDIF_CTRL2_EVEN_LINE_PATTERN_MASK (0x7 << 12) + #define LCDIF_CTRL2_EVEN_LINE_PATTERN_OFFSET 12 + #define LCDIF_CTRL2_EVEN_LINE_PATTERN_RGB (0x0 << 12) + #define LCDIF_CTRL2_EVEN_LINE_PATTERN_RBG (0x1 << 12) + #define LCDIF_CTRL2_EVEN_LINE_PATTERN_GBR (0x2 << 12) + #define LCDIF_CTRL2_EVEN_LINE_PATTERN_GRB (0x3 << 12) + #define LCDIF_CTRL2_EVEN_LINE_PATTERN_BRG (0x4 << 12) + #define LCDIF_CTRL2_EVEN_LINE_PATTERN_BGR (0x5 << 12) + #define LCDIF_CTRL2_READ_PACK_DIR (1 << 10) + #define LCDIF_CTRL2_READ_MODE_OUTPUT_IN_RGB_FORMAT (1 << 9) + #define LCDIF_CTRL2_READ_MODE_6_BIT_INPUT (1 << 8) + #define LCDIF_CTRL2_READ_MODE_NUM_PACKED_SUBWORDS_MASK (0x7 << 4) + #define LCDIF_CTRL2_READ_MODE_NUM_PACKED_SUBWORDS_OFFSET 4 + #define LCDIF_CTRL2_INITIAL_DUMMY_READ_MASK (0x7 << 1) + #define LCDIF_CTRL2_INITIAL_DUMMY_READ_OFFSET 1 + + #define LCDIF_TRANSFER_COUNT_V_COUNT_MASK (0xffff << 16) + #define LCDIF_TRANSFER_COUNT_V_COUNT_OFFSET 16 ++#define LCDIF_TRANSFER_COUNT_V_COUNT(n) (((n) << LCDIF_TRANSFER_COUNT_V_COUNT_OFFSET) & \ ++ LCDIF_TRANSFER_COUNT_V_COUNT_MASK) + #define LCDIF_TRANSFER_COUNT_H_COUNT_MASK (0xffff << 0) + #define LCDIF_TRANSFER_COUNT_H_COUNT_OFFSET 0 ++#define LCDIF_TRANSFER_COUNT_H_COUNT(n) (((n) << LCDIF_TRANSFER_COUNT_H_COUNT_OFFSET) & \ ++ LCDIF_TRANSFER_COUNT_H_COUNT_MASK) + + #define LCDIF_CUR_BUF_ADDR_MASK 0xffffffff + #define LCDIF_CUR_BUF_ADDR_OFFSET 0 + + #define LCDIF_NEXT_BUF_ADDR_MASK 0xffffffff + #define LCDIF_NEXT_BUF_ADDR_OFFSET 0 + + #define LCDIF_TIMING_CMD_HOLD_MASK (0xff << 24) + #define LCDIF_TIMING_CMD_HOLD_OFFSET 24 + #define LCDIF_TIMING_CMD_SETUP_MASK (0xff << 16) + #define LCDIF_TIMING_CMD_SETUP_OFFSET 16 + #define LCDIF_TIMING_DATA_HOLD_MASK (0xff << 8) + #define LCDIF_TIMING_DATA_HOLD_OFFSET 8 + #define LCDIF_TIMING_DATA_SETUP_MASK (0xff << 0) + #define LCDIF_TIMING_DATA_SETUP_OFFSET 0 + + #define LCDIF_VDCTRL0_VSYNC_OEB (1 << 29) + #define LCDIF_VDCTRL0_ENABLE_PRESENT (1 << 28) + #define LCDIF_VDCTRL0_VSYNC_POL (1 << 27) + #define LCDIF_VDCTRL0_HSYNC_POL (1 << 26) + #define LCDIF_VDCTRL0_DOTCLK_POL (1 << 25) + #define LCDIF_VDCTRL0_ENABLE_POL (1 << 24) + #define LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT (1 << 21) + #define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT (1 << 20) + #define LCDIF_VDCTRL0_HALF_LINE (1 << 19) + #define LCDIF_VDCTRL0_HALF_LINE_MODE (1 << 18) + #define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_MASK 0x3ffff + #define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_OFFSET 0 ++#define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH(n) (((n) << LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_OFFSET) & \ ++ LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_MASK) + + #define LCDIF_VDCTRL1_VSYNC_PERIOD_MASK 0xffffffff + #define LCDIF_VDCTRL1_VSYNC_PERIOD_OFFSET 0 ++#define LCDIF_VDCTRL1_VSYNC_PERIOD(n) (((n) << LCDIF_VDCTRL1_VSYNC_PERIOD_OFFSET) & \ ++ LCDIF_VDCTRL1_VSYNC_PERIOD_MASK) + + #define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_MASK (0x3fff << 18) + #define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_OFFSET 18 ++#define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH(n) (((n) << LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_OFFSET) & \ ++ LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_MASK) + #define LCDIF_VDCTRL2_HSYNC_PERIOD_MASK 0x3ffff + #define LCDIF_VDCTRL2_HSYNC_PERIOD_OFFSET 0 ++#define LCDIF_VDCTRL2_HSYNC_PERIOD(n) (((n) << LCDIF_VDCTRL2_HSYNC_PERIOD_OFFSET) & \ ++ LCDIF_VDCTRL2_HSYNC_PERIOD_MASK) + + #define LCDIF_VDCTRL3_MUX_SYNC_SIGNALS (1 << 29) + #define LCDIF_VDCTRL3_VSYNC_ONLY (1 << 28) + #define LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_MASK (0xfff << 16) + #define LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_OFFSET 16 ++#define LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT(n) (((n) << LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_OFFSET) & \ ++ LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_MASK) + #define LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_MASK (0xffff << 0) + #define LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_OFFSET 0 ++#define LCDIF_VDCTRL3_VERTICAL_WAIT_CNT(n) (((n) << LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_OFFSET) & \ ++ LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_MASK) + + #define LCDIF_VDCTRL4_DOTCLK_DLY_SEL_MASK (0x7 << 29) + #define LCDIF_VDCTRL4_DOTCLK_DLY_SEL_OFFSET 29 ++#define LCDIF_VDCTRL4_DOTCLK_DLY_SEL(n) (((n) << LCDIF_VDCTRL4_DOTCLK_DLY_SEL_OFFSET) & \ ++ LCDIF_VDCTRL4_DOTCLK_DLY_SEL_MASK) + #define LCDIF_VDCTRL4_SYNC_SIGNALS_ON (1 << 18) + #define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_MASK 0x3ffff + #define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_OFFSET 0 ++#define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT(n) (((n) << LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_OFFSET) & \ ++ LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_MASK) + + #endif /* __MX28_REGS_LCDIF_H__ */ diff --cc arch/arm/include/asm/arch-mxs/sys_proto.h index e701c6409e,9bddc12d4d..e277379df0 --- a/arch/arm/include/asm/arch-mxs/sys_proto.h +++ b/arch/arm/include/asm/arch-mxs/sys_proto.h @@@ -20,22 -20,22 +20,26 @@@ * */ - #ifndef __MX28_H__ - #define __MX28_H__ + #ifndef __SYS_PROTO_H__ + #define __SYS_PROTO_H__ - int mx28_reset_block(struct mx28_register_32 *reg); - int mx28_wait_mask_set(struct mx28_register_32 *reg, ++struct mxs_register_32; ++ + int mxs_reset_block(struct mxs_register_32 *reg); + int mxs_wait_mask_set(struct mxs_register_32 *reg, uint32_t mask, - int timeout); - int mx28_wait_mask_clr(struct mx28_register_32 *reg, + unsigned int timeout); + int mxs_wait_mask_clr(struct mxs_register_32 *reg, uint32_t mask, - int timeout); + unsigned int timeout); int mxsmmc_initialize(bd_t *bis, int id, int (*wp)(int)); ++void imx_get_mac_from_fuse(int dev_id, unsigned char *mac); ++ #ifdef CONFIG_SPL_BUILD #include - void mx28_common_spl_init(const iomux_cfg_t *iomux_setup, + void mxs_common_spl_init(const iomux_cfg_t *iomux_setup, const unsigned int iomux_size); #endif diff --cc arch/arm/include/asm/global_data.h index c3ff789999,37ac0daa70..b4bdcd95ea --- a/arch/arm/include/asm/global_data.h +++ b/arch/arm/include/asm/global_data.h @@@ -23,30 -23,12 +23,15 @@@ #ifndef __ASM_GBL_DATA_H #define __ASM_GBL_DATA_H - /* - * The following data structure is placed in some memory which is - * available very early after boot (like DPRAM on MPC8xx/MPC82xx, or - * some locked parts of the data cache) to allow for a minimum set of - * global variables during system initialization (until we have set - * up the memory controller so that we can use RAM). - * - * Keep it *SMALL* and remember to set GENERATED_GBL_DATA_SIZE > sizeof(gd_t) - */ - typedef struct global_data { - bd_t *bd; - unsigned long flags; - unsigned long baudrate; - unsigned long have_console; /* serial_init() was called */ - #ifdef CONFIG_PRE_CONSOLE_BUFFER - unsigned long precon_buf_idx; /* Pre-Console buffer index */ + /* Architecture-specific global data */ + struct arch_global_data { + #if defined(CONFIG_FSL_ESDHC) + u32 sdhc_clk; #endif - unsigned long env_addr; /* Address of Environment struct */ - unsigned long env_valid; /* Checksum of Environment valid? */ - unsigned long fb_base; /* base address of frame buffer */ - #ifdef CONFIG_FSL_ESDHC - unsigned long sdhc_clk; ++#ifdef CONFIG_VIDEO_IPUV3 ++ unsigned int ipu_hw_rev; +#endif #ifdef CONFIG_AT91FAMILY /* "static data" needed by at91's clock.c */ unsigned long cpu_clk_rate_hz; diff --cc arch/arm/include/asm/imx-common/iomux-v3.h index 0000000000,c34bb76ad4..860c8cfe46 mode 000000,100644..100644 --- a/arch/arm/include/asm/imx-common/iomux-v3.h +++ b/arch/arm/include/asm/imx-common/iomux-v3.h @@@ -1,0 -1,104 +1,107 @@@ + /* + * Based on Linux i.MX iomux-v3.h file: + * Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH, + * + * + * Copyright (C) 2011 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301, USA. + */ + -#ifndef __MACH_IOMUX_V3_H__ -#define __MACH_IOMUX_V3_H__ ++#ifndef __ASM_ARCH_IOMUX_V3_H__ ++#define __ASM_ARCH_IOMUX_V3_H__ + + /* + * build IOMUX_PAD structure + * + * This iomux scheme is based around pads, which are the physical balls + * on the processor. + * + * - Each pad has a pad control register (IOMUXC_SW_PAD_CTRL_x) which controls + * things like driving strength and pullup/pulldown. + * - Each pad can have but not necessarily does have an output routing register + * (IOMUXC_SW_MUX_CTL_PAD_x). + * - Each pad can have but not necessarily does have an input routing register + * (IOMUXC_x_SELECT_INPUT) + * + * The three register sets do not have a fixed offset to each other, + * hence we order this table by pad control registers (which all pads + * have) and put the optional i/o routing registers into additional + * fields. + * + * The naming convention for the pad modes is SOC_PAD___ + * If or refers to a GPIO, it is named GPIO__ + * + * IOMUX/PAD Bit field definitions + * + * MUX_CTRL_OFS: 0..11 (12) + * PAD_CTRL_OFS: 12..23 (12) + * SEL_INPUT_OFS: 24..35 (12) + * MUX_MODE + SION: 36..40 (5) - * PAD_CTRL + NO_PAD_CTRL: 41..58 (18) ++ * PAD_CTRL + PAD_CTRL_VALID: 41..58 (18) + * SEL_INP: 59..62 (4) + * reserved: 63 (1) + */ + + typedef u64 iomux_v3_cfg_t; + + #define MUX_CTRL_OFS_SHIFT 0 + #define MUX_CTRL_OFS_MASK ((iomux_v3_cfg_t)0xfff << MUX_CTRL_OFS_SHIFT) + #define MUX_PAD_CTRL_OFS_SHIFT 12 + #define MUX_PAD_CTRL_OFS_MASK ((iomux_v3_cfg_t)0xfff << \ + MUX_PAD_CTRL_OFS_SHIFT) + #define MUX_SEL_INPUT_OFS_SHIFT 24 + #define MUX_SEL_INPUT_OFS_MASK ((iomux_v3_cfg_t)0xfff << \ + MUX_SEL_INPUT_OFS_SHIFT) + + #define MUX_MODE_SHIFT 36 + #define MUX_MODE_MASK ((iomux_v3_cfg_t)0x1f << MUX_MODE_SHIFT) + #define MUX_PAD_CTRL_SHIFT 41 + #define MUX_PAD_CTRL_MASK ((iomux_v3_cfg_t)0x3ffff << MUX_PAD_CTRL_SHIFT) + #define MUX_SEL_INPUT_SHIFT 59 + #define MUX_SEL_INPUT_MASK ((iomux_v3_cfg_t)0xf << MUX_SEL_INPUT_SHIFT) + -#define MUX_PAD_CTRL(x) ((iomux_v3_cfg_t)(x) << MUX_PAD_CTRL_SHIFT) ++#define MUX_PAD_CTRL(x) (((iomux_v3_cfg_t)(x) << MUX_PAD_CTRL_SHIFT) | \ ++ PAD_CTRL_VALID) + + #define IOMUX_PAD(pad_ctrl_ofs, mux_ctrl_ofs, mux_mode, sel_input_ofs, \ + sel_input, pad_ctrl) \ + (((iomux_v3_cfg_t)(mux_ctrl_ofs) << MUX_CTRL_OFS_SHIFT) | \ + ((iomux_v3_cfg_t)(mux_mode) << MUX_MODE_SHIFT) | \ + ((iomux_v3_cfg_t)(pad_ctrl_ofs) << MUX_PAD_CTRL_OFS_SHIFT) | \ + ((iomux_v3_cfg_t)(pad_ctrl) << MUX_PAD_CTRL_SHIFT) | \ + ((iomux_v3_cfg_t)(sel_input_ofs) << MUX_SEL_INPUT_OFS_SHIFT)| \ + ((iomux_v3_cfg_t)(sel_input) << MUX_SEL_INPUT_SHIFT)) + + #define NO_PAD_CTRL (1 << 17) + #define GPIO_PIN_MASK 0x1f ++#define PAD_CTRL_VALID ((iomux_v3_cfg_t)1 << (MUX_PAD_CTRL_SHIFT + 17)) + #define GPIO_PORT_SHIFT 5 + #define GPIO_PORT_MASK (0x7 << GPIO_PORT_SHIFT) + #define GPIO_PORTA (0 << GPIO_PORT_SHIFT) + #define GPIO_PORTB (1 << GPIO_PORT_SHIFT) + #define GPIO_PORTC (2 << GPIO_PORT_SHIFT) + #define GPIO_PORTD (3 << GPIO_PORT_SHIFT) + #define GPIO_PORTE (4 << GPIO_PORT_SHIFT) + #define GPIO_PORTF (5 << GPIO_PORT_SHIFT) + + #define MUX_CONFIG_SION (0x1 << 4) + ++ + int imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad); + int imx_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t const *pad_list, + unsigned count); + -#endif /* __MACH_IOMUX_V3_H__*/ ++#endif /* __ASM_ARCH_IOMUX_V3_H__*/ diff --cc arch/arm/lib/board.c index 5270c11262,162e2cc863..4b60a10d2f --- a/arch/arm/lib/board.c +++ b/arch/arm/lib/board.c @@@ -144,7 -138,7 +138,7 @@@ static int display_banner(void * has the disadvantage that you either get nothing, or everything. * On PowerPC, you might see "DRAM: " before the system hangs - which * gives a simple yet clear indication which part of the -- * initialization if failing. ++ * initialization is failing. */ static int display_dram_config(void) { @@@ -432,12 -462,12 +462,13 @@@ void board_init_f(ulong bootflag gd->relocaddr = addr; gd->start_addr_sp = addr_sp; gd->reloc_off = addr - _TEXT_BASE; ++ debug("relocation Offset is: %08lx\n", gd->reloc_off); + if (new_fdt) { + memcpy(new_fdt, gd->fdt_blob, fdt_size); + gd->fdt_blob = new_fdt; + } memcpy(id, (void *)gd, sizeof(gd_t)); - - relocate_code(addr_sp, id, addr); - - /* NOTREACHED - relocate_code() does not return */ } #if !defined(CONFIG_SYS_NO_FLASH) @@@ -475,7 -534,7 +535,7 @@@ void board_init_r(gd_t *id, ulong dest_ debug("monitor flash len: %08lX\n", monitor_flash_len); board_init(); /* Setup chipselects */ /* -- * TODO: printing of the clock inforamtion of the board is now ++ * TODO: printing of the clock information of the board is now * implemented as part of bdinfo command. Currently only support for * davinci SOC's is added. Remove this check once all the board * implement this. diff --cc arch/arm/lib/cache-cp15.c index a69c5f6649,b6e5e95530..0ab08b2c4d --- a/arch/arm/lib/cache-cp15.c +++ b/arch/arm/lib/cache-cp15.c @@@ -39,9 -34,51 +34,41 @@@ void __arm_init_before_mmu(void void arm_init_before_mmu(void) __attribute__((weak, alias("__arm_init_before_mmu"))); -static void cp_delay (void) -{ - volatile int i; - - /* copro seems to need some delay between reading and writing */ - for (i = 0; i < 100; i++) - nop(); - asm volatile("" : : : "memory"); -} - + void set_section_dcache(int section, enum dcache_option option) + { + u32 *page_table = (u32 *)gd->arch.tlb_addr; + u32 value; + + value = (section << MMU_SECTION_SHIFT) | (3 << 10); + value |= option; + page_table[section] = value; + } + + void __mmu_page_table_flush(unsigned long start, unsigned long stop) + { + debug("%s: Warning: not implemented\n", __func__); + } + + void mmu_page_table_flush(unsigned long start, unsigned long stop) + __attribute__((weak, alias("__mmu_page_table_flush"))); + + void mmu_set_region_dcache_behaviour(u32 start, int size, + enum dcache_option option) + { + u32 *page_table = (u32 *)gd->arch.tlb_addr; + u32 upto, end; + + end = ALIGN(start + size, MMU_SECTION_SIZE) >> MMU_SECTION_SHIFT; + start = start >> MMU_SECTION_SHIFT; + debug("%s: start=%x, size=%x, option=%d\n", __func__, start, size, + option); + for (upto = start; upto < end; upto++) + set_section_dcache(upto, option); + mmu_page_table_flush((u32)&page_table[start], (u32)&page_table[end]); + } + static inline void dram_bank_mmu_setup(int bank) { - u32 *page_table = (u32 *)gd->tlb_addr; bd_t *bd = gd->bd; int i; @@@ -56,7 -97,6 +87,7 @@@ /* to activate the MMU we need to set up virtual memory: use 1M areas */ static inline void mmu_setup(void) { - u32 *page_table = (u32 *)gd->tlb_addr; ++ u32 *page_table = (u32 *)gd->arch.tlb_addr; int i; u32 reg; @@@ -104,16 -144,20 +135,18 @@@ static void cache_disable(uint32_t cach { uint32_t reg; + reg = get_cr(); - cp_delay(); + if (cache_bit == CR_C) { /* if cache isn;t enabled no need to disable */ - reg = get_cr(); if ((reg & CR_C) != CR_C) return; /* if disabling data cache, disable mmu too */ cache_bit |= CR_M; - flush_dcache_all(); } reg = get_cr(); - cp_delay(); + if (cache_bit == (CR_C | CR_M)) + flush_dcache_all(); set_cr(reg & ~cache_bit); } #endif diff --cc board/denx/m28evk/spl_boot.c index fa48c16906,49e8a75c1c..e33cc0b8bb --- a/board/denx/m28evk/spl_boot.c +++ b/board/denx/m28evk/spl_boot.c @@@ -218,55 -218,5 +218,55 @@@ const iomux_cfg_t iomux_setup[] = void board_init_ll(void) { - mx28_common_spl_init(iomux_setup, ARRAY_SIZE(iomux_setup)); + mxs_common_spl_init(iomux_setup, ARRAY_SIZE(iomux_setup)); } + +static uint32_t dram_vals[] = { + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000100, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00010101, 0x01010101, 0x000f0f01, 0x0f02020a, + 0x00000000, 0x00010101, 0x00000100, 0x00000100, 0x00000000, + 0x00000002, 0x01010000, 0x05060302, 0x06005003, 0x0a0000c8, + 0x02009c40, 0x0000030c, 0x0036a609, 0x031a0612, 0x02030202, + 0x00c8001c, 0x00000000, 0x00000000, 0x00012100, 0xffff0303, + 0x00012100, 0xffff0303, 0x00012100, 0xffff0303, 0x00012100, + 0xffff0303, 0x00000003, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000612, 0x01000F02, 0x06120612, 0x00000200, + 0x00020007, 0xf5014b27, 0xf5014b27, 0xf5014b27, 0xf5014b27, + 0x07000300, 0x07000300, 0x07000300, 0x07000300, 0x00000006, + 0x00000000, 0x00000000, 0x01000000, 0x01020408, 0x08040201, + 0x000f1133, 0x00000000, 0x00001f04, 0x00001f04, 0x00001f04, + 0x00001f04, 0x00001f04, 0x00001f04, 0x00001f04, 0x00001f04, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00010000, 0x00020304, 0x00000004, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x01010000, 0x01000000, 0x03030000, 0x00010303, + 0x01020202, 0x00000000, 0x02040303, 0x21002103, 0x00061200, + 0x06120612, 0x04320432, 0x04320432, 0x00040004, 0x00040004, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00010001 +}; + +void mx28_ddr2_setup(void) +{ + int i; + + serial_puts("\n"); + for (i = 0; i < ARRAY_SIZE(dram_vals); i++) + writel(dram_vals[i], MXS_DRAM_BASE + (4 * i)); +} diff --cc board/karo/dts/tx6q.dts index 0000000000,0000000000..9b80fa6cac new file mode 100644 --- /dev/null +++ b/board/karo/dts/tx6q.dts @@@ -1,0 -1,0 +1,62 @@@ ++/* ++ * Copyright 2012 Freescale Semiconductor, Inc. ++ * Copyright 2011 Linaro Ltd. ++ * ++ * The code contained herein is licensed under the GNU General Public ++ * License. You may obtain a copy of the GNU General Public License ++ * Version 2 or later at the following locations: ++ * ++ * http://www.opensource.org/licenses/gpl-license.html ++ * http://www.gnu.org/copyleft/gpl.html ++ */ ++ ++/dts-v1/; ++/include/ ARCH_CPU_DTS ++ ++/ { ++ model = "Ka-Ro TX6Q module"; ++ compatible = "karo,imx6q-tx6q", "fsl,imx6q"; ++ ++ memory { ++ reg = <0 0>; /* filled in by U-Boot */ ++ }; ++}; ++ ++&uart1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_uart1_3 &pinctrl_uart1_4>; ++ status = "okay"; ++}; ++ ++&uart2 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_uart2_5 &pinctrl_uart2_6>; ++ status = "okay"; ++}; ++ ++&uart3 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_uart3_1 &pinctrl_uart3_4>; ++ status = "okay"; ++}; ++ ++&fec { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_enet_1>; ++ phy-mode = "rmii"; ++ status = "okay"; ++}; ++ ++&usdhc1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_usdhc1_2>; ++ cd-gpios = <&gpio7 2 0>; ++ status = "okay"; ++}; ++ ++&usdhc2 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_usdhc2_2>; ++ cd-gpios = <&gpio7 3 0>; ++ status = "okay"; ++}; diff --cc board/karo/tx28/flash.c index 376e6b480b,0000000000..2b725ed3ec mode 100644,000000..100644 --- a/board/karo/tx28/flash.c +++ b/board/karo/tx28/flash.c @@@ -1,592 -1,0 +1,590 @@@ +#include +#include +#include +#include + +#include + +#include +#include +#include +#include +#include + +#define FCB_START_BLOCK 0 +#define NUM_FCB_BLOCKS 1 +#define MAX_FCB_BLOCKS 32768 + +struct mx28_nand_timing { + u8 data_setup; + u8 data_hold; + u8 address_setup; + u8 dsample_time; + u8 nand_timing_state; + u8 tREA; + u8 tRLOH; + u8 tRHOH; +}; + +struct mx28_fcb { + u32 checksum; + u32 fingerprint; + u32 version; + struct mx28_nand_timing timing; + u32 page_data_size; + u32 total_page_size; + u32 sectors_per_block; + u32 number_of_nands; /* not used by ROM code */ + u32 total_internal_die; /* not used by ROM code */ + u32 cell_type; /* not used by ROM code */ + u32 ecc_blockn_type; + u32 ecc_block0_size; + u32 ecc_blockn_size; + u32 ecc_block0_type; + u32 metadata_size; + u32 ecc_blocks_per_page; + u32 rsrvd[6]; /* not used by ROM code */ + u32 bch_mode; + u32 boot_patch; + u32 patch_sectors; + u32 fw1_start_page; + u32 fw2_start_page; + u32 fw1_sectors; + u32 fw2_sectors; + u32 dbbt_search_area; + u32 bb_mark_byte; + u32 bb_mark_startbit; + u32 bb_mark_phys_offset; +}; + +struct mx28_dbbt_header { + u32 checksum; + u32 fingerprint; + u32 version; + u32 number_bb; + u32 number_pages; + u8 spare[492]; +}; + +struct mx28_dbbt { + u32 nand_number; + u32 number_bb; + u32 bb_num[2040 / 4]; +}; + +#define BF_VAL(v, bf) (((v) & bf##_MASK) >> bf##_OFFSET) + +static nand_info_t *mtd = &nand_info[0]; + +extern void *_start; + +#define BIT(v,n) (((v) >> (n)) & 0x1) + +static u8 calculate_parity_13_8(u8 d) +{ + u8 p = 0; + + p |= (BIT(d, 6) ^ BIT(d, 5) ^ BIT(d, 3) ^ BIT(d, 2)) << 0; + p |= (BIT(d, 7) ^ BIT(d, 5) ^ BIT(d, 4) ^ BIT(d, 2) ^ BIT(d, 1)) << 1; + p |= (BIT(d, 7) ^ BIT(d, 6) ^ BIT(d, 5) ^ BIT(d, 1) ^ BIT(d, 0)) << 2; + p |= (BIT(d, 7) ^ BIT(d, 4) ^ BIT(d, 3) ^ BIT(d, 0)) << 3; + p |= (BIT(d, 6) ^ BIT(d, 4) ^ BIT(d, 3) ^ BIT(d, 2) ^ BIT(d, 1) ^ BIT(d, 0)) << 4; + return p; +} + +static void encode_hamming_13_8(void *_src, void *_ecc, size_t size) +{ + int i; + u8 *src = _src; + u8 *ecc = _ecc; + + for (i = 0; i < size; i++) + ecc[i] = calculate_parity_13_8(src[i]); +} + +static u32 calc_chksum(void *buf, size_t size) +{ + u32 chksum = 0; + u8 *bp = buf; + size_t i; + + for (i = 0; i < size; i++) { + chksum += bp[i]; + } + return ~chksum; +} + +/* + Physical organisation of data in NAND flash: + metadata + payload chunk 0 (may be empty) + ecc for metadata + payload chunk 0 + payload chunk 1 + ecc for payload chunk 1 +... + payload chunk n + ecc for payload chunk n + */ + +static int calc_bb_offset(nand_info_t *mtd, struct mx28_fcb *fcb) +{ + int bb_mark_offset; + int chunk_data_size = fcb->ecc_blockn_size * 8; + int chunk_ecc_size = (fcb->ecc_blockn_type << 1) * 13; + int chunk_total_size = chunk_data_size + chunk_ecc_size; + int bb_mark_chunk, bb_mark_chunk_offs; + + bb_mark_offset = (mtd->writesize - fcb->metadata_size) * 8; + if (fcb->ecc_block0_size == 0) + bb_mark_offset -= (fcb->ecc_block0_type << 1) * 13; + + bb_mark_chunk = bb_mark_offset / chunk_total_size; + bb_mark_chunk_offs = bb_mark_offset - (bb_mark_chunk * chunk_total_size); + if (bb_mark_chunk_offs > chunk_data_size) { + printf("Unsupported ECC layout; BB mark resides in ECC data: %u\n", + bb_mark_chunk_offs); + return -EINVAL; + } + bb_mark_offset -= bb_mark_chunk * chunk_ecc_size; + return bb_mark_offset; +} + +static struct mx28_fcb *create_fcb(void *buf, int fw1_start_block, + int fw2_start_block, size_t fw_size) +{ - struct mx28_gpmi_regs *gpmi_base = - (struct mx28_gpmi_regs *)MXS_GPMI_BASE; - struct mx28_bch_regs *bch_base = - (struct mx28_bch_regs *)MXS_BCH_BASE; ++ struct gpmi_regs *gpmi_base = (void *)GPMI_BASE_ADDRESS; ++ struct bch_regs *bch_base = (void *)BCH_BASE_ADDRESS; + u32 fl0, fl1; + u32 t0, t1; + int metadata_size; + int bb_mark_bit_offs; + struct mx28_fcb *fcb; + int fcb_offs; + + if (gpmi_base == NULL || bch_base == NULL) { + return ERR_PTR(-ENOMEM); + } + + fl0 = readl(&bch_base->hw_bch_flash0layout0); + fl1 = readl(&bch_base->hw_bch_flash0layout1); + t0 = readl(&gpmi_base->hw_gpmi_timing0); + t1 = readl(&gpmi_base->hw_gpmi_timing1); + + metadata_size = BF_VAL(fl0, BCH_FLASHLAYOUT0_META_SIZE); + + fcb = buf + ALIGN(metadata_size, 4); + fcb_offs = (void *)fcb - buf; + + memset(buf, 0xff, fcb_offs); + memset(fcb, 0x00, sizeof(*fcb)); + memset(fcb + 1, 0xff, mtd->erasesize - fcb_offs - sizeof(*fcb)); + + strncpy((char *)&fcb->fingerprint, "FCB ", 4); + fcb->version = cpu_to_be32(1); + + fcb->timing.data_setup = BF_VAL(t0, GPMI_TIMING0_DATA_SETUP); + fcb->timing.data_hold = BF_VAL(t0, GPMI_TIMING0_DATA_HOLD); + fcb->timing.address_setup = BF_VAL(t0, GPMI_TIMING0_ADDRESS_SETUP); + + fcb->page_data_size = mtd->writesize; + fcb->total_page_size = mtd->writesize + mtd->oobsize; + fcb->sectors_per_block = mtd->erasesize / mtd->writesize; + + fcb->ecc_block0_type = BF_VAL(fl0, BCH_FLASHLAYOUT0_ECC0); + fcb->ecc_block0_size = BF_VAL(fl0, BCH_FLASHLAYOUT0_DATA0_SIZE); + fcb->ecc_blockn_type = BF_VAL(fl1, BCH_FLASHLAYOUT1_ECCN); + fcb->ecc_blockn_size = BF_VAL(fl1, BCH_FLASHLAYOUT1_DATAN_SIZE); + + fcb->metadata_size = BF_VAL(fl0, BCH_FLASHLAYOUT0_META_SIZE); + fcb->ecc_blocks_per_page = BF_VAL(fl0, BCH_FLASHLAYOUT0_NBLOCKS); + fcb->bch_mode = readl(&bch_base->hw_bch_mode); +/* + fcb->boot_patch = 0; + fcb->patch_sectors = 0; +*/ + fcb->fw1_start_page = fw1_start_block * mtd->erasesize / mtd->writesize; + fcb->fw1_sectors = DIV_ROUND_UP(fw_size, mtd->writesize); + + if (fw2_start_block != 0 && fw2_start_block < mtd->size / mtd->erasesize) { + fcb->fw2_start_page = fw2_start_block * mtd->erasesize / mtd->writesize; + fcb->fw2_sectors = fcb->fw1_sectors; + } + + fcb->dbbt_search_area = 1; + + bb_mark_bit_offs = calc_bb_offset(mtd, fcb); + if (bb_mark_bit_offs < 0) + return ERR_PTR(bb_mark_bit_offs); + fcb->bb_mark_byte = bb_mark_bit_offs / 8; + fcb->bb_mark_startbit = bb_mark_bit_offs % 8; + fcb->bb_mark_phys_offset = mtd->writesize; + + fcb->checksum = calc_chksum(&fcb->fingerprint, 512 - 4); + return fcb; +} + +static int find_fcb(void *ref, int page) +{ + int ret = 0; + struct nand_chip *chip = mtd->priv; + void *buf = malloc(mtd->erasesize); + + if (buf == NULL) { + return -ENOMEM; + } + chip->select_chip(mtd, 0); + chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page); + ret = chip->ecc.read_page_raw(mtd, chip, buf, page); + if (ret) { + printf("Failed to read FCB from page %u: %d\n", page, ret); + return ret; + } + chip->select_chip(mtd, -1); + if (memcmp(buf, ref, mtd->writesize) == 0) { + printf("%s: Found FCB in page %u (%08x)\n", __func__, + page, page * mtd->writesize); + ret = 1; + } + free(buf); + return ret; +} + +static int write_fcb(void *buf, int block) +{ + int ret; + struct nand_chip *chip = mtd->priv; + int page = block * mtd->erasesize / mtd->writesize; + + ret = find_fcb(buf, page); + if (ret > 0) { + printf("FCB at block %d is up to date\n", block); + return 0; + } + + ret = nand_erase(mtd, block * mtd->erasesize, mtd->erasesize); + if (ret) { + printf("Failed to erase FCB block %u\n", block); + return ret; + } + + printf("Writing FCB to block %d @ %08x\n", block, + block * mtd->erasesize); + chip->select_chip(mtd, 0); + ret = chip->write_page(mtd, chip, buf, page, 0, 1); + if (ret) { + printf("Failed to write FCB to block %u: %d\n", block, ret); + } + chip->select_chip(mtd, -1); + return ret; +} + +#define chk_overlap(a,b) \ + ((a##_start_block <= b##_end_block && \ + a##_end_block >= b##_start_block) || \ + (b##_start_block <= a##_end_block && \ + b##_end_block >= a##_start_block)) + +#define fail_if_overlap(a,b,m1,m2) do { \ + if (chk_overlap(a, b)) { \ + printf("%s blocks %lu..%lu overlap %s in blocks %lu..%lu!\n", \ + m1, a##_start_block, a##_end_block, \ + m2, b##_start_block, b##_end_block); \ + return -EINVAL; \ + } \ +} while (0) + +#ifndef CONFIG_ENV_OFFSET_REDUND +#define TOTAL_ENV_SIZE CONFIG_ENV_SIZE +#else +#define TOTAL_ENV_SIZE (CONFIG_ENV_SIZE * 2) +#endif + +int do_update(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + int ret; + int block; + int erase_size = mtd->erasesize; + int page_size = mtd->writesize; + void *buf; + char *load_addr; + char *file_size; + size_t size = 0; + void *addr = NULL; + struct mx28_fcb *fcb; + unsigned long fcb_start_block = FCB_START_BLOCK; + unsigned long num_fcb_blocks = NUM_FCB_BLOCKS; + unsigned long fcb_end_block; + unsigned long mtd_num_blocks = mtd->size / mtd->erasesize; + unsigned long env_start_block = CONFIG_ENV_OFFSET / mtd->erasesize; + unsigned long env_end_block = env_start_block + + DIV_ROUND_UP(TOTAL_ENV_SIZE, mtd->erasesize) - 1; + int optind; + int fw1_set = 0; + int fw2_set = 0; + unsigned long fw1_start_block = 0, fw1_end_block; + unsigned long fw2_start_block = 0, fw2_end_block; + unsigned long fw_num_blocks; + unsigned long extra_blocks = 2; + nand_erase_options_t erase_opts = { 0, }; + int fcb_written = 0; + + load_addr = getenv("fileaddr"); + file_size = getenv("filesize"); + + if (argc < 2 && load_addr == NULL) { + printf("Load address not specified\n"); + return -EINVAL; + } + if (argc < 3 && file_size == NULL) { + printf("Image size not specified\n"); + return -EINVAL; + } + + for (optind = 1; optind < argc; optind++) { + if (strcmp(argv[optind], "-b") == 0) { + if (optind >= argc - 1) { + printf("Option %s requires an argument\n", argv[optind]); + return -EINVAL; + } + optind++; + fcb_start_block = simple_strtoul(argv[optind], NULL, 0); + if (fcb_start_block >= mtd_num_blocks) { + printf("Block number %lu is out of range: 0..%lu\n", + fcb_start_block, mtd_num_blocks - 1); + return -EINVAL; + } + } else if (strcmp(argv[optind], "-n") == 0) { + if (optind >= argc - 1) { + printf("Option %s requires an argument\n", argv[optind]); + return -EINVAL; + } + optind++; + num_fcb_blocks = simple_strtoul(argv[optind], NULL, 0); + if (num_fcb_blocks > MAX_FCB_BLOCKS) { + printf("Extraneous number of FCB blocks; max. allowed: %u\n", + MAX_FCB_BLOCKS); + return -EINVAL; + } + } else if (strcmp(argv[optind], "-f") == 0) { + if (optind >= argc - 1) { + printf("Option %s requires an argument\n", argv[optind]); + return -EINVAL; + } + optind++; + fw1_start_block = simple_strtoul(argv[optind], NULL, 0); + if (fw1_start_block >= mtd_num_blocks) { + printf("Block number %lu is out of range: 0..%lu\n", + fw1_start_block, + mtd_num_blocks - 1); + return -EINVAL; + } + fw1_set = 1; + } else if (strcmp(argv[optind], "-r") == 0) { + if (optind < argc - 1 && argv[optind + 1][0] != '-') { + optind++; + fw2_start_block = simple_strtoul(argv[optind], NULL, 0); + if (fw2_start_block >= mtd_num_blocks) { + printf("Block number %lu is out of range: 0..%lu\n", + fw2_start_block, + mtd_num_blocks - 1); + return -EINVAL; + } + } + fw2_set = 1; + } else if (strcmp(argv[optind], "-e") == 0) { + if (optind >= argc - 1) { + printf("Option %s requires an argument\n", argv[optind]); + return -EINVAL; + } + optind++; + extra_blocks = simple_strtoul(argv[optind], NULL, 0); + if (extra_blocks >= mtd_num_blocks) { + printf("Extra block count %lu is out of range: 0..%lu\n", + extra_blocks, + mtd_num_blocks - 1); + return -EINVAL; + } + } else if (argv[optind][0] == '-') { + printf("Unrecognized option %s\n", argv[optind]); + return -EINVAL; + } + } + if (argc > optind) { + load_addr = NULL; + addr = (void *)simple_strtoul(argv[optind], NULL, 0); + optind++; + } + if (argc > optind) { + file_size = NULL; + size = simple_strtoul(argv[optind], NULL, 0); + optind++; + } + if (load_addr != NULL) { + addr = (void *)simple_strtoul(load_addr, NULL, 16); + printf("Using default load address %p\n", addr); + } + if (file_size != NULL) { + size = simple_strtoul(file_size, NULL, 16); + printf("Using default file size %08x\n", size); + } + fcb_end_block = fcb_start_block + num_fcb_blocks - 1; + fw_num_blocks = DIV_ROUND_UP(size, mtd->erasesize); + + if (!fw1_set) { + fw1_start_block = fcb_end_block + 1; + fw1_end_block = fw1_start_block + fw_num_blocks + extra_blocks - 1; + if (chk_overlap(fw1, env)) { + fw1_start_block = env_end_block + 1; + fw1_end_block = fw1_start_block + fw_num_blocks + extra_blocks - 1; + } + } else { + fw1_end_block = fw1_start_block + fw_num_blocks + extra_blocks - 1; + } + + if (fw2_set && fw2_start_block == 0) { + fw2_start_block = fw1_end_block + 1; + fw2_end_block = fw2_start_block + fw_num_blocks + extra_blocks - 1; + if (chk_overlap(fw2, env)) { + fw2_start_block = env_end_block + 1; + fw2_end_block = fw2_start_block + fw_num_blocks + extra_blocks - 1; + } + } else { + fw2_end_block = fw2_start_block + fw_num_blocks + extra_blocks - 1; + } + + fail_if_overlap(fcb, env, "FCB", "Environment"); + fail_if_overlap(fcb, fw1, "FCB", "FW1"); + fail_if_overlap(fw1, env, "FW1", "Environment"); + if (fw2_set) { + fail_if_overlap(fcb, fw2, "FCB", "FW2"); + fail_if_overlap(fw2, env, "FW2", "Environment"); + fail_if_overlap(fw1, fw2, "FW1", "FW2"); + } + + buf = malloc(erase_size); + if (buf == NULL) { + printf("Failed to allocate buffer\n"); + return -ENOMEM; + } + /* search for first non-bad block in FW1 block range */ + while (fw1_start_block <= fw1_end_block) { + if (!nand_block_isbad(mtd, fw1_start_block * mtd->erasesize)) + break; + fw1_start_block++; + } + if (fw1_end_block - fw1_start_block + 1 < fw_num_blocks) { + printf("Too many bad blocks in FW1 block range: %lu..%lu\n", + fw1_end_block + 1 - fw_num_blocks - extra_blocks, + fw1_end_block); + return -EINVAL; + } + + /* search for first non-bad block in FW2 block range */ + while (fw2_set && fw2_start_block <= fw2_end_block) { + if (!nand_block_isbad(mtd, fw2_start_block * mtd->erasesize)) + break; + fw2_start_block++; + } + if (fw2_end_block - fw2_start_block + 1 < fw_num_blocks) { + printf("Too many bad blocks in FW2 area %08lx..%08lx\n", + fw2_end_block + 1 - fw_num_blocks - extra_blocks, + fw2_end_block); + return -EINVAL; + } + + fcb = create_fcb(buf, fw1_start_block, fw2_start_block, + (fw_num_blocks + extra_blocks) * mtd->erasesize); + if (IS_ERR(fcb)) { + printf("Failed to initialize FCB: %ld\n", PTR_ERR(fcb)); + return PTR_ERR(fcb); + } + encode_hamming_13_8(fcb, (void *)fcb + 512, 512); + + for (block = fcb_start_block; block < fcb_start_block + num_fcb_blocks; + block++) { + if (nand_block_isbad(mtd, block * mtd->erasesize)) { + if (block == fcb_start_block) + fcb_start_block++; + continue; + } + ret = write_fcb(buf, block); + if (ret) { + printf("Failed to write FCB to block %u\n", block); + return ret; + } + fcb_written = 1; + } + + if (!fcb_written) { + printf("Could not write FCB to flash\n"); + return -EIO; + } + + printf("Programming U-Boot image from %p to block %lu\n", + addr, fw1_start_block); + if (size & (page_size - 1)) { + memset(addr + size, 0xff, size & (page_size - 1)); + size = ALIGN(size, page_size); + } + + erase_opts.offset = fcb->fw1_start_page * page_size; + erase_opts.length = ALIGN(size, erase_size) + + extra_blocks * mtd->erasesize; + erase_opts.quiet = 1; + + printf("Erasing flash @ %08llx..%08llx\n", erase_opts.offset, + erase_opts.offset + erase_opts.length - 1); + + ret = nand_erase_opts(mtd, &erase_opts); + if (ret) { + printf("Failed to erase flash: %d\n", ret); + return ret; + } + printf("Programming flash @ %08x..%08x from %p\n", + fcb->fw1_start_page * page_size, + fcb->fw1_start_page * page_size + size, addr); + ret = nand_write_skip_bad(mtd, fcb->fw1_start_page * page_size, + &size, addr, WITH_DROP_FFS); + if (ret) { + printf("Failed to program flash: %d\n", ret); + return ret; + } + if (fw2_start_block == 0) { + return ret; + } + + printf("Programming redundant U-Boot image to block %lu\n", + fw2_start_block); + erase_opts.offset = fcb->fw2_start_page * page_size; + printf("Erasing flash @ %08llx..%08llx\n", erase_opts.offset, + erase_opts.offset + erase_opts.length - 1); + + ret = nand_erase_opts(mtd, &erase_opts); + if (ret) { + printf("Failed to erase flash: %d\n", ret); + return ret; + } + printf("Programming flash @ %08x..%08x from %p\n", + fcb->fw2_start_page * page_size, + fcb->fw2_start_page * page_size + size, addr); + ret = nand_write_skip_bad(mtd, fcb->fw2_start_page * page_size, + &size, addr, WITH_DROP_FFS); + if (ret) { + printf("Failed to program flash: %d\n", ret); + return ret; + } + return ret; +} + +U_BOOT_CMD(romupdate, 11, 0, do_update, + "Creates an FCB data structure and writes an U-Boot image to flash\n", + "[-b #] [-n #] [-f #] [-r [#]] [
] []\n" + "\t-b #\tfirst FCB block number (default 0)\n" + "\t-n #\ttotal number of FCB blocks (default 1)\n" + "\t-f #\twrite bootloader image at block #\n" + "\t-r\twrite redundant bootloader image at next free block after first image\n" + "\t-r #\twrite redundant bootloader image at block #\n" + "\t-e #\tspecify number of redundant blocks per boot loader image\n" + "\t
\tRAM address of bootloader image (default: ${fileaddr}\n" + "\t\tlength of bootloader image in RAM (default: ${filesize}" + ); diff --cc board/karo/tx28/spl_boot.c index e0541dffe9,0000000000..8cff461e5b mode 100644,000000..100644 --- a/board/karo/tx28/spl_boot.c +++ b/board/karo/tx28/spl_boot.c @@@ -1,341 -1,0 +1,338 @@@ +/* + * Copyright (C) 2011 Lothar Waßmann + * based on: board/freesclae/mx28_evk.c (C) 2010 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include + +#define MUX_CONFIG_LED (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL) +#define MUX_CONFIG_LCD (MXS_PAD_3V3 | MXS_PAD_4MA) +#define MUX_CONFIG_TSC (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP) +#define MUX_CONFIG_SSP0 (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_PULLUP) +#define MUX_CONFIG_SSP2 (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_PULLUP) +#define MUX_CONFIG_GPMI (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL) +#define MUX_CONFIG_ENET (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_PULLUP) +#define MUX_CONFIG_EMI (MXS_PAD_1V8 | MXS_PAD_12MA | MXS_PAD_NOPULL) +#define MUX_CONFIG_GPIO (MXS_PAD_3V3 | MXS_PAD_PULLUP) + +static iomux_cfg_t tx28_stk5_pads[] = { + /* LED */ + MX28_PAD_ENET0_RXD3__GPIO_4_10 | MUX_CONFIG_LED, + + /* framebuffer */ + MX28_PAD_LCD_D00__LCD_D0 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D01__LCD_D1 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D02__LCD_D2 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D03__LCD_D3 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D04__LCD_D4 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D05__LCD_D5 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D06__LCD_D6 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D07__LCD_D7 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D08__LCD_D8 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D09__LCD_D9 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D10__LCD_D10 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D11__LCD_D11 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D12__LCD_D12 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D13__LCD_D13 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D14__LCD_D14 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D15__LCD_D15 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D16__LCD_D16 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D17__LCD_D17 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D18__LCD_D18 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D19__LCD_D19 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D20__LCD_D20 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D21__LCD_D21 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D22__LCD_D22 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D23__LCD_D23 | MUX_CONFIG_LCD, + MX28_PAD_LCD_RD_E__LCD_VSYNC | MUX_CONFIG_LCD, + MX28_PAD_LCD_WR_RWN__LCD_HSYNC | MUX_CONFIG_LCD, + MX28_PAD_LCD_RS__LCD_DOTCLK | MUX_CONFIG_LCD, + MX28_PAD_LCD_CS__LCD_CS | MUX_CONFIG_LCD, + MX28_PAD_LCD_VSYNC__LCD_VSYNC | MUX_CONFIG_LCD, + MX28_PAD_LCD_HSYNC__LCD_HSYNC | MUX_CONFIG_LCD, + MX28_PAD_LCD_DOTCLK__LCD_DOTCLK | MUX_CONFIG_LCD, + MX28_PAD_LCD_ENABLE__GPIO_1_31 | MUX_CONFIG_LCD, + MX28_PAD_LCD_RESET__GPIO_3_30 | MUX_CONFIG_LCD, + + /* DUART pads */ + MX28_PAD_PWM0__GPIO_3_16 | MUX_CONFIG_GPIO, + MX28_PAD_PWM1__GPIO_3_17 | MUX_CONFIG_GPIO, + MX28_PAD_I2C0_SCL__GPIO_3_24 | MUX_CONFIG_GPIO, + MX28_PAD_I2C0_SDA__GPIO_3_25 | MUX_CONFIG_GPIO, + + MX28_PAD_AUART0_RTS__DUART_TX, + MX28_PAD_AUART0_CTS__DUART_RX, + MX28_PAD_AUART0_TX__DUART_RTS, + MX28_PAD_AUART0_RX__DUART_CTS, + + /* EMI */ + MX28_PAD_EMI_D00__EMI_DATA0 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D01__EMI_DATA1 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D02__EMI_DATA2 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D03__EMI_DATA3 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D04__EMI_DATA4 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D05__EMI_DATA5 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D06__EMI_DATA6 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D07__EMI_DATA7 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D08__EMI_DATA8 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D09__EMI_DATA9 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D10__EMI_DATA10 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D11__EMI_DATA11 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D12__EMI_DATA12 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D13__EMI_DATA13 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D14__EMI_DATA14 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D15__EMI_DATA15 | MUX_CONFIG_EMI, + MX28_PAD_EMI_ODT0__EMI_ODT0 | MUX_CONFIG_EMI, + MX28_PAD_EMI_DQM0__EMI_DQM0 | MUX_CONFIG_EMI, + MX28_PAD_EMI_ODT1__EMI_ODT1 | MUX_CONFIG_EMI, + MX28_PAD_EMI_DQM1__EMI_DQM1 | MUX_CONFIG_EMI, + MX28_PAD_EMI_DDR_OPEN_FB__EMI_DDR_OPEN_FEEDBACK | MUX_CONFIG_EMI, + MX28_PAD_EMI_CLK__EMI_CLK | MUX_CONFIG_EMI, + MX28_PAD_EMI_DQS0__EMI_DQS0 | MUX_CONFIG_EMI, + MX28_PAD_EMI_DQS1__EMI_DQS1 | MUX_CONFIG_EMI, + MX28_PAD_EMI_DDR_OPEN__EMI_DDR_OPEN | MUX_CONFIG_EMI, + + MX28_PAD_EMI_A00__EMI_ADDR0 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A01__EMI_ADDR1 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A02__EMI_ADDR2 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A03__EMI_ADDR3 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A04__EMI_ADDR4 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A05__EMI_ADDR5 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A06__EMI_ADDR6 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A07__EMI_ADDR7 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A08__EMI_ADDR8 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A09__EMI_ADDR9 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A10__EMI_ADDR10 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A11__EMI_ADDR11 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A12__EMI_ADDR12 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A13__EMI_ADDR13 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A14__EMI_ADDR14 | MUX_CONFIG_EMI, + MX28_PAD_EMI_BA0__EMI_BA0 | MUX_CONFIG_EMI, + MX28_PAD_EMI_BA1__EMI_BA1 | MUX_CONFIG_EMI, + MX28_PAD_EMI_BA2__EMI_BA2 | MUX_CONFIG_EMI, + MX28_PAD_EMI_CASN__EMI_CASN | MUX_CONFIG_EMI, + MX28_PAD_EMI_RASN__EMI_RASN | MUX_CONFIG_EMI, + MX28_PAD_EMI_WEN__EMI_WEN | MUX_CONFIG_EMI, + MX28_PAD_EMI_CE0N__EMI_CE0N | MUX_CONFIG_EMI, + MX28_PAD_EMI_CE1N__EMI_CE1N | MUX_CONFIG_EMI, + MX28_PAD_EMI_CKE__EMI_CKE | MUX_CONFIG_EMI, + + /* FEC pads */ + MX28_PAD_PWM4__GPIO_3_29 | MUX_CONFIG_ENET, + MX28_PAD_ENET0_RX_CLK__GPIO_4_13 | MUX_CONFIG_ENET, + MX28_PAD_ENET0_MDC__ENET0_MDC | MUX_CONFIG_ENET, + MX28_PAD_ENET0_MDIO__ENET0_MDIO | MUX_CONFIG_ENET, + MX28_PAD_ENET0_RX_EN__GPIO_4_2 | MUX_CONFIG_ENET, /* COL/CRS_DV/MODE2 */ + MX28_PAD_ENET0_RXD0__GPIO_4_3 | MUX_CONFIG_ENET, /* RXD0/MODE0 */ + MX28_PAD_ENET0_RXD1__GPIO_4_4 | MUX_CONFIG_ENET, /* RXD1/MODE1 */ + MX28_PAD_ENET0_TX_CLK__GPIO_4_5 | MUX_CONFIG_ENET, /* nINT/TX_ER/TXD4 */ + MX28_PAD_ENET0_TX_EN__ENET0_TX_EN | MUX_CONFIG_ENET, + MX28_PAD_ENET0_TXD0__ENET0_TXD0 | MUX_CONFIG_ENET, + MX28_PAD_ENET0_TXD1__ENET0_TXD1 | MUX_CONFIG_ENET, + MX28_PAD_ENET_CLK__CLKCTRL_ENET | MUX_CONFIG_ENET, + + /* MMC pads */ + MX28_PAD_SSP0_DATA0__SSP0_D0 | MUX_CONFIG_SSP0, + MX28_PAD_SSP0_DATA1__SSP0_D1 | MUX_CONFIG_SSP0, + MX28_PAD_SSP0_DATA2__SSP0_D2 | MUX_CONFIG_SSP0, + MX28_PAD_SSP0_DATA3__SSP0_D3 | MUX_CONFIG_SSP0, + MX28_PAD_SSP0_CMD__SSP0_CMD | MUX_CONFIG_SSP0, + MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT | MUX_CONFIG_GPIO, + MX28_PAD_SSP0_SCK__SSP0_SCK | MUX_CONFIG_SSP0, + + /* GPMI pads */ + MX28_PAD_GPMI_D00__GPMI_D0 | MUX_CONFIG_GPMI, + MX28_PAD_GPMI_D01__GPMI_D1 | MUX_CONFIG_GPMI, + MX28_PAD_GPMI_D02__GPMI_D2 | MUX_CONFIG_GPMI, + MX28_PAD_GPMI_D03__GPMI_D3 | MUX_CONFIG_GPMI, + MX28_PAD_GPMI_D04__GPMI_D4 | MUX_CONFIG_GPMI, + MX28_PAD_GPMI_D05__GPMI_D5 | MUX_CONFIG_GPMI, + MX28_PAD_GPMI_D06__GPMI_D6 | MUX_CONFIG_GPMI, + MX28_PAD_GPMI_D07__GPMI_D7 | MUX_CONFIG_GPMI, + MX28_PAD_GPMI_CE0N__GPMI_CE0N | MUX_CONFIG_GPMI, + MX28_PAD_GPMI_RDY0__GPMI_READY0 | MUX_CONFIG_GPMI, + MX28_PAD_GPMI_RDN__GPMI_RDN | MUX_CONFIG_GPMI, + MX28_PAD_GPMI_WRN__GPMI_WRN | MUX_CONFIG_GPMI, + MX28_PAD_GPMI_ALE__GPMI_ALE | MUX_CONFIG_GPMI, + MX28_PAD_GPMI_CLE__GPMI_CLE | MUX_CONFIG_GPMI, + MX28_PAD_GPMI_RESETN__GPMI_RESETN | MUX_CONFIG_GPMI, + + /* maybe used for EDT-FT5x06 */ + MX28_PAD_SSP0_DATA5__GPIO_2_5 | MUX_CONFIG_GPIO, + MX28_PAD_SSP0_DATA6__GPIO_2_6 | MUX_CONFIG_GPIO, + MX28_PAD_ENET0_RXD2__GPIO_4_9 | MUX_CONFIG_GPIO, + + /* unused pads */ + MX28_PAD_GPMI_RDY1__GPIO_0_21 | MUX_CONFIG_GPIO, + MX28_PAD_GPMI_RDY2__GPIO_0_22 | MUX_CONFIG_GPIO, + MX28_PAD_GPMI_RDY3__GPIO_0_23 | MUX_CONFIG_GPIO, + MX28_PAD_GPMI_CE1N__GPIO_0_17 | MUX_CONFIG_GPIO, + MX28_PAD_GPMI_CE2N__GPIO_0_18 | MUX_CONFIG_GPIO, + MX28_PAD_GPMI_CE3N__GPIO_0_19 | MUX_CONFIG_GPIO, + + MX28_PAD_SSP0_DATA4__GPIO_2_4 | MUX_CONFIG_GPIO, + MX28_PAD_SSP0_DATA7__GPIO_2_7 | MUX_CONFIG_GPIO, + + MX28_PAD_SSP2_SS0__GPIO_2_19 | MUX_CONFIG_GPIO, + MX28_PAD_SSP2_SS1__GPIO_2_20 | MUX_CONFIG_GPIO, + MX28_PAD_SSP2_SS2__GPIO_2_21 | MUX_CONFIG_GPIO, + MX28_PAD_SSP3_SS0__GPIO_2_27 | MUX_CONFIG_GPIO, + + MX28_PAD_ENET0_TXD2__GPIO_4_11 | MUX_CONFIG_GPIO, + MX28_PAD_ENET0_TXD3__GPIO_4_12 | MUX_CONFIG_GPIO, + MX28_PAD_ENET0_CRS__GPIO_4_15 | MUX_CONFIG_GPIO, +}; + +static void tx28_stk5_lcd_init(void) +{ + gpio_direction_output(MX28_PAD_PWM0__GPIO_3_16, 1); + gpio_direction_output(MX28_PAD_LCD_RESET__GPIO_3_30, 0); + gpio_direction_output(MX28_PAD_LCD_ENABLE__GPIO_1_31, 0); +} + +static void tx28_stk5_led_on(void) +{ + gpio_direction_output(MX28_PAD_ENET0_RXD3__GPIO_4_10, 1); +} + +void board_init_ll(void) +{ - mx28_common_spl_init(tx28_stk5_pads, ARRAY_SIZE(tx28_stk5_pads)); ++ mxs_common_spl_init(tx28_stk5_pads, ARRAY_SIZE(tx28_stk5_pads)); + tx28_stk5_lcd_init(); + tx28_stk5_led_on(); +} + +#ifndef CONFIG_TX28_S +static uint32_t tx28_dram_vals[] = { + /* TX28-41x0: NT5TU32M16DG-AC */ + /* 000 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 010 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 020 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 030 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 040 */ 0x00000000, 0x00000100, 0x00000000, 0x00000000, + /* 050 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 060 */ 0x00000000, 0x00000000, 0x00010101, 0x01010101, + /* 070 */ 0x000f0f01, 0x0102020a, 0x00000000, 0x00010101, + /* 080 */ 0x00000100, 0x00000100, 0x00000000, 0x00000002, + /* 090 */ 0x01010000, 0x07080403, 0x06005003, 0x0a0000c8, + /* 0a0 */ 0x02009c40, 0x0002030c, 0x0036a609, 0x031a0612, + /* 0b0 */ 0x02030202, 0x00c8001c, 0x00000000, 0x00000000, + /* 0c0 */ 0x00012100, 0xffff0303, 0x00012100, 0xffff0303, + /* 0d0 */ 0x00012100, 0xffff0303, 0x00012100, 0xffff0303, + /* 0e0 */ 0x00000003, 0x00000000, 0x00000000, 0x00000000, + /* 0f0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 100 */ 0x00000000, 0x00000000, 0x00000612, 0x01000f02, + /* 110 */ 0x06120612, 0x00000200, 0x00020007, 0xf4004a27, + /* 120 */ 0xf4004a27, 0xf4004a27, 0xf4004a27, 0x07400300, + /* 130 */ 0x07400300, 0x07400300, 0x07400300, 0x00000005, + /* 140 */ 0x00000000, 0x00000000, 0x01000000, 0x01020408, + /* 150 */ 0x08040201, 0x000f1133, 0x00000000, 0x00001f04, + /* 160 */ 0x00001f04, 0x00001f04, 0x00001f04, 0x00001f04, + /* 170 */ 0x00001f04, 0x00001f04, 0x00001f04, 0x00000000, + /* 180 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 190 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 1a0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 1b0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 1c0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 1d0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 1e0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 1f0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 200 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 210 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 220 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 230 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 240 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 250 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 260 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 270 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 280 */ 0x00000000, 0x00000000, 0x00010000, 0x00030404, + /* 290 */ 0x00000003, 0x00000000, 0x00000000, 0x00000000, + /* 2a0 */ 0x00000000, 0x00000000, 0x00000000, 0x01010000, + /* 2b0 */ 0x01000000, 0x03030000, 0x00010303, 0x01020202, + /* 2c0 */ 0x00000000, 0x02040303, 0x21002103, 0x00061200, + /* 2d0 */ 0x06120612, 0x04420442, 0x04420442, 0x00040004, + /* 2e0 */ 0x00040004, 0x00000000, 0x00000000, 0x00000000, + /* 2f0 */ 0x00000000, 0x00000000, +}; +#else +static uint32_t tx28_dram_vals[] = { + /* TX28-40x0: MT47H64M16HR-3 */ + /* 000 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 010 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 020 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 030 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 040 */ 0x00000000, 0x00000100, 0x00000000, 0x00000000, + /* 050 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 060 */ 0x00000000, 0x00000000, 0x00010101, 0x00010101, + /* 070 */ 0x000f0f01, 0x0102010a, 0x00000000, 0x00000101, + /* 080 */ 0x00000100, 0x00000100, 0x00000000, 0x00000002, + /* 090 */ 0x01010000, 0x07080403, 0x06005003, 0x0a0000c8, + /* 0a0 */ 0x02009c40, 0x0002030c, 0x0036a609, 0x031a0612, + /* 0b0 */ 0x02030202, 0x00c8001c, 0x00000000, 0x00000000, + /* 0c0 */ 0x00012100, 0xffff0303, 0x00012100, 0xffff0303, + /* 0d0 */ 0x00012100, 0xffff0303, 0x00012100, 0xffff0303, + /* 0e0 */ 0x00000003, 0x00000000, 0x00000000, 0x00000000, + /* 0f0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 100 */ 0x00000000, 0x00000000, 0x00000612, 0x01000f02, + /* 110 */ 0x06120612, 0x00000200, 0x00020007, 0xf4004a27, + /* 120 */ 0xf4004a27, 0xf4004a27, 0xf4004a27, 0x07400300, + /* 130 */ 0x07400300, 0x07400300, 0x07400300, 0x00000005, + /* 140 */ 0x00000000, 0x00000000, 0x01000000, 0x01020408, + /* 150 */ 0x08040201, 0x000f1133, 0x00000000, 0x00001f04, + /* 160 */ 0x00001f04, 0x00001f04, 0x00001f04, 0x00001f04, + /* 170 */ 0x00001f04, 0x00001f04, 0x00001f04, 0x00000000, + /* 180 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 190 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 1a0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 1b0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 1c0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 1d0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 1e0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 1f0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 200 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 210 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 220 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 230 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 240 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 250 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 260 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 270 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 280 */ 0x00000000, 0x00000000, 0x00010000, 0x00030404, + /* 290 */ 0x00000003, 0x00000000, 0x00000000, 0x00000000, + /* 2a0 */ 0x00000000, 0x00000000, 0x00000000, 0x01010000, + /* 2b0 */ 0x01000000, 0x03030000, 0x00010303, 0x01020202, + /* 2c0 */ 0x00000000, 0x02040303, 0x21002103, 0x00061200, + /* 2d0 */ 0x06120612, 0x04420442, 0x04420442, 0x00040004, + /* 2e0 */ 0x00040004, 0x00000000, 0x00000000, 0x00000000, + /* 2f0 */ 0x00000000, 0x00000000, +}; +#endif + - void mx28_ddr2_setup(void) ++void mxs_adjust_memory_params(uint32_t *dram_vals) +{ - int i; - - for (i = 0; i < ARRAY_SIZE(tx28_dram_vals); i++) - writel(tx28_dram_vals[i], MXS_DRAM_BASE + (4 * i)); ++ memcpy(dram_vals, tx28_dram_vals, sizeof(tx28_dram_vals)); +} diff --cc board/karo/tx28/tx28.c index 3e81bc9ca7,0000000000..c0c9107da7 mode 100644,000000..100644 --- a/board/karo/tx28/tx28.c +++ b/board/karo/tx28/tx28.c @@@ -1,767 -1,0 +1,767 @@@ +/* + * Copyright (C) 2011 Lothar Waßmann + * based on: board/freesclae/mx28_evk.c (C) 2010 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "../common/karo.h" + +DECLARE_GLOBAL_DATA_PTR; + +#define MXS_GPIO_NR(p, o) (((p) << 5) | (o)) + +#define TX28_LCD_PWR_GPIO MX28_PAD_LCD_ENABLE__GPIO_1_31 +#define TX28_LCD_RST_GPIO MX28_PAD_LCD_RESET__GPIO_3_30 +#define TX28_LCD_BACKLIGHT_GPIO MX28_PAD_PWM0__GPIO_3_16 + +#define TX28_USBH_VBUSEN_GPIO MX28_PAD_SPDIF__GPIO_3_27 +#define TX28_USBH_OC_GPIO MX28_PAD_JTAG_RTCK__GPIO_4_20 +#define TX28_USBOTG_VBUSEN_GPIO MX28_PAD_GPMI_CE2N__GPIO_0_18 +#define TX28_USBOTG_OC_GPIO MX28_PAD_GPMI_CE3N__GPIO_0_19 +#define TX28_USBOTG_ID_GPIO MX28_PAD_PWM2__GPIO_3_18 + +#define TX28_LED_GPIO MX28_PAD_ENET0_RXD3__GPIO_4_10 + +static const struct gpio tx28_gpios[] = { + { TX28_USBH_VBUSEN_GPIO, GPIOF_OUTPUT_INIT_LOW, "USBH VBUSEN", }, + { TX28_USBH_OC_GPIO, GPIOF_INPUT, "USBH OC", }, + { TX28_USBOTG_VBUSEN_GPIO, GPIOF_OUTPUT_INIT_LOW, "USBOTG VBUSEN", }, + { TX28_USBOTG_OC_GPIO, GPIOF_INPUT, "USBOTG OC", }, + { TX28_USBOTG_ID_GPIO, GPIOF_INPUT, "USBOTG ID", }, +}; + +static const iomux_cfg_t tx28_pads[] = { + /* UART pads */ +#if CONFIG_CONS_INDEX == 0 + MX28_PAD_AUART0_RX__DUART_CTS, + MX28_PAD_AUART0_TX__DUART_RTS, + MX28_PAD_AUART0_CTS__DUART_RX, + MX28_PAD_AUART0_RTS__DUART_TX, +#elif CONFIG_CONS_INDEX == 1 + MX28_PAD_AUART1_RX__AUART1_RX, + MX28_PAD_AUART1_TX__AUART1_TX, + MX28_PAD_AUART1_CTS__AUART1_CTS, + MX28_PAD_AUART1_RTS__AUART1_RTS, +#elif CONFIG_CONS_INDEX == 2 + MX28_PAD_AUART3_RX__AUART3_RX, + MX28_PAD_AUART3_TX__AUART3_TX, + MX28_PAD_AUART3_CTS__AUART3_CTS, + MX28_PAD_AUART3_RTS__AUART3_RTS, +#endif + /* I2C bus for internal DS1339, PCA9554 and on DIMM pins 40/41 */ + MX28_PAD_I2C0_SCL__I2C0_SCL, + MX28_PAD_I2C0_SDA__I2C0_SDA, + + /* USBH VBUSEN, OC */ + MX28_PAD_SPDIF__GPIO_3_27, + MX28_PAD_JTAG_RTCK__GPIO_4_20, + + /* USBOTG VBUSEN, OC, ID */ + MX28_PAD_GPMI_CE2N__GPIO_0_18, + MX28_PAD_GPMI_CE3N__GPIO_0_19, + MX28_PAD_PWM2__GPIO_3_18, +}; + +/* + * Functions + */ +int board_early_init_f(void) +{ + /* IO0 clock at 480MHz */ + mx28_set_ioclk(MXC_IOCLK0, 480000); + /* IO1 clock at 480MHz */ + mx28_set_ioclk(MXC_IOCLK1, 480000); + + /* SSP0 clock at 96MHz */ + mx28_set_sspclk(MXC_SSPCLK0, 96000, 0); + /* SSP2 clock at 96MHz */ + mx28_set_sspclk(MXC_SSPCLK2, 96000, 0); + + gpio_request_array(tx28_gpios, ARRAY_SIZE(tx28_gpios)); + mxs_iomux_setup_multiple_pads(tx28_pads, ARRAY_SIZE(tx28_pads)); + return 0; +} + +int board_init(void) +{ + /* Address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x1000; + return 0; +} + +int dram_init(void) +{ - return mx28_dram_init(); ++ return mxs_dram_init(); +} + +#ifdef CONFIG_CMD_MMC +static int tx28_mmc_wp(int dev_no) +{ + return 0; +} + +int board_mmc_init(bd_t *bis) +{ + return mxsmmc_initialize(bis, 0, tx28_mmc_wp); +} +#endif /* CONFIG_CMD_MMC */ + +#ifdef CONFIG_FEC_MXC +#ifdef CONFIG_GET_FEC_MAC_ADDR_FROM_IIM + +#ifdef CONFIG_FEC_MXC_MULTI +#define FEC_MAX_IDX 1 +#else +#define FEC_MAX_IDX 0 +#endif + +static int fec_get_mac_addr(int index) +{ + u32 val1, val2; + int timeout = 1000; - struct mx28_ocotp_regs *ocotp_regs = - (struct mx28_ocotp_regs *)MXS_OCOTP_BASE; ++ struct mxs_ocotp_regs *ocotp_regs = ++ (struct mxs_ocotp_regs *)MXS_OCOTP_BASE; + u32 *cust = &ocotp_regs->hw_ocotp_cust0; + char mac[6 * 3]; + char env_name[] = "eth.addr"; + + if (index < 0 || index > FEC_MAX_IDX) + return -EINVAL; + + /* set this bit to open the OTP banks for reading */ + writel(OCOTP_CTRL_RD_BANK_OPEN, + &ocotp_regs->hw_ocotp_ctrl_set); + + /* wait until OTP contents are readable */ + while (OCOTP_CTRL_BUSY & readl(&ocotp_regs->hw_ocotp_ctrl)) { + if (timeout-- < 0) + return -ETIMEDOUT; + udelay(100); + } + + val1 = readl(&cust[index * 8]); + val2 = readl(&cust[index * 8 + 4]); + if ((val1 | val2) == 0) + return 0; + snprintf(mac, sizeof(mac), "%02x:%02x:%02x:%02x:%02x:%02x", + (val1 >> 24) & 0xFF, (val1 >> 16) & 0xFF, + (val1 >> 8) & 0xFF, (val1 >> 0) & 0xFF, + (val2 >> 24) & 0xFF, (val2 >> 16) & 0xFF); + if (index == 0) + snprintf(env_name, sizeof(env_name), "ethaddr"); + else + snprintf(env_name, sizeof(env_name), "eth%daddr", index); + + setenv(env_name, mac); + return 0; +} +#endif /* CONFIG_GET_FEC_MAC_ADDR_FROM_IIM */ + +static const iomux_cfg_t tx28_fec_pads[] = { + MX28_PAD_ENET0_RX_EN__ENET0_RX_EN, + MX28_PAD_ENET0_RXD0__ENET0_RXD0, + MX28_PAD_ENET0_RXD1__ENET0_RXD1, +}; + +int board_eth_init(bd_t *bis) +{ + int ret; + + /* Reset the external phy */ + gpio_direction_output(MX28_PAD_ENET0_RX_CLK__GPIO_4_13, 0); + + /* Power on the external phy */ + gpio_direction_output(MX28_PAD_PWM4__GPIO_3_29, 1); + + /* Pull strap pins to high */ + gpio_direction_output(MX28_PAD_ENET0_RX_EN__GPIO_4_2, 1); + gpio_direction_output(MX28_PAD_ENET0_RXD0__GPIO_4_3, 1); + gpio_direction_output(MX28_PAD_ENET0_RXD1__GPIO_4_4, 1); + gpio_direction_input(MX28_PAD_ENET0_TX_CLK__GPIO_4_5); + + udelay(25000); + gpio_set_value(MX28_PAD_ENET0_RX_CLK__GPIO_4_13, 1); + udelay(100); + + mxs_iomux_setup_multiple_pads(tx28_fec_pads, ARRAY_SIZE(tx28_fec_pads)); + + ret = cpu_eth_init(bis); + if (ret) { + printf("cpu_eth_init() failed: %d\n", ret); + return ret; + } + + ret = fec_get_mac_addr(0); + if (ret < 0) { + printf("Failed to read FEC0 MAC address from OCOTP\n"); + return ret; + } +#ifdef CONFIG_FEC_MXC_MULTI + if (getenv("ethaddr")) { + ret = fecmxc_initialize_multi(bis, 0, 0, MXS_ENET0_BASE); + if (ret) { + printf("FEC MXS: Unable to init FEC0\n"); + return ret; + } + } + + ret = fec_get_mac_addr(1); + if (ret < 0) { + printf("Failed to read FEC1 MAC address from OCOTP\n"); + return ret; + } + if (getenv("eth1addr")) { + ret = fecmxc_initialize_multi(bis, 1, 1, MXS_ENET1_BASE); + if (ret) { + printf("FEC MXS: Unable to init FEC1\n"); + return ret; + } + } + return 0; +#else + if (getenv("ethaddr")) { + ret = fecmxc_initialize(bis); + } + return ret; +#endif +} +#endif /* CONFIG_FEC_MXC */ + +enum { + LED_STATE_INIT = -1, + LED_STATE_OFF, + LED_STATE_ON, +}; + +void show_activity(int arg) +{ + static int led_state = LED_STATE_INIT; + static ulong last; + + if (led_state == LED_STATE_INIT) { + last = get_timer(0); + gpio_set_value(TX28_LED_GPIO, 1); + led_state = LED_STATE_ON; + } else { + if (get_timer(last) > CONFIG_SYS_HZ) { + last = get_timer(0); + if (led_state == LED_STATE_ON) { + gpio_set_value(TX28_LED_GPIO, 0); + } else { + gpio_set_value(TX28_LED_GPIO, 1); + } + led_state = 1 - led_state; + } + } +} + +static const iomux_cfg_t stk5_pads[] = { + /* SW controlled LED on STK5 baseboard */ + MX28_PAD_ENET0_RXD3__GPIO_4_10, +}; + +static const struct gpio stk5_gpios[] = { +}; + +#ifdef CONFIG_LCD +static struct fb_videomode tx28_fb_modes[] = { + { + /* Standard VGA timing */ + .name = "VGA", + .refresh = 60, + .xres = 640, + .yres = 480, + .pixclock = KHZ2PICOS(25175), + .left_margin = 48, + .hsync_len = 96, + .right_margin = 16, + .upper_margin = 31, + .vsync_len = 2, + .lower_margin = 12, + .sync = FB_SYNC_DATA_ENABLE_HIGH_ACT, + .vmode = FB_VMODE_NONINTERLACED, + }, + { + /* Emerging ETV570 640 x 480 display. Syncs low active, + * DE high active, 115.2 mm x 86.4 mm display area + * VGA compatible timing + */ + .name = "ETV570", + .refresh = 60, + .xres = 640, + .yres = 480, + .pixclock = KHZ2PICOS(25175), + .left_margin = 114, + .hsync_len = 30, + .right_margin = 16, + .upper_margin = 32, + .vsync_len = 3, + .lower_margin = 10, + .sync = FB_SYNC_DATA_ENABLE_HIGH_ACT, + .vmode = FB_VMODE_NONINTERLACED, + }, + { + /* Emerging ET0350G0DH6 320 x 240 display. + * 70.08 mm x 52.56 mm display area. + */ + .name = "ET0350", + .refresh = 60, + .xres = 320, + .yres = 240, + .pixclock = KHZ2PICOS(6500), + .left_margin = 68 - 34, + .hsync_len = 34, + .right_margin = 20, + .upper_margin = 18 - 3, + .vsync_len = 3, + .lower_margin = 4, + .sync = FB_SYNC_DATA_ENABLE_HIGH_ACT, + .vmode = FB_VMODE_NONINTERLACED, + }, + { + /* Emerging ET0430G0DH6 480 x 272 display. + * 95.04 mm x 53.856 mm display area. + */ + .name = "ET0430", + .refresh = 60, + .xres = 480, + .yres = 272, + .pixclock = KHZ2PICOS(9000), + .left_margin = 2, + .hsync_len = 41, + .right_margin = 2, + .upper_margin = 2, + .vsync_len = 10, + .lower_margin = 2, + .sync = FB_SYNC_DATA_ENABLE_HIGH_ACT, + .vmode = FB_VMODE_NONINTERLACED, + }, + { + /* Emerging ET0500G0DH6 800 x 480 display. + * 109.6 mm x 66.4 mm display area. + */ + .name = "ET0500", + .refresh = 60, + .xres = 800, + .yres = 480, + .pixclock = KHZ2PICOS(33260), + .left_margin = 216 - 128, + .hsync_len = 128, + .right_margin = 1056 - 800 - 216, + .upper_margin = 35 - 2, + .vsync_len = 2, + .lower_margin = 525 - 480 - 35, + .sync = FB_SYNC_DATA_ENABLE_HIGH_ACT, + .vmode = FB_VMODE_NONINTERLACED, + }, + { + /* Emerging ETQ570G0DH6 320 x 240 display. + * 115.2 mm x 86.4 mm display area. + */ + .name = "ETQ570", + .refresh = 60, + .xres = 320, + .yres = 240, + .pixclock = KHZ2PICOS(6400), + .left_margin = 38, + .hsync_len = 30, + .right_margin = 30, + .upper_margin = 16, /* 15 according to datasheet */ + .vsync_len = 3, /* TVP -> 1>x>5 */ + .lower_margin = 4, /* 4.5 according to datasheet */ + .sync = FB_SYNC_DATA_ENABLE_HIGH_ACT, + .vmode = FB_VMODE_NONINTERLACED, + }, + { + /* Emerging ET0700G0DH6 800 x 480 display. + * 152.4 mm x 91.44 mm display area. + */ + .name = "ET0700", + .refresh = 60, + .xres = 800, + .yres = 480, + .pixclock = KHZ2PICOS(33260), + .left_margin = 216 - 128, + .hsync_len = 128, + .right_margin = 1056 - 800 - 216, + .upper_margin = 35 - 2, + .vsync_len = 2, + .lower_margin = 525 - 480 - 35, + .sync = FB_SYNC_DATA_ENABLE_HIGH_ACT, + .vmode = FB_VMODE_NONINTERLACED, + }, + { + /* unnamed entry for assigning parameters parsed from 'video_mode' string */ + .sync = FB_SYNC_DATA_ENABLE_HIGH_ACT, + .vmode = FB_VMODE_NONINTERLACED, + }, +}; + +static int lcd_enabled = 1; + +void lcd_enable(void) +{ + /* HACK ALERT: + * global variable from common/lcd.c + * Set to 0 here to prevent messages from going to LCD + * rather than serial console + */ + lcd_is_enabled = 0; + + karo_load_splashimage(1); + if (lcd_enabled) { + debug("Switching LCD on\n"); + gpio_set_value(TX28_LCD_PWR_GPIO, 1); + udelay(100); + gpio_set_value(TX28_LCD_RST_GPIO, 1); + udelay(300000); + gpio_set_value(TX28_LCD_BACKLIGHT_GPIO, 0); + } +} + +void lcd_disable(void) +{ + mxsfb_disable(); +} + +void lcd_panel_disable(void) +{ + if (lcd_enabled) { + debug("Switching LCD off\n"); + gpio_set_value(TX28_LCD_BACKLIGHT_GPIO, 1); + gpio_set_value(TX28_LCD_RST_GPIO, 0); + gpio_set_value(TX28_LCD_PWR_GPIO, 0); + } +} + +static const iomux_cfg_t stk5_lcd_pads[] = { + /* LCD RESET */ + MX28_PAD_LCD_RESET__GPIO_3_30 | MXS_PAD_CTRL, + /* LCD POWER_ENABLE */ + MX28_PAD_LCD_ENABLE__GPIO_1_31 | MXS_PAD_CTRL, + /* LCD Backlight (PWM) */ + MX28_PAD_PWM0__GPIO_3_16 | MXS_PAD_CTRL, + + /* Display */ + MX28_PAD_LCD_D00__LCD_D0 | MXS_PAD_CTRL, + MX28_PAD_LCD_D01__LCD_D1 | MXS_PAD_CTRL, + MX28_PAD_LCD_D02__LCD_D2 | MXS_PAD_CTRL, + MX28_PAD_LCD_D03__LCD_D3 | MXS_PAD_CTRL, + MX28_PAD_LCD_D04__LCD_D4 | MXS_PAD_CTRL, + MX28_PAD_LCD_D05__LCD_D5 | MXS_PAD_CTRL, + MX28_PAD_LCD_D06__LCD_D6 | MXS_PAD_CTRL, + MX28_PAD_LCD_D07__LCD_D7 | MXS_PAD_CTRL, + MX28_PAD_LCD_D08__LCD_D8 | MXS_PAD_CTRL, + MX28_PAD_LCD_D09__LCD_D9 | MXS_PAD_CTRL, + MX28_PAD_LCD_D10__LCD_D10 | MXS_PAD_CTRL, + MX28_PAD_LCD_D11__LCD_D11 | MXS_PAD_CTRL, + MX28_PAD_LCD_D12__LCD_D12 | MXS_PAD_CTRL, + MX28_PAD_LCD_D13__LCD_D13 | MXS_PAD_CTRL, + MX28_PAD_LCD_D14__LCD_D14 | MXS_PAD_CTRL, + MX28_PAD_LCD_D15__LCD_D15 | MXS_PAD_CTRL, + MX28_PAD_LCD_D16__LCD_D16 | MXS_PAD_CTRL, + MX28_PAD_LCD_D17__LCD_D17 | MXS_PAD_CTRL, + MX28_PAD_LCD_D18__LCD_D18 | MXS_PAD_CTRL, + MX28_PAD_LCD_D19__LCD_D19 | MXS_PAD_CTRL, + MX28_PAD_LCD_D20__LCD_D20 | MXS_PAD_CTRL, + MX28_PAD_LCD_D21__LCD_D21 | MXS_PAD_CTRL, + MX28_PAD_LCD_D22__LCD_D22 | MXS_PAD_CTRL, + MX28_PAD_LCD_D23__LCD_D23 | MXS_PAD_CTRL, + MX28_PAD_LCD_RD_E__LCD_VSYNC | MXS_PAD_CTRL, + MX28_PAD_LCD_WR_RWN__LCD_HSYNC | MXS_PAD_CTRL, + MX28_PAD_LCD_RS__LCD_DOTCLK | MXS_PAD_CTRL, + MX28_PAD_LCD_CS__LCD_CS | MXS_PAD_CTRL, + MX28_PAD_LCD_VSYNC__LCD_VSYNC | MXS_PAD_CTRL, + MX28_PAD_LCD_HSYNC__LCD_HSYNC | MXS_PAD_CTRL, + MX28_PAD_LCD_DOTCLK__LCD_DOTCLK | MXS_PAD_CTRL, +}; + +static const struct gpio stk5_lcd_gpios[] = { + { TX28_LCD_RST_GPIO, GPIOF_OUTPUT_INIT_LOW, "LCD RESET", }, + { TX28_LCD_PWR_GPIO, GPIOF_OUTPUT_INIT_LOW, "LCD POWER", }, + { TX28_LCD_BACKLIGHT_GPIO, GPIOF_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", }, +}; + +extern void video_hw_init(void *lcdbase); + +void lcd_ctrl_init(void *lcdbase) +{ + int color_depth = 24; + char *vm; + unsigned long val; + int refresh = 60; + struct fb_videomode *p = &tx28_fb_modes[0]; + int xres_set = 0, yres_set = 0, bpp_set = 0, refresh_set = 0; + + if (!lcd_enabled) { + debug("LCD disabled\n"); + return; + } + + if (tstc()) { + debug("Disabling LCD\n"); + lcd_enabled = 0; + return; + } + + vm = getenv("video_mode"); + if (vm == NULL) { + debug("Disabling LCD\n"); + lcd_enabled = 0; + return; + } + while (p->name != NULL) { + if (strcmp(p->name, vm) == 0) { + printf("Using video mode: '%s'\n", p->name); + vm += strlen(vm); + break; + } + p++; + } + + while (*vm != '\0') { + if (*vm >= '0' && *vm <= '9') { + char *end; + + val = simple_strtoul(vm, &end, 0); + if (end > vm) { + if (!xres_set) { + if (val > panel_info.vl_col) + val = panel_info.vl_col; + p->xres = val; + xres_set = 1; + } else if (!yres_set) { + if (val > panel_info.vl_row) + val = panel_info.vl_row; + p->yres = val; + yres_set = 1; + } else if (!bpp_set) { + switch (val) { + case 8: + case 16: + case 18: + case 24: + color_depth = val; + break; + + default: + printf("Invalid color depth: '%.*s' in video_mode; using default: '%u'\n", + end - vm, vm, color_depth); + } + bpp_set = 1; + } else if (!refresh_set) { + refresh = val; + refresh_set = 1; + } + } + vm = end; + } + switch (*vm) { + case '@': + bpp_set = 1; + /* fallthru */ + case '-': + yres_set = 1; + /* fallthru */ + case 'x': + xres_set = 1; + /* fallthru */ + case 'M': + case 'R': + vm++; + break; + + default: + if (*vm != '\0') + vm++; + } + } + if (p->xres == 0 || p->yres == 0) { + printf("Invalid video mode: %s\n", getenv("video_mode")); + lcd_enabled = 0; + printf("Supported video modes are:"); + for (p = &tx28_fb_modes[0]; p->name != NULL; p++) { + printf(" %s", p->name); + } + printf("\n"); + return; + } + p->pixclock = KHZ2PICOS(refresh * + (p->xres + p->left_margin + p->right_margin + p->hsync_len) * + (p->yres + p->upper_margin + p->lower_margin + p->vsync_len) / + 1000); + debug("Pixel clock set to %lu.%03lu MHz\n", + PICOS2KHZ(p->pixclock) / 1000, PICOS2KHZ(p->pixclock) % 1000); + + gpio_request_array(stk5_lcd_gpios, ARRAY_SIZE(stk5_lcd_gpios)); + mxs_iomux_setup_multiple_pads(stk5_lcd_pads, + ARRAY_SIZE(stk5_lcd_pads)); + + debug("video format: %ux%u-%u@%u\n", p->xres, p->yres, + color_depth, refresh); + + if (karo_load_splashimage(0) == 0) { + debug("Initializing LCD controller\n"); + mxsfb_init(p, PIX_FMT_RGB24, color_depth); + video_hw_init(lcdbase); + } else { + debug("Skipping initialization of LCD controller\n"); + } +} +#else +#define lcd_enabled 0 +#endif /* CONFIG_LCD */ + +static void stk5_board_init(void) +{ + gpio_request_array(stk5_gpios, ARRAY_SIZE(stk5_gpios)); + mxs_iomux_setup_multiple_pads(stk5_pads, ARRAY_SIZE(stk5_pads)); +} + +static void stk5v3_board_init(void) +{ + stk5_board_init(); +} + +static void stk5v5_board_init(void) +{ + stk5_board_init(); + + /* init flexcan transceiver enable GPIO */ + gpio_request_one(MXS_GPIO_NR(0, 1), GPIOF_OUTPUT_INIT_HIGH, + "Flexcan Transceiver"); + mxs_iomux_setup_pad(MX28_PAD_LCD_D00__GPIO_1_0); +} + +int board_late_init(void) +{ + const char *baseboard; + + karo_fdt_move_fdt(); + + baseboard = getenv("baseboard"); + if (!baseboard) + return 0; + + if (strncmp(baseboard, "stk5", 4) == 0) { + printf("Baseboard: %s\n", baseboard); + if ((strlen(baseboard) == 4) || + strcmp(baseboard, "stk5-v3") == 0) { + stk5v3_board_init(); + } else if (strcmp(baseboard, "stk5-v5") == 0) { + stk5v5_board_init(); + } else { + printf("WARNING: Unsupported STK5 board rev.: %s\n", + baseboard + 4); + } + } else { + printf("WARNING: Unsupported baseboard: '%s'\n", + baseboard); + return -EINVAL; + } + + return 0; +} + +int checkboard(void) +{ + printf("Board: Ka-Ro TX28-4%sxx\n", TX28_MOD_SUFFIX); + return 0; +} + +#if defined(CONFIG_OF_BOARD_SETUP) +#ifdef CONFIG_FDT_FIXUP_PARTITIONS +#include +#include +struct node_info tx28_nand_nodes[] = { + { "gpmi-nand", MTD_DEV_TYPE_NAND, }, +}; +#else +#define fdt_fixup_mtdparts(b,n,c) do { } while (0) +#endif + +static void tx28_fixup_flexcan(void *blob) +{ + karo_fdt_del_prop(blob, "fsl,p1010-flexcan", 0x80032000, "transceiver-switch"); + karo_fdt_del_prop(blob, "fsl,p1010-flexcan", 0x80034000, "transceiver-switch"); +} + +static void tx28_fixup_fec(void *blob) +{ + karo_fdt_remove_node(blob, "ethernet1"); +} + +void ft_board_setup(void *blob, bd_t *bd) +{ + const char *baseboard = getenv("baseboard"); + +#ifdef CONFIG_TX28_S + /* TX28-41xx (aka TX28S) has no external RTC + * and no I2C GPIO extender + */ + karo_fdt_remove_node(blob, "ds1339"); + karo_fdt_remove_node(blob, "pca9554"); +#endif + if (baseboard != NULL && strcmp(baseboard, "stk5-v5") == 0) { + const char *otg_mode = getenv("otg_mode"); + + if (otg_mode && strcmp(otg_mode, "host") == 0) { + printf("otg_mode=%s incompatible with baseboard %s\n", + otg_mode, baseboard); + setenv(otg_mode, "none"); + } + karo_fdt_remove_node(blob, "stk5led"); + } else { + tx28_fixup_flexcan(blob); + tx28_fixup_fec(blob); + } + + if (baseboard != NULL && strcmp(baseboard, "stk5-v3") == 0) { + const char *otg_mode = getenv("otg_mode"); + + if (otg_mode && strcmp(otg_mode, "device") == 0) + karo_fdt_remove_node(blob, "can1"); + } + + fdt_fixup_mtdparts(blob, tx28_nand_nodes, ARRAY_SIZE(tx28_nand_nodes)); + fdt_fixup_ethernet(blob); + + karo_fdt_fixup_touchpanel(blob); + karo_fdt_fixup_usb_otg(blob, "fsl,imx28-usbphy", 0x8007c000); +} +#endif diff --cc board/karo/tx48/config.mk index 461f2d7bda,0000000000..c68318af32 mode 100644,000000..100644 --- a/board/karo/tx48/config.mk +++ b/board/karo/tx48/config.mk @@@ -1,6 -1,0 +1,8 @@@ +CONFIG_SYS_TEXT_BASE = 0x80800000 +ifneq ($(CONFIG_SPL_BUILD),) + CONFIG_SPL_TEXT_BASE = 0x402F0400 +endif +PLATFORM_CPPFLAGS += -Werror ++PLATFORM_CPPFLAGS += -DDEBUG ++ +LOGO_BMP = logos/karo.bmp diff --cc board/karo/tx48/spl.c index d106f2ab48,0000000000..9c3cf6f0c9 mode 100644,000000..100644 --- a/board/karo/tx48/spl.c +++ b/board/karo/tx48/spl.c @@@ -1,415 -1,0 +1,490 @@@ +/* + * board/karo/tx48/spl.c + * Copyright (C) 2012 Lothar Waßmann + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include ++#include +#include +#include +#include +#include +#include +#include +#include +#include ++#include +#include +#include +#include - #include +#include +#include + +#define TX48_LED_GPIO AM33XX_GPIO_NR(1, 26) +#define TX48_ETH_PHY_RST_GPIO AM33XX_GPIO_NR(3, 8) +#define TX48_LCD_RST_GPIO AM33XX_GPIO_NR(1, 19) +#define TX48_LCD_PWR_GPIO AM33XX_GPIO_NR(1, 22) +#define TX48_LCD_BACKLIGHT_GPIO AM33XX_GPIO_NR(3, 14) + +#define GMII_SEL (CTRL_BASE + 0x650) + +/* UART Defines */ +#define UART_SYSCFG_OFFSET 0x54 +#define UART_SYSSTS_OFFSET 0x58 + +#define UART_RESET (0x1 << 1) +#define UART_CLK_RUNNING_MASK 0x1 +#define UART_SMART_IDLE_EN (0x1 << 0x3) + +/* Timer Defines */ +#define TSICR_REG 0x54 +#define TIOCP_CFG_REG 0x10 +#define TCLR_REG 0x38 + +/* RGMII mode define */ +#define RGMII_MODE_ENABLE 0xA +#define RMII_MODE_ENABLE 0x5 +#define MII_MODE_ENABLE 0x0 + +#define NO_OF_MAC_ADDR 1 +#define ETH_ALEN 6 + +#define MUX_CFG(value, offset) { \ + __raw_writel(value, (CTRL_BASE + (offset))); \ + } + +/* PAD Control Fields */ +#define SLEWCTRL (0x1 << 6) +#define RXACTIVE (0x1 << 5) +#define PULLUP_EN (0x1 << 4) /* Pull UP Selection */ +#define PULLUDEN (0x0 << 3) /* Pull up enabled */ +#define PULLUDDIS (0x1 << 3) /* Pull up disabled */ +#define MODE(val) (val) + +/* + * PAD CONTROL OFFSETS + * Field names corresponds to the pad signal name + */ +struct pad_signals { + int gpmc_ad0; + int gpmc_ad1; + int gpmc_ad2; + int gpmc_ad3; + int gpmc_ad4; + int gpmc_ad5; + int gpmc_ad6; + int gpmc_ad7; + int gpmc_ad8; + int gpmc_ad9; + int gpmc_ad10; + int gpmc_ad11; + int gpmc_ad12; + int gpmc_ad13; + int gpmc_ad14; + int gpmc_ad15; + int gpmc_a0; + int gpmc_a1; + int gpmc_a2; + int gpmc_a3; + int gpmc_a4; + int gpmc_a5; + int gpmc_a6; + int gpmc_a7; + int gpmc_a8; + int gpmc_a9; + int gpmc_a10; + int gpmc_a11; + int gpmc_wait0; + int gpmc_wpn; + int gpmc_be1n; + int gpmc_csn0; + int gpmc_csn1; + int gpmc_csn2; + int gpmc_csn3; + int gpmc_clk; + int gpmc_advn_ale; + int gpmc_oen_ren; + int gpmc_wen; + int gpmc_be0n_cle; + int lcd_data0; + int lcd_data1; + int lcd_data2; + int lcd_data3; + int lcd_data4; + int lcd_data5; + int lcd_data6; + int lcd_data7; + int lcd_data8; + int lcd_data9; + int lcd_data10; + int lcd_data11; + int lcd_data12; + int lcd_data13; + int lcd_data14; + int lcd_data15; + int lcd_vsync; + int lcd_hsync; + int lcd_pclk; + int lcd_ac_bias_en; + int mmc0_dat3; + int mmc0_dat2; + int mmc0_dat1; + int mmc0_dat0; + int mmc0_clk; + int mmc0_cmd; + int mii1_col; + int mii1_crs; + int mii1_rxerr; + int mii1_txen; + int mii1_rxdv; + int mii1_txd3; + int mii1_txd2; + int mii1_txd1; + int mii1_txd0; + int mii1_txclk; + int mii1_rxclk; + int mii1_rxd3; + int mii1_rxd2; + int mii1_rxd1; + int mii1_rxd0; + int rmii1_refclk; + int mdio_data; + int mdio_clk; + int spi0_sclk; + int spi0_d0; + int spi0_d1; + int spi0_cs0; + int spi0_cs1; + int ecap0_in_pwm0_out; + int uart0_ctsn; + int uart0_rtsn; + int uart0_rxd; + int uart0_txd; + int uart1_ctsn; + int uart1_rtsn; + int uart1_rxd; + int uart1_txd; + int i2c0_sda; + int i2c0_scl; + int mcasp0_aclkx; + int mcasp0_fsx; + int mcasp0_axr0; + int mcasp0_ahclkr; + int mcasp0_aclkr; + int mcasp0_fsr; + int mcasp0_axr1; + int mcasp0_ahclkx; + int xdma_event_intr0; + int xdma_event_intr1; + int nresetin_out; + int porz; + int nnmi; + int osc0_in; + int osc0_out; + int rsvd1; + int tms; + int tdi; + int tdo; + int tck; + int ntrst; + int emu0; + int emu1; + int osc1_in; + int osc1_out; + int pmic_power_en; + int rtc_porz; + int rsvd2; + int ext_wakeup; + int enz_kaldo_1p8v; + int usb0_dm; + int usb0_dp; + int usb0_ce; + int usb0_id; + int usb0_vbus; + int usb0_drvvbus; + int usb1_dm; + int usb1_dp; + int usb1_ce; + int usb1_id; + int usb1_vbus; + int usb1_drvvbus; + int ddr_resetn; + int ddr_csn0; + int ddr_cke; + int ddr_ck; + int ddr_nck; + int ddr_casn; + int ddr_rasn; + int ddr_wen; + int ddr_ba0; + int ddr_ba1; + int ddr_ba2; + int ddr_a0; + int ddr_a1; + int ddr_a2; + int ddr_a3; + int ddr_a4; + int ddr_a5; + int ddr_a6; + int ddr_a7; + int ddr_a8; + int ddr_a9; + int ddr_a10; + int ddr_a11; + int ddr_a12; + int ddr_a13; + int ddr_a14; + int ddr_a15; + int ddr_odt; + int ddr_d0; + int ddr_d1; + int ddr_d2; + int ddr_d3; + int ddr_d4; + int ddr_d5; + int ddr_d6; + int ddr_d7; + int ddr_d8; + int ddr_d9; + int ddr_d10; + int ddr_d11; + int ddr_d12; + int ddr_d13; + int ddr_d14; + int ddr_d15; + int ddr_dqm0; + int ddr_dqm1; + int ddr_dqs0; + int ddr_dqsn0; + int ddr_dqs1; + int ddr_dqsn1; + int ddr_vref; + int ddr_vtp; + int ddr_strben0; + int ddr_strben1; + int ain7; + int ain6; + int ain5; + int ain4; + int ain3; + int ain2; + int ain1; + int ain0; + int vrefp; + int vrefn; +}; + +struct pin_mux { + short reg_offset; + uint8_t val; +}; + +#define PAD_CTRL_BASE 0x800 +#define OFFSET(x) (unsigned int) (&((struct pad_signals *) \ + (PAD_CTRL_BASE))->x) + +static struct pin_mux tx48_pins[] = { +#ifdef CONFIG_CMD_NAND + { OFFSET(gpmc_ad0), MODE(0) | PULLUP_EN | RXACTIVE, }, /* NAND AD0 */ + { OFFSET(gpmc_ad1), MODE(0) | PULLUP_EN | RXACTIVE, }, /* NAND AD1 */ + { OFFSET(gpmc_ad2), MODE(0) | PULLUP_EN | RXACTIVE, }, /* NAND AD2 */ + { OFFSET(gpmc_ad3), MODE(0) | PULLUP_EN | RXACTIVE, }, /* NAND AD3 */ + { OFFSET(gpmc_ad4), MODE(0) | PULLUP_EN | RXACTIVE, }, /* NAND AD4 */ + { OFFSET(gpmc_ad5), MODE(0) | PULLUP_EN | RXACTIVE, }, /* NAND AD5 */ + { OFFSET(gpmc_ad6), MODE(0) | PULLUP_EN | RXACTIVE, }, /* NAND AD6 */ + { OFFSET(gpmc_ad7), MODE(0) | PULLUP_EN | RXACTIVE, }, /* NAND AD7 */ + { OFFSET(gpmc_wait0), MODE(0) | RXACTIVE | PULLUP_EN, }, /* NAND WAIT */ + { OFFSET(gpmc_wpn), MODE(7) | PULLUP_EN | RXACTIVE, }, /* NAND_WPN */ + { OFFSET(gpmc_csn0), MODE(0) | PULLUDEN, }, /* NAND_CS0 */ + { OFFSET(gpmc_advn_ale), MODE(0) | PULLUDEN, }, /* NAND_ADV_ALE */ + { OFFSET(gpmc_oen_ren), MODE(0) | PULLUDEN, }, /* NAND_OE */ + { OFFSET(gpmc_wen), MODE(0) | PULLUDEN, }, /* NAND_WEN */ + { OFFSET(gpmc_be0n_cle), MODE(0) | PULLUDEN, }, /* NAND_BE_CLE */ +#endif + /* I2C0 */ + { OFFSET(i2c0_sda), MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL, }, /* I2C_DATA */ + { OFFSET(i2c0_scl), MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL, }, /* I2C_SCLK */ + +#ifndef CONFIG_NO_ETH + /* RMII1 */ + { OFFSET(mii1_crs), MODE(1) | RXACTIVE, }, /* RMII1_CRS */ + { OFFSET(mii1_rxerr), MODE(1) | RXACTIVE | PULLUDEN, }, /* RMII1_RXERR */ + { OFFSET(mii1_txen), MODE(1), }, /* RMII1_TXEN */ + { OFFSET(mii1_txd1), MODE(1), }, /* RMII1_TXD1 */ + { OFFSET(mii1_txd0), MODE(1), }, /* RMII1_TXD0 */ + { OFFSET(mii1_rxd1), MODE(1) | RXACTIVE | PULLUP_EN, }, /* RMII1_RXD1 */ + { OFFSET(mii1_rxd0), MODE(1) | RXACTIVE | PULLUP_EN, }, /* RMII1_RXD0 */ + { OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN, }, /* MDIO_DATA */ + { OFFSET(mdio_clk), MODE(0) | PULLUP_EN, }, /* MDIO_CLK */ + { OFFSET(rmii1_refclk), MODE(0) | RXACTIVE, }, /* RMII1_REFCLK */ + { OFFSET(emu0), MODE(7) | RXACTIVE}, /* nINT */ + { OFFSET(emu1), MODE(7), }, /* nRST */ +#endif +}; + +static struct gpio tx48_gpios[] = { + /* configure this pin early to prevent flicker of the LCD */ + { TX48_LCD_BACKLIGHT_GPIO, GPIOF_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", }, +}; + +static struct pin_mux tx48_mmc_pins[] = { +#ifdef CONFIG_OMAP_HSMMC + /* MMC1 */ + { OFFSET(mii1_rxd2), MODE(4) | RXACTIVE | PULLUP_EN, }, /* MMC1_DAT3 */ + { OFFSET(mii1_rxd3), MODE(4) | RXACTIVE | PULLUP_EN, }, /* MMC1_DAT2 */ + { OFFSET(mii1_rxclk), MODE(4) | RXACTIVE | PULLUP_EN, }, /* MMC1_DAT1 */ + { OFFSET(mii1_txclk), MODE(4) | RXACTIVE | PULLUP_EN, }, /* MMC1_DAT0 */ + { OFFSET(gpmc_csn1), MODE(2) | RXACTIVE | PULLUP_EN, }, /* MMC1_CLK */ + { OFFSET(gpmc_csn2), MODE(2) | RXACTIVE | PULLUP_EN, }, /* MMC1_CMD */ + { OFFSET(mcasp0_fsx), MODE(4) | RXACTIVE, }, /* MMC1_CD */ +#endif +}; + +/* + * Configure the pin mux for the module + */ +static inline void tx48_set_pin_mux(const struct pin_mux *pin_mux, + int num_pins) +{ + int i; + + for (i = 0; i < num_pins; i++) + MUX_CFG(pin_mux[i].val, pin_mux[i].reg_offset); +} + - #ifdef CONFIG_SPL_BOARD_INIT - void spl_board_init(void) - { - gpio_request_array(tx48_gpios, ARRAY_SIZE(tx48_gpios)); - tx48_set_pin_mux(tx48_pins, ARRAY_SIZE(tx48_pins)); - gpmc_init(); - } - #endif /* CONFIG_SPL_BOARD_INIT */ - +static struct pin_mux tx48_uart0_pins[] = { +#ifdef CONFIG_SYS_NS16550_COM1 + /* UART0 for early boot messages */ + { OFFSET(uart0_rxd), MODE(0) | PULLUP_EN | RXACTIVE, }, /* UART0_RXD */ + { OFFSET(uart0_txd), MODE(0) | PULLUDEN, }, /* UART0_TXD */ + { OFFSET(uart0_ctsn), MODE(0) | PULLUP_EN | RXACTIVE, },/* UART0_CTS */ + { OFFSET(uart0_rtsn), MODE(0) | PULLUDEN, }, /* UART0_RTS */ +#endif +#ifdef CONFIG_SYS_NS16550_COM2 + /* UART1 */ + { OFFSET(uart1_rxd), MODE(0) | PULLUP_EN | RXACTIVE, }, /* UART1_RXD */ + { OFFSET(uart1_txd), MODE(0) | PULLUDEN, }, /* UART1_TXD */ + { OFFSET(uart1_ctsn), MODE(0) | PULLUP_EN | RXACTIVE, },/* UART1_CTS */ + { OFFSET(uart1_rtsn), MODE(0) | PULLUDEN, }, /* UART1_RTS */ +#endif +#ifdef CONFIG_SYS_NS16550_COM3 + /* UART5 */ + { OFFSET(mii1_rxdv), MODE(3) | PULLUP_EN | RXACTIVE, }, /* UART5_RXD */ + { OFFSET(mii1_col), MODE(3) | PULLUDEN, }, /* UART5_TXD */ + { OFFSET(mmc0_dat1), MODE(2) | PULLUP_EN | RXACTIVE, }, /* UART5_CTS */ + { OFFSET(mmc0_dat0), MODE(2) | PULLUDEN, }, /* UART5_RTS */ +#endif +}; + +/* + * early system init of muxing and clocks. + */ +void enable_uart0_pin_mux(void) +{ + tx48_set_pin_mux(tx48_uart0_pins, ARRAY_SIZE(tx48_uart0_pins)); +} + +void enable_mmc0_pin_mux(void) +{ + tx48_set_pin_mux(tx48_mmc_pins, ARRAY_SIZE(tx48_mmc_pins)); +} ++ ++static const struct ddr_data tx48_ddr3_data = { ++ .datardsratio0 = MT41J128MJT125_RD_DQS, ++ .datawdsratio0 = MT41J128MJT125_WR_DQS, ++ .datafwsratio0 = MT41J128MJT125_PHY_FIFO_WE, ++ .datawrsratio0 = MT41J128MJT125_PHY_WR_DATA, ++ .datadldiff0 = PHY_DLL_LOCK_DIFF, ++}; ++ ++static const struct cmd_control tx48_ddr3_cmd_ctrl_data = { ++ .cmd0csratio = MT41J128MJT125_RATIO, ++ .cmd0dldiff = MT41J128MJT125_DLL_LOCK_DIFF, ++ .cmd0iclkout = MT41J128MJT125_INVERT_CLKOUT, ++ ++ .cmd1csratio = MT41J128MJT125_RATIO, ++ .cmd1dldiff = MT41J128MJT125_DLL_LOCK_DIFF, ++ .cmd1iclkout = MT41J128MJT125_INVERT_CLKOUT, ++ ++ .cmd2csratio = MT41J128MJT125_RATIO, ++ .cmd2dldiff = MT41J128MJT125_DLL_LOCK_DIFF, ++ .cmd2iclkout = MT41J128MJT125_INVERT_CLKOUT, ++}; ++ ++static struct emif_regs tx48_ddr3_emif_reg_data = { ++ .sdram_config = MT41J128MJT125_EMIF_SDCFG, ++ .ref_ctrl = MT41J128MJT125_EMIF_SDREF, ++ .sdram_tim1 = MT41J128MJT125_EMIF_TIM1, ++ .sdram_tim2 = MT41J128MJT125_EMIF_TIM2, ++ .sdram_tim3 = MT41J128MJT125_EMIF_TIM3, ++ .zq_config = MT41J128MJT125_ZQ_CFG, ++ .emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY, ++}; ++ ++void s_init(void) ++{ ++#ifndef CONFIG_HW_WATCHDOG ++ struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE; ++ ++ /* WDT1 is already running when the bootloader gets control ++ * Disable it to avoid "random" resets ++ */ ++ writel(0xAAAA, &wdtimer->wdtwspr); ++ while (readl(&wdtimer->wdtwwps) != 0x0) ++ ; ++ writel(0x5555, &wdtimer->wdtwspr); ++ while (readl(&wdtimer->wdtwwps) != 0x0) ++ ; ++#endif ++ /* Setup the PLLs and the clocks for the peripherals */ ++ pll_init(); ++ ++ /* UART softreset */ ++ u32 regVal; ++ struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE; ++ ++ enable_uart0_pin_mux(); ++ ++ regVal = readl(&uart_base->uartsyscfg); ++ regVal |= UART_RESET; ++ writel(regVal, &uart_base->uartsyscfg); ++ while ((readl(&uart_base->uartsyssts) & ++ UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK) ++ ; ++ ++ /* Disable smart idle */ ++ regVal = readl(&uart_base->uartsyscfg); ++ regVal |= UART_SMART_IDLE_EN; ++ writel(regVal, &uart_base->uartsyscfg); ++ ++ /* Initialize the Timer */ ++ timer_init(); ++ ++ preloader_console_init(); ++ ++ config_ddr(303, MT41J128MJT125_IOCTRL_VALUE, &tx48_ddr3_data, ++ &tx48_ddr3_cmd_ctrl_data, &tx48_ddr3_emif_reg_data); ++ ++ /* Enable MMC0 */ ++ enable_mmc0_pin_mux(); ++ ++ gpio_request_array(tx48_gpios, ARRAY_SIZE(tx48_gpios)); ++ tx48_set_pin_mux(tx48_pins, ARRAY_SIZE(tx48_pins)); ++} diff --cc board/karo/tx48/tx48.c index 79640676e7,0000000000..3232d4a648 mode 100644,000000..100644 --- a/board/karo/tx48/tx48.c +++ b/board/karo/tx48/tx48.c @@@ -1,862 -1,0 +1,866 @@@ +/* + * tx48.c + * Copyright (C) 2012 Lothar Waßmann + * + * based on evm.c + * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include - #include +#include +#include + +#include "../common/karo.h" + +DECLARE_GLOBAL_DATA_PTR; + +#define TX48_LED_GPIO AM33XX_GPIO_NR(1, 26) +#define TX48_ETH_PHY_RST_GPIO AM33XX_GPIO_NR(3, 8) +#define TX48_LCD_RST_GPIO AM33XX_GPIO_NR(1, 19) +#define TX48_LCD_PWR_GPIO AM33XX_GPIO_NR(1, 22) +#define TX48_LCD_BACKLIGHT_GPIO AM33XX_GPIO_NR(3, 14) + +#define GMII_SEL (CTRL_BASE + 0x650) + +/* UART Defines */ +#define UART_SYSCFG_OFFSET 0x54 +#define UART_SYSSTS_OFFSET 0x58 + +#define UART_RESET (0x1 << 1) +#define UART_CLK_RUNNING_MASK 0x1 +#define UART_SMART_IDLE_EN (0x1 << 0x3) + +/* Timer Defines */ +#define TSICR_REG 0x54 +#define TIOCP_CFG_REG 0x10 +#define TCLR_REG 0x38 + +/* RGMII mode define */ +#define RGMII_MODE_ENABLE 0xA +#define RMII_MODE_ENABLE 0x5 +#define MII_MODE_ENABLE 0x0 + +#define NO_OF_MAC_ADDR 1 +#define ETH_ALEN 6 + +#define MUX_CFG(value, offset) { \ + __raw_writel(value, (CTRL_BASE + (offset))); \ + } + +/* PAD Control Fields */ +#define SLEWCTRL (0x1 << 6) +#define RXACTIVE (0x1 << 5) +#define PULLUP_EN (0x1 << 4) /* Pull UP Selection */ +#define PULLUDEN (0x0 << 3) /* Pull up enabled */ +#define PULLUDDIS (0x1 << 3) /* Pull up disabled */ +#define MODE(val) (val) + +/* + * PAD CONTROL OFFSETS + * Field names corresponds to the pad signal name + */ +struct pad_signals { + int gpmc_ad0; + int gpmc_ad1; + int gpmc_ad2; + int gpmc_ad3; + int gpmc_ad4; + int gpmc_ad5; + int gpmc_ad6; + int gpmc_ad7; + int gpmc_ad8; + int gpmc_ad9; + int gpmc_ad10; + int gpmc_ad11; + int gpmc_ad12; + int gpmc_ad13; + int gpmc_ad14; + int gpmc_ad15; + int gpmc_a0; + int gpmc_a1; + int gpmc_a2; + int gpmc_a3; + int gpmc_a4; + int gpmc_a5; + int gpmc_a6; + int gpmc_a7; + int gpmc_a8; + int gpmc_a9; + int gpmc_a10; + int gpmc_a11; + int gpmc_wait0; + int gpmc_wpn; + int gpmc_be1n; + int gpmc_csn0; + int gpmc_csn1; + int gpmc_csn2; + int gpmc_csn3; + int gpmc_clk; + int gpmc_advn_ale; + int gpmc_oen_ren; + int gpmc_wen; + int gpmc_be0n_cle; + int lcd_data0; + int lcd_data1; + int lcd_data2; + int lcd_data3; + int lcd_data4; + int lcd_data5; + int lcd_data6; + int lcd_data7; + int lcd_data8; + int lcd_data9; + int lcd_data10; + int lcd_data11; + int lcd_data12; + int lcd_data13; + int lcd_data14; + int lcd_data15; + int lcd_vsync; + int lcd_hsync; + int lcd_pclk; + int lcd_ac_bias_en; + int mmc0_dat3; + int mmc0_dat2; + int mmc0_dat1; + int mmc0_dat0; + int mmc0_clk; + int mmc0_cmd; + int mii1_col; + int mii1_crs; + int mii1_rxerr; + int mii1_txen; + int mii1_rxdv; + int mii1_txd3; + int mii1_txd2; + int mii1_txd1; + int mii1_txd0; + int mii1_txclk; + int mii1_rxclk; + int mii1_rxd3; + int mii1_rxd2; + int mii1_rxd1; + int mii1_rxd0; + int rmii1_refclk; + int mdio_data; + int mdio_clk; + int spi0_sclk; + int spi0_d0; + int spi0_d1; + int spi0_cs0; + int spi0_cs1; + int ecap0_in_pwm0_out; + int uart0_ctsn; + int uart0_rtsn; + int uart0_rxd; + int uart0_txd; + int uart1_ctsn; + int uart1_rtsn; + int uart1_rxd; + int uart1_txd; + int i2c0_sda; + int i2c0_scl; + int mcasp0_aclkx; + int mcasp0_fsx; + int mcasp0_axr0; + int mcasp0_ahclkr; + int mcasp0_aclkr; + int mcasp0_fsr; + int mcasp0_axr1; + int mcasp0_ahclkx; + int xdma_event_intr0; + int xdma_event_intr1; + int nresetin_out; + int porz; + int nnmi; + int osc0_in; + int osc0_out; + int rsvd1; + int tms; + int tdi; + int tdo; + int tck; + int ntrst; + int emu0; + int emu1; + int osc1_in; + int osc1_out; + int pmic_power_en; + int rtc_porz; + int rsvd2; + int ext_wakeup; + int enz_kaldo_1p8v; + int usb0_dm; + int usb0_dp; + int usb0_ce; + int usb0_id; + int usb0_vbus; + int usb0_drvvbus; + int usb1_dm; + int usb1_dp; + int usb1_ce; + int usb1_id; + int usb1_vbus; + int usb1_drvvbus; + int ddr_resetn; + int ddr_csn0; + int ddr_cke; + int ddr_ck; + int ddr_nck; + int ddr_casn; + int ddr_rasn; + int ddr_wen; + int ddr_ba0; + int ddr_ba1; + int ddr_ba2; + int ddr_a0; + int ddr_a1; + int ddr_a2; + int ddr_a3; + int ddr_a4; + int ddr_a5; + int ddr_a6; + int ddr_a7; + int ddr_a8; + int ddr_a9; + int ddr_a10; + int ddr_a11; + int ddr_a12; + int ddr_a13; + int ddr_a14; + int ddr_a15; + int ddr_odt; + int ddr_d0; + int ddr_d1; + int ddr_d2; + int ddr_d3; + int ddr_d4; + int ddr_d5; + int ddr_d6; + int ddr_d7; + int ddr_d8; + int ddr_d9; + int ddr_d10; + int ddr_d11; + int ddr_d12; + int ddr_d13; + int ddr_d14; + int ddr_d15; + int ddr_dqm0; + int ddr_dqm1; + int ddr_dqs0; + int ddr_dqsn0; + int ddr_dqs1; + int ddr_dqsn1; + int ddr_vref; + int ddr_vtp; + int ddr_strben0; + int ddr_strben1; + int ain7; + int ain6; + int ain5; + int ain4; + int ain3; + int ain2; + int ain1; + int ain0; + int vrefp; + int vrefn; +}; + +struct pin_mux { + short reg_offset; + uint8_t val; +}; + +#define PAD_CTRL_BASE 0x800 +#define OFFSET(x) (unsigned int) (&((struct pad_signals *) \ + (PAD_CTRL_BASE))->x) ++ +/* + * Configure the pin mux for the module + */ +static inline void tx48_set_pin_mux(const struct pin_mux *pin_mux, + int num_pins) +{ + int i; + + for (i = 0; i < num_pins; i++) + MUX_CFG(pin_mux[i].val, pin_mux[i].reg_offset); +} + +#define PRM_RSTST_GLOBAL_COLD_RST (1 << 0) +#define PRM_RSTST_GLOBAL_WARM_SW_RST (1 << 1) +#define PRM_RSTST_WDT1_RST (1 << 4) +#define PRM_RSTST_EXTERNAL_WARM_RST (1 << 5) +#define PRM_RSTST_ICEPICK_RST (1 << 9) + +struct prm_device { + unsigned int prmrstctrl; /* offset 0x00 */ + unsigned int prmrsttime; /* offset 0x04 */ + unsigned int prmrstst; /* offset 0x08 */ + /* ... */ +}; + +static u32 prm_rstst __attribute__((section(".data"))); + +/* + * Basic board specific setup + */ +static const struct pin_mux stk5_pads[] = { + /* heartbeat LED */ + { OFFSET(gpmc_a10), MODE(7) | PULLUDEN, }, + /* LCD RESET */ + { OFFSET(gpmc_a3), MODE(7) | PULLUDEN, }, + /* LCD POWER_ENABLE */ + { OFFSET(gpmc_a6), MODE(7) | PULLUDEN, }, + /* LCD Backlight (PWM) */ + { OFFSET(mcasp0_aclkx), MODE(7) | PULLUDEN, }, +}; + +static const struct pin_mux stk5_lcd_pads[] = { + /* LCD data bus */ + { OFFSET(lcd_data0), MODE(0) | PULLUDEN, }, + { OFFSET(lcd_data1), MODE(0) | PULLUDEN, }, + { OFFSET(lcd_data2), MODE(0) | PULLUDEN, }, + { OFFSET(lcd_data3), MODE(0) | PULLUDEN, }, + { OFFSET(lcd_data4), MODE(0) | PULLUDEN, }, + { OFFSET(lcd_data5), MODE(0) | PULLUDEN, }, + { OFFSET(lcd_data6), MODE(0) | PULLUDEN, }, + { OFFSET(lcd_data7), MODE(0) | PULLUDEN, }, + { OFFSET(lcd_data8), MODE(0) | PULLUDEN, }, + { OFFSET(lcd_data9), MODE(0) | PULLUDEN, }, + { OFFSET(lcd_data10), MODE(0) | PULLUDEN, }, + { OFFSET(lcd_data11), MODE(0) | PULLUDEN, }, + { OFFSET(lcd_data12), MODE(0) | PULLUDEN, }, + { OFFSET(lcd_data13), MODE(0) | PULLUDEN, }, + { OFFSET(lcd_data14), MODE(0) | PULLUDEN, }, + { OFFSET(lcd_data15), MODE(0) | PULLUDEN, }, + /* LCD control signals */ + { OFFSET(lcd_hsync), MODE(0) | PULLUDEN, }, + { OFFSET(lcd_vsync), MODE(0) | PULLUDEN, }, + { OFFSET(lcd_pclk), MODE(0) | PULLUDEN, }, + { OFFSET(lcd_ac_bias_en), MODE(0) | PULLUDEN, }, +}; + +static const struct gpio stk5_gpios[] = { + { AM33XX_GPIO_NR(1, 26), GPIOF_OUTPUT_INIT_LOW, "HEARTBEAT LED", }, +}; + +static const struct gpio stk5_lcd_gpios[] = { + { AM33XX_GPIO_NR(1, 19), GPIOF_OUTPUT_INIT_LOW, "LCD RESET", }, + { AM33XX_GPIO_NR(1, 22), GPIOF_OUTPUT_INIT_LOW, "LCD POWER", }, + { AM33XX_GPIO_NR(3, 14), GPIOF_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", }, +}; + +static const struct pin_mux stk5v5_pads[] = { + /* CAN transceiver control */ + { OFFSET(gpmc_ad8), MODE(7) | PULLUDEN, }, +}; + +static const struct gpio stk5v5_gpios[] = { + { AM33XX_GPIO_NR(0, 22), GPIOF_OUTPUT_INIT_HIGH, "CAN XCVR", }, +}; + +#ifdef CONFIG_LCD +static u16 tx48_cmap[256]; +vidinfo_t panel_info = { + /* set to max. size supported by SoC */ + .vl_col = 1366, + .vl_row = 768, + + .vl_bpix = LCD_COLOR24, /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */ + .cmap = tx48_cmap, +}; + +static struct da8xx_panel tx48_lcd_panel = { + .name = "640x480MR@60", + .width = 640, + .height = 480, + .hfp = 12, + .hbp = 144, + .hsw = 30, + .vfp = 10, + .vbp = 35, + .vsw = 3, + .pxl_clk = 25000000, + .invert_pxl_clk = 1, +}; + +void *lcd_base; /* Start of framebuffer memory */ +void *lcd_console_address; /* Start of console buffer */ + +int lcd_line_length; +int lcd_color_fg; +int lcd_color_bg; + +short console_col; +short console_row; + +static int lcd_enabled = 1; + +void lcd_initcolregs(void) +{ +} + +void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue) +{ +} + +void lcd_enable(void) +{ + /* HACK ALERT: + * global variable from common/lcd.c + * Set to 0 here to prevent messages from going to LCD + * rather than serial console + */ + lcd_is_enabled = 0; + + if (lcd_enabled) { + karo_load_splashimage(1); + + gpio_set_value(TX48_LCD_PWR_GPIO, 1); + gpio_set_value(TX48_LCD_RST_GPIO, 1); + udelay(300000); + gpio_set_value(TX48_LCD_BACKLIGHT_GPIO, 0); + } +} + +void lcd_disable(void) +{ + da8xx_fb_disable(); +} + +void lcd_panel_disable(void) +{ + if (lcd_enabled) { + gpio_set_value(TX48_LCD_BACKLIGHT_GPIO, 1); + gpio_set_value(TX48_LCD_PWR_GPIO, 0); + gpio_set_value(TX48_LCD_RST_GPIO, 0); + } +} + +void lcd_ctrl_init(void *lcdbase) +{ + int color_depth = 24; + char *vm; + unsigned long val; + struct da8xx_panel *p = &tx48_lcd_panel; + int refresh = 60; + + if (!lcd_enabled) { + printf("LCD disabled\n"); + return; + } + + if (tstc() || (prm_rstst & PRM_RSTST_WDT1_RST)) { + lcd_enabled = 0; + return; + } + + vm = getenv("video_mode"); + if (vm == NULL) { + lcd_enabled = 0; + return; + } + + strncpy((char *)p->name, vm, sizeof(p->name)); + + val = simple_strtoul(vm, &vm, 0); + if (val != 0) { + if (val > panel_info.vl_col) + val = panel_info.vl_col; + p->width = val; + panel_info.vl_col = val; + } + if (*vm == 'x') { + val = simple_strtoul(vm + 1, &vm, 0); + if (val > panel_info.vl_row) + val = panel_info.vl_row; + p->height = val; + panel_info.vl_row = val; + } + while (*vm != '\0') { + switch (*vm) { + case 'M': + case 'R': + vm++; + break; + + case '-': + color_depth = simple_strtoul(vm + 1, &vm, 10); + break; + + case '@': + refresh = simple_strtoul(vm + 1, &vm, 10); + break; + + default: + debug("Ignoring '%c'\n", *vm); + vm++; + } + } + switch (color_depth) { + case 8: + panel_info.vl_bpix = 3; + break; + + case 16: + panel_info.vl_bpix = 4; + break; + + case 24: + panel_info.vl_bpix = 5; + break; + + default: + printf("Invalid color_depth %u from video_mode '%s'; using default: %u\n", + color_depth, getenv("video_mode"), 24); + } + lcd_line_length = NBITS(panel_info.vl_bpix) / 8 * panel_info.vl_col; + p->pxl_clk = refresh * + (p->width + p->hfp + p->hbp + p->hsw) * + (p->height + p->vfp + p->vbp + p->vsw); + debug("Pixel clock set to %u.%03uMHz\n", + p->pxl_clk / 1000000, p->pxl_clk / 1000 % 1000); + + gpio_request_array(stk5_lcd_gpios, ARRAY_SIZE(stk5_lcd_gpios)); + tx48_set_pin_mux(stk5_lcd_pads, ARRAY_SIZE(stk5_lcd_pads)); + debug("Initializing FB driver\n"); + da8xx_video_init(&tx48_lcd_panel, color_depth); + + if (karo_load_splashimage(0) == 0) { + debug("Initializing LCD controller\n"); + video_hw_init(); + } else { + debug("Skipping initialization of LCD controller\n"); + } +} +#else +#define lcd_enabled 0 +#endif /* CONFIG_LCD */ + +static void stk5_board_init(void) +{ + tx48_set_pin_mux(stk5_pads, ARRAY_SIZE(stk5_pads)); +} + +static void stk5v3_board_init(void) +{ + stk5_board_init(); +} + +static void stk5v5_board_init(void) +{ + stk5_board_init(); + tx48_set_pin_mux(stk5v5_pads, ARRAY_SIZE(stk5v5_pads)); + gpio_request_array(stk5v5_gpios, ARRAY_SIZE(stk5v5_gpios)); +} + +/* called with default environment! */ +int board_init(void) +{ + /* mach type passed to kernel */ +#ifdef CONFIG_OF_LIBFDT + gd->bd->bi_arch_number = -1; +#endif + /* address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; + + return 0; +} + +static void show_reset_cause(u32 prm_rstst) +{ + const char *dlm = ""; + + printf("RESET cause: "); + if (prm_rstst & PRM_RSTST_GLOBAL_COLD_RST) { + printf("%sPOR", dlm); + dlm = " | "; + } + if (prm_rstst & PRM_RSTST_GLOBAL_WARM_SW_RST) { + printf("%sSW", dlm); + dlm = " | "; + } + if (prm_rstst & PRM_RSTST_WDT1_RST) { + printf("%sWATCHDOG", dlm); + dlm = " | "; + } + if (prm_rstst & PRM_RSTST_EXTERNAL_WARM_RST) { + printf("%sWARM", dlm); + dlm = " | "; + } + if (prm_rstst & PRM_RSTST_ICEPICK_RST) { + printf("%sJTAG", dlm); + dlm = " | "; + } + if (*dlm == '\0') + printf("unknown"); + + printf(" RESET\n"); +} + +/* called with default environment! */ +int checkboard(void) +{ + struct prm_device *prmdev = (struct prm_device *)PRM_DEVICE; + + prm_rstst = readl(&prmdev->prmrstst); + show_reset_cause(prm_rstst); + +#ifdef CONFIG_OF_LIBFDT + printf("Board: Ka-Ro TX48-7020 with FDT support\n"); +#else + printf("Board: Ka-Ro TX48-7020\n"); +#endif + timer_init(); + return 0; +} + +/* called with environment from NAND or MMC */ +int board_late_init(void) +{ + const char *baseboard; + +#ifdef CONFIG_OF_BOARD_SETUP + karo_fdt_move_fdt(); +#endif + baseboard = getenv("baseboard"); + if (!baseboard) + return 0; + + if (strncmp(baseboard, "stk5", 4) == 0) { + printf("Baseboard: %s\n", baseboard); + if ((strlen(baseboard) == 4) || + strcmp(baseboard, "stk5-v3") == 0) { + stk5v3_board_init(); + } else if (strcmp(baseboard, "stk5-v5") == 0) { + stk5v5_board_init(); + } else { + printf("WARNING: Unsupported STK5 board rev.: %s\n", + baseboard + 4); + } + } else { + printf("WARNING: Unsupported baseboard: '%s'\n", + baseboard); + return -EINVAL; + } + + return 0; +} + +#ifdef CONFIG_DRIVER_TI_CPSW +static void tx48_phy_init(char *name, int addr) +{ + debug("%s: Resetting ethernet PHY\n", __func__); + + gpio_direction_output(TX48_ETH_PHY_RST_GPIO, 0); + + udelay(100); + + /* Release nRST */ + gpio_set_value(TX48_ETH_PHY_RST_GPIO, 1); + + /* Wait for PHY internal POR signal to deassert */ + udelay(25000); +} + +static void cpsw_control(int enabled) +{ + /* nothing for now */ + /* TODO : VTP was here before */ +} + +static struct cpsw_slave_data cpsw_slaves[] = { + { + .slave_reg_ofs = 0x208, + .sliver_reg_ofs = 0xd80, + .phy_id = 0, + }, +}; + ++void s_init(void) ++{ ++} ++ +static struct cpsw_platform_data cpsw_data = { - .mdio_base = CPSW_MDIO_BASE, - .cpsw_base = CPSW_BASE, ++ .mdio_base = AM335X_CPSW_MDIO_BASE, ++ .cpsw_base = AM335X_CPSW_BASE, + .mdio_div = 0xff, + .channels = 8, + .cpdma_reg_ofs = 0x800, + .slaves = ARRAY_SIZE(cpsw_slaves), + .slave_data = cpsw_slaves, + .ale_reg_ofs = 0xd00, + .ale_entries = 1024, + .host_port_reg_ofs = 0x108, + .hw_stats_reg_ofs = 0x900, + .mac_control = (1 << 5) /* MIIEN */, + .control = cpsw_control, + .phy_init = tx48_phy_init, + .gigabit_en = 0, + .host_port_num = 0, + .version = CPSW_CTRL_VERSION_2, +}; + +int board_eth_init(bd_t *bis) +{ + uint8_t mac_addr[ETH_ALEN]; + uint32_t mac_hi, mac_lo; + + /* try reading mac address from efuse */ + mac_lo = __raw_readl(MAC_ID0_LO); + mac_hi = __raw_readl(MAC_ID0_HI); + + mac_addr[0] = mac_hi & 0xFF; + mac_addr[1] = (mac_hi & 0xFF00) >> 8; + mac_addr[2] = (mac_hi & 0xFF0000) >> 16; + mac_addr[3] = (mac_hi & 0xFF000000) >> 24; + mac_addr[4] = mac_lo & 0xFF; + mac_addr[5] = (mac_lo & 0xFF00) >> 8; + + if (is_valid_ether_addr(mac_addr)) { + debug("MAC addr set to: %02x:%02x:%02x:%02x:%02x:%02x\n", + mac_addr[0], mac_addr[1], mac_addr[2], + mac_addr[3], mac_addr[4], mac_addr[5]); + eth_setenv_enetaddr("ethaddr", mac_addr); + } else { + printf("ERROR: Did not find a valid mac address in e-fuse\n"); + } + + __raw_writel(RMII_MODE_ENABLE, MAC_MII_SEL); + __raw_writel(0x5D, GMII_SEL); + return cpsw_register(&cpsw_data); +} +#endif /* CONFIG_DRIVER_TI_CPSW */ + +#if defined(CONFIG_NAND_AM33XX) && defined(CONFIG_CMD_SWITCH_ECC) +/****************************************************************************** + * Command to switch between NAND HW and SW ecc + *****************************************************************************/ +static int do_switch_ecc(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) +{ + int type = 0; + + if (argc < 2) + goto usage; + + if (strncmp(argv[1], "hw", 2) == 0) { + if (argc == 3) + type = simple_strtoul(argv[2], NULL, 10); + am33xx_nand_switch_ecc(NAND_ECC_HW, type); + } + else if (strncmp(argv[1], "sw", 2) == 0) + am33xx_nand_switch_ecc(NAND_ECC_SOFT, 0); + else + goto usage; + + return 0; + +usage: + printf("Usage: nandecc %s\n", cmdtp->usage); + return 1; +} + +U_BOOT_CMD( + nandecc, 3, 1, do_switch_ecc, + "Switch NAND ECC calculation algorithm b/w hardware and software", + "[sw|hw ] \n" + " [sw|hw]- Switch b/w hardware(hw) & software(sw) ecc algorithm\n" + " hw_type- 0 for Hamming code\n" + " 1 for bch4\n" + " 2 for bch8\n" + " 3 for bch16\n" +); +#endif /* CONFIG_NAND_AM33XX && CONFIG_CMD_SWITCH_ECC */ + +enum { + LED_STATE_INIT = -1, + LED_STATE_OFF, + LED_STATE_ON, +}; + +void show_activity(int arg) +{ + static int led_state = LED_STATE_INIT; + static ulong last; + + if (led_state == LED_STATE_INIT) { + last = get_timer(0); + gpio_set_value(TX48_LED_GPIO, 1); + led_state = LED_STATE_ON; + } else { + if (get_timer(last) > CONFIG_SYS_HZ) { + last = get_timer(0); + if (led_state == LED_STATE_ON) { + gpio_set_value(TX48_LED_GPIO, 0); + } else { + gpio_set_value(TX48_LED_GPIO, 1); + } + led_state = 1 - led_state; + } + } +} + +#ifdef CONFIG_OF_BOARD_SETUP +#ifdef CONFIG_FDT_FIXUP_PARTITIONS +#include +#include +struct node_info nodes[] = { + { "ti,omap2-nand", MTD_DEV_TYPE_NAND, }, +}; + +#else +#define fdt_fixup_mtdparts(b,n,c) do { } while (0) +#endif /* CONFIG_FDT_FIXUP_PARTITIONS */ + +static void tx48_fixup_flexcan(void *blob) +{ + const char *baseboard = getenv("baseboard"); + + if (baseboard && strcmp(baseboard, "stk5-v5") == 0) + return; + + karo_fdt_del_prop(blob, "ti,dcan", 0x481cc000, "can-xcvr-enable"); + karo_fdt_del_prop(blob, "ti,dcan", 0x481d0000, "can-xcvr-enable"); +} + +void ft_board_setup(void *blob, bd_t *bd) +{ + fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes)); + fdt_fixup_ethernet(blob); + + karo_fdt_fixup_touchpanel(blob); + tx48_fixup_flexcan(blob); +} +#endif /* CONFIG_OF_BOARD_SETUP */ diff --cc board/karo/tx48/u-boot.lds index ea4a058777,0000000000..ba7f4eb5d8 mode 100644,000000..100644 --- a/board/karo/tx48/u-boot.lds +++ b/board/karo/tx48/u-boot.lds @@@ -1,92 -1,0 +1,94 @@@ +/* + * Copyright (c) 2004-2008 Texas Instruments + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + .text : + { + __image_copy_start = .; - CPUDIR/start.o (.text) - *(.text) ++ CPUDIR/start.o (.text*) ++ *(.text*) + } + + . = ALIGN(4); + .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } + + . = ALIGN(4); + .data : { - *(.data) ++ *(.data*) + } + + . = ALIGN(4); + + . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; ++ ++ . = ALIGN(4); ++ .u_boot_list : { ++ #include ++ } + + . = ALIGN(4); + + __image_copy_end = .; + + .rel.dyn : { + __rel_dyn_start = .; + *(.rel*) + __rel_dyn_end = .; + } + + .dynsym : { + __dynsym_start = .; + *(.dynsym) + } + + _end = .; + + /* + * Deprecated: this MMU section is used by pxa at present but + * should not be used by new boards/CPUs. + */ + . = ALIGN(4096); + .mmutable : { + *(.mmutable) + } + + .bss __rel_dyn_start (OVERLAY) : { + __bss_start = .; + *(.bss) + . = ALIGN(4); + __bss_end__ = .; + } + + /DISCARD/ : { *(.dynstr*) } + /DISCARD/ : { *(.dynamic*) } + /DISCARD/ : { *(.plt*) } + /DISCARD/ : { *(.interp*) } + /DISCARD/ : { *(.gnu*) } +} diff --cc board/karo/tx51/tx51.c index 180447a179,0000000000..3a611f81f4 mode 100644,000000..100644 --- a/board/karo/tx51/tx51.c +++ b/board/karo/tx51/tx51.c @@@ -1,893 -1,0 +1,859 @@@ +/* + * Copyright (C) 2011 Lothar Waßmann + * based on: board/freescale/mx28_evk.c (C) 2010 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include - #include ++#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "../common/karo.h" + - #define IMX_GPIO_NR(b, o) ((((b) - 1) << 5) | (o)) ++//#define IMX_GPIO_NR(b, o) ((((b) - 1) << 5) | (o)) + +#define TX51_FEC_RST_GPIO IMX_GPIO_NR(2, 14) +#define TX51_FEC_PWR_GPIO IMX_GPIO_NR(1, 3) +#define TX51_FEC_INT_GPIO IMX_GPIO_NR(3, 18) +#define TX51_LED_GPIO IMX_GPIO_NR(4, 10) + +#define TX51_LCD_PWR_GPIO IMX_GPIO_NR(4, 14) +#define TX51_LCD_RST_GPIO IMX_GPIO_NR(4, 13) +#define TX51_LCD_BACKLIGHT_GPIO IMX_GPIO_NR(1, 2) + +#define TX51_RESET_OUT_GPIO IMX_GPIO_NR(2, 15) + +DECLARE_GLOBAL_DATA_PTR; + - #define IOMUX_SION IOMUX_PAD(0, 0, IOMUX_CONFIG_SION, 0, 0, 0) ++#define IOMUX_SION IOMUX_PAD(0, 0, MUX_CONFIG_SION, 0, 0, 0) + - #define FEC_PAD_CTL (PAD_CTL_DVS | PAD_CTL_DSE_HIGH | \ ++#define FEC_PAD_CTRL (PAD_CTL_DVS | PAD_CTL_DSE_HIGH | \ + PAD_CTL_SRE_FAST) - #define FEC_PAD_CTL2 (PAD_CTL_DVS | PAD_CTL_SRE_FAST) - #define GPIO_PAD_CTL (PAD_CTL_DVS | PAD_CTL_DSE_HIGH) ++#define FEC_PAD_CTRL2 (PAD_CTL_DVS | PAD_CTL_SRE_FAST) ++#define GPIO_PAD_CTRL (PAD_CTL_DVS | PAD_CTL_DSE_HIGH) + +static iomux_v3_cfg_t tx51_pads[] = { + /* NAND flash pads are set up in lowlevel_init.S */ + + /* RESET_OUT */ - NEW_PAD_CTRL(MX51_PAD_EIM_A21__GPIO2_15, GPIO_PAD_CTL), ++ MX51_PAD_EIM_A21__GPIO2_15 | GPIO_PAD_CTRL, + + /* UART pads */ +#if CONFIG_MXC_UART_BASE == UART1_BASE + MX51_PAD_UART1_RXD__UART1_RXD, + MX51_PAD_UART1_TXD__UART1_TXD, + MX51_PAD_UART1_RTS__UART1_RTS, + MX51_PAD_UART1_CTS__UART1_CTS, +#endif +#if CONFIG_MXC_UART_BASE == UART2_BASE + MX51_PAD_UART2_RXD__UART2_RXD, + MX51_PAD_UART2_TXD__UART2_TXD, + MX51_PAD_EIM_D26__UART2_RTS, + MX51_PAD_EIM_D25__UART2_CTS, +#endif +#if CONFIG_MXC_UART_BASE == UART3_BASE + MX51_PAD_UART3_RXD__UART3_RXD, + MX51_PAD_UART3_TXD__UART3_TXD, + MX51_PAD_EIM_D18__UART3_RTS, + MX51_PAD_EIM_D17__UART3_CTS, +#endif + /* internal I2C */ + MX51_PAD_I2C1_DAT__GPIO4_17 | IOMUX_SION, + MX51_PAD_I2C1_CLK__GPIO4_16 | IOMUX_SION, + + /* FEC PHY GPIO functions */ - NEW_PAD_CTRL(MX51_PAD_GPIO1_3__GPIO1_3, GPIO_PAD_CTL), /* PHY POWER */ - NEW_PAD_CTRL(MX51_PAD_EIM_A20__GPIO2_14, GPIO_PAD_CTL), /* PHY RESET */ - NEW_PAD_CTRL(MX51_PAD_NANDF_CS2__GPIO3_18, GPIO_PAD_CTL), /* PHY INT */ ++ MX51_PAD_GPIO1_3__GPIO1_3 | GPIO_PAD_CTRL, /* PHY POWER */ ++ MX51_PAD_EIM_A20__GPIO2_14 | GPIO_PAD_CTRL, /* PHY RESET */ ++ MX51_PAD_NANDF_CS2__GPIO3_18 | GPIO_PAD_CTRL, /* PHY INT */ + + /* FEC functions */ - NEW_PAD_CTRL(MX51_PAD_NANDF_CS3__FEC_MDC, FEC_PAD_CTL), - NEW_PAD_CTRL(MX51_PAD_EIM_EB2__FEC_MDIO, FEC_PAD_CTL), - NEW_PAD_CTRL(MX51_PAD_NANDF_D11__FEC_RX_DV, FEC_PAD_CTL2), - NEW_PAD_CTRL(MX51_PAD_EIM_CS4__FEC_RX_ER, FEC_PAD_CTL2), - NEW_PAD_CTRL(MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK, FEC_PAD_CTL2), - NEW_PAD_CTRL(MX51_PAD_NANDF_CS7__FEC_TX_EN, FEC_PAD_CTL), - NEW_PAD_CTRL(MX51_PAD_NANDF_D8__FEC_TDATA0, FEC_PAD_CTL), - NEW_PAD_CTRL(MX51_PAD_NANDF_CS4__FEC_TDATA1, FEC_PAD_CTL), - NEW_PAD_CTRL(MX51_PAD_NANDF_CS5__FEC_TDATA2, FEC_PAD_CTL), - NEW_PAD_CTRL(MX51_PAD_NANDF_CS6__FEC_TDATA3, FEC_PAD_CTL), ++ MX51_PAD_NANDF_CS3__FEC_MDC | FEC_PAD_CTRL, ++ MX51_PAD_EIM_EB2__FEC_MDIO | FEC_PAD_CTRL, ++ MX51_PAD_NANDF_D11__FEC_RX_DV | FEC_PAD_CTRL2, ++ MX51_PAD_EIM_CS4__FEC_RX_ER | FEC_PAD_CTRL2, ++ MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK | FEC_PAD_CTRL2, ++ MX51_PAD_NANDF_CS7__FEC_TX_EN | FEC_PAD_CTRL, ++ MX51_PAD_NANDF_D8__FEC_TDATA0 | FEC_PAD_CTRL, ++ MX51_PAD_NANDF_CS4__FEC_TDATA1 | FEC_PAD_CTRL, ++ MX51_PAD_NANDF_CS5__FEC_TDATA2 | FEC_PAD_CTRL, ++ MX51_PAD_NANDF_CS6__FEC_TDATA3 | FEC_PAD_CTRL, + + /* strap pins for PHY configuration */ - NEW_PAD_CTRL(MX51_PAD_NANDF_RB3__GPIO3_11, GPIO_PAD_CTL), /* RX_CLK/REGOFF */ - NEW_PAD_CTRL(MX51_PAD_NANDF_D9__GPIO3_31, GPIO_PAD_CTL), /* RXD0/Mode0 */ - NEW_PAD_CTRL(MX51_PAD_EIM_EB3__GPIO2_23, GPIO_PAD_CTL), /* RXD1/Mode1 */ - NEW_PAD_CTRL(MX51_PAD_EIM_CS2__GPIO2_27, GPIO_PAD_CTL), /* RXD2/Mode2 */ - NEW_PAD_CTRL(MX51_PAD_EIM_CS3__GPIO2_28, GPIO_PAD_CTL), /* RXD3/nINTSEL */ - NEW_PAD_CTRL(MX51_PAD_NANDF_RB2__GPIO3_10, GPIO_PAD_CTL), /* COL/RMII/CRSDV */ - NEW_PAD_CTRL(MX51_PAD_EIM_CS5__GPIO2_30, GPIO_PAD_CTL), /* CRS/PHYAD4 */ ++ MX51_PAD_NANDF_RB3__GPIO3_11 | GPIO_PAD_CTRL, /* RX_CLK/REGOFF */ ++ MX51_PAD_NANDF_D9__GPIO3_31 | GPIO_PAD_CTRL, /* RXD0/Mode0 */ ++ MX51_PAD_EIM_EB3__GPIO2_23 | GPIO_PAD_CTRL, /* RXD1/Mode1 */ ++ MX51_PAD_EIM_CS2__GPIO2_27 | GPIO_PAD_CTRL, /* RXD2/Mode2 */ ++ MX51_PAD_EIM_CS3__GPIO2_28 | GPIO_PAD_CTRL, /* RXD3/nINTSEL */ ++ MX51_PAD_NANDF_RB2__GPIO3_10 | GPIO_PAD_CTRL, /* COL/RMII/CRSDV */ ++ MX51_PAD_EIM_CS5__GPIO2_30 | GPIO_PAD_CTRL, /* CRS/PHYAD4 */ + + /* unusable pins on TX51 */ + MX51_PAD_GPIO1_0__GPIO1_0, + MX51_PAD_GPIO1_1__GPIO1_1, +}; + +static const struct gpio tx51_gpios[] = { + /* RESET_OUT */ + { TX51_RESET_OUT_GPIO, GPIOF_OUTPUT_INIT_LOW, "RESET_OUT", }, + + /* FEC PHY control GPIOs */ + { TX51_FEC_PWR_GPIO, GPIOF_OUTPUT_INIT_LOW, "FEC POWER", }, /* PHY POWER */ + { TX51_FEC_RST_GPIO, GPIOF_OUTPUT_INIT_LOW, "FEC RESET", }, /* PHY RESET */ + { TX51_FEC_INT_GPIO, GPIOF_INPUT, "FEC PHY INT", }, /* PHY INT (TX_ER) */ + + /* FEC PHY strap pins */ + { IMX_GPIO_NR(3, 11), GPIOF_OUTPUT_INIT_LOW, "FEC PHY REGOFF", }, /* RX_CLK/REGOFF */ + { IMX_GPIO_NR(3, 31), GPIOF_OUTPUT_INIT_LOW, "FEC PHY MODE0", }, /* RXD0/Mode0 */ + { IMX_GPIO_NR(2, 23), GPIOF_OUTPUT_INIT_LOW, "FEC PHY MODE1", }, /* RXD1/Mode1 */ + { IMX_GPIO_NR(2, 27), GPIOF_OUTPUT_INIT_LOW, "FEC PHY MODE2", }, /* RXD2/Mode2 */ + { IMX_GPIO_NR(2, 28), GPIOF_OUTPUT_INIT_LOW, "FEC PHY nINTSEL", }, /* RXD3/nINTSEL */ + { IMX_GPIO_NR(3, 10), GPIOF_OUTPUT_INIT_LOW, "FEC PHY RMII", }, /* COL/RMII/CRSDV */ + { IMX_GPIO_NR(2, 30), GPIOF_OUTPUT_INIT_LOW, "FEC PHY PHYAD4", }, /* CRS/PHYAD4 */ + + /* module internal I2C bus */ + { IMX_GPIO_NR(4, 17), GPIOF_INPUT, "I2C1 SDA", }, + { IMX_GPIO_NR(4, 16), GPIOF_INPUT, "I2C1 SCL", }, + + /* Unconnected pins */ + { IMX_GPIO_NR(1, 0), GPIOF_OUTPUT_INIT_LOW, "N/C", }, + { IMX_GPIO_NR(1, 1), GPIOF_OUTPUT_INIT_LOW, "N/C", }, +}; + +/* + * Functions + */ +#define WRSR_POR (1 << 4) +#define WRSR_TOUT (1 << 1) +#define WRSR_SFTW (1 << 0) + +/* placed in section '.data' to prevent overwriting relocation info + * overlayed with bss + */ +static u32 wrsr __attribute__((section(".data"))); + +static void print_reset_cause(void) +{ + struct src *src_regs = (struct src *)SRC_BASE_ADDR; + void __iomem *wdt_base = (void __iomem *)WDOG1_BASE_ADDR; + u32 srsr; + char *dlm = ""; + + printf("Reset cause: "); + + srsr = readl(&src_regs->srsr); + wrsr = readw(wdt_base + 4); + + if (wrsr & WRSR_POR) { + printf("%sPOR", dlm); + dlm = " | "; + } + if (srsr & 0x00004) { + printf("%sCSU", dlm); + dlm = " | "; + } + if (srsr & 0x00008) { + printf("%sIPP USER", dlm); + dlm = " | "; + } + if (srsr & 0x00010) { + if (wrsr & WRSR_SFTW) { + printf("%sSOFT", dlm); + dlm = " | "; + } + if (wrsr & WRSR_TOUT) { + printf("%sWDOG", dlm); + dlm = " | "; + } + } + if (srsr & 0x00020) { + printf("%sJTAG HIGH-Z", dlm); + dlm = " | "; + } + if (srsr & 0x00040) { + printf("%sJTAG SW", dlm); + dlm = " | "; + } + if (srsr & 0x10000) { + printf("%sWARM BOOT", dlm); + dlm = " | "; + } + if (dlm[0] == '\0') + printf("unknown"); + + printf("\n"); +} + +static void print_cpuinfo(void) +{ + u32 cpurev; + + cpurev = get_cpu_rev(); + + printf("CPU: Freescale i.MX51 rev%d.%d at %d MHz\n", + (cpurev & 0x000F0) >> 4, + (cpurev & 0x0000F) >> 0, + mxc_get_clock(MXC_ARM_CLK) / 1000000); + + print_reset_cause(); +} + +int board_early_init_f(void) +{ + struct mxc_ccm_reg *ccm_regs = (struct mxc_ccm_reg *)MXC_CCM_BASE; + +#ifdef CONFIG_CMD_BOOTCE + /* WinCE fails to enable these clocks */ + writel(readl(&ccm_regs->CCGR2) | 0x0c000000, &ccm_regs->CCGR2); /* usboh3_ipg_ahb */ + writel(readl(&ccm_regs->CCGR4) | 0x30000000, &ccm_regs->CCGR4); /* srtc */ + writel(readl(&ccm_regs->CCGR6) | 0x00000300, &ccm_regs->CCGR6); /* emi_garb */ +#endif + gpio_request_array(tx51_gpios, ARRAY_SIZE(tx51_gpios)); - mxc_iomux_v3_setup_multiple_pads(tx51_pads, ARRAY_SIZE(tx51_pads)); ++ imx_iomux_v3_setup_multiple_pads(tx51_pads, ARRAY_SIZE(tx51_pads)); + + writel(0x77777777, AIPS1_BASE_ADDR + 0x00); + writel(0x77777777, AIPS1_BASE_ADDR + 0x04); + + writel(0x00000000, AIPS1_BASE_ADDR + 0x40); + writel(0x00000000, AIPS1_BASE_ADDR + 0x44); + writel(0x00000000, AIPS1_BASE_ADDR + 0x48); + writel(0x00000000, AIPS1_BASE_ADDR + 0x4c); + writel(0x00000000, AIPS1_BASE_ADDR + 0x50); + + writel(0x77777777, AIPS2_BASE_ADDR + 0x00); + writel(0x77777777, AIPS2_BASE_ADDR + 0x04); + + writel(0x00000000, AIPS2_BASE_ADDR + 0x40); + writel(0x00000000, AIPS2_BASE_ADDR + 0x44); + writel(0x00000000, AIPS2_BASE_ADDR + 0x48); + writel(0x00000000, AIPS2_BASE_ADDR + 0x4c); + writel(0x00000000, AIPS2_BASE_ADDR + 0x50); + + return 0; +} + +int board_init(void) +{ + /* Address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x1000; + return 0; +} + +int dram_init(void) +{ + int ret; + + /* dram_init must store complete ramsize in gd->ram_size */ + gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, + PHYS_SDRAM_1_SIZE); + + ret = mxc_set_clock(CONFIG_SYS_MX5_HCLK, + CONFIG_SYS_SDRAM_CLK, MXC_DDR_CLK); + if (ret) + printf("%s: Failed to set DDR clock to %u MHz: %d\n", __func__, + CONFIG_SYS_SDRAM_CLK, ret); + else + debug("%s: DDR clock set to %u.%03u MHz (desig.: %u.000 MHz)\n", + __func__, mxc_get_clock(MXC_DDR_CLK) / 1000000, + mxc_get_clock(MXC_DDR_CLK) / 1000 % 1000, + CONFIG_SYS_SDRAM_CLK); + return ret; +} + +void dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = get_ram_size((void *)PHYS_SDRAM_1, + PHYS_SDRAM_1_SIZE); +#if CONFIG_NR_DRAM_BANKS > 1 + gd->bd->bi_dram[1].start = PHYS_SDRAM_2; + gd->bd->bi_dram[1].size = get_ram_size((void *)PHYS_SDRAM_2, + PHYS_SDRAM_2_SIZE); +#endif +} + +#ifdef CONFIG_CMD_MMC +int board_mmc_getcd(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = mmc->priv; + + if (cfg->cd_gpio < 0) + return cfg->cd_gpio; + + return !gpio_get_value(cfg->cd_gpio); +} + +static struct fsl_esdhc_cfg esdhc_cfg[] = { + { + .esdhc_base = (void __iomem *)MMC_SDHC1_BASE_ADDR, - .no_snoop = 1, + .cd_gpio = IMX_GPIO_NR(3, 8), + .wp_gpio = -EINVAL, + }, + { + .esdhc_base = (void __iomem *)MMC_SDHC2_BASE_ADDR, - .no_snoop = 1, + .cd_gpio = IMX_GPIO_NR(3, 6), + .wp_gpio = -EINVAL, + }, +}; + +static const iomux_v3_cfg_t mmc0_pads[] = { + MX51_PAD_SD1_CMD__SD1_CMD, + MX51_PAD_SD1_CLK__SD1_CLK, + MX51_PAD_SD1_DATA0__SD1_DATA0, + MX51_PAD_SD1_DATA1__SD1_DATA1, + MX51_PAD_SD1_DATA2__SD1_DATA2, + MX51_PAD_SD1_DATA3__SD1_DATA3, + /* SD1 CD */ - NEW_PAD_CTRL(MX51_PAD_DISPB2_SER_RS__GPIO3_8, - PAD_CTL_PUE | PAD_CTL_PKE), ++ MX51_PAD_DISPB2_SER_RS__GPIO3_8 | MUX_PAD_CTRL(PAD_CTL_PUE | PAD_CTL_PKE), +}; + +static const iomux_v3_cfg_t mmc1_pads[] = { + MX51_PAD_SD2_CMD__SD2_CMD, + MX51_PAD_SD2_CLK__SD2_CLK, + MX51_PAD_SD2_DATA0__SD2_DATA0, + MX51_PAD_SD2_DATA1__SD2_DATA1, + MX51_PAD_SD2_DATA2__SD2_DATA2, + MX51_PAD_SD2_DATA3__SD2_DATA3, + /* SD2 CD */ - NEW_PAD_CTRL(MX51_PAD_DISPB2_SER_DIO__GPIO3_6, - PAD_CTL_PUE | PAD_CTL_PKE), ++ MX51_PAD_DISPB2_SER_DIO__GPIO3_6 | MUX_PAD_CTRL(PAD_CTL_PUE | PAD_CTL_PKE), +}; + +static struct { + const iomux_v3_cfg_t *pads; + int count; +} mmc_pad_config[] = { + { mmc0_pads, ARRAY_SIZE(mmc0_pads), }, + { mmc1_pads, ARRAY_SIZE(mmc1_pads), }, +}; + +int board_mmc_init(bd_t *bis) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(esdhc_cfg); i++) { + struct mmc *mmc; ++ struct fsl_esdhc_cfg *cfg; + + if (i >= CONFIG_SYS_FSL_ESDHC_NUM) + break; + - mxc_iomux_v3_setup_multiple_pads(mmc_pad_config[i].pads, ++ imx_iomux_v3_setup_multiple_pads(mmc_pad_config[i].pads, + mmc_pad_config[i].count); - fsl_esdhc_initialize(bis, &esdhc_cfg[i]); ++ ++ cfg = &esdhc_cfg[i]; ++ cfg->sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); ++ fsl_esdhc_initialize(bis, cfg); + + mmc = find_mmc_device(i); + if (mmc == NULL) + continue; + if (board_mmc_getcd(mmc) > 0) + mmc_init(mmc); + } + return 0; +} +#endif /* CONFIG_CMD_MMC */ + +#ifdef CONFIG_FEC_MXC + +#ifndef ETH_ALEN +#define ETH_ALEN 6 +#endif + +void imx_get_mac_from_fuse(int dev_id, unsigned char *mac) +{ + int i; + struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE; + struct fuse_bank *bank = &iim->bank[1]; + struct fuse_bank1_regs *fuse = (struct fuse_bank1_regs *)bank->fuse_regs; + + if (dev_id > 0) + return; + + for (i = 0; i < ETH_ALEN; i++) + mac[ETH_ALEN - i - 1] = readl(&fuse->mac_addr[i]); +} + +static iomux_v3_cfg_t tx51_fec_pads[] = { + /* reconfigure strap pins for FEC function */ - NEW_PAD_CTRL(MX51_PAD_NANDF_RB3__FEC_RX_CLK, FEC_PAD_CTL2), - NEW_PAD_CTRL(MX51_PAD_NANDF_D9__FEC_RDATA0, FEC_PAD_CTL2), - NEW_PAD_CTRL(MX51_PAD_EIM_EB3__FEC_RDATA1, FEC_PAD_CTL2), - NEW_PAD_CTRL(MX51_PAD_EIM_CS2__FEC_RDATA2, FEC_PAD_CTL2), - NEW_PAD_CTRL(MX51_PAD_EIM_CS3__FEC_RDATA3, FEC_PAD_CTL2), - NEW_PAD_CTRL(MX51_PAD_NANDF_RB2__FEC_COL, FEC_PAD_CTL2), - NEW_PAD_CTRL(MX51_PAD_EIM_CS5__FEC_CRS, FEC_PAD_CTL), ++ MX51_PAD_NANDF_RB3__FEC_RX_CLK | FEC_PAD_CTRL2, ++ MX51_PAD_NANDF_D9__FEC_RDATA0 | FEC_PAD_CTRL2, ++ MX51_PAD_EIM_EB3__FEC_RDATA1 | FEC_PAD_CTRL2, ++ MX51_PAD_EIM_CS2__FEC_RDATA2 | FEC_PAD_CTRL2, ++ MX51_PAD_EIM_CS3__FEC_RDATA3 | FEC_PAD_CTRL2, ++ MX51_PAD_NANDF_RB2__FEC_COL | FEC_PAD_CTRL2, ++ MX51_PAD_EIM_CS5__FEC_CRS | FEC_PAD_CTRL, +}; + +/* take bit 4 of PHY address from configured PHY address or + * set it to 0 if PHYADDR is -1 (probe for PHY) + */ +#define PHYAD4 ((CONFIG_FEC_MXC_PHYADDR >> 4) & !(CONFIG_FEC_MXC_PHYADDR >> 5)) + +static struct gpio tx51_fec_gpios[] = { + { TX51_FEC_PWR_GPIO, GPIOF_OUTPUT_INIT_HIGH, "FEC PHY POWER", }, + { IMX_GPIO_NR(3, 31), GPIOF_OUTPUT_INIT_HIGH, "FEC PHY Mode0", }, /* RXD0/Mode0 */ + { IMX_GPIO_NR(2, 23), GPIOF_OUTPUT_INIT_HIGH, "FEC PHY Mode1", }, /* RXD1/Mode1 */ + { IMX_GPIO_NR(2, 27), GPIOF_OUTPUT_INIT_HIGH, "FEC PHY Mode2", }, /* RXD2/Mode2 */ + { IMX_GPIO_NR(2, 28), GPIOF_OUTPUT_INIT_HIGH, "FEC PHY nINTSEL", }, /* RXD3/nINTSEL */ +#if PHYAD4 + { IMX_GPIO_NR(2, 30), GPIOF_OUTPUT_INIT_HIGH, "FEC PHY PHYAD4", }, /* CRS/PHYAD4 */ +#else + { IMX_GPIO_NR(2, 30), GPIOF_OUTPUT_INIT_LOW, "FEC PHY PHYAD4", }, /* CRS/PHYAD4 */ +#endif +}; + +int board_eth_init(bd_t *bis) +{ + int ret; + unsigned char mac[ETH_ALEN]; + char mac_str[ETH_ALEN * 3] = ""; + + /* Power up the external phy and assert strap options */ + gpio_request_array(tx51_fec_gpios, ARRAY_SIZE(tx51_fec_gpios)); + + /* delay at least 21ms for the PHY internal POR signal to deassert */ + udelay(22000); + + /* Deassert RESET to the external phy */ + gpio_set_value(TX51_FEC_RST_GPIO, 1); + + /* Without this delay the PHY won't work, though nothing in + * the datasheets suggests that it should be necessary! + */ + udelay(400); - mxc_iomux_v3_setup_multiple_pads(tx51_fec_pads, ++ imx_iomux_v3_setup_multiple_pads(tx51_fec_pads, + ARRAY_SIZE(tx51_fec_pads)); + + ret = cpu_eth_init(bis); + if (ret) { + printf("cpu_eth_init() failed: %d\n", ret); + return ret; + } + + imx_get_mac_from_fuse(0, mac); + snprintf(mac_str, sizeof(mac_str), "%02x:%02x:%02x:%02x:%02x:%02x", + mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]); + setenv("ethaddr", mac_str); + + return ret; +} +#endif /* CONFIG_FEC_MXC */ + +enum { + LED_STATE_INIT = -1, + LED_STATE_OFF, + LED_STATE_ON, +}; + +void show_activity(int arg) +{ + static int led_state = LED_STATE_INIT; + static ulong last; + + if (led_state == LED_STATE_INIT) { + last = get_timer(0); + gpio_set_value(TX51_LED_GPIO, 1); + led_state = LED_STATE_ON; + } else { + if (get_timer(last) > CONFIG_SYS_HZ) { + last = get_timer(0); + if (led_state == LED_STATE_ON) { + gpio_set_value(TX51_LED_GPIO, 0); + } else { + gpio_set_value(TX51_LED_GPIO, 1); + } + led_state = 1 - led_state; + } + } +} + +static const iomux_v3_cfg_t stk5_pads[] = { + /* SW controlled LED on STK5 baseboard */ + MX51_PAD_CSI2_D13__GPIO4_10, + + /* USB PHY reset */ + MX51_PAD_GPIO1_4__GPIO1_4, + /* USBOTG OC */ + MX51_PAD_GPIO1_6__GPIO1_6, + /* USB PHY clock enable */ + MX51_PAD_GPIO1_7__GPIO1_7, + /* USBH1 VBUS enable */ + MX51_PAD_GPIO1_8__GPIO1_8, + /* USBH1 OC */ + MX51_PAD_GPIO1_9__GPIO1_9, +}; + +static const struct gpio stk5_gpios[] = { + { TX51_LED_GPIO, GPIOF_OUTPUT_INIT_LOW, "HEARTBEAT LED", }, + + { IMX_GPIO_NR(1, 4), GPIOF_OUTPUT_INIT_LOW, "ULPI PHY clk enable", }, + { IMX_GPIO_NR(1, 6), GPIOF_INPUT, "USBOTG OC", }, + { IMX_GPIO_NR(1, 7), GPIOF_OUTPUT_INIT_LOW, "ULPI PHY reset", }, + { IMX_GPIO_NR(1, 8), GPIOF_OUTPUT_INIT_LOW, "USBH1 VBUS enable", }, + { IMX_GPIO_NR(1, 9), GPIOF_INPUT, "USBH1 OC", }, +}; + +#ifdef CONFIG_LCD +static ushort tx51_cmap[256]; +vidinfo_t panel_info = { + /* set to max. size supported by SoC */ + .vl_col = 1600, + .vl_row = 1200, + + .vl_bpix = LCD_COLOR24, /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */ + .cmap = tx51_cmap, +}; + +static struct fb_videomode tx51_fb_mode = { + /* Standard VGA timing */ + .name = "VGA", + .refresh = 60, + .xres = 640, + .yres = 480, + .pixclock = KHZ2PICOS(25175), + .left_margin = 48, + .hsync_len = 96, + .right_margin = 16, + .upper_margin = 31, + .vsync_len = 2, + .lower_margin = 12, + .sync = FB_SYNC_CLK_LAT_FALL, + .vmode = FB_VMODE_NONINTERLACED, +}; + - void *lcd_base; /* Start of framebuffer memory */ - void *lcd_console_address; /* Start of console buffer */ - - int lcd_line_length; - int lcd_color_fg; - int lcd_color_bg; - - short console_col; - short console_row; - - void lcd_initcolregs(void) - { - } - - void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue) - { - } - +static int lcd_enabled = 1; + +void lcd_enable(void) +{ + /* HACK ALERT: + * global variable from common/lcd.c + * Set to 0 here to prevent messages from going to LCD + * rather than serial console + */ + lcd_is_enabled = 0; + + karo_load_splashimage(1); + if (lcd_enabled) { + debug("Switching LCD on\n"); + gpio_set_value(TX51_LCD_PWR_GPIO, 1); + udelay(100); + gpio_set_value(TX51_LCD_RST_GPIO, 1); + udelay(300000); + gpio_set_value(TX51_LCD_BACKLIGHT_GPIO, 0); + } +} + - void mxcfb_disable(void); - - void lcd_disable(void) - { - mxcfb_disable(); - } - - void lcd_panel_disable(void) - { - if (lcd_enabled) { - debug("Switching LCD off\n"); - gpio_set_value(TX51_LCD_BACKLIGHT_GPIO, 1); - gpio_set_value(TX51_LCD_RST_GPIO, 0); - gpio_set_value(TX51_LCD_PWR_GPIO, 0); - } - } - +static const iomux_v3_cfg_t stk5_lcd_pads[] = { + /* LCD RESET */ + MX51_PAD_CSI2_VSYNC__GPIO4_13, + /* LCD POWER_ENABLE */ + MX51_PAD_CSI2_HSYNC__GPIO4_14, + /* LCD Backlight (PWM) */ + MX51_PAD_GPIO1_2__GPIO1_2, + + /* Display */ + MX51_PAD_DISP1_DAT0__DISP1_DAT0, + MX51_PAD_DISP1_DAT1__DISP1_DAT1, + MX51_PAD_DISP1_DAT2__DISP1_DAT2, + MX51_PAD_DISP1_DAT3__DISP1_DAT3, + MX51_PAD_DISP1_DAT4__DISP1_DAT4, + MX51_PAD_DISP1_DAT5__DISP1_DAT5, + MX51_PAD_DISP1_DAT6__DISP1_DAT6, + MX51_PAD_DISP1_DAT7__DISP1_DAT7, + MX51_PAD_DISP1_DAT8__DISP1_DAT8, + MX51_PAD_DISP1_DAT9__DISP1_DAT9, + MX51_PAD_DISP1_DAT10__DISP1_DAT10, + MX51_PAD_DISP1_DAT11__DISP1_DAT11, + MX51_PAD_DISP1_DAT12__DISP1_DAT12, + MX51_PAD_DISP1_DAT13__DISP1_DAT13, + MX51_PAD_DISP1_DAT14__DISP1_DAT14, + MX51_PAD_DISP1_DAT15__DISP1_DAT15, + MX51_PAD_DISP1_DAT16__DISP1_DAT16, + MX51_PAD_DISP1_DAT17__DISP1_DAT17, + MX51_PAD_DISP1_DAT18__DISP1_DAT18, + MX51_PAD_DISP1_DAT19__DISP1_DAT19, + MX51_PAD_DISP1_DAT20__DISP1_DAT20, + MX51_PAD_DISP1_DAT21__DISP1_DAT21, + MX51_PAD_DISP1_DAT22__DISP1_DAT22, + MX51_PAD_DISP1_DAT23__DISP1_DAT23, + MX51_PAD_DI1_PIN2__DI1_PIN2, /* HSYNC */ + MX51_PAD_DI1_PIN3__DI1_PIN3, /* VSYNC */ +}; + +static const struct gpio stk5_lcd_gpios[] = { + { TX51_LCD_RST_GPIO, GPIOF_OUTPUT_INIT_LOW, "LCD RESET", }, + { TX51_LCD_PWR_GPIO, GPIOF_OUTPUT_INIT_LOW, "LCD POWER", }, + { TX51_LCD_BACKLIGHT_GPIO, GPIOF_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", }, +}; + +void lcd_ctrl_init(void *lcdbase) +{ + int color_depth = 24; + char *vm; + unsigned long val; + int refresh = 60; + struct fb_videomode *p = &tx51_fb_mode; + int xres_set = 0, yres_set = 0, bpp_set = 0, refresh_set = 0; + int pix_fmt = 0; ++ ipu_di_clk_parent_t di_clk_parent = DI_PCLK_PLL3; ++ unsigned long di_clk_rate = 65000000; + + if (!lcd_enabled) { + debug("LCD disabled\n"); + return; + } + + if (tstc() || (wrsr & WRSR_TOUT)) { + debug("Disabling LCD\n"); + lcd_enabled = 0; + return; + } + + vm = getenv("video_mode"); + if (vm == NULL) { + debug("Disabling LCD\n"); + lcd_enabled = 0; + return; + } + while (*vm != '\0') { + if (*vm >= '0' && *vm <= '9') { + char *end; + + val = simple_strtoul(vm, &end, 0); + if (end > vm) { + if (!xres_set) { + if (val > panel_info.vl_col) + val = panel_info.vl_col; + p->xres = val; + panel_info.vl_col = val; + xres_set = 1; + } else if (!yres_set) { + if (val > panel_info.vl_row) + val = panel_info.vl_row; + p->yres = val; + panel_info.vl_row = val; + yres_set = 1; + } else if (!bpp_set) { + switch (val) { + case 8: + case 16: + case 24: + color_depth = val; + break; + + default: + printf("Invalid color depth: '%.*s' in video_mode; using default: '%u'\n", + end - vm, vm, color_depth); + } + bpp_set = 1; + } else if (!refresh_set) { + refresh = val; + refresh_set = 1; + } + } + vm = end; + } + switch (*vm) { + case '@': + bpp_set = 1; + /* fallthru */ + case '-': + yres_set = 1; + /* fallthru */ + case 'x': + xres_set = 1; + /* fallthru */ + case 'M': + case 'R': + vm++; + break; + + default: + if (!pix_fmt) { + char *tmp; + + pix_fmt = IPU_PIX_FMT_RGB24; + tmp = strchr(vm, ':'); + if (tmp) + vm = tmp; + } + if (*vm != '\0') + vm++; + } + } + switch (color_depth) { + case 8: + panel_info.vl_bpix = 3; + break; + + case 16: + panel_info.vl_bpix = 4; + break; + + case 24: + panel_info.vl_bpix = 5; + } - lcd_line_length = NBITS(panel_info.vl_bpix) / 8 * panel_info.vl_col; + + p->pixclock = KHZ2PICOS(refresh * + (p->xres + p->left_margin + p->right_margin + p->hsync_len) * + (p->yres + p->upper_margin + p->lower_margin + p->vsync_len) + / 1000); + debug("Pixel clock set to %lu.%03lu MHz\n", + PICOS2KHZ(p->pixclock) / 1000, + PICOS2KHZ(p->pixclock) % 1000); + + gpio_request_array(stk5_lcd_gpios, ARRAY_SIZE(stk5_lcd_gpios)); - mxc_iomux_v3_setup_multiple_pads(stk5_lcd_pads, ++ imx_iomux_v3_setup_multiple_pads(stk5_lcd_pads, + ARRAY_SIZE(stk5_lcd_pads)); + + debug("Initializing FB driver\n"); + if (!pix_fmt) + pix_fmt = IPU_PIX_FMT_RGB24; + + if (karo_load_splashimage(0) == 0) { + struct mxc_ccm_reg *ccm_regs = (struct mxc_ccm_reg *)MXC_CCM_BASE; + u32 ccgr4 = readl(&ccm_regs->CCGR4); + - debug("Initializing LCD controller\n"); - mx5_fb_init(p, 0, pix_fmt, 1 << panel_info.vl_bpix); - + /* MIPI HSC clock is required for initialization */ + writel(ccgr4 | (3 << 12), &ccm_regs->CCGR4); - video_hw_init(); ++ ++ debug("Initializing LCD controller\n"); ++ ipuv3_fb_init(p, 0, pix_fmt, di_clk_parent, di_clk_rate, -1); ++ + writel(ccgr4 & ~(3 << 12), &ccm_regs->CCGR4); + } else { + debug("Skipping initialization of LCD controller\n"); + } +} +#else +#define lcd_enabled 0 +#endif /* CONFIG_LCD */ + +static void stk5_board_init(void) +{ + gpio_request_array(stk5_gpios, ARRAY_SIZE(stk5_gpios)); - mxc_iomux_v3_setup_multiple_pads(stk5_pads, ARRAY_SIZE(stk5_pads)); ++ imx_iomux_v3_setup_multiple_pads(stk5_pads, ARRAY_SIZE(stk5_pads)); +} + +static void stk5v3_board_init(void) +{ + stk5_board_init(); +} + +static void tx51_set_cpu_clock(void) +{ + unsigned long cpu_clk = getenv_ulong("cpu_clk", 10, 0); + int ret; + + if (tstc() || (wrsr & WRSR_TOUT)) + return; + + if (cpu_clk == 0 || cpu_clk == mxc_get_clock(MXC_ARM_CLK) / 1000000) + return; + + ret = mxc_set_clock(CONFIG_SYS_MX5_HCLK, cpu_clk, MXC_ARM_CLK); + if (ret != 0) { + printf("Error: Failed to set CPU clock to %lu MHz\n", cpu_clk); + return; + } + printf("CPU clock set to %u.%03u MHz\n", + mxc_get_clock(MXC_ARM_CLK) / 1000000, + mxc_get_clock(MXC_ARM_CLK) / 1000 % 1000); +} + +int board_late_init(void) +{ + int ret = 0; + const char *baseboard; + + tx51_set_cpu_clock(); + karo_fdt_move_fdt(); + + baseboard = getenv("baseboard"); + if (!baseboard) + goto exit; + + if (strncmp(baseboard, "stk5", 4) == 0) { + printf("Baseboard: %s\n", baseboard); + if ((strlen(baseboard) == 4) || + strcmp(baseboard, "stk5-v3") == 0) { + stk5v3_board_init(); + } else if (strcmp(baseboard, "stk5-v5") == 0) { + printf("ERROR: Baseboard '%s' incompatible with TX51 module!\n", + baseboard); + stk5v3_board_init(); + } else { + printf("WARNING: Unsupported STK5 board rev.: %s\n", + baseboard + 4); + } + } else { + printf("WARNING: Unsupported baseboard: '%s'\n", + baseboard); + ret = -EINVAL; + } + +exit: + gpio_set_value(TX51_RESET_OUT_GPIO, 1); + return ret; +} + +int checkboard(void) +{ + print_cpuinfo(); + + printf("Board: Ka-Ro TX51-%sxx%s\n", + TX51_MOD_PREFIX, TX51_MOD_SUFFIX); + + return 0; +} + +#if defined(CONFIG_OF_BOARD_SETUP) +#ifdef CONFIG_FDT_FIXUP_PARTITIONS +#include +#include +struct node_info nodes[] = { + { "fsl,imx51-nand", MTD_DEV_TYPE_NAND, }, +}; + +#else +#define fdt_fixup_mtdparts(b,n,c) do { } while (0) +#endif + +void ft_board_setup(void *blob, bd_t *bd) +{ + fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes)); + fdt_fixup_ethernet(blob); + + karo_fdt_fixup_touchpanel(blob); + karo_fdt_fixup_usb_otg(blob, "fsl,imx-otg", 0x73f80000); +} +#endif diff --cc board/karo/tx51/u-boot.lds index 9180f86551,0000000000..5cf498f17e mode 100644,000000..100644 --- a/board/karo/tx51/u-boot.lds +++ b/board/karo/tx51/u-boot.lds @@@ -1,82 -1,0 +1,84 @@@ +/* + * (C) Copyright 2012 Lothar Waßmann + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { - board/karo/tx51/lowlevel_init.o (.text) ++ board/karo/tx51/lowlevel_init.o (.text*) + __image_copy_start = .; - CPUDIR/start.o (.text) - *(.text) ++ CPUDIR/start.o (.text*) ++ *(.text*) + } + + . = ALIGN(4); + .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } + + . = ALIGN(4); + .data : { - *(.data) ++ *(.data*) + } + + . = ALIGN(4); + + . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; ++ ++ . = ALIGN(4); ++ .u_boot_list : { ++ #include ++ } + + . = ALIGN(4); + + __image_copy_end = .; + + .rel.dyn : { + __rel_dyn_start = .; + *(.rel*) + __rel_dyn_end = .; + } + + .dynsym : { + __dynsym_start = .; + *(.dynsym) + } + + _end = .; + + .bss __rel_dyn_start (OVERLAY) : { + __bss_start = .; + *(.bss) + . = ALIGN(4); + __bss_end__ = .; + } + + /DISCARD/ : { *(.dynstr*) } + /DISCARD/ : { *(.dynamic*) } + /DISCARD/ : { *(.plt*) } + /DISCARD/ : { *(.interp*) } + /DISCARD/ : { *(.gnu*) } +} diff --cc board/karo/tx53/lowlevel_init.S index f3a3cc9a32,0000000000..5dc4a964d1 mode 100644,000000..100644 --- a/board/karo/tx53/lowlevel_init.S +++ b/board/karo/tx53/lowlevel_init.S @@@ -1,478 -1,0 +1,478 @@@ +#include +#include +#include + +#define DEBUG_LED_BIT 20 +#define LED_GPIO_BASE GPIO2_BASE_ADDR +#define LED_MUX_OFFSET 0x174 +#define LED_MUX_MODE 0x11 + +#define SDRAM_CLK CONFIG_SYS_SDRAM_CLK + +#ifdef PHYS_SDRAM_2_SIZE +#define SDRAM_SIZE (PHYS_SDRAM_1_SIZE + PHYS_SDRAM_2_SIZE) +#else +#define SDRAM_SIZE PHYS_SDRAM_1_SIZE +#endif + +#define REG_ESDCTL0 0x00 +#define REG_ESDCFG0 0x04 +#define REG_ESDCTL1 0x08 +#define REG_ESDCFG1 0x0c +#define REG_ESDMISC 0x10 +#define REG_ESDSCR 0x14 +#define REG_ESDGPR 0x34 + +#define REG_CCGR0 0x68 +#define REG_CCGR1 0x6c +#define REG_CCGR2 0x70 +#define REG_CCGR3 0x74 +#define REG_CCGR4 0x78 +#define REG_CCGR5 0x7c +#define REG_CCGR6 0x80 +#define REG_CCGR7 0x84 +#define REG_CMEOR 0x88 + +#define CPU_2_BE_32(l) \ + ((((l) << 24) & 0xFF000000) | \ + (((l) << 8) & 0x00FF0000) | \ + (((l) >> 8) & 0x0000FF00) | \ + (((l) >> 24) & 0x000000FF)) + +#define MXC_DCD_ITEM(addr, val) \ + .word CPU_2_BE_32(addr), CPU_2_BE_32(val) + +#define MXC_DCD_CMD_SZ_BYTE 1 +#define MXC_DCD_CMD_SZ_SHORT 2 +#define MXC_DCD_CMD_SZ_WORD 4 +#define MXC_DCD_CMD_FLAG_WRITE 0x0 +#define MXC_DCD_CMD_FLAG_CLR 0x1 +#define MXC_DCD_CMD_FLAG_SET 0x3 +#define MXC_DCD_CMD_FLAG_CHK_ANY (1 << 0) +#define MXC_DCD_CMD_FLAG_CHK_SET (1 << 1) +#define MXC_DCD_CMD_FLAG_CHK_CLR (0 << 1) + +#define MXC_DCD_CMD_WRT(type, flags, next) \ + .word CPU_2_BE_32((0xcc << 24) | (((next) - .) << 8) | ((flags) << 3) | (type)) + +#define MXC_DCD_CMD_CHK(type, flags, addr, mask) \ + .word CPU_2_BE_32((0xcf << 24) | (12 << 8) | ((flags) << 3) | (type)),\ + CPU_2_BE_32(addr), CPU_2_BE_32(mask) + +#define MXC_DCD_CMD_CHK_CNT(type, flags, addr, mask, count) \ + .word CPU_2_BE_32((0xcf << 24) | (16 << 8) | ((flags) << 3) | (type)),\ + CPU_2_BE_32(addr), CPU_2_BE_32(mask), CPU_2_BE_32(count) + +#define MXC_DCD_CMD_NOP() \ + .word CPU_2_BE_32((0xc0 << 24) | (4 << 8)) + +#define CK_TO_NS(ck) (((ck) * 1000 + SDRAM_CLK / 2) / SDRAM_CLK) +#define NS_TO_CK(ns) (((ns) * SDRAM_CLK + 999) / 1000) + + .macro CK_VAL, name, clks, offs, max + .iflt \clks - \offs + .set \name, 0 + .else + .ifle \clks - \offs - \max + .set \name, \clks - \offs + .endif + .endif + .endm + + .macro NS_VAL, name, ns, offs, max + .iflt \ns - \offs + .set \name, 0 + .else + CK_VAL \name, NS_TO_CK(\ns), \offs, \max + .endif + .endm + + .macro CK_MAX, name, ck1, ck2, offs, max + .ifgt \ck1 - \ck2 + CK_VAL \name, \ck1, \offs, \max + .else + CK_VAL \name, \ck2, \offs, \max + .endif + .endm + +#define ESDMISC_DDR_TYPE_DDR3 0 +#define ESDMISC_DDR_TYPE_LPDDR2 1 +#define ESDMISC_DDR_TYPE_DDR2 2 + +#define DIV_ROUND_UP(m,d) (((m) + (d) - 1) / (d)) + +#define CKIL_FREQ_Hz 32768 +#define ESDOR_CLK_PERIOD_ns (1000000000 / CKIL_FREQ_Hz / 2) /* base clock for ESDOR values */ + +/* DDR3 SDRAM */ - #if SDRAM_SIZE > RAM_BANK0_SIZE ++#if SDRAM_SIZE > PHYS_SDRAM_1_SIZE +#define BANK_ADDR_BITS 2 +#else +#define BANK_ADDR_BITS 1 +#endif +#define SDRAM_BURST_LENGTH 8 +#define RALAT 5 +#define WALAT 1 +#define ADDR_MIRROR 0 +#define DDR_TYPE ESDMISC_DDR_TYPE_DDR3 + +/* 512/1024MiB SDRAM: NT5CB128M16P-CG */ +/* ESDCFG0 0x0c */ +NS_VAL tRFC, 160, 1, 255 /* clks - 1 (0..255) */ +CK_MAX tXS, tRFC + 1 + NS_TO_CK(10), 5, 1, 255 /* clks - 1 (0..255) tRFC + 10 */ +CK_MAX tXP, 3, NS_TO_CK(6), 1, 7 /* clks - 1 (0..7) */ /* max(6ns, 3*CK) */ +CK_MAX tXPDLL, NS_TO_CK(24), 2, 1, 15 /* clks - 1 (0..15) */ +NS_VAL tFAW, 45, 1, 31 /* clks - 1 (0..31) */ +CK_VAL tCL, 9, 3, 8 /* clks - 3 (0..8) CAS Latency */ + +/* ESDCFG1 0x10 */ +NS_VAL tRCD, 14, 1, 7 /* clks - 1 (0..7) */ +NS_VAL tRP, 14, 1, 7 /* clks - 1 (0..7) */ +NS_VAL tRC, 50, 1, 31 /* clks - 1 (0..31) */ +NS_VAL tRAS, 36, 1, 31 /* clks - 1 (0..31) */ +CK_VAL tRPA, 0, 0, 1 /* clks (0..1) */ +NS_VAL tWR, 15, 1, 15 /* clks - 1 (0..15) */ +CK_VAL tMRD, 4, 1, 15 /* clks - 1 (0..15) */ +CK_VAL tCWL, 5, 2, 6 /* clks - 2 (0..6) */ + +/* ESDCFG2 0x14 */ +CK_VAL tDLLK, 512, 1, 511 /* clks - 1 (0..511) */ +CK_MAX tRTP, 4, NS_TO_CK(8), 1, 7 /* clks - 1 (0..7) */ +CK_MAX tWTR, 4, NS_TO_CK(8), 1, 7 /* clks - 1 (0..7) */ +CK_MAX tRRD, 4, NS_TO_CK(8), 1, 7 /* clks - 1 (0..7) */ + +/* ESDOR 0x30 */ +CK_MAX tXPR, NS_TO_CK(CK_TO_NS(tRFC + 1) + 10), 5, 1, 255 /* clks - 1 (0..255) max(tRFC + 10, 5CK) */ + +/* ESDOTC 0x08 */ +NS_VAL tAOFPD, 9, 1, 7 /* clks - 1 (0..7) */ +NS_VAL tAONPD, 9, 1, 7 /* clks - 1 (0..7) */ +CK_VAL tANPD, tCWL, 1, 15 /* clks - 1 (0..15) */ +CK_VAL tAXPD, tCWL, 1, 15 /* clks - 1 (0..15) */ +CK_VAL tODTLon tCWL - 1, 1, 7 /* clks - 1 (0..7) */ +CK_VAL tODTLoff tCWL - 1, 1, 31 /* clks - 1 (0..31) */ + +#define tSDE_RST (DIV_ROUND_UP(200000, ESDOR_CLK_PERIOD_ns) + 1) + + /* Add an extra (or two?) ESDOR_CLK_PERIOD_ns according to + * erroneous Erratum Engcm12377 + */ +#define tRST_CKE (DIV_ROUND_UP(500000 + 2 * ESDOR_CLK_PERIOD_ns, ESDOR_CLK_PERIOD_ns) + 1) + +#define ROW_ADDR_BITS 14 +#define COL_ADDR_BITS 10 + + .iflt tWR - 7 + .set mrs_val, (0x8080 | \ + (3 << 4) /* MRS command */ | \ + ((1 << 8) /* DLL Reset */ | \ + ((tWR + 1 - 4) << 9) | \ + (((tCL + 3) - 4) << 4)) << 16) + .else + .set mrs_val, (0x8080 | \ + (3 << 4) /* MRS command */ | \ + ((1 << 8) /* DLL Reset */ | \ + (((tWR + 1) / 2) << 9) | \ + (((tCL + 3) - 4) << 4)) << 16) + .endif +#define ESDSCR_MRS_VAL(cs) (mrs_val | ((cs) << 3)) + +#define ESDCFG0_VAL ( \ + (tRFC << 24) | \ + (tXS << 16) | \ + (tXP << 13) | \ + (tXPDLL << 9) | \ + (tFAW << 4) | \ + (tCL << 0)) \ + +#define ESDCFG1_VAL ( \ + (tRCD << 29) | \ + (tRP << 26) | \ + (tRC << 21) | \ + (tRAS << 16) | \ + (tRPA << 15) | \ + (tWR << 9) | \ + (tMRD << 5) | \ + (tCWL << 0)) \ + +#define ESDCFG2_VAL ( \ + (tDLLK << 16) | \ + (tRTP << 6) | \ + (tWTR << 3) | \ + (tRRD << 0)) + +#define BURST_LEN (SDRAM_BURST_LENGTH / 8) /* 0: 4 byte 1: 8 byte */ +#define ESDCTL_VAL (((ROW_ADDR_BITS - 11) << 24) | \ + ((COL_ADDR_BITS - 9) << 20) | \ + (BURST_LEN << 19) | \ + (1 << 16) | /* SDRAM bus width */ \ + ((-1) << (32 - BANK_ADDR_BITS))) + +#define ESDMISC_VAL ((1 << 12) | \ + (0x3 << 9) | \ + (RALAT << 6) | \ + (WALAT << 16) | \ + (ADDR_MIRROR << 19) | \ + (DDR_TYPE << 3)) + +#define ESDOR_VAL ((tXPR << 16) | (tSDE_RST << 8) | (tRST_CKE << 0)) + +#define ESDOTC_VAL ((tAOFPD << 27) | \ + (tAONPD << 24) | \ + (tANPD << 20) | \ + (tAXPD << 16) | \ + (tODTLon << 12) | \ + (tODTLoff << 4)) + +fcb_start: + b _start + .word 0x20424346 /* "FCB " marker */ + .word 0x01 /* FCB version number */ + .org 0x68 + .word 0x0 /* primary image starting page number */ + .word 0x0 /* secondary image starting page number */ + .word 0x6b + .word 0x6b + .word 0x0 /* DBBT start page (0 == NO DBBT) */ + .word 0 /* Bad block marker offset in main area (unused) */ + .org 0xac + .word 0 /* BI Swap disabled */ + .word 0 /* Bad Block marker offset in spare area */ +fcb_end: + + .org 0x400 +ivt_header: + .word CPU_2_BE_32((0xd1 << 24) | (32 << 8) | 0x40) +app_start_addr: + .long _start + .long 0x0 +dcd_ptr: + .long dcd_hdr +boot_data_ptr: + .word boot_data +self_ptr: + .word ivt_header +app_code_csf: + .word 0x0 + .word 0x0 +boot_data: + .long fcb_start +image_len: + .long CONFIG_U_BOOT_IMG_SIZE +plugin: + .word 0 +ivt_end: +#define DCD_VERSION 0x40 + +dcd_hdr: + .word CPU_2_BE_32((0xd2 << 24) | ((dcd_end - .) << 8) | DCD_VERSION) +dcd_start: + MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, zq_calib) + /* disable all irrelevant clocks */ + MXC_DCD_ITEM(CCM_BASE_ADDR + REG_CCGR0, 0xffcf0fff) + MXC_DCD_ITEM(CCM_BASE_ADDR + REG_CCGR1, 0x000fffc3) + MXC_DCD_ITEM(CCM_BASE_ADDR + REG_CCGR2, 0x033c0000) + MXC_DCD_ITEM(CCM_BASE_ADDR + REG_CCGR3, 0x000000ff) + MXC_DCD_ITEM(CCM_BASE_ADDR + REG_CCGR4, 0x00000000) + MXC_DCD_ITEM(CCM_BASE_ADDR + REG_CCGR5, 0x00fff033) + MXC_DCD_ITEM(CCM_BASE_ADDR + REG_CCGR6, 0x0f00030f) + MXC_DCD_ITEM(CCM_BASE_ADDR + REG_CCGR7, 0xfff00000) + MXC_DCD_ITEM(CCM_BASE_ADDR + REG_CMEOR, 0x00000000) + + MXC_DCD_ITEM(IOMUXC_BASE_ADDR + 0x340, 0x11) /* GPIO_17 => RESET_OUT */ + + MXC_DCD_ITEM(0x63fd800c, 0x00000000) /* M4IF: MUX NFC signals on WEIM */ +#if SDRAM_CLK > 333 + MXC_DCD_ITEM(0x53fd4014, 0x00888944) /* CBCDR */ +#else + MXC_DCD_ITEM(0x53fd4014, 0x00888644) /* CBCDR */ +#endif + MXC_DCD_ITEM(0x53fd4018, 0x00016154) /* CBCMR */ + + MXC_DCD_ITEM(0x53fd401c, 0xa6a2a020) /* CSCMR1 */ + MXC_DCD_ITEM(0x53fd4020, 0xb6b12f0a) /* CSCMR2 */ + MXC_DCD_ITEM(0x53fd4024, 0x00080b18) /* CSCDR1 */ + +#define DDR_SEL_VAL 2 +#define DSE_VAL 5 +#define ODT_VAL 2 + +#define DDR_SEL_SHIFT 25 +#define ODT_SHIFT 22 +#define DSE_SHIFT 19 +#define DDR_INPUT_SHIFT 9 +#define HYS_SHIFT 8 +#define PKE_SHIFT 7 +#define PUE_SHIFT 6 +#define PUS_SHIFT 4 + +#define DDR_SEL_MASK (DDR_SEL_VAL << DDR_SEL_SHIFT) +#define DSE_MASK (DSE_VAL << DSE_SHIFT) +#define ODT_MASK (ODT_VAL << ODT_SHIFT) + +#define DQM_VAL DSE_MASK +#define SDQS_VAL (ODT_MASK | DSE_MASK | (1 << PUE_SHIFT)) +#define SDODT_VAL (DSE_MASK | (0 << PKE_SHIFT) | (1 << PUE_SHIFT) | (0 << PUS_SHIFT)) +#define SDCLK_VAL DSE_MASK +#define SDCKE_VAL ((1 << PKE_SHIFT) | (1 << PUE_SHIFT) | (0 << PUS_SHIFT)) + + MXC_DCD_ITEM(0x53fa8724, DDR_SEL_MASK) /* DDR_TYPE: DDR3 */ + MXC_DCD_ITEM(0x53fa86f4, 0 << DDR_INPUT_SHIFT) /* DDRMODE_CTL */ + MXC_DCD_ITEM(0x53fa8714, 0 << DDR_INPUT_SHIFT) /* GRP_DDRMODE */ + MXC_DCD_ITEM(0x53fa86fc, 1 << PKE_SHIFT) /* GRP_DDRPKE */ + MXC_DCD_ITEM(0x53fa8710, 0 << HYS_SHIFT) /* GRP_DDRHYS */ + MXC_DCD_ITEM(0x53fa8708, 1 << PUE_SHIFT) /* GRP_DDRPK */ + + MXC_DCD_ITEM(0x53fa8584, DQM_VAL) /* DQM0 */ + MXC_DCD_ITEM(0x53fa8594, DQM_VAL) /* DQM1 */ + MXC_DCD_ITEM(0x53fa8560, DQM_VAL) /* DQM2 */ + MXC_DCD_ITEM(0x53fa8554, DQM_VAL) /* DQM3 */ + + MXC_DCD_ITEM(0x53fa857c, SDQS_VAL) /* SDQS0 */ + MXC_DCD_ITEM(0x53fa8590, SDQS_VAL) /* SDQS1 */ + MXC_DCD_ITEM(0x53fa8568, SDQS_VAL) /* SDQS2 */ + MXC_DCD_ITEM(0x53fa8558, SDQS_VAL) /* SDQS3 */ + + MXC_DCD_ITEM(0x53fa8580, SDODT_VAL) /* SDODT0 */ + MXC_DCD_ITEM(0x53fa8578, SDCLK_VAL) /* SDCLK0 */ + + MXC_DCD_ITEM(0x53fa8564, SDODT_VAL) /* SDODT1 */ + MXC_DCD_ITEM(0x53fa8570, SDCLK_VAL) /* SDCLK1 */ + + MXC_DCD_ITEM(0x53fa858c, SDCKE_VAL) /* SDCKE0 */ + MXC_DCD_ITEM(0x53fa855c, SDCKE_VAL) /* SDCKE1 */ + + MXC_DCD_ITEM(0x53fa8574, DSE_MASK) /* DRAM_CAS */ + MXC_DCD_ITEM(0x53fa8588, DSE_MASK) /* DRAM_RAS */ + + MXC_DCD_ITEM(0x53fa86f0, DSE_MASK) /* GRP_ADDDS */ + MXC_DCD_ITEM(0x53fa8720, DSE_MASK) /* GRP_CTLDS */ + MXC_DCD_ITEM(0x53fa8718, DSE_MASK) /* GRP_B0DS */ + MXC_DCD_ITEM(0x53fa871c, DSE_MASK) /* GRP_B1DS */ + MXC_DCD_ITEM(0x53fa8728, DSE_MASK) /* GRP_B2DS */ + MXC_DCD_ITEM(0x53fa872c, DSE_MASK) /* GRP_B3DS */ + + /* calibration defaults */ + MXC_DCD_ITEM(0x63fd904c, 0x001f001f) + MXC_DCD_ITEM(0x63fd9050, 0x001f001f) + MXC_DCD_ITEM(0x63fd907c, 0x011e011e) + MXC_DCD_ITEM(0x63fd9080, 0x011f0120) + MXC_DCD_ITEM(0x63fd9088, 0x3a393d3b) + MXC_DCD_ITEM(0x63fd9090, 0x3f3f3f3f) + + MXC_DCD_ITEM(0x63fd9018, ESDMISC_VAL) + MXC_DCD_ITEM(0x63fd9000, ESDCTL_VAL) + MXC_DCD_ITEM(0x63fd900c, ESDCFG0_VAL) + MXC_DCD_ITEM(0x63fd9010, ESDCFG1_VAL) + MXC_DCD_ITEM(0x63fd9014, ESDCFG2_VAL) + + MXC_DCD_ITEM(0x63fd902c, 0x000026d2) + MXC_DCD_ITEM(0x63fd9030, ESDOR_VAL) + MXC_DCD_ITEM(0x63fd9008, ESDOTC_VAL) + MXC_DCD_ITEM(0x63fd9004, 0x00030012) + + /* MR0 - CS0 */ + MXC_DCD_ITEM(0x63fd901c, 0x00008032) /* MRS: MR2 */ + MXC_DCD_ITEM(0x63fd901c, 0x00008033) /* MRS: MR3 */ + MXC_DCD_ITEM(0x63fd901c, 0x00408031) /* MRS: MR1 */ + MXC_DCD_ITEM(0x63fd901c, ESDSCR_MRS_VAL(0)) /* MRS: MR0 */ + /* MR0 - CS1 */ +#if BANK_ADDR_BITS > 1 + MXC_DCD_ITEM(0x63fd901c, 0x0000803a) /* MRS: MR2 */ + MXC_DCD_ITEM(0x63fd901c, 0x0000803b) /* MRS: MR3 */ + MXC_DCD_ITEM(0x63fd901c, 0x00408039) /* MRS: MR1 */ + MXC_DCD_ITEM(0x63fd901c, ESDSCR_MRS_VAL(1)) /* MRS: MR0 */ +#endif + MXC_DCD_ITEM(0x63fd9020, 0x00005800) /* refresh interval */ + MXC_DCD_ITEM(0x63fd9058, 0x00011112) + + MXC_DCD_ITEM(0x63fd90d0, 0x00000003) /* select default compare pattern for calibration */ + + /* ZQ calibration */ + MXC_DCD_ITEM(0x63fd901c, 0x04008010) /* precharge all */ + MXC_DCD_ITEM(0x63fd901c, 0x00008040) /* MRS: ZQ calibration */ + MXC_DCD_ITEM(0x63fd9040, 0x0539002b) /* Force ZQ calibration */ +zq_calib: + MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, 0, 0x63fd9040, 0x00010000) + MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, wl_calib) + + /* Write Leveling */ + MXC_DCD_ITEM(0x63fd901c, 0x00048033) /* MRS: select MPR */ + MXC_DCD_ITEM(0x63fd901c, 0x00848231) /* MRS: start write leveling */ + MXC_DCD_ITEM(0x63fd901c, 0x00000000) + MXC_DCD_ITEM(0x63fd9048, 0x00000001) +wl_calib: + MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, 0, 0x63fd9048, 0x00000001) + MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, dqs_calib) + MXC_DCD_ITEM(0x63fd901c, 0x00048031) /* MRS: end write leveling */ + MXC_DCD_ITEM(0x63fd901c, 0x00008033) /* MRS: select normal data path */ + + /* DQS calibration */ + MXC_DCD_ITEM(0x63fd901c, 0x04008010) /* precharge all */ + MXC_DCD_ITEM(0x63fd901c, 0x00048033) /* MRS: select MPR */ + MXC_DCD_ITEM(0x63fd907c, 0x90000000) /* reset RD fifo and start DQS calib. */ +dqs_calib: + MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, 0, 0x63fd907c, 0x90000000) + MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, wr_dl_calib) + MXC_DCD_ITEM(0x63fd901c, 0x00008033) /* MRS: select normal data path */ + + /* WR DL calibration */ + MXC_DCD_ITEM(0x63fd901c, 0x00000000) + MXC_DCD_ITEM(0x63fd901c, 0x04008010) /* precharge all */ + MXC_DCD_ITEM(0x63fd901c, 0x00048033) /* MRS: select MPR */ + MXC_DCD_ITEM(0x63fd90a4, 0x00000010) +wr_dl_calib: /* 6c4 */ + MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, 0, 0x63fd90a4, 0x00000010) + MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, rd_dl_calib) + MXC_DCD_ITEM(0x63fd901c, 0x00008033) /* MRS: select normal data path */ + + /* RD DL calibration */ + MXC_DCD_ITEM(0x63fd901c, 0x04008010) /* precharge all */ + MXC_DCD_ITEM(0x63fd901c, 0x00048033) /* MRS: select MPR */ + MXC_DCD_ITEM(0x63fd90a0, 0x00000010) +rd_dl_calib: /* 70c */ + MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, 0, 0x63fd90a0, 0x00000010) + MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, dcd_end) + MXC_DCD_ITEM(0x63fd901c, 0x00008033) /* MRS: select normal data path */ + + MXC_DCD_ITEM(0x63fd901c, 0x00000000) + + MXC_DCD_ITEM(0x53fa8004, 0x00194005) @ set LDO to 1.3V + + /* setup NFC pads */ + /* MUX_SEL */ + MXC_DCD_ITEM(0x53fa819c, 0x00000000) @ EIM_DA0 + MXC_DCD_ITEM(0x53fa81a0, 0x00000000) @ EIM_DA1 + MXC_DCD_ITEM(0x53fa81a4, 0x00000000) @ EIM_DA2 + MXC_DCD_ITEM(0x53fa81a8, 0x00000000) @ EIM_DA3 + MXC_DCD_ITEM(0x53fa81ac, 0x00000000) @ EIM_DA4 + MXC_DCD_ITEM(0x53fa81b0, 0x00000000) @ EIM_DA5 + MXC_DCD_ITEM(0x53fa81b4, 0x00000000) @ EIM_DA6 + MXC_DCD_ITEM(0x53fa81b8, 0x00000000) @ EIM_DA7 + MXC_DCD_ITEM(0x53fa81dc, 0x00000000) @ WE_B + MXC_DCD_ITEM(0x53fa81e0, 0x00000000) @ RE_B + MXC_DCD_ITEM(0x53fa8228, 0x00000000) @ CLE + MXC_DCD_ITEM(0x53fa822c, 0x00000000) @ ALE + MXC_DCD_ITEM(0x53fa8230, 0x00000000) @ WP_B + MXC_DCD_ITEM(0x53fa8234, 0x00000000) @ RB0 + MXC_DCD_ITEM(0x53fa8238, 0x00000000) @ CS0 + /* PAD_CTL */ + MXC_DCD_ITEM(0x53fa84ec, 0x000000e4) @ EIM_DA0 + MXC_DCD_ITEM(0x53fa84f0, 0x000000e4) @ EIM_DA1 + MXC_DCD_ITEM(0x53fa84f4, 0x000000e4) @ EIM_DA2 + MXC_DCD_ITEM(0x53fa84f8, 0x000000e4) @ EIM_DA3 + MXC_DCD_ITEM(0x53fa84fc, 0x000000e4) @ EIM_DA4 + MXC_DCD_ITEM(0x53fa8500, 0x000000e4) @ EIM_DA5 + MXC_DCD_ITEM(0x53fa8504, 0x000000e4) @ EIM_DA6 + MXC_DCD_ITEM(0x53fa8508, 0x000000e4) @ EIM_DA7 + MXC_DCD_ITEM(0x53fa852c, 0x00000004) @ NANDF_WE_B + MXC_DCD_ITEM(0x53fa8530, 0x00000004) @ NANDF_RE_B + MXC_DCD_ITEM(0x53fa85a0, 0x00000004) @ NANDF_CLE_B + MXC_DCD_ITEM(0x53fa85a4, 0x00000004) @ NANDF_ALE_B + MXC_DCD_ITEM(0x53fa85a8, 0x000000e4) @ NANDF_WE_B + MXC_DCD_ITEM(0x53fa85ac, 0x000000e4) @ NANDF_RB0 + MXC_DCD_ITEM(0x53fa85b0, 0x00000004) @ NANDF_CS0 +dcd_end: + .ifgt dcd_end - dcd_start - 1768 + DCD too large! + .endif diff --cc board/karo/tx53/tx53.c index f712c1b8e6,0000000000..250d220953 mode 100644,000000..100644 --- a/board/karo/tx53/tx53.c +++ b/board/karo/tx53/tx53.c @@@ -1,894 -1,0 +1,854 @@@ +/* + * Copyright (C) 2011 Lothar Waßmann + * based on: board/freesclae/mx28_evk.c (C) 2010 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include - #include ++#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "../common/karo.h" + - #define IMX_GPIO_NR(b, o) ((((b) - 1) << 5) | (o)) - +#define TX53_FEC_RST_GPIO IMX_GPIO_NR(7, 6) +#define TX53_FEC_PWR_GPIO IMX_GPIO_NR(3, 20) +#define TX53_FEC_INT_GPIO IMX_GPIO_NR(2, 4) +#define TX53_LED_GPIO IMX_GPIO_NR(2, 20) + +#define TX53_LCD_PWR_GPIO IMX_GPIO_NR(2, 31) +#define TX53_LCD_RST_GPIO IMX_GPIO_NR(3, 29) +#define TX53_LCD_BACKLIGHT_GPIO IMX_GPIO_NR(1, 1) + +#define TX53_RESET_OUT_GPIO IMX_GPIO_NR(7, 12) + +DECLARE_GLOBAL_DATA_PTR; + - #define MX53_GPIO_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ ++#define MX53_GPIO_PAD_CTRL MUX_PAD_CTRL(PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_DSE_HIGH | PAD_CTL_PUS_22K_UP) + - #define TX53_SDHC_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \ ++#define TX53_SDHC_PAD_CTRL MUX_PAD_CTRL(PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \ + PAD_CTL_SRE_FAST | PAD_CTL_PUS_47K_UP) + +static iomux_v3_cfg_t tx53_pads[] = { + /* NAND flash pads are set up in lowlevel_init.S */ + + /* RESET_OUT */ + MX53_PAD_GPIO_17__GPIO7_12, + + /* UART pads */ +#if CONFIG_MXC_UART_BASE == UART1_BASE + MX53_PAD_PATA_DIOW__UART1_TXD_MUX, + MX53_PAD_PATA_DMACK__UART1_RXD_MUX, + MX53_PAD_PATA_IORDY__UART1_RTS, + MX53_PAD_PATA_RESET_B__UART1_CTS, +#endif +#if CONFIG_MXC_UART_BASE == UART2_BASE + MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX, + MX53_PAD_PATA_DMARQ__UART2_TXD_MUX, + MX53_PAD_PATA_DIOR__UART2_RTS, + MX53_PAD_PATA_INTRQ__UART2_CTS, +#endif +#if CONFIG_MXC_UART_BASE == UART3_BASE + MX53_PAD_PATA_CS_0__UART3_TXD_MUX, + MX53_PAD_PATA_CS_1__UART3_RXD_MUX, + MX53_PAD_PATA_DA_2__UART3_RTS, + MX53_PAD_PATA_DA_1__UART3_CTS, +#endif + /* internal I2C */ - NEW_PAD_CTRL(MX53_PAD_EIM_D28__I2C1_SDA, MX53_GPIO_PAD_CTRL), - NEW_PAD_CTRL(MX53_PAD_EIM_D21__I2C1_SCL, MX53_GPIO_PAD_CTRL), ++ MX53_PAD_EIM_D28__I2C1_SDA | MX53_GPIO_PAD_CTRL, ++ MX53_PAD_EIM_D21__I2C1_SCL | MX53_GPIO_PAD_CTRL, + + /* FEC PHY GPIO functions */ + MX53_PAD_EIM_D20__GPIO3_20, /* PHY POWER */ + MX53_PAD_PATA_DA_0__GPIO7_6, /* PHY RESET */ + MX53_PAD_PATA_DATA4__GPIO2_4, /* PHY INT */ + + /* FEC functions */ + MX53_PAD_FEC_MDC__FEC_MDC, + MX53_PAD_FEC_MDIO__FEC_MDIO, + MX53_PAD_FEC_REF_CLK__FEC_TX_CLK, + MX53_PAD_FEC_RX_ER__FEC_RX_ER, + MX53_PAD_FEC_CRS_DV__FEC_RX_DV, + MX53_PAD_FEC_RXD1__FEC_RDATA_1, + MX53_PAD_FEC_RXD0__FEC_RDATA_0, + MX53_PAD_FEC_TX_EN__FEC_TX_EN, + MX53_PAD_FEC_TXD1__FEC_TDATA_1, + MX53_PAD_FEC_TXD0__FEC_TDATA_0, +}; + +static const struct gpio tx53_gpios[] = { + { TX53_RESET_OUT_GPIO, GPIOF_OUTPUT_INIT_HIGH, "#RESET_OUT", }, + { TX53_FEC_PWR_GPIO, GPIOF_OUTPUT_INIT_HIGH, "FEC PHY PWR", }, + { TX53_FEC_RST_GPIO, GPIOF_OUTPUT_INIT_LOW, "FEC PHY RESET", }, + { TX53_FEC_INT_GPIO, GPIOF_INPUT, "FEC PHY INT", }, +}; + +/* + * Functions + */ +/* placed in section '.data' to prevent overwriting relocation info + * overlayed with bss + */ +static u32 wrsr __attribute__((section(".data"))); + +#define WRSR_POR (1 << 4) +#define WRSR_TOUT (1 << 1) +#define WRSR_SFTW (1 << 0) + +static void print_reset_cause(void) +{ + struct src *src_regs = (struct src *)SRC_BASE_ADDR; + void __iomem *wdt_base = (void __iomem *)WDOG1_BASE_ADDR; + u32 srsr; + char *dlm = ""; + + printf("Reset cause: "); + + srsr = readl(&src_regs->srsr); + wrsr = readw(wdt_base + 4); + + if (wrsr & WRSR_POR) { + printf("%sPOR", dlm); + dlm = " | "; + } + if (srsr & 0x00004) { + printf("%sCSU", dlm); + dlm = " | "; + } + if (srsr & 0x00008) { + printf("%sIPP USER", dlm); + dlm = " | "; + } + if (srsr & 0x00010) { + if (wrsr & WRSR_SFTW) { + printf("%sSOFT", dlm); + dlm = " | "; + } + if (wrsr & WRSR_TOUT) { + printf("%sWDOG", dlm); + dlm = " | "; + } + } + if (srsr & 0x00020) { + printf("%sJTAG HIGH-Z", dlm); + dlm = " | "; + } + if (srsr & 0x00040) { + printf("%sJTAG SW", dlm); + dlm = " | "; + } + if (srsr & 0x10000) { + printf("%sWARM BOOT", dlm); + dlm = " | "; + } + if (dlm[0] == '\0') + printf("unknown"); + + printf("\n"); +} + +static void print_cpuinfo(void) +{ + u32 cpurev; + + cpurev = get_cpu_rev(); + + printf("CPU: Freescale i.MX53 rev%d.%d at %d MHz\n", + (cpurev & 0x000F0) >> 4, + (cpurev & 0x0000F) >> 0, + mxc_get_clock(MXC_ARM_CLK) / 1000000); + + print_reset_cause(); +} + +int board_early_init_f(void) +{ + gpio_request_array(tx53_gpios, ARRAY_SIZE(tx53_gpios)); - mxc_iomux_v3_setup_multiple_pads(tx53_pads, ARRAY_SIZE(tx53_pads)); ++ imx_iomux_v3_setup_multiple_pads(tx53_pads, ARRAY_SIZE(tx53_pads)); + + writel(0x77777777, AIPS1_BASE_ADDR + 0x00); + writel(0x77777777, AIPS1_BASE_ADDR + 0x04); + + writel(0x00000000, AIPS1_BASE_ADDR + 0x40); + writel(0x00000000, AIPS1_BASE_ADDR + 0x44); + writel(0x00000000, AIPS1_BASE_ADDR + 0x48); + writel(0x00000000, AIPS1_BASE_ADDR + 0x4c); + writel(0x00000000, AIPS1_BASE_ADDR + 0x50); + + writel(0x77777777, AIPS2_BASE_ADDR + 0x00); + writel(0x77777777, AIPS2_BASE_ADDR + 0x04); + + writel(0x00000000, AIPS2_BASE_ADDR + 0x40); + writel(0x00000000, AIPS2_BASE_ADDR + 0x44); + writel(0x00000000, AIPS2_BASE_ADDR + 0x48); + writel(0x00000000, AIPS2_BASE_ADDR + 0x4c); + writel(0x00000000, AIPS2_BASE_ADDR + 0x50); + + return 0; +} + +int board_init(void) +{ + /* Address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x1000; + return 0; +} + +int dram_init(void) +{ + int ret; + + /* dram_init must store complete ramsize in gd->ram_size */ + gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, + PHYS_SDRAM_1_SIZE); + + ret = mxc_set_clock(CONFIG_SYS_MX5_HCLK, + CONFIG_SYS_SDRAM_CLK, MXC_DDR_CLK); + if (ret) + printf("%s: Failed to set DDR clock to %u MHz: %d\n", __func__, + CONFIG_SYS_SDRAM_CLK, ret); + else + debug("%s: DDR clock set to %u.%03u MHz (desig.: %u.000 MHz)\n", + __func__, mxc_get_clock(MXC_DDR_CLK) / 1000000, + mxc_get_clock(MXC_DDR_CLK) / 1000 % 1000, + CONFIG_SYS_SDRAM_CLK); + return ret; +} + +void dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = get_ram_size((void *)PHYS_SDRAM_1, + PHYS_SDRAM_1_SIZE); +#if CONFIG_NR_DRAM_BANKS > 1 + gd->bd->bi_dram[1].start = PHYS_SDRAM_2; + gd->bd->bi_dram[1].size = get_ram_size((void *)PHYS_SDRAM_2, + PHYS_SDRAM_2_SIZE); +#endif +} + +#ifdef CONFIG_CMD_MMC +int board_mmc_getcd(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = mmc->priv; + + if (cfg->cd_gpio < 0) + return cfg->cd_gpio; + + return !gpio_get_value(cfg->cd_gpio); +} + +static struct fsl_esdhc_cfg esdhc_cfg[] = { + { + .esdhc_base = (void __iomem *)MMC_SDHC1_BASE_ADDR, - .no_snoop = 1, + .cd_gpio = IMX_GPIO_NR(3, 24), + .wp_gpio = -EINVAL, + }, + { + .esdhc_base = (void __iomem *)MMC_SDHC2_BASE_ADDR, - .no_snoop = 1, + .cd_gpio = IMX_GPIO_NR(3, 25), + .wp_gpio = -EINVAL, + }, +}; + +static const iomux_v3_cfg_t mmc0_pads[] = { - NEW_PAD_CTRL(MX53_PAD_SD1_CMD__ESDHC1_CMD, TX53_SDHC_PAD_CTRL), - NEW_PAD_CTRL(MX53_PAD_SD1_CLK__ESDHC1_CLK, TX53_SDHC_PAD_CTRL), - NEW_PAD_CTRL(MX53_PAD_SD1_DATA0__ESDHC1_DAT0, TX53_SDHC_PAD_CTRL), - NEW_PAD_CTRL(MX53_PAD_SD1_DATA1__ESDHC1_DAT1, TX53_SDHC_PAD_CTRL), - NEW_PAD_CTRL(MX53_PAD_SD1_DATA2__ESDHC1_DAT2, TX53_SDHC_PAD_CTRL), - NEW_PAD_CTRL(MX53_PAD_SD1_DATA3__ESDHC1_DAT3, TX53_SDHC_PAD_CTRL), ++ MX53_PAD_SD1_CMD__ESDHC1_CMD | TX53_SDHC_PAD_CTRL, ++ MX53_PAD_SD1_CLK__ESDHC1_CLK | TX53_SDHC_PAD_CTRL, ++ MX53_PAD_SD1_DATA0__ESDHC1_DAT0 | TX53_SDHC_PAD_CTRL, ++ MX53_PAD_SD1_DATA1__ESDHC1_DAT1 | TX53_SDHC_PAD_CTRL, ++ MX53_PAD_SD1_DATA2__ESDHC1_DAT2 | TX53_SDHC_PAD_CTRL, ++ MX53_PAD_SD1_DATA3__ESDHC1_DAT3 | TX53_SDHC_PAD_CTRL, + /* SD1 CD */ - NEW_PAD_CTRL(MX53_PAD_EIM_D24__GPIO3_24, MX53_GPIO_PAD_CTRL), ++ MX53_PAD_EIM_D24__GPIO3_24 | MX53_GPIO_PAD_CTRL, +}; + +static const iomux_v3_cfg_t mmc1_pads[] = { - NEW_PAD_CTRL(MX53_PAD_SD2_CMD__ESDHC2_CMD, TX53_SDHC_PAD_CTRL), - NEW_PAD_CTRL(MX53_PAD_SD2_CLK__ESDHC2_CLK, TX53_SDHC_PAD_CTRL), - NEW_PAD_CTRL(MX53_PAD_SD2_DATA0__ESDHC2_DAT0, TX53_SDHC_PAD_CTRL), - NEW_PAD_CTRL(MX53_PAD_SD2_DATA1__ESDHC2_DAT1, TX53_SDHC_PAD_CTRL), - NEW_PAD_CTRL(MX53_PAD_SD2_DATA2__ESDHC2_DAT2, TX53_SDHC_PAD_CTRL), - NEW_PAD_CTRL(MX53_PAD_SD2_DATA3__ESDHC2_DAT3, TX53_SDHC_PAD_CTRL), ++ MX53_PAD_SD2_CMD__ESDHC2_CMD | TX53_SDHC_PAD_CTRL, ++ MX53_PAD_SD2_CLK__ESDHC2_CLK | TX53_SDHC_PAD_CTRL, ++ MX53_PAD_SD2_DATA0__ESDHC2_DAT0 | TX53_SDHC_PAD_CTRL, ++ MX53_PAD_SD2_DATA1__ESDHC2_DAT1 | TX53_SDHC_PAD_CTRL, ++ MX53_PAD_SD2_DATA2__ESDHC2_DAT2 | TX53_SDHC_PAD_CTRL, ++ MX53_PAD_SD2_DATA3__ESDHC2_DAT3 | TX53_SDHC_PAD_CTRL, + /* SD2 CD */ - NEW_PAD_CTRL(MX53_PAD_EIM_D25__GPIO3_25, MX53_GPIO_PAD_CTRL), ++ MX53_PAD_EIM_D25__GPIO3_25 | MX53_GPIO_PAD_CTRL, +}; + +static struct { + const iomux_v3_cfg_t *pads; + int count; +} mmc_pad_config[] = { + { mmc0_pads, ARRAY_SIZE(mmc0_pads), }, + { mmc1_pads, ARRAY_SIZE(mmc1_pads), }, +}; + +int board_mmc_init(bd_t *bis) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(esdhc_cfg); i++) { + struct mmc *mmc; + + if (i >= CONFIG_SYS_FSL_ESDHC_NUM) + break; + - mxc_iomux_v3_setup_multiple_pads(mmc_pad_config[i].pads, ++ imx_iomux_v3_setup_multiple_pads(mmc_pad_config[i].pads, + mmc_pad_config[i].count); + fsl_esdhc_initialize(bis, &esdhc_cfg[i]); + + mmc = find_mmc_device(i); + if (mmc == NULL) + continue; + if (board_mmc_getcd(mmc) > 0) + mmc_init(mmc); + } + return 0; +} +#endif /* CONFIG_CMD_MMC */ + +#ifdef CONFIG_FEC_MXC + +#ifndef ETH_ALEN +#define ETH_ALEN 6 +#endif + +void imx_get_mac_from_fuse(int dev_id, unsigned char *mac) +{ + int i; + struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE; + struct fuse_bank *bank = &iim->bank[1]; + struct fuse_bank1_regs *fuse = (struct fuse_bank1_regs *)bank->fuse_regs; + + if (dev_id > 0) + return; + + for (i = 0; i < ETH_ALEN; i++) + mac[i] = readl(&fuse->mac_addr[i]); +} + +#define FEC_PAD_CTL (PAD_CTL_DVS | PAD_CTL_DSE_HIGH | \ + PAD_CTL_SRE_FAST) +#define FEC_PAD_CTL2 (PAD_CTL_DVS | PAD_CTL_SRE_FAST) +#define GPIO_PAD_CTL (PAD_CTL_DVS | PAD_CTL_DSE_HIGH) + +int board_eth_init(bd_t *bis) +{ + int ret; + unsigned char mac[ETH_ALEN]; + char mac_str[ETH_ALEN * 3] = ""; + + /* delay at least 21ms for the PHY internal POR signal to deassert */ + udelay(22000); + + /* Deassert RESET to the external phy */ + gpio_set_value(TX53_FEC_RST_GPIO, 1); + + ret = cpu_eth_init(bis); + if (ret) { + printf("cpu_eth_init() failed: %d\n", ret); + return ret; + } + + imx_get_mac_from_fuse(0, mac); + snprintf(mac_str, sizeof(mac_str), "%02x:%02x:%02x:%02x:%02x:%02x", + mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]); + setenv("ethaddr", mac_str); + + return ret; +} +#endif /* CONFIG_FEC_MXC */ + +enum { + LED_STATE_INIT = -1, + LED_STATE_OFF, + LED_STATE_ON, +}; + +void show_activity(int arg) +{ + static int led_state = LED_STATE_INIT; + static ulong last; + + if (led_state == LED_STATE_INIT) { + last = get_timer(0); + gpio_set_value(TX53_LED_GPIO, 1); + led_state = LED_STATE_ON; + } else { + if (get_timer(last) > CONFIG_SYS_HZ) { + last = get_timer(0); + if (led_state == LED_STATE_ON) { + gpio_set_value(TX53_LED_GPIO, 0); + } else { + gpio_set_value(TX53_LED_GPIO, 1); + } + led_state = 1 - led_state; + } + } +} + +static const iomux_v3_cfg_t stk5_pads[] = { + /* SW controlled LED on STK5 baseboard */ + MX53_PAD_EIM_A18__GPIO2_20, + + /* I2C bus on DIMM pins 40/41 */ - NEW_PAD_CTRL(MX53_PAD_GPIO_6__I2C3_SDA, MX53_GPIO_PAD_CTRL), - NEW_PAD_CTRL(MX53_PAD_GPIO_3__I2C3_SCL, MX53_GPIO_PAD_CTRL), ++ MX53_PAD_GPIO_6__I2C3_SDA | MX53_GPIO_PAD_CTRL, ++ MX53_PAD_GPIO_3__I2C3_SCL | MX53_GPIO_PAD_CTRL, + + /* TSC200x PEN IRQ */ - NEW_PAD_CTRL(MX53_PAD_EIM_D26__GPIO3_26, MX53_GPIO_PAD_CTRL), ++ MX53_PAD_EIM_D26__GPIO3_26 | MX53_GPIO_PAD_CTRL, + + /* EDT-FT5x06 Polytouch panel */ - NEW_PAD_CTRL(MX53_PAD_NANDF_CS2__GPIO6_15, MX53_GPIO_PAD_CTRL), /* IRQ */ - NEW_PAD_CTRL(MX53_PAD_EIM_A16__GPIO2_22, MX53_GPIO_PAD_CTRL), /* RESET */ - NEW_PAD_CTRL(MX53_PAD_EIM_A17__GPIO2_21, MX53_GPIO_PAD_CTRL), /* WAKE */ ++ MX53_PAD_NANDF_CS2__GPIO6_15 | MX53_GPIO_PAD_CTRL, /* IRQ */ ++ MX53_PAD_EIM_A16__GPIO2_22 | MX53_GPIO_PAD_CTRL, /* RESET */ ++ MX53_PAD_EIM_A17__GPIO2_21 | MX53_GPIO_PAD_CTRL, /* WAKE */ + + /* USBH1 */ - NEW_PAD_CTRL(MX53_PAD_EIM_D31__GPIO3_31, MX53_GPIO_PAD_CTRL), /* VBUSEN */ - NEW_PAD_CTRL(MX53_PAD_EIM_D30__GPIO3_30, MX53_GPIO_PAD_CTRL), /* OC */ ++ MX53_PAD_EIM_D31__GPIO3_31 | MX53_GPIO_PAD_CTRL, /* VBUSEN */ ++ MX53_PAD_EIM_D30__GPIO3_30 | MX53_GPIO_PAD_CTRL, /* OC */ + /* USBOTG */ + MX53_PAD_GPIO_7__GPIO1_7, /* VBUSEN */ + MX53_PAD_GPIO_8__GPIO1_8, /* OC */ + + /* DS1339 Interrupt */ - NEW_PAD_CTRL(MX53_PAD_DI0_PIN4__GPIO4_20, MX53_GPIO_PAD_CTRL), ++ MX53_PAD_DI0_PIN4__GPIO4_20 | MX53_GPIO_PAD_CTRL, +}; + +static const struct gpio stk5_gpios[] = { + { TX53_LED_GPIO, GPIOF_OUTPUT_INIT_LOW, "HEARTBEAT LED", }, + + { IMX_GPIO_NR(1, 8), GPIOF_INPUT, "USBOTG OC", }, + { IMX_GPIO_NR(1, 7), GPIOF_OUTPUT_INIT_LOW, "USBOTG VBUS enable", }, + { IMX_GPIO_NR(3, 30), GPIOF_INPUT, "USBH1 OC", }, + { IMX_GPIO_NR(3, 31), GPIOF_OUTPUT_INIT_LOW, "USBH1 VBUS enable", }, +}; + +#ifdef CONFIG_LCD +static ushort tx53_cmap[256]; +vidinfo_t panel_info = { + /* set to max. size supported by SoC */ + .vl_col = 1600, + .vl_row = 1200, + + .vl_bpix = LCD_COLOR24, /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */ + .cmap = tx53_cmap, +}; + +static struct fb_videomode tx53_fb_mode = { + /* Standard VGA timing */ + .name = "VGA", + .refresh = 60, + .xres = 640, + .yres = 480, + .pixclock = KHZ2PICOS(25175), + .left_margin = 48, + .hsync_len = 96, + .right_margin = 16, + .upper_margin = 31, + .vsync_len = 2, + .lower_margin = 12, + .sync = FB_SYNC_CLK_LAT_FALL, + .vmode = FB_VMODE_NONINTERLACED, +}; + - void *lcd_base; /* Start of framebuffer memory */ - void *lcd_console_address; /* Start of console buffer */ - - int lcd_line_length; - int lcd_color_fg; - int lcd_color_bg; - - short console_col; - short console_row; - - void lcd_initcolregs(void) - { - } - - void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue) - { - } - +static int lcd_enabled = 1; + +void lcd_enable(void) +{ + /* HACK ALERT: + * global variable from common/lcd.c + * Set to 0 here to prevent messages from going to LCD + * rather than serial console + */ + lcd_is_enabled = 0; + + karo_load_splashimage(1); + if (lcd_enabled) { + debug("Switching LCD on\n"); + gpio_set_value(TX53_LCD_PWR_GPIO, 1); + udelay(100); + gpio_set_value(TX53_LCD_RST_GPIO, 1); + udelay(300000); + gpio_set_value(TX53_LCD_BACKLIGHT_GPIO, 0); + } +} + - void mxcfb_disable(void); - - void lcd_disable(void) - { - mxcfb_disable(); - } - - void lcd_panel_disable(void) - { - if (lcd_enabled) { - debug("Switching LCD off\n"); - gpio_set_value(TX53_LCD_BACKLIGHT_GPIO, 1); - gpio_set_value(TX53_LCD_RST_GPIO, 0); - gpio_set_value(TX53_LCD_PWR_GPIO, 0); - } - } - +static const iomux_v3_cfg_t stk5_lcd_pads[] = { + /* LCD RESET */ - NEW_PAD_CTRL(MX53_PAD_EIM_D29__GPIO3_29, MX53_GPIO_PAD_CTRL), ++ MX53_PAD_EIM_D29__GPIO3_29 | MX53_GPIO_PAD_CTRL, + /* LCD POWER_ENABLE */ - NEW_PAD_CTRL(MX53_PAD_EIM_EB3__GPIO2_31, MX53_GPIO_PAD_CTRL), ++ MX53_PAD_EIM_EB3__GPIO2_31 | MX53_GPIO_PAD_CTRL, + /* LCD Backlight (PWM) */ - NEW_PAD_CTRL(MX53_PAD_GPIO_1__GPIO1_1, MX53_GPIO_PAD_CTRL), ++ MX53_PAD_GPIO_1__GPIO1_1 | MX53_GPIO_PAD_CTRL, + + /* Display */ + MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK, + MX53_PAD_DI0_PIN15__IPU_DI0_PIN15, + MX53_PAD_DI0_PIN2__IPU_DI0_PIN2, + MX53_PAD_DI0_PIN3__IPU_DI0_PIN3, + MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0, + MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1, + MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2, + MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3, + MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4, + MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5, + MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6, + MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7, + MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8, + MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9, + MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10, + MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11, + MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12, + MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13, + MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14, + MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15, + MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16, + MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17, + MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18, + MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19, + MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20, + MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21, + MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22, + MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23, + + /* LVDS option */ + MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3, + MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2, + MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK, + MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1, + MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0, + MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3, + MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK, + MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2, + MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1, + MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0, +}; + +static const struct gpio stk5_lcd_gpios[] = { + { TX53_LCD_RST_GPIO, GPIOF_OUTPUT_INIT_LOW, "LCD RESET", }, + { TX53_LCD_PWR_GPIO, GPIOF_OUTPUT_INIT_LOW, "LCD POWER", }, + { TX53_LCD_BACKLIGHT_GPIO, GPIOF_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", }, +}; + +void lcd_ctrl_init(void *lcdbase) +{ + int color_depth = 24; + char *vm; + unsigned long val; + int refresh = 60; + struct fb_videomode *p = &tx53_fb_mode; + int xres_set = 0, yres_set = 0, bpp_set = 0, refresh_set = 0; + int pix_fmt = 0; ++ ipu_di_clk_parent_t di_clk_parent = DI_PCLK_PLL3; ++ unsigned long di_clk_rate = 65000000; + + if (!lcd_enabled) { + debug("LCD disabled\n"); + return; + } + + if (tstc() || (wrsr & WRSR_TOUT)) { + debug("Disabling LCD\n"); + lcd_enabled = 0; + return; + } + + vm = getenv("video_mode"); + if (vm == NULL) { + debug("Disabling LCD\n"); + lcd_enabled = 0; + return; + } + while (*vm != '\0') { + if (*vm >= '0' && *vm <= '9') { + char *end; + + val = simple_strtoul(vm, &end, 0); + if (end > vm) { + if (!xres_set) { + if (val > panel_info.vl_col) + val = panel_info.vl_col; + p->xres = val; + panel_info.vl_col = val; + xres_set = 1; + } else if (!yres_set) { + if (val > panel_info.vl_row) + val = panel_info.vl_row; + p->yres = val; + panel_info.vl_row = val; + yres_set = 1; + } else if (!bpp_set) { + switch (val) { + case 24: + if (pix_fmt == IPU_PIX_FMT_LVDS666) + pix_fmt = IPU_PIX_FMT_LVDS888; + /* fallthru */ + case 16: + case 8: + color_depth = val; + break; + + case 18: + if (pix_fmt == IPU_PIX_FMT_LVDS666) { + color_depth = val; + break; + } + /* fallthru */ + default: + printf("Invalid color depth: '%.*s' in video_mode; using default: '%u'\n", + end - vm, vm, color_depth); + } + bpp_set = 1; + } else if (!refresh_set) { + refresh = val; + refresh_set = 1; + } + } + vm = end; + } + switch (*vm) { + case '@': + bpp_set = 1; + /* fallthru */ + case '-': + yres_set = 1; + /* fallthru */ + case 'x': + xres_set = 1; + /* fallthru */ + case 'M': + case 'R': + vm++; + break; + + default: + if (!pix_fmt) { + char *tmp; + - if (strncmp(vm, "LVDS", 4) == 0) ++ if (strncmp(vm, "LVDS", 4) == 0) { + pix_fmt = IPU_PIX_FMT_LVDS666; - else ++ di_clk_parent = DI_PCLK_LDB; ++ } else { + pix_fmt = IPU_PIX_FMT_RGB24; ++ } + tmp = strchr(vm, ':'); + if (tmp) + vm = tmp; + } + if (*vm != '\0') + vm++; + } + } + switch (color_depth) { + case 8: + panel_info.vl_bpix = 3; + break; + + case 16: + panel_info.vl_bpix = 4; + break; + + case 18: + case 24: + panel_info.vl_bpix = 5; + } - lcd_line_length = NBITS(panel_info.vl_bpix) / 8 * panel_info.vl_col; + + p->pixclock = KHZ2PICOS(refresh * + (p->xres + p->left_margin + p->right_margin + p->hsync_len) * + (p->yres + p->upper_margin + p->lower_margin + p->vsync_len) + / 1000); + debug("Pixel clock set to %lu.%03lu MHz\n", + PICOS2KHZ(p->pixclock) / 1000, + PICOS2KHZ(p->pixclock) % 1000); + + gpio_request_array(stk5_lcd_gpios, ARRAY_SIZE(stk5_lcd_gpios)); - mxc_iomux_v3_setup_multiple_pads(stk5_lcd_pads, ++ imx_iomux_v3_setup_multiple_pads(stk5_lcd_pads, + ARRAY_SIZE(stk5_lcd_pads)); + + debug("Initializing FB driver\n"); + if (!pix_fmt) + pix_fmt = IPU_PIX_FMT_RGB24; + else if (pix_fmt == IPU_PIX_FMT_LVDS666) { + writel(0x01, IOMUXC_BASE_ADDR + 8); + } else if (pix_fmt == IPU_PIX_FMT_LVDS888) { + writel(0x21, IOMUXC_BASE_ADDR + 8); + } + if (pix_fmt != IPU_PIX_FMT_RGB24) { - struct mxc_ccm_reg *ccm_regs = (struct mxc_ccm_reg *)MXC_CCM_BASE; ++ struct mxc_ccm_reg *ccm_regs = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + /* enable LDB & DI0 clock */ + writel(readl(&ccm_regs->CCGR6) | (3 << 28) | (3 << 10), + &ccm_regs->CCGR6); + } + - mx5_fb_init(p, 0, pix_fmt, 1 << panel_info.vl_bpix); - + if (karo_load_splashimage(0) == 0) { ++ ipuv3_fb_init(p, 0, pix_fmt, di_clk_parent, di_clk_rate, -1); ++ + debug("Initializing LCD controller\n"); - video_hw_init(); ++// video_hw_init(); + } else { + debug("Skipping initialization of LCD controller\n"); + } +} +#else +#define lcd_enabled 0 +#endif /* CONFIG_LCD */ + +static void stk5_board_init(void) +{ + gpio_request_array(stk5_gpios, ARRAY_SIZE(stk5_gpios)); - mxc_iomux_v3_setup_multiple_pads(stk5_pads, ARRAY_SIZE(stk5_pads)); ++ imx_iomux_v3_setup_multiple_pads(stk5_pads, ARRAY_SIZE(stk5_pads)); +} + +static void stk5v3_board_init(void) +{ + stk5_board_init(); +} + +static void stk5v5_board_init(void) +{ + stk5_board_init(); + + gpio_request_one(IMX_GPIO_NR(4, 21), GPIOF_OUTPUT_INIT_HIGH, + "Flexcan Transceiver"); - mxc_iomux_v3_setup_pad(MX53_PAD_DISP0_DAT0__GPIO4_21); ++ imx_iomux_v3_setup_pad(MX53_PAD_DISP0_DAT0__GPIO4_21); +} + +static void tx53_set_cpu_clock(void) +{ + unsigned long cpu_clk = getenv_ulong("cpu_clk", 10, 0); + int ret; + + if (tstc() || (wrsr & WRSR_TOUT)) + return; + + if (cpu_clk == 0 || cpu_clk == mxc_get_clock(MXC_ARM_CLK) / 1000000) + return; + + ret = mxc_set_clock(CONFIG_SYS_MX5_HCLK, cpu_clk, MXC_ARM_CLK); + if (ret != 0) { + printf("Error: Failed to set CPU clock to %lu MHz\n", cpu_clk); + return; + } + printf("CPU clock set to %u.%03u MHz\n", + mxc_get_clock(MXC_ARM_CLK) / 1000000, + mxc_get_clock(MXC_ARM_CLK) / 1000 % 1000); +} + +int board_late_init(void) +{ + int ret = 0; + const char *baseboard; + + tx53_set_cpu_clock(); + karo_fdt_move_fdt(); + + baseboard = getenv("baseboard"); + if (!baseboard) + goto exit; + + if (strncmp(baseboard, "stk5", 4) == 0) { + printf("Baseboard: %s\n", baseboard); + if ((strlen(baseboard) == 4) || + strcmp(baseboard, "stk5-v3") == 0) { + stk5v3_board_init(); + } else if (strcmp(baseboard, "stk5-v5") == 0) { + stk5v5_board_init(); + } else { + printf("WARNING: Unsupported STK5 board rev.: %s\n", + baseboard + 4); + } + } else { + printf("WARNING: Unsupported baseboard: '%s'\n", + baseboard); + ret = -EINVAL; + } + +exit: + gpio_set_value(TX53_RESET_OUT_GPIO, 1); + return ret; +} + +int checkboard(void) +{ + print_cpuinfo(); + + printf("Board: Ka-Ro TX53-xx3%s\n", + TX53_MOD_SUFFIX); + + return 0; +} + +#if defined(CONFIG_OF_BOARD_SETUP) +#ifdef CONFIG_FDT_FIXUP_PARTITIONS +#include +#include +struct node_info nodes[] = { + { "fsl,imx53-nand", MTD_DEV_TYPE_NAND, }, +}; + +#else +#define fdt_fixup_mtdparts(b,n,c) do { } while (0) +#endif + +static void tx53_fixup_flexcan(void *blob) +{ + const char *baseboard = getenv("baseboard"); + + if (baseboard && strcmp(baseboard, "stk5-v5") == 0) + return; + + karo_fdt_del_prop(blob, "fsl,p1010-flexcan", 0x53fc8000, "transceiver-switch"); + karo_fdt_del_prop(blob, "fsl,p1010-flexcan", 0x53fcc000, "transceiver-switch"); +} + +#ifdef CONFIG_SYS_TX53_HWREV_2 +void tx53_fixup_rtc(void *blob) +{ + karo_fdt_del_prop(blob, "dallas,ds1339", 0x68, "interrupt-parent"); + karo_fdt_del_prop(blob, "dallas,ds1339", 0x68, "interrupts"); +} +#else +static inline void tx53_fixup_rtc(void *blob) +{ +} +#endif + +void ft_board_setup(void *blob, bd_t *bd) +{ + fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes)); + fdt_fixup_ethernet(blob); + + karo_fdt_enable_node(blob, "ipu", getenv("video_mode") != NULL); + karo_fdt_fixup_touchpanel(blob); + karo_fdt_fixup_usb_otg(blob, "fsl,imx-otg", 0x53f80000); + tx53_fixup_flexcan(blob); + tx53_fixup_rtc(blob); +} +#endif diff --cc board/karo/tx53/u-boot.lds index 7842ff83a9,0000000000..f22babd521 mode 100644,000000..100644 --- a/board/karo/tx53/u-boot.lds +++ b/board/karo/tx53/u-boot.lds @@@ -1,82 -1,0 +1,84 @@@ +/* + * (C) Copyright 2012 Lothar Waßmann + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { - board/karo/tx53/lowlevel_init.o (.text) ++ board/karo/tx53/lowlevel_init.o (.text*) + __image_copy_start = .; - CPUDIR/start.o (.text) - *(.text) ++ CPUDIR/start.o (.text*) ++ *(.text*) + } + + . = ALIGN(4); + .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } + + . = ALIGN(4); + .data : { - *(.data) ++ *(.data*) + } + + . = ALIGN(4); + + . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; ++ ++ . = ALIGN(4); ++ .u_boot_list : { ++ #include ++ } + + . = ALIGN(4); + + __image_copy_end = .; + + .rel.dyn : { + __rel_dyn_start = .; + *(.rel*) + __rel_dyn_end = .; + } + + .dynsym : { + __dynsym_start = .; + *(.dynsym) + } + + _end = .; + + .bss __rel_dyn_start (OVERLAY) : { + __bss_start = .; + *(.bss) + . = ALIGN(4); + __bss_end__ = .; + } + + /DISCARD/ : { *(.dynstr*) } + /DISCARD/ : { *(.dynamic*) } + /DISCARD/ : { *(.plt*) } + /DISCARD/ : { *(.interp*) } + /DISCARD/ : { *(.gnu*) } +} diff --cc board/karo/tx6q/Makefile index 0000000000,0000000000..34c2737c54 new file mode 100644 --- /dev/null +++ b/board/karo/tx6q/Makefile @@@ -1,0 -1,0 +1,51 @@@ ++# ++# (C) Copyright 2009 DENX Software Engineering ++# Author: John Rigby ++# ++# See file CREDITS for list of people who contributed to this ++# project. ++# ++# This program is free software; you can redistribute it and/or ++# modify it under the terms of the GNU General Public License as ++# published by the Free Software Foundation; either version 2 of ++# the License, or (at your option) any later version. ++# ++# This program is distributed in the hope that it will be useful, ++# but WITHOUT ANY WARRANTY; without even the implied warranty of ++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++# GNU General Public License for more details. ++# ++# You should have received a copy of the GNU General Public License ++# along with this program; if not, write to the Free Software ++# Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++# MA 02111-1307 USA ++# ++ ++include $(TOPDIR)/config.mk ++ ++LIB = $(obj)lib$(BOARD).o ++ ++COBJS := tx6q.o ++SOBJS := lowlevel_init.o ++ifeq ($(CONFIG_SPL_BUILD),y) ++ COBJS += spl_boot.o ++else ++ifeq ($(CONFIG_CMD_ROMUPDATE),y) ++ COBJS += flash.o ++endif ++endif ++ ++SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) ++OBJS := $(addprefix $(obj),$(COBJS)) ++SOBJS := $(addprefix $(obj),$(SOBJS)) ++ ++$(LIB): $(obj).depend $(OBJS) $(SOBJS) ++ $(call cmd_link_o_target, $(OBJS) $(SOBJS)) ++ ++######################################################################### ++ ++include $(SRCTREE)/rules.mk ++ ++sinclude $(obj).depend ++ ++######################################################################### diff --cc board/karo/tx6q/config.mk index 0000000000,0000000000..a00e7e9c62 new file mode 100644 --- /dev/null +++ b/board/karo/tx6q/config.mk @@@ -1,0 -1,0 +1,13 @@@ ++# stack is allocated below CONFIG_SYS_TEXT_BASE ++CONFIG_SYS_TEXT_BASE := 0x27800000 ++#CONFIG_SYS_TEXT_BASE := 0x17800000 ++#CONFIG_SPL_TEXT_BASE := 0x00000000 ++ ++LOGO_BMP = logos/karo.bmp ++#PLATFORM_CPPFLAGS += -DDEBUG ++PLATFORM_CPPFLAGS += -Wno-unused-but-set-variable ++ ++PLATFORM_CPPFLAGS += -Werror ++#ifneq ($(CONFIG_SPL_BUILD),y) ++# ALL-y += $(obj)u-boot.sb ++#endif diff --cc board/karo/tx6q/dcd.c index 0000000000,0000000000..c40fe75868 new file mode 100644 --- /dev/null +++ b/board/karo/tx6q/dcd.c @@@ -1,0 -1,0 +1,195 @@@ ++/* ++ * Table 8-35. Valid DCD Address Ranges ++ * Address range Start address Last Address ++ * IRAM Free Space 0x00907000 0x00937FF0 ++ * CCM register set 0x020C4000 0x020C7FFF ++ * ANADIG registers 0x020C8000 0x020C8FFF ++ * IOMUX Control (IOMUXC) registers 0x020E0000 0x020E3FFF ++ * MMDC register set 0x021B0000 0x021B7FFF ++ * EIM 0x08000000 0x0FFEFFFF ++ * DDR 0x10000000 0xFFFFFFFF ++ */ ++ ++#define CPU_2_BE_32(l) \ ++ ((((l) << 24) & 0xFF000000) | \ ++ (((l) << 8) & 0x00FF0000) | \ ++ (((l) >> 8) & 0x0000FF00) | \ ++ (((l) >> 24) & 0x000000FF)) ++ ++#define CHECK_DCD_ADDR(a) ((((a) >= 0x00907000) && ((a) <= 0x00937FF0)) || \ ++ (((a) >= 0x020C4000) && ((a) < 0x020C8000)) || \ ++ (((a) >= 0x020C8000) && ((a) < 0x020C9000)) || \ ++ (((a) >= 0x020E0000) && ((a) < 0x020E4000)) || \ ++ (((a) >= 0x021B0000) && ((a) < 0x021B8000)) || \ ++ (((a) >= 0x08000000) && ((a) < 0x0FFF0000)) || \ ++ (((a) >= 0x10000000))) ++ ++#define __MXC_DCD_ITEM(addr, val) \ ++ CPU_2_BE_32(addr), CPU_2_BE_32(val) ++ ++#define MXC_DCD_ITEM(addr, val) (CHECK_DCD_ADDR(addr) ? __MXC_DCD_ITEM(addr, val) : bad_dcd_address) ++ ++#define MXC_DCD_CMD_WRT(type, flags, next) \ ++ CPU_2_BE_32((0xcc << 24) | ((next) << 8) | ((flags) << 3) | (type)) ++ ++unsigned long dcd_start[] = { ++ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, dcd_end) ++ ++ /* RESET_OUT GPIO_7_12 */ ++ MXC_DCD_ITEM(0x20e024c, 0x00000005), ++#if 1 ++ /* STK5 LED GPIO */ ++ MXC_DCD_ITEM(0x020e00ec, (1 << 20)), ++#endif ++ MXC_DCD_ITEM(0x020c402c, 0x01e436c1), /* CSC2CDR default: 0x007236c1 */ ++ MXC_DCD_ITEM(0x020c80e0, 0x00002001), /* ENET PLL */ ++ MXC_DCD_ITEM(0x020e0004, 0x48640005), /* default: 0x48400005 ENET_CLK output */ ++#if 1 ++ /* enable all relevant clocks... */ ++ MXC_DCD_ITEM(0x020c4068, 0xf0c03f3f), /* default: 0xf0c03f0f APBH-DMA */ ++ MXC_DCD_ITEM(0x020c406c, 0xf0fc0c00), /* default: 0xf0fc0000 */ ++ MXC_DCD_ITEM(0x020c4070, 0xfc3ff00c), /* default: 0xfc3ff00c */ ++ MXC_DCD_ITEM(0x020c4074, 0x3ff00000), /* default: 0x3ff00000 */ ++ MXC_DCD_ITEM(0x020c4078, 0xff00ff00), /* default: 0x0000ff00 GPMI BCH */ ++ MXC_DCD_ITEM(0x020c407c, 0xff033f0f), /* default: 0xf0033f0f UART1 */ ++ MXC_DCD_ITEM(0x020c4080, 0xffff03c3), /* default: 0xffff0003 USDHC4 (for APBH-DMA!) USDHC3 (for BCH!) */ ++ ++// MXC_DCD_ITEM(0x020c4068, 0xf0c03f3f), /* default: 0xf0c03f0f */ ++// MXC_DCD_ITEM(0x020c406c, 0xf0fc0000), ++// MXC_DCD_ITEM(0x020c4070, 0xfc3ff00c), ++// MXC_DCD_ITEM(0x020c4074, 0x3ff00000), ++// MXC_DCD_ITEM(0x020c4078, 0x0000ff00), ++// /* enable UART clocks */ ++// MXC_DCD_ITEM(0x020c407c, 0xff033f0f), /* default: 0xf0033f0f */ ++// MXC_DCD_ITEM(0x020c4080, 0xffff00c3), /* default: 0xffff0003 */ ++#else ++ /* enable all clocks... */ ++ MXC_DCD_ITEM(0x020c4068, 0xffffffff), ++ MXC_DCD_ITEM(0x020c406c, 0xffffffff), ++ MXC_DCD_ITEM(0x020c4070, 0xffffffff), ++ MXC_DCD_ITEM(0x020c4074, 0xffffffff), ++ MXC_DCD_ITEM(0x020c4078, 0xffffffff), ++ MXC_DCD_ITEM(0x020c407c, 0xffffffff), ++ MXC_DCD_ITEM(0x020c4080, 0xffffffff), ++#endif ++ /* UART1 pad config */ ++ MXC_DCD_ITEM(0x020e02a8, 0x00000001), /* UART1 TXD */ ++ MXC_DCD_ITEM(0x020e02ac, 0x00000001), /* UART1 RXD */ ++ MXC_DCD_ITEM(0x020e0920, 0x00000003), /* UART1 RXD INPUT_SEL */ ++ MXC_DCD_ITEM(0x020e02c0, 0x00000001), /* UART1 CTS */ ++ MXC_DCD_ITEM(0x020e02c4, 0x00000001), /* UART1 RTS */ ++ MXC_DCD_ITEM(0x020e091c, 0x00000003), /* UART1 RTS INPUT_SEL */ ++ ++ /* NAND */ ++ MXC_DCD_ITEM(0x020e02d4, 0x00000000), /* NANDF_CLE: NANDF_CLE */ ++ MXC_DCD_ITEM(0x020e02d8, 0x00000000), /* NANDF_ALE: NANDF_ALE */ ++ MXC_DCD_ITEM(0x020e02dc, 0x00000000), /* NANDF_WP_B: NANDF_WPn */ ++ MXC_DCD_ITEM(0x020e02e0, 0x00000000), /* NANDF_RB0: NANDF_READY0 */ ++ MXC_DCD_ITEM(0x020e02e4, 0x00000000), /* NANDF_CS0: NANDF_CS0 */ ++ MXC_DCD_ITEM(0x020e02f4, 0x00000001), /* SD4_CMD: NANDF_RDn */ ++ MXC_DCD_ITEM(0x020e02f8, 0x00000001), /* SD4_CLK: NANDF_WRn */ ++ ++ MXC_DCD_ITEM(0x020e02fc, 0x00000000), /* NANDF_D0: NANDF_D0 */ ++ MXC_DCD_ITEM(0x020e0300, 0x00000000), /* NANDF_D1: NANDF_D1 */ ++ MXC_DCD_ITEM(0x020e0304, 0x00000000), /* NANDF_D2: NANDF_D2 */ ++ MXC_DCD_ITEM(0x020e0308, 0x00000000), /* NANDF_D3: NANDF_D3 */ ++ MXC_DCD_ITEM(0x020e030c, 0x00000000), /* NANDF_D4: NANDF_D4 */ ++ MXC_DCD_ITEM(0x020e0310, 0x00000000), /* NANDF_D5: NANDF_D5 */ ++ MXC_DCD_ITEM(0x020e0314, 0x00000000), /* NANDF_D6: NANDF_D6 */ ++ MXC_DCD_ITEM(0x020e0318, 0x00000000), /* NANDF_D7: NANDF_D7 */ ++ ++ /* ext. mem CS */ ++ MXC_DCD_ITEM(0x020e02ec, 0x00000000), /* NANDF_CS2: NANDF_CS2 */ ++ ++ MXC_DCD_ITEM(0x020e05a8, 0x00000030), ++ MXC_DCD_ITEM(0x020e05b0, 0x00000030), ++ MXC_DCD_ITEM(0x020e0524, 0x00000030), ++ MXC_DCD_ITEM(0x020e051c, 0x00000030), ++ MXC_DCD_ITEM(0x020e0518, 0x00000030), ++ MXC_DCD_ITEM(0x020e050c, 0x00000030), ++ MXC_DCD_ITEM(0x020e05b8, 0x00000030), ++ MXC_DCD_ITEM(0x020e05c0, 0x00000030), ++ MXC_DCD_ITEM(0x020e05ac, 0x00020030), ++ MXC_DCD_ITEM(0x020e05b4, 0x00020030), ++ MXC_DCD_ITEM(0x020e0528, 0x00020030), ++ MXC_DCD_ITEM(0x020e0520, 0x00020030), ++ MXC_DCD_ITEM(0x020e0514, 0x00020030), ++ MXC_DCD_ITEM(0x020e0510, 0x00020030), ++ MXC_DCD_ITEM(0x020e05bc, 0x00020030), ++ MXC_DCD_ITEM(0x020e05c4, 0x00020030), ++ MXC_DCD_ITEM(0x020e056c, 0x00020030), ++ MXC_DCD_ITEM(0x020e0578, 0x00020030), ++ MXC_DCD_ITEM(0x020e0588, 0x00020030), ++ MXC_DCD_ITEM(0x020e0594, 0x00020030), ++ MXC_DCD_ITEM(0x020e057c, 0x00020030), ++ MXC_DCD_ITEM(0x020e0590, 0x00003000), ++ MXC_DCD_ITEM(0x020e0598, 0x00003000), ++ MXC_DCD_ITEM(0x020e058c, 0x00000000), ++ MXC_DCD_ITEM(0x020e059c, 0x00003030), ++ MXC_DCD_ITEM(0x020e05a0, 0x00003030), ++ MXC_DCD_ITEM(0x020e0784, 0x00000030), ++ MXC_DCD_ITEM(0x020e0788, 0x00000030), ++ MXC_DCD_ITEM(0x020e0794, 0x00000030), ++ MXC_DCD_ITEM(0x020e079c, 0x00000030), ++ MXC_DCD_ITEM(0x020e07a0, 0x00000030), ++ MXC_DCD_ITEM(0x020e07a4, 0x00000030), ++ MXC_DCD_ITEM(0x020e07a8, 0x00000030), ++ MXC_DCD_ITEM(0x020e0748, 0x00000030), ++ MXC_DCD_ITEM(0x020e074c, 0x00000030), ++ MXC_DCD_ITEM(0x020e0750, 0x00020000), ++ MXC_DCD_ITEM(0x020e0758, 0x00000000), ++ MXC_DCD_ITEM(0x020e0774, 0x00020000), ++ MXC_DCD_ITEM(0x020e078c, 0x00000030), ++ MXC_DCD_ITEM(0x020e0798, 0x000c0000), ++ MXC_DCD_ITEM(0x021b081c, 0x33333333), ++ MXC_DCD_ITEM(0x021b0820, 0x33333333), ++ MXC_DCD_ITEM(0x021b0824, 0x33333333), ++ MXC_DCD_ITEM(0x021b0828, 0x33333333), ++ MXC_DCD_ITEM(0x021b481c, 0x33333333), ++ MXC_DCD_ITEM(0x021b4820, 0x33333333), ++ MXC_DCD_ITEM(0x021b4824, 0x33333333), ++ MXC_DCD_ITEM(0x021b4828, 0x33333333), ++ MXC_DCD_ITEM(0x021b0018, 0x00081740), ++ MXC_DCD_ITEM(0x021b001c, 0x00008000), ++ MXC_DCD_ITEM(0x021b000c, 0x555a7975), ++ MXC_DCD_ITEM(0x021b0010, 0xff538e64), ++ MXC_DCD_ITEM(0x021b0014, 0x01ff00db), ++ MXC_DCD_ITEM(0x021b002c, 0x000026d2), ++ MXC_DCD_ITEM(0x021b0030, 0x005b0e21), ++ MXC_DCD_ITEM(0x021b0008, 0x09444040), ++ MXC_DCD_ITEM(0x021b0004, 0x00025576), ++ MXC_DCD_ITEM(0x021b0040, 0x00000027), ++ MXC_DCD_ITEM(0x021b0000, 0x831a0000), ++ MXC_DCD_ITEM(0x021b001c, 0x04088032), ++ MXC_DCD_ITEM(0x021b001c, 0x0408803a), ++ MXC_DCD_ITEM(0x021b001c, 0x00008033), ++ MXC_DCD_ITEM(0x021b001c, 0x0000803b), ++ MXC_DCD_ITEM(0x021b001c, 0x00428031), ++ MXC_DCD_ITEM(0x021b001c, 0x00428039), ++ MXC_DCD_ITEM(0x021b001c, 0x09408030), ++ MXC_DCD_ITEM(0x021b001c, 0x09408038), ++ MXC_DCD_ITEM(0x021b001c, 0x04008040), ++ MXC_DCD_ITEM(0x021b001c, 0x04008048), ++ MXC_DCD_ITEM(0x021b0800, 0xa1380003), ++ MXC_DCD_ITEM(0x021b4800, 0xa1380003), ++ MXC_DCD_ITEM(0x021b0020, 0x00005800), ++ MXC_DCD_ITEM(0x021b0818, 0x00000007), ++ MXC_DCD_ITEM(0x021b4818, 0x00000007), ++ MXC_DCD_ITEM(0x021b083c, 0x434b0350), ++ MXC_DCD_ITEM(0x021b0840, 0x034c0359), ++ MXC_DCD_ITEM(0x021b483c, 0x434b0350), ++ MXC_DCD_ITEM(0x021b4840, 0x03650348), ++ MXC_DCD_ITEM(0x021b0848, 0x4436383b), ++ MXC_DCD_ITEM(0x021b4848, 0x39393341), ++ MXC_DCD_ITEM(0x021b0850, 0x35373933), ++ MXC_DCD_ITEM(0x021b4850, 0x48254a36), ++ MXC_DCD_ITEM(0x021b080c, 0x001f001f), ++ MXC_DCD_ITEM(0x021b0810, 0x001f001f), ++ MXC_DCD_ITEM(0x021b480c, 0x00440044), ++ MXC_DCD_ITEM(0x021b4810, 0x00440044), ++ MXC_DCD_ITEM(0x021b08b8, 0x00000800), ++ MXC_DCD_ITEM(0x021b48b8, 0x00000800), ++ MXC_DCD_ITEM(0x021b001c, 0x00000000), ++ MXC_DCD_ITEM(0x021b0404, 0x00011006), ++ dcd_end: ++}; diff --cc board/karo/tx6q/flash.c index 0000000000,0000000000..8a1e652e0a new file mode 100644 --- /dev/null +++ b/board/karo/tx6q/flash.c @@@ -1,0 -1,0 +1,702 @@@ ++#include ++#include ++#include ++#include ++ ++#include ++ ++#include ++#include ++#include ++#include ++#include ++ ++#define FCB_START_BLOCK 0 ++#define NUM_FCB_BLOCKS 1 ++#define MAX_FCB_BLOCKS 32768 ++ ++#if CONFIG_SYS_NAND_U_BOOT_OFFS < 0x20000 ++#error CONFIG_SYS_NAND_U_BOOT_OFFS must be >= 128kIB ++#endif ++ ++struct mx6_nand_timing { ++ u8 data_setup; ++ u8 data_hold; ++ u8 address_setup; ++ u8 dsample_time; ++ u8 nand_timing_state; ++ u8 tREA; ++ u8 tRLOH; ++ u8 tRHOH; ++}; ++ ++struct mx6_fcb { ++ u32 checksum; ++ u32 fingerprint; ++ u32 version; ++ struct mx6_nand_timing timing; ++ u32 page_data_size; ++ u32 total_page_size; ++ u32 sectors_per_block; ++ u32 number_of_nands; /* not used by ROM code */ ++ u32 total_internal_die; /* not used by ROM code */ ++ u32 cell_type; /* not used by ROM code */ ++ u32 ecc_blockn_type; ++ u32 ecc_block0_size; ++ u32 ecc_blockn_size; ++ u32 ecc_block0_type; ++ u32 metadata_size; ++ u32 ecc_blocks_per_page; ++ u32 rsrvd1[6]; /* not used by ROM code */ ++ u32 bch_mode; /* erase_threshold */ ++ u32 rsrvd2[2]; ++ u32 fw1_start_page; ++ u32 fw2_start_page; ++ u32 fw1_sectors; ++ u32 fw2_sectors; ++ u32 dbbt_search_area; ++ u32 bb_mark_byte; ++ u32 bb_mark_startbit; ++ u32 bb_mark_phys_offset; ++ u32 bch_type; ++ u32 rsrvd3[8]; /* Toggle NAND timing parameters */ ++ u32 disbbm; ++ u32 bb_mark_spare_offset; ++ u32 rsrvd4[9]; /* ONFI NAND parameters */ ++ u32 disbb_search; ++}; ++ ++struct mx6_dbbt_header { ++ u32 checksum; ++ u32 fingerprint; ++ u32 version; ++ u32 number_bb; ++ u32 number_pages; ++ u8 spare[492]; ++}; ++ ++struct mx6_dbbt { ++ u32 nand_number; ++ u32 number_bb; ++ u32 bb_num[2040 / 4]; ++}; ++ ++#define BF_VAL(v, bf) (((v) & bf##_MASK) >> bf##_OFFSET) ++ ++static nand_info_t *mtd = &nand_info[0]; ++ ++extern void *_start; ++ ++#define BIT(v,n) (((v) >> (n)) & 0x1) ++ ++static inline void memdump(const void *addr, size_t len) ++{ ++ const char *buf = addr; ++ int i; ++ ++ for (i = 0; i < len; i++) { ++ if (i % 16 == 0) { ++ if (i > 0) ++ printf("\n"); ++ printf("%p:", &buf[i]); ++ } ++ printf(" %02x", buf[i]); ++ } ++ printf("\n"); ++} ++ ++static u8 calculate_parity_13_8(u8 d) ++{ ++ u8 p = 0; ++ ++ p |= (BIT(d, 6) ^ BIT(d, 5) ^ BIT(d, 3) ^ BIT(d, 2)) << 0; ++ p |= (BIT(d, 7) ^ BIT(d, 5) ^ BIT(d, 4) ^ BIT(d, 2) ^ BIT(d, 1)) << 1; ++ p |= (BIT(d, 7) ^ BIT(d, 6) ^ BIT(d, 5) ^ BIT(d, 1) ^ BIT(d, 0)) << 2; ++ p |= (BIT(d, 7) ^ BIT(d, 4) ^ BIT(d, 3) ^ BIT(d, 0)) << 3; ++ p |= (BIT(d, 6) ^ BIT(d, 4) ^ BIT(d, 3) ^ BIT(d, 2) ^ BIT(d, 1) ^ BIT(d, 0)) << 4; ++ return p; ++} ++ ++static void encode_hamming_13_8(void *_src, void *_ecc, size_t size) ++{ ++ int i; ++ u8 *src = _src; ++ u8 *ecc = _ecc; ++ ++ for (i = 0; i < size; i++) ++ ecc[i] = calculate_parity_13_8(src[i]); ++} ++ ++static u32 calc_chksum(void *buf, size_t size) ++{ ++ u32 chksum = 0; ++ u8 *bp = buf; ++ size_t i; ++ ++ for (i = 0; i < size; i++) { ++ chksum += bp[i]; ++ } ++ return ~chksum; ++} ++ ++/* ++ Physical organisation of data in NAND flash: ++ metadata ++ payload chunk 0 (may be empty) ++ ecc for metadata + payload chunk 0 ++ payload chunk 1 ++ ecc for payload chunk 1 ++... ++ payload chunk n ++ ecc for payload chunk n ++ */ ++ ++static int calc_bb_offset(nand_info_t *mtd, struct mx6_fcb *fcb) ++{ ++ int bb_mark_offset; ++ int chunk_data_size = fcb->ecc_blockn_size * 8; ++ int chunk_ecc_size = (fcb->ecc_blockn_type << 1) * 13; ++ int chunk_total_size = chunk_data_size + chunk_ecc_size; ++ int bb_mark_chunk, bb_mark_chunk_offs; ++ ++ bb_mark_offset = (mtd->writesize - fcb->metadata_size) * 8; ++ if (fcb->ecc_block0_size == 0) ++ bb_mark_offset -= (fcb->ecc_block0_type << 1) * 13; ++ ++ bb_mark_chunk = bb_mark_offset / chunk_total_size; ++ bb_mark_chunk_offs = bb_mark_offset - (bb_mark_chunk * chunk_total_size); ++ if (bb_mark_chunk_offs > chunk_data_size) { ++ printf("Unsupported ECC layout; BB mark resides in ECC data: %u\n", ++ bb_mark_chunk_offs); ++ return -EINVAL; ++ } ++ bb_mark_offset -= bb_mark_chunk * chunk_ecc_size; ++ return bb_mark_offset; ++} ++ ++#define pr_fcb_val(p, n) debug("%s=%08x(%d)\n", #n, (p)->n, (p)->n) ++ ++static struct mx6_fcb *create_fcb(void *buf, int fw1_start_block, ++ int fw2_start_block, size_t fw_size) ++{ ++ struct gpmi_regs *gpmi_base = (struct gpmi_regs *)GPMI_BASE_ADDRESS; ++ struct bch_regs *bch_base = (struct bch_regs *)BCH_BASE_ADDRESS; ++ u32 fl0, fl1; ++ u32 t0; ++ int metadata_size; ++ int bb_mark_bit_offs; ++ struct mx6_fcb *fcb; ++ int fcb_offs; ++ ++ if (gpmi_base == NULL || bch_base == NULL) { ++ return ERR_PTR(-ENOMEM); ++ } ++ ++ fl0 = readl(&bch_base->hw_bch_flash0layout0); ++ fl1 = readl(&bch_base->hw_bch_flash0layout1); ++ t0 = readl(&gpmi_base->hw_gpmi_timing0); ++// t1 = readl(&gpmi_base->hw_gpmi_timing1); ++ ++ metadata_size = BF_VAL(fl0, BCH_FLASHLAYOUT0_META_SIZE); ++ ++ fcb = buf + ALIGN(metadata_size, 4); ++ fcb_offs = (void *)fcb - buf; ++#if 0 ++ memset(buf, 0xff, fcb_offs); ++ memset(fcb, 0x00, sizeof(*fcb)); ++ memset(fcb + 1, 0xff, mtd->erasesize - fcb_offs - sizeof(*fcb)); ++#else ++ memset(buf, 0, fcb_offs); ++ memset(fcb, 0x00, sizeof(*fcb)); ++ memset(fcb + 1, 0, mtd->erasesize - fcb_offs - sizeof(*fcb)); ++#endif ++ strncpy((char *)&fcb->fingerprint, "FCB ", 4); ++ fcb->version = cpu_to_be32(1); ++#if 1 ++ fcb->disbb_search = 1; ++ fcb->disbbm = 1; ++#endif ++ fcb->timing.data_setup = BF_VAL(t0, GPMI_TIMING0_DATA_SETUP); ++ fcb->timing.data_hold = BF_VAL(t0, GPMI_TIMING0_DATA_HOLD); ++ fcb->timing.address_setup = BF_VAL(t0, GPMI_TIMING0_ADDRESS_SETUP); ++#if 0 ++ fcb->timing.data_setup = 80; ++ fcb->timing.data_hold = 60; ++ fcb->timing.address_setup = 25; ++ fcb->timing.dsample_time = 6; ++#endif ++ fcb->page_data_size = mtd->writesize; ++ fcb->total_page_size = mtd->writesize + mtd->oobsize; ++ fcb->sectors_per_block = mtd->erasesize / mtd->writesize; ++ ++ fcb->ecc_block0_type = BF_VAL(fl0, BCH_FLASHLAYOUT0_ECC0); ++ fcb->ecc_block0_size = BF_VAL(fl0, BCH_FLASHLAYOUT0_DATA0_SIZE) * 4; ++ fcb->ecc_blockn_type = BF_VAL(fl1, BCH_FLASHLAYOUT1_ECCN); ++ fcb->ecc_blockn_size = BF_VAL(fl1, BCH_FLASHLAYOUT1_DATAN_SIZE) * 4; ++ ++ pr_fcb_val(fcb, ecc_block0_type); ++ pr_fcb_val(fcb, ecc_blockn_type); ++ pr_fcb_val(fcb, ecc_block0_size); ++ pr_fcb_val(fcb, ecc_blockn_size); ++ ++ fcb->metadata_size = BF_VAL(fl0, BCH_FLASHLAYOUT0_META_SIZE); ++ fcb->ecc_blocks_per_page = BF_VAL(fl0, BCH_FLASHLAYOUT0_NBLOCKS); ++ fcb->bch_mode = readl(&bch_base->hw_bch_mode); ++ fcb->bch_type = 0; /* BCH20 */ ++ ++ fcb->fw1_start_page = fw1_start_block * mtd->erasesize / mtd->writesize; ++ fcb->fw1_sectors = DIV_ROUND_UP(fw_size, mtd->writesize); ++ ++ if (fw2_start_block != 0 && fw2_start_block < mtd->size / mtd->erasesize) { ++ fcb->fw2_start_page = fw2_start_block * mtd->erasesize / mtd->writesize; ++ fcb->fw2_sectors = fcb->fw1_sectors; ++ } ++ ++ fcb->dbbt_search_area = 1; ++ ++ bb_mark_bit_offs = calc_bb_offset(mtd, fcb); ++ if (bb_mark_bit_offs < 0) ++ return ERR_PTR(bb_mark_bit_offs); ++ fcb->bb_mark_byte = bb_mark_bit_offs / 8; ++ fcb->bb_mark_startbit = bb_mark_bit_offs % 8; ++ fcb->bb_mark_phys_offset = mtd->writesize; ++ ++ pr_fcb_val(fcb, bb_mark_byte); ++ pr_fcb_val(fcb, bb_mark_startbit); ++ pr_fcb_val(fcb, bb_mark_phys_offset); ++ ++ fcb->checksum = calc_chksum(&fcb->fingerprint, 512 - 4); ++ return fcb; ++} ++ ++static inline int find_fcb(void *ref, int page) ++{ ++ int ret = 0; ++ struct nand_chip *chip = mtd->priv; ++ void *buf = malloc(mtd->erasesize); ++ ++ if (buf == NULL) { ++ return -ENOMEM; ++ } ++ chip->select_chip(mtd, 0); ++ chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page); ++ ret = chip->ecc.read_page_raw(mtd, chip, buf, page); ++ if (ret) { ++ printf("Failed to read FCB from page %u: %d\n", page, ret); ++ return ret; ++ } ++ chip->select_chip(mtd, -1); ++ if (memcmp(buf, ref, mtd->writesize) == 0) { ++ debug("Found FCB in page %u (%08x)\n", ++ page, page * mtd->writesize); ++ ret = 1; ++ } ++ free(buf); ++ return ret; ++} ++ ++static int write_fcb(void *buf, int block) ++{ ++ int ret; ++ struct nand_chip *chip = mtd->priv; ++ int page = block * mtd->erasesize / mtd->writesize; ++ ++ ret = find_fcb(buf, page); ++ if (ret > 0) { ++ printf("FCB at block %d is up to date\n", block); ++ return 0; ++ } ++ ++ ret = nand_erase(mtd, block * mtd->erasesize, mtd->erasesize); ++ if (ret) { ++ printf("Failed to erase FCB block %u\n", block); ++ return ret; ++ } ++ ++ printf("Writing FCB to block %d @ %08x\n", block, ++ block * mtd->erasesize); ++ chip->select_chip(mtd, 0); ++ ret = chip->write_page(mtd, chip, buf, page, 0, 1); ++ if (ret) { ++ printf("Failed to write FCB to block %u: %d\n", block, ret); ++ } ++ chip->select_chip(mtd, -1); ++ ++ return ret; ++} ++ ++struct mx6_ivt { ++ u32 magic; ++ u32 entry; ++ u32 rsrvd1; ++ void *dcd; ++ void *boot_data; ++ void *self; ++ void *csf; ++ u32 rsrvd2; ++}; ++ ++struct mx6_boot_data { ++ u32 start; ++ u32 length; ++ u32 plugin; ++}; ++ ++static int find_ivt(void *buf) ++{ ++ struct mx6_ivt *ivt_hdr = buf + 0x400; ++ ++ if ((ivt_hdr->magic & 0xff0000ff) != 0x400000d1) ++ return 0; ++ ++ return 1; ++} ++ ++static inline void *reloc(void *dst, void *base, void *ptr) ++{ ++ return dst + (ptr - base); ++} ++ ++static int patch_ivt(void *buf, size_t fsize) ++{ ++ struct mx6_ivt *ivt_hdr = buf + 0x400; ++ struct mx6_boot_data *boot_data; ++ ++ if (!find_ivt(buf)) { ++ printf("No IVT found in image at %p\n", buf); ++ return -EINVAL; ++ } ++ boot_data = reloc(ivt_hdr, ivt_hdr->self, ivt_hdr->boot_data); ++ boot_data->length = fsize; ++ ++ return 0; ++} ++ ++#define chk_overlap(a,b) \ ++ ((a##_start_block <= b##_end_block && \ ++ a##_end_block >= b##_start_block) || \ ++ (b##_start_block <= a##_end_block && \ ++ b##_end_block >= a##_start_block)) ++ ++#define fail_if_overlap(a,b,m1,m2) do { \ ++ if (chk_overlap(a, b)) { \ ++ printf("%s blocks %lu..%lu overlap %s in blocks %lu..%lu!\n", \ ++ m1, a##_start_block, a##_end_block, \ ++ m2, b##_start_block, b##_end_block); \ ++ /*return -EINVAL;*/ \ ++ } \ ++} while (0) ++ ++#ifndef CONFIG_ENV_OFFSET_REDUND ++#define TOTAL_ENV_SIZE CONFIG_ENV_RANGE ++#else ++#define TOTAL_ENV_SIZE (CONFIG_ENV_RANGE * 2) ++#endif ++ ++#define pr_fcb_offset(n) printf("%s: %04x (%d)\n", #n, \ ++ offsetof(struct mx6_fcb, n), offsetof(struct mx6_fcb, n)) ++ ++int do_update(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) ++{ ++ int ret; ++ int block; ++ int erase_size = mtd->erasesize; ++ int page_size = mtd->writesize; ++ void *buf; ++ char *load_addr; ++ char *file_size; ++ size_t size = 0; ++ void *addr = NULL; ++ struct mx6_fcb *fcb; ++ unsigned long fcb_start_block = FCB_START_BLOCK; ++ unsigned long num_fcb_blocks = NUM_FCB_BLOCKS; ++ unsigned long fcb_end_block; ++ unsigned long mtd_num_blocks = mtd->size / mtd->erasesize; ++ unsigned long env_start_block = CONFIG_ENV_OFFSET / mtd->erasesize; ++ unsigned long env_end_block = env_start_block + ++ DIV_ROUND_UP(TOTAL_ENV_SIZE, mtd->erasesize) - 1; ++ int optind; ++ int fw1_set = 0; ++ int fw2_set = 0; ++ unsigned long fw1_start_block = 0, fw1_end_block; ++ unsigned long fw2_start_block = 0, fw2_end_block; ++ unsigned long fw_num_blocks; ++ unsigned long extra_blocks = 2; ++ nand_erase_options_t erase_opts = { 0, }; ++ int fcb_written = 0; ++ ++ load_addr = getenv("fileaddr"); ++ file_size = getenv("filesize"); ++ ++ if (argc < 2 && load_addr == NULL) { ++ printf("Load address not specified\n"); ++ return -EINVAL; ++ } ++ if (argc < 3 && file_size == NULL) { ++ printf("Image size not specified\n"); ++ return -EINVAL; ++ } ++ ++ for (optind = 1; optind < argc; optind++) { ++ if (strcmp(argv[optind], "-b") == 0) { ++ if (optind >= argc - 1) { ++ printf("Option %s requires an argument\n", ++ argv[optind]); ++ return -EINVAL; ++ } ++ optind++; ++ fcb_start_block = simple_strtoul(argv[optind], NULL, 0); ++ if (fcb_start_block >= mtd_num_blocks) { ++ printf("Block number %lu is out of range: 0..%lu\n", ++ fcb_start_block, mtd_num_blocks - 1); ++ return -EINVAL; ++ } ++ } else if (strcmp(argv[optind], "-n") == 0) { ++ if (optind >= argc - 1) { ++ printf("Option %s requires an argument\n", ++ argv[optind]); ++ return -EINVAL; ++ } ++ optind++; ++ num_fcb_blocks = simple_strtoul(argv[optind], NULL, 0); ++ if (num_fcb_blocks == 0) { ++ printf("Number of FCB blocks must be non-zero\n"); ++ return -EINVAL; ++ } else if (num_fcb_blocks > MAX_FCB_BLOCKS) { ++ printf("Extraneous number of FCB blocks; max. allowed: %u\n", ++ MAX_FCB_BLOCKS); ++ return -EINVAL; ++ } ++ } else if (strcmp(argv[optind], "-f") == 0) { ++ if (optind >= argc - 1) { ++ printf("Option %s requires an argument\n", ++ argv[optind]); ++ return -EINVAL; ++ } ++ optind++; ++ fw1_start_block = simple_strtoul(argv[optind], NULL, 0); ++ if (fw1_start_block >= mtd_num_blocks) { ++ printf("Block number %lu is out of range: 0..%lu\n", ++ fw1_start_block, mtd_num_blocks - 1); ++ return -EINVAL; ++ } ++ fw1_set = 1; ++ } else if (strcmp(argv[optind], "-r") == 0) { ++ if (optind < argc - 1 && argv[optind + 1][0] != '-') { ++ optind++; ++ fw2_start_block = simple_strtoul(argv[optind], ++ NULL, 0); ++ if (fw2_start_block >= mtd_num_blocks) { ++ printf("Block number %lu is out of range: 0..%lu\n", ++ fw2_start_block, ++ mtd_num_blocks - 1); ++ return -EINVAL; ++ } ++ } ++ fw2_set = 1; ++ } else if (strcmp(argv[optind], "-e") == 0) { ++ if (optind >= argc - 1) { ++ printf("Option %s requires an argument\n", ++ argv[optind]); ++ return -EINVAL; ++ } ++ optind++; ++ extra_blocks = simple_strtoul(argv[optind], NULL, 0); ++ if (extra_blocks >= mtd_num_blocks) { ++ printf("Extra block count %lu is out of range: 0..%lu\n", ++ extra_blocks, ++ mtd_num_blocks - 1); ++ return -EINVAL; ++ } ++ } else if (argv[optind][0] == '-') { ++ printf("Unrecognized option %s\n", argv[optind]); ++ return -EINVAL; ++ } else { ++ break; ++ } ++ } ++ ++ if (argc > optind) { ++ load_addr = NULL; ++ addr = (void *)simple_strtoul(argv[optind], NULL, 16); ++ optind++; ++ } ++ if (argc > optind) { ++ file_size = NULL; ++ size = simple_strtoul(argv[optind], NULL, 16); ++ optind++; ++ } ++ if (load_addr != NULL) { ++ addr = (void *)simple_strtoul(load_addr, NULL, 16); ++ printf("Using default load address %p\n", addr); ++ } ++ if (file_size != NULL) { ++ size = simple_strtoul(file_size, NULL, 16); ++ printf("Using default file size %08x\n", size); ++ } ++ fcb_end_block = fcb_start_block + num_fcb_blocks - 1; ++ fw_num_blocks = DIV_ROUND_UP(size, mtd->erasesize); ++ ++ if (!fw1_set) { ++ fw1_start_block = fcb_end_block + CONFIG_SYS_NAND_U_BOOT_OFFS / mtd->erasesize; ++ fw1_end_block = fw1_start_block + fw_num_blocks + extra_blocks - 1; ++ if (chk_overlap(fw1, env)) { ++ fw1_start_block = env_end_block + 1; ++ fw1_end_block = fw1_start_block + fw_num_blocks + extra_blocks - 1; ++ } ++ } else { ++ fw1_end_block = fw1_start_block + fw_num_blocks + extra_blocks - 1; ++ } ++ ++ if (fw2_set && fw2_start_block == 0) { ++ fw2_start_block = fw1_end_block + 1; ++ fw2_end_block = fw2_start_block + fw_num_blocks + extra_blocks - 1; ++ if (chk_overlap(fw2, env)) { ++ fw2_start_block = env_end_block + 1; ++ fw2_end_block = fw2_start_block + fw_num_blocks + extra_blocks - 1; ++ } ++ } else { ++ fw2_end_block = fw2_start_block + fw_num_blocks + extra_blocks - 1; ++ } ++ ++ fail_if_overlap(fcb, env, "FCB", "Environment"); ++ fail_if_overlap(fcb, fw1, "FCB", "FW1"); ++ fail_if_overlap(fw1, env, "FW1", "Environment"); ++ if (fw2_set) { ++ fail_if_overlap(fcb, fw2, "FCB", "FW2"); ++ fail_if_overlap(fw2, env, "FW2", "Environment"); ++ fail_if_overlap(fw1, fw2, "FW1", "FW2"); ++ } ++ ++ buf = malloc(erase_size); ++ if (buf == NULL) { ++ printf("Failed to allocate buffer\n"); ++ return -ENOMEM; ++ } ++ ++ /* search for first non-bad block in FW1 block range */ ++ while (fw1_start_block <= fw1_end_block) { ++ if (!nand_block_isbad(mtd, fw1_start_block * mtd->erasesize)) ++ break; ++ fw1_start_block++; ++ } ++ if (fw1_end_block - fw1_start_block + 1 < fw_num_blocks) { ++ printf("Too many bad blocks in FW1 block range: %lu..%lu\n", ++ fw1_end_block + 1 - fw_num_blocks - extra_blocks, ++ fw1_end_block); ++ return -EINVAL; ++ } ++ ++ /* search for first non-bad block in FW2 block range */ ++ while (fw2_set && fw2_start_block <= fw2_end_block) { ++ if (!nand_block_isbad(mtd, fw2_start_block * mtd->erasesize)) ++ break; ++ fw2_start_block++; ++ } ++ if (fw2_end_block - fw2_start_block + 1 < fw_num_blocks) { ++ printf("Too many bad blocks in FW2 area %08lx..%08lx\n", ++ fw2_end_block + 1 - fw_num_blocks - extra_blocks, ++ fw2_end_block); ++ return -EINVAL; ++ } ++ ++ fcb = create_fcb(buf, fw1_start_block, fw2_start_block, ++ ALIGN(size, mtd->writesize)); ++ if (IS_ERR(fcb)) { ++ printf("Failed to initialize FCB: %ld\n", PTR_ERR(fcb)); ++ return PTR_ERR(fcb); ++ } ++ encode_hamming_13_8(fcb, (void *)fcb + 512, 512); ++ ++ for (block = fcb_start_block; block <= fcb_end_block; block++) { ++ if (nand_block_isbad(mtd, block * mtd->erasesize)) { ++ if (block == fcb_start_block) ++ fcb_start_block++; ++ continue; ++ } ++ ret = write_fcb(buf, block); ++ if (ret) { ++ printf("Failed to write FCB to block %u\n", block); ++ return ret; ++ } ++ fcb_written = 1; ++ } ++ ++ if (!fcb_written) { ++ printf("Could not write FCB to flash\n"); ++ return -EIO; ++ } ++ ++ ret = patch_ivt(addr, size); ++ if (ret) { ++ return ret; ++ } ++ ++ printf("Programming U-Boot image from %p to block %lu\n", ++ addr, fw1_start_block); ++ if (size & (page_size - 1)) { ++ memset(addr + size, 0xff, size & (page_size - 1)); ++ size = ALIGN(size, page_size); ++ } ++ ++ erase_opts.offset = fcb->fw1_start_page * page_size; ++ erase_opts.length = ALIGN(size, erase_size) + ++ extra_blocks * mtd->erasesize; ++ erase_opts.quiet = 1; ++ ++ printf("Erasing flash @ %08llx..%08llx\n", erase_opts.offset, ++ erase_opts.offset + erase_opts.length - 1); ++ ++ ret = nand_erase_opts(mtd, &erase_opts); ++ if (ret) { ++ printf("Failed to erase flash: %d\n", ret); ++ return ret; ++ } ++ printf("Programming flash @ %08x..%08x from %p\n", ++ fcb->fw1_start_page * page_size, ++ fcb->fw1_start_page * page_size + size, addr); ++ ret = nand_write_skip_bad(mtd, fcb->fw1_start_page * page_size, ++ &size, addr, WITH_DROP_FFS); ++ if (ret) { ++ printf("Failed to program flash: %d\n", ret); ++ return ret; ++ } ++ if (fw2_start_block == 0) { ++ return ret; ++ } ++ ++ printf("Programming redundant U-Boot image to block %lu\n", ++ fw2_start_block); ++ erase_opts.offset = fcb->fw2_start_page * page_size; ++ printf("Erasing flash @ %08llx..%08llx\n", erase_opts.offset, ++ erase_opts.offset + erase_opts.length - 1); ++ ++ ret = nand_erase_opts(mtd, &erase_opts); ++ if (ret) { ++ printf("Failed to erase flash: %d\n", ret); ++ return ret; ++ } ++ printf("Programming flash @ %08x..%08x from %p\n", ++ fcb->fw2_start_page * page_size, ++ fcb->fw2_start_page * page_size + size, addr); ++ ret = nand_write_skip_bad(mtd, fcb->fw2_start_page * page_size, ++ &size, addr, WITH_DROP_FFS); ++ if (ret) { ++ printf("Failed to program flash: %d\n", ret); ++ return ret; ++ } ++ return ret; ++} ++ ++U_BOOT_CMD(romupdate, 11, 0, do_update, ++ "Creates an FCB data structure and writes an U-Boot image to flash\n", ++ "[-b #] [-n #] [-f #] [-r [#]] [
] []\n" ++ "\t-b #\tfirst FCB block number (default 0)\n" ++ "\t-n #\ttotal number of FCB blocks (default 1)\n" ++ "\t-f #\twrite bootloader image at block #\n" ++ "\t-r\twrite redundant bootloader image at next free block after first image\n" ++ "\t-r #\twrite redundant bootloader image at block #\n" ++ "\t-e #\tspecify number of redundant blocks per boot loader image\n" ++ "\t
\tRAM address of bootloader image (default: ${fileaddr}\n" ++ "\t\tlength of bootloader image in RAM (default: ${filesize}" ++ ); diff --cc board/karo/tx6q/lowlevel_init.S index 0000000000,0000000000..65a40424d8 new file mode 100644 --- /dev/null +++ b/board/karo/tx6q/lowlevel_init.S @@@ -1,0 -1,0 +1,596 @@@ ++#include ++#include ++#include ++ ++#define DEBUG_LED_BIT 20 ++#define LED_GPIO_BASE GPIO2_BASE_ADDR ++#define LED_MUX_OFFSET 0x0ec ++#define LED_MUX_MODE 0x15 ++ ++#define SDRAM_CLK CONFIG_SYS_SDRAM_CLK ++ ++#ifdef PHYS_SDRAM_2_SIZE ++#define SDRAM_SIZE (PHYS_SDRAM_1_SIZE + PHYS_SDRAM_2_SIZE) ++#else ++#define SDRAM_SIZE PHYS_SDRAM_1_SIZE ++#endif ++ ++#define CPU_2_BE_32(l) \ ++ ((((l) << 24) & 0xFF000000) | \ ++ (((l) << 8) & 0x00FF0000) | \ ++ (((l) >> 8) & 0x0000FF00) | \ ++ (((l) >> 24) & 0x000000FF)) ++ ++#define MXC_DCD_ITEM(addr, val) .word CPU_2_BE_32(addr), CPU_2_BE_32(val) ++ ++#define CHECK_DCD_ADDR(a) ((((a) >= 0x00907000) && ((a) <= 0x00937FF0)) || \ ++ (((a) >= 0x020C4000) && ((a) < 0x020C8000)) || \ ++ (((a) >= 0x020C8000) && ((a) < 0x020C9000)) || \ ++ (((a) >= 0x020E0000) && ((a) < 0x020E4000)) || \ ++ (((a) >= 0x021B0000) && ((a) < 0x021B8000)) || \ ++ (((a) >= 0x08000000) && ((a) < 0x0FFF0000)) || \ ++ (((a) >= 0x10000000))) ++ ++#define MXC_DCD_CMD_SZ_BYTE 1 ++#define MXC_DCD_CMD_SZ_SHORT 2 ++#define MXC_DCD_CMD_SZ_WORD 4 ++#define MXC_DCD_CMD_FLAG_WRITE 0x0 ++#define MXC_DCD_CMD_FLAG_CLR 0x1 ++#define MXC_DCD_CMD_FLAG_SET 0x3 ++#define MXC_DCD_CMD_FLAG_CHK_ANY (1 << 0) ++#define MXC_DCD_CMD_FLAG_CHK_SET (1 << 1) ++#define MXC_DCD_CMD_FLAG_CHK_CLR (0 << 1) ++ ++#define MXC_DCD_CMD_WRT(type, flags, next) \ ++ .word CPU_2_BE_32((0xcc << 24) | (((next) - .) << 8) | ((flags) << 3) | (type)) ++ ++#define MXC_DCD_CMD_CHK(type, flags, addr, mask) \ ++ .word CPU_2_BE_32((0xcf << 24) | (12 << 8) | ((flags) << 3) | (type)),\ ++ CPU_2_BE_32(addr), CPU_2_BE_32(mask) ++ ++#define MXC_DCD_CMD_CHK_CNT(type, flags, addr, mask, count) \ ++ .word CPU_2_BE_32((0xcf << 24) | (16 << 8) | ((flags) << 3) | (type)),\ ++ CPU_2_BE_32(addr), CPU_2_BE_32(mask), CPU_2_BE_32(count) ++ ++#define MXC_DCD_CMD_NOP \ ++ .word CPU_2_BE_32((0xc0 << 24) | (4 << 8)) ++ ++#define CK_TO_NS(ck) (((ck) * 1000 + SDRAM_CLK / 2) / SDRAM_CLK) ++#define NS_TO_CK(ns) (((ns) * SDRAM_CLK + 999) / 1000) ++ ++ .macro CK_VAL, name, clks, offs, max ++ .iflt \clks - \offs ++ .set \name, 0 ++ .else ++ .ifle \clks - \offs - \max ++ .set \name, \clks - \offs ++ .endif ++ .endif ++ .endm ++ ++ .macro NS_VAL, name, ns, offs, max ++ .iflt \ns - \offs ++ .set \name, 0 ++ .else ++ CK_VAL \name, NS_TO_CK(\ns), \offs, \max ++ .endif ++ .endm ++ ++ .macro CK_MAX, name, ck1, ck2, offs, max ++ .ifgt \ck1 - \ck2 ++ CK_VAL \name, \ck1, \offs, \max ++ .else ++ CK_VAL \name, \ck2, \offs, \max ++ .endif ++ .endm ++ ++#define MDMISC_DDR_TYPE_DDR3 0 ++#define MDMISC_DDR_TYPE_LPDDR2 1 ++#define MDMISC_DDR_TYPE_DDR2 2 ++ ++#define DIV_ROUND_UP(m,d) (((m) + (d) - 1) / (d)) ++ ++#define MDOR_CLK_PERIOD_ns 15258 /* base clock for MDOR values */ ++ ++/* DDR3 SDRAM */ ++#if SDRAM_SIZE > PHYS_SDRAM_1_SIZE ++#define BANK_ADDR_BITS 2 ++#else ++#define BANK_ADDR_BITS 1 ++#endif ++#define SDRAM_BURST_LENGTH 8 ++#define RALAT 5 ++#define WALAT 0 ++#define BI_ON 1 ++#define ADDR_MIRROR 1 ++#define DDR_TYPE MDMISC_DDR_TYPE_DDR3 ++ ++/* 512/1024MiB SDRAM: NT5CB128M16P-CG */ ++/* MDCFG0 0x0c */ ++NS_VAL tRFC, 160, 1, 255 /* clks - 1 (0..255) */ ++CK_MAX tXS, tRFC + 1 + NS_TO_CK(10), 5, 1, 255 /* clks - 1 (0..255) tRFC + 10 */ ++CK_MAX tXP, 3, NS_TO_CK(6), 1, 7 /* clks - 1 (0..7) */ /* max(6ns, 3*CK) */ ++CK_MAX tXPDLL, NS_TO_CK(24), 2, 1, 15 /* clks - 1 (0..15) */ ++NS_VAL tFAW, 45, 1, 31 /* clks - 1 (0..31) */ ++CK_VAL tCL, 8, 3, 8 /* clks - 3 (0..8) CAS Latency */ ++ ++/* MDCFG1 0x10 */ ++NS_VAL tRCD, 14, 1, 7 /* clks - 1 (0..7) */ ++NS_VAL tRP, 14, 1, 7 /* clks - 1 (0..7) */ ++NS_VAL tRC, 50, 1, 31 /* clks - 1 (0..31) */ ++NS_VAL tRAS, 36, 1, 31 /* clks - 1 (0..31) */ ++CK_VAL tRPA, 0, 0, 1 /* clks (0..1) */ ++NS_VAL tWR, 15, 1, 15 /* clks - 1 (0..15) */ ++CK_VAL tMRD, 4, 1, 15 /* clks - 1 (0..15) */ ++CK_VAL tCWL, 6, 2, 6 /* clks - 2 (0..6) */ ++ ++/* MDCFG2 0x14 */ ++CK_VAL tDLLK, 512, 1, 511 /* clks - 1 (0..511) */ ++CK_MAX tRTP, 4, NS_TO_CK(8), 1, 7 /* clks - 1 (0..7) */ ++CK_MAX tWTR, 4, NS_TO_CK(8), 1, 7 /* clks - 1 (0..7) */ ++CK_MAX tRRD, 4, NS_TO_CK(8), 1, 7 /* clks - 1 (0..7) */ ++ ++/* MDOR 0x30 */ ++CK_MAX tXPR, NS_TO_CK(CK_TO_NS(tRFC + 1) + 10), 5, 1, 255 /* clks - 1 (0..255) max(tRFC + 10, 5CK) */ ++#define tSDE_RST (DIV_ROUND_UP(200000, MDOR_CLK_PERIOD_ns) + 2) ++#define tRST_CKE (DIV_ROUND_UP(500000, MDOR_CLK_PERIOD_ns) + 2) ++ ++/* MDOTC 0x08 */ ++NS_VAL tAOFPD, 9, 1, 7 /* clks - 1 (0..7) */ ++NS_VAL tAONPD, 9, 1, 7 /* clks - 1 (0..7) */ ++CK_VAL tANPD, tCWL + 1, 1, 15 /* clks - 1 (0..15) */ ++CK_VAL tAXPD, tCWL + 1, 1, 15 /* clks - 1 (0..15) */ ++CK_VAL tODTLon tCWL, 1, 7 /* clks - 1 (0..7) */ ++CK_VAL tODTLoff tCWL, 1, 31 /* clks - 1 (0..31) */ ++ ++/* MDPDC 0x04 */ ++CK_MAX tCKE, NS_TO_CK(6), 3, 1, 7 ++CK_MAX tCKSRX, NS_TO_CK(10), 5, 0, 7 ++CK_MAX tCKSRE, NS_TO_CK(10), 5, 0, 7 ++ ++#define PRCT 0 ++#define PWDT 5 ++#define SLOW_PD 0 ++#define BOTH_CS_PD 1 ++ ++#define MDPDC_VAL_0 ( \ ++ (PRCT << 28) | \ ++ (PRCT << 24) | \ ++ (tCKE << 16) | \ ++ (SLOW_PD << 7) | \ ++ (BOTH_CS_PD << 6) | \ ++ (tCKSRX << 3) | \ ++ (tCKSRE << 0) \ ++ ) ++ ++#define MDPDC_VAL_1 (MDPDC_VAL_0 | \ ++ (PWDT << 12) | \ ++ (PWDT << 8) \ ++ ) ++ ++#define ROW_ADDR_BITS 14 ++#define COL_ADDR_BITS 10 ++ ++ .iflt tWR - 7 ++ .set mr0_val, ((1 << 8) /* DLL Reset */ | \ ++ ((tWR + 1 - 4) << 9) | \ ++ (((tCL + 3) - 4) << 4)) ++ .else ++ .set mr0_val, ((1 << 8) /* DLL Reset */ | \ ++ (((tWR + 1) / 2) << 9) | \ ++ (((tCL + 3) - 4) << 4)) ++ .endif ++#define MDSCR_MRS_VAL(cs, mr, val) (((val) << 16) | \ ++ (1 << 15) /* CON REQ */ | \ ++ (3 << 4) /* MRS command */ | \ ++ ((cs) << 3) | \ ++ ((mr) << 0)) ++ ++#define mr1_val 0x0040 ++#define mr2_val 0x0408 ++ ++#define MDCFG0_VAL ( \ ++ (tRFC << 24) | \ ++ (tXS << 16) | \ ++ (tXP << 13) | \ ++ (tXPDLL << 9) | \ ++ (tFAW << 4) | \ ++ (tCL << 0)) \ ++ ++#define MDCFG1_VAL ( \ ++ (tRCD << 29) | \ ++ (tRP << 26) | \ ++ (tRC << 21) | \ ++ (tRAS << 16) | \ ++ (tRPA << 15) | \ ++ (tWR << 9) | \ ++ (tMRD << 5) | \ ++ (tCWL << 0)) \ ++ ++#define MDCFG2_VAL ( \ ++ (tDLLK << 16) | \ ++ (tRTP << 6) | \ ++ (tWTR << 3) | \ ++ (tRRD << 0)) ++ ++#define BURST_LEN (SDRAM_BURST_LENGTH / 8) /* 0: 4 byte 1: 8 byte */ ++#define MDCTL_VAL (((ROW_ADDR_BITS - 11) << 24) | \ ++ ((COL_ADDR_BITS - 9) << 20) | \ ++ (BURST_LEN << 19) | \ ++ (2 << 16) | /* SDRAM bus width */ \ ++ ((-1) << (32 - BANK_ADDR_BITS))) ++ ++#define MDMISC_VAL ((ADDR_MIRROR << 19) | \ ++ (WALAT << 16) | \ ++ (BI_ON << 12) | \ ++ (0x3 << 9) | \ ++ (RALAT << 6) | \ ++ (DDR_TYPE << 3)) ++ ++#define MDOR_VAL ((tXPR << 16) | (tSDE_RST << 8) | (tRST_CKE << 0)) ++ ++#define MDOTC_VAL ((tAOFPD << 27) | \ ++ (tAONPD << 24) | \ ++ (tANPD << 20) | \ ++ (tAXPD << 16) | \ ++ (tODTLon << 12) | \ ++ (tODTLoff << 4)) ++ ++fcb_start: ++ b _start ++ .org 0x400 ++ivt_header: ++ .word CPU_2_BE_32((0xd1 << 24) | (32 << 8) | 0x40) ++app_start_addr: ++ .long _start ++ .long 0x0 ++dcd_ptr: ++ .long dcd_hdr ++boot_data_ptr: ++ .word boot_data ++self_ptr: ++ .word ivt_header ++app_code_csf: ++ .word 0x0 ++ .word 0x0 ++boot_data: ++ .long fcb_start ++image_len: ++ .long CONFIG_U_BOOT_IMG_SIZE ++plugin: ++ .word 0 ++ivt_end: ++#define DCD_VERSION 0x40 ++ ++#define CLKCTL_CCGR0 0x68 ++#define CLKCTL_CCGR1 0x6c ++#define CLKCTL_CCGR2 0x70 ++#define CLKCTL_CCGR3 0x74 ++#define CLKCTL_CCGR4 0x78 ++#define CLKCTL_CCGR5 0x7c ++#define CLKCTL_CCGR6 0x80 ++#define CLKCTL_CCGR7 0x84 ++#define CLKCTL_CMEOR 0x88 ++ ++#define DDR_SEL_VAL 3 ++#define DSE_VAL 6 ++#define ODT_VAL 2 ++ ++#define DDR_SEL_SHIFT 18 ++#define DDR_MODE_SHIFT 17 ++#define ODT_SHIFT 8 ++#define DSE_SHIFT 3 ++#define HYS_SHIFT 16 ++#define PKE_SHIFT 12 ++#define PUE_SHIFT 13 ++#define PUS_SHIFT 14 ++ ++#define DDR_SEL_MASK (DDR_SEL_VAL << DDR_SEL_SHIFT) ++#define DDR_MODE_MASK (1 << DDR_MODE_SHIFT) ++#define DSE_MASK (DSE_VAL << DSE_SHIFT) ++#define ODT_MASK (ODT_VAL << ODT_SHIFT) ++ ++#define DQM_MASK (DDR_MODE_MASK | DSE_MASK) ++#define SDQS_MASK DSE_MASK ++#define SDODT_MASK (DSE_MASK | (1 << PKE_SHIFT) | (1 << PUE_SHIFT) | (0 << PUS_SHIFT)) ++#define SDCLK_MASK (DDR_MODE_MASK | DSE_MASK) ++#define SDCKE_MASK ((1 << PKE_SHIFT) | (1 << PUE_SHIFT) | (0 << PUS_SHIFT)) ++#define DDR_ADDR_MASK 0 ++#define DDR_CTRL_MASK (DDR_MODE_MASK | DSE_MASK) ++ ++dcd_hdr: ++ .word CPU_2_BE_32((0xd2 << 24) | ((dcd_end - .) << 8) | DCD_VERSION) ++dcd_start: ++ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, ddr_reset) ++ /* RESET_OUT GPIO_7_12 */ ++ MXC_DCD_ITEM(0x020e024c, 0x00000005) ++ ++ MXC_DCD_ITEM(0x020c402c, 0x01e436c1) /* CSC2CDR default: 0x007236c1 */ ++ MXC_DCD_ITEM(0x020c80e0, 0x00002001) /* ENET PLL */ ++ ++ /* enable all relevant clocks... */ ++ MXC_DCD_ITEM(0x020c4068, 0xf0c03f3f) /* default: 0xf0c03f0f APBH-DMA */ ++ MXC_DCD_ITEM(0x020c406c, 0xf0fc0c00) /* default: 0xf0fc0000 */ ++ MXC_DCD_ITEM(0x020c4070, 0xfc3ff0cc) /* default: 0xfc3ff00c I2C1 */ ++ MXC_DCD_ITEM(0x020c4074, 0x3ff00000) /* default: 0x3ff00000 */ ++ MXC_DCD_ITEM(0x020c4078, 0xff00ff00) /* default: 0x0000ff00 GPMI BCH */ ++ MXC_DCD_ITEM(0x020c407c, 0xff033f0f) /* default: 0xf0033f0f UART1 */ ++ MXC_DCD_ITEM(0x020c4080, 0xffff03ff) /* default: 0xffff0003 USDHC4 (for APBH-DMA!) USDHC3 (for BCH!) */ ++ ++ /* IOMUX: */ ++ MXC_DCD_ITEM(0x020e0004, 0x48640005) /* default: 0x48400005 ENET_CLK output */ ++ /* UART1 pad config */ ++ MXC_DCD_ITEM(0x020e02a8, 0x00000001) /* UART1 TXD */ ++ MXC_DCD_ITEM(0x020e02ac, 0x00000001) /* UART1 RXD */ ++ MXC_DCD_ITEM(0x020e0920, 0x00000003) /* UART1 RXD INPUT_SEL */ ++ MXC_DCD_ITEM(0x020e02c0, 0x00000001) /* UART1 CTS */ ++ MXC_DCD_ITEM(0x020e02c4, 0x00000001) /* UART1 RTS */ ++ MXC_DCD_ITEM(0x020e091c, 0x00000003) /* UART1 RTS INPUT_SEL */ ++#if 0 ++ /* NAND */ ++ MXC_DCD_ITEM(0x020e02d4, 0x00000000) /* NANDF_CLE: NANDF_CLE */ ++ MXC_DCD_ITEM(0x020e02d8, 0x00000000) /* NANDF_ALE: NANDF_ALE */ ++ MXC_DCD_ITEM(0x020e02dc, 0x00000000) /* NANDF_WP_B: NANDF_WPn */ ++ MXC_DCD_ITEM(0x020e02e0, 0x00000000) /* NANDF_RB0: NANDF_READY0 */ ++ MXC_DCD_ITEM(0x020e02e4, 0x00000000) /* NANDF_CS0: NANDF_CS0 */ ++ MXC_DCD_ITEM(0x020e02f4, 0x00000001) /* SD4_CMD: NANDF_RDn */ ++ MXC_DCD_ITEM(0x020e02f8, 0x00000001) /* SD4_CLK: NANDF_WRn */ ++ MXC_DCD_ITEM(0x020e02fc, 0x00000000) /* NANDF_D0: NANDF_D0 */ ++ MXC_DCD_ITEM(0x020e0300, 0x00000000) /* NANDF_D1: NANDF_D1 */ ++ MXC_DCD_ITEM(0x020e0304, 0x00000000) /* NANDF_D2: NANDF_D2 */ ++ MXC_DCD_ITEM(0x020e0308, 0x00000000) /* NANDF_D3: NANDF_D3 */ ++ MXC_DCD_ITEM(0x020e030c, 0x00000000) /* NANDF_D4: NANDF_D4 */ ++ MXC_DCD_ITEM(0x020e0310, 0x00000000) /* NANDF_D5: NANDF_D5 */ ++ MXC_DCD_ITEM(0x020e0314, 0x00000000) /* NANDF_D6: NANDF_D6 */ ++ MXC_DCD_ITEM(0x020e0318, 0x00000000) /* NANDF_D7: NANDF_D7 */ ++#endif ++ /* ext. mem CS */ ++ MXC_DCD_ITEM(0x020e02ec, 0x00000000) /* NANDF_CS2: NANDF_CS2 */ ++ /* DRAM_DQM[0..7] */ ++ MXC_DCD_ITEM(0x020e05ac, DQM_MASK) ++ MXC_DCD_ITEM(0x020e05b4, DQM_MASK) ++ MXC_DCD_ITEM(0x020e0528, DQM_MASK) ++ MXC_DCD_ITEM(0x020e0520, DQM_MASK) ++ MXC_DCD_ITEM(0x020e0514, DQM_MASK) ++ MXC_DCD_ITEM(0x020e0510, DQM_MASK) ++ MXC_DCD_ITEM(0x020e05bc, DQM_MASK) ++ MXC_DCD_ITEM(0x020e05c4, DQM_MASK) ++ /* DRAM_A[0..15] */ ++ MXC_DCD_ITEM(0x020e052c, DDR_ADDR_MASK) ++ MXC_DCD_ITEM(0x020e0530, DDR_ADDR_MASK) ++ MXC_DCD_ITEM(0x020e0534, DDR_ADDR_MASK) ++ MXC_DCD_ITEM(0x020e0538, DDR_ADDR_MASK) ++ MXC_DCD_ITEM(0x020e053c, DDR_ADDR_MASK) ++ MXC_DCD_ITEM(0x020e0540, DDR_ADDR_MASK) ++ MXC_DCD_ITEM(0x020e0544, DDR_ADDR_MASK) ++ MXC_DCD_ITEM(0x020e0548, DDR_ADDR_MASK) ++ MXC_DCD_ITEM(0x020e054c, DDR_ADDR_MASK) ++ MXC_DCD_ITEM(0x020e0550, DDR_ADDR_MASK) ++ MXC_DCD_ITEM(0x020e0554, DDR_ADDR_MASK) ++ MXC_DCD_ITEM(0x020e0558, DDR_ADDR_MASK) ++ MXC_DCD_ITEM(0x020e055c, DDR_ADDR_MASK) ++ MXC_DCD_ITEM(0x020e0560, DDR_ADDR_MASK) ++ MXC_DCD_ITEM(0x020e0564, DDR_ADDR_MASK) ++ MXC_DCD_ITEM(0x020e0568, DDR_ADDR_MASK) ++ /* DRAM_CAS */ ++ MXC_DCD_ITEM(0x020e056c, DDR_CTRL_MASK) ++ /* DRAM_RAS */ ++ MXC_DCD_ITEM(0x020e0578, DDR_CTRL_MASK) ++ /* DRAM_SDCLK[0..1] */ ++ MXC_DCD_ITEM(0x020e0588, SDCLK_MASK) ++ MXC_DCD_ITEM(0x020e0594, SDCLK_MASK) ++ /* DRAM_RESET */ ++ MXC_DCD_ITEM(0x020e057c, DDR_CTRL_MASK) ++ /* DRAM_SDCKE[0..1] */ ++ MXC_DCD_ITEM(0x020e0590, SDCKE_MASK) ++ MXC_DCD_ITEM(0x020e0598, SDCKE_MASK) ++ /* DRAM_SDBA[0..2] */ ++ MXC_DCD_ITEM(0x020e0580, 0x00000000) ++ MXC_DCD_ITEM(0x020e0584, 0x00000000) ++ MXC_DCD_ITEM(0x020e058c, 0x00000000) ++ /* DRAM_SDODT[0..1] */ ++ MXC_DCD_ITEM(0x020e059c, SDODT_MASK) ++ MXC_DCD_ITEM(0x020e05a0, SDODT_MASK) ++ /* DRAM_B[0..7]DS */ ++ MXC_DCD_ITEM(0x020e0784, DSE_MASK) ++ MXC_DCD_ITEM(0x020e0788, DSE_MASK) ++ MXC_DCD_ITEM(0x020e0794, DSE_MASK) ++ MXC_DCD_ITEM(0x020e079c, DSE_MASK) ++ MXC_DCD_ITEM(0x020e07a0, DSE_MASK) ++ MXC_DCD_ITEM(0x020e07a4, DSE_MASK) ++ MXC_DCD_ITEM(0x020e07a8, DSE_MASK) ++ MXC_DCD_ITEM(0x020e0748, DSE_MASK) ++ /* ADDDS */ ++ MXC_DCD_ITEM(0x020e074c, DSE_MASK) ++ /* DDRMODE_CTL */ ++ MXC_DCD_ITEM(0x020e0750, DDR_MODE_MASK) ++ /* DDRPKE */ ++ MXC_DCD_ITEM(0x020e0758, 0x00000000) ++ /* DDRMODE */ ++ MXC_DCD_ITEM(0x020e0774, DDR_MODE_MASK) ++ /* CTLDS */ ++ MXC_DCD_ITEM(0x020e078c, DSE_MASK) ++ /* DDR_TYPE */ ++ MXC_DCD_ITEM(0x020e0798, DDR_SEL_MASK) ++ /* DDRPK */ ++ MXC_DCD_ITEM(0x020e0768, 1 << PUE_SHIFT) ++ /* DDRHYS */ ++ MXC_DCD_ITEM(0x020e0770, 0x00000000) ++ /* TERM_CTL[0..7] */ ++ MXC_DCD_ITEM(0x020e0754, ODT_MASK) ++ MXC_DCD_ITEM(0x020e075c, ODT_MASK) ++ MXC_DCD_ITEM(0x020e0760, ODT_MASK) ++ MXC_DCD_ITEM(0x020e0764, ODT_MASK) ++ MXC_DCD_ITEM(0x020e076c, ODT_MASK) ++ MXC_DCD_ITEM(0x020e0778, ODT_MASK) ++ MXC_DCD_ITEM(0x020e077c, ODT_MASK) ++ MXC_DCD_ITEM(0x020e0780, ODT_MASK) ++ ++ /* SDRAM initialization */ ++ /* MPRDDQBY[0..7]DL */ ++ MXC_DCD_ITEM(0x021b081c, 0x33333333) ++ MXC_DCD_ITEM(0x021b481c, 0x33333333) ++ MXC_DCD_ITEM(0x021b0820, 0x33333333) ++ MXC_DCD_ITEM(0x021b4820, 0x33333333) ++ MXC_DCD_ITEM(0x021b0824, 0x33333333) ++ MXC_DCD_ITEM(0x021b4824, 0x33333333) ++ MXC_DCD_ITEM(0x021b0828, 0x33333333) ++ MXC_DCD_ITEM(0x021b4828, 0x33333333) ++ /* MDMISC */ ++ MXC_DCD_ITEM(0x021b0018, MDMISC_VAL | 2) /* reset MMDC FSM */ ++ddr_reset: ++ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b0018, 0x00000002) ++ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, con_ack) ++ ++ /* MSDSCR Conf Req */ ++ MXC_DCD_ITEM(0x021b001c, 0x00008000) ++con_ack: ++ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_SET, 0x021b001c, 0x00004000) ++ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, ddr_calib) ++ /* MDCTL */ ++ MXC_DCD_ITEM(0x021b0000, MDCTL_VAL) ++ddr_calib: ++ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_SET, 0x021b0018, 0x40000000) ++ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, zq_calib) ++ ++ MXC_DCD_ITEM(0x021b000c, MDCFG0_VAL) ++ MXC_DCD_ITEM(0x021b0010, MDCFG1_VAL) ++ MXC_DCD_ITEM(0x021b0014, MDCFG2_VAL) ++ MXC_DCD_ITEM(0x021b002c, 0x000026d2) /* MDRWD */ ++ MXC_DCD_ITEM(0x021b0030, MDOR_VAL) ++ MXC_DCD_ITEM(0x021b0008, MDOTC_VAL) ++ MXC_DCD_ITEM(0x021b0004, MDPDC_VAL_0) ++ MXC_DCD_ITEM(0x021b0040, 0x00000027) /* MDASP */ ++ ++ /* CS0 MRS: */ ++ MXC_DCD_ITEM(0x021b001c, MDSCR_MRS_VAL(0, 0, mr0_val)) ++ MXC_DCD_ITEM(0x021b001c, MDSCR_MRS_VAL(0, 1, mr1_val)) ++ MXC_DCD_ITEM(0x021b001c, MDSCR_MRS_VAL(0, 2, mr2_val)) ++ MXC_DCD_ITEM(0x021b001c, MDSCR_MRS_VAL(0, 3, 0)) ++#if BANK_ADDR_BITS > 1 ++ /* CS1 MRS: MR2 */ ++ MXC_DCD_ITEM(0x021b001c, MDSCR_MRS_VAL(1, 0, mr0_val)) ++ MXC_DCD_ITEM(0x021b001c, MDSCR_MRS_VAL(1, 1, mr1_val)) ++ MXC_DCD_ITEM(0x021b001c, MDSCR_MRS_VAL(1, 2, mr2_val)) ++ MXC_DCD_ITEM(0x021b001c, MDSCR_MRS_VAL(1, 3, 4)) /* MRS: select MPR */ ++#endif ++ MXC_DCD_ITEM(0x021b0020, 0x0000c000) /* disable refresh */ ++ ++ MXC_DCD_ITEM(0x021b0818, 0x00011112) /* MPODTCTRL */ ++ MXC_DCD_ITEM(0x021b4818, 0x00011112) ++ ++ /* DDR3 calibration */ ++ MXC_DCD_ITEM(0x021b0890, 0x00000003) /* select default compare pattern for DQ calibration */ ++ MXC_DCD_ITEM(0x021b0404, 0x00011007) ++ ++ /* ZQ calibration */ ++ MXC_DCD_ITEM(0x021b001c, 0x04008010) /* precharge all */ ++ MXC_DCD_ITEM(0x021b001c, 0x04008040) /* MRS: ZQ calibration */ ++ ++ MXC_DCD_ITEM(0x021b4800, 0xa138002b) ++ MXC_DCD_ITEM(0x021b0800, 0xa139002b) ++zq_calib: ++ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b0800, 0x00010000) ++ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, wl_calib) ++ ++ /* Write leveling */ ++ MXC_DCD_ITEM(0x021b4800, 0xa1380000) ++ MXC_DCD_ITEM(0x021b0800, 0xa1380000) ++ ++ MXC_DCD_ITEM(0x021b001c, MDSCR_MRS_VAL(0, 3, 4)) /* MRS: select MPR */ ++ MXC_DCD_ITEM(0x021b001c, 0x00808231) /* MRS: start write leveling */ ++ ++ MXC_DCD_ITEM(0x021b0808, 0x00000001) /* initiate Write leveling */ ++wl_calib: ++ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b0808, 0x00000001) ++ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b0808, 0x00000f00) ++ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b4808, 0x00000001) ++ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b4808, 0x00000f00) ++ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, dqs_fifo_reset) ++ ++ MXC_DCD_ITEM(0x021b0800, 0xa138002b) ++ MXC_DCD_ITEM(0x021b4800, 0xa138002b) ++ ++ MXC_DCD_ITEM(0x021b001c, MDSCR_MRS_VAL(0, 1, mr1_val)) /* MRS: end write leveling */ ++ ++ /* DQS gating calibration */ ++ MXC_DCD_ITEM(0x020e05a8, SDQS_MASK | 0x7000) /* enable Pullups on DQS pads */ ++ MXC_DCD_ITEM(0x020e05b0, SDQS_MASK | 0x7000) ++ MXC_DCD_ITEM(0x020e0524, SDQS_MASK | 0x7000) ++ MXC_DCD_ITEM(0x020e051c, SDQS_MASK | 0x7000) ++ MXC_DCD_ITEM(0x020e0518, SDQS_MASK | 0x7000) ++ MXC_DCD_ITEM(0x020e050c, SDQS_MASK | 0x7000) ++ MXC_DCD_ITEM(0x020e05b8, SDQS_MASK | 0x7000) ++ MXC_DCD_ITEM(0x020e05c0, SDQS_MASK | 0x7000) ++ MXC_DCD_ITEM(0x021b0018, MDMISC_VAL | (7 << 6) | (3 << 16)) /* RALAT/WALAT max. */ ++ ++ MXC_DCD_ITEM(0x021b001c, 0x00008020) /* issue one refresh cycle */ ++ MXC_DCD_ITEM(0x021b001c, 0x04008050) /* precharge all to bank 0 */ ++ ++ MXC_DCD_ITEM(0x021b0848, 0x40404040) /* DQ RD Delay default values */ ++ MXC_DCD_ITEM(0x021b4848, 0x40404040) ++ MXC_DCD_ITEM(0x021b0850, 0x40404040) /* DQ WR Delay default values */ ++ MXC_DCD_ITEM(0x021b4850, 0x40404040) ++ MXC_DCD_ITEM(0x021b48b8, 0x00000800) ++ MXC_DCD_ITEM(0x021b08b8, 0x00000800) ++ ++ MXC_DCD_ITEM(0x021b083c, 0x80000000) /* issue fifo reset */ ++dqs_fifo_reset: ++ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b083c, 0x80000000) ++ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, dqs_fifo_reset2) ++ MXC_DCD_ITEM(0x021b083c, 0x80000000) /* issue 2nd fifo reset */ ++dqs_fifo_reset2: ++ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b083c, 0x80000000) ++ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, dqs_calib) ++ MXC_DCD_ITEM(0x021b083c, 0x50800000) /* choose 32 wait cycles and start DQS calib. */ ++dqs_calib: ++ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b083c, 0x10000000) ++ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b083c, 0x00001000) ++ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b483c, 0x10000000) ++ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b483c, 0x00001000) ++ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, rd_dl_calib) ++ ++ /* DRAM_SDQS[0..7] pad config */ ++ MXC_DCD_ITEM(0x020e05a8, SDQS_MASK) ++ MXC_DCD_ITEM(0x020e05b0, SDQS_MASK) ++ MXC_DCD_ITEM(0x020e0524, SDQS_MASK) ++ MXC_DCD_ITEM(0x020e051c, SDQS_MASK) ++ MXC_DCD_ITEM(0x020e0518, SDQS_MASK) ++ MXC_DCD_ITEM(0x020e050c, SDQS_MASK) ++ MXC_DCD_ITEM(0x020e05b8, SDQS_MASK) ++ MXC_DCD_ITEM(0x020e05c0, SDQS_MASK) ++ ++ MXC_DCD_ITEM(0x021b0018, MDMISC_VAL) ++ ++ /* Read delay calibration */ ++ MXC_DCD_ITEM(0x021b001c, 0x04008050) /* precharge all to bank 0 */ ++ MXC_DCD_ITEM(0x021b0860, 0x00000030) /* MPRDDLHWCTL: HW_RD_DL_EN */ ++rd_dl_calib: ++ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b0860, 0x00000010) ++ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b4860, 0x00000010) ++ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b0860, 0x0000000f) ++ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b4860, 0x0000000f) ++ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, wr_dl_calib) ++ ++ MXC_DCD_ITEM(0x021b001c, 0x04008050) /* precharge all to bank 0 */ ++ MXC_DCD_ITEM(0x021b0864, 0x00000030) /* start WR DL calibration */ ++wr_dl_calib: ++ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b0864, 0x00000010) ++ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b4864, 0x00000010) ++ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b0864, 0x0000000f) ++ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b4864, 0x0000000f) ++ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, con_ack_clr) ++ ++ MXC_DCD_ITEM(0x021b001c, MDSCR_MRS_VAL(0, 3, 0)) /* MRS: select normal data path */ ++ MXC_DCD_ITEM(0x021b0020, 0x00005800) /* MDREF */ ++ MXC_DCD_ITEM(0x021b0404, 0x00011006) /* MAPSR */ ++ MXC_DCD_ITEM(0x021b0004, MDPDC_VAL_1) ++ ++ /* MDSCR: Normal operation */ ++ MXC_DCD_ITEM(0x021b001c, 0x00000000) ++con_ack_clr: ++ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b001c, 0x00004000) ++dcd_end: ++ .ifgt dcd_end - dcd_start - 1768 ++ DCD too large! ++ .endif diff --cc board/karo/tx6q/lowlevel_init.S.borked index 0000000000,0000000000..ce22da1e85 new file mode 100644 --- /dev/null +++ b/board/karo/tx6q/lowlevel_init.S.borked @@@ -1,0 -1,0 +1,621 @@@ ++#include ++#include ++#include ++ ++#define DEBUG_LED_BIT 20 ++#define LED_GPIO_BASE GPIO2_BASE_ADDR ++#define LED_MUX_OFFSET 0x0ec ++#define LED_MUX_MODE 0x15 ++ ++#define SDRAM_CLK CONFIG_SYS_SDRAM_CLK ++ ++#ifdef PHYS_SDRAM_2_SIZE ++#define SDRAM_SIZE (PHYS_SDRAM_1_SIZE + PHYS_SDRAM_2_SIZE) ++#else ++#define SDRAM_SIZE PHYS_SDRAM_1_SIZE ++#endif ++ ++#define CPU_2_BE_32(l) \ ++ ((((l) << 24) & 0xFF000000) | \ ++ (((l) << 8) & 0x00FF0000) | \ ++ (((l) >> 8) & 0x0000FF00) | \ ++ (((l) >> 24) & 0x000000FF)) ++ ++#define MXC_DCD_ITEM(addr, val) .word CPU_2_BE_32(addr), CPU_2_BE_32(val) ++ ++#define CHECK_DCD_ADDR(a) ((((a) >= 0x00907000) && ((a) <= 0x00937FF0)) || \ ++ (((a) >= 0x020C4000) && ((a) < 0x020C8000)) || \ ++ (((a) >= 0x020C8000) && ((a) < 0x020C9000)) || \ ++ (((a) >= 0x020E0000) && ((a) < 0x020E4000)) || \ ++ (((a) >= 0x021B0000) && ((a) < 0x021B8000)) || \ ++ (((a) >= 0x08000000) && ((a) < 0x0FFF0000)) || \ ++ (((a) >= 0x10000000))) ++ ++#define MXC_DCD_CMD_SZ_BYTE 1 ++#define MXC_DCD_CMD_SZ_SHORT 2 ++#define MXC_DCD_CMD_SZ_WORD 4 ++#define MXC_DCD_CMD_FLAG_WRITE 0x0 ++#define MXC_DCD_CMD_FLAG_CLR 0x1 ++#define MXC_DCD_CMD_FLAG_SET 0x3 ++#define MXC_DCD_CMD_FLAG_CHK_ANY (1 << 0) ++#define MXC_DCD_CMD_FLAG_CHK_SET (1 << 1) ++#define MXC_DCD_CMD_FLAG_CHK_CLR (0 << 1) ++ ++#define MXC_DCD_CMD_WRT(type, flags, next) \ ++ .word CPU_2_BE_32((0xcc << 24) | (((next) - .) << 8) | ((flags) << 3) | (type)) ++ ++#define MXC_DCD_CMD_CHK(type, flags, addr, mask) \ ++ .word CPU_2_BE_32((0xcf << 24) | (12 << 8) | ((flags) << 3) | (type)),\ ++ CPU_2_BE_32(addr), CPU_2_BE_32(mask) ++ ++#define MXC_DCD_CMD_CHK_CNT(type, flags, addr, mask, count) \ ++ .word CPU_2_BE_32((0xcf << 24) | (16 << 8) | ((flags) << 3) | (type)),\ ++ CPU_2_BE_32(addr), CPU_2_BE_32(mask), CPU_2_BE_32(count) ++ ++#define MXC_DCD_CMD_NOP \ ++ .word CPU_2_BE_32((0xc0 << 24) | (4 << 8)) ++ ++#define CK_TO_NS(ck) (((ck) * 1000 + SDRAM_CLK / 2) / SDRAM_CLK) ++#define NS_TO_CK(ns) (((ns) * SDRAM_CLK + 999) / 1000) ++ ++ .macro CK_VAL, name, clks, offs, max ++ .iflt \clks - \offs ++ .set \name, 0 ++ .else ++ .ifle \clks - \offs - \max ++ .set \name, \clks - \offs ++ .endif ++ .endif ++ .endm ++ ++ .macro NS_VAL, name, ns, offs, max ++ .iflt \ns - \offs ++ .set \name, 0 ++ .else ++ CK_VAL \name, NS_TO_CK(\ns), \offs, \max ++ .endif ++ .endm ++ ++ .macro CK_MAX, name, ck1, ck2, offs, max ++ .ifgt \ck1 - \ck2 ++ CK_VAL \name, \ck1, \offs, \max ++ .else ++ CK_VAL \name, \ck2, \offs, \max ++ .endif ++ .endm ++ ++#define MDMISC_DDR_TYPE_DDR3 0 ++#define MDMISC_DDR_TYPE_LPDDR2 1 ++#define MDMISC_DDR_TYPE_DDR2 2 ++ ++#define DIV_ROUND_UP(m,d) (((m) + (d) - 1) / (d)) ++ ++#define MDOR_CLK_PERIOD_ns 15258 /* base clock for MDOR values */ ++ ++/* DDR3 SDRAM */ ++#if SDRAM_SIZE > PHYS_SDRAM_1_SIZE ++#define BANK_ADDR_BITS 2 ++#else ++#define BANK_ADDR_BITS 1 ++#endif ++#define SDRAM_BURST_LENGTH 8 ++#define RALAT 5 ++#define WALAT 0 ++#define BI_ON 1 ++#define ADDR_MIRROR 1 ++#define DDR_TYPE MDMISC_DDR_TYPE_DDR3 ++ ++/* 512/1024MiB SDRAM: NT5CB128M16P-CG */ ++/* MDCFG0 0x0c */ ++NS_VAL tRFC, 160, 1, 255 /* clks - 1 (0..255) */ ++CK_MAX tXS, tRFC + 1 + NS_TO_CK(10), 5, 1, 255 /* clks - 1 (0..255) tRFC + 10 */ ++CK_MAX tXP, 3, NS_TO_CK(6), 1, 7 /* clks - 1 (0..7) */ /* max(6ns, 3*CK) */ ++CK_MAX tXPDLL, NS_TO_CK(24), 2, 1, 15 /* clks - 1 (0..15) */ ++NS_VAL tFAW, 45, 1, 31 /* clks - 1 (0..31) */ ++CK_VAL tCL, 8, 3, 8 /* clks - 3 (0..8) CAS Latency */ ++ ++/* MDCFG1 0x10 */ ++NS_VAL tRCD, 14, 1, 7 /* clks - 1 (0..7) */ ++NS_VAL tRP, 14, 1, 7 /* clks - 1 (0..7) */ ++NS_VAL tRC, 50, 1, 31 /* clks - 1 (0..31) */ ++NS_VAL tRAS, 36, 1, 31 /* clks - 1 (0..31) */ ++CK_VAL tRPA, 0, 0, 1 /* clks (0..1) */ ++NS_VAL tWR, 15, 1, 15 /* clks - 1 (0..15) */ ++CK_VAL tMRD, 4, 1, 15 /* clks - 1 (0..15) */ ++CK_VAL tCWL, 6, 2, 6 /* clks - 2 (0..6) */ ++ ++/* MDCFG2 0x14 */ ++CK_VAL tDLLK, 512, 1, 511 /* clks - 1 (0..511) */ ++CK_MAX tRTP, 4, NS_TO_CK(8), 1, 7 /* clks - 1 (0..7) */ ++CK_MAX tWTR, 4, NS_TO_CK(8), 1, 7 /* clks - 1 (0..7) */ ++CK_MAX tRRD, 4, NS_TO_CK(8), 1, 7 /* clks - 1 (0..7) */ ++ ++/* MDOR 0x30 */ ++CK_MAX tXPR, NS_TO_CK(CK_TO_NS(tRFC + 1) + 10), 5, 1, 255 /* clks - 1 (0..255) max(tRFC + 10, 5CK) */ ++#define tSDE_RST (DIV_ROUND_UP(200000, MDOR_CLK_PERIOD_ns) + 2) ++#define tRST_CKE (DIV_ROUND_UP(500000, MDOR_CLK_PERIOD_ns) + 2) ++ ++/* MDOTC 0x08 */ ++NS_VAL tAOFPD, 9, 1, 7 /* clks - 1 (0..7) */ ++NS_VAL tAONPD, 9, 1, 7 /* clks - 1 (0..7) */ ++CK_VAL tANPD, tCWL + 1, 1, 15 /* clks - 1 (0..15) */ ++CK_VAL tAXPD, tCWL + 1, 1, 15 /* clks - 1 (0..15) */ ++CK_VAL tODTLon tCWL, 1, 7 /* clks - 1 (0..7) */ ++CK_VAL tODTLoff tCWL, 1, 31 /* clks - 1 (0..31) */ ++ ++/* MDPDC 0x04 */ ++CK_MAX tCKE, NS_TO_CK(6), 3, 1, 7 ++CK_MAX tCKSRX, NS_TO_CK(10), 5, 0, 7 ++CK_MAX tCKSRE, NS_TO_CK(10), 5, 0, 7 ++ ++#define PRCT 0 ++#define PWDT 5 ++#define SLOW_PD 0 ++#define BOTH_CS_PD 1 ++ ++#define MDPDC_VAL_0 ( \ ++ (PRCT << 28) | \ ++ (PRCT << 24) | \ ++ (tCKE << 16) | \ ++ (SLOW_PD << 7) | \ ++ (BOTH_CS_PD << 6) | \ ++ (tCKSRX << 3) | \ ++ (tCKSRE << 0) \ ++ ) ++ ++#define MDPDC_VAL_1 (MDPDC_VAL_0 | \ ++ (PWDT << 12) | \ ++ (PWDT << 8) \ ++ ) ++ ++#define ROW_ADDR_BITS 14 ++#define COL_ADDR_BITS 10 ++ ++ .iflt tWR - 7 ++ .set mr0_val, ((1 << 8) /* DLL Reset */ | \ ++ ((tWR + 1 - 4) << 9) | \ ++ (((tCL + 3) - 4) << 4)) ++ .else ++ .set mr0_val, ((1 << 8) /* DLL Reset */ | \ ++ (((tWR + 1) / 2) << 9) | \ ++ (((tCL + 3) - 4) << 4)) ++ .endif ++#define MDSCR_MRS_VAL(cs, mr, val) (((val) << 16) | \ ++ (1 << 15) /* CON REQ */ | \ ++ (3 << 4) /* MRS command */ | \ ++ ((cs) << 3) | \ ++ ((mr) << 0)) ++ ++#define mr1_val 0x0040 ++#define mr2_val 0x0408 ++ ++#define MDCFG0_VAL ( \ ++ (tRFC << 24) | \ ++ (tXS << 16) | \ ++ (tXP << 13) | \ ++ (tXPDLL << 9) | \ ++ (tFAW << 4) | \ ++ (tCL << 0)) \ ++ ++#define MDCFG1_VAL ( \ ++ (tRCD << 29) | \ ++ (tRP << 26) | \ ++ (tRC << 21) | \ ++ (tRAS << 16) | \ ++ (tRPA << 15) | \ ++ (tWR << 9) | \ ++ (tMRD << 5) | \ ++ (tCWL << 0)) \ ++ ++#define MDCFG2_VAL ( \ ++ (tDLLK << 16) | \ ++ (tRTP << 6) | \ ++ (tWTR << 3) | \ ++ (tRRD << 0)) ++ ++#define BURST_LEN (SDRAM_BURST_LENGTH / 8) /* 0: 4 byte 1: 8 byte */ ++#define MDCTL_VAL (((ROW_ADDR_BITS - 11) << 24) | \ ++ ((COL_ADDR_BITS - 9) << 20) | \ ++ (BURST_LEN << 19) | \ ++ (2 << 16) | /* SDRAM bus width */ \ ++ ((-1) << (32 - BANK_ADDR_BITS))) ++ ++#define MDMISC_VAL ((ADDR_MIRROR << 19) | \ ++ (WALAT << 16) | \ ++ (BI_ON << 12) | \ ++ (0x3 << 9) | \ ++ (RALAT << 6) | \ ++ (DDR_TYPE << 3)) ++ ++#define MDOR_VAL ((tXPR << 16) | (tSDE_RST << 8) | (tRST_CKE << 0)) ++ ++#define MDOTC_VAL ((tAOFPD << 27) | \ ++ (tAONPD << 24) | \ ++ (tANPD << 20) | \ ++ (tAXPD << 16) | \ ++ (tODTLon << 12) | \ ++ (tODTLoff << 4)) ++ ++fcb_start: ++ b _start ++ .org 0x400 ++ivt_header: ++ .word CPU_2_BE_32((0xd1 << 24) | (32 << 8) | 0x40) ++app_start_addr: ++ .long _start ++ .long 0x0 ++dcd_ptr: ++ .long dcd_hdr ++boot_data_ptr: ++ .word boot_data ++self_ptr: ++ .word ivt_header ++app_code_csf: ++ .word 0x0 ++ .word 0x0 ++boot_data: ++ .long fcb_start ++image_len: ++ .long CONFIG_U_BOOT_IMG_SIZE ++plugin: ++ .word 0 ++ivt_end: ++#define DCD_VERSION 0x40 ++ ++#define CLKCTL_CCGR0 0x68 ++#define CLKCTL_CCGR1 0x6c ++#define CLKCTL_CCGR2 0x70 ++#define CLKCTL_CCGR3 0x74 ++#define CLKCTL_CCGR4 0x78 ++#define CLKCTL_CCGR5 0x7c ++#define CLKCTL_CCGR6 0x80 ++#define CLKCTL_CCGR7 0x84 ++#define CLKCTL_CMEOR 0x88 ++ ++#define DDR_SEL_VAL 3 ++#define DSE_VAL 6 ++#define ODT_VAL 2 ++ ++#define DDR_SEL_SHIFT 18 ++#define DDR_MODE_SHIFT 17 ++#define ODT_SHIFT 8 ++#define DSE_SHIFT 3 ++#define HYS_SHIFT 16 ++#define PKE_SHIFT 12 ++#define PUE_SHIFT 13 ++#define PUS_SHIFT 14 ++ ++#define DDR_SEL_MASK (DDR_SEL_VAL << DDR_SEL_SHIFT) ++#define DDR_MODE_MASK (1 << DDR_MODE_SHIFT) ++#define DSE_MASK (DSE_VAL << DSE_SHIFT) ++#define ODT_MASK (ODT_VAL << ODT_SHIFT) ++ ++#define DQM_MASK (DDR_MODE_MASK | DSE_MASK) ++#define SDQS_MASK DSE_MASK ++#define SDODT_MASK (DSE_MASK | (1 << PKE_SHIFT) | (1 << PUE_SHIFT) | (0 << PUS_SHIFT)) ++#define SDCLK_MASK (DDR_MODE_MASK | DSE_MASK) ++#define SDCKE_MASK ((1 << PKE_SHIFT) | (1 << PUE_SHIFT) | (0 << PUS_SHIFT)) ++#define DDR_ADDR_MASK 0 ++#define DDR_CTRL_MASK (DDR_MODE_MASK | DSE_MASK) ++ ++dcd_hdr: ++ .word CPU_2_BE_32((0xd2 << 24) | ((dcd_end - .) << 8) | DCD_VERSION) ++dcd_start: ++ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, ddr_reset) ++ /* RESET_OUT GPIO_7_12 */ ++ MXC_DCD_ITEM(0x020e024c, 0x00000005) ++ ++ MXC_DCD_ITEM(0x020c402c, 0x01e436c1) /* CSC2CDR default: 0x007236c1 */ ++ MXC_DCD_ITEM(0x020c80e0, 0x00002001) /* ENET PLL */ ++ ++ /* enable all relevant clocks... */ ++ MXC_DCD_ITEM(0x020c4068, 0xf0c03f3f) /* default: 0xf0c03f0f APBH-DMA */ ++ MXC_DCD_ITEM(0x020c406c, 0xf0fc0c00) /* default: 0xf0fc0000 */ ++ MXC_DCD_ITEM(0x020c4070, 0xfc3ff0cc) /* default: 0xfc3ff00c I2C1 */ ++ MXC_DCD_ITEM(0x020c4074, 0x3ff00000) /* default: 0x3ff00000 */ ++ MXC_DCD_ITEM(0x020c4078, 0xff00ff00) /* default: 0x0000ff00 GPMI BCH */ ++ MXC_DCD_ITEM(0x020c407c, 0xff033f0f) /* default: 0xf0033f0f UART1 */ ++ MXC_DCD_ITEM(0x020c4080, 0xffff03ff) /* default: 0xffff0003 USDHC4 (for APBH-DMA!) USDHC3 (for BCH!) */ ++ ++ /* IOMUX: */ ++ MXC_DCD_ITEM(0x020e0004, 0x48640005) /* default: 0x48400005 ENET_CLK output */ ++ /* UART1 pad config */ ++ MXC_DCD_ITEM(0x020e02a8, 0x00000001) /* UART1 TXD */ ++ MXC_DCD_ITEM(0x020e02ac, 0x00000001) /* UART1 RXD */ ++ MXC_DCD_ITEM(0x020e0920, 0x00000003) /* UART1 RXD INPUT_SEL */ ++ MXC_DCD_ITEM(0x020e02c0, 0x00000001) /* UART1 CTS */ ++ MXC_DCD_ITEM(0x020e02c4, 0x00000001) /* UART1 RTS */ ++ MXC_DCD_ITEM(0x020e091c, 0x00000003) /* UART1 RTS INPUT_SEL */ ++#if 0 ++ /* NAND */ ++ MXC_DCD_ITEM(0x020e02d4, 0x00000000) /* NANDF_CLE: NANDF_CLE */ ++ MXC_DCD_ITEM(0x020e02d8, 0x00000000) /* NANDF_ALE: NANDF_ALE */ ++ MXC_DCD_ITEM(0x020e02dc, 0x00000000) /* NANDF_WP_B: NANDF_WPn */ ++ MXC_DCD_ITEM(0x020e02e0, 0x00000000) /* NANDF_RB0: NANDF_READY0 */ ++ MXC_DCD_ITEM(0x020e02e4, 0x00000000) /* NANDF_CS0: NANDF_CS0 */ ++ MXC_DCD_ITEM(0x020e02f4, 0x00000001) /* SD4_CMD: NANDF_RDn */ ++ MXC_DCD_ITEM(0x020e02f8, 0x00000001) /* SD4_CLK: NANDF_WRn */ ++ MXC_DCD_ITEM(0x020e02fc, 0x00000000) /* NANDF_D0: NANDF_D0 */ ++ MXC_DCD_ITEM(0x020e0300, 0x00000000) /* NANDF_D1: NANDF_D1 */ ++ MXC_DCD_ITEM(0x020e0304, 0x00000000) /* NANDF_D2: NANDF_D2 */ ++ MXC_DCD_ITEM(0x020e0308, 0x00000000) /* NANDF_D3: NANDF_D3 */ ++ MXC_DCD_ITEM(0x020e030c, 0x00000000) /* NANDF_D4: NANDF_D4 */ ++ MXC_DCD_ITEM(0x020e0310, 0x00000000) /* NANDF_D5: NANDF_D5 */ ++ MXC_DCD_ITEM(0x020e0314, 0x00000000) /* NANDF_D6: NANDF_D6 */ ++ MXC_DCD_ITEM(0x020e0318, 0x00000000) /* NANDF_D7: NANDF_D7 */ ++#endif ++ /* ext. mem CS */ ++ MXC_DCD_ITEM(0x020e02ec, 0x00000000) /* NANDF_CS2: NANDF_CS2 */ ++ /* DRAM_DQM[0..7] */ ++ MXC_DCD_ITEM(0x020e05ac, DQM_MASK) ++ MXC_DCD_ITEM(0x020e05b4, DQM_MASK) ++ MXC_DCD_ITEM(0x020e0528, DQM_MASK) ++ MXC_DCD_ITEM(0x020e0520, DQM_MASK) ++ MXC_DCD_ITEM(0x020e0514, DQM_MASK) ++ MXC_DCD_ITEM(0x020e0510, DQM_MASK) ++ MXC_DCD_ITEM(0x020e05bc, DQM_MASK) ++ MXC_DCD_ITEM(0x020e05c4, DQM_MASK) ++ /* DRAM_A[0..15] */ ++ MXC_DCD_ITEM(0x020e052c, DDR_ADDR_MASK) ++ MXC_DCD_ITEM(0x020e0530, DDR_ADDR_MASK) ++ MXC_DCD_ITEM(0x020e0534, DDR_ADDR_MASK) ++ MXC_DCD_ITEM(0x020e0538, DDR_ADDR_MASK) ++ MXC_DCD_ITEM(0x020e053c, DDR_ADDR_MASK) ++ MXC_DCD_ITEM(0x020e0540, DDR_ADDR_MASK) ++ MXC_DCD_ITEM(0x020e0544, DDR_ADDR_MASK) ++ MXC_DCD_ITEM(0x020e0548, DDR_ADDR_MASK) ++ MXC_DCD_ITEM(0x020e054c, DDR_ADDR_MASK) ++ MXC_DCD_ITEM(0x020e0550, DDR_ADDR_MASK) ++ MXC_DCD_ITEM(0x020e0554, DDR_ADDR_MASK) ++ MXC_DCD_ITEM(0x020e0558, DDR_ADDR_MASK) ++ MXC_DCD_ITEM(0x020e055c, DDR_ADDR_MASK) ++ MXC_DCD_ITEM(0x020e0560, DDR_ADDR_MASK) ++ MXC_DCD_ITEM(0x020e0564, DDR_ADDR_MASK) ++ MXC_DCD_ITEM(0x020e0568, DDR_ADDR_MASK) ++ /* DRAM_CAS */ ++ MXC_DCD_ITEM(0x020e056c, DDR_CTRL_MASK) ++ /* DRAM_RAS */ ++ MXC_DCD_ITEM(0x020e0578, DDR_CTRL_MASK) ++ /* DRAM_SDCLK[0..1] */ ++ MXC_DCD_ITEM(0x020e0588, SDCLK_MASK) ++ MXC_DCD_ITEM(0x020e0594, SDCLK_MASK) ++ /* DRAM_RESET */ ++ MXC_DCD_ITEM(0x020e057c, DDR_CTRL_MASK) ++ /* DRAM_SDCKE[0..1] */ ++ MXC_DCD_ITEM(0x020e0590, SDCKE_MASK) ++ MXC_DCD_ITEM(0x020e0598, SDCKE_MASK) ++ /* DRAM_SDBA[0..2] */ ++ MXC_DCD_ITEM(0x020e0580, 0x00000000) ++ MXC_DCD_ITEM(0x020e0584, 0x00000000) ++ MXC_DCD_ITEM(0x020e058c, 0x00000000) ++ /* DRAM_SDODT[0..1] */ ++ MXC_DCD_ITEM(0x020e059c, SDODT_MASK) ++ MXC_DCD_ITEM(0x020e05a0, SDODT_MASK) ++ /* DRAM_B[0..7]DS */ ++ MXC_DCD_ITEM(0x020e0784, DSE_MASK) ++ MXC_DCD_ITEM(0x020e0788, DSE_MASK) ++ MXC_DCD_ITEM(0x020e0794, DSE_MASK) ++ MXC_DCD_ITEM(0x020e079c, DSE_MASK) ++ MXC_DCD_ITEM(0x020e07a0, DSE_MASK) ++ MXC_DCD_ITEM(0x020e07a4, DSE_MASK) ++ MXC_DCD_ITEM(0x020e07a8, DSE_MASK) ++ MXC_DCD_ITEM(0x020e0748, DSE_MASK) ++ /* ADDDS */ ++ MXC_DCD_ITEM(0x020e074c, DSE_MASK) ++ /* DDRMODE_CTL */ ++ MXC_DCD_ITEM(0x020e0750, DDR_MODE_MASK) ++ /* DDRPKE */ ++ MXC_DCD_ITEM(0x020e0758, 0x00000000) ++ /* DDRMODE */ ++ MXC_DCD_ITEM(0x020e0774, DDR_MODE_MASK) ++ /* CTLDS */ ++ MXC_DCD_ITEM(0x020e078c, DSE_MASK) ++ /* DDR_TYPE */ ++ MXC_DCD_ITEM(0x020e0798, DDR_SEL_MASK) ++ /* DDRPK */ ++ MXC_DCD_ITEM(0x020e0768, 1 << PUE_SHIFT) ++ /* DDRHYS */ ++ MXC_DCD_ITEM(0x020e0770, 0x00000000) ++ /* TERM_CTL[0..7] */ ++ MXC_DCD_ITEM(0x020e0754, ODT_MASK) ++ MXC_DCD_ITEM(0x020e075c, ODT_MASK) ++ MXC_DCD_ITEM(0x020e0760, ODT_MASK) ++ MXC_DCD_ITEM(0x020e0764, ODT_MASK) ++ MXC_DCD_ITEM(0x020e076c, ODT_MASK) ++ MXC_DCD_ITEM(0x020e0778, ODT_MASK) ++ MXC_DCD_ITEM(0x020e077c, ODT_MASK) ++ MXC_DCD_ITEM(0x020e0780, ODT_MASK) ++ ++ /* SDRAM initialization */ ++ /* MPRDDQBY[0..7]DL */ ++ MXC_DCD_ITEM(0x021b081c, 0x33333333) ++ MXC_DCD_ITEM(0x021b481c, 0x33333333) ++ MXC_DCD_ITEM(0x021b0820, 0x33333333) ++ MXC_DCD_ITEM(0x021b4820, 0x33333333) ++ MXC_DCD_ITEM(0x021b0824, 0x33333333) ++ MXC_DCD_ITEM(0x021b4824, 0x33333333) ++ MXC_DCD_ITEM(0x021b0828, 0x33333333) ++ MXC_DCD_ITEM(0x021b4828, 0x33333333) ++ /* MDMISC */ ++ MXC_DCD_ITEM(0x021b0018, MDMISC_VAL | 2) /* reset MMDC FSM */ ++ddr_reset: ++ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b0018, 0x00000002) ++ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, con_ack) ++ ++ /* MSDSCR Conf Req */ ++ MXC_DCD_ITEM(0x021b001c, 0x00008000) ++con_ack: ++ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_SET, 0x021b001c, 0x00004000) ++ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, ddr_calib) ++ /* MDCTL */ ++ MXC_DCD_ITEM(0x021b0000, MDCTL_VAL) ++ddr_calib: ++ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_SET, 0x021b0018, 0x40000000) ++ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, zq_calib) ++ ++ MXC_DCD_ITEM(0x021b000c, MDCFG0_VAL) ++ MXC_DCD_ITEM(0x021b0010, MDCFG1_VAL) ++ MXC_DCD_ITEM(0x021b0014, MDCFG2_VAL) ++ MXC_DCD_ITEM(0x021b002c, 0x000026d2) /* MDRWD */ ++ MXC_DCD_ITEM(0x021b0030, MDOR_VAL) ++ MXC_DCD_ITEM(0x021b0008, MDOTC_VAL) ++ MXC_DCD_ITEM(0x021b0004, MDPDC_VAL_0) ++ MXC_DCD_ITEM(0x021b0040, 0x00000027) /* MDASP */ ++ ++ /* CS0 MRS: */ ++ MXC_DCD_ITEM(0x021b001c, MDSCR_MRS_VAL(0, 0, mr0_val)) ++ MXC_DCD_ITEM(0x021b001c, MDSCR_MRS_VAL(0, 1, mr1_val)) ++ MXC_DCD_ITEM(0x021b001c, MDSCR_MRS_VAL(0, 2, mr2_val)) ++ MXC_DCD_ITEM(0x021b001c, MDSCR_MRS_VAL(0, 3, 0)) ++#if BANK_ADDR_BITS > 1 ++ /* CS1 MRS: MR2 */ ++ MXC_DCD_ITEM(0x021b001c, MDSCR_MRS_VAL(1, 0, mr0_val)) ++ MXC_DCD_ITEM(0x021b001c, MDSCR_MRS_VAL(1, 1, mr1_val)) ++ MXC_DCD_ITEM(0x021b001c, MDSCR_MRS_VAL(1, 2, mr2_val)) ++ MXC_DCD_ITEM(0x021b001c, MDSCR_MRS_VAL(1, 3, 4)) /* MRS: select MPR */ ++#endif ++ MXC_DCD_ITEM(0x021b0020, 0x0000c000) /* disable refresh */ ++ ++ MXC_DCD_ITEM(0x021b0818, 0x00011112) /* MPODTCTRL */ ++ MXC_DCD_ITEM(0x021b4818, 0x00011112) ++ ++ /* DDR3 calibration */ ++ MXC_DCD_ITEM(0x021b0890, 0x00000003) /* select default compare pattern for DQ calibration */ ++ MXC_DCD_ITEM(0x021b0404, 0x00011007) ++ ++ /* ZQ calibration */ ++ MXC_DCD_ITEM(0x021b001c, 0x04008010) /* precharge all */ ++ MXC_DCD_ITEM(0x021b001c, 0x04008040) /* MRS: ZQ calibration */ ++ ++ MXC_DCD_ITEM(0x021b4800, 0xa138002b) ++ MXC_DCD_ITEM(0x021b0800, 0xa139002b) ++zq_calib: ++ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b0800, 0x00010000) ++ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, wl_calib) ++ ++ /* Write leveling */ ++ MXC_DCD_ITEM(0x021b4800, 0xa1380000) ++ MXC_DCD_ITEM(0x021b0800, 0xa1380000) ++ ++ MXC_DCD_ITEM(0x021b001c, MDSCR_MRS_VAL(0, 3, 4)) /* MRS: select MPR */ ++ MXC_DCD_ITEM(0x021b001c, 0x00808231) /* MRS: start write leveling */ ++ ++ MXC_DCD_ITEM(0x021b0808, 0x00000001) /* initiate Write leveling */ ++wl_calib: ++ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b0808, 0x00000001) ++ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b0808, 0x00000f00) ++ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b4808, 0x00000001) ++ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b4808, 0x00000f00) ++ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, dqs_fifo_reset) ++ ++ MXC_DCD_ITEM(0x021b0800, 0xa138002b) ++ MXC_DCD_ITEM(0x021b4800, 0xa138002b) ++ ++ MXC_DCD_ITEM(0x021b001c, MDSCR_MRS_VAL(0, 1, mr1_val)) /* MRS: end write leveling */ ++ ++ /* DQS gating calibration */ ++ MXC_DCD_ITEM(0x020e05a8, SDQS_MASK | 0x7000) /* enable Pullups on DQS pads */ ++ MXC_DCD_ITEM(0x020e05b0, SDQS_MASK | 0x7000) ++ MXC_DCD_ITEM(0x020e0524, SDQS_MASK | 0x7000) ++ MXC_DCD_ITEM(0x020e051c, SDQS_MASK | 0x7000) ++ MXC_DCD_ITEM(0x020e0518, SDQS_MASK | 0x7000) ++ MXC_DCD_ITEM(0x020e050c, SDQS_MASK | 0x7000) ++ MXC_DCD_ITEM(0x020e05b8, SDQS_MASK | 0x7000) ++ MXC_DCD_ITEM(0x020e05c0, SDQS_MASK | 0x7000) ++ MXC_DCD_ITEM(0x021b0018, MDMISC_VAL | (7 << 6) | (3 << 16)) /* RALAT/WALAT max. */ ++ ++ MXC_DCD_ITEM(0x021b001c, 0x00008020) /* issue one refresh cycle */ ++ MXC_DCD_ITEM(0x021b001c, 0x04008050) /* precharge all to bank 0 */ ++ ++ MXC_DCD_ITEM(0x021b0848, 0x40404040) /* DQ RD Delay default values */ ++ MXC_DCD_ITEM(0x021b4848, 0x40404040) ++ MXC_DCD_ITEM(0x021b0850, 0x40404040) /* DQ WR Delay default values */ ++ MXC_DCD_ITEM(0x021b4850, 0x40404040) ++ MXC_DCD_ITEM(0x021b48b8, 0x00000800) ++ MXC_DCD_ITEM(0x021b08b8, 0x00000800) ++ ++ MXC_DCD_ITEM(0x021b083c, 0x80000000) /* issue fifo reset */ ++dqs_fifo_reset: ++ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b083c, 0x80000000) ++ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, dqs_fifo_reset2) ++ MXC_DCD_ITEM(0x021b083c, 0x80000000) /* issue 2nd fifo reset */ ++dqs_fifo_reset2: ++ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b083c, 0x80000000) ++ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, dqs_calib) ++ MXC_DCD_ITEM(0x021b083c, 0x50800000) /* choose 32 wait cycles and start DQS calib. */ ++dqs_calib: ++ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b083c, 0x10000000) ++ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b083c, 0x00001000) ++ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b483c, 0x10000000) ++ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b483c, 0x00001000) ++ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, rd_dl_fifo_reset1) ++ ++ /* DRAM_SDQS[0..7] pad config */ ++ MXC_DCD_ITEM(0x020e05a8, SDQS_MASK) ++ MXC_DCD_ITEM(0x020e05b0, SDQS_MASK) ++ MXC_DCD_ITEM(0x020e0524, SDQS_MASK) ++ MXC_DCD_ITEM(0x020e051c, SDQS_MASK) ++ MXC_DCD_ITEM(0x020e0518, SDQS_MASK) ++ MXC_DCD_ITEM(0x020e050c, SDQS_MASK) ++ MXC_DCD_ITEM(0x020e05b8, SDQS_MASK) ++ MXC_DCD_ITEM(0x020e05c0, SDQS_MASK) ++ ++ MXC_DCD_ITEM(0x021b0018, MDMISC_VAL) ++rd_dl_fifo_reset1: ++ /* Read delay calibration */ ++ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_SET, rd_dl_fifo_reset2) ++ MXC_DCD_ITEM(0x021b083c, 0x80000000) /* issue fifo reset */ ++rd_dl_fifo_reset2: ++ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b083c, 0x80000000) ++ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_SET, rd_dl_fifo_reset3) ++ MXC_DCD_ITEM(0x021b083c, 0x80000000) /* issue 2nd fifo reset */ ++rd_dl_fifo_reset3: ++ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b083c, 0x80000000) ++ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, rd_dl_calib) ++ ++ MXC_DCD_ITEM(0x021b001c, 0x04008050) /* precharge all to bank 0 */ ++ MXC_DCD_ITEM(0x021b0860, 0x00000030) /* MPRDDLHWCTL: HW_RD_DL_EN */ ++rd_dl_calib: ++ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b0860, 0x00000010) ++ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b4860, 0x00000010) ++ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b0860, 0x0000000f) ++ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b4860, 0x0000000f) ++ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, wr_dl_fifo_reset1) ++ ++ /* Write Delay calibration */ ++wr_dl_fifo_reset1: ++ /* Read delay calibration */ ++ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_SET, wr_dl_fifo_reset2) ++ MXC_DCD_ITEM(0x021b083c, 0x80000000) /* issue fifo reset */ ++wr_dl_fifo_reset2: ++ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b083c, 0x80000000) ++ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_SET, wr_dl_fifo_reset3) ++ MXC_DCD_ITEM(0x021b083c, 0x80000000) /* issue 2nd fifo reset */ ++wr_dl_fifo_reset3: ++ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b083c, 0x80000000) ++ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, wr_dl_calib) ++ ++ MXC_DCD_ITEM(0x021b001c, 0x04008050) /* precharge all to bank 0 */ ++ MXC_DCD_ITEM(0x021b0864, 0x00000030) /* start WR DL calibration */ ++wr_dl_calib: ++ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b0864, 0x00000010) ++ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b4864, 0x00000010) ++ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b0864, 0x0000000f) ++ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b4864, 0x0000000f) ++ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, con_ack_clr) ++ ++ MXC_DCD_ITEM(0x021b001c, MDSCR_MRS_VAL(0, 3, 0)) /* MRS: select normal data path */ ++ MXC_DCD_ITEM(0x021b0020, 0x00005800) /* MDREF */ ++ MXC_DCD_ITEM(0x021b0404, 0x00011006) /* MAPSR */ ++ MXC_DCD_ITEM(0x021b0004, MDPDC_VAL_1) ++ ++ /* MDSCR: Normal operation */ ++ MXC_DCD_ITEM(0x021b001c, 0x00000000) ++con_ack_clr: ++ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b001c, 0x00004000) ++dcd_end: ++ .ifgt dcd_end - dcd_start - 1768 ++ DCD too large! ++ .endif ++dcd_size: ++ .word (1768 - (dcd_end - dcd_start)) / (3 * 4) diff --cc board/karo/tx6q/lowlevel_init.S.ok index 0000000000,0000000000..fc4f27ebef new file mode 100644 --- /dev/null +++ b/board/karo/tx6q/lowlevel_init.S.ok @@@ -1,0 -1,0 +1,609 @@@ ++#include ++#include ++#include ++ ++#define DEBUG_LED_BIT 20 ++#define LED_GPIO_BASE GPIO2_BASE_ADDR ++#define LED_MUX_OFFSET 0x0ec ++#define LED_MUX_MODE 0x15 ++ ++#define SDRAM_CLK CONFIG_SYS_SDRAM_CLK ++ ++#ifdef PHYS_SDRAM_2_SIZE ++#define SDRAM_SIZE (PHYS_SDRAM_1_SIZE + PHYS_SDRAM_2_SIZE) ++#else ++#define SDRAM_SIZE PHYS_SDRAM_1_SIZE ++#endif ++ ++#define CPU_2_BE_32(l) \ ++ ((((l) << 24) & 0xFF000000) | \ ++ (((l) << 8) & 0x00FF0000) | \ ++ (((l) >> 8) & 0x0000FF00) | \ ++ (((l) >> 24) & 0x000000FF)) ++ ++#define MXC_DCD_ITEM(addr, val) .word CPU_2_BE_32(addr), CPU_2_BE_32(val) ++ ++#define CHECK_DCD_ADDR(a) ((((a) >= 0x00907000) && ((a) <= 0x00937FF0)) || \ ++ (((a) >= 0x020C4000) && ((a) < 0x020C8000)) || \ ++ (((a) >= 0x020C8000) && ((a) < 0x020C9000)) || \ ++ (((a) >= 0x020E0000) && ((a) < 0x020E4000)) || \ ++ (((a) >= 0x021B0000) && ((a) < 0x021B8000)) || \ ++ (((a) >= 0x08000000) && ((a) < 0x0FFF0000)) || \ ++ (((a) >= 0x10000000))) ++ ++#define MXC_DCD_CMD_SZ_BYTE 1 ++#define MXC_DCD_CMD_SZ_SHORT 2 ++#define MXC_DCD_CMD_SZ_WORD 4 ++#define MXC_DCD_CMD_FLAG_WRITE 0x0 ++#define MXC_DCD_CMD_FLAG_CLR 0x1 ++#define MXC_DCD_CMD_FLAG_SET 0x3 ++#define MXC_DCD_CMD_FLAG_CHK_ANY (1 << 0) ++#define MXC_DCD_CMD_FLAG_CHK_SET (1 << 1) ++#define MXC_DCD_CMD_FLAG_CHK_CLR (0 << 1) ++ ++#define MXC_DCD_CMD_WRT(type, flags, next) \ ++ .word CPU_2_BE_32((0xcc << 24) | (((next) - .) << 8) | ((flags) << 3) | (type)) ++ ++#define MXC_DCD_CMD_CHK(type, flags, addr, mask) \ ++ .word CPU_2_BE_32((0xcf << 24) | (12 << 8) | ((flags) << 3) | (type)),\ ++ CPU_2_BE_32(addr), CPU_2_BE_32(mask) ++ ++#define MXC_DCD_CMD_CHK_CNT(type, flags, addr, mask, count) \ ++ .word CPU_2_BE_32((0xcf << 24) | (16 << 8) | ((flags) << 3) | (type)),\ ++ CPU_2_BE_32(addr), CPU_2_BE_32(mask), CPU_2_BE_32(count) ++ ++#define MXC_DCD_CMD_NOP \ ++ .word CPU_2_BE_32((0xc0 << 24) | (4 << 8)) ++ ++#define CK_TO_NS(ck) (((ck) * 1000 + SDRAM_CLK / 2) / SDRAM_CLK) ++#define NS_TO_CK(ns) (((ns) * SDRAM_CLK + 999) / 1000) ++ ++ .macro CK_VAL, name, clks, offs, max ++ .iflt \clks - \offs ++ .set \name, 0 ++ .else ++ .ifle \clks - \offs - \max ++ .set \name, \clks - \offs ++ .endif ++ .endif ++ .endm ++ ++ .macro NS_VAL, name, ns, offs, max ++ .iflt \ns - \offs ++ .set \name, 0 ++ .else ++ CK_VAL \name, NS_TO_CK(\ns), \offs, \max ++ .endif ++ .endm ++ ++ .macro CK_MAX, name, ck1, ck2, offs, max ++ .ifgt \ck1 - \ck2 ++ CK_VAL \name, \ck1, \offs, \max ++ .else ++ CK_VAL \name, \ck2, \offs, \max ++ .endif ++ .endm ++ ++#define MDMISC_DDR_TYPE_DDR3 0 ++#define MDMISC_DDR_TYPE_LPDDR2 1 ++#define MDMISC_DDR_TYPE_DDR2 2 ++ ++#define DIV_ROUND_UP(m,d) (((m) + (d) - 1) / (d)) ++ ++#define MDOR_CLK_PERIOD_ns 15258 /* base clock for MDOR values */ ++ ++/* DDR3 SDRAM */ ++#if SDRAM_SIZE > PHYS_SDRAM_1_SIZE ++#define BANK_ADDR_BITS 2 ++#else ++#define BANK_ADDR_BITS 1 ++#endif ++#define SDRAM_BURST_LENGTH 8 ++#define RALAT 5 ++#define WALAT 0 ++#define BI_ON 1 ++#define ADDR_MIRROR 1 ++#define DDR_TYPE MDMISC_DDR_TYPE_DDR3 ++ ++/* 512/1024MiB SDRAM: NT5CB128M16P-CG */ ++/* MDCFG0 0x0c */ ++NS_VAL tRFC, 160, 1, 255 /* clks - 1 (0..255) */ ++CK_MAX tXS, tRFC + 1 + NS_TO_CK(10), 5, 1, 255 /* clks - 1 (0..255) tRFC + 10 */ ++CK_MAX tXP, 3, NS_TO_CK(6), 1, 7 /* clks - 1 (0..7) */ /* max(6ns, 3*CK) */ ++CK_MAX tXPDLL, NS_TO_CK(24), 2, 1, 15 /* clks - 1 (0..15) */ ++NS_VAL tFAW, 45, 1, 31 /* clks - 1 (0..31) */ ++CK_VAL tCL, 8, 3, 8 /* clks - 3 (0..8) CAS Latency */ ++ ++/* MDCFG1 0x10 */ ++NS_VAL tRCD, 14, 1, 7 /* clks - 1 (0..7) */ ++NS_VAL tRP, 14, 1, 7 /* clks - 1 (0..7) */ ++NS_VAL tRC, 50, 1, 31 /* clks - 1 (0..31) */ ++NS_VAL tRAS, 36, 1, 31 /* clks - 1 (0..31) */ ++CK_VAL tRPA, 0, 0, 1 /* clks (0..1) */ ++NS_VAL tWR, 15, 1, 15 /* clks - 1 (0..15) */ ++CK_VAL tMRD, 4, 1, 15 /* clks - 1 (0..15) */ ++CK_VAL tCWL, 6, 2, 6 /* clks - 2 (0..6) */ ++ ++/* MDCFG2 0x14 */ ++CK_VAL tDLLK, 512, 1, 511 /* clks - 1 (0..511) */ ++CK_MAX tRTP, 4, NS_TO_CK(8), 1, 7 /* clks - 1 (0..7) */ ++CK_MAX tWTR, 4, NS_TO_CK(8), 1, 7 /* clks - 1 (0..7) */ ++CK_MAX tRRD, 4, NS_TO_CK(8), 1, 7 /* clks - 1 (0..7) */ ++ ++/* MDOR 0x30 */ ++CK_MAX tXPR, NS_TO_CK(CK_TO_NS(tRFC + 1) + 10), 5, 1, 255 /* clks - 1 (0..255) max(tRFC + 10, 5CK) */ ++#define tSDE_RST (DIV_ROUND_UP(200000, MDOR_CLK_PERIOD_ns) + 2) ++#define tRST_CKE (DIV_ROUND_UP(500000, MDOR_CLK_PERIOD_ns) + 2) ++ ++/* MDOTC 0x08 */ ++NS_VAL tAOFPD, 9, 1, 7 /* clks - 1 (0..7) */ ++NS_VAL tAONPD, 9, 1, 7 /* clks - 1 (0..7) */ ++CK_VAL tANPD, tCWL + 1, 1, 15 /* clks - 1 (0..15) */ ++CK_VAL tAXPD, tCWL + 1, 1, 15 /* clks - 1 (0..15) */ ++CK_VAL tODTLon tCWL, 1, 7 /* clks - 1 (0..7) */ ++CK_VAL tODTLoff tCWL, 1, 31 /* clks - 1 (0..31) */ ++ ++/* MDPDC 0x04 */ ++CK_MAX tCKE, NS_TO_CK(6), 3, 1, 7 ++CK_MAX tCKSRX, NS_TO_CK(10), 5, 0, 7 ++CK_MAX tCKSRE, NS_TO_CK(10), 5, 0, 7 ++ ++#define PRCT 0 ++#define PWDT 5 ++#define SLOW_PD 0 ++#define BOTH_CS_PD 1 ++ ++#define MDPDC_VAL_0 ( \ ++ (PRCT << 28) | \ ++ (PRCT << 24) | \ ++ (tCKE << 16) | \ ++ (SLOW_PD << 7) | \ ++ (BOTH_CS_PD << 6) | \ ++ (tCKSRX << 3) | \ ++ (tCKSRE << 0) \ ++ ) ++ ++#define MDPDC_VAL_1 (MDPDC_VAL_0 | \ ++ (PWDT << 12) | \ ++ (PWDT << 8) \ ++ ) ++ ++#define ROW_ADDR_BITS 14 ++#define COL_ADDR_BITS 10 ++ ++ .iflt tWR - 7 ++ .set mr0_val, ((1 << 8) /* DLL Reset */ | \ ++ ((tWR + 1 - 4) << 9) | \ ++ (((tCL + 3) - 4) << 4)) ++ .else ++ .set mr0_val, ((1 << 8) /* DLL Reset */ | \ ++ (((tWR + 1) / 2) << 9) | \ ++ (((tCL + 3) - 4) << 4)) ++ .endif ++#define MDSCR_MRS_VAL(cs, mr, val) (((val) << 16) | \ ++ (1 << 15) /* CON REQ */ | \ ++ (3 << 4) /* MRS command */ | \ ++ ((cs) << 3) | \ ++ ((mr) << 0)) ++ ++#define mr1_val 0x0040 ++#define mr2_val 0x0408 ++ ++#define MDCFG0_VAL ( \ ++ (tRFC << 24) | \ ++ (tXS << 16) | \ ++ (tXP << 13) | \ ++ (tXPDLL << 9) | \ ++ (tFAW << 4) | \ ++ (tCL << 0)) \ ++ ++#define MDCFG1_VAL ( \ ++ (tRCD << 29) | \ ++ (tRP << 26) | \ ++ (tRC << 21) | \ ++ (tRAS << 16) | \ ++ (tRPA << 15) | \ ++ (tWR << 9) | \ ++ (tMRD << 5) | \ ++ (tCWL << 0)) \ ++ ++#define MDCFG2_VAL ( \ ++ (tDLLK << 16) | \ ++ (tRTP << 6) | \ ++ (tWTR << 3) | \ ++ (tRRD << 0)) ++ ++#define BURST_LEN (SDRAM_BURST_LENGTH / 8) /* 0: 4 byte 1: 8 byte */ ++#define MDCTL_VAL (((ROW_ADDR_BITS - 11) << 24) | \ ++ ((COL_ADDR_BITS - 9) << 20) | \ ++ (BURST_LEN << 19) | \ ++ (2 << 16) | /* SDRAM bus width */ \ ++ ((-1) << (32 - BANK_ADDR_BITS))) ++ ++#define MDMISC_VAL ((ADDR_MIRROR << 19) | \ ++ (WALAT << 16) | \ ++ (BI_ON << 12) | \ ++ (0x3 << 9) | \ ++ (RALAT << 6) | \ ++ (DDR_TYPE << 3)) ++ ++#define MDOR_VAL ((tXPR << 16) | (tSDE_RST << 8) | (tRST_CKE << 0)) ++ ++#define MDOTC_VAL ((tAOFPD << 27) | \ ++ (tAONPD << 24) | \ ++ (tANPD << 20) | \ ++ (tAXPD << 16) | \ ++ (tODTLon << 12) | \ ++ (tODTLoff << 4)) ++ ++fcb_start: ++ b _start ++ .org 0x400 ++ivt_header: ++ .word CPU_2_BE_32((0xd1 << 24) | (32 << 8) | 0x40) ++app_start_addr: ++ .long _start ++ .long 0x0 ++dcd_ptr: ++ .long dcd_hdr ++boot_data_ptr: ++ .word boot_data ++self_ptr: ++ .word ivt_header ++app_code_csf: ++ .word 0x0 ++ .word 0x0 ++boot_data: ++ .long fcb_start ++image_len: ++ .long CONFIG_U_BOOT_IMG_SIZE ++plugin: ++ .word 0 ++ivt_end: ++#define DCD_VERSION 0x40 ++ ++#define CLKCTL_CCGR0 0x68 ++#define CLKCTL_CCGR1 0x6c ++#define CLKCTL_CCGR2 0x70 ++#define CLKCTL_CCGR3 0x74 ++#define CLKCTL_CCGR4 0x78 ++#define CLKCTL_CCGR5 0x7c ++#define CLKCTL_CCGR6 0x80 ++#define CLKCTL_CCGR7 0x84 ++#define CLKCTL_CMEOR 0x88 ++ ++#define DDR_SEL_VAL 3 ++#define DSE_VAL 6 ++#define ODT_VAL 2 ++ ++#define DDR_SEL_SHIFT 18 ++#define DDR_MODE_SHIFT 17 ++#define ODT_SHIFT 8 ++#define DSE_SHIFT 3 ++#define HYS_SHIFT 16 ++#define PKE_SHIFT 12 ++#define PUE_SHIFT 13 ++#define PUS_SHIFT 14 ++ ++#define DDR_SEL_MASK (DDR_SEL_VAL << DDR_SEL_SHIFT) ++#define DDR_MODE_MASK (1 << DDR_MODE_SHIFT) ++#define DSE_MASK (DSE_VAL << DSE_SHIFT) ++#define ODT_MASK (ODT_VAL << ODT_SHIFT) ++ ++#define DQM_MASK (DDR_MODE_MASK | DSE_MASK) ++#define SDQS_MASK DSE_MASK ++#define SDODT_MASK (DSE_MASK | (1 << PKE_SHIFT) | (1 << PUE_SHIFT) | (0 << PUS_SHIFT)) ++#define SDCLK_MASK (DDR_MODE_MASK | DSE_MASK) ++#define SDCKE_MASK ((1 << PKE_SHIFT) | (1 << PUE_SHIFT) | (0 << PUS_SHIFT)) ++#define DDR_ADDR_MASK 0 ++#define DDR_CTRL_MASK (DDR_MODE_MASK | DSE_MASK) ++ ++dcd_hdr: ++ .word CPU_2_BE_32((0xd2 << 24) | ((dcd_end - .) << 8) | DCD_VERSION) ++dcd_start: ++ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, ddr_reset) ++ /* RESET_OUT GPIO_7_12 */ ++ MXC_DCD_ITEM(0x020e024c, 0x00000005) ++ ++ MXC_DCD_ITEM(0x020c402c, 0x01e436c1) /* CSC2CDR default: 0x007236c1 */ ++ MXC_DCD_ITEM(0x020c80e0, 0x00002001) /* ENET PLL */ ++ ++ /* enable all relevant clocks... */ ++ MXC_DCD_ITEM(0x020c4068, 0xf0c03f3f) /* default: 0xf0c03f0f APBH-DMA */ ++ MXC_DCD_ITEM(0x020c406c, 0xf0fc0c00) /* default: 0xf0fc0000 */ ++ MXC_DCD_ITEM(0x020c4070, 0xfc3ff0cc) /* default: 0xfc3ff00c I2C1 */ ++ MXC_DCD_ITEM(0x020c4074, 0x3ff00000) /* default: 0x3ff00000 */ ++ MXC_DCD_ITEM(0x020c4078, 0xff00ff00) /* default: 0x0000ff00 GPMI BCH */ ++ MXC_DCD_ITEM(0x020c407c, 0xff033f0f) /* default: 0xf0033f0f UART1 */ ++ MXC_DCD_ITEM(0x020c4080, 0xffff03ff) /* default: 0xffff0003 USDHC4 (for APBH-DMA!) USDHC3 (for BCH!) */ ++ ++ /* IOMUX: */ ++ MXC_DCD_ITEM(0x020e0004, 0x48640005) /* default: 0x48400005 ENET_CLK output */ ++ /* UART1 pad config */ ++ MXC_DCD_ITEM(0x020e02a8, 0x00000001) /* UART1 TXD */ ++ MXC_DCD_ITEM(0x020e02ac, 0x00000001) /* UART1 RXD */ ++ MXC_DCD_ITEM(0x020e0920, 0x00000003) /* UART1 RXD INPUT_SEL */ ++ MXC_DCD_ITEM(0x020e02c0, 0x00000001) /* UART1 CTS */ ++ MXC_DCD_ITEM(0x020e02c4, 0x00000001) /* UART1 RTS */ ++ MXC_DCD_ITEM(0x020e091c, 0x00000003) /* UART1 RTS INPUT_SEL */ ++#if 0 ++ /* NAND */ ++ MXC_DCD_ITEM(0x020e02d4, 0x00000000) /* NANDF_CLE: NANDF_CLE */ ++ MXC_DCD_ITEM(0x020e02d8, 0x00000000) /* NANDF_ALE: NANDF_ALE */ ++ MXC_DCD_ITEM(0x020e02dc, 0x00000000) /* NANDF_WP_B: NANDF_WPn */ ++ MXC_DCD_ITEM(0x020e02e0, 0x00000000) /* NANDF_RB0: NANDF_READY0 */ ++ MXC_DCD_ITEM(0x020e02e4, 0x00000000) /* NANDF_CS0: NANDF_CS0 */ ++ MXC_DCD_ITEM(0x020e02f4, 0x00000001) /* SD4_CMD: NANDF_RDn */ ++ MXC_DCD_ITEM(0x020e02f8, 0x00000001) /* SD4_CLK: NANDF_WRn */ ++ MXC_DCD_ITEM(0x020e02fc, 0x00000000) /* NANDF_D0: NANDF_D0 */ ++ MXC_DCD_ITEM(0x020e0300, 0x00000000) /* NANDF_D1: NANDF_D1 */ ++ MXC_DCD_ITEM(0x020e0304, 0x00000000) /* NANDF_D2: NANDF_D2 */ ++ MXC_DCD_ITEM(0x020e0308, 0x00000000) /* NANDF_D3: NANDF_D3 */ ++ MXC_DCD_ITEM(0x020e030c, 0x00000000) /* NANDF_D4: NANDF_D4 */ ++ MXC_DCD_ITEM(0x020e0310, 0x00000000) /* NANDF_D5: NANDF_D5 */ ++ MXC_DCD_ITEM(0x020e0314, 0x00000000) /* NANDF_D6: NANDF_D6 */ ++ MXC_DCD_ITEM(0x020e0318, 0x00000000) /* NANDF_D7: NANDF_D7 */ ++#endif ++ /* ext. mem CS */ ++ MXC_DCD_ITEM(0x020e02ec, 0x00000000) /* NANDF_CS2: NANDF_CS2 */ ++ /* DRAM_DQM[0..7] */ ++ MXC_DCD_ITEM(0x020e05ac, DQM_MASK) ++ MXC_DCD_ITEM(0x020e05b4, DQM_MASK) ++ MXC_DCD_ITEM(0x020e0528, DQM_MASK) ++ MXC_DCD_ITEM(0x020e0520, DQM_MASK) ++ MXC_DCD_ITEM(0x020e0514, DQM_MASK) ++ MXC_DCD_ITEM(0x020e0510, DQM_MASK) ++ MXC_DCD_ITEM(0x020e05bc, DQM_MASK) ++ MXC_DCD_ITEM(0x020e05c4, DQM_MASK) ++ /* DRAM_A[0..15] */ ++ MXC_DCD_ITEM(0x020e052c, DDR_ADDR_MASK) ++ MXC_DCD_ITEM(0x020e0530, DDR_ADDR_MASK) ++ MXC_DCD_ITEM(0x020e0534, DDR_ADDR_MASK) ++ MXC_DCD_ITEM(0x020e0538, DDR_ADDR_MASK) ++ MXC_DCD_ITEM(0x020e053c, DDR_ADDR_MASK) ++ MXC_DCD_ITEM(0x020e0540, DDR_ADDR_MASK) ++ MXC_DCD_ITEM(0x020e0544, DDR_ADDR_MASK) ++ MXC_DCD_ITEM(0x020e0548, DDR_ADDR_MASK) ++ MXC_DCD_ITEM(0x020e054c, DDR_ADDR_MASK) ++ MXC_DCD_ITEM(0x020e0550, DDR_ADDR_MASK) ++ MXC_DCD_ITEM(0x020e0554, DDR_ADDR_MASK) ++ MXC_DCD_ITEM(0x020e0558, DDR_ADDR_MASK) ++ MXC_DCD_ITEM(0x020e055c, DDR_ADDR_MASK) ++ MXC_DCD_ITEM(0x020e0560, DDR_ADDR_MASK) ++ MXC_DCD_ITEM(0x020e0564, DDR_ADDR_MASK) ++ MXC_DCD_ITEM(0x020e0568, DDR_ADDR_MASK) ++ /* DRAM_CAS */ ++ MXC_DCD_ITEM(0x020e056c, DDR_CTRL_MASK) ++ /* DRAM_RAS */ ++ MXC_DCD_ITEM(0x020e0578, DDR_CTRL_MASK) ++ /* DRAM_SDCLK[0..1] */ ++ MXC_DCD_ITEM(0x020e0588, SDCLK_MASK) ++ MXC_DCD_ITEM(0x020e0594, SDCLK_MASK) ++ /* DRAM_RESET */ ++ MXC_DCD_ITEM(0x020e057c, DDR_CTRL_MASK) ++ /* DRAM_SDCKE[0..1] */ ++ MXC_DCD_ITEM(0x020e0590, SDCKE_MASK) ++ MXC_DCD_ITEM(0x020e0598, SDCKE_MASK) ++ /* DRAM_SDBA[0..2] */ ++ MXC_DCD_ITEM(0x020e0580, 0x00000000) ++ MXC_DCD_ITEM(0x020e0584, 0x00000000) ++ MXC_DCD_ITEM(0x020e058c, 0x00000000) ++ /* DRAM_SDODT[0..1] */ ++ MXC_DCD_ITEM(0x020e059c, SDODT_MASK) ++ MXC_DCD_ITEM(0x020e05a0, SDODT_MASK) ++ /* DRAM_B[0..7]DS */ ++ MXC_DCD_ITEM(0x020e0784, DSE_MASK) ++ MXC_DCD_ITEM(0x020e0788, DSE_MASK) ++ MXC_DCD_ITEM(0x020e0794, DSE_MASK) ++ MXC_DCD_ITEM(0x020e079c, DSE_MASK) ++ MXC_DCD_ITEM(0x020e07a0, DSE_MASK) ++ MXC_DCD_ITEM(0x020e07a4, DSE_MASK) ++ MXC_DCD_ITEM(0x020e07a8, DSE_MASK) ++ MXC_DCD_ITEM(0x020e0748, DSE_MASK) ++ /* ADDDS */ ++ MXC_DCD_ITEM(0x020e074c, DSE_MASK) ++ /* DDRMODE_CTL */ ++ MXC_DCD_ITEM(0x020e0750, DDR_MODE_MASK) ++ /* DDRPKE */ ++ MXC_DCD_ITEM(0x020e0758, 0x00000000) ++ /* DDRMODE */ ++ MXC_DCD_ITEM(0x020e0774, DDR_MODE_MASK) ++ /* CTLDS */ ++ MXC_DCD_ITEM(0x020e078c, DSE_MASK) ++ /* DDR_TYPE */ ++ MXC_DCD_ITEM(0x020e0798, DDR_SEL_MASK) ++ /* DDRPK */ ++ MXC_DCD_ITEM(0x020e0768, 1 << PUE_SHIFT) ++ /* DDRHYS */ ++ MXC_DCD_ITEM(0x020e0770, 0x00000000) ++ /* TERM_CTL[0..7] */ ++ MXC_DCD_ITEM(0x020e0754, ODT_MASK) ++ MXC_DCD_ITEM(0x020e075c, ODT_MASK) ++ MXC_DCD_ITEM(0x020e0760, ODT_MASK) ++ MXC_DCD_ITEM(0x020e0764, ODT_MASK) ++ MXC_DCD_ITEM(0x020e076c, ODT_MASK) ++ MXC_DCD_ITEM(0x020e0778, ODT_MASK) ++ MXC_DCD_ITEM(0x020e077c, ODT_MASK) ++ MXC_DCD_ITEM(0x020e0780, ODT_MASK) ++ ++ /* SDRAM initialization */ ++ /* MPRDDQBY[0..7]DL */ ++ MXC_DCD_ITEM(0x021b081c, 0x33333333) ++ MXC_DCD_ITEM(0x021b481c, 0x33333333) ++ MXC_DCD_ITEM(0x021b0820, 0x33333333) ++ MXC_DCD_ITEM(0x021b4820, 0x33333333) ++ MXC_DCD_ITEM(0x021b0824, 0x33333333) ++ MXC_DCD_ITEM(0x021b4824, 0x33333333) ++ MXC_DCD_ITEM(0x021b0828, 0x33333333) ++ MXC_DCD_ITEM(0x021b4828, 0x33333333) ++ /* MDMISC */ ++ MXC_DCD_ITEM(0x021b0018, MDMISC_VAL | 2) /* reset MMDC FSM */ ++ddr_reset: ++ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b0018, 0x00000002) ++ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, con_ack) ++ ++ /* MSDSCR Conf Req */ ++ MXC_DCD_ITEM(0x021b001c, 0x00008000) ++con_ack: ++ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_SET, 0x021b001c, 0x00004000) ++ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, ddr_calib) ++ /* MDCTL */ ++ MXC_DCD_ITEM(0x021b0000, MDCTL_VAL) ++ddr_calib: ++ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_SET, 0x021b0018, 0x40000000) ++ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, zq_calib) ++ ++ MXC_DCD_ITEM(0x021b000c, MDCFG0_VAL) ++ MXC_DCD_ITEM(0x021b0010, MDCFG1_VAL) ++ MXC_DCD_ITEM(0x021b0014, MDCFG2_VAL) ++ MXC_DCD_ITEM(0x021b002c, 0x000026d2) /* MDRWD */ ++ MXC_DCD_ITEM(0x021b0030, MDOR_VAL) ++ MXC_DCD_ITEM(0x021b0008, MDOTC_VAL) ++ MXC_DCD_ITEM(0x021b0004, MDPDC_VAL_0) ++ MXC_DCD_ITEM(0x021b0040, 0x00000027) /* MDASP */ ++ ++ /* CS0 MRS: */ ++ MXC_DCD_ITEM(0x021b001c, MDSCR_MRS_VAL(0, 0, mr0_val)) ++ MXC_DCD_ITEM(0x021b001c, MDSCR_MRS_VAL(0, 1, mr1_val)) ++ MXC_DCD_ITEM(0x021b001c, MDSCR_MRS_VAL(0, 2, mr2_val)) ++ MXC_DCD_ITEM(0x021b001c, MDSCR_MRS_VAL(0, 3, 0)) ++#if BANK_ADDR_BITS > 1 ++ /* CS1 MRS: MR2 */ ++ MXC_DCD_ITEM(0x021b001c, MDSCR_MRS_VAL(1, 0, mr0_val)) ++ MXC_DCD_ITEM(0x021b001c, MDSCR_MRS_VAL(1, 1, mr1_val)) ++ MXC_DCD_ITEM(0x021b001c, MDSCR_MRS_VAL(1, 2, mr2_val)) ++ MXC_DCD_ITEM(0x021b001c, MDSCR_MRS_VAL(1, 3, 4)) /* MRS: select MPR */ ++#endif ++ MXC_DCD_ITEM(0x021b0020, 0x0000c000) /* disable refresh */ ++ ++ MXC_DCD_ITEM(0x021b0818, 0x00011112) /* MPODTCTRL */ ++ MXC_DCD_ITEM(0x021b4818, 0x00011112) ++ ++ /* DDR3 calibration */ ++ MXC_DCD_ITEM(0x021b0890, 0x00000003) /* select default compare pattern for DQ calibration */ ++ MXC_DCD_ITEM(0x021b0404, 0x00011007) ++ ++ /* ZQ calibration */ ++ MXC_DCD_ITEM(0x021b001c, 0x04008010) /* precharge all */ ++ MXC_DCD_ITEM(0x021b001c, 0x04008040) /* MRS: ZQ calibration */ ++ ++ MXC_DCD_ITEM(0x021b4800, 0xa138002b) ++ MXC_DCD_ITEM(0x021b0800, 0xa139002b) ++zq_calib: ++ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b0800, 0x00010000) ++ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, wl_calib) ++ ++ /* Write leveling */ ++ MXC_DCD_ITEM(0x021b4800, 0xa1380000) ++ MXC_DCD_ITEM(0x021b0800, 0xa1380000) ++ ++ MXC_DCD_ITEM(0x021b001c, MDSCR_MRS_VAL(0, 3, 4)) /* MRS: select MPR */ ++ MXC_DCD_ITEM(0x021b001c, 0x00808231) /* MRS: start write leveling */ ++ ++ MXC_DCD_ITEM(0x021b0808, 0x00000001) /* initiate Write leveling */ ++wl_calib: ++ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b0808, 0x00000001) ++ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b0808, 0x00000f00) ++ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b4808, 0x00000001) ++ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b4808, 0x00000f00) ++ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, dqs_fifo_reset) ++ ++ MXC_DCD_ITEM(0x021b0800, 0xa138002b) ++ MXC_DCD_ITEM(0x021b4800, 0xa138002b) ++ ++ MXC_DCD_ITEM(0x021b001c, MDSCR_MRS_VAL(0, 1, mr1_val)) /* MRS: end write leveling */ ++ ++ /* DQS gating calibration */ ++ MXC_DCD_ITEM(0x020e05a8, SDQS_MASK | 0x7000) /* enable Pullups on DQS pads */ ++ MXC_DCD_ITEM(0x020e05b0, SDQS_MASK | 0x7000) ++ MXC_DCD_ITEM(0x020e0524, SDQS_MASK | 0x7000) ++ MXC_DCD_ITEM(0x020e051c, SDQS_MASK | 0x7000) ++ MXC_DCD_ITEM(0x020e0518, SDQS_MASK | 0x7000) ++ MXC_DCD_ITEM(0x020e050c, SDQS_MASK | 0x7000) ++ MXC_DCD_ITEM(0x020e05b8, SDQS_MASK | 0x7000) ++ MXC_DCD_ITEM(0x020e05c0, SDQS_MASK | 0x7000) ++ MXC_DCD_ITEM(0x021b0018, MDMISC_VAL | (7 << 6) | (3 << 16)) /* RALAT/WALAT max. */ ++ ++ MXC_DCD_ITEM(0x021b001c, 0x00008020) /* issue one refresh cycle */ ++ MXC_DCD_ITEM(0x021b001c, 0x04008050) /* precharge all to bank 0 */ ++ ++ MXC_DCD_ITEM(0x021b0848, 0x40404040) /* DQ RD Delay default values */ ++ MXC_DCD_ITEM(0x021b4848, 0x40404040) ++ MXC_DCD_ITEM(0x021b0850, 0x40404040) /* DQ WR Delay default values */ ++ MXC_DCD_ITEM(0x021b4850, 0x40404040) ++ MXC_DCD_ITEM(0x021b48b8, 0x00000800) ++ MXC_DCD_ITEM(0x021b08b8, 0x00000800) ++ ++ MXC_DCD_ITEM(0x021b083c, 0x80000000) /* issue fifo reset */ ++dqs_fifo_reset: ++ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b083c, 0x80000000) ++ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, dqs_fifo_reset2) ++ MXC_DCD_ITEM(0x021b083c, 0x80000000) /* issue 2nd fifo reset */ ++dqs_fifo_reset2: ++ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b083c, 0x80000000) ++ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, dqs_calib) ++ MXC_DCD_ITEM(0x021b083c, 0x50800000) /* choose 32 wait cycles and start DQS calib. */ ++dqs_calib: ++ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b083c, 0x10000000) ++ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b083c, 0x00001000) ++ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b483c, 0x10000000) ++ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b483c, 0x00001000) ++ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, rd_dl_fifo_reset1) ++ ++ /* DRAM_SDQS[0..7] pad config */ ++ MXC_DCD_ITEM(0x020e05a8, SDQS_MASK) ++ MXC_DCD_ITEM(0x020e05b0, SDQS_MASK) ++ MXC_DCD_ITEM(0x020e0524, SDQS_MASK) ++ MXC_DCD_ITEM(0x020e051c, SDQS_MASK) ++ MXC_DCD_ITEM(0x020e0518, SDQS_MASK) ++ MXC_DCD_ITEM(0x020e050c, SDQS_MASK) ++ MXC_DCD_ITEM(0x020e05b8, SDQS_MASK) ++ MXC_DCD_ITEM(0x020e05c0, SDQS_MASK) ++ ++ MXC_DCD_ITEM(0x021b0018, MDMISC_VAL) ++rd_dl_fifo_reset1: ++ /* Read delay calibration */ ++ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_SET, rd_dl_fifo_reset2) ++ MXC_DCD_ITEM(0x021b083c, 0x80000000) /* issue fifo reset */ ++rd_dl_fifo_reset2: ++ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b083c, 0x80000000) ++ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_SET, rd_dl_fifo_reset3) ++ MXC_DCD_ITEM(0x021b083c, 0x80000000) /* issue 2nd fifo reset */ ++rd_dl_fifo_reset3: ++ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b083c, 0x80000000) ++ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, rd_dl_calib) ++ ++ MXC_DCD_ITEM(0x021b001c, 0x04008050) /* precharge all to bank 0 */ ++ MXC_DCD_ITEM(0x021b0860, 0x00000030) /* MPRDDLHWCTL: HW_RD_DL_EN */ ++rd_dl_calib: ++ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b0860, 0x00000010) ++ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b4860, 0x00000010) ++ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b0860, 0x0000000f) ++ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b4860, 0x0000000f) ++ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, wr_dl_calib) ++ ++ /* Write Delay calibration */ ++ MXC_DCD_ITEM(0x021b001c, 0x04008050) /* precharge all to bank 0 */ ++ MXC_DCD_ITEM(0x021b0864, 0x00000030) /* start WR DL calibration */ ++wr_dl_calib: ++ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b0864, 0x00000010) ++ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b4864, 0x00000010) ++ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b0864, 0x0000000f) ++ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b4864, 0x0000000f) ++ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, con_ack_clr) ++ ++ MXC_DCD_ITEM(0x021b001c, MDSCR_MRS_VAL(0, 3, 0)) /* MRS: select normal data path */ ++ MXC_DCD_ITEM(0x021b0020, 0x00005800) /* MDREF */ ++ MXC_DCD_ITEM(0x021b0404, 0x00011006) /* MAPSR */ ++ MXC_DCD_ITEM(0x021b0004, MDPDC_VAL_1) ++ ++ /* MDSCR: Normal operation */ ++ MXC_DCD_ITEM(0x021b001c, 0x00000000) ++con_ack_clr: ++ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b001c, 0x00004000) ++dcd_end: ++ .ifgt dcd_end - dcd_start - 1768 ++ DCD too large! ++ .endif ++dcd_size: ++ .word (1768 - (dcd_end - dcd_start)) / (3 * 4) diff --cc board/karo/tx6q/lowlevel_init.S.rotten index 0000000000,0000000000..f6a2d6cf6c new file mode 100644 --- /dev/null +++ b/board/karo/tx6q/lowlevel_init.S.rotten @@@ -1,0 -1,0 +1,610 @@@ ++#include ++#include ++#include ++ ++#define DEBUG_LED_BIT 20 ++#define LED_GPIO_BASE GPIO2_BASE_ADDR ++#define LED_MUX_OFFSET 0x0ec ++#define LED_MUX_MODE 0x15 ++ ++#define SDRAM_CLK CONFIG_SYS_SDRAM_CLK ++ ++#ifdef PHYS_SDRAM_2_SIZE ++#define SDRAM_SIZE (PHYS_SDRAM_1_SIZE + PHYS_SDRAM_2_SIZE) ++#else ++#define SDRAM_SIZE PHYS_SDRAM_1_SIZE ++#endif ++ ++#if 1 ++#define CPU_2_BE_32(l) \ ++ ((((l) << 24) & 0xFF000000) | \ ++ (((l) << 8) & 0x00FF0000) | \ ++ (((l) >> 8) & 0x0000FF00) | \ ++ (((l) >> 24) & 0x000000FF)) ++#else ++#define CPU_2_BE_32(l) (l) ++#endif ++ ++#define MXC_DCD_ITEM(addr, val) .word CPU_2_BE_32(addr), CPU_2_BE_32(val) ++ ++#define CHECK_DCD_ADDR(a) ((((a) >= 0x00907000) && ((a) <= 0x00937FF0)) || \ ++ (((a) >= 0x020C4000) && ((a) < 0x020C8000)) || \ ++ (((a) >= 0x020C8000) && ((a) < 0x020C9000)) || \ ++ (((a) >= 0x020E0000) && ((a) < 0x020E4000)) || \ ++ (((a) >= 0x021B0000) && ((a) < 0x021B8000)) || \ ++ (((a) >= 0x08000000) && ((a) < 0x0FFF0000)) || \ ++ (((a) >= 0x10000000))) ++ ++#define MXC_DCD_CMD_SZ_BYTE 1 ++#define MXC_DCD_CMD_SZ_SHORT 2 ++#define MXC_DCD_CMD_SZ_WORD 4 ++#define MXC_DCD_CMD_FLAG_WRITE 0x0 ++#define MXC_DCD_CMD_FLAG_CLR 0x1 ++#define MXC_DCD_CMD_FLAG_SET 0x3 ++#define MXC_DCD_CMD_FLAG_CHK_ANY (1 << 0) ++#define MXC_DCD_CMD_FLAG_CHK_SET (1 << 1) ++#define MXC_DCD_CMD_FLAG_CHK_CLR (0 << 1) ++ ++#define MXC_DCD_CMD_WRT(type, flags, next) \ ++ .word CPU_2_BE_32((0xcc << 24) | (((next) - .) << 8) | ((flags) << 3) | (type)) ++ ++#define MXC_DCD_CMD_CHK(type, flags, addr, mask) \ ++ .word CPU_2_BE_32((0xcf << 24) | (12 << 8) | ((flags) << 3) | (type)),\ ++ CPU_2_BE_32(addr), CPU_2_BE_32(mask) ++ ++#define MXC_DCD_CMD_CHK_CNT(type, flags, addr, mask, count) \ ++ .word CPU_2_BE_32((0xcf << 24) | (16 << 8) | ((flags) << 3) | (type)),\ ++ CPU_2_BE_32(addr), CPU_2_BE_32(mask), CPU_2_BE_32(count) ++ ++#define MXC_DCD_CMD_NOP \ ++ .word CPU_2_BE_32((0xc0 << 24) | (4 << 8)) ++ ++#define CK_TO_NS(ck) (((ck) * 1000 + SDRAM_CLK / 2) / SDRAM_CLK) ++#define NS_TO_CK(ns) (((ns) * SDRAM_CLK + 999) / 1000) ++ ++ .macro CK_VAL, name, clks, offs, max ++ .iflt \clks - \offs ++ .set \name, 0 ++ .else ++ .ifle \clks - \offs - \max ++ .set \name, \clks - \offs ++ .endif ++ .endif ++ .endm ++ ++ .macro NS_VAL, name, ns, offs, max ++ .iflt \ns - \offs ++ .set \name, 0 ++ .else ++ CK_VAL \name, NS_TO_CK(\ns), \offs, \max ++ .endif ++ .endm ++ ++ .macro CK_MAX, name, ck1, ck2, offs, max ++ .ifgt \ck1 - \ck2 ++ CK_VAL \name, \ck1, \offs, \max ++ .else ++ CK_VAL \name, \ck2, \offs, \max ++ .endif ++ .endm ++ ++#define MDMISC_DDR_TYPE_DDR3 0 ++#define MDMISC_DDR_TYPE_LPDDR2 1 ++#define MDMISC_DDR_TYPE_DDR2 2 ++ ++#define DIV_ROUND_UP(m,d) (((m) + (d) - 1) / (d)) ++ ++#define MDOR_CLK_PERIOD_ns 15258 /* base clock for MDOR values */ ++ ++/* DDR3 SDRAM */ ++#if SDRAM_SIZE > PHYS_SDRAM_1_SIZE ++#define BANK_ADDR_BITS 2 ++#else ++#define BANK_ADDR_BITS 1 ++#endif ++#define SDRAM_BURST_LENGTH 8 ++#define RALAT 5 ++#define WALAT 0 ++#define BI_ON 1 ++#define ADDR_MIRROR 1 ++#define DDR_TYPE MDMISC_DDR_TYPE_DDR3 ++ ++/* 512/1024MiB SDRAM: NT5CB128M16P-CG */ ++/* MDCFG0 0x0c */ ++NS_VAL tRFC, 160, 1, 255 /* clks - 1 (0..255) */ ++CK_MAX tXS, tRFC + 1 + NS_TO_CK(10), 5, 1, 255 /* clks - 1 (0..255) tRFC + 10 */ ++CK_MAX tXP, 3, NS_TO_CK(6), 1, 7 /* clks - 1 (0..7) */ /* max(6ns, 3*CK) */ ++CK_MAX tXPDLL, NS_TO_CK(24), 2, 1, 15 /* clks - 1 (0..15) */ ++NS_VAL tFAW, 45, 1, 31 /* clks - 1 (0..31) */ ++CK_VAL tCL, 8, 3, 8 /* clks - 3 (0..8) CAS Latency */ ++ ++/* MDCFG1 0x10 */ ++NS_VAL tRCD, 14, 1, 7 /* clks - 1 (0..7) */ ++NS_VAL tRP, 14, 1, 7 /* clks - 1 (0..7) */ ++NS_VAL tRC, 50, 1, 31 /* clks - 1 (0..31) */ ++NS_VAL tRAS, 36, 1, 31 /* clks - 1 (0..31) */ ++CK_VAL tRPA, 0, 0, 1 /* clks (0..1) */ ++NS_VAL tWR, 15, 1, 15 /* clks - 1 (0..15) */ ++CK_VAL tMRD, 4, 1, 15 /* clks - 1 (0..15) */ ++CK_VAL tCWL, 6, 2, 6 /* clks - 2 (0..6) */ ++ ++/* MDCFG2 0x14 */ ++CK_VAL tDLLK, 512, 1, 511 /* clks - 1 (0..511) */ ++CK_MAX tRTP, 4, NS_TO_CK(8), 1, 7 /* clks - 1 (0..7) */ ++CK_MAX tWTR, 4, NS_TO_CK(8), 1, 7 /* clks - 1 (0..7) */ ++CK_MAX tRRD, 4, NS_TO_CK(8), 1, 7 /* clks - 1 (0..7) */ ++ ++/* MDOR 0x30 */ ++CK_MAX tXPR, NS_TO_CK(CK_TO_NS(tRFC + 1) + 10), 5, 1, 255 /* clks - 1 (0..255) max(tRFC + 10, 5CK) */ ++#define tSDE_RST (DIV_ROUND_UP(200000, MDOR_CLK_PERIOD_ns) + 2) ++#define tRST_CKE (DIV_ROUND_UP(500000, MDOR_CLK_PERIOD_ns) + 2) ++ ++/* MDOTC 0x08 */ ++NS_VAL tAOFPD, 9, 1, 7 /* clks - 1 (0..7) */ ++NS_VAL tAONPD, 9, 1, 7 /* clks - 1 (0..7) */ ++CK_VAL tANPD, tCWL + 1, 1, 15 /* clks - 1 (0..15) */ ++CK_VAL tAXPD, tCWL + 1, 1, 15 /* clks - 1 (0..15) */ ++CK_VAL tODTLon tCWL, 1, 7 /* clks - 1 (0..7) */ ++CK_VAL tODTLoff tCWL, 1, 31 /* clks - 1 (0..31) */ ++ ++/* MDPDC 0x04 */ ++CK_MAX tCKE, NS_TO_CK(6), 3, 1, 7 ++CK_MAX tCKSRX, NS_TO_CK(10), 5, 0, 7 ++CK_MAX tCKSRE, NS_TO_CK(10), 5, 0, 7 ++ ++#define PRCT 0 ++#define PWDT 5 ++#define SLOW_PD 0 ++#define BOTH_CS_PD 1 ++ ++#define MDPDC_VAL_0 ( \ ++ (tCKE << 16) | \ ++ (tCKSRX << 3) | \ ++ (tCKSRE << 0) \ ++ ) ++ ++#define MDPDC_VAL_1 (MDPDC_VAL_0 | \ ++ (PRCT << 28) | \ ++ (PRCT << 24) | \ ++ (PWDT << 12) | \ ++ (PWDT << 8) | \ ++ (BOTH_CS_PD << 6) | \ ++ (SLOW_PD << 7) \ ++ ) ++ ++#define ROW_ADDR_BITS 14 ++#define COL_ADDR_BITS 10 ++ ++ .iflt tWR - 7 ++ .set mrs_val, ((1 << 15) /* CON REQ */ | \ ++ (3 << 4) /* MRS command */ | \ ++ ((1 << 8) /* DLL Reset */ | \ ++ ((tWR + 1 - 4) << 9) | \ ++ (((tCL + 3) - 4) << 4)) << 16) ++ .else ++ .set mrs_val, ((1 << 15) /* CON REQ */ | \ ++ (3 << 4) /* MRS command */ | \ ++ ((1 << 8) /* DLL Reset */ | \ ++ (((tWR + 1) / 2) << 9) | \ ++ (((tCL + 3) - 4) << 4)) << 16) ++ .endif ++#define MDSCR_MRS_VAL(cs) (mrs_val | ((cs) << 3)) ++ ++#define MDCFG0_VAL ( \ ++ (tRFC << 24) | \ ++ (tXS << 16) | \ ++ (tXP << 13) | \ ++ (tXPDLL << 9) | \ ++ (tFAW << 4) | \ ++ (tCL << 0)) \ ++ ++#define MDCFG1_VAL ( \ ++ (tRCD << 29) | \ ++ (tRP << 26) | \ ++ (tRC << 21) | \ ++ (tRAS << 16) | \ ++ (tRPA << 15) | \ ++ (tWR << 9) | \ ++ (tMRD << 5) | \ ++ (tCWL << 0)) \ ++ ++#define MDCFG2_VAL ( \ ++ (tDLLK << 16) | \ ++ (tRTP << 6) | \ ++ (tWTR << 3) | \ ++ (tRRD << 0)) ++ ++#define BURST_LEN (SDRAM_BURST_LENGTH / 8) /* 0: 4 byte 1: 8 byte */ ++#define MDCTL_VAL (((ROW_ADDR_BITS - 11) << 24) | \ ++ ((COL_ADDR_BITS - 9) << 20) | \ ++ (BURST_LEN << 19) | \ ++ (2 << 16) | /* SDRAM bus width */ \ ++ ((-1) << (32 - BANK_ADDR_BITS))) ++ ++#define MDMISC_VAL ((ADDR_MIRROR << 19) | \ ++ (WALAT << 16) | \ ++ (BI_ON << 12) | \ ++ (0x3 << 9) | \ ++ (RALAT << 6) | \ ++ (DDR_TYPE << 3)) ++ ++#define MDOR_VAL ((tXPR << 16) | (tSDE_RST << 8) | (tRST_CKE << 0)) ++ ++#define MDOTC_VAL ((tAOFPD << 27) | \ ++ (tAONPD << 24) | \ ++ (tANPD << 20) | \ ++ (tAXPD << 16) | \ ++ (tODTLon << 12) | \ ++ (tODTLoff << 4)) ++ ++fcb_start: ++ b _start ++ .org 0x400 ++ivt_header: ++ .word CPU_2_BE_32((0xd1 << 24) | (32 << 8) | 0x40) ++app_start_addr: ++ .long _start ++ .long 0x0 ++dcd_ptr: ++ .long dcd_hdr ++boot_data_ptr: ++ .word boot_data ++self_ptr: ++ .word ivt_header ++app_code_csf: ++ .word 0x0 ++ .word 0x0 ++boot_data: ++ .long fcb_start ++image_len: ++ .long CONFIG_U_BOOT_IMG_SIZE ++plugin: ++ .word 0 ++ivt_end: ++#define DCD_VERSION 0x40 ++ ++#define CLKCTL_CCGR0 0x68 ++#define CLKCTL_CCGR1 0x6c ++#define CLKCTL_CCGR2 0x70 ++#define CLKCTL_CCGR3 0x74 ++#define CLKCTL_CCGR4 0x78 ++#define CLKCTL_CCGR5 0x7c ++#define CLKCTL_CCGR6 0x80 ++#define CLKCTL_CCGR7 0x84 ++#define CLKCTL_CMEOR 0x88 ++ ++#define DDR_SEL_VAL 3 ++#define DSE_VAL 6 ++#define ODT_VAL 2 ++ ++#define DDR_SEL_SHIFT 18 ++#define DDR_MODE_SHIFT 17 ++#define ODT_SHIFT 8 ++#define DSE_SHIFT 3 ++#define HYS_SHIFT 16 ++#define PKE_SHIFT 12 ++#define PUE_SHIFT 13 ++#define PUS_SHIFT 14 ++ ++#define DDR_SEL_MASK (DDR_SEL_VAL << DDR_SEL_SHIFT) ++#define DDR_MODE_MASK (1 << DDR_MODE_SHIFT) ++#define DSE_MASK (DSE_VAL << DSE_SHIFT) ++#define ODT_MASK (ODT_VAL << ODT_SHIFT) ++ ++#define DQM_MASK (DDR_MODE_MASK | DSE_MASK) ++#define SDQS_MASK DSE_MASK ++#define SDODT_MASK (DSE_MASK | (0 << PKE_SHIFT) | (1 << PUE_SHIFT) | (0 << PUS_SHIFT)) ++#define SDCLK_MASK (DDR_MODE_MASK | DSE_MASK) ++#define SDCKE_MASK ((1 << PKE_SHIFT) | (1 << PUE_SHIFT) | (0 << PUS_SHIFT)) ++#define DDR_ADDR_MASK DDR_MODE_MASK ++#define DDR_CTRL_MASK (DDR_MODE_MASK | DSE_MASK) ++ ++dcd_hdr: ++ .word CPU_2_BE_32((0xd2 << 24) | ((dcd_end - .) << 8) | DCD_VERSION) ++dcd_start: ++ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, con_ack) ++ /* RESET_OUT GPIO_7_12 */ ++ MXC_DCD_ITEM(0x020e024c, 0x00000005) ++#if 0 ++ /* STK5 LED GPIO */ ++ MXC_DCD_ITEM(0x020e00ec, (1 << 20)) ++#endif ++ MXC_DCD_ITEM(0x020c402c, 0x01e436c1) /* CSC2CDR default: 0x007236c1 */ ++ MXC_DCD_ITEM(0x020c80e0, 0x00002001) /* ENET PLL */ ++ ++ /* enable all relevant clocks... */ ++ MXC_DCD_ITEM(0x020c4068, 0xf0c03f3f) /* default: 0xf0c03f0f APBH-DMA */ ++ MXC_DCD_ITEM(0x020c406c, 0xf0fc0c00) /* default: 0xf0fc0000 */ ++ MXC_DCD_ITEM(0x020c4070, 0xfc3ff0cc) /* default: 0xfc3ff00c I2C1 */ ++ MXC_DCD_ITEM(0x020c4074, 0x3ff00000) /* default: 0x3ff00000 */ ++ MXC_DCD_ITEM(0x020c4078, 0xff00ff00) /* default: 0x0000ff00 GPMI BCH */ ++ MXC_DCD_ITEM(0x020c407c, 0xff033f0f) /* default: 0xf0033f0f UART1 */ ++ MXC_DCD_ITEM(0x020c4080, 0xffff03ff) /* default: 0xffff0003 USDHC4 (for APBH-DMA!) USDHC3 (for BCH!) */ ++ ++ /* IOMUX: */ ++ MXC_DCD_ITEM(0x020e0004, 0x48640005) /* default: 0x48400005 ENET_CLK output */ ++ /* UART1 pad config */ ++ MXC_DCD_ITEM(0x020e02a8, 0x00000001) /* UART1 TXD */ ++ MXC_DCD_ITEM(0x020e02ac, 0x00000001) /* UART1 RXD */ ++ MXC_DCD_ITEM(0x020e0920, 0x00000003) /* UART1 RXD INPUT_SEL */ ++ MXC_DCD_ITEM(0x020e02c0, 0x00000001) /* UART1 CTS */ ++ MXC_DCD_ITEM(0x020e02c4, 0x00000001) /* UART1 RTS */ ++ MXC_DCD_ITEM(0x020e091c, 0x00000003) /* UART1 RTS INPUT_SEL */ ++ /* NAND */ ++ MXC_DCD_ITEM(0x020e02d4, 0x00000000) /* NANDF_CLE: NANDF_CLE */ ++ MXC_DCD_ITEM(0x020e02d8, 0x00000000) /* NANDF_ALE: NANDF_ALE */ ++ MXC_DCD_ITEM(0x020e02dc, 0x00000000) /* NANDF_WP_B: NANDF_WPn */ ++ MXC_DCD_ITEM(0x020e02e0, 0x00000000) /* NANDF_RB0: NANDF_READY0 */ ++ MXC_DCD_ITEM(0x020e02e4, 0x00000000) /* NANDF_CS0: NANDF_CS0 */ ++ MXC_DCD_ITEM(0x020e02f4, 0x00000001) /* SD4_CMD: NANDF_RDn */ ++ MXC_DCD_ITEM(0x020e02f8, 0x00000001) /* SD4_CLK: NANDF_WRn */ ++ MXC_DCD_ITEM(0x020e02fc, 0x00000000) /* NANDF_D0: NANDF_D0 */ ++ MXC_DCD_ITEM(0x020e0300, 0x00000000) /* NANDF_D1: NANDF_D1 */ ++ MXC_DCD_ITEM(0x020e0304, 0x00000000) /* NANDF_D2: NANDF_D2 */ ++ MXC_DCD_ITEM(0x020e0308, 0x00000000) /* NANDF_D3: NANDF_D3 */ ++ MXC_DCD_ITEM(0x020e030c, 0x00000000) /* NANDF_D4: NANDF_D4 */ ++ MXC_DCD_ITEM(0x020e0310, 0x00000000) /* NANDF_D5: NANDF_D5 */ ++ MXC_DCD_ITEM(0x020e0314, 0x00000000) /* NANDF_D6: NANDF_D6 */ ++ MXC_DCD_ITEM(0x020e0318, 0x00000000) /* NANDF_D7: NANDF_D7 */ ++ /* ext. mem CS */ ++ MXC_DCD_ITEM(0x020e02ec, 0x00000000) /* NANDF_CS2: NANDF_CS2 */ ++ /* DRAM_SDQS[0..7] */ ++ MXC_DCD_ITEM(0x020e05a8, SDQS_MASK) ++ MXC_DCD_ITEM(0x020e05b0, SDQS_MASK) ++ MXC_DCD_ITEM(0x020e0524, SDQS_MASK) ++ MXC_DCD_ITEM(0x020e051c, SDQS_MASK) ++ MXC_DCD_ITEM(0x020e0518, SDQS_MASK) ++ MXC_DCD_ITEM(0x020e050c, SDQS_MASK) ++ MXC_DCD_ITEM(0x020e05b8, SDQS_MASK) ++ MXC_DCD_ITEM(0x020e05c0, SDQS_MASK) ++ /* DRAM_DQM[0..7] */ ++ MXC_DCD_ITEM(0x020e05ac, DQM_MASK) ++ MXC_DCD_ITEM(0x020e05b4, DQM_MASK) ++ MXC_DCD_ITEM(0x020e0528, DQM_MASK) ++ MXC_DCD_ITEM(0x020e0520, DQM_MASK) ++ MXC_DCD_ITEM(0x020e0514, DQM_MASK) ++ MXC_DCD_ITEM(0x020e0510, DQM_MASK) ++ MXC_DCD_ITEM(0x020e05bc, DQM_MASK) ++ MXC_DCD_ITEM(0x020e05c4, DQM_MASK) ++ /* DRAM_A[0..15] */ ++ MXC_DCD_ITEM(0x020e052c, DDR_ADDR_MASK) ++ MXC_DCD_ITEM(0x020e0530, DDR_ADDR_MASK) ++ MXC_DCD_ITEM(0x020e0534, DDR_ADDR_MASK) ++ MXC_DCD_ITEM(0x020e0538, DDR_ADDR_MASK) ++ MXC_DCD_ITEM(0x020e053c, DDR_ADDR_MASK) ++ MXC_DCD_ITEM(0x020e0540, DDR_ADDR_MASK) ++ MXC_DCD_ITEM(0x020e0544, DDR_ADDR_MASK) ++ MXC_DCD_ITEM(0x020e0548, DDR_ADDR_MASK) ++ MXC_DCD_ITEM(0x020e054c, DDR_ADDR_MASK) ++ MXC_DCD_ITEM(0x020e0550, DDR_ADDR_MASK) ++ MXC_DCD_ITEM(0x020e0554, DDR_ADDR_MASK) ++ MXC_DCD_ITEM(0x020e0558, DDR_ADDR_MASK) ++ MXC_DCD_ITEM(0x020e055c, DDR_ADDR_MASK) ++ MXC_DCD_ITEM(0x020e0560, DDR_ADDR_MASK) ++ MXC_DCD_ITEM(0x020e0564, DDR_ADDR_MASK) ++ MXC_DCD_ITEM(0x020e0568, DDR_ADDR_MASK) ++ /* DRAM_CAS */ ++ MXC_DCD_ITEM(0x020e056c, DDR_CTRL_MASK) ++ /* DRAM_RAS */ ++ MXC_DCD_ITEM(0x020e0578, DDR_CTRL_MASK) ++ /* DRAM_SDCLK[0..1] */ ++ MXC_DCD_ITEM(0x020e0588, SDCLK_MASK) ++ MXC_DCD_ITEM(0x020e0594, SDCLK_MASK) ++ /* DRAM_RESET */ ++ MXC_DCD_ITEM(0x020e057c, DDR_CTRL_MASK) ++ /* DRAM_SDCKE[0..1] */ ++ MXC_DCD_ITEM(0x020e0590, SDCKE_MASK) ++ MXC_DCD_ITEM(0x020e0598, SDCKE_MASK) ++ /* DRAM_SDBA[0..2] */ ++ MXC_DCD_ITEM(0x020e0580, 0x00000000) ++ MXC_DCD_ITEM(0x020e0584, 0x00000000) ++ MXC_DCD_ITEM(0x020e058c, 0x00000000) ++ /* DRAM_SDODT[0..1] */ ++ MXC_DCD_ITEM(0x020e059c, SDODT_MASK) ++ MXC_DCD_ITEM(0x020e05a0, SDODT_MASK) ++ /* DRAM_B[0..7]DS */ ++ MXC_DCD_ITEM(0x020e0784, DSE_MASK) ++ MXC_DCD_ITEM(0x020e0788, DSE_MASK) ++ MXC_DCD_ITEM(0x020e0794, DSE_MASK) ++ MXC_DCD_ITEM(0x020e079c, DSE_MASK) ++ MXC_DCD_ITEM(0x020e07a0, DSE_MASK) ++ MXC_DCD_ITEM(0x020e07a4, DSE_MASK) ++ MXC_DCD_ITEM(0x020e07a8, DSE_MASK) ++ MXC_DCD_ITEM(0x020e0748, DSE_MASK) ++ /* ADDDS */ ++ MXC_DCD_ITEM(0x020e074c, DSE_MASK) ++ /* DDRMODE_CTL */ ++ MXC_DCD_ITEM(0x020e0750, DDR_MODE_MASK) ++ /* DDRPKE */ ++ MXC_DCD_ITEM(0x020e0758, 0x00000000) ++ /* DDRMODE */ ++ MXC_DCD_ITEM(0x020e0774, DDR_MODE_MASK) ++ /* CTLDS */ ++ MXC_DCD_ITEM(0x020e078c, DSE_MASK) ++ /* DDR_TYPE */ ++ MXC_DCD_ITEM(0x020e0798, DDR_SEL_MASK) ++ /* DDRPK */ ++ MXC_DCD_ITEM(0x020e0768, 1 << PUE_SHIFT) ++ /* DDRHYS */ ++ MXC_DCD_ITEM(0x020e0770, 0x00000000) ++ /* TERM_CTL[0..7] */ ++#if 0 ++ MXC_DCD_ITEM(0x020e0754, ODT_MASK) ++ MXC_DCD_ITEM(0x020e075c, ODT_MASK) ++ MXC_DCD_ITEM(0x020e0760, ODT_MASK) ++ MXC_DCD_ITEM(0x020e0764, ODT_MASK) ++ MXC_DCD_ITEM(0x020e076c, ODT_MASK) ++ MXC_DCD_ITEM(0x020e0778, ODT_MASK) ++ MXC_DCD_ITEM(0x020e077c, ODT_MASK) ++ MXC_DCD_ITEM(0x020e0780, ODT_MASK) ++#endif ++ /* SDRAM initialization */ ++#if 1 ++ /* MPRDDQBY[0..7]DL */ ++ MXC_DCD_ITEM(0x021b081c, 0x33333333) ++ MXC_DCD_ITEM(0x021b481c, 0x33333333) ++ MXC_DCD_ITEM(0x021b0820, 0x33333333) ++ MXC_DCD_ITEM(0x021b4820, 0x33333333) ++ MXC_DCD_ITEM(0x021b0824, 0x33333333) ++ MXC_DCD_ITEM(0x021b4824, 0x33333333) ++ MXC_DCD_ITEM(0x021b0828, 0x33333333) ++ MXC_DCD_ITEM(0x021b4828, 0x33333333) ++#endif ++MDMISC: /* MDMISC */ ++ MXC_DCD_ITEM(0x021b0018, MDMISC_VAL) ;@ 0x00081740 ++MSDSCR: /* MSDSCR Conf Req */ ++ MXC_DCD_ITEM(0x021b001c, 0x00008000) ++con_ack: ++ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_SET, 0x021b001c, 0x00004000) ++ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, zq_calib) ++MDCFG0: /* MDCFG0 */ ++ MXC_DCD_ITEM(0x021b000c, MDCFG0_VAL) ;@ 0x555a7975 ++MDCFG1: /* MDCFG1 */ ++ MXC_DCD_ITEM(0x021b0010, MDCFG1_VAL) ;@ 0xff538e64 ++MDCFG2: /* MDCFG2 */ ++ MXC_DCD_ITEM(0x021b0014, MDCFG2_VAL) ;@ 0x01ff00db ++MDRWD: /* MDRWD */ ++ MXC_DCD_ITEM(0x021b002c, 0x000026d2) ++MDOR: /* MDOR */ ++ MXC_DCD_ITEM(0x021b0030, MDOR_VAL) ;@ 0x005b0e21 ++MDOTC: /* MDOTC */ ++ MXC_DCD_ITEM(0x021b0008, MDOTC_VAL) ;@ 0x09444040 ++MDPDC: /* MDPDC */ ++ MXC_DCD_ITEM(0x021b0004, MDPDC_VAL_1) ;@ 0x00025576 ++ MXC_DCD_ITEM(0x021b0004, MDPDC_VAL_0) ;@ 0x00025576 ++MDASP: /* MDASP */ ++ MXC_DCD_ITEM(0x021b0040, 0x00000027) ++MDCTL: /* MDCTL */ ++ MXC_DCD_ITEM(0x021b0000, MDCTL_VAL);@ 0x831a0000 ++ddr_calib: ++ /* CS0 MRS: */ ++MR2: /* MR2 */ ++ MXC_DCD_ITEM(0x021b001c, 0x04088032) ++MR3: /* MR3 */ ++ MXC_DCD_ITEM(0x021b001c, 0x00008033) ++MR1: /* MR1 */ ++ MXC_DCD_ITEM(0x021b001c, 0x00048031) ++MR0: /* MR0 */ ++ MXC_DCD_ITEM(0x021b001c, MDSCR_MRS_VAL(0)) ;@ 0x09408030 ++#if BANK_ADDR_BITS > 1 ++ /* CS1 MRS: MR2 */ ++ MXC_DCD_ITEM(0x021b001c, 0x0408803a) ++ MXC_DCD_ITEM(0x021b001c, 0x0000803b) ++ MXC_DCD_ITEM(0x021b001c, 0x00408039) ++ MXC_DCD_ITEM(0x021b001c, MDSCR_MRS_VAL(1)) ;@ 0x09408038 ++#endif ++MDREF: /* MDREF */ ++ MXC_DCD_ITEM(0x021b0020, 0x00005800) ++MPODTCTRL: /* MPODTCTRL */ ++#if 0 ++ MXC_DCD_ITEM(0x021b0818, 0x00011112) ;@ 0x00000007 ++ MXC_DCD_ITEM(0x021b4818, 0x00011112) ;@ 0x00000007 ++#else ++ MXC_DCD_ITEM(0x021b0818, 0x00000007) ++ MXC_DCD_ITEM(0x021b4818, 0x00000007) ++#endif ++ MXC_DCD_ITEM(0x021b0890, 0x00000003) /* select default compare pattern for DQ calibration */ ++ ++ /* ZQ calibration */ ++ MXC_DCD_ITEM(0x021b001c, 0x04008010) /* precharge all */ ++ MXC_DCD_ITEM(0x021b001c, 0x00008040) /* MRS: ZQ calibration */ ++ ++ MXC_DCD_ITEM(0x021b0800, 0xa1390003) ++zq_calib: ++ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b0800, 0x00010000) ++#if 1 ++ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, wl_calib) ++ MXC_DCD_ITEM(0x021b001c, 0x00048033) /* MRS: select MPR */ ++ MXC_DCD_ITEM(0x021b001c, 0x00c08231) /* MRS: start write leveling */ ++ ++ MXC_DCD_ITEM(0x021b001c, 0x00000000) ++ MXC_DCD_ITEM(0x021b0808, 0x00000001) /* initiate Write leveling */ ++ MXC_DCD_ITEM(0x021b4808, 0x00000001) ++wl_calib: ++ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b0808, 0x00000001) ++ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b0808, 0x00f00000) ++ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b4808, 0x00000001) ++ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b4808, 0x00f00000) ++#endif ++ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, dqs_calib) ++ MXC_DCD_ITEM(0x021b001c, 0x00048031) /* MRS: end write leveling */ ++ MXC_DCD_ITEM(0x021b001c, 0x00008033) /* MRS: select normal data path */ ++ ++ /* DQS gating calibration */ ++ MXC_DCD_ITEM(0x021b0018, MDMISC_VAL | (3 << 16) | (3 << 9)) ;@ 0x00081740 ++#if 1 ++ MXC_DCD_ITEM(0x021b001c, 0x04008010) /* precharge all */ ++ MXC_DCD_ITEM(0x021b001c, 0x00048033) /* MRS: select MPR */ ++#if 1 ++ MXC_DCD_ITEM(0x021b0848, 0x47424140) /* DQ Delay default values */ ++ MXC_DCD_ITEM(0x021b4848, 0x41414047) ++#endif ++ MXC_DCD_ITEM(0x021b083c, 0x90000000) /* reset RD fifo and start DQS calib. */ ++ MXC_DCD_ITEM(0x021b483c, 0x90000000) ++dqs_calib: ++ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b083c, 0x90000000) ++ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b483c, 0x90000000) ++#endif ++ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, rd_dl_calib) ++ MXC_DCD_ITEM(0x021b001c, 0x00008033) /* MRS: select normal data path */ ++ ++ MXC_DCD_ITEM(0x021b001c, 0x00000000) ++ MXC_DCD_ITEM(0x021b0018, MDMISC_VAL) ;@ 0x00081740 ++ ++ /* Read delay calibration */ ++ MXC_DCD_ITEM(0x021b001c, 0x04008010) /* precharge all */ ++ MXC_DCD_ITEM(0x021b001c, 0x00048033) /* MRS: select MPR */ ++#define DO_CALIB ++#ifdef DO_CALIB ++ MXC_DCD_ITEM(0x021b0860, 0x00000010) /* MPRDDLHWCTL: HW_RD_DL_EN */ ++ MXC_DCD_ITEM(0x021b4860, 0x00000010) ++#endif ++rd_dl_calib: ++ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b0860, 0x00000010) ++ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b4860, 0x00000010) ++ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, wr_dl_calib) ++ MXC_DCD_ITEM(0x021b001c, 0x00008033) /* MRS: select normal data path */ ++ ++ /* Write Delay calibration */ ++ MXC_DCD_ITEM(0x021b001c, 0x04008010) /* precharge all */ ++ MXC_DCD_ITEM(0x021b001c, 0x00048033) /* MRS: select MPR */ ++#ifdef DO_CALIB ++ MXC_DCD_ITEM(0x021b0864, 0x00000010) ++ MXC_DCD_ITEM(0x021b4864, 0x00000010) ++#endif ++wr_dl_calib: ++ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b0864, 0x00000010) ++ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b4864, 0x00000010) ++ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, dcd_end) ++ MXC_DCD_ITEM(0x021b001c, 0x00008033) /* MRS: select normal data path */ ++ ++ /* MDSCR: Normal operation */ ++ MXC_DCD_ITEM(0x021b001c, 0x00000000) ++#if 0 ++ MXC_DCD_ITEM(0x021b0868, 0x00000000) ++ MXC_DCD_ITEM(0x021b086c, 0x00000000) ++ MXC_DCD_ITEM(0x021b4868, 0x00000000) ++ MXC_DCD_ITEM(0x021b486c, 0x00000000) ++@ MXC_DCD_ITEM(0x021b0844, 0x1f251f21) ++ MXC_DCD_ITEM(0x021b0898, 0x4ffa481a) ++ MXC_DCD_ITEM(0x021b089c, 0x4ffa481a) ++ MXC_DCD_ITEM(0x021b4898, 0x4ffa481a) ++ MXC_DCD_ITEM(0x021b489c, 0x4ffa481a) ++#endif ++MAPSR: /* MAPSR */ ++ MXC_DCD_ITEM(0x021b0404, 0x00011006) ++ MXC_DCD_ITEM(0x021b0004, MDPDC_VAL_1) ;@ 0x00025576 ++#if 1 ++ MXC_DCD_ITEM(0x021b083c, 0x034b0350) /* DG_DL_ABS_OFFS[0..1] */ ++ MXC_DCD_ITEM(0x021b483c, 0x034b0350) ++ MXC_DCD_ITEM(0x021b0840, 0x034c0359) /* DG_DL_ABS_OFFS[2..3] */ ++ MXC_DCD_ITEM(0x021b4840, 0x03650348) ++#endif ++#if 0 ++bogus_ram_access: ++ MXC_DCD_ITEM(0x12345678, 0x12345678) ++#endif ++dcd_end: ++ .ifgt dcd_end - dcd_start - 1768 ++ DCD too large! ++ .endif diff --cc board/karo/tx6q/mmdc_regs.h index 0000000000,0000000000..fb26c92b14 new file mode 100644 --- /dev/null +++ b/board/karo/tx6q/mmdc_regs.h @@@ -1,0 -1,0 +1,79 @@@ ++#define MMDC_MDCTL 0x0000 ++#define MMDC_MDPDC 0x0004 ++#define MMDC_MDOTC 0x0008 ++#define MMDC_MDCFG0 0x000C ++#define MMDC_MDCFG1 0x0010 ++#define MMDC_MDCFG2 0x0014 ++#define MMDC_MDMISC 0x0018 ++#define MMDC_MDSCR 0x001C ++#define MMDC_MDREF 0x0020 ++#define MMDC_MDRWD 0x002C ++#define MMDC_MDOR 0x0030 ++#define MMDC_MDMRR 0x0034 ++#define MMDC_MDCFG3LP 0x0038 ++#define MMDC_MDMR4 0x003C ++#define MMDC_MDASP 0x0040 ++#define MMDC_MAARCR 0x0400 ++#define MMDC_MAPSR 0x0404 ++#define MMDC_MAEXIDR0 0x0408 ++#define MMDC_MAEXIDR1 0x040C ++#define MMDC_MADPCR0 0x0410 ++#define MMDC_MADPCR1 0x0414 ++#define MMDC_MADPSR0 0x0418 ++#define MMDC_MADPSR1 0x041C ++#define MMDC_MADPSR2 0x0420 ++#define MMDC_MADPSR3 0x0424 ++#define MMDC_MADPSR4 0x0428 ++#define MMDC_MADPSR5 0x042C ++#define MMDC_MASBS0 0x0430 ++#define MMDC_MASBS1 0x0434 ++#define MMDC_MAGENP 0x0440 ++#define MMDC_MPZQHWCTRL 0x0800 ++#define MMDC_MPZQSWCTRL 0x0804 ++#define MMDC_MPWLGCR 0x0808 ++#define MMDC_MPWLDECTRL0 0x080C ++#define MMDC_MPWLDECTRL1 0x0810 ++#define MMDC_MPWLDLST 0x0814 ++#define MMDC_MPODTCTRL 0x0818 ++#define MMDC_MPRDDQBY0DL 0x081C ++#define MMDC_MPRDDQBY1DL 0x0820 ++#define MMDC_MPRDDQBY2DL 0x0824 ++#define MMDC_MPRDDQBY3DL 0x0828 ++#define MMDC_MPWRDQBY0DL 0x082C ++#define MMDC_MPWRDQBY1DL 0x0830 ++#define MMDC_MPWRDQBY2DL 0x0834 ++#define MMDC_MPWRDQBY3DL 0x0838 ++#define MMDC_MPDGCTRL0 0x083C ++#define MMDC_MPDGCTRL1 0x0840 ++#define MMDC_MPDGDLST0 0x0844 ++#define MMDC_MPRDDLCTL 0x0848 ++#define MMDC_MPRDDLST 0x084C ++#define MMDC_MPWRDLCTL 0x0850 ++#define MMDC_MPWRDLST 0x0854 ++#define MMDC_MPSDCTRL 0x0858 ++#define MMDC_MPZQLP2CTL 0x085C ++#define MMDC_MPRDDLHWCTL 0x0860 ++#define MMDC_MPWRDLHWCTL 0x0864 ++#define MMDC_MPRDDLHWST0 0x0868 ++#define MMDC_MPRDDLHWST1 0x086C ++#define MMDC_MPWRDLHWST0 0x0870 ++#define MMDC_MPWRDLHWST1 0x0874 ++#define MMDC_MPWLHWERR 0x0878 ++#define MMDC_MPDGHWST0 0x087C ++#define MMDC_MPDGHWST1 0x0880 ++#define MMDC_MPDGHWST2 0x0884 ++#define MMDC_MPDGHWST3 0x0888 ++#define MMDC_MPPDCMPR1 0x088C ++#define MMDC_MPPDCMPR2 0x0890 ++#define MMDC_MPSWDAR0 0x0894 ++#define MMDC_MPSWDRDR0 0x0898 ++#define MMDC_MPSWDRDR1 0x089C ++#define MMDC_MPSWDRDR2 0x08A0 ++#define MMDC_MPSWDRDR3 0x08A4 ++#define MMDC_MPSWDRDR4 0x08A8 ++#define MMDC_MPSWDRDR5 0x08AC ++#define MMDC_MPSWDRDR6 0x08B0 ++#define MMDC_MPSWDRDR7 0x08B4 ++#define MMDC_MPMUR0 0x08B8 ++#define MMDC_MPWRCADL 0x08BC ++#define MMDC_MPDCCR 0x08C0 diff --cc board/karo/tx6q/spl_boot.c index 0000000000,0000000000..1dc02531b1 new file mode 100644 --- /dev/null +++ b/board/karo/tx6q/spl_boot.c @@@ -1,0 -1,0 +1,216 @@@ ++/* ++ * Copyright (C) 2011 Lothar Waßmann ++ * based on: board/freesclae/mx28_evk.c (C) 2010 Freescale Semiconductor, Inc. ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define MUX_CONFIG_LED MX6_PAD_CTL_DSE_80ohm ++#define MUX_CONFIG_LCD (MX6_PAD_CTL_SPEED_HIGH | MX6_PAD_CTL_SRE_FAST | \ ++ MX6_PAD_CTL_DSE_80ohm) ++#define MUX_CONFIG_TSC (MX6_PAD_CTL_SRE_FAST | MX6_PAD_CTL_DSE_80ohm | \ ++ MX6_PAD_CTL_PUS_47K_UP) ++#define MUX_CONFIG_GPMI MX6_PAD_CTL_DSE_80ohm ++#define MUX_CONFIG_EMI MX6Q_HIGH_DRV ++#define MUX_CONFIG_GPIO MX6_PAD_CTL_PUS_47K_UP ++ ++static iomux_v3_cfg_t tx6q_stk5_pads[] = { ++ /* LED */ ++ MX6Q_PAD_EIM_A18__GPIO_2_20, ++ ++ /* framebuffer */ ++ MX6Q_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0, ++ MX6Q_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1, ++ MX6Q_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2, ++ MX6Q_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3, ++ MX6Q_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4, ++ MX6Q_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5, ++ MX6Q_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6, ++ MX6Q_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7, ++ MX6Q_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8, ++ MX6Q_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9, ++ MX6Q_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10, ++ MX6Q_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11, ++ MX6Q_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12, ++ MX6Q_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13, ++ MX6Q_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14, ++ MX6Q_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15, ++ MX6Q_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16, ++ MX6Q_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17, ++ MX6Q_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18, ++ MX6Q_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19, ++ MX6Q_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20, ++ MX6Q_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21, ++ MX6Q_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22, ++ MX6Q_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23, ++ MX6Q_PAD_DI0_PIN3__IPU1_DI0_PIN3, /* LCD VSYNC */ ++ MX6Q_PAD_DI0_PIN2__IPU1_DI0_PIN2, /* LCD HSYNC */ ++ MX6Q_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK, /* LCD DOTCLK */ ++ MX6Q_PAD_DI0_PIN15__IPU1_DI0_PIN15, /* LCD OE/ACD */ ++ ++ /* UART1 pads */ ++ MX6Q_PAD_SD3_DAT7__UART1_TXD, ++ MX6Q_PAD_SD3_DAT6__UART1_RXD, ++ MX6Q_PAD_SD3_DAT1__UART1_RTS, ++ MX6Q_PAD_SD3_DAT0__UART1_CTS, ++ ++ /* EMI */ ++ MX6_PAD_EMI_D00__EMI_DATA0, ++ MX6_PAD_EMI_D01__EMI_DATA1, ++ MX6_PAD_EMI_D02__EMI_DATA2, ++ MX6_PAD_EMI_D03__EMI_DATA3, ++ MX6_PAD_EMI_D04__EMI_DATA4, ++ MX6_PAD_EMI_D05__EMI_DATA5, ++ MX6_PAD_EMI_D06__EMI_DATA6, ++ MX6_PAD_EMI_D07__EMI_DATA7, ++ MX6_PAD_EMI_D08__EMI_DATA8, ++ MX6_PAD_EMI_D09__EMI_DATA9, ++ MX6_PAD_EMI_D10__EMI_DATA10, ++ MX6_PAD_EMI_D11__EMI_DATA11, ++ MX6_PAD_EMI_D12__EMI_DATA12, ++ MX6_PAD_EMI_D13__EMI_DATA13, ++ MX6_PAD_EMI_D14__EMI_DATA14, ++ MX6_PAD_EMI_D15__EMI_DATA15, ++ MX6_PAD_EMI_ODT0__EMI_ODT0, ++ MX6_PAD_EMI_DQM0__EMI_DQM0, ++ MX6_PAD_EMI_ODT1__EMI_ODT1, ++ MX6_PAD_EMI_DQM1__EMI_DQM1, ++ MX6_PAD_EMI_DDR_OPEN_FB__EMI_DDR_OPEN_FEEDBACK, ++ MX6_PAD_EMI_CLK__EMI_CLK, ++ MX6_PAD_EMI_DQS0__EMI_DQS0, ++ MX6_PAD_EMI_DQS1__EMI_DQS1, ++ MX6_PAD_EMI_DDR_OPEN__EMI_DDR_OPEN, ++ ++ MX6_PAD_EMI_A00__EMI_ADDR0, ++ MX6_PAD_EMI_A01__EMI_ADDR1, ++ MX6_PAD_EMI_A02__EMI_ADDR2, ++ MX6_PAD_EMI_A03__EMI_ADDR3, ++ MX6_PAD_EMI_A04__EMI_ADDR4, ++ MX6_PAD_EMI_A05__EMI_ADDR5, ++ MX6_PAD_EMI_A06__EMI_ADDR6, ++ MX6_PAD_EMI_A07__EMI_ADDR7, ++ MX6_PAD_EMI_A08__EMI_ADDR8, ++ MX6_PAD_EMI_A09__EMI_ADDR9, ++ MX6_PAD_EMI_A10__EMI_ADDR10, ++ MX6_PAD_EMI_A11__EMI_ADDR11, ++ MX6_PAD_EMI_A12__EMI_ADDR12, ++ MX6_PAD_EMI_A13__EMI_ADDR13, ++ MX6_PAD_EMI_A14__EMI_ADDR14, ++ MX6_PAD_EMI_BA0__EMI_BA0, ++ MX6_PAD_EMI_BA1__EMI_BA1, ++ MX6_PAD_EMI_BA2__EMI_BA2, ++ MX6_PAD_EMI_CASN__EMI_CASN, ++ MX6_PAD_EMI_RASN__EMI_RASN, ++ MX6_PAD_EMI_WEN__EMI_WEN, ++ MX6_PAD_EMI_CE0N__EMI_CE0N, ++ MX6_PAD_EMI_CE1N__EMI_CE1N, ++ MX6_PAD_EMI_CKE__EMI_CKE, ++ ++ /* FEC pads */ ++ MX6_PAD_PWM4__GPIO_3_29, ++ MX6_PAD_ENET0_RX_CLK__GPIO_4_13, ++ MX6_PAD_ENET0_MDC__ENET0_MDC, ++ MX6_PAD_ENET0_MDIO__ENET0_MDIO, ++ MX6_PAD_ENET0_RX_EN__GPIO_4_2, /* COL/CRS_DV/MODE2 */ ++ MX6_PAD_ENET0_RXD0__GPIO_4_3, /* RXD0/MODE0 */ ++ MX6_PAD_ENET0_RXD1__GPIO_4_4, /* RXD1/MODE1 */ ++ MX6_PAD_ENET0_TX_CLK__GPIO_4_5, /* nINT/TX_ER/TXD4 */ ++ MX6_PAD_ENET0_TX_EN__ENET0_TX_EN, ++ MX6_PAD_ENET0_TXD0__ENET0_TXD0, ++ MX6_PAD_ENET0_TXD1__ENET0_TXD1, ++ MX6_PAD_ENET_CLK__CLKCTRL_ENET, ++ ++ /* MMC pads */ ++ MX6_PAD_SSP0_DATA0__SSP0_D0, ++ MX6_PAD_SSP0_DATA1__SSP0_D1, ++ MX6_PAD_SSP0_DATA2__SSP0_D2, ++ MX6_PAD_SSP0_DATA3__SSP0_D3, ++ MX6_PAD_SSP0_CMD__SSP0_CMD, ++ MX6_PAD_SSP0_DETECT__SSP0_CARD_DETECT, ++ MX6_PAD_SSP0_SCK__SSP0_SCK, ++ ++ /* GPMI pads */ ++ MX6_PAD_GPMI_D00__GPMI_D0, ++ MX6_PAD_GPMI_D01__GPMI_D1, ++ MX6_PAD_GPMI_D02__GPMI_D2, ++ MX6_PAD_GPMI_D03__GPMI_D3, ++ MX6_PAD_GPMI_D04__GPMI_D4, ++ MX6_PAD_GPMI_D05__GPMI_D5, ++ MX6_PAD_GPMI_D06__GPMI_D6, ++ MX6_PAD_GPMI_D07__GPMI_D7, ++ MX6_PAD_GPMI_CE0N__GPMI_CE0N, ++ MX6_PAD_GPMI_RDY0__GPMI_READY0, ++ MX6_PAD_GPMI_RDN__GPMI_RDN, ++ MX6_PAD_GPMI_WRN__GPMI_WRN, ++ MX6_PAD_GPMI_ALE__GPMI_ALE, ++ MX6_PAD_GPMI_CLE__GPMI_CLE, ++ MX6_PAD_GPMI_RESETN__GPMI_RESETN, ++ ++ /* maybe used for EDT-FT5x06 */ ++ MX6_PAD_SSP0_DATA5__GPIO_2_5, ++ MX6_PAD_SSP0_DATA6__GPIO_2_6, ++ MX6_PAD_ENET0_RXD2__GPIO_4_9, ++ ++ /* unused pads */ ++ MX6_PAD_GPMI_RDY1__GPIO_0_21, ++ MX6_PAD_GPMI_RDY2__GPIO_0_22, ++ MX6_PAD_GPMI_RDY3__GPIO_0_23, ++ MX6_PAD_GPMI_CE1N__GPIO_0_17, ++ MX6_PAD_GPMI_CE2N__GPIO_0_18, ++ MX6_PAD_GPMI_CE3N__GPIO_0_19, ++ ++ MX6_PAD_SSP0_DATA4__GPIO_2_4, ++ MX6_PAD_SSP0_DATA7__GPIO_2_7, ++ ++ MX6_PAD_SSP2_SS0__GPIO_2_19, ++ MX6_PAD_SSP2_SS1__GPIO_2_20, ++ MX6_PAD_SSP2_SS2__GPIO_2_21, ++ MX6_PAD_SSP3_SS0__GPIO_2_27, ++ ++ MX6_PAD_ENET0_TXD2__GPIO_4_11, ++ MX6_PAD_ENET0_TXD3__GPIO_4_12, ++ MX6_PAD_ENET0_CRS__GPIO_4_15, ++}; ++ ++static void tx6q_stk5_lcd_init(void) ++{ ++ gpio_direction_output(MX6_PAD_PWM0__GPIO_3_16, 1); ++ gpio_direction_output(MX6_PAD_LCD_RESET__GPIO_3_30, 0); ++ gpio_direction_output(MX6_PAD_LCD_ENABLE__GPIO_1_31, 0); ++} ++ ++static void tx6q_stk5_led_on(void) ++{ ++ gpio_direction_output(MX6Q_PAD_EIM_A18__GPIO_2_20, 1); ++} ++ ++void board_init_ll(void) ++{ ++ mx6_common_spl_init(tx6q_stk5_pads, ARRAY_SIZE(tx6q_stk5_pads)); ++ tx6q_stk5_lcd_init(); ++ tx6q_stk5_led_on(); ++} diff --cc board/karo/tx6q/tx6q.c index 0000000000,0000000000..b61c62930f new file mode 100644 --- /dev/null +++ b/board/karo/tx6q/tx6q.c @@@ -1,0 -1,0 +1,1094 @@@ ++/* ++ * Copyright (C) 2012 Lothar Waßmann ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++//#define DEBUG ++//#define TIMER_TEST ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "../common/karo.h" ++ ++#define TX6Q_FEC_RST_GPIO IMX_GPIO_NR(7, 6) ++#define TX6Q_FEC_PWR_GPIO IMX_GPIO_NR(3, 20) ++#define TX6Q_FEC_INT_GPIO IMX_GPIO_NR(2, 4) ++#define TX6Q_LED_GPIO IMX_GPIO_NR(2, 20) ++ ++#define TX6Q_LCD_PWR_GPIO IMX_GPIO_NR(2, 31) ++#define TX6Q_LCD_RST_GPIO IMX_GPIO_NR(3, 29) ++#define TX6Q_LCD_BACKLIGHT_GPIO IMX_GPIO_NR(1, 1) ++ ++#define TX6Q_RESET_OUT_GPIO IMX_GPIO_NR(7, 12) ++ ++#define TEMPERATURE_MIN -40 ++#define TEMPERATURE_HOT 80 ++#define TEMPERATURE_MAX 125 ++ ++DECLARE_GLOBAL_DATA_PTR; ++ ++#define MUX_CFG_SION IOMUX_PAD(0, 0, IOMUX_CONFIG_SION, 0, 0, 0) ++ ++static const iomux_v3_cfg_t tx6q_pads[] = { ++ /* NAND flash pads */ ++ MX6Q_PAD_NANDF_CLE__RAWNAND_CLE, ++ MX6Q_PAD_NANDF_ALE__RAWNAND_ALE, ++ MX6Q_PAD_NANDF_WP_B__RAWNAND_RESETN, ++ MX6Q_PAD_NANDF_RB0__RAWNAND_READY0, ++ MX6Q_PAD_NANDF_CS0__RAWNAND_CE0N, ++ MX6Q_PAD_SD4_CMD__RAWNAND_RDN, ++ MX6Q_PAD_SD4_CLK__RAWNAND_WRN, ++ MX6Q_PAD_NANDF_D0__RAWNAND_D0, ++ MX6Q_PAD_NANDF_D1__RAWNAND_D1, ++ MX6Q_PAD_NANDF_D2__RAWNAND_D2, ++ MX6Q_PAD_NANDF_D3__RAWNAND_D3, ++ MX6Q_PAD_NANDF_D4__RAWNAND_D4, ++ MX6Q_PAD_NANDF_D5__RAWNAND_D5, ++ MX6Q_PAD_NANDF_D6__RAWNAND_D6, ++ MX6Q_PAD_NANDF_D7__RAWNAND_D7, ++ ++ /* RESET_OUT */ ++ MX6Q_PAD_GPIO_17__GPIO_7_12, ++ ++ /* UART pads */ ++#if CONFIG_MXC_UART_BASE == UART1_BASE ++ MX6Q_PAD_SD3_DAT7__UART1_TXD, ++ MX6Q_PAD_SD3_DAT6__UART1_RXD, ++ MX6Q_PAD_SD3_DAT1__UART1_RTS, ++ MX6Q_PAD_SD3_DAT0__UART1_CTS, ++#endif ++#if CONFIG_MXC_UART_BASE == UART2_BASE ++ MX6Q_PAD_SD4_DAT4__UART2_RXD, ++ MX6Q_PAD_SD4_DAT7__UART2_TXD, ++ MX6Q_PAD_SD4_DAT5__UART2_RTS, ++ MX6Q_PAD_SD4_DAT6__UART2_CTS, ++#endif ++#if CONFIG_MXC_UART_BASE == UART3_BASE ++ MX6Q_PAD_EIM_D24__UART3_TXD, ++ MX6Q_PAD_EIM_D25__UART3_RXD, ++ MX6Q_PAD_SD3_RST__UART3_RTS, ++ MX6Q_PAD_SD3_DAT3__UART3_CTS, ++#endif ++ /* internal I2C */ ++ MX6Q_PAD_EIM_D28__I2C1_SDA, ++ MX6Q_PAD_EIM_D21__I2C1_SCL, ++ ++ /* FEC PHY GPIO functions */ ++ MX6Q_PAD_EIM_D20__GPIO_3_20 | MUX_CFG_SION, /* PHY POWER */ ++ MX6Q_PAD_SD3_DAT2__GPIO_7_6 | MUX_CFG_SION, /* PHY RESET */ ++ MX6Q_PAD_SD3_DAT4__GPIO_7_1, /* PHY INT */ ++}; ++ ++static const iomux_v3_cfg_t tx6q_fec_pads[] = { ++ /* FEC functions */ ++ MX6Q_PAD_ENET_MDC__ENET_MDC, ++ MX6Q_PAD_ENET_MDIO__ENET_MDIO, ++ MX6Q_PAD_GPIO_16__ENET_ANATOP_ETHERNET_REF_OUT, ++ MX6Q_PAD_ENET_RX_ER__ENET_RX_ER, ++ MX6Q_PAD_ENET_CRS_DV__ENET_RX_EN, ++ MX6Q_PAD_ENET_RXD1__ENET_RDATA_1, ++ MX6Q_PAD_ENET_RXD0__ENET_RDATA_0, ++ MX6Q_PAD_ENET_TX_EN__ENET_TX_EN, ++ MX6Q_PAD_ENET_TXD1__ENET_TDATA_1, ++ MX6Q_PAD_ENET_TXD0__ENET_TDATA_0, ++}; ++ ++static const struct gpio tx6q_gpios[] = { ++ { TX6Q_RESET_OUT_GPIO, GPIOF_OUTPUT_INIT_HIGH, "#RESET_OUT", }, ++ { TX6Q_FEC_PWR_GPIO, GPIOF_OUTPUT_INIT_HIGH, "FEC PHY PWR", }, ++ { TX6Q_FEC_RST_GPIO, GPIOF_OUTPUT_INIT_LOW, "FEC PHY RESET", }, ++ { TX6Q_FEC_INT_GPIO, GPIOF_INPUT, "FEC PHY INT", }, ++}; ++ ++/* ++ * Functions ++ */ ++/* placed in section '.data' to prevent overwriting relocation info ++ * overlayed with bss ++ */ ++static u32 wrsr __attribute__((section(".data"))); ++ ++#define WRSR_POR (1 << 4) ++#define WRSR_TOUT (1 << 1) ++#define WRSR_SFTW (1 << 0) ++ ++static void print_reset_cause(void) ++{ ++ struct src *src_regs = (struct src *)SRC_BASE_ADDR; ++ void __iomem *wdt_base = (void __iomem *)WDOG1_BASE_ADDR; ++ u32 srsr; ++ char *dlm = ""; ++ ++ printf("Reset cause: "); ++ ++ srsr = readl(&src_regs->srsr); ++ wrsr = readw(wdt_base + 4); ++ ++ if (wrsr & WRSR_POR) { ++ printf("%sPOR", dlm); ++ dlm = " | "; ++ } ++ if (srsr & 0x00004) { ++ printf("%sCSU", dlm); ++ dlm = " | "; ++ } ++ if (srsr & 0x00008) { ++ printf("%sIPP USER", dlm); ++ dlm = " | "; ++ } ++ if (srsr & 0x00010) { ++ if (wrsr & WRSR_SFTW) { ++ printf("%sSOFT", dlm); ++ dlm = " | "; ++ } ++ if (wrsr & WRSR_TOUT) { ++ printf("%sWDOG", dlm); ++ dlm = " | "; ++ } ++ } ++ if (srsr & 0x00020) { ++ printf("%sJTAG HIGH-Z", dlm); ++ dlm = " | "; ++ } ++ if (srsr & 0x00040) { ++ printf("%sJTAG SW", dlm); ++ dlm = " | "; ++ } ++ if (srsr & 0x10000) { ++ printf("%sWARM BOOT", dlm); ++ dlm = " | "; ++ } ++ if (dlm[0] == '\0') ++ printf("unknown"); ++ ++ printf("\n"); ++} ++ ++int read_cpu_temperature(void); ++int check_cpu_temperature(int boot); ++ ++static void print_cpuinfo(void) ++{ ++ u32 cpurev; ++ ++ cpurev = get_cpu_rev(); ++ ++ printf("CPU: Freescale i.MX6Q rev%d.%d at %d MHz\n", ++ (cpurev & 0x000F0) >> 4, ++ (cpurev & 0x0000F) >> 0, ++ mxc_get_clock(MXC_ARM_CLK) / 1000000); ++ ++ print_reset_cause(); ++ check_cpu_temperature(1); ++} ++ ++#define LTC3676_DVB2A 0x0C ++#define LTC3676_DVB2B 0x0D ++#define LTC3676_DVB4A 0x10 ++#define LTC3676_DVB4B 0x11 ++ ++#define VDD_SOC_mV (1375 + 50) ++#define VDD_CORE_mV (1375 + 50) ++ ++#define mV_to_regval(mV) (((mV) * 360 / 330 - 825 + 1) / 25) ++#define regval_to_mV(v) (((v) * 25 + 825) * 330 / 360) ++ ++static int setup_pmic_voltages(void) ++{ ++ int ret; ++ unsigned char value; ++ ++ i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); ++ ++ ret = i2c_probe(CONFIG_SYS_I2C_SLAVE); ++ if (ret != 0) { ++ printf("Failed to initialize I2C\n"); ++ return ret; ++ } ++ ++ ret = i2c_read(CONFIG_SYS_I2C_SLAVE, 0x11, 1, &value, 1); ++ if (ret) { ++ printf("%s: i2c_read error: %d\n", __func__, ret); ++ return ret; ++ } ++ ++ /* VDDCORE/VDDSOC default 1.375V is not enough, considering ++ pfuze tolerance and IR drop and ripple, need increase ++ to 1.425V for SabreSD */ ++ ++ value = 0x39; /* VB default value & PGOOD not forced when slewing */ ++ ret = i2c_write(CONFIG_SYS_I2C_SLAVE, LTC3676_DVB2B, 1, &value, 1); ++ if (ret) { ++ printf("%s: failed to write PMIC DVB2B register: %d\n", ++ __func__, ret); ++ return ret; ++ } ++ ret = i2c_write(CONFIG_SYS_I2C_SLAVE, LTC3676_DVB4B, 1, &value, 1); ++ if (ret) { ++ printf("%s: failed to write PMIC DVB4B register: %d\n", ++ __func__, ret); ++ return ret; ++ } ++ ++ value = mV_to_regval(VDD_SOC_mV); ++ ret = i2c_write(CONFIG_SYS_I2C_SLAVE, LTC3676_DVB2A, 1, &value, 1); ++ if (ret) { ++ printf("%s: failed to write PMIC DVB2A register: %d\n", ++ __func__, ret); ++ return ret; ++ } ++ printf("VDDSOC set to %dmV\n", regval_to_mV(value)); ++ ++ value = mV_to_regval(VDD_CORE_mV); ++ ret = i2c_write(CONFIG_SYS_I2C_SLAVE, LTC3676_DVB4A, 1, &value, 1); ++ if (ret) { ++ printf("%s: failed to write PMIC DVB4A register: %d\n", ++ __func__, ret); ++ return ret; ++ } ++ printf("VDDCORE set to %dmV\n", regval_to_mV(value)); ++ return 0; ++} ++ ++int board_early_init_f(void) ++{ ++#if 0 ++ writel(0xffffffff, 0x020c4068); /* CCGR0 */ ++ writel(0xffffffff, 0x020c406c); /* CCGR1 */ ++ writel(0xffffffff, 0x020c4070); /* CCGR2 */ ++ writel(0xffffffff, 0x020c4074); /* CCGR3 */ ++ writel(0xffffffff, 0x020c4078); /* CCGR4 */ ++ writel(0xffffffff, 0x020c407c); /* CCGR5 */ ++ writel(0xffffffff, 0x020c4080); /* CCGR6 */ ++ writel(0xffffffff, 0x020c4084); /* CCGR7 */ ++#endif ++#if 0 ++ writel(0x00000000, 0x020e02d4); /* NANDF_CLE: NANDF_CLE */ ++ writel(0x00000000, 0x020e02d8); /* NANDF_ALE: NANDF_ALE */ ++ writel(0x00000000, 0x020e02dc); /* NANDF_WP_B: NANDF_WPn */ ++ writel(0x00000000, 0x020e02e0); /* NANDF_RB0: NANDF_READY0 */ ++ writel(0x00000000, 0x020e02e4); /* NANDF_CS0: NANDF_CS0 */ ++ writel(0x00000001, 0x020e02f4); /* SD4_CMD: NANDF_RDn */ ++ writel(0x00000001, 0x020e02f8); /* SD4_CLK: NANDF_WRn */ ++ ++ writel(0x00000000, 0x020e02fc); /* NANDF_D0: NANDF_D0 */ ++ writel(0x00000000, 0x020e0300); /* NANDF_D1: NANDF_D1 */ ++ writel(0x00000000, 0x020e0304); /* NANDF_D2: NANDF_D2 */ ++ writel(0x00000000, 0x020e0308); /* NANDF_D3: NANDF_D3 */ ++ writel(0x00000000, 0x020e030c); /* NANDF_D4: NANDF_D4 */ ++ writel(0x00000000, 0x020e0310); /* NANDF_D5: NANDF_D5 */ ++ writel(0x00000000, 0x020e0314); /* NANDF_D6: NANDF_D6 */ ++ writel(0x00000000, 0x020e0318); /* NANDF_D7: NANDF_D7 */ ++#endif ++ gpio_request_array(tx6q_gpios, ARRAY_SIZE(tx6q_gpios)); ++ imx_iomux_v3_setup_multiple_pads(tx6q_pads, ARRAY_SIZE(tx6q_pads)); ++ ++#if 0 ++ int ret; ++ ret = setup_pmic_voltages(); ++ if (ret) { ++ printf("Failed to setup PMIC voltages\n"); ++// hang(); ++ } ++#endif ++ return 0; ++} ++ ++int board_init(void) ++{ ++ int ret; ++ ++ /* Address of boot parameters */ ++ gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x1000; ++#if 1 ++ gd->bd->bi_arch_number = 4429; ++#endif ++ ret = setup_pmic_voltages(); ++ if (ret) { ++ printf("Failed to setup PMIC voltages\n"); ++// hang(); ++ } ++ return 0; ++} ++ ++int dram_init(void) ++{ ++ /* dram_init must store complete ramsize in gd->ram_size */ ++ gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, ++ PHYS_SDRAM_1_SIZE); ++ return 0; ++} ++ ++void dram_init_banksize(void) ++{ ++ gd->bd->bi_dram[0].start = PHYS_SDRAM_1; ++ gd->bd->bi_dram[0].size = get_ram_size((void *)PHYS_SDRAM_1, ++ PHYS_SDRAM_1_SIZE); ++#if CONFIG_NR_DRAM_BANKS > 1 ++ gd->bd->bi_dram[1].start = PHYS_SDRAM_2; ++ gd->bd->bi_dram[1].size = get_ram_size((void *)PHYS_SDRAM_2, ++ PHYS_SDRAM_2_SIZE); ++#endif ++} ++ ++#ifdef CONFIG_CMD_MMC ++static const iomux_v3_cfg_t mmc0_pads[] = { ++ MX6Q_PAD_SD1_CMD__USDHC1_CMD, ++ MX6Q_PAD_SD1_CLK__USDHC1_CLK, ++ MX6Q_PAD_SD1_DAT0__USDHC1_DAT0, ++ MX6Q_PAD_SD1_DAT1__USDHC1_DAT1, ++ MX6Q_PAD_SD1_DAT2__USDHC1_DAT2, ++ MX6Q_PAD_SD1_DAT3__USDHC1_DAT3, ++ /* SD1 CD */ ++ MX6Q_PAD_SD3_CMD__GPIO_7_2, ++}; ++ ++static const iomux_v3_cfg_t mmc1_pads[] = { ++ MX6Q_PAD_SD2_CMD__USDHC2_CMD, ++ MX6Q_PAD_SD2_CLK__USDHC2_CLK, ++ MX6Q_PAD_SD2_DAT0__USDHC2_DAT0, ++ MX6Q_PAD_SD2_DAT1__USDHC2_DAT1, ++ MX6Q_PAD_SD2_DAT2__USDHC2_DAT2, ++ MX6Q_PAD_SD2_DAT3__USDHC2_DAT3, ++ /* SD2 CD */ ++ MX6Q_PAD_SD3_CLK__GPIO_7_3, ++}; ++ ++static struct tx6q_esdhc_cfg { ++ const iomux_v3_cfg_t *pads; ++ int num_pads; ++ enum mxc_clock clkid; ++ struct fsl_esdhc_cfg cfg; ++} tx6q_esdhc_cfg[] = { ++ { ++ .pads = mmc0_pads, ++ .num_pads = ARRAY_SIZE(mmc0_pads), ++ .clkid = MXC_ESDHC_CLK, ++ .cfg = { ++ .esdhc_base = (void __iomem *)USDHC1_BASE_ADDR, ++ .cd_gpio = IMX_GPIO_NR(7, 2), ++ .wp_gpio = -EINVAL, ++ }, ++ }, ++ { ++ .pads = mmc1_pads, ++ .num_pads = ARRAY_SIZE(mmc1_pads), ++ .clkid = MXC_ESDHC2_CLK, ++ .cfg = { ++ .esdhc_base = (void __iomem *)USDHC2_BASE_ADDR, ++ .cd_gpio = IMX_GPIO_NR(7, 3), ++ .wp_gpio = -EINVAL, ++ }, ++ }, ++}; ++ ++static inline struct tx6q_esdhc_cfg *to_tx6q_esdhc_cfg(struct fsl_esdhc_cfg *cfg) ++{ ++ void *p = cfg; ++ ++ return p - offsetof(struct tx6q_esdhc_cfg, cfg); ++} ++ ++int board_mmc_getcd(struct mmc *mmc) ++{ ++ struct fsl_esdhc_cfg *cfg = mmc->priv; ++ ++ if (cfg->cd_gpio < 0) ++ return cfg->cd_gpio; ++ ++ debug("SD card %d is %spresent\n", ++ to_tx6q_esdhc_cfg(cfg) - tx6q_esdhc_cfg, gpio_get_value(cfg->cd_gpio) ? "NOT " : ""); ++ return !gpio_get_value(cfg->cd_gpio); ++} ++ ++int board_mmc_init(bd_t *bis) ++{ ++ int i; ++ ++ for (i = 0; i < ARRAY_SIZE(tx6q_esdhc_cfg); i++) { ++ struct mmc *mmc; ++ struct fsl_esdhc_cfg *cfg = &tx6q_esdhc_cfg[i].cfg; ++ ++ if (i >= CONFIG_SYS_FSL_ESDHC_NUM) ++ break; ++ ++ cfg->sdhc_clk = mxc_get_clock(tx6q_esdhc_cfg[i].clkid); ++ imx_iomux_v3_setup_multiple_pads(tx6q_esdhc_cfg[i].pads, ++ tx6q_esdhc_cfg[i].num_pads); ++ ++ debug("%s: Initializing MMC slot %d\n", __func__, i); ++ fsl_esdhc_initialize(bis, cfg); ++ ++ mmc = find_mmc_device(i); ++ if (mmc == NULL) ++ continue; ++ if (board_mmc_getcd(mmc) > 0) ++ mmc_init(mmc); ++ } ++ return 0; ++} ++#endif /* CONFIG_CMD_MMC */ ++ ++#ifdef CONFIG_FEC_MXC ++ ++#define FEC_PAD_CTL (PAD_CTL_DVS | PAD_CTL_DSE_HIGH | \ ++ PAD_CTL_SRE_FAST) ++#define FEC_PAD_CTL2 (PAD_CTL_DVS | PAD_CTL_SRE_FAST) ++#define GPIO_PAD_CTL (PAD_CTL_DVS | PAD_CTL_DSE_HIGH) ++ ++#ifndef ETH_ALEN ++#define ETH_ALEN 6 ++#endif ++ ++int board_eth_init(bd_t *bis) ++{ ++ int ret; ++#if 0 ++ unsigned char mac[ETH_ALEN]; ++ char mac_str[ETH_ALEN * 3] = ""; ++#endif ++ /* delay at least 21ms for the PHY internal POR signal to deassert */ ++ udelay(22000); ++ ++ imx_iomux_v3_setup_multiple_pads(tx6q_fec_pads, ARRAY_SIZE(tx6q_fec_pads)); ++#if 0 ++ printf("RXD0(MODE0)=%d\n", gpio_get_value(IMX_GPIO_NR(1, 27))); ++ printf("RXD1(MODE1)=%d\n", gpio_get_value(IMX_GPIO_NR(1, 26))); ++ printf("CRS_DV(MODE2)=%d\n", gpio_get_value(IMX_GPIO_NR(1, 25))); ++ ++ printf("RX_ER(PHYAD0)=%d\n", gpio_get_value(IMX_GPIO_NR(1, 24))); ++ ++ printf("GPIO7[6](FEC RESET)=%d\n", gpio_get_value(IMX_GPIO_NR(7, 6))); ++ printf("GPIO3[20](FEC PWR)=%d\n", gpio_get_value(IMX_GPIO_NR(3, 20))); ++#endif ++ ++ /* Deassert RESET to the external phy */ ++ gpio_set_value(TX6Q_FEC_RST_GPIO, 1); ++ ++ ret = cpu_eth_init(bis); ++ if (ret) { ++ printf("cpu_eth_init() failed: %d\n", ret); ++ return ret; ++ } ++#if 0 ++ imx_get_mac_from_fuse(-1, mac); ++ snprintf(mac_str, sizeof(mac_str), "%02x:%02x:%02x:%02x:%02x:%02x", ++ mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]); ++ setenv("ethaddr", mac_str); ++#endif ++ return ret; ++} ++#endif /* CONFIG_FEC_MXC */ ++ ++enum { ++ LED_STATE_INIT = -1, ++ LED_STATE_OFF, ++ LED_STATE_ON, ++}; ++ ++static inline int calc_blink_rate(int tmp) ++{ ++ return CONFIG_SYS_HZ + CONFIG_SYS_HZ / 10 - ++ (tmp - TEMPERATURE_MIN) * CONFIG_SYS_HZ / ++ (TEMPERATURE_HOT - TEMPERATURE_MIN); ++} ++ ++void show_activity(int arg) ++{ ++ static int led_state = LED_STATE_INIT; ++ static int blink_rate; ++ static ulong last; ++ ++ if (led_state == LED_STATE_INIT) { ++ last = get_timer(0); ++ gpio_set_value(TX6Q_LED_GPIO, 1); ++ led_state = LED_STATE_ON; ++ blink_rate = calc_blink_rate(check_cpu_temperature(0)); ++ } else { ++ if (get_timer(last) > blink_rate) { ++ blink_rate = calc_blink_rate(check_cpu_temperature(0)); ++ last = get_timer_masked(); ++ if (led_state == LED_STATE_ON) { ++ gpio_set_value(TX6Q_LED_GPIO, 0); ++ } else { ++ gpio_set_value(TX6Q_LED_GPIO, 1); ++ } ++ led_state = 1 - led_state; ++ } ++ } ++} ++ ++static const iomux_v3_cfg_t stk5_pads[] = { ++ /* SW controlled LED on STK5 baseboard */ ++ MX6Q_PAD_EIM_A18__GPIO_2_20, ++ ++ /* LCD data pins */ ++ MX6Q_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0, ++ MX6Q_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1, ++ MX6Q_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2, ++ MX6Q_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3, ++ MX6Q_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4, ++ MX6Q_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5, ++ MX6Q_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6, ++ MX6Q_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7, ++ MX6Q_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8, ++ MX6Q_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9, ++ MX6Q_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10, ++ MX6Q_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11, ++ MX6Q_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12, ++ MX6Q_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13, ++ MX6Q_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14, ++ MX6Q_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15, ++ MX6Q_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16, ++ MX6Q_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17, ++ MX6Q_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18, ++ MX6Q_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19, ++ MX6Q_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20, ++ MX6Q_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21, ++ MX6Q_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22, ++ MX6Q_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23, ++ MX6Q_PAD_DI0_PIN2__IPU1_DI0_PIN2, /* HSYNC */ ++ MX6Q_PAD_DI0_PIN3__IPU1_DI0_PIN3, /* VSYNC */ ++ MX6Q_PAD_DI0_PIN15__IPU1_DI0_PIN15, /* OE_ACD */ ++ MX6Q_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK, /* LSCLK */ ++ ++ /* I2C bus on DIMM pins 40/41 */ ++ MX6Q_PAD_GPIO_6__I2C3_SDA, ++ MX6Q_PAD_GPIO_3__I2C3_SCL, ++ ++ /* TSC200x PEN IRQ */ ++ MX6Q_PAD_EIM_D26__GPIO_3_26, ++ ++ /* EDT-FT5x06 Polytouch panel */ ++ MX6Q_PAD_NANDF_CS2__GPIO_6_15, /* IRQ */ ++ MX6Q_PAD_EIM_A16__GPIO_2_22, /* RESET */ ++ MX6Q_PAD_EIM_A17__GPIO_2_21, /* WAKE */ ++ ++ /* USBH1 */ ++ MX6Q_PAD_EIM_D31__GPIO_3_31, /* VBUSEN */ ++ MX6Q_PAD_EIM_D30__GPIO_3_30, /* OC */ ++ /* USBOTG */ ++ MX6Q_PAD_EIM_D23__GPIO_3_23, /* USBOTG ID */ ++ MX6Q_PAD_GPIO_7__GPIO_1_7, /* VBUSEN */ ++ MX6Q_PAD_GPIO_8__GPIO_1_8, /* OC */ ++ ++ /* DEBUG */ ++ MX6Q_PAD_GPIO_0__CCM_CLKO, ++ MX6Q_PAD_NANDF_CS2__CCM_CLKO2, ++}; ++ ++static const struct gpio stk5_gpios[] = { ++ { TX6Q_LED_GPIO, GPIOF_OUTPUT_INIT_LOW, "HEARTBEAT LED", }, ++ ++ { IMX_GPIO_NR(3, 23), GPIOF_INPUT, "USBOTG ID", }, ++ { IMX_GPIO_NR(1, 8), GPIOF_INPUT, "USBOTG OC", }, ++ { IMX_GPIO_NR(1, 7), GPIOF_OUTPUT_INIT_LOW, "USBOTG VBUS enable", }, ++ { IMX_GPIO_NR(3, 30), GPIOF_INPUT, "USBH1 OC", }, ++ { IMX_GPIO_NR(3, 31), GPIOF_OUTPUT_INIT_LOW, "USBH1 VBUS enable", }, ++}; ++ ++#ifdef CONFIG_LCD ++vidinfo_t panel_info = { ++ /* set to max. size supported by SoC */ ++ .vl_col = 1920, ++ .vl_row = 1080, ++ ++ .vl_bpix = LCD_COLOR24, /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */ ++}; ++ ++static struct fb_videomode tx6q_fb_mode = { ++ /* Standard VGA timing */ ++ .name = "VGA", ++ .refresh = 60, ++ .xres = 640, ++ .yres = 480, ++ .pixclock = KHZ2PICOS(25175), ++ .left_margin = 48, ++ .hsync_len = 96, ++ .right_margin = 16, ++ .upper_margin = 31, ++ .vsync_len = 2, ++ .lower_margin = 12, ++ .sync = FB_SYNC_CLK_LAT_FALL, ++ .vmode = FB_VMODE_NONINTERLACED, ++}; ++ ++static int lcd_enabled = 1; ++ ++void lcd_enable(void) ++{ ++ /* HACK ALERT: ++ * global variable from common/lcd.c ++ * Set to 0 here to prevent messages from going to LCD ++ * rather than serial console ++ */ ++ lcd_is_enabled = 0; ++ ++ karo_load_splashimage(1); ++ if (lcd_enabled) { ++ debug("Switching LCD on\n"); ++ gpio_set_value(TX6Q_LCD_PWR_GPIO, 1); ++ udelay(100); ++ gpio_set_value(TX6Q_LCD_RST_GPIO, 1); ++ udelay(300000); ++ gpio_set_value(TX6Q_LCD_BACKLIGHT_GPIO, 0); ++ } ++} ++ ++static const iomux_v3_cfg_t stk5_lcd_pads[] = { ++ /* LCD RESET */ ++ MX6Q_PAD_EIM_D29__GPIO_3_29, ++ /* LCD POWER_ENABLE */ ++ MX6Q_PAD_EIM_EB3__GPIO_2_31, ++ /* LCD Backlight (PWM) */ ++ MX6Q_PAD_GPIO_1__GPIO_1_1, ++ ++ /* Display */ ++ MX6Q_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK, ++ MX6Q_PAD_DI0_PIN15__IPU1_DI0_PIN15, ++ MX6Q_PAD_DI0_PIN2__IPU1_DI0_PIN2, ++ MX6Q_PAD_DI0_PIN3__IPU1_DI0_PIN3, ++ MX6Q_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0, ++ MX6Q_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1, ++ MX6Q_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2, ++ MX6Q_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3, ++ MX6Q_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4, ++ MX6Q_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5, ++ MX6Q_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6, ++ MX6Q_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7, ++ MX6Q_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8, ++ MX6Q_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9, ++ MX6Q_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10, ++ MX6Q_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11, ++ MX6Q_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12, ++ MX6Q_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13, ++ MX6Q_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14, ++ MX6Q_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15, ++ MX6Q_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16, ++ MX6Q_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17, ++ MX6Q_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18, ++ MX6Q_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19, ++ MX6Q_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20, ++ MX6Q_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21, ++ MX6Q_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22, ++ MX6Q_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23, ++ ++ /* LVDS option */ ++ MX6Q_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3, ++ MX6Q_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2, ++ MX6Q_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK, ++ MX6Q_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1, ++ MX6Q_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0, ++ MX6Q_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3, ++ MX6Q_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK, ++ MX6Q_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2, ++ MX6Q_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1, ++ MX6Q_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0, ++}; ++ ++static const struct gpio stk5_lcd_gpios[] = { ++ { TX6Q_LCD_RST_GPIO, GPIOF_OUTPUT_INIT_LOW, "LCD RESET", }, ++ { TX6Q_LCD_PWR_GPIO, GPIOF_OUTPUT_INIT_LOW, "LCD POWER", }, ++ { TX6Q_LCD_BACKLIGHT_GPIO, GPIOF_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", }, ++}; ++ ++void lcd_ctrl_init(void *lcdbase) ++{ ++ int color_depth = 24; ++ char *vm; ++ unsigned long val; ++ int refresh = 60; ++ struct fb_videomode *p = &tx6q_fb_mode; ++ int xres_set = 0, yres_set = 0, bpp_set = 0, refresh_set = 0; ++ int pix_fmt = 0; ++ ipu_di_clk_parent_t di_clk_parent = DI_PCLK_PLL3; ++ unsigned long di_clk_rate = 65000000; ++ ++ if (!lcd_enabled) { ++ debug("LCD disabled\n"); ++ return; ++ } ++ ++ if (tstc() || (wrsr & WRSR_TOUT)) { ++ debug("Disabling LCD\n"); ++ lcd_enabled = 0; ++ return; ++ } ++ ++ vm = getenv("video_mode"); ++ if (vm == NULL) { ++ debug("Disabling LCD\n"); ++ lcd_enabled = 0; ++ return; ++ } ++ while (*vm != '\0') { ++ if (*vm >= '0' && *vm <= '9') { ++ char *end; ++ ++ val = simple_strtoul(vm, &end, 0); ++ if (end > vm) { ++ if (!xres_set) { ++ if (val > panel_info.vl_col) ++ val = panel_info.vl_col; ++ p->xres = val; ++ panel_info.vl_col = val; ++ xres_set = 1; ++ } else if (!yres_set) { ++ if (val > panel_info.vl_row) ++ val = panel_info.vl_row; ++ p->yres = val; ++ panel_info.vl_row = val; ++ yres_set = 1; ++ } else if (!bpp_set) { ++ switch (val) { ++ case 24: ++ if (pix_fmt == IPU_PIX_FMT_LVDS666) ++ pix_fmt = IPU_PIX_FMT_LVDS888; ++ /* fallthru */ ++ case 16: ++ case 8: ++ color_depth = val; ++ break; ++ ++ case 18: ++ if (pix_fmt == IPU_PIX_FMT_LVDS666) { ++ color_depth = val; ++ break; ++ } ++ /* fallthru */ ++ default: ++ printf("Invalid color depth: '%.*s' in video_mode; using default: '%u'\n", ++ end - vm, vm, color_depth); ++ } ++ bpp_set = 1; ++ } else if (!refresh_set) { ++ refresh = val; ++ refresh_set = 1; ++ } ++ } ++ vm = end; ++ } ++ switch (*vm) { ++ case '@': ++ bpp_set = 1; ++ /* fallthru */ ++ case '-': ++ yres_set = 1; ++ /* fallthru */ ++ case 'x': ++ xres_set = 1; ++ /* fallthru */ ++ case 'M': ++ case 'R': ++ vm++; ++ break; ++ ++ default: ++ if (!pix_fmt) { ++ char *tmp; ++ ++ if (strncmp(vm, "LVDS", 4) == 0) { ++ pix_fmt = IPU_PIX_FMT_LVDS666; ++ di_clk_parent = DI_PCLK_LDB; ++ } else { ++ pix_fmt = IPU_PIX_FMT_RGB24; ++ } ++ tmp = strchr(vm, ':'); ++ if (tmp) ++ vm = tmp; ++ } ++ if (*vm != '\0') ++ vm++; ++ } ++ } ++ switch (color_depth) { ++ case 8: ++ panel_info.vl_bpix = 3; ++ break; ++ ++ case 16: ++ panel_info.vl_bpix = 4; ++ break; ++ ++ case 18: ++ case 24: ++ panel_info.vl_bpix = 5; ++ } ++ ++ p->pixclock = KHZ2PICOS(refresh * ++ (p->xres + p->left_margin + p->right_margin + p->hsync_len) * ++ (p->yres + p->upper_margin + p->lower_margin + p->vsync_len) ++ / 1000); ++ debug("Pixel clock set to %lu.%03lu MHz\n", ++ PICOS2KHZ(p->pixclock) / 1000, ++ PICOS2KHZ(p->pixclock) % 1000); ++ ++ gpio_request_array(stk5_lcd_gpios, ARRAY_SIZE(stk5_lcd_gpios)); ++ imx_iomux_v3_setup_multiple_pads(stk5_lcd_pads, ++ ARRAY_SIZE(stk5_lcd_pads)); ++ ++ debug("Initializing FB driver\n"); ++ if (!pix_fmt) ++ pix_fmt = IPU_PIX_FMT_RGB24; ++ else if (pix_fmt == IPU_PIX_FMT_LVDS666) { ++ writel(0x01, IOMUXC_BASE_ADDR + 8); ++ } else if (pix_fmt == IPU_PIX_FMT_LVDS888) { ++ writel(0x21, IOMUXC_BASE_ADDR + 8); ++ } ++ if (pix_fmt != IPU_PIX_FMT_RGB24) { ++ struct mxc_ccm_reg *ccm_regs = (struct mxc_ccm_reg *)CCM_BASE_ADDR; ++ /* enable LDB & DI0 clock */ ++ writel(readl(&ccm_regs->CCGR3) | (3 << 12) | (3 << 2), ++ &ccm_regs->CCGR3); ++ } ++ ++ if (karo_load_splashimage(0) == 0) { ++ debug("Initializing LCD controller\n"); ++ ipuv3_fb_init(p, 0, pix_fmt, di_clk_parent, di_clk_rate, -1); ++ } else { ++ debug("Skipping initialization of LCD controller\n"); ++ } ++} ++#else ++#define lcd_enabled 0 ++#endif /* CONFIG_LCD */ ++ ++static void stk5_board_init(void) ++{ ++ gpio_request_array(stk5_gpios, ARRAY_SIZE(stk5_gpios)); ++ imx_iomux_v3_setup_multiple_pads(stk5_pads, ARRAY_SIZE(stk5_pads)); ++} ++ ++static void stk5v3_board_init(void) ++{ ++ stk5_board_init(); ++} ++ ++static void stk5v5_board_init(void) ++{ ++ stk5_board_init(); ++ ++ gpio_request_one(IMX_GPIO_NR(4, 21), GPIOF_OUTPUT_INIT_HIGH, ++ "Flexcan Transceiver"); ++ imx_iomux_v3_setup_pad(MX6Q_PAD_DISP0_DAT0__GPIO_4_21); ++} ++ ++static void tx6q_set_cpu_clock(void) ++{ ++ unsigned long cpu_clk = getenv_ulong("cpu_clk", 10, 0); ++ ++ if (tstc() || (wrsr & WRSR_TOUT)) ++ return; ++ ++ if (cpu_clk == 0 || cpu_clk == mxc_get_clock(MXC_ARM_CLK) / 1000000) ++ return; ++ ++ mxc_set_clock(CONFIG_SYS_MX6_HCLK, cpu_clk, MXC_ARM_CLK); ++ ++ printf("CPU clock set to %u.%03u MHz\n", ++ mxc_get_clock(MXC_ARM_CLK) / 1000000, ++ mxc_get_clock(MXC_ARM_CLK) / 1000 % 1000); ++} ++ ++static void tx6_init_mac(void) ++{ ++ u8 mac[ETH_ALEN]; ++ char mac_str[ETH_ALEN * 3] = ""; ++ ++ imx_get_mac_from_fuse(-1, mac); ++ if (!is_valid_ether_addr(mac)) { ++ printf("No valid MAC address programmed\n"); ++ return; ++ } ++ ++ snprintf(mac_str, sizeof(mac_str), "%02x:%02x:%02x:%02x:%02x:%02x", ++ mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]); ++ setenv("ethaddr", mac_str); ++ printf("MAC addr from fuse: %02x:%02x:%02x:%02x:%02x:%02x\n", ++ mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]); ++} ++ ++int board_late_init(void) ++{ ++ int ret = 0; ++ const char *baseboard; ++ ++ tx6q_set_cpu_clock(); ++ karo_fdt_move_fdt(); ++ ++ baseboard = getenv("baseboard"); ++ if (!baseboard) ++ goto exit; ++ ++ printf("Baseboard: %s\n", baseboard); ++ ++ if (strncmp(baseboard, "stk5", 4) == 0) { ++ if ((strlen(baseboard) == 4) || ++ strcmp(baseboard, "stk5-v3") == 0) { ++ stk5v3_board_init(); ++ } else if (strcmp(baseboard, "stk5-v5") == 0) { ++ stk5v5_board_init(); ++ } else { ++ printf("WARNING: Unsupported STK5 board rev.: %s\n", ++ baseboard + 4); ++ } ++ } else { ++ printf("WARNING: Unsupported baseboard: '%s'\n", ++ baseboard); ++ ret = -EINVAL; ++ } ++ ++exit: ++ tx6_init_mac(); ++ ++ gpio_set_value(TX6Q_RESET_OUT_GPIO, 1); ++ return ret; ++} ++ ++#define iomux_field(v,f) (((iomux_v3_cfg_t)(v) << f##_SHIFT) & f##_MASK) ++ ++#define chk_iomux_field(f1,f2) ({ \ ++ iomux_v3_cfg_t __c = iomux_field(~0, f1); \ ++ if (__c & f2##_MASK) { \ ++ printf("%18s[%016llx] overlaps with:\n%18s[%016llx]\n", \ ++ #f1, f1##_MASK, \ ++ #f2, f2##_MASK); \ ++ } \ ++ (__c & f2##_MASK) != 0; \ ++}) ++ ++#define chk_iomux_bit(f1,f2) ({ \ ++ iomux_v3_cfg_t __c = iomux_field(~0, f1); \ ++ if (__c & f2) { \ ++ printf("%18s[%016llx] overlaps with:\n%18s[%016llx]\n", \ ++ #f1, f1##_MASK, \ ++ #f2, (iomux_v3_cfg_t)f2); \ ++ } \ ++ (__c & f2) != 0; \ ++}) ++ ++int checkboard(void) ++{ ++ print_cpuinfo(); ++ ++ printf("Board: Ka-Ro TX6Q\n"); ++ ++#ifdef TIMER_TEST ++ { ++ struct mxc_gpt { ++ unsigned int control; ++ unsigned int prescaler; ++ unsigned int status; ++ unsigned int nouse[6]; ++ unsigned int counter; ++ }; ++ const int us_delay = 10; ++ unsigned long start = get_timer(0); ++ unsigned long last = gd->arch.tbl; ++ unsigned long loop = 0; ++ unsigned long cnt = 0; ++ static struct mxc_gpt *timer_base = (struct mxc_gpt *)GPT1_BASE_ADDR; ++ ++ printf("GPT prescaler=%u\n", readl(&timer_base->prescaler) + 1); ++ printf("clock tick rate: %lu.%03lukHz\n", ++ gd->arch.timer_rate_hz / 1000, gd->arch.timer_rate_hz % 1000); ++ printf("ticks/us=%lu\n", gd->arch.timer_rate_hz / CONFIG_SYS_HZ / 1000); ++ ++ while (!tstc()) { ++ unsigned long elapsed = get_timer(start); ++ unsigned long diff = gd->arch.tbl - last; ++ ++ loop++; ++ last = gd->arch.tbl; ++ ++ printf("loop %4lu: t=%08lx diff=%08lx steps=%6lu elapsed time: %4lu", ++ loop, gd->arch.tbl, diff, cnt, elapsed / CONFIG_SYS_HZ); ++ cnt = 0; ++ while (get_timer(elapsed + start) < CONFIG_SYS_HZ) { ++ cnt++; ++ udelay(us_delay); ++ } ++ printf(" counter=%08x udelay(%u)=%lu.%03luus\n", ++ readl(&timer_base->counter), us_delay, ++ 1000000000 / cnt / 1000, 1000000000 / cnt % 1000); ++ } ++ } ++#endif ++ return 0; ++} ++ ++#if defined(CONFIG_OF_BOARD_SETUP) ++#ifdef CONFIG_FDT_FIXUP_PARTITIONS ++#include ++#include ++struct node_info nodes[] = { ++ { "fsl,imx53-nand", MTD_DEV_TYPE_NAND, }, ++}; ++ ++#else ++#define fdt_fixup_mtdparts(b,n,c) do { } while (0) ++#endif ++ ++static void tx6q_fixup_flexcan(void *blob) ++{ ++ const char *baseboard = getenv("baseboard"); ++ ++ if (baseboard && strcmp(baseboard, "stk5-v5") == 0) ++ return; ++ ++ karo_fdt_del_prop(blob, "fsl,p1010-flexcan", 0x02090000, "transceiver-switch"); ++ karo_fdt_del_prop(blob, "fsl,p1010-flexcan", 0x02094000, "transceiver-switch"); ++} ++ ++void tx6q_fixup_rtc(void *blob) ++{ ++ karo_fdt_del_prop(blob, "dallas,ds1339", 0x68, "interrupt-parent"); ++ karo_fdt_del_prop(blob, "dallas,ds1339", 0x68, "interrupts"); ++} ++ ++void ft_board_setup(void *blob, bd_t *bd) ++{ ++ fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes)); ++ fdt_fixup_ethernet(blob); ++ ++ karo_fdt_fixup_touchpanel(blob); ++ karo_fdt_fixup_usb_otg(blob, "", 0); ++ tx6q_fixup_flexcan(blob); ++ tx6q_fixup_rtc(blob); ++} ++#endif diff --cc board/karo/tx6q/u-boot.bd index 0000000000,0000000000..bbf6658107 new file mode 100644 --- /dev/null +++ b/board/karo/tx6q/u-boot.bd @@@ -1,0 -1,0 +1,14 @@@ ++sources { ++ u_boot_spl="@@BUILD_DIR@@spl/u-boot-spl"; ++ u_boot="@@BUILD_DIR@@u-boot"; ++} ++ ++section (0) { ++ load u_boot_spl; ++ load ivt (entry = u_boot_spl:reset) > 0x8000; ++ hab call 0x8000; ++ ++ load u_boot; ++ load ivt (entry = u_boot:reset) > 0x8000; ++ hab call 0x8000; ++} diff --cc board/karo/tx6q/u-boot.lds index 0000000000,0000000000..bcbafe9801 new file mode 100644 --- /dev/null +++ b/board/karo/tx6q/u-boot.lds @@@ -1,0 -1,0 +1,84 @@@ ++/* ++ * (C) Copyright 2012 Lothar Waßmann ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") ++OUTPUT_ARCH(arm) ++ENTRY(_start) ++SECTIONS ++{ ++ . = 0x00000000; ++ ++ . = ALIGN(4); ++ .text : ++ { ++ board/karo/tx6q/lowlevel_init.o (.text*) ++ __image_copy_start = .; ++ CPUDIR/start.o (.text*) ++ *(.text*) ++ } ++ ++ . = ALIGN(4); ++ .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } ++ ++ . = ALIGN(4); ++ .data : { ++ *(.data*) ++ } ++ ++ . = ALIGN(4); ++ ++ . = .; ++ ++ . = ALIGN(4); ++ .u_boot_list : { ++ #include ++ } ++ ++ . = ALIGN(4); ++ ++ __image_copy_end = .; ++ ++ .rel.dyn : { ++ __rel_dyn_start = .; ++ *(.rel*) ++ __rel_dyn_end = .; ++ } ++ ++ .dynsym : { ++ __dynsym_start = .; ++ *(.dynsym) ++ } ++ ++ _end = .; ++ ++ .bss __rel_dyn_start (OVERLAY) : { ++ __bss_start = .; ++ *(.bss) ++ . = ALIGN(4); ++ __bss_end__ = .; ++ } ++ ++ /DISCARD/ : { *(.dynstr*) } ++ /DISCARD/ : { *(.dynamic*) } ++ /DISCARD/ : { *(.plt*) } ++ /DISCARD/ : { *(.interp*) } ++ /DISCARD/ : { *(.gnu*) } ++} diff --cc board/ti/am335x/board.c index 0000000000,ed4229e258..fada50c0c5 mode 000000,100644..100644 --- a/board/ti/am335x/board.c +++ b/board/ti/am335x/board.c @@@ -1,0 -1,439 +1,439 @@@ + /* + * board.c + * + * Board functions for TI AM335X based boards + * + * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the + * GNU General Public License for more details. + */ + + #include + #include + #include + #include + #include + #include + #include + #include + #include + #include + #include + #include + #include + #include + #include + #include -#include ++//#include + #include "board.h" + + DECLARE_GLOBAL_DATA_PTR; + + static struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE; + #ifdef CONFIG_SPL_BUILD + static struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE; + #endif + + /* MII mode defines */ + #define MII_MODE_ENABLE 0x0 + #define RGMII_MODE_ENABLE 0x3A + + /* GPIO that controls power to DDR on EVM-SK */ + #define GPIO_DDR_VTT_EN 7 + + static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; + + static struct am335x_baseboard_id __attribute__((section (".data"))) header; + + static inline int board_is_bone(void) + { + return !strncmp(header.name, "A335BONE", HDR_NAME_LEN); + } + + static inline int board_is_bone_lt(void) + { + return !strncmp(header.name, "A335BNLT", HDR_NAME_LEN); + } + + static inline int board_is_evm_sk(void) + { + return !strncmp("A335X_SK", header.name, HDR_NAME_LEN); + } + + static inline int board_is_idk(void) + { + return !strncmp(header.config, "SKU#02", 6); + } + + /* + * Read header information from EEPROM into global structure. + */ + static int read_eeprom(void) + { + /* Check if baseboard eeprom is available */ + if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) { + puts("Could not probe the EEPROM; something fundamentally " + "wrong on the I2C bus.\n"); + return -ENODEV; + } + + /* read the eeprom using i2c */ + if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, (uchar *)&header, + sizeof(header))) { + puts("Could not read the EEPROM; something fundamentally" + " wrong on the I2C bus.\n"); + return -EIO; + } + + if (header.magic != 0xEE3355AA) { + /* + * read the eeprom using i2c again, + * but use only a 1 byte address + */ + if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1, + (uchar *)&header, sizeof(header))) { + puts("Could not read the EEPROM; something " + "fundamentally wrong on the I2C bus.\n"); + return -EIO; + } + + if (header.magic != 0xEE3355AA) { + printf("Incorrect magic number (0x%x) in EEPROM\n", + header.magic); + return -EINVAL; + } + } + + return 0; + } + + /* UART Defines */ + #ifdef CONFIG_SPL_BUILD + #define UART_RESET (0x1 << 1) + #define UART_CLK_RUNNING_MASK 0x1 + #define UART_SMART_IDLE_EN (0x1 << 0x3) + + static void rtc32k_enable(void) + { + struct rtc_regs *rtc = (struct rtc_regs *)AM335X_RTC_BASE; + + /* + * Unlock the RTC's registers. For more details please see the + * RTC_SS section of the TRM. In order to unlock we need to + * write these specific values (keys) in this order. + */ + writel(0x83e70b13, &rtc->kick0r); + writel(0x95a4f1e0, &rtc->kick1r); + + /* Enable the RTC 32K OSC by setting bits 3 and 6. */ + writel((1 << 3) | (1 << 6), &rtc->osc); + } + + static const struct ddr_data ddr2_data = { + .datardsratio0 = ((MT47H128M16RT25E_RD_DQS<<30) | + (MT47H128M16RT25E_RD_DQS<<20) | + (MT47H128M16RT25E_RD_DQS<<10) | + (MT47H128M16RT25E_RD_DQS<<0)), + .datawdsratio0 = ((MT47H128M16RT25E_WR_DQS<<30) | + (MT47H128M16RT25E_WR_DQS<<20) | + (MT47H128M16RT25E_WR_DQS<<10) | + (MT47H128M16RT25E_WR_DQS<<0)), + .datawiratio0 = ((MT47H128M16RT25E_PHY_WRLVL<<30) | + (MT47H128M16RT25E_PHY_WRLVL<<20) | + (MT47H128M16RT25E_PHY_WRLVL<<10) | + (MT47H128M16RT25E_PHY_WRLVL<<0)), + .datagiratio0 = ((MT47H128M16RT25E_PHY_GATELVL<<30) | + (MT47H128M16RT25E_PHY_GATELVL<<20) | + (MT47H128M16RT25E_PHY_GATELVL<<10) | + (MT47H128M16RT25E_PHY_GATELVL<<0)), + .datafwsratio0 = ((MT47H128M16RT25E_PHY_FIFO_WE<<30) | + (MT47H128M16RT25E_PHY_FIFO_WE<<20) | + (MT47H128M16RT25E_PHY_FIFO_WE<<10) | + (MT47H128M16RT25E_PHY_FIFO_WE<<0)), + .datawrsratio0 = ((MT47H128M16RT25E_PHY_WR_DATA<<30) | + (MT47H128M16RT25E_PHY_WR_DATA<<20) | + (MT47H128M16RT25E_PHY_WR_DATA<<10) | + (MT47H128M16RT25E_PHY_WR_DATA<<0)), + .datauserank0delay = MT47H128M16RT25E_PHY_RANK0_DELAY, + .datadldiff0 = PHY_DLL_LOCK_DIFF, + }; + + static const struct cmd_control ddr2_cmd_ctrl_data = { + .cmd0csratio = MT47H128M16RT25E_RATIO, + .cmd0dldiff = MT47H128M16RT25E_DLL_LOCK_DIFF, + .cmd0iclkout = MT47H128M16RT25E_INVERT_CLKOUT, + + .cmd1csratio = MT47H128M16RT25E_RATIO, + .cmd1dldiff = MT47H128M16RT25E_DLL_LOCK_DIFF, + .cmd1iclkout = MT47H128M16RT25E_INVERT_CLKOUT, + + .cmd2csratio = MT47H128M16RT25E_RATIO, + .cmd2dldiff = MT47H128M16RT25E_DLL_LOCK_DIFF, + .cmd2iclkout = MT47H128M16RT25E_INVERT_CLKOUT, + }; + + static const struct emif_regs ddr2_emif_reg_data = { + .sdram_config = MT47H128M16RT25E_EMIF_SDCFG, + .ref_ctrl = MT47H128M16RT25E_EMIF_SDREF, + .sdram_tim1 = MT47H128M16RT25E_EMIF_TIM1, + .sdram_tim2 = MT47H128M16RT25E_EMIF_TIM2, + .sdram_tim3 = MT47H128M16RT25E_EMIF_TIM3, + .emif_ddr_phy_ctlr_1 = MT47H128M16RT25E_EMIF_READ_LATENCY, + }; + + static const struct ddr_data ddr3_data = { + .datardsratio0 = MT41J128MJT125_RD_DQS, + .datawdsratio0 = MT41J128MJT125_WR_DQS, + .datafwsratio0 = MT41J128MJT125_PHY_FIFO_WE, + .datawrsratio0 = MT41J128MJT125_PHY_WR_DATA, + .datadldiff0 = PHY_DLL_LOCK_DIFF, + }; + + static const struct cmd_control ddr3_cmd_ctrl_data = { + .cmd0csratio = MT41J128MJT125_RATIO, + .cmd0dldiff = MT41J128MJT125_DLL_LOCK_DIFF, + .cmd0iclkout = MT41J128MJT125_INVERT_CLKOUT, + + .cmd1csratio = MT41J128MJT125_RATIO, + .cmd1dldiff = MT41J128MJT125_DLL_LOCK_DIFF, + .cmd1iclkout = MT41J128MJT125_INVERT_CLKOUT, + + .cmd2csratio = MT41J128MJT125_RATIO, + .cmd2dldiff = MT41J128MJT125_DLL_LOCK_DIFF, + .cmd2iclkout = MT41J128MJT125_INVERT_CLKOUT, + }; + + static struct emif_regs ddr3_emif_reg_data = { + .sdram_config = MT41J128MJT125_EMIF_SDCFG, + .ref_ctrl = MT41J128MJT125_EMIF_SDREF, + .sdram_tim1 = MT41J128MJT125_EMIF_TIM1, + .sdram_tim2 = MT41J128MJT125_EMIF_TIM2, + .sdram_tim3 = MT41J128MJT125_EMIF_TIM3, + .zq_config = MT41J128MJT125_ZQ_CFG, + .emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY, + }; + #endif + + /* + * early system init of muxing and clocks. + */ + void s_init(void) + { + /* WDT1 is already running when the bootloader gets control + * Disable it to avoid "random" resets + */ + writel(0xAAAA, &wdtimer->wdtwspr); + while (readl(&wdtimer->wdtwwps) != 0x0) + ; + writel(0x5555, &wdtimer->wdtwspr); + while (readl(&wdtimer->wdtwwps) != 0x0) + ; + + #ifdef CONFIG_SPL_BUILD + /* Setup the PLLs and the clocks for the peripherals */ + pll_init(); + + /* Enable RTC32K clock */ + rtc32k_enable(); + + /* UART softreset */ + u32 regVal; + + #ifdef CONFIG_SERIAL1 + enable_uart0_pin_mux(); + #endif /* CONFIG_SERIAL1 */ + #ifdef CONFIG_SERIAL2 + enable_uart1_pin_mux(); + #endif /* CONFIG_SERIAL2 */ + #ifdef CONFIG_SERIAL3 + enable_uart2_pin_mux(); + #endif /* CONFIG_SERIAL3 */ + #ifdef CONFIG_SERIAL4 + enable_uart3_pin_mux(); + #endif /* CONFIG_SERIAL4 */ + #ifdef CONFIG_SERIAL5 + enable_uart4_pin_mux(); + #endif /* CONFIG_SERIAL5 */ + #ifdef CONFIG_SERIAL6 + enable_uart5_pin_mux(); + #endif /* CONFIG_SERIAL6 */ + + regVal = readl(&uart_base->uartsyscfg); + regVal |= UART_RESET; + writel(regVal, &uart_base->uartsyscfg); + while ((readl(&uart_base->uartsyssts) & + UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK) + ; + + /* Disable smart idle */ + regVal = readl(&uart_base->uartsyscfg); + regVal |= UART_SMART_IDLE_EN; + writel(regVal, &uart_base->uartsyscfg); + + gd = &gdata; + + preloader_console_init(); + + /* Initalize the board header */ + enable_i2c0_pin_mux(); + i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); + if (read_eeprom() < 0) + puts("Could not get board ID.\n"); + + enable_board_pin_mux(&header); + if (board_is_evm_sk()) { + /* + * EVM SK 1.2A and later use gpio0_7 to enable DDR3. + * This is safe enough to do on older revs. + */ + gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en"); + gpio_direction_output(GPIO_DDR_VTT_EN, 1); + } + + if (board_is_evm_sk() || board_is_bone_lt()) + config_ddr(303, MT41J128MJT125_IOCTRL_VALUE, &ddr3_data, + &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data); + else + config_ddr(266, MT47H128M16RT25E_IOCTRL_VALUE, &ddr2_data, + &ddr2_cmd_ctrl_data, &ddr2_emif_reg_data); + #endif + } + + /* + * Basic board specific setup. Pinmux has been handled already. + */ + int board_init(void) + { + i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); + if (read_eeprom() < 0) + puts("Could not get board ID.\n"); + + gd->bd->bi_boot_params = PHYS_DRAM_1 + 0x100; + + gpmc_init(); + + return 0; + } + + #ifdef CONFIG_BOARD_LATE_INIT + int board_late_init(void) + { + #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + char safe_string[HDR_NAME_LEN + 1]; + + /* Now set variables based on the header. */ + strncpy(safe_string, (char *)header.name, sizeof(header.name)); + safe_string[sizeof(header.name)] = 0; + setenv("board_name", safe_string); + + strncpy(safe_string, (char *)header.version, sizeof(header.version)); + safe_string[sizeof(header.version)] = 0; + setenv("board_rev", safe_string); + #endif + + return 0; + } + #endif + + #ifdef CONFIG_DRIVER_TI_CPSW + static void cpsw_control(int enabled) + { + /* VTP can be added here */ + + return; + } + + static struct cpsw_slave_data cpsw_slaves[] = { + { + .slave_reg_ofs = 0x208, + .sliver_reg_ofs = 0xd80, + .phy_id = 0, + }, + { + .slave_reg_ofs = 0x308, + .sliver_reg_ofs = 0xdc0, + .phy_id = 1, + }, + }; + + static struct cpsw_platform_data cpsw_data = { + .mdio_base = AM335X_CPSW_MDIO_BASE, + .cpsw_base = AM335X_CPSW_BASE, + .mdio_div = 0xff, + .channels = 8, + .cpdma_reg_ofs = 0x800, + .slaves = 1, + .slave_data = cpsw_slaves, + .ale_reg_ofs = 0xd00, + .ale_entries = 1024, + .host_port_reg_ofs = 0x108, + .hw_stats_reg_ofs = 0x900, + .mac_control = (1 << 5), + .control = cpsw_control, + .host_port_num = 0, + .version = CPSW_CTRL_VERSION_2, + }; + #endif + + #if defined(CONFIG_DRIVER_TI_CPSW) || \ + (defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET)) + int board_eth_init(bd_t *bis) + { + int rv, n = 0; + #ifdef CONFIG_DRIVER_TI_CPSW + uint8_t mac_addr[6]; + uint32_t mac_hi, mac_lo; + + if (!eth_getenv_enetaddr("ethaddr", mac_addr)) { + debug(" not set. Reading from E-fuse\n"); + /* try reading mac address from efuse */ + mac_lo = readl(&cdev->macid0l); + mac_hi = readl(&cdev->macid0h); + mac_addr[0] = mac_hi & 0xFF; + mac_addr[1] = (mac_hi & 0xFF00) >> 8; + mac_addr[2] = (mac_hi & 0xFF0000) >> 16; + mac_addr[3] = (mac_hi & 0xFF000000) >> 24; + mac_addr[4] = mac_lo & 0xFF; + mac_addr[5] = (mac_lo & 0xFF00) >> 8; + + if (is_valid_ether_addr(mac_addr)) + eth_setenv_enetaddr("ethaddr", mac_addr); + else + goto try_usbether; + } + + if (board_is_bone() || board_is_bone_lt() || board_is_idk()) { + writel(MII_MODE_ENABLE, &cdev->miisel); + cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if = + PHY_INTERFACE_MODE_MII; + } else { + writel(RGMII_MODE_ENABLE, &cdev->miisel); + cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if = + PHY_INTERFACE_MODE_RGMII; + } + + rv = cpsw_register(&cpsw_data); + if (rv < 0) + printf("Error %d registering CPSW switch\n", rv); + else + n += rv; + #endif + try_usbether: + #if defined(CONFIG_USB_ETHER) && !defined(CONFIG_SPL_BUILD) + rv = usb_eth_initialize(bis); + if (rv < 0) + printf("Error %d registering USB_ETHER\n", rv); + else + n += rv; + #endif + return n; + } + #endif diff --cc boards.cfg index 39a726995e,98f7a14d1e..6b9f9fa1a8 --- a/boards.cfg +++ b/boards.cfg @@@ -160,8 -188,6 +188,8 @@@ devkit3250 ar jadecpu arm arm926ejs jadecpu syteco mb86r0x mx25pdk arm arm926ejs mx25pdk freescale mx25 mx25pdk:IMX_CONFIG=board/freescale/mx25pdk/imximage.cfg tx25 arm arm926ejs tx25 karo mx25 - tx28-40xx arm arm926ejs tx28 karo mx28 tx28:TX28 - tx28-41xx arm arm926ejs tx28 karo mx28 tx28:TX28_S ++tx28-40xx arm arm926ejs tx28 karo mxs tx28:TX28 ++tx28-41xx arm arm926ejs tx28 karo mxs tx28:TX28_S zmx25 arm arm926ejs zmx25 syteco mx25 imx27lite arm arm926ejs imx27lite logicpd mx27 magnesium arm arm926ejs imx27lite logicpd mx27 @@@ -185,12 -230,15 +232,17 @@@ versatileqemu ar integratorap_cm946es arm arm946es integrator armltd - integratorap:CM946ES integratorcp_cm946es arm arm946es integrator armltd - integratorcp:CM946ES ca9x4_ct_vxp arm armv7 vexpress armltd - am335x_evm arm armv7 am335x ti am33xx + am335x_evm arm armv7 am335x ti am33xx am335x_evm:SERIAL1,CONS_INDEX=1 + am335x_evm_uart1 arm armv7 am335x ti am33xx am335x_evm:SERIAL2,CONS_INDEX=2 + am335x_evm_uart2 arm armv7 am335x ti am33xx am335x_evm:SERIAL3,CONS_INDEX=3 + am335x_evm_uart3 arm armv7 am335x ti am33xx am335x_evm:SERIAL4,CONS_INDEX=4 + am335x_evm_uart4 arm armv7 am335x ti am33xx am335x_evm:SERIAL5,CONS_INDEX=5 + am335x_evm_uart5 arm armv7 am335x ti am33xx am335x_evm:SERIAL6,CONS_INDEX=6 +tx48 arm armv7 tx48 karo am33xx tx48:SYS_MPU_CLK=500,SYS_DDR_CLK=266 +tx48-dt arm armv7 tx48 karo am33xx tx48:OF_LIBFDT,SYS_MPU_CLK=720,SYS_DDR_CLK=444 highbank arm armv7 highbank - highbank - efikamx arm armv7 efikamx - mx5 efikamx:MACH_TYPE=MACH_TYPE_MX51_EFIKAMX,IMX_CONFIG=board/efikamx/imximage_mx.cfg - efikasb arm armv7 efikamx - mx5 efikamx:MACH_TYPE=MACH_TYPE_MX51_EFIKASB,IMX_CONFIG=board/efikamx/imximage_sb.cfg + mx51_efikamx arm armv7 mx51_efikamx genesi mx5 mx51_efikamx:MACH_TYPE=MACH_TYPE_MX51_EFIKAMX,IMX_CONFIG=board/genesi/mx51_efikamx/imximage_mx.cfg + mx51_efikasb arm armv7 mx51_efikamx genesi mx5 mx51_efikamx:MACH_TYPE=MACH_TYPE_MX51_EFIKASB,IMX_CONFIG=board/genesi/mx51_efikamx/imximage_sb.cfg mx51evk arm armv7 mx51evk freescale mx5 mx51evk:IMX_CONFIG=board/freescale/mx51evk/imximage.cfg mx53ard arm armv7 mx53ard freescale mx5 mx53ard:IMX_CONFIG=board/freescale/mx53ard/imximage_dd3.cfg mx53evk arm armv7 mx53evk freescale mx5 mx53evk:IMX_CONFIG=board/freescale/mx53evk/imximage.cfg @@@ -198,18 -246,11 +250,22 @@@ mx53loco ar mx53smd arm armv7 mx53smd freescale mx5 mx53smd:IMX_CONFIG=board/freescale/mx53smd/imximage.cfg ima3-mx53 arm armv7 ima3-mx53 esg mx5 ima3-mx53:IMX_CONFIG=board/esg/ima3-mx53/imximage.cfg vision2 arm armv7 vision2 ttcontrol mx5 vision2:IMX_CONFIG=board/ttcontrol/vision2/imximage_hynix.cfg +tx51-6xx0 arm armv7 tx51 karo mx5 tx51:SYS_CPU_CLK=600,NR_DRAM_BANKS=1,SYS_SDRAM_CLK=166 +tx51-6xx1 arm armv7 tx51 karo mx5 tx51:SYS_CPU_CLK=600,NR_DRAM_BANKS=2,SYS_SDRAM_CLK=200 +tx51-6xx2 arm armv7 tx51 karo mx5 tx51:SYS_CPU_CLK=600,NR_DRAM_BANKS=2,SYS_SDRAM_CLK=166 +tx51-8xx0 arm armv7 tx51 karo mx5 tx51:SYS_CPU_CLK=800,NR_DRAM_BANKS=1,SYS_SDRAM_CLK=166 +tx51-8xx1 arm armv7 tx51 karo mx5 tx51:SYS_CPU_CLK=800,NR_DRAM_BANKS=2,SYS_SDRAM_CLK=200 +tx51-8xx2 arm armv7 tx51 karo mx5 tx51:SYS_CPU_CLK=800,NR_DRAM_BANKS=2,SYS_SDRAM_CLK=166 +tx53-xx20 arm armv7 tx53 karo mx5 tx53:NR_DRAM_BANKS=1,SYS_TX53_HWREV_2 +tx53-xx21 arm armv7 tx53 karo mx5 tx53:NR_DRAM_BANKS=2,SYS_TX53_HWREV_2 +tx53-xx30 arm armv7 tx53 karo mx5 tx53:NR_DRAM_BANKS=1 +tx53-xx31 arm armv7 tx53 karo mx5 tx53:NR_DRAM_BANKS=2 ++tx6q arm armv7 tx6q karo mx6 mx6qarm2 arm armv7 mx6qarm2 freescale mx6 mx6qarm2:IMX_CONFIG=board/freescale/mx6qarm2/imximage.cfg - mx6qsabrelite arm armv7 mx6qsabrelite freescale mx6 mx6qsabrelite:IMX_CONFIG=board/freescale/mx6qsabrelite/imximage.cfg + mx6qsabreauto arm armv7 mx6qsabreauto freescale mx6 mx6qsabreauto:IMX_CONFIG=board/freescale/mx6qsabreauto/imximage.cfg + mx6qsabrelite arm armv7 mx6qsabrelite freescale mx6 mx6qsabrelite:IMX_CONFIG=board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg + mx6qsabresd arm armv7 mx6qsabresd freescale mx6 mx6qsabresd:IMX_CONFIG=board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg + eco5pk arm armv7 eco5pk 8dtech omap3 cm_t35 arm armv7 cm_t35 - omap3 omap3_overo arm armv7 overo - omap3 omap3_pandora arm armv7 pandora - omap3 diff --cc common/Makefile index f7b76384ae,54fcc81588..e850875712 --- a/common/Makefile +++ b/common/Makefile @@@ -72,9 -71,10 +71,11 @@@ COBJS-$(CONFIG_CMD_SOURCE) += cmd_sourc COBJS-$(CONFIG_CMD_BDI) += cmd_bdinfo.o COBJS-$(CONFIG_CMD_BEDBUG) += bedbug.o cmd_bedbug.o COBJS-$(CONFIG_CMD_BMP) += cmd_bmp.o +COBJS-$(CONFIG_CMD_BOOTCE) += cmd_bootce.o COBJS-$(CONFIG_CMD_BOOTLDR) += cmd_bootldr.o + COBJS-$(CONFIG_CMD_BOOTSTAGE) += cmd_bootstage.o COBJS-$(CONFIG_CMD_CACHE) += cmd_cache.o + COBJS-$(CONFIG_CMD_CBFS) += cmd_cbfs.o COBJS-$(CONFIG_CMD_CONSOLE) += cmd_console.o COBJS-$(CONFIG_CMD_CPLBINFO) += cmd_cplbinfo.o COBJS-$(CONFIG_DATAFLASH_MMC_SELECT) += cmd_dataflash_mmc_mux.o @@@ -102,11 -104,14 +105,15 @@@ COBJS-$(CONFIG_CMD_FLASH) += cmd_flash. ifdef CONFIG_FPGA COBJS-$(CONFIG_CMD_FPGA) += cmd_fpga.o endif + COBJS-$(CONFIG_CMD_FS_GENERIC) += cmd_fs.o + COBJS-$(CONFIG_CMD_GETTIME) += cmd_gettime.o COBJS-$(CONFIG_CMD_GPIO) += cmd_gpio.o +COBJS-$(CONFIG_CMD_IIM) += cmd_iim.o COBJS-$(CONFIG_CMD_I2C) += cmd_i2c.o + COBJS-$(CONFIG_CMD_HASH) += cmd_hash.o COBJS-$(CONFIG_CMD_IDE) += cmd_ide.o COBJS-$(CONFIG_CMD_IMMAP) += cmd_immap.o + COBJS-$(CONFIG_CMD_INI) += cmd_ini.o COBJS-$(CONFIG_CMD_IRQ) += cmd_irq.o COBJS-$(CONFIG_CMD_ITEST) += cmd_itest.o COBJS-$(CONFIG_CMD_JFFS2) += cmd_jffs2.o @@@ -137,7 -142,7 +144,8 @@@ COBJS-$(CONFIG_CMD_NAND) += cmd_nand. COBJS-$(CONFIG_CMD_NET) += cmd_net.o COBJS-$(CONFIG_CMD_ONENAND) += cmd_onenand.o COBJS-$(CONFIG_CMD_OTP) += cmd_otp.o + COBJS-$(CONFIG_CMD_PART) += cmd_part.o +COBJS-$(CONFIG_CMD_PATA) += cmd_pata.o ifdef CONFIG_PCI COBJS-$(CONFIG_CMD_PCI) += cmd_pci.o endif diff --cc common/cmd_bootce.c index 78bed8da40,0000000000..1255feb291 mode 100644,000000..100644 --- a/common/cmd_bootce.c +++ b/common/cmd_bootce.c @@@ -1,1043 -1,0 +1,1027 @@@ +/* + * Copyright (C) 2012 Lothar Waßmann + * based on: code from RedBoot (C) Uwe Steinkohl + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ ++//#define DEBUG ++//#define TEST_LAUNCH ++//#define DDEBUG ++#ifdef DDEBUG ++#define _debug printf ++#else ++#define _debug debug ++#endif + +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define WINCE_VRAM_BASE 0x80000000 +#define CE_FIX_ADDRESS(a) ((void *)((a) - WINCE_VRAM_BASE + CONFIG_SYS_SDRAM_BASE)) + +#ifndef INT_MAX - #define INT_MAX ((1U << (sizeof(int) * 8 - 1)) - 1) ++#define INT_MAX ((int)(~0 >> 1)) +#endif + +/* Bin image parse states */ +#define CE_PS_RTI_ADDR 0 +#define CE_PS_RTI_LEN 1 +#define CE_PS_E_ADDR 2 +#define CE_PS_E_LEN 3 +#define CE_PS_E_CHKSUM 4 +#define CE_PS_E_DATA 5 + +#define CE_MIN(a, b) (((a) < (b)) ? (a) : (b)) +#define CE_MAX(a, b) (((a) > (b)) ? (a) : (b)) + +#define _STRMAC(s) #s +#define STRMAC(s) _STRMAC(s) + +static ce_bin __attribute__ ((aligned (32))) g_bin; +static ce_net __attribute__ ((aligned (32))) g_net; - - static inline void print_IPaddr(IPaddr_t ip) - { - printf("%d.%d.%d.%d", - ip & 0xff, - (ip >> 8) & 0xff, - (ip >> 16) & 0xff, - (ip >> 24) & 0xff); - } ++static IPaddr_t server_ip; + +static void ce_init_bin(ce_bin *bin, unsigned char *dataBuffer) +{ + memset(bin, 0, sizeof(*bin)); + ++debug("%s@%d: \n", __func__, __LINE__); + bin->data = dataBuffer; + bin->parseState = CE_PS_RTI_ADDR; + bin->parsePtr = (unsigned char *)bin; ++debug("%s@%d: \n", __func__, __LINE__); +} + +static int ce_is_bin_image(void *image, int imglen) +{ + if (imglen < CE_BIN_SIGN_LEN) { + return 0; + } + + return memcmp(image, CE_BIN_SIGN, CE_BIN_SIGN_LEN) == 0; +} + +static const struct ce_magic { + char magic[8]; + size_t size; + ce_std_driver_globals drv_glb; +} ce_magic_template = { + .magic = "KARO_CE6", + .size = sizeof(ce_std_driver_globals), + .drv_glb = { + .header = { + .signature = STD_DRV_GLB_SIGNATURE, + .oalVersion = 1, + .bspVersion = 2, + }, + }, +}; + +#ifdef DEBUG +static void __attribute__((unused)) ce_dump_block(void *ptr, int length) +{ + char *p = ptr; + int i; + int j; + + for (i = 0; i < length; i++) { + if (!(i % 16)) { + printf("\n%p: ", ptr + i); + } + + printf("%02x ", p[i]); + if (!((i + 1) % 16)){ + printf(" "); + for (j = i - 15; j <= i; j++){ + if((p[j] > 0x1f) && (p[j] < 0x7f)) { + printf("%c", p[j]); + } else { + printf("."); + } + } + } + } + printf("\n"); +} +#else +static inline void ce_dump_block(void *ptr, int length) +{ +} +#endif + - static void ce_setup_std_drv_globals(ce_std_driver_globals *std_drv_glb, - ce_bin *bin) ++static void ce_setup_std_drv_globals(ce_std_driver_globals *std_drv_glb) +{ + char *mtdparts = getenv("mtdparts"); + size_t max_len = ALIGN((unsigned long)std_drv_glb, SZ_4K) - + (unsigned long)&std_drv_glb->mtdparts; + + if (eth_get_dev()) { + memcpy(&std_drv_glb->kitl.mac, eth_get_dev()->enetaddr, + sizeof(std_drv_glb->kitl.mac)); + } + snprintf(std_drv_glb->deviceId, sizeof(std_drv_glb->deviceId), + "Triton%02X", eth_get_dev()->enetaddr[5]); + - std_drv_glb->kitl.ipAddress = gd->bd->bi_ip_addr; ++ NetCopyIP(&std_drv_glb->kitl.ipAddress, &NetOurIP); + std_drv_glb->kitl.ipMask = getenv_IPaddr("netmask"); + std_drv_glb->kitl.ipRoute = getenv_IPaddr("gatewayip"); + + if (mtdparts) { + strncpy(std_drv_glb->mtdparts, mtdparts, max_len); + std_drv_glb->mtdparts[max_len - 1] = '\0'; + } else { + printf("Failed to get mtdparts environment variable\n"); + } +} + +static void ce_prepare_run_bin(ce_bin *bin) +{ + ce_driver_globals *drv_glb; + struct ce_magic *ce_magic = (void *)CONFIG_SYS_SDRAM_BASE + 0x160; + ce_std_driver_globals *std_drv_glb = &ce_magic->drv_glb; + + /* Clear os RAM area (if needed) */ + if (bin->edbgConfig.flags & EDBG_FL_CLEANBOOT) { + debug("cleaning memory from %p to %p\n", + bin->eRamStart, bin->eRamStart + bin->eRamLen); + + printf("Preparing clean boot ... "); + memset(bin->eRamStart, 0, bin->eRamLen); + printf("ok\n"); + } + + /* Prepare driver globals (if needed) */ + if (bin->eDrvGlb) { + debug("Copying CE MAGIC from %p to %p..%p\n", + &ce_magic_template, ce_magic, + (void *)ce_magic + sizeof(*ce_magic) - 1); + memcpy(ce_magic, &ce_magic_template, sizeof(*ce_magic)); + - ce_setup_std_drv_globals(std_drv_glb, bin); ++ ce_setup_std_drv_globals(std_drv_glb); + ce_magic->size = sizeof(*std_drv_glb) + + strlen(std_drv_glb->mtdparts) + 1; + ce_dump_block(ce_magic, offsetof(struct ce_magic, drv_glb) + + ce_magic->size); + + drv_glb = bin->eDrvGlb; + memset(drv_glb, 0, sizeof(*drv_glb)); + + drv_glb->signature = DRV_GLB_SIGNATURE; + + /* Local ethernet MAC address */ + memcpy(drv_glb->macAddr, std_drv_glb->kitl.mac, + sizeof(drv_glb->macAddr)); + debug("got MAC address %02x:%02x:%02x:%02x:%02x:%02x from environment\n", + drv_glb->macAddr[0], drv_glb->macAddr[1], + drv_glb->macAddr[2], drv_glb->macAddr[3], + drv_glb->macAddr[4], drv_glb->macAddr[5]); + + /* Local IP address */ + drv_glb->ipAddr = getenv_IPaddr("ipaddr"); + + /* Subnet mask */ + drv_glb->ipMask = getenv_IPaddr("netmask"); + + /* Gateway config */ + drv_glb->ipGate = getenv_IPaddr("gatewayip"); +#ifdef DEBUG - debug("got IP address "); - print_IPaddr(drv_glb->ipAddr); - debug(" from environment\n"); - debug("got IP mask "); - print_IPaddr(drv_glb->ipMask); - debug(" from environment\n"); - debug("got gateway address "); - print_IPaddr(drv_glb->ipGate); - debug(" from environment\n"); ++ debug("got IP address %pI4 from environment\n", &drv_glb->ipAddr); ++ debug("got IP mask %pI4 from environment\n", &drv_glb->ipMask); ++ debug("got gateway address %pI4 from environment\n", &drv_glb->ipGate); +#endif + /* EDBG services config */ + memcpy(&drv_glb->edbgConfig, &bin->edbgConfig, + sizeof(bin->edbgConfig)); + } + + /* + * Make sure, all the above makes it into SDRAM because + * WinCE switches the cache & MMU off, obviously without + * flushing it first! + */ + flush_dcache_all(); +} + +static int ce_lookup_ep_bin(ce_bin *bin) +{ + ce_rom_hdr *header; + ce_toc_entry *tentry; + e32_rom *e32; + unsigned int i; + uint32_t *sig = (uint32_t *)(bin->rtiPhysAddr + ROM_SIGNATURE_OFFSET); + + debug("Looking for TOC signature at %p\n", sig); + + /* Check image Table Of Contents (TOC) signature */ + if (*sig != ROM_SIGNATURE) { + printf("Error: Did not find image TOC signature!\n"); + printf("Expected %08x at address %p; found %08x instead\n", + ROM_SIGNATURE, sig, *sig); + return 0; + } + + /* Lookup entry point */ + header = CE_FIX_ADDRESS(*(unsigned int *)(bin->rtiPhysAddr + + ROM_SIGNATURE_OFFSET + + sizeof(unsigned int))); + tentry = (ce_toc_entry *)(header + 1); + + for (i = 0; i < header->nummods; i++) { + // Look for 'nk.exe' module + if (strcmp(CE_FIX_ADDRESS(tentry[i].fileName), "nk.exe") == 0) { + // Save entry point and RAM addresses + + e32 = CE_FIX_ADDRESS(tentry[i].e32Offset); + + bin->eEntryPoint = CE_FIX_ADDRESS(tentry[i].loadOffset) + + e32->e32_entryrva; + bin->eRamStart = CE_FIX_ADDRESS(header->ramStart); + bin->eRamLen = header->ramEnd - header->ramStart; + // Save driver_globals address + // Must follow RAM section in CE config.bib file + // + // eg. + // + // RAM 80900000 03200000 RAM + // DRV_GLB 83B00000 00001000 RESERVED + // + bin->eDrvGlb = CE_FIX_ADDRESS(header->ramEnd); + return 1; + } + } + + // Error: Did not find 'nk.exe' module + return 0; +} + +static int ce_parse_bin(ce_bin *bin) +{ - unsigned char *pbData = bin->data; ++ unsigned char *pbData = g_net.data + 4;//bin->data; + int len = bin->dataLen; + int copyLen; + + debug("starting ce image parsing:\n\tbin->binLen: 0x%08X\n", bin->binLen); ++ debug("\tlen=%d\n", len); ++ debug("\tparse_state=%d\n", bin->parseState); + + if (len) { ++ ce_dump_block(pbData, len); ++#if 0 ++if (bin->binLen > 1024) ++ return CE_PR_EOF; ++#endif + if (bin->binLen == 0) { + // Check for the .BIN signature first + if (!ce_is_bin_image(pbData, len)) { + printf("Error: Invalid or corrupted .BIN image!\n"); + return CE_PR_ERROR; + } + + printf("Loading Windows CE .BIN image ...\n"); + // Skip signature + len -= CE_BIN_SIGN_LEN; + pbData += CE_BIN_SIGN_LEN; + } + + while (len) { + switch (bin->parseState) { + case CE_PS_RTI_ADDR: + case CE_PS_RTI_LEN: + case CE_PS_E_ADDR: + case CE_PS_E_LEN: + case CE_PS_E_CHKSUM: + copyLen = CE_MIN(sizeof(unsigned int) - bin->parseLen, len); + memcpy(&bin->parsePtr[bin->parseLen], pbData, copyLen); + + bin->parseLen += copyLen; + len -= copyLen; + pbData += copyLen; + + if (bin->parseLen == sizeof(unsigned int)) { + if (bin->parseState == CE_PS_RTI_ADDR) + bin->rtiPhysAddr = CE_FIX_ADDRESS(bin->rtiPhysAddr); + else if (bin->parseState == CE_PS_E_ADDR && + bin->ePhysAddr) + bin->ePhysAddr = CE_FIX_ADDRESS(bin->ePhysAddr); + + bin->parseState++; + bin->parseLen = 0; + bin->parsePtr += sizeof(unsigned int); + + if (bin->parseState == CE_PS_E_DATA) { + if (bin->ePhysAddr) { + bin->parsePtr = bin->ePhysAddr; + bin->parseChkSum = 0; + } else { + /* EOF */ + len = 0; + bin->endOfBin = 1; + } + } + } + break; + + case CE_PS_E_DATA: ++ debug("ePhysAddr=%p physlen=%08x parselen=%08x\n", ++ bin->ePhysAddr, bin->ePhysLen, bin->parseLen); + if (bin->ePhysAddr) { + copyLen = CE_MIN(bin->ePhysLen - bin->parseLen, len); + bin->parseLen += copyLen; + len -= copyLen; + + while (copyLen--) { + bin->parseChkSum += *pbData; + *bin->parsePtr++ = *pbData++; + } + + if (bin->parseLen == bin->ePhysLen) { + printf("Section [%02d]: address %p, size 0x%08X, checksum %s\n", + bin->section, + bin->ePhysAddr, + bin->ePhysLen, + (bin->eChkSum == bin->parseChkSum) ? "ok" : "fail"); + + if (bin->eChkSum != bin->parseChkSum) { + printf("Error: Checksum error, corrupted .BIN file!\n"); + printf("checksum calculated: 0x%08x from file: 0x%08x\n", + bin->parseChkSum, bin->eChkSum); + bin->binLen = 0; + return CE_PR_ERROR; + } + + bin->section++; + bin->parseState = CE_PS_E_ADDR; + bin->parseLen = 0; + bin->parsePtr = (unsigned char *)&bin->ePhysAddr; + } + } else { + bin->parseLen = 0; + bin->endOfBin = 1; + len = 0; + } + break; + } + } + } + + if (bin->endOfBin) { + if (!ce_lookup_ep_bin(bin)) { + printf("Error: entry point not found!\n"); + bin->binLen = 0; + return CE_PR_ERROR; + } + + printf("Entry point: %p, address range: %p-%p\n", + bin->eEntryPoint, + bin->rtiPhysAddr, + bin->rtiPhysAddr + bin->rtiPhysLen); + + return CE_PR_EOF; + } + + /* Need more data */ + bin->binLen += bin->dataLen; + return CE_PR_MORE; +} + +static int ce_bin_load(void *image, int imglen) +{ + ce_init_bin(&g_bin, image); + g_bin.dataLen = imglen; + if (ce_parse_bin(&g_bin) == CE_PR_EOF) { + ce_prepare_run_bin(&g_bin); + return 1; + } + + return 0; +} + +static void ce_run_bin(void (*entry)(void)) +{ + printf("Launching Windows CE ...\n"); ++#ifdef TEST_LAUNCH ++return; ++#endif + entry(); +} + +static int do_bootce(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + void *addr; + size_t image_size; + char *s; + + if (argc > 1) { + addr = (void *)simple_strtoul(argv[1], NULL, 16); + image_size = INT_MAX; /* actually we do not know the image size */ + } else if (getenv("fileaddr") != NULL) { + addr = (void *)getenv_ulong("fileaddr", 16, 0); + image_size = getenv_ulong("filesize", 16, INT_MAX); + } else { + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + } + + printf ("## Booting Windows CE Image from address %p ...\n", addr); + + /* check if there is a valid windows CE image */ + if (ce_is_bin_image(addr, image_size)) { + if (!ce_bin_load(addr, image_size)) { + /* Ops! Corrupted .BIN image! */ + /* Handle error here ... */ + printf("corrupted .BIN image !!!\n"); + return 1; + } + if ((s = getenv("autostart")) != NULL) { + if (*s != 'y') { + /* + * just use bootce to load the image to SDRAM; + * Do not start it automatically. + */ + setenv_addr("fileaddr", + g_bin.eEntryPoint); + return 0; + } + } + ce_run_bin(g_bin.eEntryPoint); /* start the image */ + } else { + printf("Image does not seem to be a valid Windows CE image!\n"); + return 1; + } + return 1; /* never reached - just to keep compiler happy */ +} + +U_BOOT_CMD( + bootce, 2, 0, do_bootce, + "bootce\t- Boot a Windows CE image from memory \n", + "[args..]\n" + "\taddr\t\t-boot image from address addr\n" +); + - static void wince_handler(uchar *pkt, unsigned dport, IPaddr_t sip, - unsigned sport, unsigned len) - { - void *eth_pkt = pkt - IP_HDR_SIZE - ETHER_HDR_SIZE; - unsigned eth_len = len + IP_HDR_SIZE + ETHER_HDR_SIZE; - - NetState = NETLOOP_SUCCESS; /* got input - quit net loop */ - - if (memcmp(eth_pkt, eth_get_dev()->enetaddr, ETH_ALEN) != 0) { - g_net.got_packet_4me = 0; - return; - } - memcpy(&g_net.data[g_net.align_offset], - eth_pkt, eth_len); - - g_net.dataLen = len; - g_net.got_packet_4me = 1; - - g_net.srvAddrRecv.sin_port = *((unsigned short *)(&g_net.data[ - ETHER_HDR_SIZE + IP_HDR_SIZE_NO_UDP + g_net.align_offset])); - NetCopyIP(&g_net.srvAddrRecv.sin_addr, &g_net.data[ETHER_HDR_SIZE + - g_net.align_offset + 12]); - memcpy(NetServerEther, &g_net.data[g_net.align_offset + 6], ETH_ALEN); - #if 0 - printf("received packet: buffer %p Laenge %d \n", pkt, len); - printf("from "); - print_IPaddr(g_net.srvAddrRecv.sin_addr); - printf(", port: %d\n", ntohs(g_net.srvAddrRecv.sin_port)); - - ce_dump_block(pkt, len); - - printf("Headers:\n"); - ce_dump_block(eth_pkt, ETHER_HDR_SIZE + IP_HDR_SIZE); - printf("my port should be: %d\n", - ntohs(*((unsigned short *)(&g_net.data[ETHER_HDR_SIZE + - IP_HDR_SIZE_NO_UDP + - g_net.align_offset + 2])))); - #endif - } - - /* returns packet length if successfull */ - static int ce_recv_packet(uchar *buf, int len, struct sockaddr_in *from, - struct sockaddr_in *local, struct timeval *timeout) - { - int rxlength; - ulong time_started; - - g_net.got_packet_4me = 0; - time_started = get_timer(0); - NetSetHandler(wince_handler); - - while (1) { - rxlength = eth_rx(); - if (g_net.got_packet_4me) - return g_net.dataLen; - /* check for timeout */ - if (get_timer(time_started) > timeout->tv_sec * CONFIG_SYS_HZ) { - return -ETIMEDOUT; - } - } - } - - static int ce_recv_frame(ce_net *net, int timeout) - { - struct timeval timeo; - - timeo.tv_sec = timeout; - timeo.tv_usec = 0; - - net->dataLen = ce_recv_packet(&net->data[net->align_offset], - sizeof(net->data) - net->align_offset, - &net->srvAddrRecv, &net->locAddr, &timeo); - - if (net->dataLen < 0 || net->dataLen > sizeof(net->data)) { - /* Error! No data available */ - net->dataLen = 0; - } - - return net->dataLen; - } - - static int ce_send_frame(ce_net *net) - { - uchar *pkt = (uchar *)NetTxPacket + ETHER_HDR_SIZE + IP_HDR_SIZE; - - memcpy(pkt, &net->data[net->align_offset + ETHER_HDR_SIZE + IP_HDR_SIZE], - net->dataLen); - return NetSendUDPPacket(NetServerEther, net->srvAddrSend.sin_addr, - ntohs(net->srvAddrSend.sin_port), - ntohs(net->locAddr.sin_port), net->dataLen); - } - +static int ce_send_write_ack(ce_net *net) +{ - unsigned short *wdata; - unsigned long aligned_address; - - aligned_address = (unsigned long)&net->data[ETHER_HDR_SIZE + IP_HDR_SIZE + net->align_offset]; ++ int ret; ++ unsigned short wdata[2]; ++ int retries = 0; + - wdata = (unsigned short *)aligned_address; + wdata[0] = htons(EDBG_CMD_WRITE_ACK); + wdata[1] = htons(net->blockNum); - - net->dataLen = 4; - - return ce_send_frame(net); ++ net->dataLen = sizeof(wdata); ++ memcpy(net->data, wdata, net->dataLen); ++ ++ do { ++ ret = bootme_send_frame(net->data, net->dataLen); ++ if (ret) { ++ printf("Failed to send write ack %d; retries=%d\n", ++ ret, retries); ++ } ++debug("*"); ++ } while (ret != 0 && retries-- > 0); ++ return ret; +} + - static int ce_process_download(ce_net *net, ce_bin *bin) ++static enum bootme_state ce_process_download(ce_net *net, ce_bin *bin) +{ - int ret = CE_PR_MORE; ++ int ret = net->state; + - if (net->dataLen >= 2) { ++ if (net->dataLen >= 4) { + unsigned short command; ++ unsigned short blknum; + - command = ntohs(*(unsigned short *)&net->data[CE_DOFFSET]); ++ memcpy(&command, net->data, sizeof(command)); ++ command = ntohs(command); + debug("command found: 0x%04X\n", command); + ++ if (net->state == BOOTME_DOWNLOAD) { ++ unsigned short nxt = net->blockNum + 1; ++ ++ memcpy(&blknum, &net->data[2], sizeof(blknum)); ++ blknum = ntohs(blknum); ++ if (blknum == nxt) { ++ net->blockNum = blknum; ++debug("#"); ++ } else { ++ int rc = ce_send_write_ack(net); ++ ++ printf("Dropping out of sequence packet with ID %d (expected %d)\n", ++ blknum, nxt); ++ if (rc != 0) ++ return rc; ++ ++ return ret; ++ } ++ } ++ + switch (command) { + case EDBG_CMD_WRITE_REQ: - if (!net->link) { ++ if (net->state == BOOTME_INIT) { + // Check file name for WRITE request + // CE EShell uses "boot.bin" file name +#if 0 + printf(">>>>>>>> First Frame, IP: %s, port: %d\n", + inet_ntoa((in_addr_t *)&net->srvAddrRecv), + ntohs(net->srvAddrRecv.sin_port)); +#endif - if (strncmp((char *)&net->data[CE_DOFFSET + 2], ++ if (strncmp((char *)&net->data[2], + "boot.bin", 8) == 0) { + // Some diag output + if (net->verbose) { - printf("Locked Down download link, IP: "); - print_IPaddr(net->srvAddrRecv.sin_addr); - printf(", port: %d\n", ntohs(net->srvAddrRecv.sin_port)); - - printf("Sending BOOTME request [%d] to ", - net->seqNum); - print_IPaddr(net->srvAddrSend.sin_addr); - printf("\n"); ++ printf("Locked Down download link, IP: %pI4\n", ++ &NetServerIP); ++ printf("Sending BOOTME request [%d] to %pI4\n", ++ net->seqNum, &NetServerIP); + } + + // Lock down EShell download link - net->locAddr.sin_port = htons(EDBG_DOWNLOAD_PORT + 1); - net->srvAddrSend.sin_port = net->srvAddrRecv.sin_port; - net->srvAddrSend.sin_addr = net->srvAddrRecv.sin_addr; - net->link = 1; ++// net->link = 1; ++ ret = BOOTME_DOWNLOAD; + } else { + // Unknown link - net->srvAddrRecv.sin_port = 0; ++ printf("Unknown link\n"); + } + - if (net->link) { - ce_send_write_ack(net); ++ if (ret == BOOTME_DOWNLOAD) { ++ int rc = ce_send_write_ack(net); ++ if (rc != 0) ++ return rc; + } + } + break; + + case EDBG_CMD_WRITE: - /* Fix data len */ ++ /* Fixup data len */ + bin->dataLen = net->dataLen - 4; - + ret = ce_parse_bin(bin); + if (ret != CE_PR_ERROR) { - net->blockNum++; - ce_send_write_ack(net); ++ int rc = ce_send_write_ack(net); ++ if (rc) ++ return rc; ++ if (ret == CE_PR_EOF) ++ ret = BOOTME_DONE; ++ } else { ++ ret = BOOTME_ERROR; + } + break; + + case EDBG_CMD_READ_REQ: ++ printf("Ignoring EDBG_CMD_READ_REQ\n"); + /* Read requests are not supported + * Do nothing ... + */ + break; + + case EDBG_CMD_ERROR: + printf("Error: unknown error on the host side\n"); + + bin->binLen = 0; - ret = CE_PR_ERROR; ++ ret = BOOTME_ERROR; + break; + + default: + printf("unknown command 0x%04X\n", command); - return -EINVAL; ++ net->state = BOOTME_ERROR; + } + } + return ret; +} + - static void ce_init_edbg_link(ce_net *net) - { - /* Initialize EDBG link for commands */ - - net->locAddr.sin_port = htons(EDBG_DOWNLOAD_PORT); - net->srvAddrSend.sin_port = htons(EDBG_DOWNLOAD_PORT); - net->srvAddrRecv.sin_port = 0; - net->link = 0; - } - - static void ce_process_edbg(ce_net *net, ce_bin *bin) ++static enum bootme_state ce_process_edbg(ce_net *net, ce_bin *bin) +{ - eth_dbg_hdr *header; ++ enum bootme_state ret = net->state; ++ eth_dbg_hdr header; + - if (net->dataLen < sizeof(eth_dbg_hdr)) { ++debug("%s: received packet of %u byte @ %p\n", __func__, net->dataLen, net->data); ++ if (net->dataLen < sizeof(header)) { + /* Bad packet */ - - net->srvAddrRecv.sin_port = 0; - return; ++ printf("Invalid packet size %u\n", net->dataLen); ++ net->dataLen = 0; ++ return ret; + } - - header = (eth_dbg_hdr *)&net->data[net->align_offset + ETHER_HDR_SIZE + IP_HDR_SIZE]; - - if (header->id != EDBG_ID) { ++debug("%s@%d: Copying header from %p..%p to %p\n", __func__, __LINE__, ++ net->data, net->data + sizeof(header) - 1, &header); ++ memcpy(&header, net->data, sizeof(header)); ++ if (header.id != EDBG_ID) { + /* Bad packet */ - - net->srvAddrRecv.sin_port = 0; - return; ++ printf("Bad EDBG ID %08x\n", header.id); ++ net->dataLen = 0; ++ return ret; + } + - if (header->service != EDBG_SVC_ADMIN) { ++debug("%s@%d\n", __func__, __LINE__); ++ if (header.service != EDBG_SVC_ADMIN) { + /* Unknown service */ - return; ++ printf("Bad EDBG service %02x\n", header.service); ++ net->dataLen = 0; ++ return ret; + } + - if (!net->link) { ++debug("%s@%d\n", __func__, __LINE__); ++ if (net->state == BOOTME_INIT) { + /* Some diag output */ + if (net->verbose) { - printf("Locked Down EDBG service link, IP: "); - print_IPaddr(net->srvAddrRecv.sin_addr); - printf(", port: %d\n", ntohs(net->srvAddrRecv.sin_port)); ++ printf("Locked Down EDBG service link, IP: %pI4\n", ++ &NetServerIP); + } + + /* Lock down EDBG link */ - net->srvAddrSend.sin_port = net->srvAddrRecv.sin_port; - net->link = 1; ++// net->link = 1; ++ net->state = BOOTME_DEBUG; + } + - switch (header->cmd) { ++debug("%s@%d\n", __func__, __LINE__); ++ switch (header.cmd) { + case EDBG_CMD_JUMPIMG: ++debug("%s@%d\n", __func__, __LINE__); + net->gotJumpingRequest = 1; + + if (net->verbose) { + printf("Received JUMPING command\n"); + } + /* Just pass through and copy CONFIG structure */ + case EDBG_CMD_OS_CONFIG: ++debug("%s@%d\n", __func__, __LINE__); + /* Copy config structure */ - memcpy(&bin->edbgConfig, header->data, ++ memcpy(&bin->edbgConfig, header.data, + sizeof(edbg_os_config_data)); + if (net->verbose) { + printf("Received CONFIG command\n"); + if (bin->edbgConfig.flags & EDBG_FL_DBGMSG) { + printf("--> Enabling DBGMSG service, IP: %d.%d.%d.%d, port: %d\n", + (bin->edbgConfig.dbgMsgIPAddr >> 0) & 0xFF, + (bin->edbgConfig.dbgMsgIPAddr >> 8) & 0xFF, + (bin->edbgConfig.dbgMsgIPAddr >> 16) & 0xFF, + (bin->edbgConfig.dbgMsgIPAddr >> 24) & 0xFF, + ntohs(bin->edbgConfig.dbgMsgPort)); + } + + if (bin->edbgConfig.flags & EDBG_FL_PPSH) { + printf("--> Enabling PPSH service, IP: %d.%d.%d.%d, port: %d\n", + (bin->edbgConfig.ppshIPAddr >> 0) & 0xFF, + (bin->edbgConfig.ppshIPAddr >> 8) & 0xFF, + (bin->edbgConfig.ppshIPAddr >> 16) & 0xFF, + (bin->edbgConfig.ppshIPAddr >> 24) & 0xFF, + ntohs(bin->edbgConfig.ppshPort)); + } + + if (bin->edbgConfig.flags & EDBG_FL_KDBG) { + printf("--> Enabling KDBG service, IP: %d.%d.%d.%d, port: %d\n", + (bin->edbgConfig.kdbgIPAddr >> 0) & 0xFF, + (bin->edbgConfig.kdbgIPAddr >> 8) & 0xFF, + (bin->edbgConfig.kdbgIPAddr >> 16) & 0xFF, + (bin->edbgConfig.kdbgIPAddr >> 24) & 0xFF, + ntohs(bin->edbgConfig.kdbgPort)); + } + + if (bin->edbgConfig.flags & EDBG_FL_CLEANBOOT) { + printf("--> Force clean boot\n"); + } + } ++ ret = BOOTME_DEBUG; + break; + + default: + if (net->verbose) { - printf("Received unknown command: %08X\n", header->cmd); ++ printf("Received unknown command: %08X\n", header.cmd); + } - return; ++ return BOOTME_ERROR; + } + + /* Respond with ack */ - header->flags = EDBG_FL_FROM_DEV | EDBG_FL_ACK; ++ header.flags = EDBG_FL_FROM_DEV | EDBG_FL_ACK; + net->dataLen = EDBG_DATA_OFFSET; - ce_send_frame(net); ++debug("%s@%d: sending packet %p len %u\n", __func__, __LINE__, ++ net->data, net->dataLen); ++ bootme_send_frame(net->data, net->dataLen); ++ return ret; ++} ++ ++static enum bootme_state ce_edbg_handler(const void *buf, size_t len) ++{ ++ enum bootme_state ret; ++ ++ if (len == 0) { ++ _debug("%s: EOF\n", __func__); ++ return BOOTME_DONE; ++ } ++#if 0 ++ if (len > sizeof(g_net.data)) { ++ debug("Dropping oversized packet of %u bytes (max. size %u)\n", ++ len, sizeof(g_net.data)); ++ return g_net.state; ++ } ++ debug("Copying network packet of %u bytes from %p to %p\n", ++ len, buf, g_net.data); ++ memcpy(g_net.data, buf, len); ++ g_net.dataLen = len; ++#else ++ g_net.data = (void *)buf; ++ g_net.dataLen = len; ++#endif ++ ret = ce_process_edbg(&g_net, &g_bin); ++ return ret; ++} ++ ++static void ce_init_edbg_link(ce_net *net) ++{ ++ /* Initialize EDBG link for commands */ ++ net->state = BOOTME_INIT; ++} ++ ++static enum bootme_state ce_download_handler(const void *buf, size_t len) ++{ ++#if 0 ++ if (len > sizeof(g_net.data)) { ++ debug("Dropping oversized packet of %u bytes (max. size %u)\n", ++ len, sizeof(g_net.data)); ++ return g_net.state; ++ } ++ debug("Copying network packet of %u bytes from %p to %p\n", ++ len, buf, g_net.data); ++ memcpy(g_net.data, buf, len); ++ g_net.dataLen = len; ++#else ++ g_net.data = (void *)buf; ++ g_net.dataLen = len; ++#endif ++ g_net.state = ce_process_download(&g_net, &g_bin); ++ return g_net.state; +} + +static int ce_send_bootme(ce_net *net) +{ + eth_dbg_hdr *header; + edbg_bootme_data *data; - #ifdef DEBUG ++ unsigned char txbuf[PKTSIZE_ALIGN]; ++#ifdef DEBUG_ + int i; + unsigned char *pkt; +#endif + /* Fill out BOOTME packet */ ++net->data = txbuf; ++assert(net->data != NULL); + memset(net->data, 0, PKTSIZE); - header = (eth_dbg_hdr *)&net->data[CE_DOFFSET]; ++ header = (eth_dbg_hdr *)net->data; + data = (edbg_bootme_data *)header->data; + + header->id = EDBG_ID; + header->service = EDBG_SVC_ADMIN; + header->flags = EDBG_FL_FROM_DEV; + header->seqNum = net->seqNum++; + header->cmd = EDBG_CMD_BOOTME; + + data->versionMajor = 0; + data->versionMinor = 0; + data->cpuId = EDBG_CPU_TYPE_ARM; + data->bootmeVer = EDBG_CURRENT_BOOTME_VERSION; + data->bootFlags = 0; + data->downloadPort = 0; + data->svcPort = 0; + + /* MAC address from environment*/ + if (!eth_getenv_enetaddr("ethaddr", data->macAddr)) { + printf("'ethaddr' is not set or invalid\n"); + memset(data->macAddr, 0, sizeof(data->macAddr)); + } + - /* IP address from environment */ - data->ipAddr = getenv_IPaddr("ipaddr"); ++ /* IP address from active config */ ++ NetCopyIP(&data->ipAddr, &NetOurIP); + + // Device name string (NULL terminated). Should include + // platform and number based on Ether address (e.g. Odo42, CEPCLS2346, etc) + + // We will use lower MAC address segment to create device name + // eg. MAC '00-0C-C6-69-09-05', device name 'Triton05' + + strncpy(data->platformId, "Triton", sizeof(data->platformId)); + snprintf(data->deviceName, sizeof(data->deviceName), "%s%02X", + data->platformId, data->macAddr[5]); + - #ifdef DEBUG ++#ifdef DEBUG_ + printf("header->id: %08X\r\n", header->id); + printf("header->service: %08X\r\n", header->service); + printf("header->flags: %08X\r\n", header->flags); + printf("header->seqNum: %08X\r\n", header->seqNum); + printf("header->cmd: %08X\r\n\r\n", header->cmd); + + printf("data->versionMajor: %08X\r\n", data->versionMajor); + printf("data->versionMinor: %08X\r\n", data->versionMinor); + printf("data->cpuId: %08X\r\n", data->cpuId); + printf("data->bootmeVer: %08X\r\n", data->bootmeVer); + printf("data->bootFlags: %08X\r\n", data->bootFlags); + printf("data->svcPort: %08X\r\n\r\n", ntohs(data->svcPort)); + + printf("data->macAddr: %02X-%02X-%02X-%02X-%02X-%02X\r\n", + data->macAddr[0], data->macAddr[1], + data->macAddr[2], data->macAddr[3], + data->macAddr[4], data->macAddr[5]); + + printf("data->ipAddr: %d.%d.%d.%d\r\n", + (data->ipAddr >> 0) & 0xFF, + (data->ipAddr >> 8) & 0xFF, + (data->ipAddr >> 16) & 0xFF, + (data->ipAddr >> 24) & 0xFF); + + printf("data->platformId: %s\r\n", data->platformId); + + printf("data->deviceName: %s\r\n", data->deviceName); +#endif + // Some diag output ... + if (net->verbose) { - printf("Sending BOOTME request [%d] to ", net->seqNum); - print_IPaddr(net->srvAddrSend.sin_addr); - printf("\n"); ++ printf("Sending BOOTME request [%d] to %pI4\n", net->seqNum, ++ &server_ip); + } + + net->dataLen = BOOTME_PKT_SIZE; - #ifdef DEBUG ++// net->status = CE_PR_MORE; ++ net->state = BOOTME_INIT; ++#ifdef DEBUG_ + debug("Start of buffer: %p\n", net->data); - debug("Start of ethernet buffer: %p\n", &net->data[net->align_offset]); ++ debug("Start of ethernet buffer: %p\n", net->data); + debug("Start of CE header: %p\n", header); + debug("Start of CE data: %p\n", data); + - pkt = &net->data[net->align_offset]; ++ pkt = net->data; + debug("packet to send (ceconnect): \n"); - for (i = 0; i < net->dataLen + ETHER_HDR_SIZE + IP_HDR_SIZE; i++) { ++ for (i = 0; i < net->dataLen; i++) { + debug("0x%02X ", pkt[i]); + if (!((i + 1) % 16)) + debug("\n"); + } + debug("\n"); +#endif - memcpy(NetServerEther, NetBcastAddr, 6); - return ce_send_frame(net); ++ return BootMeRequest(server_ip, net->data, net->dataLen, 1); +} + - static int ce_init_download_link(ce_net *net, ce_bin *bin, - struct sockaddr_in *host_addr, int verbose) ++static inline int ce_init_download_link(ce_net *net, ce_bin *bin, int verbose) +{ - int ret; - unsigned long aligned_address; - + if (!eth_get_dev()) { + printf("No network interface available\n"); + return -ENODEV; + } - printf("Usinge device '%s'\n", eth_get_name()); ++ printf("Using device '%s'\n", eth_get_name()); + + /* Initialize EDBG link for download */ + memset(net, 0, sizeof(*net)); + - /* our buffer contains space for ethernet- ip- and udp- headers */ - /* calculate an offset so that our ce field is aligned to 4 bytes */ - aligned_address = (unsigned long)net->data; - /* we need 42 bytes room for headers (14 Ethernet , 20 IPv4, 8 UDP) */ - aligned_address += ETHER_HDR_SIZE + IP_HDR_SIZE; - /* want CE header aligned to 4 Byte boundary */ - net->align_offset = (4 - (aligned_address % 4)) % 4; ++ net->verbose = verbose; + - net->locAddr.sin_family = AF_INET; - net->locAddr.sin_addr = getenv_IPaddr("ipaddr"); - net->locAddr.sin_port = htons(EDBG_DOWNLOAD_PORT); ++ ce_init_bin(bin, NULL);//&net->data[4]); ++ return 0; ++} + - net->srvAddrSend.sin_family = AF_INET; - net->srvAddrSend.sin_port = htons(EDBG_DOWNLOAD_PORT); ++#define UINT_MAX ~0UL + - net->srvAddrRecv.sin_family = AF_INET; - net->srvAddrRecv.sin_port = 0; ++static inline int ce_download_file(ce_net *net, ulong timeout) ++{ ++ ulong start = get_timer_masked(); + - if (host_addr->sin_addr) { - /* Use specified host address ... */ - net->srvAddrSend.sin_addr = host_addr->sin_addr; - net->srvAddrRecv.sin_addr = host_addr->sin_addr; - } else { - /* ... or default server address */ - net->srvAddrSend.sin_addr = getenv_IPaddr("serverip"); - net->srvAddrRecv.sin_addr = getenv_IPaddr("serverip"); - } ++ while (net->state == BOOTME_INIT) { ++ int ret; + - net->verbose = verbose; ++ if (timeout && get_timer(start) > timeout) { ++ printf("CELOAD - Canceled, timeout\n"); ++ return 1; ++ } + - ce_init_bin(bin, &net->data[CE_DOFFSET + 4]); ++ if (ctrlc()) { ++ printf("CELOAD - canceled by user\n"); ++ return 1; ++ } + - eth_halt(); ++ if (ce_send_bootme(&g_net)) { ++ printf("CELOAD - error while sending BOOTME request\n"); ++ return 1; ++ } ++ if (net->verbose) { ++ if (timeout) { ++ printf("Waiting for connection, timeout %lu sec\n", ++ DIV_ROUND_UP(timeout - get_timer(start), ++ CONFIG_SYS_HZ)); ++ } else { ++ printf("Waiting for connection, enter ^C to abort\n"); ++ } ++ } + - #ifdef CONFIG_NET_MULTI - eth_set_current(); - #endif - ret = eth_init(gd->bd); - if (ret < 0) { - printf("ceconnect: failed to init ethernet: %d\n", ret); - eth_halt(); - return ret; ++ ret = BootMeDownload(ce_download_handler); ++ printf("BootMeDownload() returned %d\n", ret); ++ if (ret == BOOTME_ERROR) { ++ printf("CELOAD - aborted\n"); ++ return 1; ++ } + } - #ifdef ET_DEBUG - puts("ceconnect: init ethernet done!\n"); - #endif - memcpy(NetOurEther, eth_get_dev()->enetaddr, ETH_ALEN); - NetCopyIP(&NetOurIP, &gd->bd->bi_ip_addr); - NetOurGatewayIP = getenv_IPaddr("gatewayip"); - NetOurSubnetMask = getenv_IPaddr("netmask"); - NetServerIP = getenv_IPaddr("serverip"); + return 0; +} + - static int do_ceconnect(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) ++static void ce_disconnect(void) +{ ++ net_set_udp_handler(NULL); ++ eth_halt(); ++} ++ ++static int do_ceconnect(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) ++{ ++ int verbose = 0; ++ ulong timeout = 0; ++ int ret = 1; + int i; - int verbose = 0, use_timeout = 0; - int timeout = 0, recv_timeout, ret; - struct sockaddr_in host_ip_addr; ++ ++ server_ip = 0; + + for (i = 1; i < argc; i++){ + if (*argv[i] != '-') + break; + if (argv[i][1] == 'v') { + verbose = 1; + } else if (argv[i][1] == 't') { + i++; + if (argc > i) { + timeout = simple_strtoul(argv[i], + NULL, 10); - use_timeout = 1; ++ if (timeout >= UINT_MAX / CONFIG_SYS_HZ) { ++ printf("Timeout value %lu out of range (max.: %lu)\n", ++ timeout, UINT_MAX / CONFIG_SYS_HZ - 1); ++ return 1; ++ } ++ timeout *= CONFIG_SYS_HZ; + } else { + printf("Option requires an argument - t\n"); + return 1; + } - } - } - - memset(&host_ip_addr, 0xff, sizeof(host_ip_addr)); - - if (ce_init_download_link(&g_net, &g_bin, &host_ip_addr, verbose) != 0) - return 1; - - while (1) { - if (g_net.link) { - recv_timeout = 3; - } else { - recv_timeout = 1; - - if (use_timeout && timeout <= 0) { - printf("CELOAD - Canceled, timeout\n"); - eth_halt(); - return 1; - } - if (ctrlc()) { - printf("CELOAD - canceled by user\n"); - eth_halt(); - return 1; - } - - debug("sending broadcast frame bootme\n"); - - if (ce_send_bootme(&g_net)) { - printf("CELOAD - error while sending BOOTME request\n"); - eth_halt(); ++ } else if (argv[i][1] == 'h') { ++ i++; ++ if (argc > i) { ++ server_ip = string_to_ip(argv[i]); ++ printf("Using server %pI4\n", &server_ip); ++ } else { ++ printf("Option requires an argument - t\n"); + return 1; + } - debug("net state is: %d\n", NetState); - if (verbose) { - if (use_timeout) { - printf("Waiting for connection, timeout %d sec\n", timeout); - } else { - printf("Waiting for connection, enter ^C to abort\n"); - } - } - } - - if (ce_recv_frame(&g_net, recv_timeout)) { - ret = ce_process_download(&g_net, &g_bin); - if (ret != CE_PR_MORE) - break; - } else if (use_timeout) { - timeout -= recv_timeout; + } + } ++#ifndef TEST_LAUNCH ++ if (ce_init_download_link(&g_net, &g_bin, verbose) != 0) ++ goto err; + ++ if (ce_download_file(&g_net, timeout)) ++ goto err; ++#else ++g_bin.binLen = 1; ++#endif + if (g_bin.binLen) { + // Try to receive edbg commands from host ++_debug("%s@%d: \n", __func__, __LINE__); + ce_init_edbg_link(&g_net); ++_debug("%s@%d: \n", __func__, __LINE__); + if (verbose) + printf("Waiting for EDBG commands ...\n"); + - while (ce_recv_frame(&g_net, 3)) - ce_process_edbg(&g_net, &g_bin); ++_debug("%s@%d: \n", __func__, __LINE__); ++ ret = BootMeDebugStart(ce_edbg_handler); ++_debug("%s@%d: ret=%d\n", __func__, __LINE__, ret); ++ if (ret != BOOTME_DONE) ++ goto err; ++_debug("%s@%d: \n", __func__, __LINE__); + + // Prepare WinCE image for execution + ce_prepare_run_bin(&g_bin); ++_debug("%s@%d: \n", __func__, __LINE__); + + // Launch WinCE, if necessary + if (g_net.gotJumpingRequest) + ce_run_bin(g_bin.eEntryPoint); ++_debug("%s@%d: \n", __func__, __LINE__); + } - eth_halt(); - return 0; ++ ret = 0; ++err: ++ ce_disconnect(); ++ return ret; +} + +U_BOOT_CMD( + ceconnect, 4, 1, do_ceconnect, + "ceconnect - Set up a connection to the CE host PC over TCP/IP and download the run-time image\n", + "ceconnect [-v] [-t ]\n" + " -v verbose operation\n" + " -t - max wait time (#sec) for the connection\n" +); diff --cc common/cmd_fdt.c index aa7707ca46,9e2de34737..6088baf64f --- a/common/cmd_fdt.c +++ b/common/cmd_fdt.c @@@ -824,6 -989,11 +989,11 @@@ static char fdt_help_text[] "fdt rsvmem delete - Delete a mem reserves\n" "fdt chosen [ ] - Add/update the /chosen branch in the tree\n" " / - initrd start/end addr\n" - "NOTE: Dereference aliases by omiting the leading '/', " + "NOTE: Dereference aliases by omitting the leading '/', " - "e.g. fdt print ethernet0." + "e.g. fdt print ethernet0."; + #endif + + U_BOOT_CMD( + fdt, 255, 0, do_fdt, + "flattened device tree utility commands", fdt_help_text ); diff --cc common/cmd_nand.c index a461e64eac,1568594ca4..b6b22a9d3f --- a/common/cmd_nand.c +++ b/common/cmd_nand.c @@@ -578,13 -617,36 +618,38 @@@ static int do_nand(cmd_tbl_t *cmdtp, in read = strncmp(cmd, "read", 4) == 0; /* 1 = read, 0 = write */ printf("\nNAND %s: ", read ? "read" : "write"); + if (arg_off_size(argc - 3, argv + 3, &dev, &off, &size) != 0) + return CMD_RET_FAILURE; nand = &nand_info[dev]; - rwsize = size; s = strchr(cmd, '.'); + + if (s && !strcmp(s, ".raw")) { + raw = 1; + + if (arg_off(argv[3], &dev, &off, &size)) + return 1; + + if (argc > 4 && !str2long(argv[4], &pagecount)) { + printf("'%s' is not a number\n", argv[4]); + return 1; + } + + if (pagecount * nand->writesize > size) { + puts("Size exceeds partition or device limit\n"); + return -1; + } + + rwsize = pagecount * (nand->writesize + nand->oobsize); + } else { + if (arg_off_size(argc - 3, argv + 3, &dev, + &off, &size) != 0) + return 1; + + rwsize = size; + } + if (!s || !strcmp(s, ".jffs2") || !strcmp(s, ".e") || !strcmp(s, ".i")) { if (read) @@@ -607,10 -669,11 +672,11 @@@ } else if (!strcmp(s, ".yaffs")) { if (read) { printf("Unknown nand command suffix '%s'.\n", s); - return 1; + return CMD_RET_FAILURE; } ret = nand_write_skip_bad(nand, off, &rwsize, - (u_char *)addr, WITH_YAFFS_OOB); + (u_char *)addr, + WITH_INLINE_OOB); #endif } else if (!strcmp(s, ".oob")) { /* out-of-band data */ @@@ -624,33 -687,38 +690,38 @@@ ret = nand->read_oob(nand, off, &ops); else ret = nand->write_oob(nand, off, &ops); - } else if (!strcmp(s, ".raw")) { - /* Raw access */ - mtd_oob_ops_t ops = { - .datbuf = (u8 *)addr, - .oobbuf = ((u8 *)addr) + nand->writesize, - .len = nand->writesize, - .ooblen = nand->oobsize, - .mode = MTD_OOB_RAW - }; - - rwsize = nand->writesize + nand->oobsize; - - if (read) - ret = nand->read_oob(nand, off, &ops); - else - ret = nand->write_oob(nand, off, &ops); + } else if (raw) { + ret = raw_access(nand, addr, off, pagecount, read); } else { printf("Unknown nand command suffix '%s'.\n", s); - return 1; + return CMD_RET_FAILURE; } printf(" %zu bytes %s: %s\n", rwsize, read ? "read" : "written", ret ? "ERROR" : "OK"); - return ret == 0 ? 0 : 1; + return ret == 0 ? CMD_RET_SUCCESS : CMD_RET_FAILURE; } + #ifdef CONFIG_CMD_NAND_TORTURE + if (strcmp(cmd, "torture") == 0) { + if (argc < 3) + goto usage; + + if (!str2off(argv[2], &off)) { + puts("Offset is not a valid number\n"); + return 1; + } + + printf("\nNAND torture: device %d offset 0x%llx size 0x%x\n", + dev, off, nand->erasesize); + ret = nand_torture(nand, off); + printf(" %s\n", ret ? "Failed" : "Passed"); + + return ret == 0 ? 0 : 1; + } + #endif + if (strcmp(cmd, "markbad") == 0) { argc -= 2; argv += 2; @@@ -699,17 -767,24 +770,24 @@@ puts("NAND flash successfully locked\n"); } else { puts("Error locking NAND flash\n"); - return 1; + return CMD_RET_FAILURE; } } - return 0; + return CMD_RET_SUCCESS; } - if (strcmp(cmd, "unlock") == 0) { + if (strncmp(cmd, "unlock", 5) == 0) { + int allexcept = 0; + + s = strchr(cmd, '.'); + + if (s && !strcmp(s, ".allexcept")) + allexcept = 1; + if (arg_off_size(argc - 2, argv + 2, &dev, &off, &size) < 0) - return 1; + return CMD_RET_FAILURE; - if (!nand_unlock(&nand_info[dev], off, size)) { + if (!nand_unlock(&nand_info[dev], off, size, allexcept)) { puts("NAND flash successfully unlocked\n"); } else { puts("Error unlocking NAND flash, " diff --cc common/fdt_support.c index 593f16c162,6b9fa0550f..2cd5a51e70 --- a/common/fdt_support.c +++ b/common/fdt_support.c @@@ -1090,7 -1088,7 +1088,7 @@@ u64 __of_translate_address(void *blob, goto bail; bus = &of_busses[0]; -- /* Cound address cells & copy address locally */ ++ /* Count address cells & copy address locally */ bus->count_cells(blob, parent, &na, &ns); if (!OF_CHECK_COUNTS(na, ns)) { printf("%s: Bad cell count for %s\n", __FUNCTION__, diff --cc common/lcd.c index 66b1c04cdd,66d4f94f9e..77052e696d --- a/common/lcd.c +++ b/common/lcd.c @@@ -214,24 -256,26 +256,28 @@@ void lcd_printf(const char *fmt, ... /* ** Low-Level Graphics Routines */ /************************************************************************/ - static void lcd_drawchars (ushort x, ushort y, uchar *str, int count) + static void lcd_drawchars(ushort x, ushort y, uchar *str, int count) { - uchar *dest; + void *dest; ushort row; + #if defined(CONFIG_LCD_LOGO) && !defined(CONFIG_LCD_INFO_BELOW_LOGO) + y += BMP_LOGO_HEIGHT; + #endif + #if LCD_BPP == LCD_MONOCHROME ushort off = x * (1 << LCD_BPP) % 8; #endif - dest = (uchar *)(lcd_base + y * lcd_line_length + x * (1 << LCD_BPP) / 8); + dest = lcd_base + y * lcd_line_length + x * (1 << LCD_BPP) / 8; - for (row=0; row < VIDEO_FONT_HEIGHT; ++row, dest += lcd_line_length) { + for (row = 0; row < VIDEO_FONT_HEIGHT; ++row, dest += lcd_line_length) { uchar *s = str; int i; -#if LCD_BPP == LCD_COLOR16 - ushort *d = (ushort *)dest; +#if LCD_BPP == LCD_COLOR24 + ulong *d = dest; +#elif LCD_BPP == LCD_COLOR16 + ushort *d = dest; #else uchar *d = dest; #endif @@@ -252,8 -296,14 +298,8 @@@ *d++ = rest | (sym >> off); rest = sym << (8-off); -#elif LCD_BPP == LCD_COLOR8 - for (c = 0; c < 8; ++c) { - *d++ = (bits & 0x80) ? - lcd_color_fg : lcd_color_bg; - bits <<= 1; - } -#elif LCD_BPP == LCD_COLOR16 +#else - for (c=0; c<8; ++c) { + for (c = 0; c < 8; ++c) { *d++ = (bits & 0x80) ? lcd_color_fg : lcd_color_bg; bits <<= 1; @@@ -301,32 -343,23 +339,33 @@@ static int test_colors[N_BLK_HOR*N_BLK_ CONSOLE_COLOR_BLUE, CONSOLE_COLOR_MAGENTA, CONSOLE_COLOR_CYAN, }; +#if LCD_BPP == LCD_COLOR8 +typedef uchar pix_t; +#elif LCD_BPP == LCD_COLOR16 +typedef ushort pix_t; +#elif LCD_BPP == LCD_COLOR24 +typedef ulong pix_t; +#else +#error Unsupported pixelformat +#endif + - static void test_pattern (void) + static void test_pattern(void) { ushort v_max = panel_info.vl_row; ushort h_max = panel_info.vl_col; ushort v_step = (v_max + N_BLK_VERT - 1) / N_BLK_VERT; ushort h_step = (h_max + N_BLK_HOR - 1) / N_BLK_HOR; ushort v, h; - uchar *pix = (uchar *)lcd_base; + pix_t *pix = lcd_base; - printf ("[LCD] Test Pattern: %d x %d [%d x %d]\n", + printf("[LCD] Test Pattern: %d x %d [%d x %d]\n", h_max, v_max, h_step, v_step); - for (v = 0; v < v_max; v++) { + /* WARNING: Code silently assumes 8bit/pixel */ + for (v = 0; v < v_max; ++v) { uchar iy = v / v_step; - for (h = 0; h < h_max; h++) { - uchar ix = N_BLK_HOR * iy + (h / h_step); + for (h = 0; h < h_max; ++h) { + uchar ix = N_BLK_HOR * iy + (h/h_step); *pix++ = test_colors[ix]; } } @@@ -338,21 -371,27 +377,27 @@@ /* ** GENERIC Initialization Routines */ /************************************************************************/ + int lcd_get_size(int *line_length) + { + *line_length = (panel_info.vl_col * NBITS(panel_info.vl_bpix)) / 8; + return *line_length * panel_info.vl_row; + } + -int drv_lcd_init (void) +int drv_lcd_init(void) { struct stdio_dev lcddev; int rc; - lcd_base = (void *)(gd->fb_base); + lcd_base = (void *)gd->fb_base; - lcd_line_length = (panel_info.vl_col * NBITS (panel_info.vl_bpix)) / 8; + lcd_get_size(&lcd_line_length); - lcd_init (lcd_base); /* LCD initialization */ + lcd_init(lcd_base); /* LCD initialization */ /* Device initialization */ - memset (&lcddev, 0, sizeof (lcddev)); + memset(&lcddev, 0, sizeof(lcddev)); - strcpy (lcddev.name, "lcd"); + strcpy(lcddev.name, "lcd"); lcddev.ext = 0; /* No extensions */ lcddev.flags = DEV_FLAGS_OUTPUT; /* Output only */ lcddev.putc = lcd_putc; /* 'putc' function */ @@@ -407,10 -439,8 +445,8 @@@ void lcd_clear(void lcd_line_length*panel_info.vl_row); #endif /* Paint the logo and retrieve LCD base address */ - debug ("[LCD] Drawing the logo @ %p...\n", lcd_base); - debug("[LCD] Drawing the logo...\n"); -- lcd_console_address = lcd_logo (); - flush_dcache_range((unsigned long)lcd_base, - (unsigned long)lcd_base + lcd_line_length*panel_info.vl_row); ++ debug("[LCD] Drawing the logo @ %p...\n", lcd_base); ++ lcd_console_address = lcd_logo(); console_col = 0; console_row = 0; @@@ -424,17 -462,15 +468,17 @@@ U_BOOT_CMD /*----------------------------------------------------------------------*/ - static int lcd_init (void *lcdbase) + static int lcd_init(void *lcdbase) { /* Initialize the lcd controller */ - debug ("[LCD] Initializing %ux%ux%u LCD framebuffer at %p\n", - debug("[LCD] Initializing LCD frambuffer at %p\n", lcdbase); ++ debug("[LCD] Initializing %ux%ux%u LCD framebuffer at %p\n", + panel_info.vl_col, panel_info.vl_row, NBITS(panel_info.vl_bpix), + lcdbase); - lcd_ctrl_init (lcdbase); + lcd_ctrl_init(lcdbase); lcd_is_enabled = 1; lcd_clear(); -- lcd_enable (); ++ lcd_enable(); /* Initialize the console */ console_col = 0; @@@ -504,7 -541,7 +549,7 @@@ static int lcd_getfgcolor(void /*----------------------------------------------------------------------*/ - static inline int lcd_getbgcolor (void) -static int lcd_getbgcolor(void) ++static inline int lcd_getbgcolor(void) { return lcd_color_bg; } @@@ -514,27 -551,48 +559,48 @@@ /************************************************************************/ /* ** Chipset depending Bitmap / Logo stuff... */ /************************************************************************/ + static inline ushort *configuration_get_cmap(void) + { + #if defined CONFIG_CPU_PXA + struct pxafb_info *fbi = &panel_info.pxa; + return (ushort *)fbi->palette; + #elif defined(CONFIG_MPC823) - immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; ++ immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; + cpm8xx_t *cp = &(immr->im_cpm); + return (ushort *)&(cp->lcd_cmap[255 * sizeof(ushort)]); + #elif defined(CONFIG_ATMEL_LCD) + return (ushort *)(panel_info.mmio + ATMEL_LCDC_LUT(0)); + #elif !defined(CONFIG_ATMEL_HLCD) && !defined(CONFIG_EXYNOS_FB) + return panel_info.cmap; + #else + #if defined(CONFIG_LCD_LOGO) + return bmp_logo_palette; + #else + return NULL; + #endif + #endif + } + #ifdef CONFIG_LCD_LOGO - void bitmap_plot (int x, int y) + void bitmap_plot(int x, int y) { #ifdef CONFIG_ATMEL_LCD - uint *cmap; + uint *cmap = (uint *)bmp_logo_palette; #else - ushort *cmap; + ushort *cmap = (ushort *)bmp_logo_palette; #endif ushort i, j; uchar *bmap; uchar *fb; - #if defined(CONFIG_CPU_PXA) - struct pxafb_info *fbi = &panel_info.pxa; - #elif defined(CONFIG_MPC823) - volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; - volatile cpm8xx_t *cp = &immr->im_cpm; + ushort *fb16; + #if defined(CONFIG_MPC823) - immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; ++ immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; + cpm8xx_t *cp = &(immr->im_cpm); #endif - debug ("Logo: width %d height %d colors %d cmap %d\n", + debug("Logo: width %d height %d colors %d cmap %d\n", BMP_LOGO_WIDTH, BMP_LOGO_HEIGHT, BMP_LOGO_COLORS, - (int)(sizeof(bmp_logo_palette)/(sizeof(ushort)))); + ARRAY_SIZE(bmp_logo_palette)); bmap = &bmp_logo_bitmap[0]; fb = (uchar *)(lcd_base + y * lcd_line_length + x); @@@ -590,13 -645,13 +653,12 @@@ bmap += BMP_LOGO_WIDTH; fb += panel_info.vl_col; } - } - else { /* true color mode */ + } else if (NBITS(panel_info.vl_bpix) == 16) { u16 col16; - u16 *fb16 = lcd_base + y * lcd_line_length + x; - - for (i = 0; i < BMP_LOGO_HEIGHT; i++) { + fb16 = (ushort *)(lcd_base + y * lcd_line_length + x); + for (i = 0; i < BMP_LOGO_HEIGHT; ++i) { for (j = 0; j < BMP_LOGO_WIDTH; j++) { - col16 = bmp_logo_palette[bmap[j] - 16]; + col16 = bmp_logo_palette[(bmap[j]-16)]; fb16[j] = ((col16 & 0x000F) << 1) | ((col16 & 0x00F0) << 3) | @@@ -605,27 -660,13 +667,28 @@@ bmap += BMP_LOGO_WIDTH; fb16 += panel_info.vl_col; } + } else { /* true color mode */ + u16 col16; + u32 *fb32 = lcd_base + y * lcd_line_length + x; + + for (i = 0; i < BMP_LOGO_HEIGHT; i++) { + for (j = 0; j < BMP_LOGO_WIDTH; j++) { + col16 = bmp_logo_palette[bmap[j] - 16]; + fb32[j] = + ((col16 & 0x000F) << 4) | + ((col16 & 0x00F0) << 8) | + ((col16 & 0x0F00) << 12); + } + bmap += BMP_LOGO_WIDTH; + fb32 += panel_info.vl_col; + } } - flush_dcache_range((unsigned long)fb, - (unsigned long)fb + BMP_LOGO_HEIGHT * BMP_LOGO_WIDTH); WATCHDOG_RESET(); + lcd_sync(); } + #else + static inline void bitmap_plot(int x, int y) {} #endif /* CONFIG_LCD_LOGO */ /*----------------------------------------------------------------------*/ @@@ -649,28 -861,22 +883,23 @@@ int lcd_display_bitmap(ulong bmp_image uchar *fb; bmp_image_t *bmp=(bmp_image_t *)bmp_image; uchar *bmap; - ushort padded_line; - int width, height, byte_width; - int pwidth = panel_info.vl_col; + ushort padded_width; - unsigned long width, height, byte_width; ++ unsigned long width, height; + unsigned long pwidth = panel_info.vl_col; - unsigned colors, bpix, bmp_bpix; + unsigned long long colors; + unsigned bpix, bmp_bpix; - #if defined(CONFIG_CPU_PXA) - struct pxafb_info *fbi = &panel_info.pxa; - #elif defined(CONFIG_MPC823) - volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; - volatile cpm8xx_t *cp = &(immr->im_cpm); - #endif - if (!((bmp->header.signature[0]=='B') && - (bmp->header.signature[1]=='M'))) { - printf ("Error: no valid bmp image at %lx\n", bmp_image); + if (!bmp || !((bmp->header.signature[0] == 'B') && + (bmp->header.signature[1] == 'M'))) { + printf("Error: no valid bmp image at %lx\n", bmp_image); + return 1; } - width = le32_to_cpu (bmp->header.width); - height = le32_to_cpu (bmp->header.height); + width = le32_to_cpu(bmp->header.width); + height = le32_to_cpu(bmp->header.height); bmp_bpix = le16_to_cpu(bmp->header.bit_count); - colors = 1 << bmp_bpix; + colors = 1ULL << bmp_bpix; bpix = NBITS(panel_info.vl_bpix); @@@ -689,8 -896,8 +919,8 @@@ return 1; } - debug ("Display-bmp: %u x %u with %llu colors\n", - debug("Display-bmp: %d x %d with %d colors\n", - (int)width, (int)height, (int)colors); ++ debug("Display-bmp: %lu x %lu with %llu colors\n", + width, height, colors); #if !defined(CONFIG_MCC200) /* MCC200 LCD doesn't need CMAP, supports 1bpp b&w only */ @@@ -741,111 -941,95 +964,98 @@@ * specific. */ #if defined(CONFIG_MCC200) - if (bpix==1) - { + if (bpix == 1) { - width = ((width + 7) & ~7) >> 3; - x = ((x + 7) & ~7) >> 3; - pwidth= ((pwidth + 7) & ~7) >> 3; + width = ALIGN(width, 8) >> 3; + x = ALIGN(x, 8) >> 3; + pwidth= ALIGN(pwidth, 8) >> 3; } #endif - padded_line = ALIGN(width, 4); - padded_width = (width&0x3) ? ((width&~0x3)+4) : (width); ++ padded_width = ALIGN(width, 4); #ifdef CONFIG_SPLASH_SCREEN_ALIGN - if (x == BMP_ALIGN_CENTER) - x = max(0, (pwidth - width) / 2); - else if (x < 0) - x = max(0, pwidth - width + x + 1); - - if (y == BMP_ALIGN_CENTER) - y = max(0, (panel_info.vl_row - height) / 2); - else if (y < 0) - y = max(0, panel_info.vl_row - height + y + 1); + splash_align_axis(&x, pwidth, width); + splash_align_axis(&y, panel_info.vl_row, height); #endif /* CONFIG_SPLASH_SCREEN_ALIGN */ + bmap = (uchar *)bmp + le32_to_cpu (bmp->header.data_offset); if ((x + width) > pwidth) - width = pwidth - x; - if ((y + height) > panel_info.vl_row) + width = max(pwidth - x, pwidth); + if ((y + height) > panel_info.vl_row) { height = panel_info.vl_row - y; - bmap += (panel_info.vl_row - y) * padded_line; ++ bmap += (panel_info.vl_row - y) * padded_width; + } + bmap = (uchar *)bmp + le32_to_cpu(bmp->header.data_offset); fb = (uchar *) (lcd_base + (y + height - 1) * lcd_line_length + x * bpix / 8); + switch (bmp_bpix) { case 1: /* pass through */ case 8: - if (bpix > 16) - byte_width = width * 4; - else if (bpix == 16) - byte_width = width * 2; - else - byte_width = width; - for (i = 0; i < height; i++) { + #ifdef CONFIG_LCD_BMP_RLE8 + if (le32_to_cpu(bmp->header.compression) == BMP_BI_RLE8) { + if (bpix != 16) { + /* TODO implement render code for bpix != 16 */ + printf("Error: only support 16 bpix"); + return 1; + } + lcd_display_rle8_bitmap(bmp, cmap_base, fb, x, y); + break; + } + #endif + - if (bpix != 16) - byte_width = width; - else - byte_width = width * 2; - + for (i = 0; i < height; ++i) { WATCHDOG_RESET(); for (j = 0; j < width; j++) { - if (bpix != 16) { - FB_PUT_BYTE(fb, bmap); - } else { + if (bpix == 32) { + int i = *bmap++; + + fb[3] = 0; /* T */ + fb[0] = bmp->color_table[i].blue; + fb[1] = bmp->color_table[i].green; + fb[2] = bmp->color_table[i].red; + fb += sizeof(uint32_t) / sizeof(*fb); + } else if (bpix == 16) { *(uint16_t *)fb = cmap_base[*(bmap++)]; fb += sizeof(uint16_t) / sizeof(*fb); + } else { - #if defined(CONFIG_CPU_PXA) || defined(CONFIG_ATMEL_LCD) - *(fb++) = *(bmap++); - #elif defined(CONFIG_MPC823) || defined(CONFIG_MCC200) - *(fb++) = 255 - *(bmap++); - #endif ++ FB_PUT_BYTE(fb, bmap); } } - bmap += padded_line - width; - fb -= byte_width + lcd_line_length; - bmap += (padded_width - width); - fb -= (byte_width + lcd_line_length); ++ bmap += padded_width - width; ++ fb -= width + lcd_line_length; } break; #if defined(CONFIG_BMP_16BPP) case 16: - for (i = 0; i < height; i++) { + for (i = 0; i < height; ++i) { WATCHDOG_RESET(); - for (j = 0; j < width; j++) { - #if defined(CONFIG_ATMEL_LCD_BGR555) - *(fb++) = ((bmap[0] & 0x1f) << 2) | - (bmap[1] & 0x03); - *(fb++) = (bmap[0] & 0xe0) | - ((bmap[1] & 0x7c) >> 2); - bmap += 2; - #else - *(fb++) = *(bmap++); - *(fb++) = *(bmap++); - #endif - } - bmap += (padded_line - width) * 2; + for (j = 0; j < width; j++) + fb_put_word(&fb, &bmap); + + bmap += (padded_width - width) * 2; - fb -= (width * 2 + lcd_line_length); + fb -= width * 2 + lcd_line_length; } break; #endif /* CONFIG_BMP_16BPP */ - -#if defined(CONFIG_BMP_32BPP) case 32: - for (i = 0; i < height; i++) { + for (i = 0; i < height; ++i) { + WATCHDOG_RESET(); for (j = 0; j < width; j++) { - *(fb++) = *(bmap++); - *(fb++) = *(bmap++); - *(fb++) = *(bmap++); - *(fb++) = *(bmap++); + fb[3] = *bmap++; /* T */ + fb[0] = *bmap++; /* B */ + fb[1] = *bmap++; /* G */ + fb[2] = *bmap++; /* R */ + fb += 4; } - bmap += (padded_line - width) * 4; - fb -= (lcd_line_length + width * (bpix / 8)); ++ bmap += (padded_width - width) * 4; + fb -= width * 4 + lcd_line_length; } break; -#endif /* CONFIG_BMP_32BPP */ - default: - break; }; - lcd_sync(); return 0; } #endif @@@ -859,15 -1043,12 +1069,16 @@@ static void *lcd_logo(void if (do_splash && (s = getenv("splashimage")) != NULL) { int x = 0, y = 0; + char *end; + do_splash = 0; - addr = simple_strtoul (s, NULL, 16); + addr = simple_strtoul (s, &end, 16); + if (addr == 0 || *end != '\0') + return lcd_base; #ifdef CONFIG_SPLASH_SCREEN_ALIGN - if ((s = getenv ("splashpos")) != NULL) { + s = getenv("splashpos"); + if (s != NULL) { if (s[0] == 'm') x = BMP_ALIGN_CENTER; else diff --cc common/main.c index 4f744f4db8,e2d2e09bf9..31d6331fa1 --- a/common/main.c +++ b/common/main.c @@@ -1345,7 -1452,7 +1459,7 @@@ static int builtin_run_command(const ch continue; } - if (cmd_process(flag, argc, argv, &repeatable) != CMD_RET_SUCCESS) - if (cmd_process(flag, argc, argv, &repeatable, NULL)) ++ if (cmd_process(flag, argc, argv, &repeatable, NULL) != CMD_RET_SUCCESS) rc = -1; /* Did the user stop this? */ diff --cc common/spl/spl_nand.c index 7cf41742c8,61de5a4f05..fde7327659 --- a/common/spl/spl_nand.c +++ b/common/spl/spl_nand.c @@@ -21,17 -21,13 +21,14 @@@ * MA 02111-1307 USA */ #include - #include - #include - #include + #include + #include #include #include - #include - #include -void spl_nand_load_image(void) +int spl_nand_load_image(void) { + int ret; struct image_header *header; int *src __attribute__((unused)); int *dst __attribute__((unused)); diff --cc common/spl/spl_ymodem.c index 1c3ca93eea,40e50356f9..fc6083fc64 --- a/common/spl/spl_ymodem.c +++ b/common/spl/spl_ymodem.c @@@ -26,12 -26,10 +26,11 @@@ * MA 02111-1307 USA */ #include + #include #include ++#include #include #include - #include - #include - #include #define BUF_SIZE 1024 diff --cc drivers/dma/apbh_dma.c index cb2193ec55,37a941cc5b..fc4051cd23 --- a/drivers/dma/apbh_dma.c +++ b/drivers/dma/apbh_dma.c @@@ -30,10 -30,10 +30,90 @@@ #include #include #include ++#include #include #include ++#ifdef DEBUG_ ++static inline u32 mxs_readl(void *addr, ++ const char *fn, int ln) ++{ ++ u32 val = readl(addr); ++ static void *last_addr; ++ static u32 last_val; ++ ++ if (addr != last_addr || last_val != val) { ++ printf("%s@%d: Read %08x from %p\n", fn, ln, val, addr); ++ last_addr = addr; ++ last_val = val; ++ } ++ return val; ++} ++ ++static inline void mxs_writel(u32 val, void *addr, ++ const char *name, const char *fn, int ln) ++{ ++#if 0 ++ printf("%s@%d: Writing %08x to %s[%p]...", fn, ln, val, name, addr); ++#else ++ printf("%s@%d: Writing %08x to %p...", fn, ln, val, addr); ++#endif ++ writel(val, addr); ++ printf(" result: %08x\n", readl(addr)); ++} ++ ++#undef readl ++#define readl(a) mxs_readl(a, __func__, __LINE__) ++ ++#undef writel ++#define writel(v, a) mxs_writel(v, a, #a, __func__, __LINE__) ++#endif ++ ++#define pr_dma_flag(c,f) do { if ((c) & MXS_DMA_DESC_##f) printf("%s ", #f); } while (0) ++static inline void dump_dma_desc(struct mxs_dma_desc *desc) ++{ ++ struct mxs_dma_cmd *cmd = &desc->cmd; ++ ++ printf("DMA desc %p:\n", desc); ++ printf("NXT: %08lx\n", cmd->next); ++ printf("CMD: %08lx - ", cmd->data); ++ printf("CNT: %04lx ", (cmd->data & MXS_DMA_DESC_BYTES_MASK) >> MXS_DMA_DESC_BYTES_OFFSET); ++ printf("PIO: %ld ", (cmd->data & MXS_DMA_DESC_PIO_WORDS_MASK) >> MXS_DMA_DESC_PIO_WORDS_OFFSET); ++ pr_dma_flag(cmd->data, HALT_ON_TERMINATE); ++ pr_dma_flag(cmd->data, WAIT4END); ++ pr_dma_flag(cmd->data, DEC_SEM); ++ pr_dma_flag(cmd->data, NAND_WAIT_4_READY); ++ pr_dma_flag(cmd->data, NAND_LOCK); ++ pr_dma_flag(cmd->data, IRQ); ++ pr_dma_flag(cmd->data, CHAIN); ++ printf("\nMOD: "); ++ switch (cmd->data & MXS_DMA_DESC_COMMAND_MASK) { ++ case MXS_DMA_DESC_COMMAND_NO_DMAXFER: ++ printf("NO_DMA\n"); ++ break; ++ case MXS_DMA_DESC_COMMAND_DMA_WRITE: ++ printf("WRITE\n"); ++ break; ++ case MXS_DMA_DESC_COMMAND_DMA_READ: ++ printf("READ\n"); ++ break; ++ case MXS_DMA_DESC_COMMAND_DMA_SENSE: ++ printf("SENSE\n"); ++ } ++ if (cmd->data & MXS_DMA_DESC_PIO_WORDS_MASK) { ++ int pio_words = (cmd->data & MXS_DMA_DESC_PIO_WORDS_MASK) >> MXS_DMA_DESC_PIO_WORDS_OFFSET; ++ int i; ++ ++ printf("PIO: "); ++ for (i = 0; i < pio_words; i++) { ++ printf("%08lx ", cmd->pio_words[i]); ++ } ++ printf("\n"); ++ } ++} ++ static struct mxs_dma_chan mxs_dma_channels[MXS_MAX_DMA_CHANNELS]; ++static struct apbh_regs *apbh_regs = (struct apbh_regs *)MXS_APBH_BASE; /* * Test is the DMA channel is valid channel @@@ -42,12 -42,12 +122,16 @@@ int mxs_dma_validate_chan(int channel { struct mxs_dma_chan *pchan; -- if ((channel < 0) || (channel >= MXS_MAX_DMA_CHANNELS)) ++ if ((channel < 0) || (channel >= MXS_MAX_DMA_CHANNELS)) { ++ printf("Invalid DMA channel %d\n", channel); return -EINVAL; ++ } pchan = mxs_dma_channels + channel; -- if (!(pchan->flags & MXS_DMA_FLAGS_ALLOCATED)) ++ if (!(pchan->flags & MXS_DMA_FLAGS_ALLOCATED)) { ++ printf("DMA channel %d not allocated\n", channel); return -EINVAL; ++ } return 0; } @@@ -76,8 -76,8 +160,6 @@@ static unsigned int mxs_dma_cmd_address */ static int mxs_dma_read_semaphore(int channel) { - struct mx28_apbh_regs *apbh_regs = - (struct mx28_apbh_regs *)MXS_APBH_BASE; - struct mxs_apbh_regs *apbh_regs = - (struct mxs_apbh_regs *)MXS_APBH_BASE; uint32_t tmp; int ret; @@@ -119,8 -119,8 +201,6 @@@ inline void mxs_dma_flush_desc(struct m */ static int mxs_dma_enable(int channel) { - struct mx28_apbh_regs *apbh_regs = - (struct mx28_apbh_regs *)MXS_APBH_BASE; - struct mxs_apbh_regs *apbh_regs = - (struct mxs_apbh_regs *)MXS_APBH_BASE; unsigned int sem; struct mxs_dma_chan *pchan; struct mxs_dma_desc *pdesc; @@@ -139,7 -139,7 +219,7 @@@ pdesc = list_first_entry(&pchan->active, struct mxs_dma_desc, node); if (pdesc == NULL) -- return -EFAULT; ++ return -EINVAL; if (pchan->flags & MXS_DMA_FLAGS_BUSY) { if (!(pdesc->cmd.data & MXS_DMA_DESC_CHAIN)) @@@ -162,12 -162,12 +242,14 @@@ } else { pchan->active_num += pchan->pending_num; pchan->pending_num = 0; ++#if 1 ++ writel(1 << (channel + APBH_CTRL0_CLKGATE_CHANNEL_OFFSET), ++ &apbh_regs->hw_apbh_ctrl0_clr); ++#endif writel(mxs_dma_cmd_address(pdesc), &apbh_regs->ch[channel].hw_apbh_ch_nxtcmdar); writel(pchan->active_num, &apbh_regs->ch[channel].hw_apbh_ch_sema); -- writel(1 << (channel + APBH_CTRL0_CLKGATE_CHANNEL_OFFSET), -- &apbh_regs->hw_apbh_ctrl0_clr); } pchan->flags |= MXS_DMA_FLAGS_BUSY; @@@ -191,8 -191,8 +273,6 @@@ static int mxs_dma_disable(int channel) { struct mxs_dma_chan *pchan; - struct mx28_apbh_regs *apbh_regs = - (struct mx28_apbh_regs *)MXS_APBH_BASE; - struct mxs_apbh_regs *apbh_regs = - (struct mxs_apbh_regs *)MXS_APBH_BASE; int ret; ret = mxs_dma_validate_chan(channel); @@@ -201,13 -201,13 +281,14 @@@ pchan = mxs_dma_channels + channel; -- if (!(pchan->flags & MXS_DMA_FLAGS_BUSY)) ++ if ((pchan->flags & MXS_DMA_FLAGS_BUSY)) { ++ printf("%s: DMA channel %d busy\n", __func__, channel); return -EINVAL; -- ++ } ++#if 0 writel(1 << (channel + APBH_CTRL0_CLKGATE_CHANNEL_OFFSET), &apbh_regs->hw_apbh_ctrl0_set); -- -- pchan->flags &= ~MXS_DMA_FLAGS_BUSY; ++#endif pchan->active_num = 0; pchan->pending_num = 0; list_splice_init(&pchan->active, &pchan->done); @@@ -220,8 -220,8 +301,6 @@@ */ static int mxs_dma_reset(int channel) { - struct mx28_apbh_regs *apbh_regs = - (struct mx28_apbh_regs *)MXS_APBH_BASE; - struct mxs_apbh_regs *apbh_regs = - (struct mxs_apbh_regs *)MXS_APBH_BASE; int ret; ret = mxs_dma_validate_chan(channel); @@@ -241,8 -241,8 +320,6 @@@ */ static int mxs_dma_enable_irq(int channel, int enable) { - struct mx28_apbh_regs *apbh_regs = - (struct mx28_apbh_regs *)MXS_APBH_BASE; - struct mxs_apbh_regs *apbh_regs = - (struct mxs_apbh_regs *)MXS_APBH_BASE; int ret; ret = mxs_dma_validate_chan(channel); @@@ -267,8 -267,8 +344,6 @@@ */ static int mxs_dma_ack_irq(int channel) { - struct mx28_apbh_regs *apbh_regs = - (struct mx28_apbh_regs *)MXS_APBH_BASE; - struct mxs_apbh_regs *apbh_regs = - (struct mxs_apbh_regs *)MXS_APBH_BASE; int ret; ret = mxs_dma_validate_chan(channel); @@@ -504,8 -504,8 +579,6 @@@ static int mxs_dma_finish(int channel, */ static int mxs_dma_wait_complete(uint32_t timeout, unsigned int chan) { - struct mx28_apbh_regs *apbh_regs = - (struct mx28_apbh_regs *)MXS_APBH_BASE; - struct mxs_apbh_regs *apbh_regs = - (struct mxs_apbh_regs *)MXS_APBH_BASE; int ret; ret = mxs_dma_validate_chan(chan); @@@ -554,10 -554,10 +627,7 @@@ int mxs_dma_go(int chan */ void mxs_dma_init(void) { - struct mx28_apbh_regs *apbh_regs = - (struct mx28_apbh_regs *)MXS_APBH_BASE; - struct mxs_apbh_regs *apbh_regs = - (struct mxs_apbh_regs *)MXS_APBH_BASE; -- - mx28_reset_block(&apbh_regs->hw_apbh_ctrl0_reg); + mxs_reset_block(&apbh_regs->hw_apbh_ctrl0_reg); #ifdef CONFIG_APBH_DMA_BURST8 writel(APBH_CTRL0_AHB_BURST8_EN, diff --cc drivers/gpio/Makefile index 155402cdd8,2d97b4f1e4..e2e38f925b --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@@ -25,10 -25,8 +25,11 @@@ include $(TOPDIR)/config.m LIB := $(obj)libgpio.o +COBJS-y += gpiolib.o + +COBJS-$(CONFIG_AM33XX_GPIO) += am33xx_gpio.o COBJS-$(CONFIG_AT91_GPIO) += at91_gpio.o + COBJS-$(CONFIG_INTEL_ICH6_GPIO) += intel_ich6_gpio.o COBJS-$(CONFIG_KIRKWOOD_GPIO) += kw_gpio.o COBJS-$(CONFIG_MARVELL_GPIO) += mvgpio.o COBJS-$(CONFIG_MARVELL_MFP) += mvmfp.o diff --cc drivers/gpio/am33xx_gpio.c index 71cd50e34d,0000000000..8f447ed1e7 mode 100644,000000..100644 --- a/drivers/gpio/am33xx_gpio.c +++ b/drivers/gpio/am33xx_gpio.c @@@ -1,106 -1,0 +1,106 @@@ +/* + * Copyright (C) 2012 Lothar Waßmann + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include +#include - #include +#include +#include +#include +#include ++#include + +struct gpio_regs { + unsigned int res1[0x134 / 4]; + unsigned int oe; /* 0x134 */ + unsigned int datain; /* 0x138 */ + unsigned int res2[0x54 / 4]; + unsigned int cleardataout; /* 0x190 */ + unsigned int setdataout; /* 0x194 */ +}; + - struct gpio_regs *gpio_base[] = { - (struct gpio_regs *)GPIO0_BASE, - (struct gpio_regs *)GPIO1_BASE, - (struct gpio_regs *)GPIO2_BASE, - (struct gpio_regs *)GPIO3_BASE, ++static const struct gpio_regs *gpio_base[] = { ++ (struct gpio_regs *)AM33XX_GPIO0_BASE, ++ (struct gpio_regs *)AM33XX_GPIO1_BASE, ++ (struct gpio_regs *)AM33XX_GPIO2_BASE, ++ (struct gpio_regs *)AM33XX_GPIO3_BASE, +}; + +static unsigned long gpio_map[ARRAY_SIZE(gpio_base)]; + +#define MAX_GPIO (ARRAY_SIZE(gpio_base) * 32) + +int gpio_request(unsigned gpio, const char *name) +{ + if (gpio >= MAX_GPIO) + return -EINVAL; + if (test_and_set_bit(gpio, gpio_map)) + return -EBUSY; + return 0; +} + +int gpio_free(unsigned gpio) +{ + if (gpio >= MAX_GPIO) + return -EINVAL; + + if (test_bit(gpio, gpio_map)) + __clear_bit(gpio, gpio_map); + else + printf("ERROR: trying to free unclaimed GPIO %u\n", gpio); + + return 0; +} + +int gpio_set_value(unsigned gpio, int val) +{ + int bank = gpio / 32; + int mask = 1 << (gpio % 32); + + if (bank >= ARRAY_SIZE(gpio_base)) + return -EINVAL; + + if (val) + writel(mask, &gpio_base[bank]->setdataout); + else + writel(mask, &gpio_base[bank]->cleardataout); + return 0; +} + +int gpio_direction_input(unsigned gpio) +{ + int bank = gpio / 32; + int mask = 1 << (gpio % 32); + + if (bank >= ARRAY_SIZE(gpio_base)) + return -EINVAL; + + writel(readl(&gpio_base[bank]->oe) | mask, &gpio_base[bank]->oe); + return 0; +} + +int gpio_direction_output(unsigned gpio, int val) +{ + int bank = gpio / 32; + int mask = 1 << (gpio % 32); + + if (bank >= ARRAY_SIZE(gpio_base)) + return -EINVAL; + + gpio_set_value(gpio, val); + writel(readl(&gpio_base[bank]->oe) & ~mask, &gpio_base[bank]->oe); + return 0; +} diff --cc drivers/gpio/mxc_gpio.c index 8a92fec6fc,a3880641f0..35e9246977 --- a/drivers/gpio/mxc_gpio.c +++ b/drivers/gpio/mxc_gpio.c @@@ -41,13 -41,15 +41,15 @@@ static unsigned long gpio_ports[] = [0] = GPIO1_BASE_ADDR, [1] = GPIO2_BASE_ADDR, [2] = GPIO3_BASE_ADDR, - #if defined(CONFIG_MX25) || defined(CONFIG_MX51) || defined(CONFIG_MX53) || \ - defined(CONFIG_MX6Q) + #if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX51) || \ + defined(CONFIG_MX53) || defined(CONFIG_MX6) [3] = GPIO4_BASE_ADDR, #endif - #if defined(CONFIG_MX53) || defined(CONFIG_MX6Q) -#if defined(CONFIG_MX27) || defined(CONFIG_MX53) || defined(CONFIG_MX6) ++#if defined(CONFIG_MX27) || defined(CONFIG_MX53) || defined(CONFIG_MX6Q) [4] = GPIO5_BASE_ADDR, [5] = GPIO6_BASE_ADDR, + #endif -#if defined(CONFIG_MX53) || defined(CONFIG_MX6) ++#if defined(CONFIG_MX53) || defined(CONFIG_MX6Q) [6] = GPIO7_BASE_ADDR, #endif }; @@@ -59,8 -61,8 +61,10 @@@ static int mxc_gpio_direction(unsigned struct gpio_regs *regs; u32 l; -- if (port >= ARRAY_SIZE(gpio_ports)) ++ if (port >= ARRAY_SIZE(gpio_ports)) { ++ printf("%s: Invalid GPIO %d\n", __func__, gpio); return -1; ++ } gpio &= 0x1f; @@@ -86,8 -88,8 +90,10 @@@ int gpio_set_value(unsigned gpio, int v struct gpio_regs *regs; u32 l; -- if (port >= ARRAY_SIZE(gpio_ports)) ++ if (port >= ARRAY_SIZE(gpio_ports)) { ++ printf("%s: Invalid GPIO %d\n", __func__, gpio); return -1; ++ } gpio &= 0x1f; @@@ -109,28 -111,28 +115,42 @@@ int gpio_get_value(unsigned gpio struct gpio_regs *regs; u32 val; -- if (port >= ARRAY_SIZE(gpio_ports)) ++ if (port >= ARRAY_SIZE(gpio_ports)) { ++ printf("%s: Invalid GPIO %d\n", __func__, gpio); return -1; ++ } gpio &= 0x1f; regs = (struct gpio_regs *)gpio_ports[port]; - val = (readl(®s->gpio_dr) >> gpio) & 0x01; - val = (readl(®s->gpio_psr) >> gpio) & 0x01; -- ++ if (readl(®s->gpio_dir) & (1 << gpio)) { ++ printf("WARNING: Reading status of output GPIO_%d_%d\n", ++ port - GPIO_TO_PORT(0), gpio); ++ val = (readl(®s->gpio_dr) >> gpio) & 0x01; ++ } else { ++ val = (readl(®s->gpio_psr) >> gpio) & 0x01; ++ } return val; } int gpio_request(unsigned gpio, const char *label) { unsigned int port = GPIO_TO_PORT(gpio); -- if (port >= ARRAY_SIZE(gpio_ports)) ++ if (port >= ARRAY_SIZE(gpio_ports)) { ++ printf("%s: Invalid GPIO %d\n", __func__, gpio); return -1; ++ } return 0; } int gpio_free(unsigned gpio) { ++ unsigned int port = GPIO_TO_PORT(gpio); ++ if (port >= ARRAY_SIZE(gpio_ports)) { ++ printf("%s: Invalid GPIO %d\n", __func__, gpio); ++ return -1; ++ } return 0; } diff --cc drivers/misc/Makefile index 99aec1f47a,8cdc3b649c..f0efd2dcfb --- a/drivers/misc/Makefile +++ b/drivers/misc/Makefile @@@ -27,8 -27,7 +27,8 @@@ LIB := $(obj)libmisc. COBJS-$(CONFIG_ALI152X) += ali512x.o COBJS-$(CONFIG_DS4510) += ds4510.o - COBJS-$(CONFIG_FSL_LAW) += fsl_law.o + COBJS-$(CONFIG_CBMEM_CONSOLE) += cbmem_console.o +COBJS-$(CONFIG_IMX_IIM) += imx_iim.o COBJS-$(CONFIG_GPIO_LED) += gpio_led.o COBJS-$(CONFIG_FSL_MC9SDZ60) += mc9sdz60.o COBJS-$(CONFIG_NS87308) += ns87308.o diff --cc drivers/misc/imx_iim.c index 0438ec7eff,0000000000..207d9548ea mode 100644,000000..100644 --- a/drivers/misc/imx_iim.c +++ b/drivers/misc/imx_iim.c @@@ -1,318 -1,0 +1,319 @@@ +/* + * (C) Copyright 2008-2010 Freescale Semiconductor, Inc. + * Terry Lv + * + * Copyright 2007, Freescale Semiconductor, Inc + * Andy Fleming + * + * Based vaguely on the pxa mmc code: + * (C) Copyright 2003 + * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net + * + * Adapted for U-Boot version 2012-04-01 by Lothar Waßmann + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include ++#include +#include +#include + +static struct iim_regs *imx_iim = (void *)IMX_IIM_BASE; + +/* slen - string length, e.g.: 23 -> slen=2; abcd -> slen=4 */ +/* only convert hex value as string input. so "12" is 0x12. */ +static u32 quick_atoi(char *a, u32 slen) +{ + u32 i, num = 0, digit; + + for (i = 0; i < slen; i++) { + if (a[i] >= '0' && a[i] <= '9') { + digit = a[i] - '0'; + } else if (a[i] >= 'a' && a[i] <= 'f') { + digit = a[i] - 'a' + 10; + } else if (a[i] >= 'A' && a[i] <= 'F') { + digit = a[i] - 'A' + 10; + } else { + printf("ERROR: %c\n", a[i]); + return -1; + } + num = (num * 16) + digit; + } + + return num; +} + +static void fuse_op_start(void) +{ + /* Do not generate interrupt */ + writel(0, &imx_iim->statm); + /* clear the status bits and error bits */ + writel(0x3, &imx_iim->stat); + writel(0xfe, &imx_iim->err); +} + +/* + * The action should be either: + * POLL_FUSE_PRGD + * or: + * POLL_FUSE_SNSD + */ +static s32 poll_fuse_op_done(s32 action) +{ + u32 status, error; + + if (action != POLL_FUSE_PRGD && action != POLL_FUSE_SNSD) { + printf("%s(%d) invalid operation\n", __func__, action); + return -1; + } + + /* Poll busy bit till it is NOT set */ + while ((readl(&imx_iim->stat) & IIM_STAT_BUSY) != 0) + ; + + /* Test for successful write */ + status = readl(&imx_iim->stat); + error = readl(&imx_iim->err); + + if ((status & action) != 0 && \ + (error & (action >> IIM_ERR_SHIFT)) == 0) { + if (error) { + printf("Even though the operation" + "seems successful...\n"); + printf("There are some error(s) " + "at addr=%p: 0x%x\n", + &imx_iim->err, error); + } + return 0; + } + printf("%s(%d) failed\n", __func__, action); + printf("status address=%p, value=0x%x\n", + &imx_iim->stat, status); + printf("There are some error(s) at addr=%p: 0x%x\n", + &imx_iim->err, error); + return -1; +} + +static u32 sense_fuse(s32 bank, s32 row, s32 bit) +{ + s32 addr, addr_l, addr_h; + void *reg_addr; + + fuse_op_start(); + + addr = ((bank << 11) | (row << 3) | (bit & 0x7)); + /* Set IIM Program Upper Address */ + addr_h = (addr >> 8) & 0x000000FF; + /* Set IIM Program Lower Address */ + addr_l = (addr & 0x000000FF); + +#ifdef IIM_FUSE_DEBUG + printf("%s: addr_h=0x%x, addr_l=0x%x\n", + __func__, addr_h, addr_l); +#endif + writel(addr_h, &imx_iim->ua); + writel(addr_l, &imx_iim->la); + + /* Start sensing */ + writel(0x8, &imx_iim->fctl); + if (poll_fuse_op_done(POLL_FUSE_SNSD) != 0) { + printf("%s(bank: %d, row: %d, bit: %d failed\n", + __func__, bank, row, bit); + } + reg_addr = &imx_iim->sdat; + + return readl(reg_addr); +} + +int iim_read(int bank, char row) +{ + u32 fuse_val; + s32 err = 0; + + printf("Read fuse at bank:%d row:%d\n", bank, row); + fuse_val = sense_fuse(bank, row, 0); + printf("fuses at (bank:%d, row:%d) = 0x%x\n", bank, row, fuse_val); + + return err; +} + +/* Blow fuses based on the bank, row and bit positions (all 0-based) +*/ +static s32 fuse_blow_bit(s32 bank, s32 row, s32 bit) +{ + int addr, addr_l, addr_h, ret = -1; + + fuse_op_start(); + + /* Disable IIM Program Protect */ + writel(0xaa, &imx_iim->preg_p); + + addr = ((bank << 11) | (row << 3) | (bit & 0x7)); + /* Set IIM Program Upper Address */ + addr_h = (addr >> 8) & 0x000000FF; + /* Set IIM Program Lower Address */ + addr_l = (addr & 0x000000FF); + +#ifdef IIM_FUSE_DEBUG + printf("blowing addr_h=0x%x, addr_l=0x%x\n", addr_h, addr_l); +#endif + + writel(addr_h, &imx_iim->ua); + writel(addr_l, &imx_iim->la); + + /* Start Programming */ + writel(0x31, &imx_iim->fctl); + if (poll_fuse_op_done(POLL_FUSE_PRGD) == 0) + ret = 0; + + /* Enable IIM Program Protect */ + writel(0x0, &imx_iim->preg_p); + + return ret; +} + +static void fuse_blow_row(s32 bank, s32 row, s32 value) +{ + u32 reg, i; + + /* enable fuse blown */ + reg = readl(CCM_BASE_ADDR + 0x64); + reg |= 0x10; + writel(reg, CCM_BASE_ADDR + 0x64); + + for (i = 0; i < 8; i++) { + if (((value >> i) & 0x1) == 0) + continue; + if (fuse_blow_bit(bank, row, i) != 0) { + printf("fuse_blow_bit(bank: %d, row: %d, " + "bit: %d failed\n", + bank, row, i); + } + } + reg &= ~0x10; + writel(reg, CCM_BASE_ADDR + 0x64); +} + +int iim_blow(int bank, int row, int val) +{ + u32 fuse_val, err = 0; + + printf("Blowing fuse at bank:%d row:%d value:%d\n", + bank, row, val); + fuse_blow_row(bank, row, val); + fuse_val = sense_fuse(bank, row, 0); + printf("fuses at (bank:%d, row:%d) = 0x%x\n", bank, row, fuse_val); + + return err; +} + +int iim_blow_func(char *func_name, char *func_val) +{ + u32 value, i; + char *s; + char val[3]; + s32 err = 0; + + if (strcmp(func_name, "scc") == 0) { + /* fuse_blow scc + C3D153EDFD2EA9982226EF5047D3B9A0B9C7138EA87C028401D28C2C2C0B9AA2 */ + printf("Ready to burn SCC fuses\n"); + s = func_val; + for (i = 0; ; ++i) { + memcpy(val, s, 2); + val[2] = '\0'; + value = quick_atoi(val, 2); + /* printf("fuse_blow_row(2, %d, value=0x%x)\n", + i, value); */ + fuse_blow_row(2, i, value); + + if (*(++s) == '\0') { + printf("ERROR: Odd string input\n"); + err = -1; + break; + } + if (*(++s) == '\0') { + printf("Successful\n"); + break; + } + } + } else if (strcmp(func_name, "srk") == 0) { + /* fuse_blow srk + 418bccd09b53bee1ab59e2662b3c7877bc0094caee201052add49be8780dff95 */ + printf("Ready to burn SRK key fuses\n"); + s = func_val; + for (i = 0; ; ++i) { + memcpy(val, s, 2); + val[2] = '\0'; + value = quick_atoi(val, 2); + if (i == 0) { + /* 0x41 goes to SRK_HASH[255:248], + * bank 1, row 1 */ + fuse_blow_row(1, 1, value); + } else { + /* 0x8b in SRK_HASH[247:240] bank 3, row 1 */ + /* 0xcc in SRK_HASH[239:232] bank 3, row 2 */ + /* ... */ + fuse_blow_row(3, i, value); + + if (*(++s) == '\0') { + printf("ERROR: Odd string input\n"); + err = -1; + break; + } + if (*(++s) == '\0') { + printf("Successful\n"); + break; + } + } + } + } else if (strcmp(func_name, "fecmac") == 0) { + u8 ea[6] = { 0 }; + + if (func_val == NULL) { + /* Read the Mac address and print it */ + imx_get_mac_from_fuse(0, ea); + + printf("FEC MAC address: "); + printf("0x%02x:0x%02x:0x%02x:0x%02x:0x%02x:0x%02x\n\n", + ea[0], ea[1], ea[2], ea[3], ea[4], ea[5]); + + return 0; + } + + eth_parse_enetaddr(func_val, ea); + if (!is_valid_ether_addr(ea)) { + printf("Error: invalid mac address parameter!\n"); + err = -1; + } else { + for (i = 0; i < 6; ++i) + fuse_blow_row(1, i + 9, ea[i]); + } + } else { + printf("This command is not supported\n"); + } + + return err; +} + + diff --cc drivers/mmc/fsl_esdhc.c index db5278b64d,b90f3e7769..8ca2ae03b6 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@@ -193,7 -181,7 +193,7 @@@ static int esdhc_setup_data(struct mmc #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO uint wml_value; -- wml_value = data->blocksize/4; ++ wml_value = data->blocksize / 4; if (data->flags & MMC_DATA_READ) { if (wml_value > WML_RD_WML_MAX) @@@ -205,12 -193,14 +205,12 @@@ if (wml_value > WML_WR_WML_MAX) wml_value = WML_WR_WML_MAX_VAL; if ((esdhc_read32(®s->prsstat) & PRSSTAT_WPSPL) == 0) { -- printf("\nThe SD card is locked. Can not write to a locked card.\n\n"); -- return TIMEOUT; ++ printf("The SD card is locked. Can not write to a locked card.\n"); ++ return UNUSABLE_ERR; } + flush_dcache_range((unsigned long)data->src, + (unsigned long)data->src + data->blocks * data->blocksize); esdhc_clrsetbits32(®s->wml, WML_WR_WML_MASK, wml_value << 16); esdhc_write32(®s->dsaddr, (u32)data->src); @@@ -218,17 -208,16 +218,16 @@@ #else /* CONFIG_SYS_FSL_ESDHC_USE_PIO */ if (!(data->flags & MMC_DATA_READ)) { if ((esdhc_read32(®s->prsstat) & PRSSTAT_WPSPL) == 0) { -- printf("\nThe SD card is locked. " -- "Can not write to a locked card.\n\n"); -- return TIMEOUT; ++ printf("The SD card is locked. Can not write to a locked card.\n"); ++ return UNUSABLE_ERR; } esdhc_write32(®s->dsaddr, (u32)data->src); - } else + } else { esdhc_write32(®s->dsaddr, (u32)data->dest); + } #endif /* CONFIG_SYS_FSL_ESDHC_USE_PIO */ -- esdhc_write32(®s->blkattr, data->blocks << 16 | data->blocksize); ++ esdhc_write32(®s->blkattr, (data->blocks << 16) | data->blocksize); /* Calculate the timeout period for data transactions */ /* @@@ -245,26 -234,34 +244,34 @@@ * => timeout + 13 = log2(mmc->tran_speed/4) + 1 * => timeout + 13 = fls(mmc->tran_speed/4) */ -- timeout = fls(mmc->tran_speed/4); ++ timeout = fls(mmc->tran_speed / 4); timeout -= 13; if (timeout > 14) timeout = 14; -- -- if (timeout < 0) ++ else if (timeout < 0) timeout = 0; #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC_A001 if ((timeout == 4) || (timeout == 8) || (timeout == 12)) timeout++; #endif -- esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, timeout << 16); return 0; } -static void check_and_invalidate_dcache_range - (struct mmc_cmd *cmd, - struct mmc_data *data) { - unsigned start = (unsigned)data->dest ; ++static void check_and_invalidate_dcache_range(struct mmc_cmd *cmd, ++ struct mmc_data *data) ++{ ++ unsigned start = (unsigned)data->dest; + unsigned size = roundup(ARCH_DMA_MINALIGN, - data->blocks*data->blocksize); - unsigned end = start+size ; ++ data->blocks * data->blocksize); ++ unsigned end = start + size; ++ + invalidate_dcache_range(start, end); + } + /* * Sends a command out on the bus. Takes the mmc pointer, * a command pointer, and an optional data pointer. @@@ -274,25 -271,25 +281,33 @@@ esdhc_send_cmd(struct mmc *mmc, struct { uint xfertyp; uint irqstat; - struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; - volatile struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base; + struct fsl_esdhc_cfg *cfg = mmc->priv; + volatile struct fsl_esdhc *regs = cfg->esdhc_base; ++ unsigned long start; #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION) return 0; #endif -- esdhc_write32(®s->irqstat, -1); sync(); ++ start = get_timer_masked(); /* Wait for the bus to be idle */ while ((esdhc_read32(®s->prsstat) & PRSSTAT_CICHB) || -- (esdhc_read32(®s->prsstat) & PRSSTAT_CIDHB)) -- ; ++ (esdhc_read32(®s->prsstat) & PRSSTAT_CIDHB)) { ++ if (get_timer(start) > CONFIG_SYS_HZ) { ++ printf("%s: Timeout waiting for bus idle\n", __func__); ++ return TIMEOUT; ++ } ++ } -- while (esdhc_read32(®s->prsstat) & PRSSTAT_DLA) -- ; ++ start = get_timer_masked(); ++ while (esdhc_read32(®s->prsstat) & PRSSTAT_DLA) { ++ if (get_timer(start) > CONFIG_SYS_HZ) ++ return TIMEOUT; ++ } /* Wait at least 8 SD clock cycles before the next command */ /* @@@ -317,18 -314,41 +332,52 @@@ esdhc_write32(®s->cmdarg, cmd->cmdarg); #if defined(CONFIG_FSL_USDHC) esdhc_write32(®s->mixctrl, -- (esdhc_read32(®s->mixctrl) & 0xFFFFFF80) | (xfertyp & 0x7F)); ++ (esdhc_read32(®s->mixctrl) & ~0x7f) | (xfertyp & 0x7F)); esdhc_write32(®s->xfertyp, xfertyp & 0xFFFF0000); #else esdhc_write32(®s->xfertyp, xfertyp); #endif + + /* Mask all irqs */ + esdhc_write32(®s->irqsigen, 0); + ++ start = get_timer_masked(); /* Wait for the command to complete */ - while (!(esdhc_read32(®s->irqstat) & IRQSTAT_CC)) - while (!(esdhc_read32(®s->irqstat) & (IRQSTAT_CC | IRQSTAT_CTOE))) -- ; ++ while (!(esdhc_read32(®s->irqstat) & (IRQSTAT_CC | IRQSTAT_CTOE))) { ++ if (get_timer(start) > CONFIG_SYS_HZ) { ++ printf("%s: Timeout waiting for cmd completion\n", __func__); ++ return TIMEOUT; ++ } ++ } + + if (data && (data->flags & MMC_DATA_READ)) + check_and_invalidate_dcache_range(cmd, data); irqstat = esdhc_read32(®s->irqstat); esdhc_write32(®s->irqstat, irqstat); + /* Reset CMD and DATA portions on error */ + if (irqstat & (CMD_ERR | IRQSTAT_CTOE)) { + esdhc_write32(®s->sysctl, esdhc_read32(®s->sysctl) | + SYSCTL_RSTC); - while (esdhc_read32(®s->sysctl) & SYSCTL_RSTC) - ; ++ start = get_timer_masked(); ++ while (esdhc_read32(®s->sysctl) & SYSCTL_RSTC) { ++ if (get_timer(start) > CONFIG_SYS_HZ) ++ return TIMEOUT; ++ } + + if (data) { + esdhc_write32(®s->sysctl, + esdhc_read32(®s->sysctl) | + SYSCTL_RSTD); - while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTD)) - ; ++ start = get_timer_masked(); ++ while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTD)) { ++ if (get_timer(start) > CONFIG_SYS_HZ) ++ return TIMEOUT; ++ } + } + } + if (irqstat & CMD_ERR) return COMM_ERR; @@@ -355,32 -392,30 +421,50 @@@ #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO esdhc_pio_read_write(mmc, data); #else ++ unsigned long start = get_timer_masked(); ++ unsigned long data_timeout = data->blocks * ++ data->blocksize * 100 / mmc->bus_width / ++ (mmc->tran_speed / CONFIG_SYS_HZ) + CONFIG_SYS_HZ; ++ do { irqstat = esdhc_read32(®s->irqstat); -- if (irqstat & IRQSTAT_DTOE) ++ if (irqstat & IRQSTAT_DTOE) { ++ printf("MMC/SD data %s timeout\n", ++ data->flags & MMC_DATA_READ ? ++ "read" : "write"); return TIMEOUT; ++ } -- if (irqstat & DATA_ERR) ++ if (irqstat & DATA_ERR) { ++ printf("MMC/SD data error\n"); return COMM_ERR; ++ } ++ ++ if (get_timer(start) > data_timeout) { ++ printf("MMC/SD timeout waiting for %s xfer completion\n", ++ data->flags & MMC_DATA_READ ? ++ "read" : "write"); ++ return TIMEOUT; ++ } } while (!(irqstat & IRQSTAT_TC) && -- (esdhc_read32(®s->prsstat) & PRSSTAT_DLA)); - invalidate_dcache_range((unsigned long)data->dest, - (unsigned long)data->dest + data->blocks * data->blocksize); ++ (esdhc_read32(®s->prsstat) & PRSSTAT_DLA)); ++ ++ check_and_invalidate_dcache_range(cmd, data); #endif } -- esdhc_write32(®s->irqstat, -1); ++ esdhc_write32(®s->irqstat, irqstat); return 0; } - void set_sysctl(struct mmc *mmc, uint clock) + static void set_sysctl(struct mmc *mmc, uint clock) { - int sdhc_clk = gd->sdhc_clk; int div, pre_div; - struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; - volatile struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base; + struct fsl_esdhc_cfg *cfg = mmc->priv; + volatile struct fsl_esdhc *regs = cfg->esdhc_base; + int sdhc_clk = cfg->sdhc_clk; uint clk; if (clock < mmc->f_min) @@@ -498,12 -534,12 +583,14 @@@ int fsl_esdhc_initialize(bd_t *bis, str u32 caps, voltage_caps; if (!cfg) -- return -1; ++ return -EINVAL; - mmc = malloc(sizeof(struct mmc)); + mmc = kzalloc(sizeof(struct mmc), GFP_KERNEL); ++ if (!mmc) ++ return -ENOMEM; sprintf(mmc->name, "FSL_SDHC"); - regs = (struct fsl_esdhc *)cfg->esdhc_base; + regs = cfg->esdhc_base; /* First reset the eSDHC controller */ esdhc_reset(regs); @@@ -535,16 -574,16 +625,16 @@@ #endif if ((mmc->voltages & voltage_caps) == 0) { printf("voltage not supported by controller\n"); -- return -1; ++ return -EINVAL; } - mmc->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT; + mmc->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT | MMC_MODE_HC; if (caps & ESDHC_HOSTCAPBLT_HSS) mmc->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS; mmc->f_min = 400000; - mmc->f_max = MIN(gd->sdhc_clk, 52000000); - mmc->f_max = MIN(gd->arch.sdhc_clk, 52000000); ++ mmc->f_max = MIN(cfg->sdhc_clk, 52000000); mmc->b_max = 0; mmc_register(mmc); @@@ -556,9 -595,10 +646,11 @@@ int fsl_esdhc_mmc_init(bd_t *bis { struct fsl_esdhc_cfg *cfg; - cfg = malloc(sizeof(struct fsl_esdhc_cfg)); - memset(cfg, 0, sizeof(struct fsl_esdhc_cfg)); - cfg->esdhc_base = CONFIG_SYS_FSL_ESDHC_ADDR; + cfg = kzalloc(sizeof(struct fsl_esdhc_cfg), GFP_KERNEL); - ++ if (!cfg) ++ return -ENOMEM; + cfg->esdhc_base = (void __iomem *)CONFIG_SYS_FSL_ESDHC_ADDR; + cfg->sdhc_clk = gd->arch.sdhc_clk; return fsl_esdhc_initialize(bis, cfg); } diff --cc drivers/mmc/mmc.c index 596732e80e,72e8ce6da4..d26e89a88c --- a/drivers/mmc/mmc.c +++ b/drivers/mmc/mmc.c @@@ -643,9 -543,9 +543,10 @@@ static int mmc_send_op_cond(struct mmc udelay(1000); } while (!(cmd.response[0] & OCR_BUSY) && timeout--); -- if (timeout <= 0) ++ if (timeout <= 0) { ++debug("%s: timeout\n", __func__); return UNUSABLE_ERR; -- ++ } if (mmc_host_is_spi(mmc)) { /* read OCR for spi */ cmd.cmdidx = MMC_CMD_SPI_READ_OCR; cmd.resp_type = MMC_RSP_R3; diff --cc drivers/mmc/mxsmmc.c index 7f643d4b31,024df592f2..70c141cecf --- a/drivers/mmc/mxsmmc.c +++ b/drivers/mmc/mxsmmc.c @@@ -70,18 -142,11 +142,13 @@@ static in mxsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) { struct mxsmmc_priv *priv = (struct mxsmmc_priv *)mmc->priv; - struct mx28_ssp_regs *ssp_regs = priv->regs; + struct mxs_ssp_regs *ssp_regs = priv->regs; uint32_t reg; int timeout; - uint32_t data_count; uint32_t ctrl0; + const uint32_t busy_stat = SSP_STATUS_BUSY | SSP_STATUS_DATA_BUSY | + SSP_STATUS_CMD_BUSY; - #ifndef CONFIG_MXS_MMC_DMA - uint32_t *data_ptr; - #else - uint32_t cache_data_count; - #endif + int ret; debug("MMC%d: CMD%d\n", mmc->block_dev.dev, cmd->cmdidx); @@@ -194,68 -269,20 +266,19 @@@ if (!data) return 0; - data_count = data->blocksize * data->blocks; - timeout = get_timer(0); - - #ifdef CONFIG_MXS_MMC_DMA - if (data_count % ARCH_DMA_MINALIGN) - cache_data_count = roundup(data_count, ARCH_DMA_MINALIGN); - else - cache_data_count = data_count; - - if (data->flags & MMC_DATA_READ) { - priv->desc->cmd.data = MXS_DMA_DESC_COMMAND_DMA_WRITE; - priv->desc->cmd.address = (dma_addr_t)data->dest; - } else { - priv->desc->cmd.data = MXS_DMA_DESC_COMMAND_DMA_READ; - priv->desc->cmd.address = (dma_addr_t)data->src; - - /* Flush data to DRAM so DMA can pick them up */ - flush_dcache_range((uint32_t)priv->desc->cmd.address, - (uint32_t)(priv->desc->cmd.address + cache_data_count)); - } - - priv->desc->cmd.data |= MXS_DMA_DESC_IRQ | MXS_DMA_DESC_DEC_SEM | - (data_count << MXS_DMA_DESC_BYTES_OFFSET); - - - mxs_dma_desc_append(MXS_DMA_CHANNEL_AHB_APBH_SSP0, priv->desc); - if (mxs_dma_go(MXS_DMA_CHANNEL_AHB_APBH_SSP0)) { - printf("MMC%d: DMA transfer failed\n", mmc->block_dev.dev); - return COMM_ERR; - } - - /* The data arrived into DRAM, invalidate cache over them */ - if (data->flags & MMC_DATA_READ) { - invalidate_dcache_range((uint32_t)priv->desc->cmd.address, - (uint32_t)(priv->desc->cmd.address + cache_data_count)); - } - #else - if (data->flags & MMC_DATA_READ) { - data_ptr = (uint32_t *)data->dest; - while (data_count) { - reg = readl(&ssp_regs->hw_ssp_status); - if (!(reg & SSP_STATUS_FIFO_EMPTY)) { - *data_ptr++ = readl(&ssp_regs->hw_ssp_data); - data_count -= 4; - timeout = get_timer(0); - } else if ((get_timer(timeout) > MXSMMC_MAX_TIMEOUT) && - (readl(&ssp_regs->hw_ssp_status) & SSP_STATUS_FIFO_EMPTY)) { - break; - } + if (data->blocksize * data->blocks < MXSMMC_SMALL_TRANSFER) { + ret = mxsmmc_send_cmd_pio(priv, data); + if (ret) { - printf("MMC%d: Data timeout with command %d " - "(status 0x%08x)!\n", ++ printf("MMC%d: Data timeout with command %d (status 0x%08x)!\n", + mmc->block_dev.dev, cmd->cmdidx, reg); + return ret; } } else { - data_ptr = (uint32_t *)data->src; - while (data_count) { - reg = readl(&ssp_regs->hw_ssp_status); - if (!(reg & SSP_STATUS_FIFO_FULL)) { - writel(*data_ptr++, &ssp_regs->hw_ssp_data); - data_count -= 4; - timeout = get_timer(0); - } else if ((get_timer(timeout) > MXSMMC_MAX_TIMEOUT * 100) && - (readl(&ssp_regs->hw_ssp_status) & SSP_STATUS_FIFO_FULL)) { - break; - } + ret = mxsmmc_send_cmd_dma(priv, data); + if (ret) { + printf("MMC%d: DMA transfer failed\n", + mmc->block_dev.dev); + return ret; } } diff --cc drivers/mtd/nand/Makefile index 3dd21edb5a,c77c0c4f0f..1d4b72b07b --- a/drivers/mtd/nand/Makefile +++ b/drivers/mtd/nand/Makefile @@@ -38,12 -47,15 +47,16 @@@ COBJS-y += nand. COBJS-y += nand_bbt.o COBJS-y += nand_ids.o COBJS-y += nand_util.o - endif COBJS-y += nand_ecc.o COBJS-y += nand_base.o + + endif # not spl + + ifdef NORMAL_DRIVERS + COBJS-$(CONFIG_NAND_ECC_BCH) += nand_bch.o +COBJS-$(CONFIG_NAND_AM33XX) += am33xx_nand.o COBJS-$(CONFIG_NAND_ATMEL) += atmel_nand.o COBJS-$(CONFIG_DRIVER_NAND_BFIN) += bfin_nand.o COBJS-$(CONFIG_NAND_DAVINCI) += davinci_nand.o diff --cc drivers/mtd/nand/am33xx_nand.c index 40bfef1503,0000000000..14602ee263 mode 100644,000000..100644 --- a/drivers/mtd/nand/am33xx_nand.c +++ b/drivers/mtd/nand/am33xx_nand.c @@@ -1,918 -1,0 +1,916 @@@ +/* + * (C) Copyright 2012 Lothar Waßmann + * based on ti81xx_nand.c + * (C) Copyright 2004-2008 Texas Instruments, + * Mansoor Ahamed + * + * Derived from work done by Rohit Choraria for omap + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +struct nand_bch_priv { + uint8_t type; + uint8_t nibbles; +}; + +/* bch types */ +#define ECC_BCH4 0 +#define ECC_BCH8 1 +#define ECC_BCH16 2 + +/* BCH nibbles for diff bch levels */ +#define ECC_BCH4_NIBBLES 13 +#define ECC_BCH8_NIBBLES 26 +#define ECC_BCH16_NIBBLES 52 + +static uint8_t cs; +#ifndef CONFIG_SPL_BUILD +static struct nand_ecclayout hw_nand_oob = GPMC_NAND_HW_ECC_LAYOUT_KERNEL; +static struct nand_ecclayout hw_bch4_nand_oob = GPMC_NAND_HW_BCH4_ECC_LAYOUT; +static struct nand_ecclayout hw_bch16_nand_oob = GPMC_NAND_HW_BCH16_ECC_LAYOUT; +#endif +static struct nand_ecclayout hw_bch8_nand_oob = GPMC_NAND_HW_BCH8_ECC_LAYOUT; + - static struct gpmc *gpmc_cfg = (struct gpmc *)GPMC_BASE; - +static struct nand_bch_priv bch_priv = { + .type = ECC_BCH8, + .nibbles = ECC_BCH8_NIBBLES, +}; + +#ifndef CONFIG_SYS_NAND_NO_OOB +static uint8_t bbt_pattern[] = {'B', 'b', 't', '0' }; +static uint8_t mirror_pattern[] = {'1', 't', 'b', 'B' }; + +static struct nand_bbt_descr bbt_main_descr = { + .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE | + NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP, + .offs = 58, + .len = 4, + .veroffs = 62, + .maxblocks = 4, + .pattern = bbt_pattern, +}; + +static struct nand_bbt_descr bbt_mirror_descr = { + .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE | + NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP, + .offs = 58, + .len = 4, + .veroffs = 62, + .maxblocks = 4, + .pattern = mirror_pattern, +}; +#endif + +/* + * am33xx_read_bch8_result - Read BCH result for BCH8 level + * + * @mtd: MTD device structure + * @big_endian: When set read register 3 first + * @ecc_code: Read syndrome from BCH result registers + */ +static void am33xx_read_bch8_result(struct mtd_info *mtd, int big_endian, + uint8_t *ecc_code) +{ + uint32_t *ptr; + int i = 0, j; + + if (big_endian) { + u32 res; + ptr = &gpmc_cfg->bch_result_0_3[0].bch_result_x[3]; + res = readl(ptr); + ecc_code[i++] = res & 0xFF; + for (j = 0; j < 3; j++) { + u32 res = readl(--ptr); + + ecc_code[i++] = (res >> 24) & 0xFF; + ecc_code[i++] = (res >> 16) & 0xFF; + ecc_code[i++] = (res >> 8) & 0xFF; + ecc_code[i++] = res & 0xFF; + } + } else { + ptr = &gpmc_cfg->bch_result_0_3[0].bch_result_x[0]; + for (j = 0; j < 3; j++) { + u32 res = readl(ptr++); + + ecc_code[i++] = res & 0xFF; + ecc_code[i++] = (res >> 8) & 0xFF; + ecc_code[i++] = (res >> 16) & 0xFF; + ecc_code[i++] = (res >> 24) & 0xFF; + } + ecc_code[i++] = readl(ptr) & 0xFF; + } + ecc_code[i] = 0xff; +} + +/* + * am33xx_ecc_disable - Disable H/W ECC calculation + * + * @mtd: MTD device structure + * + */ +static void am33xx_ecc_disable(struct mtd_info *mtd) +{ + writel((readl(&gpmc_cfg->ecc_config) & ~0x1), + &gpmc_cfg->ecc_config); +} + +/* + * am33xx_nand_hwcontrol - Set the address pointers correctly for the + * following address/data/command operation + */ +static void am33xx_nand_hwcontrol(struct mtd_info *mtd, int32_t cmd, + uint32_t ctrl) +{ + register struct nand_chip *this = mtd->priv; + + debug("nand cmd %08x ctrl %08x\n", cmd, ctrl); + /* + * Point the IO_ADDR to DATA and ADDRESS registers instead + * of chip address + */ + switch (ctrl) { + case NAND_CTRL_CHANGE | NAND_CTRL_CLE: + this->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_cmd; + break; + case NAND_CTRL_CHANGE | NAND_CTRL_ALE: + this->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_adr; + break; + case NAND_CTRL_CHANGE | NAND_NCE: + this->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_dat; + } + + if (cmd != NAND_CMD_NONE) + writeb(cmd, this->IO_ADDR_W); +} + +/* + * am33xx_hwecc_init_bch - Initialize the BCH Hardware ECC for NAND flash in + * GPMC controller + * @mtd: MTD device structure + * @mode: Read/Write mode + */ +static void am33xx_hwecc_init_bch(struct nand_chip *chip, int32_t mode) +{ + uint32_t val, dev_width = (chip->options & NAND_BUSWIDTH_16) >> 1; + uint32_t unused_length = 0; + struct nand_bch_priv *bch = chip->priv; + + switch (bch->nibbles) { + case ECC_BCH4_NIBBLES: + unused_length = 3; + break; + case ECC_BCH8_NIBBLES: + unused_length = 2; + break; + case ECC_BCH16_NIBBLES: + unused_length = 0; + } + + /* Clear the ecc result registers, select ecc reg as 1 */ + writel(ECCCLEAR | ECCRESULTREG1, &gpmc_cfg->ecc_control); + + switch (mode) { + case NAND_ECC_WRITE: + /* eccsize1 config */ + val = ((unused_length + bch->nibbles) << 22); + break; + + case NAND_ECC_READ: + default: + /* by default eccsize0 selected for ecc1resultsize */ + /* eccsize0 config */ + val = (bch->nibbles << 12); + /* eccsize1 config */ + val |= (unused_length << 22); + } + /* ecc size configuration */ + writel(val, &gpmc_cfg->ecc_size_config); + /* by default 512bytes sector page is selected */ + /* set bch mode */ + val = (1 << 16); + /* bch4 / bch8 / bch16 */ + val |= (bch->type << 12); + /* set wrap mode to 1 */ + val |= (1 << 8); + val |= (dev_width << 7); + val |= (cs << 1); + /* enable ecc */ + /* val |= (1); */ /* should not enable ECC just init i.e. config */ + writel(val, &gpmc_cfg->ecc_config); +} + +#ifndef CONFIG_SPL_BUILD +/* + * am33xx_hwecc_init - Initialize the Hardware ECC for NAND flash in + * GPMC controller + * @mtd: MTD device structure + * + */ +static void am33xx_hwecc_init(struct nand_chip *chip) +{ + /* + * Init ECC Control Register + * Clear all ECC | Enable Reg1 + */ + writel(ECCCLEAR | ECCRESULTREG1, &gpmc_cfg->ecc_control); + writel(ECCSIZE1 | ECCSIZE0 | ECCSIZE0SEL, &gpmc_cfg->ecc_size_config); +} + +/* + * gen_true_ecc - This function will generate true ECC value, which + * can be used when correcting data read from NAND flash memory core + * + * @ecc_buf: buffer to store ecc code + * + * @return: re-formatted ECC value + */ +static uint32_t gen_true_ecc(uint8_t *ecc_buf) +{ + return ecc_buf[0] | (ecc_buf[1] << 16) | ((ecc_buf[2] & 0xF0) << 20) | + ((ecc_buf[2] & 0x0F) << 8); +} +#endif + +/* + * am33xx_rotate_ecc_bch - Rotate the syndrome bytes + * + * @mtd: MTD device structure + * @calc_ecc: ECC read from ECC registers + * @syndrome: Rotated syndrome will be retuned in this array + * + */ +static inline void am33xx_rotate_ecc_bch(struct mtd_info *mtd, uint8_t *calc_ecc, + uint8_t *syndrome) +{ + struct nand_chip *chip = mtd->priv; + struct nand_bch_priv *bch = chip->priv; + int n_bytes; + int i, j; + + switch (bch->type) { + case ECC_BCH4: + n_bytes = 8; + break; + + case ECC_BCH16: + n_bytes = 28; + break; + + case ECC_BCH8: + default: + n_bytes = 13; + } + + for (i = 0, j = (n_bytes - 1); i < n_bytes; i++, j--) + syndrome[i] = calc_ecc[j]; + syndrome[i] = 0xff; +} + + +/* + * am33xx_fix_errors_bch - Correct bch error in the data + * + * @mtd: MTD device structure + * @data: Data read from flash + * @error_count:Number of errors in data + * @error_loc: Locations of errors in the data + * + */ +static void am33xx_fix_errors_bch(struct mtd_info *mtd, uint8_t *data, + uint32_t error_count, uint32_t *error_loc) +{ + struct nand_chip *chip = mtd->priv; + struct nand_bch_priv *bch = chip->priv; + int count = 0; + uint32_t error_byte_pos; + uint32_t error_bit_mask; + uint32_t last_bit = (bch->nibbles * 4) - 1; + + /* Flip all bits as specified by the error location array. */ + /* FOR( each found error location flip the bit ) */ + for (count = 0; count < error_count; count++) { + if (error_loc[count] > last_bit) { + /* Remove the ECC spare bits from correction. */ + error_loc[count] -= (last_bit + 1); + /* Offset bit in data region */ + error_byte_pos = ((512 * 8) - (error_loc[count]) - 1) / 8; + /* Error Bit mask */ + error_bit_mask = 0x1 << (error_loc[count] % 8); + /* Toggle the error bit to make the correction. */ + data[error_byte_pos] ^= error_bit_mask; + } + } +} + +/* + * am33xx_correct_data_bch - Compares the ecc read from nand spare area + * with ECC registers values and corrects one bit error if it has occured + * + * @mtd: MTD device structure + * @dat: page data + * @read_ecc: ecc read from nand flash (ignored) + * @calc_ecc: ecc read from ECC registers + * + * @return 0 if data is OK or corrected, else returns -1 + */ +static inline int am33xx_read_page_bch(struct mtd_info *mtd, struct nand_chip *chip, + uint8_t *buf, int page); + +static int am33xx_correct_data_bch(struct mtd_info *mtd, uint8_t *dat, + uint8_t *read_ecc, uint8_t *calc_ecc) +{ + struct nand_chip *chip = mtd->priv; + struct nand_bch_priv *bch = chip->priv; + uint8_t syndrome[28]; + uint32_t error_count = 0; + uint32_t error_loc[8]; + uint32_t i, ecc_flag; + + ecc_flag = 0; + for (i = 0; i < (chip->ecc.bytes - 1); i++) + if (read_ecc[i] != 0xff) + ecc_flag = 1; + + if (!ecc_flag) + return 0; + + elm_reset(); + elm_config(bch->type); + + /* while reading ECC result we read it in big endian. + * Hence while loading to ELM we have rotate to get the right endian. + */ + am33xx_rotate_ecc_bch(mtd, calc_ecc, syndrome); + + /* use elm module to check for errors */ + if (elm_check_error(syndrome, bch->nibbles, &error_count, error_loc) != 0) { + printf("uncorrectable ECC error\n"); + return -1; + } + + /* correct bch error */ + if (error_count > 0) { + am33xx_fix_errors_bch(mtd, dat, error_count, error_loc); + } + + return 0; +} + +#ifndef CONFIG_SPL_BUILD +/* + * am33xx_correct_data - Compares the ecc read from nand spare area with ECC + * registers values and corrects one bit error if it has occured + * Further details can be had from Am33xx TRM and the following selected links: + * http://en.wikipedia.org/wiki/Hamming_code + * http://www.cs.utexas.edu/users/plaxton/c/337/05f/slides/ErrorCorrection-4.pdf + * + * @mtd: MTD device structure + * @dat: page data + * @read_ecc: ecc read from nand flash + * @calc_ecc: ecc read from ECC registers + * + * @return 0 if data is OK or corrected, else returns -1 + */ +static int am33xx_correct_data(struct mtd_info *mtd, uint8_t *dat, + uint8_t *read_ecc, uint8_t *calc_ecc) +{ + uint32_t orig_ecc, new_ecc, res, hm; + uint16_t parity_bits, byte; + int bit; + + /* Regenerate the orginal ECC */ + orig_ecc = gen_true_ecc(read_ecc); + new_ecc = gen_true_ecc(calc_ecc); + /* Get the XOR of real ecc */ + res = orig_ecc ^ new_ecc; + if (res) { + /* Get the hamming width */ + hm = hweight32(res); + /* Single bit errors can be corrected! */ + if (hm == 12) { + /* Correctable data! */ + parity_bits = res >> 16; + bit = (parity_bits & 0x7); + byte = (parity_bits >> 3) & 0x1FF; + /* Flip the bit to correct */ + dat[byte] ^= (0x1 << bit); + } else if (hm == 1) { + printf("am33xx_nand: Error: Corrupted ECC\n"); + /* ECC itself is corrupted */ + return 2; + } else { + /* + * hm distance != parity pairs OR one, could mean 2 bit + * error OR potentially be on a blank page.. + * orig_ecc: contains spare area data from nand flash. + * new_ecc: generated ecc while reading data area. + * Note: if the ecc = 0, all data bits from which it was + * generated are 0xFF. + * The 3 byte(24 bits) ecc is generated per 512byte + * chunk of a page. If orig_ecc(from spare area) + * is 0xFF && new_ecc(computed now from data area)=0x0, + * this means that data area is 0xFF and spare area is + * 0xFF. A sure sign of an erased page! + */ + if ((orig_ecc == 0x0FFF0FFF) && (new_ecc == 0x00000000)) + return 0; + printf("am33xx_nand: Error: Multibit error detected; hm=%d\n", + hm); + /* detected 2 bit error */ + return -1; + } + } + return 0; +} +#endif + +/* + * am33xx_calculate_ecc_bch - Read BCH ECC result + * + * @mtd: MTD structure + * @dat: unused + * @ecc_code: ecc_code buffer + */ +static int am33xx_calculate_ecc_bch(struct mtd_info *mtd, const uint8_t *dat, + uint8_t *ecc_code) +{ + struct nand_chip *chip = mtd->priv; + struct nand_bch_priv *bch = chip->priv; + int big_endian = 1; + int ret = 0; + + if (bch->type == ECC_BCH8) + am33xx_read_bch8_result(mtd, big_endian, ecc_code); + else /* BCH4 and BCH16 currently not supported */ + ret = -1; + + /* + * Stop reading anymore ECC vals and clear old results + * enable will be called if more reads are required + */ + am33xx_ecc_disable(mtd); + + return ret; +} + +#ifndef CONFIG_SPL_BUILD +/* + * am33xx_calculate_ecc - Generate non-inverted ECC bytes. + * + * Using noninverted ECC can be considered ugly since writing a blank + * page ie. padding will clear the ECC bytes. This is no problem as + * long nobody is trying to write data on the seemingly unused page. + * Reading an erased page will produce an ECC mismatch between + * generated and read ECC bytes that has to be dealt with separately. + * E.g. if page is 0xFF (fresh erased), and if HW ECC engine within GPMC + * is used, the result of read will be 0x0 while the ECC offsets of the + * spare area will be 0xFF which will result in an ECC mismatch. + * @mtd: MTD structure + * @dat: unused + * @ecc_code: ecc_code buffer + */ +static int am33xx_calculate_ecc(struct mtd_info *mtd, const uint8_t *dat, + uint8_t *ecc_code) +{ + u_int32_t val; + + /* Start Reading from HW ECC1_Result = 0x200 */ + val = readl(&gpmc_cfg->ecc1_result); + + ecc_code[0] = val & 0xFF; + ecc_code[1] = (val >> 16) & 0xFF; + ecc_code[2] = ((val >> 8) & 0x0F) | ((val >> 20) & 0xF0); + + /* + * Stop reading anymore ECC vals and clear old results + * enable will be called if more reads are required + */ + writel(0x000, &gpmc_cfg->ecc_config); + + return 0; +} +#endif + +#ifdef CONFIG_SPL_BUILD +static void am33xx_spl_nand_command(struct mtd_info *mtd, unsigned int cmd, + int col, int page) +{ + struct nand_chip *chip = mtd->priv; + + while (!chip->dev_ready(mtd)) + ; + + /* Emulate NAND_CMD_READOOB */ + if (cmd == NAND_CMD_READOOB) { + col += CONFIG_SYS_NAND_PAGE_SIZE; + cmd = NAND_CMD_READ0; + } + + /* Shift the offset from byte addressing to word addressing. */ + if (chip->options & NAND_BUSWIDTH_16) + col >>= 1; + + /* Begin command latch cycle */ + chip->cmd_ctrl(mtd, cmd, NAND_CTRL_CLE | NAND_CTRL_CHANGE); + /* Set ALE and clear CLE to start address cycle */ + /* Column address */ + chip->cmd_ctrl(mtd, col & 0xff, + NAND_CTRL_ALE | NAND_CTRL_CHANGE); /* A[7:0] */ + chip->cmd_ctrl(mtd, (col >> 8) & 0xff, NAND_CTRL_ALE); /* A[11:9] */ + /* Row address */ + chip->cmd_ctrl(mtd, page & 0xff, NAND_CTRL_ALE); /* A[19:12] */ + chip->cmd_ctrl(mtd, (page >> 8) & 0xff, + NAND_CTRL_ALE); /* A[27:20] */ +#ifdef CONFIG_SYS_NAND_5_ADDR_CYCLE + /* One more address cycle for devices > 128MiB */ + chip->cmd_ctrl(mtd, (page >> 16) & 0x0f, + NAND_CTRL_ALE); /* A[31:28] */ +#endif + chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE); + + /* Latch in address */ + chip->cmd_ctrl(mtd, cmd == NAND_CMD_RNDOUT ? + NAND_CMD_RNDOUTSTART : NAND_CMD_READSTART, + NAND_CTRL_CLE | NAND_CTRL_CHANGE); + chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE); + + /* + * Wait a while for the data to be ready + */ + while (!chip->dev_ready(mtd)) + ; +} +#endif + +/** + * am33xx_read_page_bch - hardware ecc based page read function + * @mtd: mtd info structure + * @chip: nand chip info structure + * @buf: buffer to store read data + * @page: page number to read + * + */ +static inline int am33xx_read_page_bch(struct mtd_info *mtd, struct nand_chip *chip, + uint8_t *buf, int page) +{ + int ret = 0; + int i, eccsize = chip->ecc.size; + int eccbytes = chip->ecc.bytes; + int eccsteps = chip->ecc.steps; + uint8_t *p = buf; + uint8_t *ecc_calc = chip->buffers->ecccalc; + uint8_t *ecc_code = chip->buffers->ecccode; + uint32_t *eccpos = chip->ecc.layout->eccpos; + uint8_t *oob = chip->oob_poi; + uint32_t data_pos = 0; + uint32_t oob_pos = (eccsize * eccsteps) + eccpos[0]; + + chip->cmdfunc(mtd, NAND_CMD_READ0, data_pos, page); + + for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize, + oob += eccbytes) { + chip->ecc.hwctl(mtd, NAND_ECC_READ); + /* read data */ + chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_pos, page); + chip->read_buf(mtd, p, eccsize); + /* read respective ecc from oob area */ + chip->cmdfunc(mtd, NAND_CMD_RNDOUT, oob_pos, page); + chip->read_buf(mtd, oob, eccbytes); + /* read syndrome */ + chip->ecc.calculate(mtd, p, &ecc_calc[i]); + + data_pos += eccsize; + oob_pos += eccbytes; + } + + for (i = 0; i < chip->ecc.total; i++) { + ecc_code[i] = chip->oob_poi[i]; + } + + eccsteps = chip->ecc.steps; + p = buf; + + for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { + int stat; + + stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]); + if (stat < 0) { + printf("am33xx_nand: uncorrectable ECC error in page %5d\n", + page); + mtd->ecc_stats.failed++; + return -EBADMSG; + } else if (stat) { + mtd->ecc_stats.corrected += stat; + printf("%s: corrected ECC errors: %d\n", __func__, stat); + ret += stat; + } + } + return ret; +} + +/* + * am33xx_enable_ecc_bch- This function enables the bch h/w ecc functionality + * @mtd: MTD device structure + * @mode: Read/Write mode + * + */ +static void am33xx_enable_ecc_bch(struct mtd_info *mtd, int32_t mode) +{ + struct nand_chip *chip = mtd->priv; + + am33xx_hwecc_init_bch(chip, mode); + /* enable ecc */ + writel(readl(&gpmc_cfg->ecc_config) | 0x1, &gpmc_cfg->ecc_config); +} + +#ifndef CONFIG_SPL_BUILD +/* + * am33xx_enable_ecc - This function enables the hardware ecc functionality + * @mtd: MTD device structure + * @mode: Read/Write mode + */ +static void am33xx_enable_ecc(struct mtd_info *mtd, int32_t mode) +{ + struct nand_chip *chip = mtd->priv; + uint32_t val, dev_width = (chip->options & NAND_BUSWIDTH_16) >> 1; + + switch (mode) { + case NAND_ECC_READ: + case NAND_ECC_WRITE: + /* Clear the ecc result registers, select ecc reg as 1 */ + writel(ECCCLEAR | ECCRESULTREG1, &gpmc_cfg->ecc_control); + + /* + * Size 0 = 0xFF, Size1 is 0xFF - both are 512 bytes + * tell all regs to generate size0 sized regs + * we just have a single ECC engine for all CS + */ + writel(ECCSIZE1 | ECCSIZE0 | ECCSIZE0SEL, + &gpmc_cfg->ecc_size_config); + val = (dev_width << 7) | (cs << 1) | (1 << 0); + writel(val, &gpmc_cfg->ecc_config); + break; + default: + printf("Error: Unrecognized Mode[%d]!\n", mode); + } +} + +/* + * __am33xx_nand_switch_ecc - switch the ECC operation ib/w h/w ecc + * (i.e. hamming / bch) and s/w ecc. + * The default is to come up on s/w ecc + * + * @nand: NAND chip datastructure + * @hardware: NAND_ECC_HW -switch to h/w ecc + * NAND_ECC_SOFT -switch to s/w ecc + * + * @mode: 0 - hamming code + * 1 - bch4 + * 2 - bch8 + * 3 - bch16 + */ +static void __am33xx_nand_switch_ecc(struct nand_chip *nand, + nand_ecc_modes_t hardware, int32_t mode) +{ + struct nand_bch_priv *bch; + + bch = nand->priv; + + /* Reset ecc interface */ + nand->ecc.read_page = NULL; + nand->ecc.write_page = NULL; + nand->ecc.read_oob = NULL; + nand->ecc.write_oob = NULL; + nand->ecc.hwctl = NULL; + nand->ecc.correct = NULL; + nand->ecc.calculate = NULL; + + nand->ecc.mode = hardware; + /* Setup the ecc configurations again */ + if (hardware == NAND_ECC_HW) { + if (mode) { + /* -1 for converting mode to bch type */ + bch->type = mode - 1; + debug("HW ECC BCH"); + switch (bch->type) { + case ECC_BCH4: + nand->ecc.bytes = 8; + nand->ecc.layout = &hw_bch4_nand_oob; + bch->nibbles = ECC_BCH4_NIBBLES; + debug("4 not supported\n"); + return; + + case ECC_BCH16: + nand->ecc.bytes = 26; + nand->ecc.layout = &hw_bch16_nand_oob; + bch->nibbles = ECC_BCH16_NIBBLES; + debug("16 not supported\n"); + return; + + case ECC_BCH8: + default: + nand->ecc.bytes = CONFIG_SYS_NAND_ECCBYTES; + nand->ecc.layout = &hw_bch8_nand_oob; + bch->nibbles = ECC_BCH8_NIBBLES; + debug("8 Selected\n"); + } + nand->ecc.mode = NAND_ECC_HW; + nand->ecc.size = 512; + nand->ecc.read_page = am33xx_read_page_bch; + nand->ecc.hwctl = am33xx_enable_ecc_bch; + nand->ecc.correct = am33xx_correct_data_bch; + nand->ecc.calculate = am33xx_calculate_ecc_bch; + am33xx_hwecc_init_bch(nand, NAND_ECC_READ); + } else { + nand->ecc.layout = &hw_nand_oob; + nand->ecc.size = 512; + nand->ecc.bytes = 3; + nand->ecc.hwctl = am33xx_enable_ecc; + nand->ecc.correct = am33xx_correct_data; + nand->ecc.calculate = am33xx_calculate_ecc; + am33xx_hwecc_init(nand); + debug("HW ECC Hamming Code selected\n"); + } + } else if (hardware == NAND_ECC_SOFT) { + /* Use mtd default settings */ + nand->ecc.layout = NULL; + debug("SW ECC selected\n"); + } else { + debug("ECC Disabled\n"); + } +} + +/* + * am33xx_nand_switch_ecc - switch the ECC operation ib/w h/w ecc + * (i.e. hamming / bch) and s/w ecc. + * The default is to come up on s/w ecc + * + * @hardware - NAND_ECC_HW -switch to h/w ecc + * NAND_ECC_SOFT -switch to s/w ecc + * + * @mode - 0 - hamming code + * 1 - bch4 + * 2 - bch8 + * 3 - bch16 + */ +void am33xx_nand_switch_ecc(nand_ecc_modes_t hardware, int32_t mode) +{ + struct nand_chip *nand; + struct mtd_info *mtd; + + if (nand_curr_device < 0 || + nand_curr_device >= CONFIG_SYS_MAX_NAND_DEVICE) { + printf("Error: Can't switch ecc, no devices available\n"); + return; + } + + mtd = &nand_info[nand_curr_device]; + nand = mtd->priv; + + __am33xx_nand_switch_ecc(nand, hardware, mode); + + nand->options |= NAND_OWN_BUFFERS; + /* Update NAND handling after ECC mode switch */ + nand_scan_tail(mtd); + nand->options &= ~NAND_OWN_BUFFERS; +} + +#else /* CONFIG_SPL_BUILD */ +/* Check wait pin as dev ready indicator */ +static int am33xx_spl_dev_ready(struct mtd_info *mtd) +{ + int ret; + +// printf("dev status: "); + ret = readl(&gpmc_cfg->status) & (1 << 8); +// printf("%d %08x\n", ret, gpmc_cfg->status); + return ret; +} +#endif + +/* + * Board-specific NAND initialization. The following members of the + * argument are board-specific: + * - IO_ADDR_R: address to read the 8 I/O lines of the flash device + * - IO_ADDR_W: address to write the 8 I/O lines of the flash device + * - cmd_ctrl: hardwarespecific function for accesing control-lines + * - waitfunc: hardwarespecific function for accesing device ready/busy line + * - ecc.hwctl: function to enable (reset) hardware ecc generator + * - ecc.mode: mode of ecc, see defines + * - chip_delay: chip dependent delay for transfering data from array to + * read regs (tR) + * - options: various chip options. They can partly be set to inform + * nand_scan about special functionality. See the defines for further + * explanation + */ +int board_nand_init(struct nand_chip *nand) +{ + /* int32_t gpmc_config = 0; */ + cs = 0; + + /* + * xloader/Uboot's gpmc configuration would have configured GPMC for + * nand type of memory. The following logic scans and latches on to the + * first CS with NAND type memory. + * TBD: need to make this logic generic to handle multiple CS NAND + * devices. + */ + while (cs < GPMC_MAX_CS) { + /* Check if NAND type is set */ + if ((readl(&gpmc_cfg->cs[cs].config1) & 0xC00) == 0x800) { + /* Found it!! */ + debug("Searching for NAND device @ GPMC CS:%d\n", cs); + break; + } + cs++; + } + if (cs >= GPMC_MAX_CS) { + printf("NAND: Unable to find NAND settings in " + "GPMC Configuration - quitting\n"); + return -ENODEV; + } + + nand->IO_ADDR_R = (void __iomem *)&gpmc_cfg->cs[cs].nand_dat; + nand->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_cmd; + + nand->cmd_ctrl = am33xx_nand_hwcontrol; + nand->options = NAND_NO_PADDING | NAND_CACHEPRG | NAND_NO_AUTOINCR; +#ifdef CONFIG_SYS_NAND_USE_FLASH_BBT +#ifdef CONFIG_SYS_NAND_NO_OOB + nand->options |= NAND_USE_FLASH_BBT | NAND_USE_FLASH_BBT_NO_OOB; +#else + nand->options |= NAND_USE_FLASH_BBT; + nand->bbt_td = &bbt_main_descr; + nand->bbt_md = &bbt_mirror_descr; +#endif /* CONFIG_SYS_NAND_NO_OOB */ +#endif /* CONFIG_SYS_NAND_USE_FLASH_BBT */ + + /* If we are 16 bit dev, our gpmc config tells us that */ + if ((readl(&gpmc_cfg->cs[cs].config1) & 0x3000) == 0x1000) { + nand->options |= NAND_BUSWIDTH_16; + } + + nand->chip_delay = 100; + + /* required in case of BCH */ + elm_init(); + + /* BCH info that will be correct for SPL or overridden otherwise. */ + nand->priv = &bch_priv; + + bch_priv.nibbles = ECC_BCH8_NIBBLES; + bch_priv.type = ECC_BCH8; + nand->ecc.mode = NAND_ECC_HW; + nand->ecc.layout = &hw_bch8_nand_oob; + nand->ecc.size = CONFIG_SYS_NAND_ECCSIZE; + nand->ecc.bytes = CONFIG_SYS_NAND_ECCBYTES; + nand->ecc.hwctl = am33xx_enable_ecc_bch; + nand->ecc.read_page = am33xx_read_page_bch; + nand->ecc.correct = am33xx_correct_data_bch; + nand->ecc.calculate = am33xx_calculate_ecc_bch; + +#ifndef CONFIG_SPL_BUILD + nand_curr_device = 0; +#else + nand->cmdfunc = am33xx_spl_nand_command; + + nand->ecc.steps = CONFIG_SYS_NAND_PAGE_SIZE / CONFIG_SYS_NAND_ECCSIZE; + nand->ecc.total = CONFIG_SYS_NAND_ECCBYTES * nand->ecc.steps; + + if (nand->options & NAND_BUSWIDTH_16) + nand->read_buf = nand_read_buf16; + else + nand->read_buf = nand_read_buf; + + nand->dev_ready = am33xx_spl_dev_ready; +#endif /* CONFIG_SPL_BUILD */ + am33xx_hwecc_init_bch(nand, NAND_ECC_READ); + + return 0; +} diff --cc drivers/mtd/nand/mxs_nand.c index a9cef16d7c,e38e151254..37ed099641 --- a/drivers/mtd/nand/mxs_nand.c +++ b/drivers/mtd/nand/mxs_nand.c @@@ -24,7 -24,8 +24,9 @@@ * with this program; if not, write to the Free Software Foundation, Inc., * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. */ ++//#define DEBUG + #include #include #include #include @@@ -34,18 -34,18 +35,28 @@@ #include #include #include ++#include ++#include #include #include #define MXS_NAND_DMA_DESCRIPTOR_COUNT 4 ++#ifndef CONFIG_MX6Q #define MXS_NAND_CHUNK_DATA_CHUNK_SIZE 512 ++#else ++#define MXS_NAND_CHUNK_DATA_CHUNK_SIZE (512 / 4) ++#endif ++ #define MXS_NAND_METADATA_SIZE 10 #define MXS_NAND_COMMAND_BUFFER_SIZE 32 ++/* BCH timeout in microseconds */ #define MXS_NAND_BCH_TIMEOUT 10000 ++static struct bch_regs *bch_regs = (void *)BCH_BASE_ADDRESS; ++static struct gpmi_regs *gpmi_regs = (void *)GPMI_BASE_ADDRESS; struct mxs_nand_info { int cur_chip; @@@ -72,6 -72,6 +83,109 @@@ uint32_t desc_index; }; ++#ifdef DEBUG ++#define dump_reg(b, r) __dump_reg(&b->r, #r) ++static inline void __dump_reg(void *addr, const char *name) ++{ ++ printf("%16s[%p]=%08x\n", name, addr, readl(addr)); ++} ++ ++#define dump_bch_reg(n) __dump_reg(&bch_regs->hw_bch_##n, #n) ++#define dump_gpmi_reg(n) __dump_reg(&gpmi_regs->hw_gpmi_##n, #n) ++static inline void dump_regs(void) ++{ ++ printf("BCH:\n"); ++ dump_bch_reg(ctrl); ++ dump_bch_reg(status0); ++ dump_bch_reg(mode); ++ dump_bch_reg(debug0); ++ dump_bch_reg(dbgkesread); ++ dump_bch_reg(dbgcsferead); ++ dump_bch_reg(dbgsyndegread); ++ dump_bch_reg(dbgahbmread); ++ dump_bch_reg(blockname); ++ dump_bch_reg(version); ++ ++ printf("\nGPMI:\n"); ++ dump_gpmi_reg(ctrl0); ++ dump_gpmi_reg(eccctrl); ++ dump_gpmi_reg(ecccount); ++ dump_gpmi_reg(payload); ++ dump_gpmi_reg(auxiliary); ++ dump_gpmi_reg(ctrl1); ++ dump_gpmi_reg(data); ++ dump_gpmi_reg(stat); ++ dump_gpmi_reg(debug); ++ dump_gpmi_reg(version); ++ dump_gpmi_reg(debug2); ++ dump_gpmi_reg(debug3); ++} ++ ++static inline int dbg_addr(void *addr) ++{ ++ if (((unsigned long)addr & ~0xfff) == BCH_BASE_ADDRESS) ++ return 1; ++ return 1; ++} ++ ++static inline u32 mxs_readl(void *addr, ++ const char *fn, int ln) ++{ ++ u32 val = readl(addr); ++ static void *last_addr; ++ static u32 last_val; ++ ++ if (!dbg_addr(addr)) ++ return val; ++ ++ if (addr != last_addr || last_val != val) { ++ printf("%s@%d: Read %08x from %p\n", fn, ln, val, addr); ++ last_addr = addr; ++ last_val = val; ++ } ++ return val; ++} ++ ++static inline void mxs_writel(u32 val, void *addr, ++ const char *fn, int ln) ++{ ++ if (dbg_addr(addr)) ++ printf("%s@%d: Writing %08x to %p...", fn, ln, val, addr); ++ writel(val, addr); ++ if (dbg_addr(addr)) ++ printf(" result: %08x\n", readl(addr)); ++} ++ ++#undef readl ++#define readl(a) mxs_readl(a, __func__, __LINE__) ++ ++#undef writel ++#define writel(v, a) mxs_writel(v, a, __func__, __LINE__) ++static inline void memdump(const void *addr, size_t len) ++{ ++ const char *buf = addr; ++ int i; ++ ++ for (i = 0; i < len; i++) { ++ if (i % 16 == 0) { ++ if (i > 0) ++ printf("\n"); ++ printf("%p:", &buf[i]); ++ } ++ printf(" %02x", buf[i]); ++ } ++ printf("\n"); ++} ++#else ++static inline void memdump(void *addr, size_t len) ++{ ++} ++ ++static inline void dump_regs(void) ++{ ++} ++#endif ++ struct nand_ecclayout fake_ecc_layout; /* @@@ -133,9 -133,9 +247,10 @@@ static void mxs_nand_return_dma_descs(s info->desc_index = 0; } --static uint32_t mxs_nand_ecc_chunk_cnt(uint32_t page_data_size) ++static uint32_t mxs_nand_ecc_chunk_cnt(struct mtd_info *mtd) { -- return page_data_size / MXS_NAND_CHUNK_DATA_CHUNK_SIZE; ++ struct nand_chip *nand = mtd->priv; ++ return mtd->writesize / nand->ecc.size; } static uint32_t mxs_nand_ecc_size_in_bits(uint32_t ecc_strength) @@@ -148,6 -148,6 +263,27 @@@ static uint32_t mxs_nand_aux_status_off return (MXS_NAND_METADATA_SIZE + 0x3) & ~0x3; } ++static int mxs_nand_gpmi_init(void) ++{ ++ int ret; ++ ++ /* Reset the GPMI block. */ ++ ret = mxs_reset_block(&gpmi_regs->hw_gpmi_ctrl0_reg); ++ if (ret) ++ return ret; ++ ++ /* ++ * Choose NAND mode, set IRQ polarity, disable write protection and ++ * select BCH ECC. ++ */ ++ clrsetbits_le32(&gpmi_regs->hw_gpmi_ctrl1, ++ GPMI_CTRL1_GPMI_MODE, ++ GPMI_CTRL1_ATA_IRQRDY_POLARITY | GPMI_CTRL1_DEV_RESET | ++ GPMI_CTRL1_BCH_MODE); ++ writel(0x500 << 16, &gpmi_regs->hw_gpmi_timing1); ++ return 0; ++} ++ static inline uint32_t mxs_nand_get_ecc_strength(uint32_t page_data_size, uint32_t page_oob_size) { @@@ -233,12 -233,12 +369,15 @@@ static uint32_t mxs_nand_mark_bit_offse */ static int mxs_nand_wait_for_bch_complete(void) { - struct mx28_bch_regs *bch_regs = (struct mx28_bch_regs *)MXS_BCH_BASE; - struct mxs_bch_regs *bch_regs = (struct mxs_bch_regs *)MXS_BCH_BASE; int timeout = MXS_NAND_BCH_TIMEOUT; int ret; - ret = mx28_wait_mask_set(&bch_regs->hw_bch_ctrl_reg, + ret = mxs_wait_mask_set(&bch_regs->hw_bch_ctrl_reg, BCH_CTRL_COMPLETE_IRQ, timeout); ++ if (ret) { ++ debug("%s@%d: %d\n", __func__, __LINE__, ret); ++ mxs_nand_gpmi_init(); ++ } writel(BCH_CTRL_COMPLETE_IRQ, &bch_regs->hw_bch_ctrl_clr); @@@ -322,8 -322,8 +461,15 @@@ static void mxs_nand_cmd_ctrl(struct mt /* Execute the DMA chain. */ ret = mxs_dma_go(channel); -- if (ret) -- printf("MXS NAND: Error sending command\n"); ++ if (ret) { ++ int i; ++ ++ printf("MXS NAND: Error sending command %08lx\n", d->cmd.pio_words[0]); ++ for (i = 0; i < nand_info->cmd_queue_len; i++) { ++ printf("%02x ", nand_info->cmd_buf[i]); ++ } ++ printf("\n"); ++ } mxs_nand_return_dma_descs(nand_info); @@@ -338,8 -338,8 +484,6 @@@ static int mxs_nand_device_ready(struc { struct nand_chip *chip = mtd->priv; struct mxs_nand_info *nand_info = chip->priv; - struct mx28_gpmi_regs *gpmi_regs = - (struct mx28_gpmi_regs *)MXS_GPMI_BASE; - struct mxs_gpmi_regs *gpmi_regs = - (struct mxs_gpmi_regs *)MXS_GPMI_BASE; uint32_t tmp; tmp = readl(&gpmi_regs->hw_gpmi_stat); @@@ -374,7 -374,7 +518,7 @@@ static void mxs_nand_swap_block_mark(st uint32_t src; uint32_t dst; -- ++return; bit_offset = mxs_nand_mark_bit_offset(mtd); buf_offset = mxs_nand_mark_byte_offset(mtd); @@@ -389,6 -389,6 +533,9 @@@ dst = oob_buf[0]; ++ debug("Swapping byte %02x @ %03x.%d with %02x @ %03x\n", ++ src & 0xff, buf_offset, bit_offset, dst & 0xff, 0); ++ oob_buf[0] = src; data_buf[buf_offset] &= ~(0xff << bit_offset); @@@ -419,6 -419,6 +566,8 @@@ static void mxs_nand_read_buf(struct mt return; } ++ memset(buf, 0xee, length); ++ /* Compile the DMA descriptor - a descriptor that reads data. */ d = mxs_nand_get_dma_desc(nand_info); d->cmd.data = @@@ -437,7 -437,7 +586,7 @@@ length; mxs_dma_desc_append(channel, d); -- ++#ifndef CONFIG_MX6Q /* * A DMA descriptor that waits for the command to end and the chip to * become ready. @@@ -461,11 -461,11 +610,11 @@@ GPMI_CTRL0_ADDRESS_NAND_DATA; mxs_dma_desc_append(channel, d); -- ++#endif /* Execute the DMA chain. */ ret = mxs_dma_go(channel); if (ret) { -- printf("MXS NAND: DMA read error\n"); ++ printf("%s: DMA read error\n", __func__); goto rtn; } @@@ -527,7 -527,7 +676,7 @@@ static void mxs_nand_write_buf(struct m /* Execute the DMA chain. */ ret = mxs_dma_go(channel); if (ret) -- printf("MXS NAND: DMA write error\n"); ++ printf("%s: DMA write error\n", __func__); mxs_nand_return_dma_descs(nand_info); } @@@ -642,7 -630,7 +791,7 @@@ static int mxs_nand_ecc_read_page(struc /* Execute the DMA chain. */ ret = mxs_dma_go(channel); if (ret) { -- printf("MXS NAND: DMA read error\n"); ++ printf("%s: DMA read error\n", __func__); goto rtn; } @@@ -660,7 -648,7 +809,7 @@@ /* Loop over status bytes, accumulating ECC status. */ status = nand_info->oob_buf + mxs_nand_aux_status_offset(); -- for (i = 0; i < mxs_nand_ecc_chunk_cnt(mtd->writesize); i++) { ++ for (i = 0; i < mxs_nand_ecc_chunk_cnt(mtd); i++) { if (status[i] == 0x00) continue; @@@ -750,13 -736,13 +899,13 @@@ static void mxs_nand_ecc_write_page(str /* Execute the DMA chain. */ ret = mxs_dma_go(channel); if (ret) { -- printf("MXS NAND: DMA write error\n"); ++ printf("%s: DMA write error\n", __func__); goto rtn; } ret = mxs_nand_wait_for_bch_complete(); if (ret) { -- printf("MXS NAND: BCH write timeout\n"); ++ printf("%s: BCH write timeout\n", __func__); goto rtn; } @@@ -982,21 -968,14 +1131,25 @@@ static int mxs_nand_scan_bbt(struct mtd { struct nand_chip *nand = mtd->priv; struct mxs_nand_info *nand_info = nand->priv; - struct mx28_bch_regs *bch_regs = (struct mx28_bch_regs *)MXS_BCH_BASE; - struct mxs_bch_regs *bch_regs = (struct mxs_bch_regs *)MXS_BCH_BASE; uint32_t tmp; /* Configure BCH and set NFC geometry */ - mxs_reset_block(&bch_regs->hw_bch_ctrl_reg); + if (readl(&bch_regs->hw_bch_ctrl_reg) & + (BCH_CTRL_SFTRST | BCH_CTRL_CLKGATE)) + /* When booting from NAND the BCH engine will already + * be operational and obviously does not like being reset here. + * There will be occasional read errors upon boot when this + * reset is done. + */ - mx28_reset_block(&bch_regs->hw_bch_ctrl_reg); ++ mxs_reset_block(&bch_regs->hw_bch_ctrl_reg); ++ readl(&bch_regs->hw_bch_ctrl_reg); ++ ++ debug("mtd->writesize=%d\n", mtd->writesize); ++ debug("mtd->oobsize=%d\n", mtd->oobsize); ++ debug("ecc_strength=%d\n", mxs_nand_get_ecc_strength(mtd->writesize, mtd->oobsize)); /* Configure layout 0 */ -- tmp = (mxs_nand_ecc_chunk_cnt(mtd->writesize) - 1) ++ tmp = (mxs_nand_ecc_chunk_cnt(mtd) - 1) << BCH_FLASHLAYOUT0_NBLOCKS_OFFSET; tmp |= MXS_NAND_METADATA_SIZE << BCH_FLASHLAYOUT0_META_SIZE_OFFSET; tmp |= (mxs_nand_get_ecc_strength(mtd->writesize, mtd->oobsize) >> 1) @@@ -1050,7 -1029,7 +1203,7 @@@ int mxs_nand_alloc_buffers(struct mxs_n /* DMA buffers */ buf = memalign(MXS_DMA_ALIGNMENT, nand_info->data_buf_size); if (!buf) { -- printf("MXS NAND: Error allocating DMA buffers\n"); ++ printf("%s: Error allocating DMA buffers\n", __func__); return -ENOMEM; } @@@ -1077,53 -1056,56 +1230,56 @@@ */ int mxs_nand_init(struct mxs_nand_info *info) { - struct mx28_gpmi_regs *gpmi_regs = - (struct mx28_gpmi_regs *)MXS_GPMI_BASE; - struct mxs_gpmi_regs *gpmi_regs = - (struct mxs_gpmi_regs *)MXS_GPMI_BASE; - struct mxs_bch_regs *bch_regs = - (struct mxs_bch_regs *)MXS_BCH_BASE; -- int i = 0, j; ++ int ret; ++ int i; info->desc = malloc(sizeof(struct mxs_dma_desc *) * MXS_NAND_DMA_DESCRIPTOR_COUNT); -- if (!info->desc) ++ if (!info->desc) { ++ printf("MXS NAND: Unable to allocate DMA descriptor table\n"); ++ ret = -ENOMEM; goto err1; ++ } ++ ++ mxs_dma_init(); /* Allocate the DMA descriptors. */ for (i = 0; i < MXS_NAND_DMA_DESCRIPTOR_COUNT; i++) { info->desc[i] = mxs_dma_desc_alloc(); -- if (!info->desc[i]) ++ if (!info->desc[i]) { ++ printf("MXS NAND: Unable to allocate DMA descriptors\n"); ++ ret = -ENOMEM; goto err2; ++ } } /* Init the DMA controller. */ -- for (j = MXS_DMA_CHANNEL_AHB_APBH_GPMI0; -- j <= MXS_DMA_CHANNEL_AHB_APBH_GPMI7; j++) { -- if (mxs_dma_init_channel(j)) ++ for (i = 0; i < CONFIG_SYS_NAND_MAX_CHIPS; i++) { ++ const int chan = MXS_DMA_CHANNEL_AHB_APBH_GPMI0 + i; ++ ++ ret = mxs_dma_init_channel(chan); ++ if (ret) { ++ printf("Failed to initialize DMA channel %d\n", chan); goto err3; ++ } } -- /* Reset the GPMI block. */ - mx28_reset_block(&gpmi_regs->hw_gpmi_ctrl0_reg); - mxs_reset_block(&gpmi_regs->hw_gpmi_ctrl0_reg); - mxs_reset_block(&bch_regs->hw_bch_ctrl_reg); -- -- /* -- * Choose NAND mode, set IRQ polarity, disable write protection and -- * select BCH ECC. -- */ -- clrsetbits_le32(&gpmi_regs->hw_gpmi_ctrl1, -- GPMI_CTRL1_GPMI_MODE, -- GPMI_CTRL1_ATA_IRQRDY_POLARITY | GPMI_CTRL1_DEV_RESET | -- GPMI_CTRL1_BCH_MODE); ++ ret = mxs_nand_gpmi_init(); ++ if (ret) ++ goto err3; return 0; err3: -- for (--j; j >= 0; j--) -- mxs_dma_release(j); ++ for (--i; i >= 0; i--) ++ mxs_dma_release(i + MXS_DMA_CHANNEL_AHB_APBH_GPMI0); ++ i = MXS_NAND_DMA_DESCRIPTOR_COUNT - 1; err2: free(info->desc); --err1: for (--i; i >= 0; i--) mxs_dma_desc_free(info->desc[i]); -- printf("MXS NAND: Unable to allocate DMA descriptors\n"); -- return -ENOMEM; ++err1: ++ return ret; } /*! diff --cc drivers/mtd/nand/nand_base.c index de2c713bf1,a2d06be99f..d98e146d6f --- a/drivers/mtd/nand/nand_base.c +++ b/drivers/mtd/nand/nand_base.c @@@ -3118,6 -3119,6 +3117,8 @@@ int nand_scan_tail(struct mtd_info *mtd chip->ecc.steps = mtd->writesize / chip->ecc.size; if (chip->ecc.steps * chip->ecc.size != mtd->writesize) { printk(KERN_WARNING "Invalid ecc parameters\n"); ++ printk(KERN_WARNING "steps=%d size=%d writesize=%d\n", ++ chip->ecc.steps, chip->ecc.size, mtd->writesize); BUG(); } chip->ecc.total = chip->ecc.steps * chip->ecc.bytes; diff --cc drivers/net/Makefile index 987c41b83a,786a6567a5..7788f1ba6e --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@@ -70,8 -69,8 +69,9 @@@ COBJS-$(CONFIG_SH_ETHER) += sh_eth. COBJS-$(CONFIG_SMC91111) += smc91111.o COBJS-$(CONFIG_SMC911X) += smc911x.o COBJS-$(CONFIG_DRIVER_TI_EMAC) += davinci_emac.o +COBJS-$(CONFIG_DRIVER_TI_CPSW) += cpsw.o COBJS-$(CONFIG_TSEC_ENET) += tsec.o fsl_mdio.o + COBJS-$(CONFIG_DRIVER_TI_CPSW) += cpsw.o COBJS-$(CONFIG_FMAN_ENET) += fsl_mdio.o COBJS-$(CONFIG_TSI108_ETH) += tsi108_eth.o COBJS-$(CONFIG_ULI526X) += uli526x.o diff --cc drivers/net/cpsw.c index d4c0818397,db04795dfc..cf3f553194 --- a/drivers/net/cpsw.c +++ b/drivers/net/cpsw.c @@@ -26,11 -20,12 +20,12 @@@ #include #include #include -#include #include #include + #include +#include - #define BITMASK(bits) ((1 << (bits)) - 1) + #define BITMASK(bits) (BIT(bits) - 1) #define PHY_REG_MASK 0x1f #define PHY_ID_MASK 0x1f #define NUM_DESCS (PKTBUFSRX * 2) @@@ -79,13 -84,13 +84,13 @@@ struct cpsw_mdio_regs u32 __reserved_1[20]; struct { - u32 access; - u32 physel; - #define USERACCESS_GO (1 << 31) - #define USERACCESS_WRITE (1 << 30) - #define USERACCESS_ACK (1 << 29) + u32 access; + u32 physel; + #define USERACCESS_GO BIT(31) + #define USERACCESS_WRITE BIT(30) + #define USERACCESS_ACK BIT(29) -#define USERACCESS_READ (0) -#define USERACCESS_DATA (0xffff) +#define USERACCESS_READ 0 +#define USERACCESS_DATA 0xffff } user[0]; }; @@@ -188,12 -188,9 +188,12 @@@ struct cpdma_desc u32 hw_buffer; u32 hw_len; u32 hw_mode; - /* software fields */ - u32 sw_buffer; - u32 sw_len; +} __attribute__((aligned(CONFIG_SYS_CACHELINE_SIZE))); + +struct cpsw_desc { - volatile void *sw_buffer; ++ void *sw_buffer; + struct cpsw_desc *next; + struct cpdma_desc *dma_desc; }; struct cpdma_chan { @@@ -209,9 -206,13 +209,13 @@@ #define chan_read(chan, fld) __raw_readl((chan)->fld) #define chan_read_ptr(chan, fld) ((void *)__raw_readl((chan)->fld)) + #define for_each_slave(slave, priv) \ + for (slave = (priv)->slaves; slave != (priv)->slaves + \ - (priv)->data.slaves; slave++) ++ (priv)->data->slaves; slave++) + struct cpsw_priv { struct eth_device *dev; - struct cpsw_platform_data data; + struct cpsw_platform_data *data; int host_port; struct cpsw_regs *regs; @@@ -453,37 -449,37 +452,38 @@@ static struct cpsw_mdio_regs *mdio_regs /* wait until hardware is ready for another user access */ static inline u32 wait_for_user_access(void) { - int timeout = 1000; - u32 reg = 0; + int timeout = MDIO_TIMEOUT; + u32 reg; - while (timeout-- && - ((reg = __raw_readl(&mdio_regs->user[0].access)) & USERACCESS_GO)) - udelay(10); - - if (timeout == -1) { - printf("wait_for_user_access Timeout\n"); - return -ETIMEDOUT; + while ((reg = __raw_readl(&mdio_regs->user[0].access)) & USERACCESS_GO) { + udelay(1); + if (--timeout <= 0) { + printf("TIMEOUT waiting for USERACCESS_GO\n"); + return -1; + } } + return reg; } /* wait until hardware state machine is idle */ static inline void wait_for_idle(void) { - int timeout = 1000; + int timeout = MDIO_TIMEOUT; - while (timeout-- && - ((__raw_readl(&mdio_regs->control) & CONTROL_IDLE) == 0)) - udelay(10); - - if (timeout == -1) - printf("wait_for_idle Timeout\n"); + while ((__raw_readl(&mdio_regs->control) & CONTROL_IDLE) == 0) { + if (--timeout <= 0) { + printf("TIMEOUT waiting for state machine idle\n"); + break; + } + udelay(1); + } } - static int cpsw_mdio_read(const char *devname, unsigned char phy_id, - unsigned char phy_reg, unsigned short *data) + static int cpsw_mdio_read(struct mii_dev *bus, int phy_id, + int dev_addr, int phy_reg) { + unsigned short data; u32 reg; if (phy_reg & ~PHY_REG_MASK || phy_id & ~PHY_ID_MASK) @@@ -533,19 -531,19 +535,22 @@@ static void cpsw_mdio_init(char *name, */ udelay(1000); - miiphy_register(name, cpsw_mdio_read, cpsw_mdio_write); + bus->read = cpsw_mdio_read; + bus->write = cpsw_mdio_write; + sprintf(bus->name, name); + + mdio_register(bus); } - static inline void soft_reset(void *reg) + /* Set a self-clearing bit in a register, and wait for it to clear */ + static inline void setbit_and_wait_for_clear32(void *addr) { + int loops = 0; + - debug("%s %p\n", __func__, reg); - __raw_writel(1, reg); - while (__raw_readl(reg) & 1) { + __raw_writel(CLEAR_BIT, addr); + while (__raw_readl(addr) & CLEAR_BIT) - ; + loops++; - } + debug("%s: reset finished after %u loops\n", __func__, loops); } #define mac_hi(mac) (((mac)[0] << 0) | ((mac)[1] << 8) | \ @@@ -559,51 -557,24 +564,69 @@@ static void cpsw_set_slave_mac(struct c __raw_writel(mac_lo(priv->dev->enetaddr), &slave->regs->sa_lo); } +#define NUM_TRIES 50 ++#if 1 +static void cpsw_slave_update_link(struct cpsw_slave *slave, + struct cpsw_priv *priv, int *link) +{ - char *name = priv->dev->name; - int phy_id = slave->data->phy_id; - int speed, duplex; - unsigned short reg; ++ struct phy_device *phy = priv->phydev; + u32 mac_control = 0; + int retries = NUM_TRIES; + - while (retries-- > 0) { - if (miiphy_read(name, phy_id, MII_BMSR, ®)) { - printf("Failed to read PHY reg\n"); - return; /* could not read, assume no link */ ++ do { ++ phy_startup(phy); ++ *link = phy->link; ++ ++ if (*link) { /* link up */ ++ mac_control = priv->data->mac_control; ++ if (phy->speed == 1000) ++ mac_control |= GIGABITEN; ++ if (phy->duplex == DUPLEX_FULL) ++ mac_control |= FULLDUPLEXEN; ++ if (phy->speed == 100) ++ mac_control |= MIIEN; ++ } else { ++ udelay(10000); + } ++ } while (!*link && retries-- > 0); ++ debug("%s: mac_control: %08x -> %08x after %u loops\n", __func__, ++ slave->mac_control, mac_control, NUM_TRIES - retries); + - if (reg & BMSR_LSTATUS) { /* link up */ - speed = miiphy_speed(name, phy_id); - duplex = miiphy_duplex(name, phy_id); ++ if (mac_control == slave->mac_control) ++ return; + - *link = 1; - mac_control = priv->data->mac_control; - if (speed == 10) - mac_control |= BIT(18); /* In Band mode */ - else if (speed == 100) - mac_control |= BIT(15); - else if (speed == 1000) { - if (priv->data->gigabit_en) - mac_control |= BIT(7); - else { - /* Disable gigabit as it's non-functional */ - mac_control &= ~BIT(7); - speed = 100; - } - } ++ if (mac_control) { ++ printf("link up on port %d, speed %d, %s duplex\n", ++ slave->slave_num, phy->speed, ++ (phy->duplex == DUPLEX_FULL) ? "full" : "half"); ++ } else { ++ printf("link down on port %d\n", slave->slave_num); ++ } + - if (duplex == FULL) - mac_control |= BIT(0); /* FULLDUPLEXEN */ - break; - } - udelay(100000); ++ __raw_writel(mac_control, &slave->sliver->mac_control); ++ slave->mac_control = mac_control; ++} ++#else + static void cpsw_slave_update_link(struct cpsw_slave *slave, + struct cpsw_priv *priv, int *link) + { + struct phy_device *phy = priv->phydev; + u32 mac_control = 0; + + phy_startup(phy); + *link = phy->link; + + if (*link) { /* link up */ + mac_control = priv->data.mac_control; + if (phy->speed == 1000) + mac_control |= GIGABITEN; + if (phy->duplex == DUPLEX_FULL) + mac_control |= FULLDUPLEXEN; + if (phy->speed == 100) + mac_control |= MIIEN; } + debug("%s: mac_control: %08x -> %08x after %u loops\n", __func__, + slave->mac_control, mac_control, NUM_TRIES - retries); if (mac_control == slave->mac_control) return; @@@ -619,6 -590,6 +642,7 @@@ __raw_writel(mac_control, &slave->sliver->mac_control); slave->mac_control = mac_control; } ++#endif static int cpsw_update_link(struct cpsw_priv *priv) { @@@ -637,11 -612,9 +665,10 @@@ static inline u32 cpsw_get_slave_port(s static void cpsw_slave_init(struct cpsw_slave *slave, struct cpsw_priv *priv) { - u32 slave_port; + u32 slave_port; + debug("%s\n", __func__); - - soft_reset(&slave->sliver->soft_reset); + setbit_and_wait_for_clear32(&slave->sliver->soft_reset); /* setup priority mapping */ __raw_writel(0x76543210, &slave->sliver->rx_pri_map); @@@ -658,28 -631,14 +685,26 @@@ cpsw_ale_port_state(priv, slave_port, ALE_PORT_STATE_FORWARD); cpsw_ale_add_mcast(priv, NetBcastAddr, 1 << slave_port); - - priv->data->phy_init(priv->dev->name, slave->data->phy_id); } -static struct cpdma_desc *cpdma_desc_alloc(struct cpsw_priv *priv) +static void cpdma_desc_get(struct cpsw_desc *desc) +{ + invalidate_dcache_range((u32)desc->dma_desc, (u32)(&desc->dma_desc[1])); +} + +static void cpdma_desc_put(struct cpsw_desc *desc) +{ + flush_dcache_range((u32)desc->dma_desc, (u32)(&desc->dma_desc[1])); +} + +static struct cpsw_desc *cpdma_desc_alloc(struct cpsw_priv *priv) { - struct cpdma_desc *desc = priv->desc_free; + struct cpsw_desc *desc = priv->desc_free; - if (desc) - priv->desc_free = desc_read_ptr(desc, hw_next); + if (desc) { + cpdma_desc_get(desc); + priv->desc_free = desc->next; + } return desc; } @@@ -692,19 -649,13 +717,20 @@@ static void cpdma_desc_free(struct cpsw priv->desc_free = desc; } } + static int cpdma_submit(struct cpsw_priv *priv, struct cpdma_chan *chan, - volatile void *buffer, int len) + void *buffer, int len) { - struct cpdma_desc *desc, *prev; + struct cpsw_desc *desc, *prev; u32 mode; + if (!buffer) { + printf("ERROR: %s() NULL buffer\n", __func__); + return -EINVAL; + } + + flush_dcache_range((u32)buffer, (u32)buffer + len); + desc = cpdma_desc_alloc(priv); if (!desc) return -ENOMEM; @@@ -755,9 -696,9 +781,9 @@@ done } static int cpdma_process(struct cpsw_priv *priv, struct cpdma_chan *chan, - volatile void **buffer, int *len) + void **buffer, int *len) { - struct cpdma_desc *desc = chan->head; + struct cpsw_desc *desc = chan->head; u32 status; if (!desc) @@@ -786,14 -731,11 +812,12 @@@ static int cpsw_init(struct eth_device *dev, bd_t *bis) { struct cpsw_priv *priv = dev->priv; + struct cpsw_slave *slave; int i, ret; + debug("%s\n", __func__); - - priv->data->control(1); - /* soft reset the controller and initialize priv */ - soft_reset(&priv->regs->soft_reset); + setbit_and_wait_for_clear32(&priv->regs->soft_reset); /* initialize and reset the address lookup engine */ cpsw_ale_enable(priv, 1); @@@ -854,23 -792,33 +879,23 @@@ } /* clear dma state */ - soft_reset(priv->dma_regs + CPDMA_SOFTRESET); + setbit_and_wait_for_clear32(priv->dma_regs + CPDMA_SOFTRESET); - if (priv->data.version == CPSW_CTRL_VERSION_2) { - for (i = 0; i < priv->data.channels; i++) { - __raw_writel(0, priv->dma_regs + CPDMA_RXHDP_VER2 + 4 - * i); - __raw_writel(0, priv->dma_regs + CPDMA_RXFREE + 4 - * i); - __raw_writel(0, priv->dma_regs + CPDMA_RXCP_VER2 + 4 - * i); - __raw_writel(0, priv->dma_regs + CPDMA_TXHDP_VER2 + 4 - * i); - __raw_writel(0, priv->dma_regs + CPDMA_TXCP_VER2 + 4 - * i); + if (priv->data->version == CPSW_CTRL_VERSION_2) { + for (i = 0; i < priv->data->channels; i++) { + __raw_writel(0, priv->dma_regs + CPDMA_RXHDP_VER2 + 4 * i); + __raw_writel(0, priv->dma_regs + CPDMA_RXFREE + 4 * i); + __raw_writel(0, priv->dma_regs + CPDMA_RXCP_VER2 + 4 * i); + __raw_writel(0, priv->dma_regs + CPDMA_TXHDP_VER2 + 4 * i); + __raw_writel(0, priv->dma_regs + CPDMA_TXCP_VER2 + 4 * i); } } else { - for (i = 0; i < priv->data.channels; i++) { - __raw_writel(0, priv->dma_regs + CPDMA_RXHDP_VER1 + 4 - * i); - __raw_writel(0, priv->dma_regs + CPDMA_RXFREE + 4 - * i); - __raw_writel(0, priv->dma_regs + CPDMA_RXCP_VER1 + 4 - * i); - __raw_writel(0, priv->dma_regs + CPDMA_TXHDP_VER1 + 4 - * i); - __raw_writel(0, priv->dma_regs + CPDMA_TXCP_VER1 + 4 - * i); + for (i = 0; i < priv->data->channels; i++) { + __raw_writel(0, priv->dma_regs + CPDMA_RXHDP_VER1 + 4 * i); + __raw_writel(0, priv->dma_regs + CPDMA_RXFREE + 4 * i); + __raw_writel(0, priv->dma_regs + CPDMA_RXCP_VER1 + 4 * i); + __raw_writel(0, priv->dma_regs + CPDMA_TXHDP_VER1 + 4 * i); + __raw_writel(0, priv->dma_regs + CPDMA_TXCP_VER1 + 4 * i); } } @@@ -892,29 -841,42 +918,38 @@@ static void cpsw_halt(struct eth_device *dev) { - struct cpsw_priv *priv = dev->priv; + struct cpsw_priv *priv = dev->priv; + + writel(0, priv->dma_regs + CPDMA_TXCONTROL); + writel(0, priv->dma_regs + CPDMA_RXCONTROL); + + /* soft reset the controller and initialize priv */ + setbit_and_wait_for_clear32(&priv->regs->soft_reset); + + /* clear dma state */ + setbit_and_wait_for_clear32(priv->dma_regs + CPDMA_SOFTRESET); - priv->data.control(0); + debug("%s\n", __func__); + priv->data->control(0); } - static int cpsw_send(struct eth_device *dev, volatile void *packet, int length) + static int cpsw_send(struct eth_device *dev, void *packet, int length) { - struct cpsw_priv *priv = dev->priv; + struct cpsw_priv *priv = dev->priv; - volatile void *buffer; + void *buffer; int len; - int timeout = CPDMA_TIMEOUT; - if (!cpsw_update_link(priv)) - return -EIO; + debug("%s@%d: sending packet %p..%p\n", __func__, __LINE__, + packet, packet + length - 1); - flush_dcache_range((unsigned long)packet, - (unsigned long)packet + length); + if (!priv->data->mac_control && !cpsw_update_link(priv)) { + printf("%s: Cannot send packet; link is down\n", __func__); + return -EIO; + } /* first reap completed packets */ - while (timeout-- && - (cpdma_process(priv, &priv->tx_chan, &buffer, &len) >= 0)) - ; - - if (timeout == -1) { - printf("cpdma_process timeout\n"); - return -ETIMEDOUT; - } + while (cpdma_process(priv, &priv->tx_chan, &buffer, &len) == 0) + /* NOP */; return cpdma_submit(priv, &priv->tx_chan, packet, length); } @@@ -922,18 -884,18 +957,19 @@@ static int cpsw_recv(struct eth_device *dev) { struct cpsw_priv *priv = dev->priv; - volatile void *buffer; + void *buffer; int len; - cpsw_update_link(priv); - - while (cpdma_process(priv, &priv->rx_chan, &buffer, &len) >= 0) { - invalidate_dcache_range((unsigned long)buffer, - (unsigned long)buffer + PKTSIZE_ALIGN); - NetReceive(buffer, len); - cpdma_submit(priv, &priv->rx_chan, buffer, PKTSIZE); + while (cpdma_process(priv, &priv->rx_chan, &buffer, &len) == 0) { + if (buffer) { + NetReceive(buffer, len); + cpdma_submit(priv, &priv->rx_chan, buffer, PKTSIZE); + } else { + printf("NULL buffer returned from cpdma_process\n"); + return -EIO; + } } + return 0; } @@@ -954,11 -937,9 +1014,13 @@@ static int cpsw_phy_init(struct eth_dev int cpsw_register(struct cpsw_platform_data *data) { struct cpsw_priv *priv; + struct cpsw_slave *slave; void *regs = (void *)data->cpsw_base; struct eth_device *dev; + int i; ++ int idx = 0; + + debug("%s@%d\n", __func__, __LINE__); dev = calloc(sizeof(*dev), 1); if (!dev) @@@ -970,10 -951,10 +1032,10 @@@ return -ENOMEM; } - priv->data = *data; + priv->data = data; - priv->dev = dev; + priv->dev = dev; - priv->slaves = malloc(sizeof(struct cpsw_slave) * data->slaves); + priv->slaves = calloc(sizeof(struct cpsw_slave), data->slaves); if (!priv->slaves) { free(dev); free(priv); @@@ -1003,8 -968,12 +1065,10 @@@ priv->dma_regs = regs + data->cpdma_reg_ofs; priv->ale_regs = regs + data->ale_reg_ofs; - for_each_slave(priv, cpsw_slave_setup, idx, priv); - debug("%s@%d\n", __func__, __LINE__); - int idx = 0; - + for_each_slave(slave, priv) { + cpsw_slave_setup(slave, idx, priv); + idx = idx + 1; + } strcpy(dev->name, "cpsw"); dev->iobase = 0; diff --cc drivers/net/fec_mxc.c index 8d4cef00c5,3e232c7cbc..07b2a5a2cc --- a/drivers/net/fec_mxc.c +++ b/drivers/net/fec_mxc.c @@@ -25,15 -25,22 +25,24 @@@ #include #include #include --#include "fec_mxc.h" ++#include #include #include #include #include + #include + ++#include "fec_mxc.h" + DECLARE_GLOBAL_DATA_PTR; + /* + * Timeout the transfer after 5 mS. This is usually a bit more, since + * the code in the tightloops this timeout is used in adds some overhead. + */ + #define FEC_XFER_TIMEOUT 5000 + #ifndef CONFIG_MII #error "CONFIG_MII has to be defined!" #endif @@@ -539,9 -535,9 +552,8 @@@ static int fec_open(struct eth_device * #ifdef FEC_QUIRK_ENET_MAC { u32 ecr = readl(&fec->eth->ecntrl) & ~FEC_ECNTRL_SPEED; -- u32 rcr = (readl(&fec->eth->r_cntrl) & -- ~(FEC_RCNTRL_RMII | FEC_RCNTRL_RMII_10T)) | -- FEC_RCNTRL_RGMII | FEC_RCNTRL_MII_MODE; ++ u32 rcr = readl(&fec->eth->r_cntrl) & ~FEC_RCNTRL_RMII_10T; ++ if (speed == _1000BASET) ecr |= FEC_ECNTRL_SPEED; else if (speed != _100BASET) @@@ -557,7 -553,7 +569,7 @@@ */ fec_rx_task_enable(fec); -- udelay(100000); ++// udelay(100000); return 0; } @@@ -702,12 -698,13 +714,12 @@@ static void fec_halt(struct eth_device * @param[in] length Data count in bytes * @return 0 on success */ - static int fec_send(struct eth_device *dev, volatile void *packet, int length) + static int fec_send(struct eth_device *dev, void *packet, int length) { unsigned int status; - int timeout = 1000; - uint32_t size; + uint32_t size, end; uint32_t addr; + int timeout = FEC_XFER_TIMEOUT; - int ret = 0; /* * This routine transmits one frame. This routine only accepts @@@ -803,17 -805,16 +816,18 @@@ static int fec_recv(struct eth_device * int frame_length, len = 0; struct nbuf *frame; uint16_t bd_status; - uint32_t addr, size; + uint32_t addr, size, end; int i; - uchar buff[FEC_MAX_PKT_SIZE] __aligned(ARCH_DMA_MINALIGN); /* * Check if any critical events have happened */ ievent = readl(&fec->eth->ievent); -- writel(ievent, &fec->eth->ievent); - debug("fec_recv: ievent 0x%lx\n", ievent); ++ if (ievent) ++ writel(ievent, &fec->eth->ievent); + + if (ievent) + debug("fec_recv: ievent 0x%lx\n", ievent); if (ievent & FEC_IEVENT_BABR) { fec_halt(dev); fec_init(dev, fec->bd); @@@ -1003,7 -1006,7 +1018,10 @@@ static int fec_probe(bd_t *bd, int dev_ eth_register(edev); if (fec_get_hwaddr(edev, dev_id, ethaddr) == 0) { -- debug("got MAC%d address from fuse: %pM\n", dev_id, ethaddr); ++ if (dev_id < 0) ++ debug("got MAC address from fuse: %pM\n", ethaddr); ++ else ++ debug("got MAC%d address from fuse: %pM\n", dev_id, ethaddr); memcpy(edev->enetaddr, ethaddr, 6); } /* Configure phy */ diff --cc drivers/video/Makefile index 51fe5bc3c5,170a358b52..f5f039d7be --- a/drivers/video/Makefile +++ b/drivers/video/Makefile @@@ -34,16 -37,17 +37,18 @@@ COBJS-$(CONFIG_EXYNOS_PWM_BL) += exynos COBJS-$(CONFIG_FSL_DIU_FB) += fsl_diu_fb.o videomodes.o COBJS-$(CONFIG_S6E8AX0) += s6e8ax0.o COBJS-$(CONFIG_S6E63D6) += s6e63d6.o + COBJS-$(CONFIG_LD9040) += ld9040.o COBJS-$(CONFIG_SED156X) += sed156x.o COBJS-$(CONFIG_VIDEO_AMBA) += amba.o + COBJS-$(CONFIG_VIDEO_COREBOOT) += coreboot_fb.o COBJS-$(CONFIG_VIDEO_CT69000) += ct69000.o videomodes.o COBJS-$(CONFIG_VIDEO_DA8XX) += da8xx-fb.o videomodes.o ++COBJS-$(CONFIG_VIDEO_IPUV3) += mxc_ipuv3_fb.o ipu_common.o ipu_disp.o COBJS-$(CONFIG_VIDEO_MB862xx) += mb862xx.o videomodes.o COBJS-$(CONFIG_VIDEO_MB86R0xGDC) += mb86r0xgdc.o videomodes.o COBJS-$(CONFIG_VIDEO_MX3) += mx3fb.o videomodes.o - COBJS-$(CONFIG_VIDEO_MX5) += mxc_ipuv3_fb.o ipu_common.o ipu_disp.o -COBJS-$(CONFIG_VIDEO_IPUV3) += mxc_ipuv3_fb.o ipu_common.o ipu_disp.o +COBJS-$(CONFIG_VIDEO_MXS) += mxsfb.o - COBJS-$(CONFIG_VIDEO_OMAP3) += omap3_dss.o videomodes.o + COBJS-$(CONFIG_VIDEO_OMAP3) += omap3_dss.o COBJS-$(CONFIG_VIDEO_SED13806) += sed13806.o COBJS-$(CONFIG_VIDEO_SM501) += sm501.o COBJS-$(CONFIG_VIDEO_SMI_LYNXEM) += smiLynxEM.o videomodes.o diff --cc drivers/video/da8xx-fb.c index 06157b7305,30c19b3a43..83d0b3c4c1 --- a/drivers/video/da8xx-fb.c +++ b/drivers/video/da8xx-fb.c @@@ -34,7 -33,7 +34,7 @@@ #include #include --#include ++#include #include "videomodes.h" #include diff --cc drivers/video/ipu_common.c index a287f2cca6,ad4af5283a..a72536c85b --- a/drivers/video/ipu_common.c +++ b/drivers/video/ipu_common.c @@@ -4,9 -4,9 +4,9 @@@ * (C) Copyright 2010 * Stefano Babic, DENX Software Engineering, sbabic@denx.de * -- * Linux IPU driver for MX51: ++ * Linux IPU driver * -- * (C) Copyright 2005-2010 Freescale Semiconductor, Inc. ++ * (C) Copyright 2005-2011 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@@ -29,17 -29,17 +29,16 @@@ /* #define DEBUG */ #include ++#include #include #include #include #include #include #include --#include "ipu.h" --#include "ipu_regs.h" ++#include --extern struct mxc_ccm_reg *mxc_ccm; --extern u32 *ipu_cpmem_base; ++#include "ipu_regs.h" struct ipu_ch_param_word { uint32_t data[5]; @@@ -53,67 -53,68 +52,47 @@@ struct ipu_ch_param #define ipu_ch_param_addr(ch) (((struct ipu_ch_param *)ipu_cpmem_base) + (ch)) #define _param_word(base, w) \ -- (((struct ipu_ch_param *)(base))->word[(w)].data) ++ (((struct ipu_ch_param *)(base))->word[w].data) --#define ipu_ch_param_set_field(base, w, bit, size, v) { \ -- int i = (bit) / 32; \ -- int off = (bit) % 32; \ -- _param_word(base, w)[i] |= (v) << off; \ -- if (((bit) + (size) - 1) / 32 > i) { \ ++#define ipu_ch_param_set_field(base, w, bit, size, v) { \ ++ int i = (bit) / 32; \ ++ int off = (bit) % 32; \ ++ _param_word(base, w)[i] |= (v) << off; \ ++ if (((bit) + (size) - 1) / 32 > i) { \ _param_word(base, w)[i + 1] |= (v) >> (off ? (32 - off) : 0); \ -- } \ ++ } \ } --#define ipu_ch_param_mod_field(base, w, bit, size, v) { \ -- int i = (bit) / 32; \ -- int off = (bit) % 32; \ -- u32 mask = (1UL << size) - 1; \ -- u32 temp = _param_word(base, w)[i]; \ -- temp &= ~(mask << off); \ -- _param_word(base, w)[i] = temp | (v) << off; \ -- if (((bit) + (size) - 1) / 32 > i) { \ -- temp = _param_word(base, w)[i + 1]; \ -- temp &= ~(mask >> (32 - off)); \ -- _param_word(base, w)[i + 1] = \ ++#define ipu_ch_param_mod_field(base, w, bit, size, v) { \ ++ int i = (bit) / 32; \ ++ int off = (bit) % 32; \ ++ u32 mask = (1UL << size) - 1; \ ++ u32 temp = _param_word(base, w)[i]; \ ++ temp &= ~(mask << off); \ ++ _param_word(base, w)[i] = temp | (v) << off; \ ++ if (((bit) + (size) - 1) / 32 > i) { \ ++ temp = _param_word(base, w)[i + 1]; \ ++ temp &= ~(mask >> (32 - off)); \ ++ _param_word(base, w)[i + 1] = \ temp | ((v) >> (off ? (32 - off) : 0)); \ -- } \ ++ } \ } --#define ipu_ch_param_read_field(base, w, bit, size) ({ \ -- u32 temp2; \ -- int i = (bit) / 32; \ -- int off = (bit) % 32; \ -- u32 mask = (1UL << size) - 1; \ -- u32 temp1 = _param_word(base, w)[i]; \ -- temp1 = mask & (temp1 >> off); \ -- if (((bit)+(size) - 1) / 32 > i) { \ -- temp2 = _param_word(base, w)[i + 1]; \ -- temp2 &= mask >> (off ? (32 - off) : 0); \ -- temp1 |= temp2 << (off ? (32 - off) : 0); \ -- } \ -- temp1; \ ++#define ipu_ch_param_read_field(base, w, bit, size) ({ \ ++ u32 temp2; \ ++ int i = (bit) / 32; \ ++ int off = (bit) % 32; \ ++ u32 mask = (1UL << size) - 1; \ ++ u32 temp1 = _param_word(base, w)[i]; \ ++ temp1 = mask & (temp1 >> off); \ ++ if (((bit)+(size) - 1) / 32 > i) { \ ++ temp2 = _param_word(base, w)[i + 1]; \ ++ temp2 &= mask >> (off ? (32 - off) : 0); \ ++ temp1 |= temp2 << (off ? (32 - off) : 0); \ ++ } \ ++ temp1; \ }) -#define IPU_SW_RST_TOUT_USEC (10000) -- --void clk_enable(struct clk *clk) --{ -- if (clk) { -- if (clk->usecount++ == 0) { -- clk->enable(clk); -- } -- } --} -- --void clk_disable(struct clk *clk) --{ -- if (clk) { -- if (!(--clk->usecount)) { -- if (clk->disable) -- clk->disable(clk); -- } -- } --} -- int clk_get_usecount(struct clk *clk) { if (clk == NULL) @@@ -155,86 -156,99 +134,59 @@@ long clk_round_rate(struct clk *clk, un int clk_set_parent(struct clk *clk, struct clk *parent) { ++ debug("Setting parent of clk %p to %p (%p)\n", clk, parent, ++ clk ? clk->parent : NULL); ++ ++ if (!clk || clk == parent) ++ return 0; ++ ++ if (clk->set_parent) { ++ int ret; ++ ++ ret = clk->set_parent(clk, parent); ++ if (ret) ++ return ret; ++ } clk->parent = parent; -- if (clk->set_parent) -- return clk->set_parent(clk, parent); return 0; } static int clk_ipu_enable(struct clk *clk) { -- u32 reg; -- -- reg = __raw_readl(clk->enable_reg); -- reg |= MXC_CCM_CCGR_CG_MASK << clk->enable_shift; -- __raw_writel(reg, clk->enable_reg); -- -#if defined(CONFIG_MX51) || defined(CONFIG_MX53) -- /* Handshake with IPU when certain clock rates are changed. */ -- reg = __raw_readl(&mxc_ccm->ccdr); -- reg &= ~MXC_CCM_CCDR_IPU_HS_MASK; -- __raw_writel(reg, &mxc_ccm->ccdr); -- -- /* Handshake with IPU when LPM is entered as its enabled. */ -- reg = __raw_readl(&mxc_ccm->clpcr); -- reg &= ~MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS; -- __raw_writel(reg, &mxc_ccm->clpcr); - -#endif ++ ipu_clk_enable(); return 0; } static void clk_ipu_disable(struct clk *clk) { -- u32 reg; -- -- reg = __raw_readl(clk->enable_reg); -- reg &= ~(MXC_CCM_CCGR_CG_MASK << clk->enable_shift); -- __raw_writel(reg, clk->enable_reg); -- -#if defined(CONFIG_MX51) || defined(CONFIG_MX53) -- /* -- * No handshake with IPU whe dividers are changed -- * as its not enabled. -- */ -- reg = __raw_readl(&mxc_ccm->ccdr); -- reg |= MXC_CCM_CCDR_IPU_HS_MASK; -- __raw_writel(reg, &mxc_ccm->ccdr); -- -- /* No handshake with IPU when LPM is entered as its not enabled. */ -- reg = __raw_readl(&mxc_ccm->clpcr); -- reg |= MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS; -- __raw_writel(reg, &mxc_ccm->clpcr); -#endif ++ ipu_clk_disable(); } -- static struct clk ipu_clk = { .name = "ipu_clk", - #if defined(CONFIG_MX51) - .rate = 133000000, - #elif defined(CONFIG_MX53) - .rate = 216000000, - .rate = CONFIG_IPUV3_CLK, -#if defined(CONFIG_MX51) || defined(CONFIG_MX53) - .enable_reg = (u32 *)(CCM_BASE_ADDR + - offsetof(struct mxc_ccm_reg, CCGR5)), - .enable_shift = MXC_CCM_CCGR5_IPU_OFFSET, -#else - .enable_reg = (u32 *)(CCM_BASE_ADDR + - offsetof(struct mxc_ccm_reg, CCGR3)), - .enable_shift = MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET, ++#if defined(CONFIG_IPU_CLKRATE) ++ .rate = CONFIG_IPU_CLKRATE, #endif - .enable_reg = (u32 *)(MXC_CCM_BASE + - offsetof(struct mxc_ccm_reg, CCGR5)), - .enable_shift = MXC_CCM_CCGR5_CG5_OFFSET, .enable = clk_ipu_enable, .disable = clk_ipu_disable, - .usecount = 0, -}; - -static struct clk ldb_clk = { - .name = "ldb_clk", - .rate = 65000000, - .usecount = 0, }; /* Globals */ struct clk *g_ipu_clk; -struct clk *g_ldb_clk; --unsigned char g_ipu_clk_enabled; struct clk *g_di_clk[2]; struct clk *g_pixel_clk[2]; unsigned char g_dc_di_assignment[10]; --uint32_t g_channel_init_mask; --uint32_t g_channel_enable_mask; ++int g_ipu_clk_enabled; ++u32 *ipu_dc_tmpl_reg; ++static uint32_t g_channel_init_mask; ++static uint32_t g_channel_enable_mask; static int ipu_dc_use_count; static int ipu_dp_use_count; static int ipu_dmfc_use_count; static int ipu_di_use_count[2]; --u32 *ipu_cpmem_base; --u32 *ipu_dc_tmpl_reg; ++static u32 *ipu_cpmem_base; /* Static functions */ @@@ -284,13 -298,13 +236,13 @@@ static unsigned long ipu_pixel_clk_roun unsigned long rate) { u32 div, div1; -- u32 tmp; ++ u64 tmp; /* * Calculate divider * Fractional part is 4 bits, * so simply multiply by 2^4 to get fractional part. */ - tmp = clk->parent->rate * 16; - tmp = (clk->parent->rate * 16); ++ tmp = (u64)clk->parent->rate * 16; div = tmp / rate; if (div < 0x10) /* Min DI disp clock divider is 1 */ @@@ -304,19 -318,19 +256,32 @@@ else div &= 0xFF8; } -- return (clk->parent->rate * 16) / div; ++ tmp /= div; ++#if 1 ++ debug("%s: requested rate: %lu.%03luMHz parent_rate: %lu.%03luMHz actual rate: %llu.%03lluMHz div: %u.%u\n", __func__, ++ rate / 1000000, rate / 1000 % 1000, ++ clk->parent->rate / 1000000, clk->parent->rate / 1000 % 1000, ++ tmp / 1000000, tmp / 1000 % 1000, div / 16, div % 16); ++#endif ++ return tmp; } static int ipu_pixel_clk_set_rate(struct clk *clk, unsigned long rate) { -- u32 div = (clk->parent->rate * 16) / rate; ++ u32 div = ((u64)clk->parent->rate * 16) / rate; ++ ++ debug("%s: parent_rate: %lu.%03luMHz actual rate: %lu.%03luMHz div: %u.%u\n", __func__, ++ clk->parent->rate / 1000000, clk->parent->rate / 1000 % 1000, ++ rate / 1000000, rate / 1000 % 1000, div / 16, div % 16); __raw_writel(div, DI_BS_CLKGEN0(clk->id)); /* Setup pixel clock timing */ __raw_writel((div / 16) << 16, DI_BS_CLKGEN1(clk->id)); -- clk->rate = (clk->parent->rate * 16) / div; ++ clk->rate = ((u64)clk->parent->rate * 16) / div; ++ debug("%s: pix_clk=%lu.%03luMHz\n", __func__, ++ clk->rate / 1000000, clk->rate / 1000 % 1000); return 0; } @@@ -338,43 -353,45 +303,68 @@@ static void ipu_pixel_clk_disable(struc static int ipu_pixel_clk_set_parent(struct clk *clk, struct clk *parent) { -- u32 di_gen = __raw_readl(DI_GENERAL(clk->id)); ++ int ret; ++ u32 di_gen; ++ ++ ret = clk_enable(clk); ++ if (ret) ++ return ret; ++ ++ di_gen = __raw_readl(DI_GENERAL(clk->id)); if (parent == g_ipu_clk) di_gen &= ~DI_GEN_DI_CLK_EXT; - else if (!IS_ERR(g_di_clk[clk->id]) && parent == g_ldb_clk) + else if (!IS_ERR(g_di_clk[clk->id]) && parent == g_di_clk[clk->id]) di_gen |= DI_GEN_DI_CLK_EXT; else -- return -EINVAL; ++ goto err; ++ ret = clk_enable(parent); ++ if (ret) ++ goto err; __raw_writel(di_gen, DI_GENERAL(clk->id)); ipu_pixel_clk_recalc(clk); -- return 0; ++ clk->disable(clk->parent); ++ clk->parent = parent; ++err: ++ clk_disable(clk); ++ return ret; } static struct clk pixel_clk[] = { { - .name = "pixel_clk", - .id = 0, - .recalc = ipu_pixel_clk_recalc, - .set_rate = ipu_pixel_clk_set_rate, - .round_rate = ipu_pixel_clk_round_rate, - .set_parent = ipu_pixel_clk_set_parent, - .enable = ipu_pixel_clk_enable, - .disable = ipu_pixel_clk_disable, - .usecount = 0, + .name = "pixel_clk", + .id = 0, + .recalc = ipu_pixel_clk_recalc, + .set_rate = ipu_pixel_clk_set_rate, + .round_rate = ipu_pixel_clk_round_rate, + .set_parent = ipu_pixel_clk_set_parent, + .enable = ipu_pixel_clk_enable, + .disable = ipu_pixel_clk_disable, }, { - .name = "pixel_clk", - .id = 1, - .recalc = ipu_pixel_clk_recalc, - .set_rate = ipu_pixel_clk_set_rate, - .round_rate = ipu_pixel_clk_round_rate, - .set_parent = ipu_pixel_clk_set_parent, - .enable = ipu_pixel_clk_enable, - .disable = ipu_pixel_clk_disable, - .usecount = 0, + .name = "pixel_clk", + .id = 1, + .recalc = ipu_pixel_clk_recalc, + .set_rate = ipu_pixel_clk_set_rate, + .round_rate = ipu_pixel_clk_round_rate, + .set_parent = ipu_pixel_clk_set_parent, + .enable = ipu_pixel_clk_enable, + .disable = ipu_pixel_clk_disable, + }, +}; + ++static struct clk di_clk[] = { ++ { ++ .name = "ipu_di_clk", ++ .id = 0, ++ }, ++ { ++ .name = "ipu_di_clk", ++ .id = 1, + }, + }; + /* * This function resets IPU */ @@@ -398,45 -424,48 +388,67 @@@ void ipu_reset(void * * @return Returns 0 on success or negative error code on error */ --int ipu_probe(void) ++int ipu_probe(int di, ipu_di_clk_parent_t di_clk_parent, int di_clk_val) { -- unsigned long ipu_base; - #ifdef CONFIG_MX51 -#if defined CONFIG_MX51 - u32 temp; ++ int ret; ++ void *ipu_base; ++ unsigned long start; + ++#if defined(CONFIG_MXC_HSC) + u32 temp; u32 *reg_hsc_mcd = (u32 *)MIPI_HSC_BASE_ADDR; u32 *reg_hsc_mxt_conf = (u32 *)(MIPI_HSC_BASE_ADDR + 0x800); __raw_writel(0xF00, reg_hsc_mcd); -- /* CSI mode reserved*/ ++ /* CSI mode reserved */ temp = __raw_readl(reg_hsc_mxt_conf); __raw_writel(temp | 0x0FF, reg_hsc_mxt_conf); temp = __raw_readl(reg_hsc_mxt_conf); __raw_writel(temp | 0x10000, reg_hsc_mxt_conf); #endif - -- ipu_base = IPU_CTRL_BASE_ADDR; -- ipu_cpmem_base = (u32 *)(ipu_base + IPU_CPMEM_REG_BASE); -- ipu_dc_tmpl_reg = (u32 *)(ipu_base + IPU_DC_TMPL_REG_BASE); ++ ipu_base = (void *)IPU_CTRL_BASE_ADDR; ++ /* base fixup */ ++ if (gd->arch.ipu_hw_rev == IPUV3_HW_REV_IPUV3H) /* IPUv3H */ ++ ipu_base += IPUV3H_REG_BASE; ++ else if (gd->arch.ipu_hw_rev == IPUV3_HW_REV_IPUV3M) /* IPUv3M */ ++ ipu_base += IPUV3M_REG_BASE; ++ else /* IPUv3D, v3E, v3EX */ ++ ipu_base += IPUV3DEX_REG_BASE; ++ ipu_cpmem_base = ipu_base + IPU_CPMEM_REG_BASE; ++ ipu_dc_tmpl_reg = ipu_base + IPU_DC_TMPL_REG_BASE; ++ ++ printf("IPU HW Rev: %d\n", gd->arch.ipu_hw_rev); g_pixel_clk[0] = &pixel_clk[0]; g_pixel_clk[1] = &pixel_clk[1]; ++ g_di_clk[0] = &di_clk[0]; ++ g_di_clk[1] = &di_clk[1]; ++ g_di_clk[di]->rate = di_clk_val; ++ g_ipu_clk = &ipu_clk; debug("ipu_clk = %u\n", clk_get_rate(g_ipu_clk)); - g_ldb_clk = &ldb_clk; - debug("ldb_clk = %u\n", clk_get_rate(g_ldb_clk)); - ipu_reset(); - clk_set_parent(g_pixel_clk[0], g_ipu_clk); - clk_set_parent(g_pixel_clk[1], g_ipu_clk); - clk_enable(g_ipu_clk); ++ ret = clk_enable(g_ipu_clk); ++ if (ret) ++ return ret; + ipu_reset(); - clk_set_parent(g_pixel_clk[0], g_ipu_clk); - clk_set_parent(g_pixel_clk[1], g_ipu_clk); - clk_enable(g_ipu_clk); - -- g_di_clk[0] = NULL; -- g_di_clk[1] = NULL; ++ if (di_clk_parent == DI_PCLK_LDB) { ++ clk_set_parent(g_pixel_clk[di], g_di_clk[di]); ++ } else { ++ clk_set_parent(g_pixel_clk[0], g_ipu_clk); ++ clk_set_parent(g_pixel_clk[1], g_ipu_clk); ++ } __raw_writel(0x807FFFFF, IPU_MEM_RST); -- while (__raw_readl(IPU_MEM_RST) & 0x80000000) -- ; ++ start = get_timer_masked(); ++ while (__raw_readl(IPU_MEM_RST) & 0x80000000) { ++ if (get_timer(start) > CONFIG_SYS_HZ) ++ return -ETIME; ++ } ipu_init_dc_mappings(); @@@ -565,7 -594,7 +577,6 @@@ int32_t ipu_init_channel(ipu_channel_t break; default: printf("Missing channel initialization\n"); -- break; } /* Enable IPU sub module */ @@@ -683,41 -711,41 +692,41 @@@ static inline void ipu_ch_param_dump(in { #ifdef DEBUG struct ipu_ch_param *p = ipu_ch_param_addr(ch); -- debug("ch %d word 0 - %08X %08X %08X %08X %08X\n", ch, ++ printf("ch %d word 0 - %08X %08X %08X %08X %08X\n", ch, p->word[0].data[0], p->word[0].data[1], p->word[0].data[2], p->word[0].data[3], p->word[0].data[4]); -- debug("ch %d word 1 - %08X %08X %08X %08X %08X\n", ch, ++ printf("ch %d word 1 - %08X %08X %08X %08X %08X\n", ch, p->word[1].data[0], p->word[1].data[1], p->word[1].data[2], p->word[1].data[3], p->word[1].data[4]); -- debug("PFS 0x%x, ", ++ printf("PFS 0x%x, ", ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 85, 4)); -- debug("BPP 0x%x, ", ++ printf("BPP 0x%x, ", ipu_ch_param_read_field(ipu_ch_param_addr(ch), 0, 107, 3)); -- debug("NPB 0x%x\n", ++ printf("NPB 0x%x\n", ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 78, 7)); -- debug("FW %d, ", ++ printf("FW %d, ", ipu_ch_param_read_field(ipu_ch_param_addr(ch), 0, 125, 13)); -- debug("FH %d, ", ++ printf("FH %d, ", ipu_ch_param_read_field(ipu_ch_param_addr(ch), 0, 138, 12)); -- debug("Stride %d\n", ++ printf("Stride %d\n", ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 102, 14)); -- debug("Width0 %d+1, ", ++ printf("Width0 %d+1, ", ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 116, 3)); -- debug("Width1 %d+1, ", ++ printf("Width1 %d+1, ", ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 119, 3)); -- debug("Width2 %d+1, ", ++ printf("Width2 %d+1, ", ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 122, 3)); -- debug("Width3 %d+1, ", ++ printf("Width3 %d+1, ", ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 125, 3)); -- debug("Offset0 %d, ", ++ printf("Offset0 %d, ", ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 128, 5)); -- debug("Offset1 %d, ", ++ printf("Offset1 %d, ", ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 133, 5)); -- debug("Offset2 %d, ", ++ printf("Offset2 %d, ", ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 138, 5)); -- debug("Offset3 %d\n", ++ printf("Offset3 %d\n", ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 143, 5)); #endif } @@@ -751,91 -779,91 +760,88 @@@ static void ipu_ch_param_init(int ch { uint32_t u_offset = 0; uint32_t v_offset = 0; -- struct ipu_ch_param params; - - memset(¶ms, 0, sizeof(params)); - memset(¶ms, 0, sizeof(params)); - -- ipu_ch_param_set_field(¶ms, 0, 125, 13, width - 1); ++ ipu_ch_param_set_field(ipu_ch_param_addr(ch), 0, 125, 13, width - 1); if ((ch == 8) || (ch == 9) || (ch == 10)) { -- ipu_ch_param_set_field(¶ms, 0, 138, 12, (height / 2) - 1); -- ipu_ch_param_set_field(¶ms, 1, 102, 14, (stride * 2) - 1); ++ ipu_ch_param_set_field(ipu_ch_param_addr(ch), 0, 138, 12, (height / 2) - 1); ++ ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 102, 14, (stride * 2) - 1); } else { -- ipu_ch_param_set_field(¶ms, 0, 138, 12, height - 1); -- ipu_ch_param_set_field(¶ms, 1, 102, 14, stride - 1); ++ ipu_ch_param_set_field(ipu_ch_param_addr(ch), 0, 138, 12, height - 1); ++ ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 102, 14, stride - 1); } -- ipu_ch_param_set_field(¶ms, 1, 0, 29, addr0 >> 3); -- ipu_ch_param_set_field(¶ms, 1, 29, 29, addr1 >> 3); ++ ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 0, 29, addr0 >> 3); ++ ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 29, 29, addr1 >> 3); switch (pixel_fmt) { case IPU_PIX_FMT_GENERIC: /*Represents 8-bit Generic data */ -- ipu_ch_param_set_field(¶ms, 0, 107, 3, 5); /* bits/pixel */ -- ipu_ch_param_set_field(¶ms, 1, 85, 4, 6); /* pix format */ -- ipu_ch_param_set_field(¶ms, 1, 78, 7, 63); /* burst size */ ++ ipu_ch_param_set_field(ipu_ch_param_addr(ch), 0, 107, 3, 5); /* bits/pixel */ ++ ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 85, 4, 6); /* pix format */ ++ ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 78, 7, 63); /* burst size */ break; case IPU_PIX_FMT_GENERIC_32: /*Represents 32-bit Generic data */ break; case IPU_PIX_FMT_RGB565: -- ipu_ch_param_set_field(¶ms, 0, 107, 3, 3); /* bits/pixel */ -- ipu_ch_param_set_field(¶ms, 1, 85, 4, 7); /* pix format */ -- ipu_ch_param_set_field(¶ms, 1, 78, 7, 15); /* burst size */ ++ ipu_ch_param_set_field(ipu_ch_param_addr(ch), 0, 107, 3, 3); /* bits/pixel */ ++ ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 85, 4, 7); /* pix format */ ++ ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 78, 7, 15); /* burst size */ -- ipu_ch_params_set_packing(¶ms, 5, 0, 6, 5, 5, 11, 8, 16); ++ ipu_ch_params_set_packing(ipu_ch_param_addr(ch), 5, 0, 6, 5, 5, 11, 8, 16); break; case IPU_PIX_FMT_BGR24: -- ipu_ch_param_set_field(¶ms, 0, 107, 3, 1); /* bits/pixel */ -- ipu_ch_param_set_field(¶ms, 1, 85, 4, 7); /* pix format */ -- ipu_ch_param_set_field(¶ms, 1, 78, 7, 19); /* burst size */ ++ ipu_ch_param_set_field(ipu_ch_param_addr(ch), 0, 107, 3, 1); /* bits/pixel */ ++ ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 85, 4, 7); /* pix format */ ++ ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 78, 7, 19); /* burst size */ -- ipu_ch_params_set_packing(¶ms, 8, 0, 8, 8, 8, 16, 8, 24); ++ ipu_ch_params_set_packing(ipu_ch_param_addr(ch), 8, 0, 8, 8, 8, 16, 8, 24); break; case IPU_PIX_FMT_RGB24: case IPU_PIX_FMT_YUV444: -- ipu_ch_param_set_field(¶ms, 0, 107, 3, 1); /* bits/pixel */ -- ipu_ch_param_set_field(¶ms, 1, 85, 4, 7); /* pix format */ -- ipu_ch_param_set_field(¶ms, 1, 78, 7, 19); /* burst size */ ++ ipu_ch_param_set_field(ipu_ch_param_addr(ch), 0, 107, 3, 1); /* bits/pixel */ ++ ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 85, 4, 7); /* pix format */ ++ ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 78, 7, 19); /* burst size */ -- ipu_ch_params_set_packing(¶ms, 8, 16, 8, 8, 8, 0, 8, 24); ++ ipu_ch_params_set_packing(ipu_ch_param_addr(ch), 8, 16, 8, 8, 8, 0, 8, 24); break; case IPU_PIX_FMT_BGRA32: case IPU_PIX_FMT_BGR32: -- ipu_ch_param_set_field(¶ms, 0, 107, 3, 0); /* bits/pixel */ -- ipu_ch_param_set_field(¶ms, 1, 85, 4, 7); /* pix format */ -- ipu_ch_param_set_field(¶ms, 1, 78, 7, 15); /* burst size */ ++ ipu_ch_param_set_field(ipu_ch_param_addr(ch), 0, 107, 3, 0); /* bits/pixel */ ++ ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 85, 4, 7); /* pix format */ ++ ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 78, 7, 15); /* burst size */ -- ipu_ch_params_set_packing(¶ms, 8, 8, 8, 16, 8, 24, 8, 0); ++ ipu_ch_params_set_packing(ipu_ch_param_addr(ch), 8, 8, 8, 16, 8, 24, 8, 0); break; case IPU_PIX_FMT_RGBA32: case IPU_PIX_FMT_RGB32: -- ipu_ch_param_set_field(¶ms, 0, 107, 3, 0); /* bits/pixel */ -- ipu_ch_param_set_field(¶ms, 1, 85, 4, 7); /* pix format */ -- ipu_ch_param_set_field(¶ms, 1, 78, 7, 15); /* burst size */ ++ ipu_ch_param_set_field(ipu_ch_param_addr(ch), 0, 107, 3, 0); /* bits/pixel */ ++ ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 85, 4, 7); /* pix format */ ++ ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 78, 7, 15); /* burst size */ -- ipu_ch_params_set_packing(¶ms, 8, 24, 8, 16, 8, 8, 8, 0); ++ ipu_ch_params_set_packing(ipu_ch_param_addr(ch), 8, 24, 8, 16, 8, 8, 8, 0); break; case IPU_PIX_FMT_ABGR32: -- ipu_ch_param_set_field(¶ms, 0, 107, 3, 0); /* bits/pixel */ -- ipu_ch_param_set_field(¶ms, 1, 85, 4, 7); /* pix format */ ++ ipu_ch_param_set_field(ipu_ch_param_addr(ch), 0, 107, 3, 0); /* bits/pixel */ ++ ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 85, 4, 7); /* pix format */ -- ipu_ch_params_set_packing(¶ms, 8, 0, 8, 8, 8, 16, 8, 24); ++ ipu_ch_params_set_packing(ipu_ch_param_addr(ch), 8, 0, 8, 8, 8, 16, 8, 24); break; case IPU_PIX_FMT_UYVY: -- ipu_ch_param_set_field(¶ms, 0, 107, 3, 3); /* bits/pixel */ -- ipu_ch_param_set_field(¶ms, 1, 85, 4, 0xA); /* pix format */ -- ipu_ch_param_set_field(¶ms, 1, 78, 7, 15); /* burst size */ ++ ipu_ch_param_set_field(ipu_ch_param_addr(ch), 0, 107, 3, 3); /* bits/pixel */ ++ ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 85, 4, 0xA); /* pix format */ ++ ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 78, 7, 15); /* burst size */ break; case IPU_PIX_FMT_YUYV: -- ipu_ch_param_set_field(¶ms, 0, 107, 3, 3); /* bits/pixel */ -- ipu_ch_param_set_field(¶ms, 1, 85, 4, 0x8); /* pix format */ -- ipu_ch_param_set_field(¶ms, 1, 78, 7, 31); /* burst size */ ++ ipu_ch_param_set_field(ipu_ch_param_addr(ch), 0, 107, 3, 3); /* bits/pixel */ ++ ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 85, 4, 0x8); /* pix format */ ++ ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 78, 7, 31); /* burst size */ break; case IPU_PIX_FMT_YUV420P2: case IPU_PIX_FMT_YUV420P: -- ipu_ch_param_set_field(¶ms, 1, 85, 4, 2); /* pix format */ ++ ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 85, 4, 2); /* pix format */ if (uv_stride < stride / 2) uv_stride = stride / 2; @@@ -844,16 -872,16 +850,16 @@@ v_offset = u_offset + (uv_stride * height / 2); /* burst size */ if ((ch == 8) || (ch == 9) || (ch == 10)) { -- ipu_ch_param_set_field(¶ms, 1, 78, 7, 15); ++ ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 78, 7, 15); uv_stride = uv_stride*2; } else { -- ipu_ch_param_set_field(¶ms, 1, 78, 7, 31); ++ ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 78, 7, 31); } break; case IPU_PIX_FMT_YVU422P: /* BPP & pixel format */ -- ipu_ch_param_set_field(¶ms, 1, 85, 4, 1); /* pix format */ -- ipu_ch_param_set_field(¶ms, 1, 78, 7, 31); /* burst size */ ++ ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 85, 4, 1); /* pix format */ ++ ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 78, 7, 31); /* burst size */ if (uv_stride < stride / 2) uv_stride = stride / 2; @@@ -863,8 -891,8 +869,8 @@@ break; case IPU_PIX_FMT_YUV422P: /* BPP & pixel format */ -- ipu_ch_param_set_field(¶ms, 1, 85, 4, 1); /* pix format */ -- ipu_ch_param_set_field(¶ms, 1, 78, 7, 31); /* burst size */ ++ ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 85, 4, 1); /* pix format */ ++ ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 78, 7, 31); /* burst size */ if (uv_stride < stride / 2) uv_stride = stride / 2; @@@ -874,8 -902,8 +880,8 @@@ break; case IPU_PIX_FMT_NV12: /* BPP & pixel format */ -- ipu_ch_param_set_field(¶ms, 1, 85, 4, 4); /* pix format */ -- ipu_ch_param_set_field(¶ms, 1, 78, 7, 31); /* burst size */ ++ ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 85, 4, 4); /* pix format */ ++ ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 78, 7, 31); /* burst size */ uv_stride = stride; u_offset = (u == 0) ? stride * height : u; break; @@@ -886,7 -914,7 +892,7 @@@ if (uv_stride) -- ipu_ch_param_set_field(¶ms, 1, 128, 14, uv_stride - 1); ++ ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 128, 14, uv_stride - 1); /* Get the uv offset from user when need cropping */ if (u || v) { @@@ -900,11 -928,11 +906,10 @@@ if (v_offset/8 > 0x3fffff) puts("The value of V offset exceeds IPU limitation\n"); -- ipu_ch_param_set_field(¶ms, 0, 46, 22, u_offset / 8); -- ipu_ch_param_set_field(¶ms, 0, 68, 22, v_offset / 8); ++ ipu_ch_param_set_field(ipu_ch_param_addr(ch), 0, 46, 22, u_offset / 8); ++ ipu_ch_param_set_field(ipu_ch_param_addr(ch), 0, 68, 22, v_offset / 8); debug("initializing idma ch %d @ %p\n", ch, ipu_ch_param_addr(ch)); -- memcpy(ipu_ch_param_addr(ch), ¶ms, sizeof(params)); }; /* @@@ -956,7 -984,8 +961,7 @@@ int32_t ipu_init_channel_buffer(ipu_cha stride = width * bytes_per_pixel(pixel_fmt); if (stride % 4) { - printf("Stride not 32-bit aligned, stride = %d\n", stride); - printf( - "Stride not 32-bit aligned, stride = %d\n", stride); ++ printf("Stride %d not 32-bit aligned\n", stride); return -EINVAL; } /* Build parameter memory data for DMA channel */ @@@ -1018,8 -1047,8 +1023,12 @@@ int32_t ipu_enable_channel(ipu_channel_ } if ((channel == MEM_DC_SYNC) || (channel == MEM_BG_SYNC) || -- (channel == MEM_FG_SYNC)) ++ (channel == MEM_FG_SYNC)) { ++ reg = __raw_readl(IDMAC_WM_EN(in_dma)); ++ __raw_writel(reg | idma_mask(in_dma), IDMAC_WM_EN(in_dma)); ++ ipu_dp_dc_enable(channel); ++ } g_channel_enable_mask |= 1L << IPU_CHAN_ID(channel); @@@ -1140,7 -1170,9 +1149,7 @@@ uint32_t bytes_per_pixel(uint32_t fmt case IPU_PIX_FMT_BGR24: case IPU_PIX_FMT_RGB24: return 3; - case IPU_PIX_FMT_GENERIC_32: /* generic data */ - break; + case IPU_PIX_FMT_GENERIC_32: /*generic data */ case IPU_PIX_FMT_BGR32: case IPU_PIX_FMT_BGRA32: case IPU_PIX_FMT_RGB32: diff --cc drivers/video/ipu_disp.c index 52f82e6e22,b4116df8ca..b98342eca3 --- a/drivers/video/ipu_disp.c +++ b/drivers/video/ipu_disp.c @@@ -4,9 -4,9 +4,9 @@@ * (C) Copyright 2010 * Stefano Babic, DENX Software Engineering, sbabic@denx.de * -- * Linux IPU driver for MX51: ++ * Linux IPU driver * -- * (C) Copyright 2005-2010 Freescale Semiconductor, Inc. ++ * (C) Copyright 2005-2011 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@@ -30,12 -30,12 +30,12 @@@ /* #define DEBUG */ #include ++#include #include #include #include #include --#include --#include "ipu.h" ++ #include "ipu_regs.h" enum csc_type_t { @@@ -59,16 -59,17 +59,18 @@@ struct dp_csc_param_t #define DC_DISP_ID_SERIAL 2 #define DC_DISP_ID_ASYNC 3 --int dmfc_type_setup; ++static int dmfc_type_setup; static int dmfc_size_28, dmfc_size_29, dmfc_size_24, dmfc_size_27, dmfc_size_23; --int g_di1_tvout; ++static int g_di1_tvout; ++#if 0 extern struct clk *g_ipu_clk; -extern struct clk *g_ldb_clk; extern struct clk *g_di_clk[2]; extern struct clk *g_pixel_clk[2]; extern unsigned char g_ipu_clk_enabled; extern unsigned char g_dc_di_assignment[]; ++#endif void ipu_dmfc_init(int dmfc_type, int first) { @@@ -887,13 -887,13 +889,13 @@@ void adapt_panel_to_ipu_restricitions(u * fail. */ --int32_t ipu_init_sync_panel(int disp, uint32_t pixel_clk, -- uint16_t width, uint16_t height, -- uint32_t pixel_fmt, -- uint16_t h_start_width, uint16_t h_sync_width, -- uint16_t h_end_width, uint16_t v_start_width, -- uint16_t v_sync_width, uint16_t v_end_width, -- uint32_t v_to_h_sync, ipu_di_signal_cfg_t sig) ++int ipu_init_sync_panel(int disp, uint32_t pixel_clk, ++ uint16_t width, uint16_t height, ++ uint32_t pixel_fmt, ++ uint16_t h_start_width, uint16_t h_sync_width, ++ uint16_t h_end_width, uint16_t v_start_width, ++ uint16_t v_sync_width, uint16_t v_end_width, ++ uint32_t v_to_h_sync, ipu_di_signal_cfg_t sig) { uint32_t reg; uint32_t di_gen, vsync_cnt; @@@ -928,44 -928,33 +930,59 @@@ rounded_pixel_clk = clk_round_rate(g_pixel_clk[disp], pixel_clk); -- div = clk_get_rate(di_parent) / -- rounded_pixel_clk; -- if (div % 2) -- div++; -- if (clk_get_rate(di_parent) != div * -- rounded_pixel_clk) -- clk_set_rate(di_parent, -- div * rounded_pixel_clk); -- udelay(10000); -- clk_set_rate(g_di_clk[disp], -- 2 * rounded_pixel_clk); -- udelay(10000); ++ if (di_parent != NULL) { ++ div = clk_get_rate(di_parent) / ++ rounded_pixel_clk; ++ if (div % 2) ++ div++; ++ if (clk_get_rate(di_parent) != div * ++ rounded_pixel_clk) ++ clk_set_rate(di_parent, ++ div * rounded_pixel_clk); ++ udelay(10000); ++ clk_set_rate(g_di_clk[disp], ++ 2 * rounded_pixel_clk); ++ udelay(10000); ++ } } } - clk_set_parent(g_pixel_clk[disp], g_ldb_clk); + clk_set_parent(g_pixel_clk[disp], g_di_clk[disp]); } else { if (clk_get_usecount(g_pixel_clk[disp]) != 0) clk_set_parent(g_pixel_clk[disp], g_ipu_clk); } rounded_pixel_clk = clk_round_rate(g_pixel_clk[disp], pixel_clk); + clk_set_rate(g_pixel_clk[disp], rounded_pixel_clk); + udelay(5000); + /* Get integer portion of divider */ + div = clk_get_rate(clk_get_parent(g_pixel_clk[disp])) / + rounded_pixel_clk; + - ipu_di_data_wave_config(disp, SYNC_WAVE, div - 1, div - 1); ++ /* Enable for a divide by 2 clock change. */ ++ reg = __raw_readl(IPU_PM); ++ reg &= ~(0x7f << 7); ++ reg |= 0x20 << 7; ++ reg &= ~(0x7f << 23); ++ reg |= 0x20 << 23; ++ __raw_writel(reg, IPU_PM); + + di_gen = 0; + + if (pixel_fmt != IPU_PIX_FMT_LVDS666 && + pixel_fmt != IPU_PIX_FMT_LVDS888) { + clk_set_rate(g_pixel_clk[disp], rounded_pixel_clk); + udelay(5000); + /* Get integer portion of divider */ + div = clk_get_rate(clk_get_parent(g_pixel_clk[disp])) / + rounded_pixel_clk; + ipu_di_data_wave_config(disp, SYNC_WAVE, div - 1, div - 1); + } else { + clk_set_rate(g_pixel_clk[disp], clk_get_rate(g_ipu_clk)); + div = 1; + ipu_di_data_wave_config(disp, SYNC_WAVE, 0, 0); + di_gen |= (6 << 24); + di_gen |= DI_GEN_DI_CLK_EXT; + } ipu_di_data_pin_config(disp, SYNC_WAVE, DI_PIN15, 3, 0, div * 2); map = ipu_pixfmt_to_map(pixel_fmt); @@@ -1187,15 -1178,15 +1204,20 @@@ __raw_writel(0, DI_STP_REP(disp, 7)); __raw_writel(0, DI_STP_REP(disp, 9)); ++ h_total = ((width + h_start_width + h_sync_width) / 2) - 2; ++ ipu_di_sync_config(disp, 6, 1, 0, 2, DI_SYNC_CLK, h_total, ++ DI_SYNC_INT_HSYNC, 0, DI_SYNC_NONE, ++ DI_SYNC_NONE, 0, 0); ++ /* Init template microcode */ if (disp) { - ipu_dc_write_tmpl(2, WROD(0), 0, map, SYNC_WAVE, 8, 5); - ipu_dc_write_tmpl(3, WROD(0), 0, map, SYNC_WAVE, 4, 5); - ipu_dc_write_tmpl(4, WROD(0), 0, map, SYNC_WAVE, 0, 5); + ipu_dc_write_tmpl(2, WROD(0), 0, map, SYNC_WAVE, 8, 5); + ipu_dc_write_tmpl(3, WROD(0), 0, map, SYNC_WAVE, 4, 5); + ipu_dc_write_tmpl(4, WROD(0), 0, map, SYNC_WAVE, 0, 5); } else { - ipu_dc_write_tmpl(5, WROD(0), 0, map, SYNC_WAVE, 8, 5); - ipu_dc_write_tmpl(6, WROD(0), 0, map, SYNC_WAVE, 4, 5); - ipu_dc_write_tmpl(7, WROD(0), 0, map, SYNC_WAVE, 0, 5); + ipu_dc_write_tmpl(5, WROD(0), 0, map, SYNC_WAVE, 8, 5); + ipu_dc_write_tmpl(6, WROD(0), 0, map, SYNC_WAVE, 4, 5); + ipu_dc_write_tmpl(7, WROD(0), 0, map, SYNC_WAVE, 0, 5); } if (sig.Hsync_pol) @@@ -1205,12 -1196,13 +1227,19 @@@ if (sig.clk_pol) di_gen |= DI_GEN_POL_CLK; + ++ /* Set the clock to stop at counter 6. */ ++ di_gen |= 0x6000000; } __raw_writel(di_gen, DI_GENERAL(disp)); -- __raw_writel((--vsync_cnt << DI_VSYNC_SEL_OFFSET) | -- 0x00000002, DI_SYNC_AS_GEN(disp)); ++ if (sig.interlaced) ++ __raw_writel((--vsync_cnt << DI_VSYNC_SEL_OFFSET) | ++ 0x00000002, DI_SYNC_AS_GEN(disp)); ++ else ++ __raw_writel((--vsync_cnt << DI_VSYNC_SEL_OFFSET), ++ DI_SYNC_AS_GEN(disp)); reg = __raw_readl(DI_POL(disp)); reg &= ~(DI_POL_DRDY_DATA_POLARITY | DI_POL_DRDY_POLARITY_15); @@@ -1239,9 -1231,9 +1268,10 @@@ * * @return Returns 0 on success or negative error code on fail */ --int32_t ipu_disp_set_global_alpha(ipu_channel_t channel, unsigned char enable, ++int ipu_disp_set_global_alpha(ipu_channel_t channel, unsigned char enable, uint8_t alpha) { ++ int ret; uint32_t reg; unsigned char bg_chan; @@@ -1257,8 -1249,8 +1287,9 @@@ else bg_chan = 0; -- if (!g_ipu_clk_enabled) -- clk_enable(g_ipu_clk); ++ ret = clk_enable(g_ipu_clk); ++ if (ret) ++ return ret; if (bg_chan) { reg = __raw_readl(DP_COM_CONF()); @@@ -1283,8 -1275,8 +1314,7 @@@ reg = __raw_readl(IPU_SRM_PRI2) | 0x8; __raw_writel(reg, IPU_SRM_PRI2); -- if (!g_ipu_clk_enabled) -- clk_disable(g_ipu_clk); ++ clk_disable(g_ipu_clk); return 0; } @@@ -1300,9 -1292,9 +1330,10 @@@ * * @return Returns 0 on success or negative error code on fail */ --int32_t ipu_disp_set_color_key(ipu_channel_t channel, unsigned char enable, ++int ipu_disp_set_color_key(ipu_channel_t channel, unsigned char enable, uint32_t color_key) { ++ int ret; uint32_t reg; int y, u, v; int red, green, blue; @@@ -1312,8 -1304,8 +1343,9 @@@ (channel == MEM_BG_ASYNC1 || channel == MEM_FG_ASYNC1))) return -EINVAL; -- if (!g_ipu_clk_enabled) -- clk_enable(g_ipu_clk); ++ ret = clk_enable(g_ipu_clk); ++ if (ret) ++ return ret; color_key_4rgb = 1; /* Transform color key from rgb to yuv if CSC is enabled */ @@@ -1352,8 -1344,8 +1384,7 @@@ reg = __raw_readl(IPU_SRM_PRI2) | 0x8; __raw_writel(reg, IPU_SRM_PRI2); -- if (!g_ipu_clk_enabled) -- clk_disable(g_ipu_clk); ++ clk_disable(g_ipu_clk); return 0; } diff --cc drivers/video/ipu_regs.h index d89d280b4f,982e252509..ed70d2083c --- a/drivers/video/ipu_regs.h +++ b/drivers/video/ipu_regs.h @@@ -4,9 -4,9 +4,9 @@@ * (C) Copyright 2010 * Stefano Babic, DENX Software Engineering, sbabic@denx.de * -- * Linux IPU driver for MX51: ++ * Linux IPU driver: * -- * (C) Copyright 2005-2009 Freescale Semiconductor, Inc. ++ * (C) Copyright 2005-2011 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@@ -32,31 -32,41 +32,59 @@@ #define IPU_DISP0_BASE 0x00000000 #define IPU_MCU_T_DEFAULT 8 --#define IPU_DISP1_BASE (IPU_MCU_T_DEFAULT << 25) - #define IPU_CM_REG_BASE 0x1E000000 - #define IPU_STAT_REG_BASE 0x1E000200 - #define IPU_IDMAC_REG_BASE 0x1E008000 - #define IPU_ISP_REG_BASE 0x1E010000 - #define IPU_DP_REG_BASE 0x1E018000 - #define IPU_IC_REG_BASE 0x1E020000 - #define IPU_IRT_REG_BASE 0x1E028000 - #define IPU_CSI0_REG_BASE 0x1E030000 - #define IPU_CSI1_REG_BASE 0x1E038000 - #define IPU_DI0_REG_BASE 0x1E040000 - #define IPU_DI1_REG_BASE 0x1E048000 - #define IPU_SMFC_REG_BASE 0x1E050000 - #define IPU_DC_REG_BASE 0x1E058000 - #define IPU_DMFC_REG_BASE 0x1E060000 - #define IPU_CPMEM_REG_BASE 0x1F000000 - #define IPU_LUT_REG_BASE 0x1F020000 - #define IPU_SRM_REG_BASE 0x1F040000 - #define IPU_TPM_REG_BASE 0x1F060000 - #define IPU_DC_TMPL_REG_BASE 0x1F080000 - #define IPU_ISP_TBPR_REG_BASE 0x1F0C0000 - #define IPU_VDI_REG_BASE 0x1E068000 - ++#define IPU_DISP1_BASE (gd->arch.ipu_hw_rev < IPUV3_HW_REV_IPUV3H ? \ ++ (IPU_MCU_T_DEFAULT << 25) : \ ++ 0x00000000) ++ ++#define IPUV3DEX_REG_BASE 0x1E000000 ++#define IPUV3M_REG_BASE 0x1E000000 ++#define IPUV3H_REG_BASE 0x00200000 ++ + #define IPU_CM_REG_BASE 0x00000000 + #define IPU_STAT_REG_BASE 0x00000200 + #define IPU_IDMAC_REG_BASE 0x00008000 + #define IPU_ISP_REG_BASE 0x00010000 + #define IPU_DP_REG_BASE 0x00018000 + #define IPU_IC_REG_BASE 0x00020000 + #define IPU_IRT_REG_BASE 0x00028000 + #define IPU_CSI0_REG_BASE 0x00030000 + #define IPU_CSI1_REG_BASE 0x00038000 + #define IPU_DI0_REG_BASE 0x00040000 + #define IPU_DI1_REG_BASE 0x00048000 + #define IPU_SMFC_REG_BASE 0x00050000 + #define IPU_DC_REG_BASE 0x00058000 + #define IPU_DMFC_REG_BASE 0x00060000 -#define IPU_VDI_REG_BASE 0x00680000 -#if defined(CONFIG_MX51) || defined(CONFIG_MX53) -#define IPU_CPMEM_REG_BASE 0x01000000 -#define IPU_LUT_REG_BASE 0x01020000 -#define IPU_SRM_REG_BASE 0x01040000 -#define IPU_TPM_REG_BASE 0x01060000 -#define IPU_DC_TMPL_REG_BASE 0x01080000 -#define IPU_ISP_TBPR_REG_BASE 0x010C0000 -#elif defined(CONFIG_MX6) -#define IPU_CPMEM_REG_BASE 0x00100000 -#define IPU_LUT_REG_BASE 0x00120000 -#define IPU_SRM_REG_BASE 0x00140000 -#define IPU_TPM_REG_BASE 0x00160000 -#define IPU_DC_TMPL_REG_BASE 0x00180000 -#define IPU_ISP_TBPR_REG_BASE 0x001C0000 -#endif - -#define IPU_CTRL_BASE_ADDR (IPU_SOC_BASE_ADDR + IPU_SOC_OFFSET) ++#define IPU_VDI_REG_BASE 0x00068000 ++#define IPU_CPMEM_REG_BASE (gd->arch.ipu_hw_rev >= IPUV3_HW_REV_IPUV3H ? \ ++ 0x00100000 : \ ++ 0x01000000) ++#define IPU_LUT_REG_BASE (gd->arch.ipu_hw_rev >= IPUV3_HW_REV_IPUV3H ? \ ++ 0x00120000 : \ ++ 0x01020000) ++#define IPU_SRM_REG_BASE (gd->arch.ipu_hw_rev >= IPUV3_HW_REV_IPUV3H ? \ ++ 0x00140000 : \ ++ 0x01040000) ++#define IPU_TPM_REG_BASE (gd->arch.ipu_hw_rev >= IPUV3_HW_REV_IPUV3H ? \ ++ 0x00160000 : \ ++ 0x01060000) ++#define IPU_DC_TMPL_REG_BASE (gd->arch.ipu_hw_rev >= IPUV3_HW_REV_IPUV3H ? \ ++ 0x00180000 : \ ++ 0x01080000) ++#define IPU_ISP_TBPR_REG_BASE (gd->arch.ipu_hw_rev >= IPUV3_HW_REV_IPUV3H ? \ ++ 0x001C0000 : \ ++ 0x010C0000) ++ ++#define IPU_DISP_REG_BASE_ADDR (gd->arch.ipu_hw_rev >= IPUV3_HW_REV_IPUV3H ? \ ++ IPU_CTRL_BASE_ADDR + IPUV3H_REG_BASE : \ ++ IPU_CTRL_BASE_ADDR + IPUV3M_REG_BASE) extern u32 *ipu_dc_tmpl_reg; ++extern struct clk *g_ipu_clk; ++extern struct clk *g_di_clk[2]; ++extern struct clk *g_pixel_clk[2]; ++ ++extern int g_ipu_clk_enabled; ++extern unsigned char g_dc_di_assignment[]; #define DC_EVT_NF 0 #define DC_EVT_NL 1 @@@ -303,7 -313,7 +331,7 @@@ struct ipu_dmfc u32 stat; }; --#define IPU_CM_REG ((struct ipu_cm *)(IPU_CTRL_BASE_ADDR + \ ++#define IPU_CM_REG ((struct ipu_cm *)(IPU_DISP_REG_BASE_ADDR + \ IPU_CM_REG_BASE)) #define IPU_CONF (&IPU_CM_REG->conf) #define IPU_SRM_PRI1 (&IPU_CM_REG->srm_pri1) @@@ -314,40 -324,40 +342,43 @@@ #define IPU_FS_DISP_FLOW1 (&IPU_CM_REG->fs_disp_flow[0]) #define IPU_DISP_GEN (&IPU_CM_REG->disp_gen) #define IPU_MEM_RST (&IPU_CM_REG->mem_rst) ++#define IPU_PM (&IPU_CM_REG->pm) #define IPU_GPR (&IPU_CM_REG->gpr) --#define IPU_CHA_DB_MODE_SEL(ch) (&IPU_CM_REG->ch_db_mode_sel[ch / 32]) ++#define IPU_CHA_DB_MODE_SEL(ch) (&IPU_CM_REG->ch_db_mode_sel[(ch) / 32]) --#define IPU_STAT ((struct ipu_stat *)(IPU_CTRL_BASE_ADDR + \ ++#define IPU_STAT ((struct ipu_stat *)(IPU_DISP_REG_BASE_ADDR + \ IPU_STAT_REG_BASE)) --#define IPU_CHA_CUR_BUF(ch) (&IPU_STAT->cur_buf[ch / 32]) --#define IPU_CHA_BUF0_RDY(ch) (&IPU_STAT->ch_buf0_rdy[ch / 32]) --#define IPU_CHA_BUF1_RDY(ch) (&IPU_STAT->ch_buf1_rdy[ch / 32]) ++#define IPU_CHA_CUR_BUF(ch) (&IPU_STAT->cur_buf[(ch) / 32]) ++#define IPU_CHA_BUF0_RDY(ch) (&IPU_STAT->ch_buf0_rdy[(ch) / 32]) ++#define IPU_CHA_BUF1_RDY(ch) (&IPU_STAT->ch_buf1_rdy[(ch) / 32]) #define IPU_INT_CTRL(n) (&IPU_CM_REG->int_ctrl[(n) - 1]) --#define IDMAC_REG ((struct ipu_idmac *)(IPU_CTRL_BASE_ADDR + \ ++#define IDMAC_REG ((struct ipu_idmac *)(IPU_DISP_REG_BASE_ADDR + \ IPU_IDMAC_REG_BASE)) #define IDMAC_CONF (&IDMAC_REG->conf) --#define IDMAC_CHA_EN(ch) (&IDMAC_REG->ch_en[ch / 32]) --#define IDMAC_CHA_PRI(ch) (&IDMAC_REG->ch_pri[ch / 32]) ++#define IDMAC_CHA_EN(ch) (&IDMAC_REG->ch_en[(ch) / 32]) ++#define IDMAC_CHA_PRI(ch) (&IDMAC_REG->ch_pri[(ch) / 32]) ++#define IDMAC_WM_EN(ch) (&IDMAC_REG->wm_en[(ch) / 32]) ++ ++#define DI_REG(di) ((struct ipu_di *)(IPU_DISP_REG_BASE_ADDR + \ ++ (((di) == 1) ? IPU_DI1_REG_BASE : \ ++ IPU_DI0_REG_BASE))) --#define DI_REG(di) ((struct ipu_di *)(IPU_CTRL_BASE_ADDR + \ -- ((di == 1) ? IPU_DI1_REG_BASE : \ -- IPU_DI0_REG_BASE))) #define DI_GENERAL(di) (&DI_REG(di)->general) #define DI_BS_CLKGEN0(di) (&DI_REG(di)->bs_clkgen0) #define DI_BS_CLKGEN1(di) (&DI_REG(di)->bs_clkgen1) --#define DI_SW_GEN0(di, gen) (&DI_REG(di)->sw_gen0[gen - 1]) --#define DI_SW_GEN1(di, gen) (&DI_REG(di)->sw_gen1[gen - 1]) --#define DI_STP_REP(di, gen) (&DI_REG(di)->stp_rep[(gen - 1) / 2]) ++#define DI_SW_GEN0(di, gen) (&DI_REG(di)->sw_gen0[(gen) - 1]) ++#define DI_SW_GEN1(di, gen) (&DI_REG(di)->sw_gen1[(gen) - 1]) ++#define DI_STP_REP(di, gen) (&DI_REG(di)->stp_rep[((gen) - 1) / 2]) #define DI_SYNC_AS_GEN(di) (&DI_REG(di)->sync_as) #define DI_DW_GEN(di, gen) (&DI_REG(di)->dw_gen[gen]) --#define DI_DW_SET(di, gen, set) (&DI_REG(di)->dw_set[gen + 12 * set]) ++#define DI_DW_SET(di, gen, set) (&DI_REG(di)->dw_set[(gen) + 12 * set]) #define DI_POL(di) (&DI_REG(di)->pol) #define DI_SCR_CONF(di) (&DI_REG(di)->scr_conf) --#define DMFC_REG ((struct ipu_dmfc *)(IPU_CTRL_BASE_ADDR + \ ++#define DMFC_REG ((struct ipu_dmfc *)(IPU_DISP_REG_BASE_ADDR + \ IPU_DMFC_REG_BASE)) #define DMFC_WR_CHAN (&DMFC_REG->wr_chan) #define DMFC_WR_CHAN_DEF (&DMFC_REG->wr_chan_def) @@@ -356,12 -366,12 +387,12 @@@ #define DMFC_GENERAL1 (&DMFC_REG->general[0]) #define DMFC_IC_CTRL (&DMFC_REG->ic_ctrl) -- --#define DC_REG ((struct ipu_dc *)(IPU_CTRL_BASE_ADDR + \ ++#define DC_REG ((struct ipu_dc *)(IPU_DISP_REG_BASE_ADDR + \ IPU_DC_REG_BASE)) --#define DC_MAP_CONF_PTR(n) (&DC_REG->dc_map_ptr[n / 2]) --#define DC_MAP_CONF_VAL(n) (&DC_REG->dc_map_val[n / 2]) ++#define DC_MAP_CONF_PTR(n) (&DC_REG->dc_map_ptr[(n) / 2]) ++#define DC_MAP_CONF_VAL(n) (&DC_REG->dc_map_val[(n) / 2]) ++DECLARE_GLOBAL_DATA_PTR; static inline struct ipu_dc_ch *dc_ch_offset(int ch) { @@@ -381,10 -391,10 +412,9 @@@ printf("%s: invalid channel %d\n", __func__, ch); return NULL; } -- } --#define DC_RL_CH(ch, evt) (&dc_ch_offset(ch)->rl[evt / 2]) ++#define DC_RL_CH(ch, evt) (&dc_ch_offset(ch)->rl[(evt) / 2]) #define DC_WR_CH_CONF(ch) (&dc_ch_offset(ch)->wr_ch_conf) #define DC_WR_CH_ADDR(ch) (&dc_ch_offset(ch)->wr_ch_addr) @@@ -400,7 -410,7 +430,7 @@@ #define DP_ASYNC0 0x60 #define DP_ASYNC1 0xBC --#define DP_REG ((struct ipu_dp *)(IPU_CTRL_BASE_ADDR + \ ++#define DP_REG ((struct ipu_dp *)(IPU_DISP_REG_BASE_ADDR + \ IPU_DP_REG_BASE)) #define DP_COM_CONF() (&DP_REG->com_conf_sync) #define DP_GRAPH_WIND_CTRL() (&DP_REG->graph_wind_ctrl_sync) @@@ -413,6 -423,6 +443,6 @@@ #define DP_CSC_1() (&DP_REG->csc_sync[1]) /* DC template opcodes */ --#define WROD(lf) (0x18 | (lf << 1)) ++#define WROD(lf) (0x18 | ((lf) << 1)) #endif diff --cc drivers/video/mxc_ipuv3_fb.c index 72f8603c35,ace226cece..9b26029223 --- a/drivers/video/mxc_ipuv3_fb.c +++ b/drivers/video/mxc_ipuv3_fb.c @@@ -4,9 -4,9 +4,9 @@@ * (C) Copyright 2010 * Stefano Babic, DENX Software Engineering, sbabic@denx.de * -- * MX51 Linux framebuffer: ++ * IPUv3 Linux framebuffer: * -- * (C) Copyright 2004-2010 Freescale Semiconductor, Inc. ++ * (C) Copyright 2004-2011 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@@ -27,6 -27,6 +27,8 @@@ * MA 02111-1307 USA */ ++/* #define DEBUG */ ++// #define DEBUG #include #include #include @@@ -34,23 -34,22 +36,46 @@@ #include #include #include ++#include ++#include #include #include "videomodes.h" --#include "ipu.h" #include "mxcfb.h" -#include "ipu_regs.h" + +DECLARE_GLOBAL_DATA_PTR; + ++extern vidinfo_t panel_info; ++ ++void *lcd_base; /* Start of framebuffer memory */ ++void *lcd_console_address; /* Start of console buffer */ ++ ++int lcd_line_length; ++int lcd_color_fg; ++int lcd_color_bg; ++ ++short console_col; ++short console_row; + static int mxcfb_map_video_memory(struct fb_info *fbi); static int mxcfb_unmap_video_memory(struct fb_info *fbi); --/* graphics setup */ --static GraphicDevice panel; - static struct fb_videomode *gmode; -static struct fb_videomode const *gmode; --static uint8_t gdisp; --static uint32_t gpixfmt; ++void lcd_initcolregs(void) ++{ ++} ++ ++void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue) ++{ ++} + -void fb_videomode_to_var(struct fb_var_screeninfo *var, ++void lcd_disable(void) ++{ ++} ++ ++void lcd_panel_disable(void) ++{ ++} + +static void fb_videomode_to_var(struct fb_var_screeninfo *var, const struct fb_videomode *mode) { var->xres = mode->xres; @@@ -119,10 -121,6 +147,8 @@@ static uint32_t bpp_to_pixfmt(struct fb case 16: pixfmt = IPU_PIX_FMT_RGB565; break; - + case 8: + pixfmt = IPU_PIX_FMT_GENERIC; } return pixfmt; } @@@ -420,9 -430,9 +461,6 @@@ static int mxcfb_map_video_memory(struc fbi->screen_size = fbi->fix.smem_len; -- /* Clear the screen */ - memset(fbi->screen_base, 0, fbi->fix.smem_len); - memset((char *)fbi->screen_base, 0, fbi->fix.smem_len); -- return 0; } @@@ -489,8 -502,8 +527,7 @@@ static struct fb_info *mxcfb_init_fbinf * * @return Appropriate error code to the kernel common code */ --static int mxcfb_probe(u32 interface_pix_fmt, uint8_t disp, - struct fb_videomode *mode) - struct fb_videomode const *mode) ++static int mxcfb_probe(u32 interface_pix_fmt, struct fb_videomode *mode, int di) { struct fb_info *fbi; struct mxcfb_info *mxcfbi; @@@ -512,7 -527,7 +549,7 @@@ mxcfbi->blank = FB_BLANK_POWERDOWN; } -- mxcfbi->ipu_di = disp; ++ mxcfbi->ipu_di = di; ipu_disp_set_global_alpha(mxcfbi->ipu_ch, 1, 0x80); ipu_disp_set_color_key(mxcfbi->ipu_ch, 0, 0); @@@ -523,10 -538,10 +560,12 @@@ mxcfb_info[mxcfbi->ipu_di] = fbi; /* Need dummy values until real panel is configured */ ++ fbi->var.xres = panel_info.vl_col; ++ fbi->var.yres = panel_info.vl_row; mxcfbi->ipu_di_pix_fmt = interface_pix_fmt; fb_videomode_to_var(&fbi->var, mode); - fbi->var.bits_per_pixel = default_bpp; - fbi->var.bits_per_pixel = 16; ++ fbi->var.bits_per_pixel = NBITS(panel_info.vl_bpix); fbi->fix.line_length = fbi->var.xres * (fbi->var.bits_per_pixel / 8); fbi->fix.smem_len = fbi->var.yres_virtual * fbi->fix.line_length; @@@ -539,76 -558,74 +578,64 @@@ mxcfb_set_par(fbi); -- panel.winSizeX = mode->xres; -- panel.winSizeY = mode->yres; -- panel.plnSizeX = mode->xres; -- panel.plnSizeY = mode->yres; -- -- panel.frameAdrs = (u32)fbi->screen_base; -- panel.memSize = fbi->screen_size; ++ lcd_line_length = (panel_info.vl_col * NBITS(panel_info.vl_bpix)) / 8; - switch (fbi->var.bits_per_pixel) { - case 8: - panel.gdfBytesPP = 1; - panel.gdfIndex = GDF__8BIT_INDEX; - break; - - case 16: - panel.gdfBytesPP = 2; - panel.gdfIndex = GDF_16BIT_565RGB; - break; - - case 32: - panel.gdfBytesPP = 4; - panel.gdfIndex = GDF_32BIT_X888RGB; - break; - - default: - hang(); - } - panel.gdfBytesPP = 2; - panel.gdfIndex = GDF_16BIT_565RGB; ++ debug("MXC IPUV3 configured\n" ++ "XRES = %d YRES = %d BitsXpixel = %d\n", ++ panel_info.vl_col, ++ panel_info.vl_row, ++ panel_info.vl_bpix); ipu_dump_registers(); return 0; - -err0: - return ret; } - void mxcfb_disable(void) -void ipuv3_fb_shutdown(void) ++ulong calc_fbsize(void) { - ipu_disable_channel(MEM_BG_SYNC); - ipu_disable_channel(MEM_DC_SYNC); - ipu_uninit_channel(MEM_BG_SYNC); - ipu_uninit_channel(MEM_DC_SYNC); - int i; - struct ipu_stat *stat = (struct ipu_stat *)IPU_STAT; - - for (i = 0; i < ARRAY_SIZE(mxcfb_info); i++) { - struct fb_info *fbi = mxcfb_info[i]; - if (fbi) { - struct mxcfb_info *mxc_fbi = fbi->par; - ipu_disable_channel(mxc_fbi->ipu_ch); - ipu_uninit_channel(mxc_fbi->ipu_ch); - } - } - for (i = 0; i < ARRAY_SIZE(stat->int_stat); i++) { - __raw_writel(__raw_readl(&stat->int_stat[i]), - &stat->int_stat[i]); - } ++ return (panel_info.vl_col * panel_info.vl_row * ++ NBITS(panel_info.vl_bpix)) / 8; } --void *video_hw_init(void) ++int overwrite_console(void) { -- int ret; ++ /* Keep stdout / stderr on serial, our LCD is for splashscreen only */ ++ return 1; ++} -- ret = ipu_probe(); -- if (ret) -- puts("Error initializing IPU\n"); ++#if 0 ++void lcd_ctrl_init(void *lcdbase) ++{ ++ u32 mem_len = panel_info.vl_col * ++ panel_info.vl_row * ++ NBITS(panel_info.vl_bpix) / 8; -- ret = mxcfb_probe(gpixfmt, gdisp, gmode); - debug("Framebuffer at 0x%08x\n", panel.frameAdrs); - debug("Framebuffer at 0x%x\n", (unsigned int)panel.frameAdrs); ++ /* ++ * We rely on lcdbase being a physical address, i.e., either MMU off, ++ * or 1-to-1 mapping. Might want to add some virt2phys here. ++ */ ++ if (!lcdbase) ++ return; - return &panel; - return (void *)&panel; ++ memset(lcdbase, 0, mem_len); } ++#endif --void video_set_lut(unsigned int index, /* color number */ -- unsigned char r, /* red */ -- unsigned char g, /* green */ -- unsigned char b /* blue */ -- ) ++int ipuv3_fb_init(struct fb_videomode *mode, int di, unsigned int interface_pix_fmt, ++ ipu_di_clk_parent_t di_clk_parent, unsigned long di_clk_val, int bpp) { -- return; --} ++ int ret; - int mx5_fb_init(struct fb_videomode *mode, uint8_t disp, uint32_t pixfmt, int bpp) -int ipuv3_fb_init(struct fb_videomode const *mode, - uint8_t disp, - uint32_t pixfmt) --{ -- gmode = mode; -- gdisp = disp; -- gpixfmt = pixfmt; - default_bpp = bpp; ++// default_bpp = bpp; -- return 0; ++ ret = ipu_probe(di, di_clk_parent, di_clk_val); ++ if (ret) { ++ printf("Error initializing IPU\n"); ++ return ret; ++ } ++ ++ debug("Framebuffer at %p\n", lcd_base); ++ ret = mxcfb_probe(interface_pix_fmt, mode, di); ++ ++ return ret; } diff --cc drivers/video/mxsfb.c index 93f7e2bebc,0000000000..70f35435ed mode 100644,000000..100644 --- a/drivers/video/mxsfb.c +++ b/drivers/video/mxsfb.c @@@ -1,312 -1,0 +1,310 @@@ +/* + * Copyright (C) 2012 Lothar Waßmann + * - * LCD driver for i.MX28 ++ * LCD driver for i.MXS + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include + - static ushort mxsfb_cmap[256]; +vidinfo_t panel_info = { + /* set to max. size supported by SoC */ + .vl_col = 800, + .vl_row = 480, + + .vl_bpix = LCD_COLOR24, /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */ - .cmap = mxsfb_cmap, +}; + +static int bits_per_pixel; +static int color_depth; +static uint32_t pix_fmt; +static struct fb_var_screeninfo mxsfb_var; + - static struct mx28_lcdif_regs *lcd_regs = (void *)MXS_LCDIF_BASE; ++static struct mxs_lcdif_regs *lcd_regs = (void *)MXS_LCDIF_BASE; + +void *lcd_base; /* Start of framebuffer memory */ +void *lcd_console_address; /* Start of console buffer */ + +int lcd_line_length; +int lcd_color_fg; +int lcd_color_bg; + +short console_col; +short console_row; + +void lcd_initcolregs(void) +{ +} + +void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue) +{ +} + +#define fourcc_str(fourcc) ((fourcc) >> 0) & 0xff, \ + ((fourcc) >> 8) & 0xff, \ + ((fourcc) >> 16) & 0xff, \ + ((fourcc) >> 24) & 0xff + +#define LCD_CTRL_DEFAULT (LCDIF_CTRL_LCDIF_MASTER | \ + LCDIF_CTRL_BYPASS_COUNT | \ + LCDIF_CTRL_DOTCLK_MODE) + +#define LCD_CTRL1_DEFAULT 0 +#define LCD_CTRL2_DEFAULT LCDIF_CTRL2_OUTSTANDING_REQS_REQ_2 + +#define LCD_VDCTRL0_DEFAULT (LCDIF_VDCTRL0_ENABLE_PRESENT | \ + LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT | \ + LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT) +#define LCD_VDCTRL1_DEFAULT 0 +#define LCD_VDCTRL2_DEFAULT 0 +#define LCD_VDCTRL3_DEFAULT 0 +#define LCD_VDCTRL4_DEFAULT LCDIF_VDCTRL4_SYNC_SIGNALS_ON + +void video_hw_init(void *lcdbase) +{ + int ret; + unsigned int div = 0, best = 0, pix_clk; + u32 frac1; + const unsigned long lcd_clk = 480000000; + u32 lcd_ctrl = LCD_CTRL_DEFAULT | LCDIF_CTRL_RUN; + u32 lcd_ctrl1 = LCD_CTRL1_DEFAULT, lcd_ctrl2 = LCD_CTRL2_DEFAULT; + u32 lcd_vdctrl0 = LCD_VDCTRL0_DEFAULT; + u32 lcd_vdctrl1 = LCD_VDCTRL1_DEFAULT; + u32 lcd_vdctrl2 = LCD_VDCTRL2_DEFAULT; + u32 lcd_vdctrl3 = LCD_VDCTRL3_DEFAULT; + u32 lcd_vdctrl4 = LCD_VDCTRL4_DEFAULT; - struct mx28_clkctrl_regs *clk_regs = (void *)MXS_CLKCTRL_BASE; ++ struct mxs_clkctrl_regs *clk_regs = (void *)MXS_CLKCTRL_BASE; + char buf1[16], buf2[16]; + + /* pixel format in memory */ + switch (color_depth) { + case 8: + lcd_ctrl |= LCDIF_CTRL_WORD_LENGTH_8BIT; + lcd_ctrl1 |= LCDIF_CTRL1_BYTE_PACKING_FORMAT(1); + break; + + case 16: + lcd_ctrl |= LCDIF_CTRL_WORD_LENGTH_16BIT; + lcd_ctrl1 |= LCDIF_CTRL1_BYTE_PACKING_FORMAT(3); + break; + + case 18: + lcd_ctrl |= LCDIF_CTRL_WORD_LENGTH_18BIT; + lcd_ctrl1 |= LCDIF_CTRL1_BYTE_PACKING_FORMAT(7); + break; + + case 24: + lcd_ctrl |= LCDIF_CTRL_WORD_LENGTH_24BIT; + lcd_ctrl1 |= LCDIF_CTRL1_BYTE_PACKING_FORMAT(7); + break; + + default: + printf("Invalid bpp: %d\n", color_depth); + return; + } + + /* pixel format on the LCD data pins */ + switch (pix_fmt) { + case PIX_FMT_RGB332: + lcd_ctrl |= LCDIF_CTRL_LCD_DATABUS_WIDTH_8BIT; + break; + + case PIX_FMT_RGB565: + lcd_ctrl |= LCDIF_CTRL_LCD_DATABUS_WIDTH_16BIT; + break; + + case PIX_FMT_BGR666: + lcd_ctrl |= 1 << LCDIF_CTRL_INPUT_DATA_SWIZZLE_OFFSET; + /* fallthru */ + case PIX_FMT_RGB666: + lcd_ctrl |= LCDIF_CTRL_LCD_DATABUS_WIDTH_18BIT; + break; + + case PIX_FMT_BGR24: + lcd_ctrl |= 1 << LCDIF_CTRL_INPUT_DATA_SWIZZLE_OFFSET; + /* fallthru */ + case PIX_FMT_RGB24: + lcd_ctrl |= LCDIF_CTRL_LCD_DATABUS_WIDTH_24BIT; + break; + + default: + printf("Invalid pixel format: %c%c%c%c\n", fourcc_str(pix_fmt)); + return; + } + + pix_clk = PICOS2KHZ(mxsfb_var.pixclock); + debug("designated pix_clk: %sMHz\n", strmhz(buf1, pix_clk * 1000)); + + for (frac1 = 18; frac1 < 36; frac1++) { + static unsigned int err = ~0; + unsigned long clk = lcd_clk / 1000 * 18 / frac1; + unsigned int d = (clk + pix_clk - 1) / pix_clk; + unsigned int diff = abs(clk / d - pix_clk); + + debug("frac1=%u div=%u lcd_clk=%-8sMHz pix_clk=%-8sMHz diff=%u err=%u\n", + frac1, d, strmhz(buf1, clk * 1000), strmhz(buf2, clk * 1000 / d), + diff, err); + + if (clk < pix_clk) + break; + if (d > 255) + continue; + + if (diff < err) { + best = frac1; + div = d; + err = diff; + if (err == 0) + break; + } + } + if (div == 0) { + printf("Requested pixel clock %sMHz out of range\n", + strmhz(buf1, pix_clk * 1000)); + return; + } + + debug("div=%lu(%u*%u/18) for pixel clock %sMHz with base clock %sMHz\n", + lcd_clk / pix_clk / 1000, best, div, + strmhz(buf1, lcd_clk / div * 18 / best), + strmhz(buf2, lcd_clk)); + + frac1 = (readl(&clk_regs->hw_clkctrl_frac1_reg) & ~0xff) | best; + writel(frac1, &clk_regs->hw_clkctrl_frac1_reg); + writel(1 << 14, &clk_regs->hw_clkctrl_clkseq_clr); + + /* enable LCD clk and fractional divider */ + writel(div, &clk_regs->hw_clkctrl_lcdif_reg); + while (readl(&clk_regs->hw_clkctrl_lcdif_reg) & (1 << 29)) + ; + - ret = mx28_reset_block(&lcd_regs->hw_lcdif_ctrl_reg); ++ ret = mxs_reset_block(&lcd_regs->hw_lcdif_ctrl_reg); + if (ret) { + printf("Failed to reset LCD controller: LCDIF_CTRL: %08x CLKCTRL_LCDIF: %08x\n", + readl(&lcd_regs->hw_lcdif_ctrl_reg), + readl(&clk_regs->hw_clkctrl_lcdif_reg)); + return; + } + + if (mxsfb_var.sync & FB_SYNC_HOR_HIGH_ACT) + lcd_vdctrl0 |= LCDIF_VDCTRL0_HSYNC_POL; + + if (mxsfb_var.sync & FB_SYNC_VERT_HIGH_ACT) + lcd_vdctrl0 |= LCDIF_VDCTRL0_HSYNC_POL; + + if (mxsfb_var.sync & FB_SYNC_DATA_ENABLE_HIGH_ACT) + lcd_vdctrl0 |= LCDIF_VDCTRL0_ENABLE_POL; + + if (mxsfb_var.sync & FB_SYNC_DOTCLK_FALLING_ACT) + lcd_vdctrl0 |= LCDIF_VDCTRL0_DOTCLK_POL; + + lcd_vdctrl0 |= LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH(mxsfb_var.vsync_len); + lcd_vdctrl1 |= LCDIF_VDCTRL1_VSYNC_PERIOD(mxsfb_var.vsync_len + + mxsfb_var.upper_margin + + mxsfb_var.lower_margin + + mxsfb_var.yres); + lcd_vdctrl2 |= LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH(mxsfb_var.hsync_len); + lcd_vdctrl2 |= LCDIF_VDCTRL2_HSYNC_PERIOD(mxsfb_var.hsync_len + + mxsfb_var.left_margin + + mxsfb_var.right_margin + + mxsfb_var.xres); + + lcd_vdctrl3 |= LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT(mxsfb_var.left_margin + + mxsfb_var.hsync_len); + lcd_vdctrl3 |= LCDIF_VDCTRL3_VERTICAL_WAIT_CNT(mxsfb_var.upper_margin + + mxsfb_var.vsync_len); + + lcd_vdctrl4 |= LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT(mxsfb_var.xres); + + writel((u32)lcdbase, &lcd_regs->hw_lcdif_next_buf_reg); + writel(LCDIF_TRANSFER_COUNT_H_COUNT(mxsfb_var.xres) | + LCDIF_TRANSFER_COUNT_V_COUNT(mxsfb_var.yres), + &lcd_regs->hw_lcdif_transfer_count_reg); + + writel(lcd_vdctrl0, &lcd_regs->hw_lcdif_vdctrl0_reg); + writel(lcd_vdctrl1, &lcd_regs->hw_lcdif_vdctrl1_reg); + writel(lcd_vdctrl2, &lcd_regs->hw_lcdif_vdctrl2_reg); + writel(lcd_vdctrl3, &lcd_regs->hw_lcdif_vdctrl3_reg); + writel(lcd_vdctrl4, &lcd_regs->hw_lcdif_vdctrl4_reg); + + writel(lcd_ctrl1, &lcd_regs->hw_lcdif_ctrl1_reg); + writel(lcd_ctrl2, &lcd_regs->hw_lcdif_ctrl2_reg); + + writel(lcd_ctrl, &lcd_regs->hw_lcdif_ctrl_reg); + + debug("mxsfb framebuffer driver initialized\n"); +} + +void mxsfb_disable(void) +{ + u32 lcd_ctrl = readl(&lcd_regs->hw_lcdif_ctrl_reg); + + writel(lcd_ctrl & ~LCDIF_CTRL_RUN, &lcd_regs->hw_lcdif_ctrl_reg); +} + +int mxsfb_init(struct fb_videomode *mode, uint32_t pixfmt, int bpp) +{ + switch (bpp) { + case 8: + bits_per_pixel = 8; + panel_info.vl_bpix = LCD_COLOR8; + break; + + case 16: + bits_per_pixel = 16; + panel_info.vl_bpix = LCD_COLOR16; + break; + + case 18: + bits_per_pixel = 32; + panel_info.vl_bpix = LCD_COLOR24; + break; + + case 24: + bits_per_pixel = 32; + panel_info.vl_bpix = LCD_COLOR24; + break; + + default: + return -EINVAL; + } + + pix_fmt = pixfmt; + color_depth = bpp; + + lcd_line_length = bits_per_pixel / 8 * mode->xres; + + mxsfb_var.xres = mode->xres; + mxsfb_var.yres = mode->yres; + mxsfb_var.xres_virtual = mode->xres; + mxsfb_var.yres_virtual = mode->yres; + mxsfb_var.pixclock = mode->pixclock; + mxsfb_var.left_margin = mode->left_margin; + mxsfb_var.right_margin = mode->right_margin; + mxsfb_var.upper_margin = mode->upper_margin; + mxsfb_var.lower_margin = mode->lower_margin; + mxsfb_var.hsync_len = mode->hsync_len; + mxsfb_var.vsync_len = mode->vsync_len; + mxsfb_var.sync = mode->sync; + + panel_info.vl_col = mode->xres; + panel_info.vl_row = mode->yres; + + return 0; +} diff --cc drivers/watchdog/imx_watchdog.c index 0000000000,50e602af12..ee53a58251 mode 000000,100644..100644 --- a/drivers/watchdog/imx_watchdog.c +++ b/drivers/watchdog/imx_watchdog.c @@@ -1,0 -1,66 +1,61 @@@ + /* + * watchdog.c - driver for i.mx on-chip watchdog + * + * Licensed under the GPL-2 or later. + */ + + #include + #include + #include + #include + + struct watchdog_regs { + u16 wcr; /* Control */ + u16 wsr; /* Service */ + u16 wrsr; /* Reset Status */ + }; + + #define WCR_WDZST 0x01 + #define WCR_WDBG 0x02 + #define WCR_WDE 0x04 /* WDOG enable */ + #define WCR_WDT 0x08 + #define WCR_WDW 0x80 + #define SET_WCR_WT(x) (x << 8) + + #ifdef CONFIG_IMX_WATCHDOG + void hw_watchdog_reset(void) + { + struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR; + + writew(0x5555, &wdog->wsr); + writew(0xaaaa, &wdog->wsr); + } + + void hw_watchdog_init(void) + { + struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR; + u16 timeout; + + /* + * The timer watchdog can be set between + * 0.5 and 128 Seconds. If not defined + * in configuration file, sets 128 Seconds + */ + #ifndef CONFIG_WATCHDOG_TIMEOUT_MSECS + #define CONFIG_WATCHDOG_TIMEOUT_MSECS 128000 + #endif + timeout = (CONFIG_WATCHDOG_TIMEOUT_MSECS / 500) - 1; + writew(WCR_WDZST | WCR_WDBG | WCR_WDE | WCR_WDT | + WCR_WDW | SET_WCR_WT(timeout), &wdog->wcr); + hw_watchdog_reset(); + } + #endif + + void reset_cpu(ulong addr) + { + struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR; + - writew(WCR_WDE, &wdog->wcr); - writew(0x5555, &wdog->wsr); - writew(0xaaaa, &wdog->wsr); /* load minimum 1/2 second timeout */ + while (1) { - /* - * spin for .5 seconds before reset - */ ++ writew(0, &wdog->wcr); /* clear SRS initiating SOFT reset */ + } + } diff --cc dts/Makefile index 67b2997483,785104e6d6..d3b48d21fe --- a/dts/Makefile +++ b/dts/Makefile @@@ -36,7 -36,9 +36,8 @@@ $(error Your architecture does not hav Please define CONFIG_ARCH_DEVICE_TREE)) # We preprocess the device tree file provide a useful define - DTS_CPPFLAGS := -DARCH_CPU_DTS=\"$(SRCTREE)/arch/$(ARCH)/dts/$(CONFIG_ARCH_DEVICE_TREE).dtsi\" -DTS_CPPFLAGS := -ansi \ - -DARCH_CPU_DTS=\"$(SRCTREE)/arch/$(ARCH)/dts/$(CONFIG_ARCH_DEVICE_TREE).dtsi\" \ ++DTS_CPPFLAGS := -DARCH_CPU_DTS=\"$(SRCTREE)/arch/$(ARCH)/dts/$(CONFIG_ARCH_DEVICE_TREE).dtsi\" \ + -DBOARD_DTS=\"$(SRCTREE)/board/$(VENDOR)/$(BOARD)/dts/$(DEVICE_TREE).dts\" all: $(obj).depend $(LIB) @@@ -47,11 -49,11 +48,11 @@@ DT_BIN := $(obj)dt.dt $(DT_BIN): $(TOPDIR)/board/$(VENDOR)/dts/$(DEVICE_TREE).dts rc=$$( \ - cat $< | $(CPP) -P $(DTS_CPPFLAGS) - | \ - { { $(DTC) -R 4 -p 0x1000 -O dtb -o ${DT_BIN} - 2>&1 ; \ + cat $< | $(CPP) -P -x assembler-with-cpp $(DTS_CPPFLAGS) - | \ + { { $(DTC) -R 4 -p 0x1000 -O dtb -o ${DT_BIN} - >&2 ; \ echo $$? >&3 ; } | \ grep -v '^DTC: dts->dtb on file' ; \ - } 3>&1 ) ; \ + } 3>&1 1>&2 ) ; \ exit $$rc process_lds = \ @@@ -66,17 -68,19 +67,19 @@@ $(obj)dt.o: $(DT_BIN # We look in the LDSCRIPT first. # Then try the linker which should give us the answer. # Then check it worked. - [ -n "$${LDSCRIPT}" ] && oformat=`$(call process_lds,cat $(LDSCRIPT),FORMAT)` &&\ + [ -n "$(LDSCRIPT)" ] && \ + oformat=`$(call process_lds,cat $(LDSCRIPT),FORMAT)` && \ oarch=`$(call process_lds,cat $(LDSCRIPT),ARCH)` ;\ + \ - [ -z $${oformat} ] && \ + [ -z "$${oformat}" ] && \ oformat=`$(call process_lds,$(GET_LDS),FORMAT)` ;\ - [ -z $${oarch} ] && \ + [ -z "$${oarch}" ] && \ oarch=`$(call process_lds,$(GET_LDS),ARCH)` ;\ \ - [ -z $${oformat} ] && \ + [ -z "$${oformat}" ] && \ echo "Cannot read OUTPUT_FORMAT from lds file $(LDSCRIPT)" && \ exit 1 || true ;\ - [ -z $${oarch} ] && \ + [ -z "$${oarch}" ] && \ echo "Cannot read OUTPUT_ARCH from lds file $(LDSCRIPT)" && \ exit 1 || true ;\ \ diff --cc include/asm-generic/gpio.h index e003103e3c,bfedbe4459..dceaddcb7c --- a/include/asm-generic/gpio.h +++ b/include/asm-generic/gpio.h @@@ -41,23 -41,12 +41,24 @@@ * an error value of -1. */ +enum gpio_flags { + GPIOF_INPUT, + GPIOF_OUTPUT_INIT_LOW, + GPIOF_OUTPUT_INIT_HIGH, +}; + +struct gpio { + unsigned int gpio; + enum gpio_flags flags; + const char *label; +}; + /** - * Request ownership of a GPIO. + * Request a gpio. This should be called before any of the other functions + * are used on this gpio. * - * @param gpio GPIO number - * @param label Name given to the GPIO + * @param gp GPIO number + * @param label User label for this GPIO * @return 0 if ok, -1 on error */ int gpio_request(unsigned gpio, const char *label); diff --cc include/configs/tx25.h index 3dfafa5077,80194d824c..34575d6560 --- a/include/configs/tx25.h +++ b/include/configs/tx25.h @@@ -18,8 -18,8 +18,8 @@@ * MA 02111-1307 USA */ --#ifndef __CONFIG_H --#define __CONFIG_H ++#ifndef __CONFIGS_TX25_H ++#define __CONFIGS_TX25_H /* @@@ -182,4 -176,4 +176,4 @@@ #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \ GENERATED_GBL_DATA_SIZE) --#endif /* __CONFIG_H */ ++#endif /* __CONFIGS_TX25_H */ diff --cc include/configs/tx28.h index 452ced4168,0000000000..1f5f382462 mode 100644,000000..100644 --- a/include/configs/tx28.h +++ b/include/configs/tx28.h @@@ -1,288 -1,0 +1,290 @@@ +/* + * Copyright (C) 2012 + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ - #ifndef __TX28_H - #define __TX28_H ++#ifndef __CONFIGS_TX28_H ++#define __CONFIGS_TX28_H + - #include +#include +#include + +/* + * Ka-Ro TX28 board - SoC configuration + */ +#define CONFIG_MX28 /* i.MX28 SoC */ +#define CONFIG_MXS_GPIO /* GPIO control */ +#define CONFIG_SYS_HZ 1000 /* Ticks per second */ +#ifdef CONFIG_TX28_S +#define PHYS_SDRAM_1_SIZE SZ_64M +#define TX28_MOD_SUFFIX "1" +#else +#define PHYS_SDRAM_1_SIZE SZ_128M +#define CONFIG_SYS_SPL_FIXED_BATT_SUPPLY +#define TX28_MOD_SUFFIX "0" +#endif + +#ifndef CONFIG_SPL_BUILD +#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_SHOW_ACTIVITY +#define CONFIG_ARCH_CPU_INIT +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_BOARD_LATE_INIT +#define CONFIG_BOARD_EARLY_INIT_F + +/* LCD Logo and Splash screen support */ +#define CONFIG_LCD +#ifdef CONFIG_LCD +#define CONFIG_SPLASH_SCREEN +#define CONFIG_SPLASH_SCREEN_ALIGN +#define CONFIG_VIDEO_MXS +#define CONFIG_LCD_LOGO +#define LCD_BPP LCD_COLOR24 +#define CONFIG_CMD_BMP +#define CONFIG_VIDEO_BMP_RLE8 +#endif /* CONFIG_LCD */ +#endif /* CONFIG_SPL_BUILD */ + +/* + * Memory configuration options + */ +#define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of SDRAM */ +#define PHYS_SDRAM_1 0x40000000 /* SDRAM Bank #1 */ +#define CONFIG_STACKSIZE SZ_64K +#define CONFIG_SYS_MALLOC_LEN SZ_4M +#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1 /* Memtest start address */ +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + SZ_4M) + +/* + * U-Boot general configurations + */ +#define CONFIG_SYS_LONGHELP +#define CONFIG_SYS_PROMPT "TX28 U-Boot > " +#define CONFIG_SYS_CBSIZE 2048 /* Console I/O buffer size */ +#define CONFIG_SYS_PBSIZE \ + (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) + /* Print buffer size */ +#define CONFIG_SYS_MAXARGS 64 /* Max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + /* Boot argument buffer size */ +#define CONFIG_VERSION_VARIABLE /* U-BOOT version */ +#define CONFIG_AUTO_COMPLETE /* Command auto complete */ +#define CONFIG_CMDLINE_EDITING /* Command history etc */ + +#define CONFIG_SYS_64BIT_VSPRINTF +#define CONFIG_SYS_NO_FLASH + +/* + * Flattened Device Tree (FDT) support +*/ +#define CONFIG_OF_LIBFDT +#ifdef CONFIG_OF_LIBFDT +#define CONFIG_FDT_FIXUP_PARTITIONS +#define CONFIG_OF_EMBED +#define CONFIG_OF_BOARD_SETUP +#define CONFIG_DEFAULT_DEVICE_TREE tx28 +#define CONFIG_ARCH_DEVICE_TREE mx28 ++#define CONFIG_SYS_FDT_ADDR (PHYS_SDRAM_1 + SZ_16M) +#endif + +/* + * Boot Linux + */ +#define xstr(s) str(s) +#define str(s) #s - #define __pfx(x, s) (x##s) - #define _pfx(x, s) __pfx(x, s) ++#define __pfx(x, s) (x##s) ++#define _pfx(x, s) __pfx(x, s) + +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS - #define CONFIG_BOOTDELAY 3 ++#define CONFIG_BOOTDELAY 3 +#define CONFIG_ZERO_BOOTDELAY_CHECK - #define CONFIG_SYS_AUTOLOAD "no" - #define CONFIG_BOOTFILE "uImage" - #define CONFIG_BOOTARGS "console=ttyAMA0,115200 ro debug panic=1" - #define CONFIG_BOOTCOMMAND "run bootcmd_nand" - #define CONFIG_LOADADDR 43000000 - #define CONFIG_SYS_LOAD_ADDR _pfx(0x, CONFIG_LOADADDR) - #define CONFIG_U_BOOT_IMG_SIZE SZ_1M ++#define CONFIG_SYS_AUTOLOAD "no" ++#define CONFIG_BOOTFILE "uImage" ++#define CONFIG_BOOTARGS "console=ttyAMA0,115200 ro debug panic=1" ++#define CONFIG_BOOTCOMMAND "run bootcmd_nand" ++#define CONFIG_LOADADDR 43000000 ++#define CONFIG_SYS_LOAD_ADDR _pfx(0x, CONFIG_LOADADDR) ++#define CONFIG_U_BOOT_IMG_SIZE SZ_1M + +/* + * Extra Environments + */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "autostart=no\0" \ + "baseboard=stk5-v3\0" \ + "bootargs_mmc=run default_bootargs;set bootargs ${bootargs}" \ + " root=/dev/mmcblk0p3 rootwait\0" \ + "bootargs_nand=run default_bootargs;set bootargs ${bootargs}" \ + " root=/dev/mtdblock3 rootfstype=jffs2\0" \ - "nfsroot=/tftpboot/rootfs\0" \ + "bootargs_nfs=run default_bootargs;set bootargs ${bootargs}" \ + " root=/dev/nfs ip=dhcp nfsroot=${serverip}:${nfsroot},nolock\0"\ + "bootcmd_mmc=set autostart no;run bootargs_mmc;" \ - " fatload mmc 0 ${loadaddr} uImage;run bootm_cmd\0" \ ++ "fatload mmc 0 ${loadaddr} uImage;run bootm_cmd\0" \ + "bootcmd_nand=set autostart no;run bootargs_nand;" \ - " nboot linux;run bootm_cmd\0" \ ++ "nboot linux;run bootm_cmd\0" \ + "bootcmd_net=set autostart no;run bootargs_nfs;dhcp;" \ - " run bootm_cmd\0" \ ++ "run bootm_cmd\0" \ + "bootm_cmd=fdt boardsetup;bootm ${loadaddr} - ${fdtaddr}\0" \ + "default_bootargs=set bootargs " CONFIG_BOOTARGS \ + " mxsfb.mode=${video_mode} ${append_bootargs}\0" \ + "fdtaddr=41000000\0" \ + "mtdids=" MTDIDS_DEFAULT "\0" \ + "mtdparts=" MTDPARTS_DEFAULT "\0" \ ++ "nfsroot=/tftpboot/rootfs\0" \ + "otg_mode=device\0" \ + "touchpanel=tsc2007\0" \ + "video_mode=VGA\0" + +#define MTD_NAME "gpmi-nand" +#define MTDIDS_DEFAULT "nand0=" MTD_NAME + +/* + * U-Boot Commands + */ +#include +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_MMC +#define CONFIG_CMD_NAND +#define CONFIG_CMD_MTDPARTS +#define CONFIG_CMD_BOOTCE +#define CONFIG_CMD_TIME + +/* + * Serial Driver + */ +#define CONFIG_PL011_SERIAL +#define CONFIG_PL011_CLOCK 24000000 +#define CONFIG_PL01x_PORTS { \ + (void *)MXS_UARTDBG_BASE, \ + } +#define CONFIG_CONS_INDEX 0 /* do not change! */ +#define CONFIG_BAUDRATE 115200 /* Default baud rate */ +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, } +#define CONFIG_SYS_CONSOLE_INFO_QUIET + +/* + * Ethernet Driver + */ +#define CONFIG_FEC_MXC +#ifdef CONFIG_FEC_MXC +/* This is required for the FEC driver to work with cache enabled */ +#define CONFIG_SYS_ARM_CACHE_WRITETHROUGH + +#ifndef CONFIG_TX28_S +#define CONFIG_FEC_MXC_MULTI +#else +#define IMX_FEC_BASE MXS_ENET0_BASE +#define CONFIG_FEC_MXC_PHYADDR 0x00 +#endif + +#define CONFIG_MII +#define CONFIG_FEC_XCV_TYPE RMII +#define CONFIG_GET_FEC_MAC_ADDR_FROM_IIM +#define CONFIG_NET_MULTI +#define CONFIG_CMD_MII +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_PING +/* Add for working with "strict" DHCP server */ +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_DNS +#endif + +/* + * NAND flash driver + */ +#ifdef CONFIG_CMD_NAND +#define CONFIG_MTD_DEVICE +#define CONFIG_ENV_IS_IN_NAND +#define CONFIG_NAND_MXS +#define CONFIG_APBH_DMA +#define CONFIG_APBH_DMA_BURST +#define CONFIG_APBH_DMA_BURST8 +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x20000 +#define CONFIG_CMD_NAND_TRIMFFS +#define CONFIG_SYS_MXS_DMA_CHANNEL 4 +#define CONFIG_SYS_MAX_FLASH_SECT 1024 +#define CONFIG_SYS_MAX_FLASH_BANKS 1 +#define CONFIG_SYS_NAND_MAX_CHIPS 1 +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_USE_FLASH_BBT +#ifdef CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_OVERWRITE +#define CONFIG_ENV_OFFSET (CONFIG_U_BOOT_IMG_SIZE + CONFIG_SYS_NAND_U_BOOT_OFFS) +#define CONFIG_ENV_SIZE SZ_128K +#define CONFIG_ENV_RANGE 0x60000 +#endif /* CONFIG_ENV_IS_IN_NAND */ +#define CONFIG_SYS_NAND_BASE 0x00000000 +#define CONFIG_CMD_ROMUPDATE +#endif /* CONFIG_CMD_NAND */ + +/* + * MMC Driver + */ +#ifdef CONFIG_CMD_MMC +#ifndef CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_IS_IN_MMC +#endif +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_MXS_MMC ++#define CONFIG_BOUNCE_BUFFER + +#define CONFIG_DOS_PARTITION +#define CONFIG_CMD_FAT +#define CONFIG_CMD_EXT2 + +/* + * Environments on MMC + */ +#ifdef CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_ENV_OVERWRITE +/* Associated with the MMC layout defined in mmcops.c */ +#define CONFIG_ENV_OFFSET SZ_1K +#define CONFIG_ENV_SIZE (SZ_128K - CONFIG_ENV_OFFSET) +#define CONFIG_DYNAMIC_MMC_DEVNO +#endif /* CONFIG_ENV_IS_IN_MMC */ +#endif /* CONFIG_CMD_MMC */ + +#ifdef CONFIG_ENV_OFFSET_REDUND +#define MTDPARTS_DEFAULT "mtdparts=" MTD_NAME ":" \ + "1m@" xstr(CONFIG_SYS_NAND_U_BOOT_OFFS) "(u-boot)," \ + xstr(CONFIG_ENV_RANGE) \ + "(env)," \ + xstr(CONFIG_ENV_RANGE) \ + "(env2),4m(linux),16m(rootfs),256k(dtb),-(userfs)" +#else +#define MTDPARTS_DEFAULT "mtdparts=" MTD_NAME ":" \ + "1m@" xstr(CONFIG_SYS_NAND_U_BOOT_OFFS) "(u-boot)," \ + xstr(CONFIG_ENV_RANGE) \ + "(env),4m(linux),16m(rootfs),256k(dtb),-(userfs)" +#endif + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \ + GENERATED_GBL_DATA_SIZE) + +/* Defines for SPL */ +#define CONFIG_SPL +#define CONFIG_SPL_NO_CPU_SUPPORT_CODE - #define CONFIG_SPL_START_S_PATH "arch/arm/cpu/arm926ejs/mx28" - #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/arm926ejs/mx28/u-boot-spl.lds" ++#define CONFIG_SPL_START_S_PATH "arch/arm/cpu/arm926ejs/mxs" ++#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds" +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_GPIO_SUPPORT +#define CONFIG_SYS_SPL_VDDD_VAL 1500 +#define CONFIG_SYS_SPL_BATT_BO_LEVEL 2800 ++#define CONFIG_SYS_SPL_VDDMEM_VAL 0 /* VDDMEM is not utilized on TX28 */ + - #endif /* __CONFIG_H */ ++#endif /* __CONFIGS_TX28_H */ diff --cc include/configs/tx48.h index 96df26c671,0000000000..515cc503b0 mode 100644,000000..100644 --- a/include/configs/tx48.h +++ b/include/configs/tx48.h @@@ -1,347 -1,0 +1,357 @@@ +/* + * tx48.h + * + * Copyright (C) 2012 Lothar Waßmann + * + * based on: am335x_evm + * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + - #ifndef __TX48_H - #define __TX48_H ++#ifndef __CONFIGS_TX48_H ++#define __CONFIGS_TX48_H + - #include +#include + +/* + * Ka-Ro TX48 board - SoC configuration + */ +#define CONFIG_AM33XX +#define CONFIG_AM33XX_GPIO +#define CONFIG_SYS_HZ 1000 /* Ticks per second */ + +#ifndef CONFIG_SPL_BUILD +#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_SHOW_ACTIVITY +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO +#define CONFIG_BOARD_LATE_INIT + +/* LCD Logo and Splash screen support */ +#define CONFIG_LCD +#ifdef CONFIG_LCD +#define CONFIG_SPLASH_SCREEN +#define CONFIG_SPLASH_SCREEN_ALIGN +#define CONFIG_VIDEO_DA8XX +#define DAVINCI_LCD_CNTL_BASE 0x4830e000 +#define CONFIG_LCD_LOGO +#define LCD_BPP LCD_COLOR24 +#define CONFIG_CMD_BMP +#define CONFIG_VIDEO_BMP_RLE8 +#endif /* CONFIG_LCD */ +#endif /* CONFIG_SPL_BUILD */ + +/* Clock Defines */ +#define V_OSCK 24000000 /* Clock output from T2 */ +#define V_SCLK V_OSCK + +/* + * Memory configuration options + */ +#define CONFIG_SYS_SDRAM_DDR3 +#define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of SDRAM */ +#define PHYS_SDRAM_1 0x80000000 /* SDRAM Bank #1 */ +#define CONFIG_MAX_RAM_BANK_SIZE SZ_1G + +#define CONFIG_STACKSIZE SZ_64K +#define CONFIG_SYS_MALLOC_LEN SZ_4M + +#define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1 + SZ_64M) +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + SZ_8M) ++#define CONFIG_SYS_SDRAM_CLK 266 ++ ++#define CONFIG_SYS_CACHELINE_SIZE 64 + +/* + * U-Boot general configurations + */ +#define CONFIG_SYS_LONGHELP +#define CONFIG_SYS_PROMPT "TX48 U-Boot > " +#define CONFIG_SYS_CBSIZE 2048 /* Console I/O buffer size */ +#define CONFIG_SYS_PBSIZE \ + (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) + /* Print buffer size */ +#define CONFIG_SYS_MAXARGS 64 /* Max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + /* Boot argument buffer size */ +#define CONFIG_VERSION_VARIABLE /* U-BOOT version */ +#define CONFIG_AUTO_COMPLETE /* Command auto complete */ +#define CONFIG_CMDLINE_EDITING /* Command history etc */ + +#define CONFIG_SYS_64BIT_VSPRINTF +#define CONFIG_SYS_NO_FLASH + +/* + * Flattened Device Tree (FDT) support +*/ +#ifdef CONFIG_OF_LIBFDT /* set via cmdline parameter thru boards.cfg */ +#define CONFIG_FDT_FIXUP_PARTITIONS +#define CONFIG_OF_EMBED +#define CONFIG_OF_BOARD_SETUP +#define CONFIG_DEFAULT_DEVICE_TREE tx48 +#define CONFIG_ARCH_DEVICE_TREE am33xx +#define CONFIG_MACH_TYPE (-1) ++#define CONFIG_SYS_FDT_ADDR (PHYS_SDRAM_1 + SZ_16M) +#else +#ifndef MACH_TYPE_TIAM335EVM +#define MACH_TYPE_TIAM335EVM 3589 /* Until the next sync */ +#endif +#define CONFIG_MACH_TYPE MACH_TYPE_TIAM335EVM +#endif + +/* + * Boot Linux + */ +#define xstr(s) str(s) +#define str(s) #s +#define __pfx(x, s) (x##s) +#define _pfx(x, s) __pfx(x, s) + +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_BOOTDELAY 3 +#define CONFIG_ZERO_BOOTDELAY_CHECK +#define CONFIG_SYS_AUTOLOAD "no" +#define CONFIG_BOOTFILE "uImage" +#define CONFIG_BOOTARGS "console=ttyO0,115200 ro debug panic=1" +#define CONFIG_BOOTCOMMAND "run bootcmd_nand" +#define CONFIG_LOADADDR 83000000 +#define CONFIG_SYS_LOAD_ADDR _pfx(0x, CONFIG_LOADADDR) +#define CONFIG_U_BOOT_IMG_SIZE SZ_1M ++#if 0 +#define CONFIG_HW_WATCHDOG ++#endif + +/* + * Extra Environments + */ +#ifdef CONFIG_OF_LIBFDT +#define TX48_BOOTM_CMD \ + "bootm_cmd=fdt boardsetup;bootm ${loadaddr} - ${fdtaddr}\0" +#define TX48_MTDPARTS_CMD "" +#else +#define TX48_BOOTM_CMD \ + "bootm_cmd=bootm\0" +#define TX48_MTDPARTS_CMD "${mtdparts} " +#endif + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "autostart=no\0" \ + "baseboard=stk5-v3\0" \ + "bootargs_mmc=run default_bootargs;set bootargs ${bootargs}" \ + " root=/dev/mmcblk0p2 rootwait\0" \ + "bootargs_nand=run default_bootargs;set bootargs ${bootargs}" \ + " root=/dev/mtdblock4 rootfstype=jffs2\0" \ + "nfsroot=/tftpboot/rootfs\0" \ + "bootargs_nfs=run default_bootargs;set bootargs ${bootargs}" \ + " root=/dev/nfs ip=dhcp nfsroot=${serverip}:${nfsroot},nolock\0"\ + "bootcmd_mmc=set autostart no;run bootargs_mmc;" \ + " fatload mmc 0 ${loadaddr} uImage;run bootm_cmd\0" \ + "bootcmd_nand=set autostart no;run bootargs_nand;" \ + " nboot linux;run bootm_cmd\0" \ + "bootcmd_net=set autostart no;run bootargs_nfs;dhcp;" \ + " run bootm_cmd\0" \ + TX48_BOOTM_CMD \ + "default_bootargs=set bootargs " CONFIG_BOOTARGS \ + TX48_MTDPARTS_CMD \ + " video=${video_mode} ${append_bootargs}\0" \ + "cpu_clk=400\0" \ + "fdtaddr=81000000\0" \ + "mtdids=" MTDIDS_DEFAULT "\0" \ + "mtdparts=" MTDPARTS_DEFAULT "\0" \ + "otg_mode=device\0" \ + "touchpanel=tsc2007\0" \ + "video_mode=640x480MR-24@60\0" + +#define MTD_NAME "omap2-nand.0" +#define MTDIDS_DEFAULT "nand0=" MTD_NAME + +/* + * U-Boot Commands + */ +#include +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_MMC +#define CONFIG_CMD_NAND +#define CONFIG_CMD_MTDPARTS +#define CONFIG_CMD_BOOTCE +#define CONFIG_CMD_TIME + +/* + * Serial Driver + */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_MEM32 +#define CONFIG_SYS_NS16550_REG_SIZE (-4) +#define CONFIG_SYS_NS16550_CLK 48000000 +#define CONFIG_SYS_NS16550_COM1 0x44e09000 /* UART0 */ +#define CONFIG_SYS_NS16550_COM2 0x48022000 /* UART1 */ +#define CONFIG_SYS_NS16550_COM6 0x481aa000 /* UART5 */ + +#define CONFIG_SYS_NS16550_COM3 0x481aa000 /* UART2 */ +#define CONFIG_SYS_NS16550_COM4 0x481aa000 /* UART3 */ +#define CONFIG_SYS_NS16550_COM5 0x481aa000 /* UART4 */ +#define CONFIG_CONS_INDEX 1 /* one based! */ +#define CONFIG_BAUDRATE 115200 /* Default baud rate */ +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, } +#define CONFIG_SYS_CONSOLE_INFO_QUIET + +/* + * Ethernet Driver + */ +#ifdef CONFIG_CMD_NET +#define CONFIG_DRIVER_TI_CPSW +#define CONFIG_NET_MULTI +#define CONFIG_PHY_GIGE ++#define CONFIG_PHY_SMSC ++#define CONFIG_PHYLIB ++#define CONFIG_PHY_ADDR (-1) +#define CONFIG_MII +#define CONFIG_CMD_MII +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_PING +/* Add for working with "strict" DHCP server */ +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_DNS +#define CONFIG_BOOTP_DNS2 +#endif + +/* + * NAND flash driver + */ +#ifdef CONFIG_CMD_NAND +#define CONFIG_MTD_DEVICE +#define CONFIG_ENV_IS_IN_NAND +#define CONFIG_NAND_AM33XX +#define GPMC_NAND_ECC_LP_x8_LAYOUT +#define GPMC_NAND_HW_ECC_LAYOUT_KERNEL GPMC_NAND_HW_ECC_LAYOUT +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x20000 +#define CONFIG_SYS_NAND_PAGE_SIZE 2048 +#define CONFIG_SYS_NAND_OOBSIZE 64 +#define CONFIG_SYS_NAND_ECCSIZE 512 +#define CONFIG_SYS_NAND_ECCBYTES 14 +#define CONFIG_CMD_NAND_TRIMFFS +#define CONFIG_SYS_NAND_MAX_CHIPS 1 +#define CONFIG_SYS_NAND_MAXBAD 20 /* Max. number of bad blocks guaranteed by manufacturer */ +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_USE_FLASH_BBT +#ifdef CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_OVERWRITE +#define CONFIG_ENV_OFFSET (CONFIG_U_BOOT_IMG_SIZE + CONFIG_SYS_NAND_U_BOOT_OFFS) +#define CONFIG_ENV_SIZE SZ_128K +#define CONFIG_ENV_RANGE 0x60000 +#endif /* CONFIG_ENV_IS_IN_NAND */ +#define CONFIG_SYS_NAND_BASE 0x08000000 /* must be defined but value is irrelevant */ +#define NAND_BASE CONFIG_SYS_NAND_BASE +#endif /* CONFIG_CMD_NAND */ + +/* + * MMC Driver + */ +#ifdef CONFIG_CMD_MMC +#ifndef CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_IS_IN_MMC +#endif +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_OMAP_HSMMC +#define CONFIG_OMAP_MMC_DEV_1 + +#define CONFIG_DOS_PARTITION +#define CONFIG_CMD_FAT +#define CONFIG_CMD_EXT2 + +/* + * Environments on MMC + */ +#ifdef CONFIG_ENV_IS_IN_MMC - #define CONFIG_SYS_MMC_ENV_DEV 0 ++#define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_ENV_OVERWRITE +/* Associated with the MMC layout defined in mmcops.c */ +#define CONFIG_ENV_OFFSET SZ_1K +#define CONFIG_ENV_SIZE (SZ_128K - CONFIG_ENV_OFFSET) +#define CONFIG_DYNAMIC_MMC_DEVNO +#endif /* CONFIG_ENV_IS_IN_MMC */ +#endif /* CONFIG_CMD_MMC */ + +#ifdef CONFIG_ENV_OFFSET_REDUND +#define MTDPARTS_DEFAULT "mtdparts=" MTD_NAME ":" \ + "128k(u-boot-spl)," \ + "1m(u-boot)," \ + xstr(CONFIG_ENV_RANGE) \ + "(env)," \ + xstr(CONFIG_ENV_RANGE) \ + "(env2),4m(linux),16m(rootfs),256k(dtb),-(userfs)" +#else +#define MTDPARTS_DEFAULT "mtdparts=" MTD_NAME ":" \ + "128k(u-boot-spl)," \ + "1m(u-boot)," \ + xstr(CONFIG_ENV_RANGE) \ + "(env),4m(linux),16m(rootfs),256k(dtb),-(userfs)" +#endif + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define SRAM0_SIZE SZ_64K +#define CONFIG_SYS_INIT_SP_ADDR 0x4030B7FC +#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR + + /* Platform/Board specific defs */ +#define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */ +#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ + +/* Defines for SPL */ +#define CONFIG_SPL ++#define CONFIG_SPL_FRAMEWORK +#define CONFIG_SPL_BOARD_INIT +#define CONFIG_SPL_MAX_SIZE (46 * SZ_1K) +#define CONFIG_SPL_GPIO_SUPPORT - #ifdef CONFIG_NAND_AM33XX ++#ifdef CONFIG_NAND_OMAP_GPMC ++#define CONFIG_SPL_NAND_AM33XX_BCH +#define CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SPL_NAND_SIMPLE +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \ + CONFIG_SYS_NAND_PAGE_SIZE) +#define CONFIG_SYS_NAND_BLOCK_SIZE SZ_128K +#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS +#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ + 10, 11, 12, 13, 14, 15, 16, 17, \ + 18, 19, 20, 21, 22, 23, 24, 25, \ + 26, 27, 28, 29, 30, 31, 32, 33, \ + 34, 35, 36, 37, 38, 39, 40, 41, \ + 42, 43, 44, 45, 46, 47, 48, 49, \ + 50, 51, 52, 53, 54, 55, 56, 57, } +#endif + +#define CONFIG_SPL_BSS_START_ADDR PHYS_SDRAM_1 +#define CONFIG_SPL_BSS_MAX_SIZE SZ_512K + +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ + +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_YMODEM_SUPPORT +#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" + +/* + * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM + * 64 bytes before this address should be set aside for u-boot.img's + * header. That is 0x800FFFC0--0x80100000 should not be used for any + * other needs. + */ +#define CONFIG_SYS_SPL_MALLOC_START (PHYS_SDRAM_1 + SZ_2M + SZ_32K) +#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_1M + - #endif /* __TX48_H */ ++#endif /* __CONFIGS_TX48_H */ diff --cc include/configs/tx51.h index 7282109c68,0000000000..bdb252df16 mode 100644,000000..100644 --- a/include/configs/tx51.h +++ b/include/configs/tx51.h @@@ -1,294 -1,0 +1,295 @@@ +/* + * Copyright (C) 2012 + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ - #ifndef __TX51_H - #define __TX51_H ++#ifndef __CONFIGS_TX51_H ++#define __CONFIGS_TX51_H + - #include +#include + +/* + * Ka-Ro TX51 board - SoC configuration + */ +#define CONFIG_MX51 /* i.MX51 SoC */ +#define CONFIG_SYS_MX5_IOMUX_V3 +#define CONFIG_MXC_GPIO /* GPIO control */ - #define CONFIG_SYS_MX5_HCLK 24000000 - #define CONFIG_SYS_MX5_CLK32 32768 - #define CONFIG_SYS_DDR_CLKSEL 0 - #define CONFIG_SYS_HZ 1000 /* Ticks per second */ ++#define CONFIG_SYS_MX5_HCLK 24000000 ++#define CONFIG_SYS_MX5_CLK32 32768 ++#define CONFIG_SYS_DDR_CLKSEL 0 ++#define CONFIG_SYS_HZ 1000 /* Ticks per second */ +#define CONFIG_SHOW_ACTIVITY +#define CONFIG_DISPLAY_BOARDINFO +#define CONFIG_BOARD_LATE_INIT +#define CONFIG_BOARD_EARLY_INIT_F + +#if CONFIG_SYS_CPU_CLK == 600 - #define TX51_MOD_PREFIX "6" ++#define TX51_MOD_PREFIX "6" +#elif CONFIG_SYS_CPU_CLK == 800 - #define TX51_MOD_PREFIX "8" ++#define TX51_MOD_PREFIX "8" +#define CONFIG_MX51_PLL_ERRATA +#else +#error Invalid CPU clock +#endif + +/* LCD Logo and Splash screen support */ +#define CONFIG_LCD +#ifdef CONFIG_LCD +#define CONFIG_SPLASH_SCREEN +#define CONFIG_SPLASH_SCREEN_ALIGN - #define CONFIG_VIDEO_MX5 ++#define CONFIG_VIDEO_IPUV3 ++#define CONFIG_IPUV3_CLK 200000000 +#define CONFIG_LCD_LOGO +#define LCD_BPP LCD_COLOR24 +#define CONFIG_CMD_BMP +#define CONFIG_VIDEO_BMP_RLE8 +#endif /* CONFIG_LCD */ + +/* + * Memory configurations + */ - #define PHYS_SDRAM_1 0x90000000 /* Base address of bank 1 */ - #define PHYS_SDRAM_1_SIZE SZ_128M ++#define PHYS_SDRAM_1 0x90000000 /* Base address of bank 1 */ ++#define PHYS_SDRAM_1_SIZE SZ_128M +#if CONFIG_NR_DRAM_BANKS > 1 - #define PHYS_SDRAM_2 0x98000000 /* Base address of bank 2 */ - #define PHYS_SDRAM_2_SIZE SZ_128M ++#define PHYS_SDRAM_2 0x98000000 /* Base address of bank 2 */ ++#define PHYS_SDRAM_2_SIZE SZ_128M +#else - #define TX51_MOD_SUFFIX "0" ++#define TX51_MOD_SUFFIX "0" +#endif - #define CONFIG_STACKSIZE SZ_128K - #define CONFIG_SYS_MALLOC_LEN SZ_8M - #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1 /* Memtest start address */ - #define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + SZ_4M) /* 4 MB RAM test */ ++#define CONFIG_STACKSIZE SZ_128K ++#define CONFIG_SYS_MALLOC_LEN SZ_8M ++#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1 /* Memtest start address */ ++#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + SZ_4M) /* 4 MB RAM test */ +#if CONFIG_SYS_SDRAM_CLK == 200 - #define CONFIG_SYS_CLKTL_CBCDR 0x59e35180 - #define TX51_MOD_SUFFIX "1" ++#define CONFIG_SYS_CLKTL_CBCDR 0x59e35180 ++#define TX51_MOD_SUFFIX "1" +#elif CONFIG_SYS_SDRAM_CLK == 166 - #define CONFIG_SYS_CLKTL_CBCDR 0x01e35180 ++#define CONFIG_SYS_CLKTL_CBCDR 0x01e35180 +#ifndef TX51_MOD_SUFFIX - #define TX51_MOD_SUFFIX "2" ++#define TX51_MOD_SUFFIX "2" +#endif +#else +#error Invalid SDRAM clock +#endif + +/* + * U-Boot general configurations + */ +#define CONFIG_SYS_LONGHELP - #define CONFIG_SYS_PROMPT "TX51 U-Boot > " - #define CONFIG_SYS_CBSIZE 2048 /* Console I/O buffer size */ ++#define CONFIG_SYS_PROMPT "TX51 U-Boot > " ++#define CONFIG_SYS_CBSIZE 2048 /* Console I/O buffer size */ +#define CONFIG_SYS_PBSIZE \ + (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) + /* Print buffer size */ - #define CONFIG_SYS_MAXARGS 64 /* Max number of command args */ - #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE ++#define CONFIG_SYS_MAXARGS 64 /* Max number of command args */ ++#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + /* Boot argument buffer size */ +#define CONFIG_VERSION_VARIABLE /* U-BOOT version */ +#define CONFIG_AUTO_COMPLETE /* Command auto complete */ +#define CONFIG_CMDLINE_EDITING /* Command history etc */ + +#define CONFIG_SYS_64BIT_VSPRINTF +#define CONFIG_SYS_NO_FLASH + +/* + * Flattened Device Tree (FDT) support +*/ +#define CONFIG_OF_LIBFDT +#define CONFIG_OF_EMBED +#define CONFIG_OF_BOARD_SETUP +#define CONFIG_DEFAULT_DEVICE_TREE tx51 +#define CONFIG_ARCH_DEVICE_TREE mx51 ++#define CONFIG_SYS_FDT_ADDR (PHYS_SDRAM_1 + SZ_16M) + +/* + * Boot Linux + */ - #define xstr(s) str(s) - #define str(s) #s - #define __pfx(x, s) (x##s) - #define _pfx(x, s) __pfx(x, s) ++#define xstr(s) str(s) ++#define str(s) #s ++#define __pfx(x, s) (x##s) ++#define _pfx(x, s) __pfx(x, s) + +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS - #define CONFIG_BOOTDELAY 3 ++#define CONFIG_BOOTDELAY 3 +#define CONFIG_ZERO_BOOTDELAY_CHECK - #define CONFIG_SYS_AUTOLOAD "no" - #define CONFIG_BOOTFILE "uImage" - #define CONFIG_BOOTARGS "console=ttymxc0,115200 ro debug panic=1" - #define CONFIG_BOOTCOMMAND "run bootcmd_nand" - #define CONFIG_LOADADDR 94000000 - #define CONFIG_SYS_LOAD_ADDR _pfx(0x, CONFIG_LOADADDR) - #define CONFIG_U_BOOT_IMG_SIZE SZ_1M ++#define CONFIG_SYS_AUTOLOAD "no" ++#define CONFIG_BOOTFILE "uImage" ++#define CONFIG_BOOTARGS "console=ttymxc0,115200 ro debug panic=1" ++#define CONFIG_BOOTCOMMAND "run bootcmd_nand" ++#define CONFIG_LOADADDR 94000000 ++#define CONFIG_SYS_LOAD_ADDR _pfx(0x, CONFIG_LOADADDR) ++#define CONFIG_U_BOOT_IMG_SIZE SZ_1M +#define CONFIG_HW_WATCHDOG + +/* + * Extra Environments + */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "autostart=no\0" \ + "baseboard=stk5-v3\0" \ + "bootargs_mmc=run default_bootargs;set bootargs ${bootargs}" \ + " root=/dev/mmcblk0p3 rootwait\0" \ + "bootargs_nand=run default_bootargs;set bootargs ${bootargs}" \ + " root=/dev/mtdblock3 rootfstype=jffs2\0" \ + "nfsroot=/tftpboot/rootfs\0" \ + "bootargs_nfs=run default_bootargs;set bootargs ${bootargs}" \ + " root=/dev/nfs ip=dhcp nfsroot=${serverip}:${nfsroot},nolock\0"\ + "bootcmd_mmc=set autostart no;run bootargs_mmc;" \ + "mmc read ${loadaddr} 100 3000;run bootm_cmd\0" \ + "bootcmd_nand=set autostart no;run bootargs_nand;" \ + "nboot linux;run bootm_cmd\0" \ + "bootcmd_net=set autostart no;run bootargs_nfs;dhcp;" \ + "run bootm_cmd\0" \ + "bootm_cmd=fdt boardsetup;bootm ${loadaddr} - ${fdtaddr}\0" \ + "default_bootargs=set bootargs " CONFIG_BOOTARGS \ + " video=${video_mode} ${append_bootargs}\0" \ + "cpu_clk=" xstr(CONFIG_SYS_CPU_CLK) "\0" \ + "fdtaddr=91000000\0" \ + "mtdids=" MTDIDS_DEFAULT "\0" \ + "mtdparts=" MTDPARTS_DEFAULT "\0" \ + "otg_mode=device\0" \ + "touchpanel=tsc2007\0" \ + "video_mode=VGA-1:640x480MR-24@60\0" + +#define MTD_NAME "mxc_nand" +#define MTDIDS_DEFAULT "nand0=" MTD_NAME +#define CONFIG_FDT_FIXUP_PARTITIONS + +/* + * U-Boot Commands + */ +#include +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_IIM +#define CONFIG_CMD_MMC +#define CONFIG_CMD_NAND +#define CONFIG_CMD_MTDPARTS +#define CONFIG_CMD_BOOTCE +#define CONFIG_CMD_TIME + +/* + * Serial Driver + */ +#define CONFIG_MXC_UART +#define CONFIG_MXC_UART_BASE UART1_BASE ++#define CONFIG_MXC_GPIO +#define CONFIG_BAUDRATE 115200 /* Default baud rate */ +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, } +#define CONFIG_SYS_CONSOLE_INFO_QUIET + +/* + * Ethernet Driver + */ +#define CONFIG_FEC_MXC +#ifdef CONFIG_FEC_MXC +#define IMX_FEC_BASE FEC_BASE_ADDR +#define CONFIG_FEC_MXC_PHYADDR 0x1f +#define CONFIG_PHYLIB +#define CONFIG_PHY_SMSC +#define CONFIG_MII +#define CONFIG_FEC_XCV_TYPE MII100 +#define CONFIG_GET_FEC_MAC_ADDR_FROM_IIM +#define CONFIG_CMD_MII +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_PING +/* Add for working with "strict" DHCP server */ +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_DNS +#endif + +/* + * NAND flash driver + */ +#ifdef CONFIG_CMD_NAND +#define CONFIG_MTD_DEVICE +#define CONFIG_ENV_IS_IN_NAND +#define CONFIG_NAND_MXC +#define CONFIG_MXC_NAND_REGS_BASE 0xcfff0000 +#define CONFIG_MXC_NAND_IP_BASE 0x83fdb000 +#define CONFIG_MXC_NAND_HWECC +#define CONFIG_CMD_NAND_TRIMFFS +#define CONFIG_SYS_MAX_FLASH_SECT 1024 +#define CONFIG_SYS_MAX_FLASH_BANKS 1 +#define CONFIG_SYS_NAND_MAX_CHIPS 1 +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_USE_FLASH_BBT +#ifdef CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_OVERWRITE +#define CONFIG_ENV_OFFSET CONFIG_U_BOOT_IMG_SIZE +#define CONFIG_ENV_SIZE 0x20000 /* 128 KiB */ +#define CONFIG_ENV_RANGE 0x60000 +#endif +#ifndef CONFIG_SYS_NO_FLASH +#define CONFIG_CMD_FLASH +#define CONFIG_SYS_NAND_BASE 0xa0000000 +#define CONFIG_FIT +#else +#define CONFIG_SYS_NAND_BASE 0x00000000 +#define CONFIG_CMD_ROMUPDATE +#endif +#endif /* CONFIG_CMD_NAND */ + +/* + * MMC Driver + */ +#ifdef CONFIG_CMD_MMC +#ifndef CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_IS_IN_MMC +#endif +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_FSL_ESDHC +#define CONFIG_SYS_FSL_ESDHC_USE_PIO +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define CONFIG_SYS_FSL_ESDHC_NUM 2 + - #define CONFIG_BOOT_PARTITION_ACCESS +#define CONFIG_DOS_PARTITION +#define CONFIG_CMD_FAT +#define CONFIG_CMD_EXT2 + +/* + * Environments on MMC + */ +#ifdef CONFIG_ENV_IS_IN_MMC - #define CONFIG_SYS_MMC_ENV_DEV 0 ++#define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_ENV_OVERWRITE +/* Associated with the MMC layout defined in mmcops.c */ +#define CONFIG_ENV_OFFSET SZ_1K +#define CONFIG_ENV_SIZE (SZ_128K - CONFIG_ENV_OFFSET) +#define CONFIG_DYNAMIC_MMC_DEVNO +#endif /* CONFIG_ENV_IS_IN_MMC */ +#endif /* CONFIG_CMD_MMC */ + +#ifdef CONFIG_ENV_OFFSET_REDUND +#define MTDPARTS_DEFAULT "mtdparts=" MTD_NAME ":" \ + "1m(u-boot)," \ + xstr(CONFIG_ENV_RANGE) \ + "(env)," \ + xstr(CONFIG_ENV_RANGE) \ + "(env2),4m(linux),16m(rootfs),256k(dtb),-(userfs)" +#else +#define MTDPARTS_DEFAULT "mtdparts=" MTD_NAME ":" \ + "1m(u-boot)," \ + xstr(CONFIG_ENV_RANGE) \ + "(env),4m(linux),16m(rootfs),256k(dtb),-(userfs)" +#endif + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \ + GENERATED_GBL_DATA_SIZE) + +#ifdef CONFIG_CMD_IIM +#define CONFIG_IMX_IIM +#endif + - #endif /* __CONFIG_H */ ++#endif /* __CONFIGS_TX51_H */ diff --cc include/configs/tx53.h index ff607c1107,0000000000..73f8972a2c mode 100644,000000..100644 --- a/include/configs/tx53.h +++ b/include/configs/tx53.h @@@ -1,277 -1,0 +1,278 @@@ +/* + * Copyright (C) 2012 + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ - #ifndef __TX53_H - #define __TX53_H ++#ifndef __CONFIGS_TX53_H ++#define __CONFIGS_TX53_H + - #include +#include + +/* + * Ka-Ro TX53 board - SoC configuration + */ +#define CONFIG_TX53 /* TX53 SoM */ +#define CONFIG_MX53 /* i.MX53 SoC */ +#define CONFIG_SYS_MX5_IOMUX_V3 +#define CONFIG_MXC_GPIO /* GPIO control */ - #define CONFIG_SYS_MX5_HCLK 24000000 - #define CONFIG_SYS_MX5_CLK32 32768 - #define CONFIG_SYS_DDR_CLKSEL 0 - #define CONFIG_SYS_HZ 1000 /* Ticks per second */ ++#define CONFIG_SYS_MX5_HCLK 24000000 ++#define CONFIG_SYS_MX5_CLK32 32768 ++#define CONFIG_SYS_DDR_CLKSEL 0 ++#define CONFIG_SYS_HZ 1000 /* Ticks per second */ +#define CONFIG_SHOW_ACTIVITY +#define CONFIG_DISPLAY_BOARDINFO +#define CONFIG_BOARD_LATE_INIT +#define CONFIG_BOARD_EARLY_INIT_F + +/* LCD Logo and Splash screen support */ +#define CONFIG_LCD +#ifdef CONFIG_LCD +#define CONFIG_SPLASH_SCREEN +#define CONFIG_SPLASH_SCREEN_ALIGN - #define CONFIG_VIDEO_MX5 ++#define CONFIG_VIDEO_IPUV3 ++#define CONFIG_IPUV3_CLK 200000000 +#define CONFIG_LCD_LOGO - #define LCD_BPP LCD_COLOR24 ++#define LCD_BPP LCD_COLOR24 +#define CONFIG_CMD_BMP +#define CONFIG_VIDEO_BMP_RLE8 +#endif /* CONFIG_LCD */ + +/* + * Memory configurations + */ - #define PHYS_SDRAM_1 0x70000000 /* Base address of bank 1 */ - #define PHYS_SDRAM_1_SIZE SZ_512M ++#define PHYS_SDRAM_1 0x70000000 /* Base address of bank 1 */ ++#define PHYS_SDRAM_1_SIZE SZ_512M +#if CONFIG_NR_DRAM_BANKS > 1 - #define PHYS_SDRAM_2 0xb0000000 /* Base address of bank 2 */ - #define PHYS_SDRAM_2_SIZE SZ_512M - #define TX53_MOD_SUFFIX "1" ++#define PHYS_SDRAM_2 0xb0000000 /* Base address of bank 2 */ ++#define PHYS_SDRAM_2_SIZE SZ_512M ++#define TX53_MOD_SUFFIX "1" +#else - #define TX53_MOD_SUFFIX "0" ++#define TX53_MOD_SUFFIX "0" +#endif - #define CONFIG_STACKSIZE SZ_128K - #define CONFIG_SYS_MALLOC_LEN SZ_8M - #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1 /* Memtest start address */ - #define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + SZ_4M) /* 4 MB RAM test */ - #define CONFIG_SYS_SDRAM_CLK 400 ++#define CONFIG_STACKSIZE SZ_128K ++#define CONFIG_SYS_MALLOC_LEN SZ_8M ++#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1 /* Memtest start address */ ++#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + SZ_4M) /* 4 MB RAM test */ ++#define CONFIG_SYS_SDRAM_CLK 400 + +/* + * U-Boot general configurations + */ +#define CONFIG_SYS_LONGHELP - #define CONFIG_SYS_PROMPT "TX53 U-Boot > " - #define CONFIG_SYS_CBSIZE 2048 /* Console I/O buffer size */ ++#define CONFIG_SYS_PROMPT "TX53 U-Boot > " ++#define CONFIG_SYS_CBSIZE 2048 /* Console I/O buffer size */ +#define CONFIG_SYS_PBSIZE \ + (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) + /* Print buffer size */ - #define CONFIG_SYS_MAXARGS 64 /* Max number of command args */ - #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE ++#define CONFIG_SYS_MAXARGS 64 /* Max number of command args */ ++#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + /* Boot argument buffer size */ +#define CONFIG_VERSION_VARIABLE /* U-BOOT version */ +#define CONFIG_AUTO_COMPLETE /* Command auto complete */ +#define CONFIG_CMDLINE_EDITING /* Command history etc */ + +#define CONFIG_SYS_64BIT_VSPRINTF +#define CONFIG_SYS_NO_FLASH + +/* + * Flattened Device Tree (FDT) support +*/ +#define CONFIG_OF_LIBFDT +#define CONFIG_OF_EMBED +#define CONFIG_OF_BOARD_SETUP +#define CONFIG_DEFAULT_DEVICE_TREE tx53 +#define CONFIG_ARCH_DEVICE_TREE mx53 +#define CONFIG_SYS_FDT_ADDR (PHYS_SDRAM_1 + SZ_16M) + +/* + * Boot Linux + */ - #define xstr(s) str(s) - #define str(s) #s - #define __pfx(x, s) (x##s) - #define _pfx(x, s) __pfx(x, s) ++#define xstr(s) str(s) ++#define str(s) #s ++#define __pfx(x, s) (x##s) ++#define _pfx(x, s) __pfx(x, s) + +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS - #define CONFIG_BOOTDELAY 3 ++#define CONFIG_BOOTDELAY 3 +#define CONFIG_ZERO_BOOTDELAY_CHECK - #define CONFIG_SYS_AUTOLOAD "no" - #define CONFIG_BOOTFILE "uImage" - #define CONFIG_BOOTARGS "console=ttymxc0,115200 ro debug panic=1" - #define CONFIG_BOOTCOMMAND "run bootcmd_nand" - #define CONFIG_LOADADDR 78000000 - #define CONFIG_SYS_LOAD_ADDR _pfx(0x, CONFIG_LOADADDR) - #define CONFIG_U_BOOT_IMG_SIZE SZ_1M ++#define CONFIG_SYS_AUTOLOAD "no" ++#define CONFIG_BOOTFILE "uImage" ++#define CONFIG_BOOTARGS "console=ttymxc0,115200 ro debug panic=1" ++#define CONFIG_BOOTCOMMAND "run bootcmd_nand" ++#define CONFIG_LOADADDR 78000000 ++#define CONFIG_SYS_LOAD_ADDR _pfx(0x, CONFIG_LOADADDR) ++#define CONFIG_U_BOOT_IMG_SIZE SZ_1M +#define CONFIG_HW_WATCHDOG + +/* + * Extra Environments + */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "autostart=no\0" \ + "baseboard=stk5-v3\0" \ + "bootargs_mmc=run default_bootargs;set bootargs ${bootargs}" \ + " root=/dev/mmcblk0p3 rootwait\0" \ + "bootargs_nand=run default_bootargs;set bootargs ${bootargs}" \ - " ${mtdparts} root=/dev/mtdblock3 rootfstype=jffs2\0" \ ++ " root=/dev/mtdblock3 rootfstype=jffs2\0" \ + "nfsroot=/tftpboot/rootfs\0" \ + "bootargs_nfs=run default_bootargs;set bootargs ${bootargs}" \ + " root=/dev/nfs ip=dhcp nfsroot=${serverip}:${nfsroot},nolock\0"\ + "bootcmd_mmc=set autostart no;run bootargs_mmc;" \ + "mmc read ${loadaddr} 100 3000;run bootm_cmd\0" \ + "bootcmd_nand=set autostart no;run bootargs_nand;" \ + "nboot linux;run bootm_cmd\0" \ + "bootcmd_net=set autostart no;run bootargs_nfs;dhcp;" \ + "run bootm_cmd\0" \ + "bootm_cmd=fdt boardsetup;bootm ${loadaddr} - ${fdtaddr}\0" \ + "default_bootargs=set bootargs " CONFIG_BOOTARGS \ + " video=${video_mode} ${append_bootargs}\0" \ + "cpu_clk=800\0" \ ++ "fdtaddr=71000000\0" \ + "mtdids=" MTDIDS_DEFAULT "\0" \ + "mtdparts=" MTDPARTS_DEFAULT "\0" \ + "otg_mode=device\0" \ + "touchpanel=tsc2007\0" \ + "video_mode=VGA-1:640x480MR-24@60\0" + +#define MTD_NAME "mxc_nand" +#define MTDIDS_DEFAULT "nand0=" MTD_NAME +#define CONFIG_FDT_FIXUP_PARTITIONS + +/* + * U-Boot Commands + */ +#include +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_IIM +#define CONFIG_CMD_MMC +#define CONFIG_CMD_NAND +#define CONFIG_CMD_MTDPARTS +#define CONFIG_CMD_BOOTCE +#define CONFIG_CMD_TIME + +/* + * Serial Driver + */ +#define CONFIG_MXC_UART +#define CONFIG_MXC_UART_BASE UART1_BASE +#define CONFIG_MXC_GPIO +#define CONFIG_BAUDRATE 115200 /* Default baud rate */ +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, } +#define CONFIG_SYS_CONSOLE_INFO_QUIET + +/* + * Ethernet Driver + */ +#define CONFIG_FEC_MXC +#ifdef CONFIG_FEC_MXC +#define IMX_FEC_BASE FEC_BASE_ADDR +#define CONFIG_FEC_MXC_PHYADDR 0 +#define CONFIG_PHYLIB +#define CONFIG_PHY_SMSC +#define CONFIG_MII +#define CONFIG_FEC_XCV_TYPE MII100 +#define CONFIG_GET_FEC_MAC_ADDR_FROM_IIM +#define CONFIG_CMD_MII +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_PING +/* Add for working with "strict" DHCP server */ +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_DNS +#endif + +/* + * NAND flash driver + */ +#ifdef CONFIG_CMD_NAND +#define CONFIG_MTD_DEVICE +#define CONFIG_ENV_IS_IN_NAND +#define CONFIG_NAND_MXC +#define CONFIG_MXC_NAND_REGS_BASE 0xf7ff0000 +#define CONFIG_MXC_NAND_IP_BASE 0x63fdb000 +#define CONFIG_MXC_NAND_HWECC +#define CONFIG_CMD_NAND_TRIMFFS +#define CONFIG_SYS_MAX_FLASH_SECT 1024 +#define CONFIG_SYS_MAX_FLASH_BANKS 1 +#define CONFIG_SYS_NAND_MAX_CHIPS 1 +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_USE_FLASH_BBT +#ifdef CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_OVERWRITE +#define CONFIG_ENV_OFFSET CONFIG_U_BOOT_IMG_SIZE +#define CONFIG_ENV_SIZE 0x20000 /* 128 KiB */ +#define CONFIG_ENV_RANGE 0x60000 +#endif +#ifndef CONFIG_SYS_NO_FLASH +#define CONFIG_CMD_FLASH +#define CONFIG_SYS_NAND_BASE 0xa0000000 +#define CONFIG_FIT +#else +#define CONFIG_SYS_NAND_BASE 0x00000000 +#define CONFIG_CMD_ROMUPDATE +#endif +#endif /* CONFIG_CMD_NAND */ + +/* + * MMC Driver + */ +#ifdef CONFIG_CMD_MMC +#ifndef CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_IS_IN_MMC +#endif +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_FSL_ESDHC +#define CONFIG_SYS_FSL_ESDHC_USE_PIO +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define CONFIG_SYS_FSL_ESDHC_NUM 2 + +#define CONFIG_DOS_PARTITION +#define CONFIG_CMD_FAT +#define CONFIG_CMD_EXT2 + +/* + * Environments on MMC + */ +#ifdef CONFIG_ENV_IS_IN_MMC - #define CONFIG_SYS_MMC_ENV_DEV 0 ++#define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_ENV_OVERWRITE +/* Associated with the MMC layout defined in mmcops.c */ +#define CONFIG_ENV_OFFSET SZ_1K +#define CONFIG_ENV_SIZE (SZ_128K - CONFIG_ENV_OFFSET) +#define CONFIG_DYNAMIC_MMC_DEVNO +#endif /* CONFIG_ENV_IS_IN_MMC */ +#endif /* CONFIG_CMD_MMC */ + +#ifdef CONFIG_ENV_OFFSET_REDUND +#define MTDPARTS_DEFAULT "mtdparts=" MTD_NAME ":" \ + "1m(u-boot)," \ + xstr(CONFIG_ENV_RANGE) \ + "(env)," \ + xstr(CONFIG_ENV_RANGE) \ + "(env2),4m(linux),16m(rootfs),256k(dtb),-(userfs)" +#else +#define MTDPARTS_DEFAULT "mtdparts=" MTD_NAME ":" \ + "1m(u-boot)," \ + xstr(CONFIG_ENV_RANGE) \ + "(env),4m(linux),16m(rootfs),256k(dtb),-(userfs)" +#endif + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \ + GENERATED_GBL_DATA_SIZE) + +#ifdef CONFIG_CMD_IIM +#define CONFIG_IMX_IIM +#endif + - #endif /* __CONFIG_H */ ++#endif /* __CONFIGS_TX53_H */ diff --cc include/configs/tx6q.h index 0000000000,0000000000..1e0c6bed35 new file mode 100644 --- /dev/null +++ b/include/configs/tx6q.h @@@ -1,0 -1,0 +1,306 @@@ ++/* ++ * Copyright (C) 2012 ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation version 2. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++#ifndef __TX6Q_H ++#define __TX6Q_H ++ ++#include ++ ++/* ++ * Ka-Ro TX6Q board - SoC configuration ++ */ ++#define CONFIG_MX6Q ++#define CONFIG_SYS_MX6_HCLK 24000000 ++#define CONFIG_SYS_MX6_CLK32 32768 ++#define CONFIG_SYS_HZ 1000 /* Ticks per second */ ++#define CONFIG_SHOW_ACTIVITY ++#define CONFIG_ARCH_CPU_INIT ++#define CONFIG_DISPLAY_BOARDINFO ++#define CONFIG_BOARD_LATE_INIT ++#define CONFIG_BOARD_EARLY_INIT_F ++#if 0 ++#define CONFIG_NETCONSOLE ++#endif ++ ++/* LCD Logo and Splash screen support */ ++#if 1 ++#define CONFIG_LCD ++#endif ++#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE ++#ifdef CONFIG_LCD ++#define CONFIG_SPLASH_SCREEN ++#define CONFIG_SPLASH_SCREEN_ALIGN ++#define CONFIG_VIDEO_IPUV3 ++#define CONFIG_IPU_CLKRATE 266000000 ++#define CONFIG_LCD_LOGO ++#define LCD_BPP LCD_COLOR24 ++#define CONFIG_CMD_BMP ++#define CONFIG_VIDEO_BMP_RLE8 ++#endif /* CONFIG_LCD */ ++ ++/* ++ * Memory configuration options ++ */ ++#define CONFIG_NR_DRAM_BANKS 1 /* # of SDRAM banks */ ++#define PHYS_SDRAM_1 0x10000000 /* Base address of bank 1 */ ++#define PHYS_SDRAM_1_SIZE SZ_1G ++#define CONFIG_STACKSIZE SZ_128K ++#define CONFIG_SYS_MALLOC_LEN SZ_8M ++#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1 /* Memtest start address */ ++#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + SZ_4M) ++#define CONFIG_SYS_SDRAM_CLK 528 ++ ++/* ++ * U-Boot general configurations ++ */ ++#define CONFIG_SYS_LONGHELP ++#define CONFIG_SYS_PROMPT "TX6Q U-Boot > " ++#define CONFIG_SYS_CBSIZE 2048 /* Console I/O buffer size */ ++#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ ++ sizeof(CONFIG_SYS_PROMPT) + 16) /* Print buffer size */ ++#define CONFIG_SYS_MAXARGS 64 /* Max number of command args */ ++#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE ++ /* Boot argument buffer size */ ++#define CONFIG_VERSION_VARIABLE /* U-BOOT version */ ++#define CONFIG_AUTO_COMPLETE /* Command auto complete */ ++#define CONFIG_CMDLINE_EDITING /* Command history etc */ ++ ++#define CONFIG_SYS_64BIT_VSPRINTF ++#define CONFIG_SYS_NO_FLASH ++ ++/* ++ * Flattened Device Tree (FDT) support ++*/ ++#define CONFIG_OF_LIBFDT ++#ifdef CONFIG_OF_LIBFDT ++#define CONFIG_FDT_FIXUP_PARTITIONS ++#define CONFIG_OF_EMBED ++#define CONFIG_OF_BOARD_SETUP ++#define CONFIG_DEFAULT_DEVICE_TREE tx6q ++#define CONFIG_ARCH_DEVICE_TREE mx6q ++#define CONFIG_SYS_FDT_ADDR (PHYS_SDRAM_1 + SZ_16M) ++#endif ++ ++/* ++ * Boot Linux ++ */ ++#define xstr(s) str(s) ++#define str(s) #s ++#define __pfx(x, s) (x##s) ++#define _pfx(x, s) __pfx(x, s) ++ ++#define CONFIG_CMDLINE_TAG ++#define CONFIG_SETUP_MEMORY_TAGS ++#define CONFIG_BOOTDELAY 1 ++#define CONFIG_ZERO_BOOTDELAY_CHECK ++#define CONFIG_SYS_AUTOLOAD "no" ++#define CONFIG_BOOTFILE "uImage" ++#define CONFIG_BOOTARGS "console=ttymxc0,115200 ro debug panic=1" ++#define CONFIG_BOOTCOMMAND "run bootcmd_nand" ++#define CONFIG_LOADADDR 18000000 ++#define CONFIG_SYS_LOAD_ADDR _pfx(0x, CONFIG_LOADADDR) ++#define CONFIG_U_BOOT_IMG_SIZE SZ_1M ++#define CONFIG_IMX_WATCHDOG ++#define CONFIG_WATCHDOG_TIMEOUT_MSECS 3000 ++ ++/* ++ * Extra Environments ++ */ ++#define CONFIG_EXTRA_ENV_SETTINGS \ ++ "autostart=no\0" \ ++ "baseboard=stk5-v3\0" \ ++ "bootargs_mmc=run default_bootargs;set bootargs ${bootargs}" \ ++ " root=/dev/mmcblk0p3 rootwait\0" \ ++ "bootargs_nand=run default_bootargs;set bootargs ${bootargs}" \ ++ " root=/dev/mtdblock3 rootfstype=jffs2\0" \ ++ "bootargs_nfs=run default_bootargs;set bootargs ${bootargs}" \ ++ " root=/dev/nfs ip=dhcp nfsroot=${serverip}:${nfsroot},nolock\0"\ ++ "bootcmd_mmc=set autostart no;run bootargs_mmc;" \ ++ "fatload mmc 0 ${loadaddr} uImage;run bootm_cmd\0" \ ++ "bootcmd_nand=set autostart no;run bootargs_nand;" \ ++ "nboot linux;run bootm_cmd\0" \ ++ "bootcmd_net=set autostart no;run bootargs_nfs;dhcp;" \ ++ "run bootm_cmd\0" \ ++ "bootdelay=-1\0" \ ++ "bootm_cmd=fdt boardsetup;bootm ${loadaddr} - ${fdtaddr}\0" \ ++ "cpu_clk=800\0" \ ++ "default_bootargs=set bootargs " CONFIG_BOOTARGS \ ++ " video=${video_mode} ${append_bootargs}\0" \ ++ "fdtaddr=11000000\0" \ ++ "mtdids=" MTDIDS_DEFAULT "\0" \ ++ "mtdparts=" MTDPARTS_DEFAULT "\0" \ ++ "nfsroot=/tftpboot/rootfs\0" \ ++ "otg_mode=device\0" \ ++ "touchpanel=tsc2007\0" \ ++ "video_mode=VGA-1:640x480MR-24@60\0" ++ ++#define MTD_NAME "gpmi-nand" ++#define MTDIDS_DEFAULT "nand0=" MTD_NAME ++ ++/* ++ * U-Boot Commands ++ */ ++#include ++#define CONFIG_CMD_CACHE ++#define CONFIG_CMD_MMC ++#define CONFIG_CMD_NAND ++#define CONFIG_CMD_MTDPARTS ++#if 1 ++#define CONFIG_CMD_BOOTCE ++#endif ++#define CONFIG_CMD_TIME ++#define CONFIG_CMD_I2C ++ ++/* ++ * Serial Driver ++ */ ++#define CONFIG_MXC_UART ++#define CONFIG_MXC_UART_BASE UART1_BASE ++#define CONFIG_BAUDRATE 115200 /* Default baud rate */ ++#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, } ++#define CONFIG_SYS_CONSOLE_INFO_QUIET ++ ++/* ++ * GPIO driver ++ */ ++#define CONFIG_MXC_GPIO ++ ++/* ++ * Ethernet Driver ++ */ ++#define CONFIG_FEC_MXC ++#ifdef CONFIG_FEC_MXC ++/* This is required for the FEC driver to work with cache enabled */ ++#define CONFIG_SYS_ARM_CACHE_WRITETHROUGH ++ ++#define IMX_FEC_BASE ENET_BASE_ADDR ++#define CONFIG_FEC_MXC_PHYADDR 0 ++#define CONFIG_PHYLIB ++#define CONFIG_PHY_SMSC ++#define CONFIG_MII ++#define CONFIG_FEC_XCV_TYPE RMII ++#define CONFIG_GET_FEC_MAC_ADDR_FROM_IIM ++#define CONFIG_CMD_MII ++#define CONFIG_CMD_DHCP ++#define CONFIG_CMD_PING ++/* Add for working with "strict" DHCP server */ ++#define CONFIG_BOOTP_SUBNETMASK ++#define CONFIG_BOOTP_GATEWAY ++#define CONFIG_BOOTP_DNS ++#endif ++ ++/* ++ * I2C Configs ++ */ ++#ifdef CONFIG_CMD_I2C ++#define CONFIG_HARD_I2C 1 ++#define CONFIG_I2C_MXC 1 ++#define CONFIG_SYS_I2C_BASE I2C1_BASE_ADDR ++#define CONFIG_SYS_I2C_MX6_PORT1 ++#define CONFIG_SYS_I2C_SPEED 10000 ++#define CONFIG_SYS_I2C_SLAVE 0x3c ++#define CONFIG_MX6_INTER_LDO_BYPASS 0 ++#endif ++ ++/* ++ * NAND flash driver ++ */ ++#ifdef CONFIG_CMD_NAND ++#define CONFIG_MTD_DEVICE ++#if 0 ++#define CONFIG_MTD_DEBUG ++#define CONFIG_MTD_DEBUG_VERBOSE 4 ++#endif ++#define CONFIG_ENV_IS_IN_NAND ++#define CONFIG_NAND_MXS ++#define CONFIG_NAND_PAGE_SIZE 2048 ++#define CONFIG_NAND_OOB_SIZE 64 ++#define CONFIG_NAND_PAGES_PER_BLOCK 64 ++#define CONFIG_APBH_DMA ++#define CONFIG_APBH_DMA_BURST ++#define CONFIG_APBH_DMA_BURST8 ++#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x20000 ++#define CONFIG_CMD_NAND_TRIMFFS ++#define CONFIG_SYS_MXS_DMA_CHANNEL 4 ++#define CONFIG_SYS_MAX_FLASH_SECT 1024 ++#define CONFIG_SYS_MAX_FLASH_BANKS 1 ++#define CONFIG_SYS_NAND_MAX_CHIPS 1 ++#define CONFIG_SYS_MAX_NAND_DEVICE 1 ++#define CONFIG_SYS_NAND_5_ADDR_CYCLE ++#define CONFIG_SYS_NAND_USE_FLASH_BBT ++#ifdef CONFIG_ENV_IS_IN_NAND ++#define CONFIG_ENV_OVERWRITE ++#define CONFIG_ENV_OFFSET (CONFIG_U_BOOT_IMG_SIZE + CONFIG_SYS_NAND_U_BOOT_OFFS) ++#define CONFIG_ENV_SIZE SZ_128K ++#define CONFIG_ENV_RANGE 0x60000 ++#endif ++#define CONFIG_SYS_NAND_BASE 0x00000000 ++#define CONFIG_CMD_ROMUPDATE ++#endif /* CONFIG_CMD_NAND */ ++ ++/* ++ * MMC Driver ++ */ ++#ifdef CONFIG_CMD_MMC ++#ifndef CONFIG_ENV_IS_IN_NAND ++#define CONFIG_ENV_IS_IN_MMC ++#endif ++#define CONFIG_MMC ++#define CONFIG_GENERIC_MMC ++#define CONFIG_FSL_ESDHC ++#define CONFIG_FSL_USDHC ++#if 0 ++#define CONFIG_SYS_FSL_ESDHC_USE_PIO ++#endif ++#define CONFIG_SYS_FSL_ESDHC_ADDR 0 ++#define CONFIG_SYS_FSL_ESDHC_NUM 2 ++ ++#define CONFIG_DOS_PARTITION ++#define CONFIG_CMD_FAT ++#define CONFIG_CMD_EXT2 ++ ++/* ++ * Environments on MMC ++ */ ++#ifdef CONFIG_ENV_IS_IN_MMC ++#define CONFIG_SYS_MMC_ENV_DEV 0 ++#define CONFIG_ENV_OVERWRITE ++/* Associated with the MMC layout defined in mmcops.c */ ++#define CONFIG_ENV_OFFSET SZ_1K ++#define CONFIG_ENV_SIZE (SZ_128K - CONFIG_ENV_OFFSET) ++#define CONFIG_DYNAMIC_MMC_DEVNO ++#endif /* CONFIG_ENV_IS_IN_MMC */ ++#endif /* CONFIG_CMD_MMC */ ++ ++#ifdef CONFIG_ENV_OFFSET_REDUND ++#define MTDPARTS_DEFAULT "mtdparts=" MTD_NAME ":" \ ++ "1m@" xstr(CONFIG_SYS_NAND_U_BOOT_OFFS) "(u-boot)," \ ++ xstr(CONFIG_ENV_RANGE) \ ++ "(env)," \ ++ xstr(CONFIG_ENV_RANGE) \ ++ "(env2),4m(linux),16m(rootfs),256k(dtb),-(userfs)" ++#else ++#define MTDPARTS_DEFAULT "mtdparts=" MTD_NAME ":" \ ++ "1m@" xstr(CONFIG_SYS_NAND_U_BOOT_OFFS) "(u-boot)," \ ++ xstr(CONFIG_ENV_RANGE) \ ++ "(env),4m(linux),16m(rootfs),256k(dtb),-(userfs)" ++#endif ++ ++#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 ++#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \ ++ GENERATED_GBL_DATA_SIZE) ++ ++#ifdef CONFIG_CMD_IIM ++#define CONFIG_IMX_IIM ++#endif ++ ++#endif /* __CONFIG_H */ diff --cc include/fsl_esdhc.h index 86320a16a5,47d2fe4f18..efb48c97a7 --- a/include/fsl_esdhc.h +++ b/include/fsl_esdhc.h @@@ -165,10 -166,8 +167,10 @@@ #define ESDHC_HOSTCAPBLT_HSS 0x00200000 struct fsl_esdhc_cfg { - u32 esdhc_base; + void __iomem *esdhc_base; - u32 no_snoop; + u32 sdhc_clk; + int cd_gpio; + int wp_gpio; }; /* Select the correct accessors depending on endianess */ diff --cc include/ipu.h index 99a2491cf5,99a2491cf5..1391a24bf4 --- a/include/ipu.h +++ b/include/ipu.h @@@ -4,9 -4,9 +4,9 @@@ * (C) Copyright 2010 * Stefano Babic, DENX Software Engineering, sbabic@denx.de * -- * Linux IPU driver for MX51: ++ * Linux IPU driver: * -- * (C) Copyright 2005-2010 Freescale Semiconductor, Inc. ++ * (C) Copyright 2005-2011 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@@ -31,57 -31,57 +31,14 @@@ #define __ASM_ARCH_IPU_H__ #include --#include ++#include ++#include ++ ++struct clk; #define IDMA_CHAN_INVALID 0xFF #define HIGH_RESOLUTION_WIDTH 1024 --struct clk { -- const char *name; -- int id; -- /* Source clock this clk depends on */ -- struct clk *parent; -- /* Secondary clock to enable/disable with this clock */ -- struct clk *secondary; -- /* Current clock rate */ -- unsigned long rate; -- /* Reference count of clock enable/disable */ -- __s8 usecount; -- /* Register bit position for clock's enable/disable control. */ -- u8 enable_shift; -- /* Register address for clock's enable/disable control. */ -- void *enable_reg; -- u32 flags; -- /* -- * Function ptr to recalculate the clock's rate based on parent -- * clock's rate -- */ -- void (*recalc) (struct clk *); -- /* -- * Function ptr to set the clock to a new rate. The rate must match a -- * supported rate returned from round_rate. Leave blank if clock is not -- * programmable -- */ -- int (*set_rate) (struct clk *, unsigned long); -- /* -- * Function ptr to round the requested clock rate to the nearest -- * supported rate that is less than or equal to the requested rate. -- */ -- unsigned long (*round_rate) (struct clk *, unsigned long); -- /* -- * Function ptr to enable the clock. Leave blank if clock can not -- * be gated. -- */ -- int (*enable) (struct clk *); -- /* -- * Function ptr to disable the clock. Leave blank if clock can not -- * be gated. -- */ -- void (*disable) (struct clk *); -- /* Function ptr to set the parent clock of the clock. */ -- int (*set_parent) (struct clk *, struct clk *); --}; -- /* * Enumeration of Synchronous (Memory-less) panel types */ @@@ -90,6 -90,6 +47,51 @@@ typedef enum IPU_PANEL_TFT, } ipu_panel_t; ++/* IPU Pixel format definitions */ ++#define fourcc(a, b, c, d)\ ++ (((__u32)(a)<<0)|((__u32)(b)<<8)|((__u32)(c)<<16)|((__u32)(d)<<24)) ++ ++/* ++ * Pixel formats are defined with ASCII FOURCC code. The pixel format codes are ++ * the same used by V4L2 API. ++ */ ++ ++#define IPU_PIX_FMT_GENERIC fourcc('I', 'P', 'U', '0') ++#define IPU_PIX_FMT_GENERIC_32 fourcc('I', 'P', 'U', '1') ++#define IPU_PIX_FMT_LVDS666 fourcc('L', 'V', 'D', '6') ++#define IPU_PIX_FMT_LVDS888 fourcc('L', 'V', 'D', '8') ++ ++#define IPU_PIX_FMT_RGB332 fourcc('R', 'G', 'B', '1') /*< 8 RGB-3-3-2 */ ++#define IPU_PIX_FMT_RGB555 fourcc('R', 'G', 'B', 'O') /*< 16 RGB-5-5-5 */ ++#define IPU_PIX_FMT_RGB565 fourcc('R', 'G', 'B', 'P') /*< 1 6 RGB-5-6-5 */ ++#define IPU_PIX_FMT_RGB666 fourcc('R', 'G', 'B', '6') /*< 18 RGB-6-6-6 */ ++#define IPU_PIX_FMT_BGR666 fourcc('B', 'G', 'R', '6') /*< 18 BGR-6-6-6 */ ++#define IPU_PIX_FMT_BGR24 fourcc('B', 'G', 'R', '3') /*< 24 BGR-8-8-8 */ ++#define IPU_PIX_FMT_RGB24 fourcc('R', 'G', 'B', '3') /*< 24 RGB-8-8-8 */ ++#define IPU_PIX_FMT_BGR32 fourcc('B', 'G', 'R', '4') /*< 32 BGR-8-8-8-8 */ ++#define IPU_PIX_FMT_BGRA32 fourcc('B', 'G', 'R', 'A') /*< 32 BGR-8-8-8-8 */ ++#define IPU_PIX_FMT_RGB32 fourcc('R', 'G', 'B', '4') /*< 32 RGB-8-8-8-8 */ ++#define IPU_PIX_FMT_RGBA32 fourcc('R', 'G', 'B', 'A') /*< 32 RGB-8-8-8-8 */ ++#define IPU_PIX_FMT_ABGR32 fourcc('A', 'B', 'G', 'R') /*< 32 ABGR-8-8-8-8 */ ++ ++/* YUV Interleaved Formats */ ++#define IPU_PIX_FMT_YUYV fourcc('Y', 'U', 'Y', 'V') /*< 16 YUV 4:2:2 */ ++#define IPU_PIX_FMT_UYVY fourcc('U', 'Y', 'V', 'Y') /*< 16 YUV 4:2:2 */ ++#define IPU_PIX_FMT_Y41P fourcc('Y', '4', '1', 'P') /*< 12 YUV 4:1:1 */ ++#define IPU_PIX_FMT_YUV444 fourcc('Y', '4', '4', '4') /*< 24 YUV 4:4:4 */ ++ ++/* two planes -- one Y, one Cb + Cr interleaved */ ++#define IPU_PIX_FMT_NV12 fourcc('N', 'V', '1', '2') /* 12 Y/CbCr 4:2:0 */ ++ ++#define IPU_PIX_FMT_GREY fourcc('G', 'R', 'E', 'Y') /*< 8 Greyscale */ ++#define IPU_PIX_FMT_YVU410P fourcc('Y', 'V', 'U', '9') /*< 9 YVU 4:1:0 */ ++#define IPU_PIX_FMT_YUV410P fourcc('Y', 'U', 'V', '9') /*< 9 YUV 4:1:0 */ ++#define IPU_PIX_FMT_YVU420P fourcc('Y', 'V', '1', '2') /*< 12 YVU 4:2:0 */ ++#define IPU_PIX_FMT_YUV420P fourcc('I', '4', '2', '0') /*< 12 YUV 4:2:0 */ ++#define IPU_PIX_FMT_YUV420P2 fourcc('Y', 'U', '1', '2') /*< 12 YUV 4:2:0 */ ++#define IPU_PIX_FMT_YVU422P fourcc('Y', 'V', '1', '6') /*< 16 YVU 4:2:2 */ ++#define IPU_PIX_FMT_YUV422P fourcc('4', '2', '2', 'P') /*< 16 YUV 4:2:2 */ ++ /* * IPU Driver channels definitions. * Note these are different from IDMA channels @@@ -135,14 -135,14 +137,25 @@@ typedef enum * Enumeration of types of buffers for a logical channel. */ typedef enum { -- IPU_OUTPUT_BUFFER = 0, /*< Buffer for output from IPU */ -- IPU_ALPHA_IN_BUFFER = 1, /*< Buffer for input to IPU */ -- IPU_GRAPH_IN_BUFFER = 2, /*< Buffer for input to IPU */ -- IPU_VIDEO_IN_BUFFER = 3, /*< Buffer for input to IPU */ ++ IPU_OUTPUT_BUFFER = 0, /* Buffer for output from IPU */ ++ IPU_ALPHA_IN_BUFFER = 1, /* Buffer for input to IPU */ ++ IPU_GRAPH_IN_BUFFER = 2, /* Buffer for input to IPU */ ++ IPU_VIDEO_IN_BUFFER = 3, /* Buffer for input to IPU */ IPU_INPUT_BUFFER = IPU_VIDEO_IN_BUFFER, IPU_SEC_INPUT_BUFFER = IPU_GRAPH_IN_BUFFER, } ipu_buffer_t; ++ ++/* ++ * Enumeration of version of IPU V3 . ++ */ ++typedef enum { ++ IPUV3_HW_REV_IPUV3DEX = 2, /* IPUv3D, IPUv3E IPUv3EX */ ++ IPUV3_HW_REV_IPUV3M = 3, /* IPUv3M */ ++ IPUV3_HW_REV_IPUV3H = 4, /* IPUv3H */ ++} ipu3_hw_rev_t; ++ ++ #define IPU_PANEL_SERIAL 1 #define IPU_PANEL_PARALLEL 2 @@@ -214,7 -214,7 +227,18 @@@ typedef enum YUV } ipu_color_space_t; ++typedef enum { ++ DI_PCLK_PLL3, ++ DI_PCLK_LDB, ++ DI_PCLK_TVE ++} ipu_di_clk_parent_t; ++ /* Common IPU API */ ++int ipuv3_fb_init(struct fb_videomode *mode, int di, ++ unsigned int interface_pix_fmt, ++ ipu_di_clk_parent_t di_clk_parent, ++ unsigned long di_clk_val, int bpp); ++ int32_t ipu_init_channel(ipu_channel_t channel, ipu_channel_params_t *params); void ipu_uninit_channel(ipu_channel_t channel); @@@ -250,7 -250,7 +274,7 @@@ int32_t ipu_disp_set_color_key(ipu_chan uint32_t bytes_per_pixel(uint32_t fmt); --void clk_enable(struct clk *clk); ++int clk_enable(struct clk *clk); void clk_disable(struct clk *clk); u32 clk_get_rate(struct clk *clk); int clk_set_rate(struct clk *clk, unsigned long rate); @@@ -260,7 -260,7 +284,7 @@@ int clk_get_usecount(struct clk *clk) struct clk *clk_get_parent(struct clk *clk); void ipu_dump_registers(void); --int ipu_probe(void); ++int ipu_probe(int di, ipu_di_clk_parent_t di_clk_parent, int di_clk_val); void ipu_dmfc_init(int dmfc_type, int first); void ipu_init_dc_mappings(void); diff --cc include/ipu_pixfmt.h index 5ffc98d861,1163bf4b4e..0000000000 deleted file mode 100644,100644 --- a/include/ipu_pixfmt.h +++ /dev/null @@@ -1,81 -1,84 +1,0 @@@ --/* -- * (C) Copyright 2011 -- * Stefano Babic, DENX Software Engineering, sbabic@denx.de -- * -- * Based on Linux IPU driver for MX51 (ipu.h): -- * -- * (C) Copyright 2005-2010 Freescale Semiconductor, Inc. -- * -- * See file CREDITS for list of people who contributed to this -- * project. -- * -- * This program is free software; you can redistribute it and/or -- * modify it under the terms of the GNU General Public License as -- * published by the Free Software Foundation; either version 2 of -- * the License, or (at your option) any later version. -- * -- * This program is distributed in the hope that it will be useful, -- * but WITHOUT ANY WARRANTY; without even the implied warranty of -- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- * GNU General Public License for more details. -- * -- * You should have received a copy of the GNU General Public License -- * along with this program; if not, write to the Free Software -- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, -- * MA 02111-1307 USA -- */ -- --#ifndef __IPU_PIXFMT_H__ --#define __IPU_PIXFMT_H__ -- --#include --#include -- --/* IPU Pixel format definitions */ --#define fourcc(a, b, c, d)\ -- (((__u32)(a)<<0)|((__u32)(b)<<8)|((__u32)(c)<<16)|((__u32)(d)<<24)) -- --/* -- * Pixel formats are defined with ASCII FOURCC code. The pixel format codes are -- * the same used by V4L2 API. -- */ -- --#define IPU_PIX_FMT_GENERIC fourcc('I', 'P', 'U', '0') --#define IPU_PIX_FMT_GENERIC_32 fourcc('I', 'P', 'U', '1') --#define IPU_PIX_FMT_LVDS666 fourcc('L', 'V', 'D', '6') --#define IPU_PIX_FMT_LVDS888 fourcc('L', 'V', 'D', '8') -- --#define IPU_PIX_FMT_RGB332 fourcc('R', 'G', 'B', '1') /*< 8 RGB-3-3-2 */ --#define IPU_PIX_FMT_RGB555 fourcc('R', 'G', 'B', 'O') /*< 16 RGB-5-5-5 */ --#define IPU_PIX_FMT_RGB565 fourcc('R', 'G', 'B', 'P') /*< 1 6 RGB-5-6-5 */ --#define IPU_PIX_FMT_RGB666 fourcc('R', 'G', 'B', '6') /*< 18 RGB-6-6-6 */ --#define IPU_PIX_FMT_BGR666 fourcc('B', 'G', 'R', '6') /*< 18 BGR-6-6-6 */ --#define IPU_PIX_FMT_BGR24 fourcc('B', 'G', 'R', '3') /*< 24 BGR-8-8-8 */ --#define IPU_PIX_FMT_RGB24 fourcc('R', 'G', 'B', '3') /*< 24 RGB-8-8-8 */ --#define IPU_PIX_FMT_BGR32 fourcc('B', 'G', 'R', '4') /*< 32 BGR-8-8-8-8 */ --#define IPU_PIX_FMT_BGRA32 fourcc('B', 'G', 'R', 'A') /*< 32 BGR-8-8-8-8 */ --#define IPU_PIX_FMT_RGB32 fourcc('R', 'G', 'B', '4') /*< 32 RGB-8-8-8-8 */ --#define IPU_PIX_FMT_RGBA32 fourcc('R', 'G', 'B', 'A') /*< 32 RGB-8-8-8-8 */ --#define IPU_PIX_FMT_ABGR32 fourcc('A', 'B', 'G', 'R') /*< 32 ABGR-8-8-8-8 */ -- --/* YUV Interleaved Formats */ --#define IPU_PIX_FMT_YUYV fourcc('Y', 'U', 'Y', 'V') /*< 16 YUV 4:2:2 */ --#define IPU_PIX_FMT_UYVY fourcc('U', 'Y', 'V', 'Y') /*< 16 YUV 4:2:2 */ --#define IPU_PIX_FMT_Y41P fourcc('Y', '4', '1', 'P') /*< 12 YUV 4:1:1 */ --#define IPU_PIX_FMT_YUV444 fourcc('Y', '4', '4', '4') /*< 24 YUV 4:4:4 */ -- --/* two planes -- one Y, one Cb + Cr interleaved */ --#define IPU_PIX_FMT_NV12 fourcc('N', 'V', '1', '2') /* 12 Y/CbCr 4:2:0 */ -- --#define IPU_PIX_FMT_GREY fourcc('G', 'R', 'E', 'Y') /*< 8 Greyscale */ --#define IPU_PIX_FMT_YVU410P fourcc('Y', 'V', 'U', '9') /*< 9 YVU 4:1:0 */ --#define IPU_PIX_FMT_YUV410P fourcc('Y', 'U', 'V', '9') /*< 9 YUV 4:1:0 */ --#define IPU_PIX_FMT_YVU420P fourcc('Y', 'V', '1', '2') /*< 12 YVU 4:2:0 */ --#define IPU_PIX_FMT_YUV420P fourcc('I', '4', '2', '0') /*< 12 YUV 4:2:0 */ --#define IPU_PIX_FMT_YUV420P2 fourcc('Y', 'U', '1', '2') /*< 12 YUV 4:2:0 */ --#define IPU_PIX_FMT_YVU422P fourcc('Y', 'V', '1', '6') /*< 16 YVU 4:2:2 */ --#define IPU_PIX_FMT_YUV422P fourcc('4', '2', '2', 'P') /*< 16 YUV 4:2:2 */ -- - int mx5_fb_init(struct fb_videomode *mode, uint8_t disp, uint32_t pixfmt, int bpp); -int ipuv3_fb_init(struct fb_videomode const *mode, - uint8_t disp, - uint32_t pixfmt); -void ipuv3_fb_shutdown(void); -- --#endif diff --cc include/nand.h index 2f8e5f1666,dded4e27f0..16afde1e92 --- a/include/nand.h +++ b/include/nand.h @@@ -31,12 -31,9 +31,12 @@@ * at the same time, so do it here. When all drivers are * converted, this will go away. */ - #if defined(CONFIG_NAND_FSL_ELBC) + #if defined(CONFIG_NAND_FSL_ELBC) || defined(CONFIG_NAND_ATMEL) #define CONFIG_SYS_NAND_SELF_INIT #endif +#if defined(CONFIG_NAND_MXC) +#define CONFIG_SYS_NAND_SELF_INIT +#endif extern void nand_init(void); diff --cc include/net.h index ee11f82ccc,970d4d1fab..76c6d6605a --- a/include/net.h +++ b/include/net.h @@@ -369,7 -437,7 +437,7 @@@ extern int NetRestartWrap; /* Tried a enum proto_t { BOOTP, RARP, ARP, TFTPGET, DHCP, PING, DNS, NFS, CDP, NETCONS, SNTP, - TFTPSRV, TFTPPUT - TFTPSRV, TFTPPUT, LINKLOCAL ++ TFTPSRV, TFTPPUT, LINKLOCAL, BOOTME }; /* from net/net.c */ @@@ -408,28 -491,88 +491,91 @@@ extern void NetStartAgain(void) extern int NetEthHdrSize(void); /* Set ethernet header; returns the size of the header */ - extern int NetSetEther(volatile uchar *, uchar *, uint); + extern int NetSetEther(uchar *, uchar *, uint); + extern int net_update_ether(struct ethernet_hdr *et, uchar *addr, uint prot); /* Set IP header */ - extern void NetSetIP(volatile uchar *, IPaddr_t, int, int, int); + extern void net_set_ip_header(uchar *pkt, IPaddr_t dest, IPaddr_t source); + extern void net_set_udp_header(uchar *pkt, IPaddr_t dest, int dport, + int sport, int len); /* Checksum */ - extern int NetCksumOk(uchar *, int); /* Return true if cksum OK */ - extern uint NetCksum(uchar *, int); /* Calculate the checksum */ - - /* Set callbacks */ - extern void NetSetHandler(rxhand_f *); /* Set RX packet handler */ + extern int NetCksumOk(uchar *, int); /* Return true if cksum OK */ + extern uint NetCksum(uchar *, int); /* Calculate the checksum */ + + /* Callbacks */ + extern rxhand_f *net_get_udp_handler(void); /* Get UDP RX packet handler */ + extern void net_set_udp_handler(rxhand_f *); /* Set UDP RX packet handler */ + extern rxhand_f *net_get_arp_handler(void); /* Get ARP RX packet handler */ + extern void net_set_arp_handler(rxhand_f *); /* Set ARP RX packet handler */ extern void net_set_icmp_handler(rxhand_icmp_f *f); /* Set ICMP RX handler */ - extern void NetSetTimeout(ulong, thand_f *);/* Set timeout handler */ + extern void NetSetTimeout(ulong, thand_f *);/* Set timeout handler */ + + /* Network loop state */ + enum net_loop_state { + NETLOOP_CONTINUE, + NETLOOP_RESTART, + NETLOOP_SUCCESS, + NETLOOP_FAIL + }; + extern enum net_loop_state net_state; + + static inline void net_set_state(enum net_loop_state state) + { + debug_cond(DEBUG_INT_STATE, "--- NetState set to %d\n", state); + net_state = state; + } - /* Transmit "NetTxPacket" */ - extern void NetSendPacket(volatile uchar *, int); + /* Transmit a packet */ + static inline void NetSendPacket(uchar *pkt, int len) + { + (void) eth_send(pkt, len); + } - /* Transmit UDP packet, performing ARP request if needed */ - extern int NetSendUDPPacket(uchar *ether, IPaddr_t dest, int dport, int sport, int len); + /* + * Transmit "NetTxPacket" as UDP packet, performing ARP request if needed + * (ether will be populated) + * + * @param ether Raw packet buffer + * @param dest IP address to send the datagram to + * @param dport Destination UDP port + * @param sport Source UDP port + * @param payload_len Length of data after the UDP header + */ + extern int NetSendUDPPacket(uchar *ether, IPaddr_t dest, int dport, + int sport, int payload_len); /* Processes a received packet */ - extern void NetReceive(volatile uchar *, int); + extern void NetReceive(uchar *, int); + + #ifdef CONFIG_NETCONSOLE + void NcStart(void); + int nc_input_packet(uchar *pkt, IPaddr_t src_ip, unsigned dest_port, + unsigned src_port, unsigned len); + #endif + + static inline __attribute__((always_inline)) int eth_is_on_demand_init(void) + { + #ifdef CONFIG_NETCONSOLE + extern enum proto_t net_loop_last_protocol; + + return net_loop_last_protocol != NETCONS; + #else + return 1; + #endif + } + + static inline void eth_set_last_protocol(int protocol) + { + #ifdef CONFIG_NETCONSOLE + extern enum proto_t net_loop_last_protocol; + + net_loop_last_protocol = protocol; + #endif + } ++#ifdef CONFIG_CMD_BOOTCE ++void BootmeStart(void); ++#endif /* * Check if autoload is enabled. If so, use either NFS or TFTP to download diff --cc include/netdev.h index 8a2cece245,7f158d433b..98bd6f5152 --- a/include/netdev.h +++ b/include/netdev.h @@@ -204,42 -215,6 +215,43 @@@ struct mv88e61xx_config int mv88e61xx_switch_initialize(struct mv88e61xx_config *swconfig); #endif /* CONFIG_MV88E61XX_SWITCH */ +#ifdef CONFIG_DRIVER_TI_CPSW + +enum { + CPSW_CTRL_VERSION_1 = 0, /* version1 devices */ + CPSW_CTRL_VERSION_2 /* version2 devices */ +}; + +struct cpsw_slave_data { + u32 slave_reg_ofs; + u32 sliver_reg_ofs; + int phy_id; ++ int phy_if; +}; + +struct cpsw_platform_data { + u32 mdio_base; + u32 cpsw_base; + int mdio_div; + int channels; /* number of cpdma channels (symmetric) */ + u32 cpdma_reg_ofs; /* cpdma register offset */ + int slaves; /* number of slave cpgmac ports */ + u32 ale_reg_ofs; /* address lookup engine reg offset */ + int ale_entries; /* ale table size */ + u32 host_port_reg_ofs; /* cpdma host port registers */ + u32 hw_stats_reg_ofs; /* cpsw hw stats counters */ + u32 mac_control; + struct cpsw_slave_data *slave_data; + void (*control)(int enabled); + void (*phy_init)(char *name, int addr); + u32 gigabit_en; /* gigabit capable AND enabled */ + u32 host_port_num; + u8 version; +}; + +int cpsw_register(struct cpsw_platform_data *data); + +#endif /* CONFIG_DRIVER_TI_CPSW */ /* * Allow FEC to fine-tune MII configuration on boards which require this. */ diff --cc include/wince.h index ff8d1650b5,0000000000..1efd14f1a6 mode 100644,000000..100644 --- a/include/wince.h +++ b/include/wince.h @@@ -1,426 -1,0 +1,449 @@@ +/* + * Copyright (C) 2012 Lothar Waßmann + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ +#ifndef __WINCE_H__ +#define __WINCE_H__ + - #define CE_DOFFSET (net->align_offset + ETHER_HDR_SIZE + IP_HDR_SIZE) - +/* Bin image parse results */ +#define CE_PR_EOF 0 +#define CE_PR_MORE 1 +#define CE_PR_ERROR 2 + +#pragma pack(1) + +/* Edbg BOOTME packet structures */ +typedef struct { + unsigned int id; /* Protocol identifier ("EDBG" on the wire) */ + unsigned char service; /* Service identifier */ + unsigned char flags; /* Flags (see defs below) */ + unsigned char seqNum; /* For detection of dropped packets */ + unsigned char cmd; /* For administrative messages */ + uchar data[]; /* Cmd specific data starts here (format is determined by + * Cmd, len is determined by UDP packet size) + */ +} eth_dbg_hdr; + +#define OFFSETOF(s,m) ((unsigned int)&(((s*)0)->m)) +#define EDBG_DATA_OFFSET (OFFSETOF(eth_dbg_hdr, data)) + +typedef struct { + unsigned char versionMajor; /* Bootloader version */ + unsigned char versionMinor; /* Bootloader version */ + unsigned char macAddr[6]; /* Ether address of device (net byte order) */ + unsigned int ipAddr; /* IP address of device (net byte order) */ + char platformId[17]; /* Platform Id string (NULL terminated) */ + char deviceName[17]; /* Device name string (NULL terminated). Should include + * platform and number based on Ether address + * (e.g. Odo42, CEPCLS2346, etc) + */ + unsigned char cpuId; /* CPU identifier (upper nibble = type) */ +/* The following fields were added in CE 3.0 Platform Builder release */ + unsigned char bootmeVer; /* BOOTME Version. + * Must be in the range 2 -> EDBG_CURRENT_BOOTME_VERSION, + * or remaining fields will be ignored by Eshell and defaults will be used. + */ + unsigned int bootFlags; /* Boot Flags */ + unsigned short downloadPort; /* Download Port (net byte order) (0 -> EDBG_DOWNLOAD_PORT) */ + unsigned short svcPort; /* Service Port (net byte order) (0 -> EDBG_SVC_PORT) */ +} edbg_bootme_data; + +#define BOOTME_PKT_SIZE (EDBG_DATA_OFFSET + sizeof(edbg_bootme_data)) + +// WinCE .BIN file format signature +#define CE_BIN_SIGN "B000FF\x0A" +#define CE_BIN_SIGN_LEN 7 + +typedef struct { + unsigned char sign[CE_BIN_SIGN_LEN]; + unsigned int rtiPhysAddr; + unsigned int rtiPhysLen; +} ce_bin_hdr; + +typedef struct { + unsigned int physAddr; + unsigned int physLen; + unsigned int chkSum; + unsigned char data[]; +} ce_bin_entry; + +// CE ROM image structures + +#define ROM_SIGNATURE_OFFSET 0x40 /* Offset from the image's physfirst address to the ROM signature. */ +#define ROM_SIGNATURE 0x43454345 /* Signature 'CECE' (little endian) */ +#define ROM_TOC_POINTER_OFFSET 0x44 /* Offset from the image's physfirst address to the TOC pointer. */ +#define ROM_TOC_OFFSET_OFFSET 0x48 /* Offset from the image's physfirst address to the TOC offset (from physfirst). */ + +typedef struct { + unsigned int dllfirst; /* first DLL address */ + unsigned int dlllast; /* last DLL address */ + unsigned int physfirst; /* first physical address */ + unsigned int physlast; /* highest physical address */ + unsigned int nummods; /* number of TOCentry's */ + unsigned int ramStart; /* start of RAM */ + unsigned int ramFree; /* start of RAM free space */ + unsigned int ramEnd; /* end of RAM */ + unsigned int copyEntries; /* number of copy section entries */ + unsigned int copyOffset; /* offset to copy section */ + unsigned int profileLen; /* length of PROFentries RAM */ + unsigned int profileOffset; /* offset to PROFentries */ + unsigned int numfiles; /* number of FILES */ + unsigned int kernelFlags; /* optional kernel flags from ROMFLAGS .bib config option */ + unsigned int fsRamPercent; /* Percentage of RAM used for filesystem */ +/* from FSRAMPERCENT .bib config option + * byte 0 = #4K chunks/Mbyte of RAM for filesystem 0-2Mbytes 0-255 + * byte 1 = #4K chunks/Mbyte of RAM for filesystem 2-4Mbytes 0-255 + * byte 2 = #4K chunks/Mbyte of RAM for filesystem 4-6Mbytes 0-255 + * byte 3 = #4K chunks/Mbyte of RAM for filesystem > 6Mbytes 0-255 + */ + unsigned int drivglobStart; /* device driver global starting address */ + unsigned int drivglobLen; /* device driver global length */ + unsigned short cpuType; /* CPU (machine) Type */ + unsigned short miscFlags; /* Miscellaneous flags */ + void *extensions; /* pointer to ROM Header extensions */ + unsigned int trackingStart; /* tracking memory starting address */ + unsigned int trackingLen; /* tracking memory ending address */ +} ce_rom_hdr; + +/* Win32 FILETIME strcuture */ +typedef struct { + unsigned int loDateTime; + unsigned int hiDateTime; +} ce_file_time; + +/* Table Of Contents entry structure */ +typedef struct { + unsigned int fileAttributes; + ce_file_time fileTime; + unsigned int fileSize; + char *fileName; + unsigned int e32Offset; /* Offset to E32 structure */ + unsigned int o32Offset; /* Offset to O32 structure */ + unsigned int loadOffset; /* MODULE load buffer offset */ +} ce_toc_entry; + +/* Extra information header block */ +typedef struct { + unsigned int rva; /* Virtual relative address of info */ + unsigned int size; /* Size of information block */ +} e32_info; + +#define ROM_EXTRA 9 + +typedef struct { + unsigned short e32_objcnt; /* Number of memory objects */ + unsigned short e32_imageflags; /* Image flags */ + unsigned int e32_entryrva; /* Relative virt. addr. of entry point */ + unsigned int e32_vbase; /* Virtual base address of module */ + unsigned short e32_subsysmajor;/* The subsystem major version number */ + unsigned short e32_subsysminor;/* The subsystem minor version number */ + unsigned int e32_stackmax; /* Maximum stack size */ + unsigned int e32_vsize; /* Virtual size of the entire image */ + unsigned int e32_sect14rva; /* section 14 rva */ + unsigned int e32_sect14size; /* section 14 size */ + unsigned int e32_timestamp; /* Time EXE/DLL was created/modified */ + e32_info e32_unit[ROM_EXTRA]; /* Array of extra info units */ + unsigned short e32_subsys; /* The subsystem type */ +} e32_rom; + - - +/* OS config msg */ + +#define EDBG_FL_DBGMSG 0x01 /* Debug messages */ +#define EDBG_FL_PPSH 0x02 /* Text shell */ +#define EDBG_FL_KDBG 0x04 /* Kernel debugger */ +#define EDBG_FL_CLEANBOOT 0x08 /* Force a clean boot */ + +typedef struct { + unsigned char flags; /* Flags that will be used to determine what features are + * enabled over ethernet (saved in driver globals by bootloader) + */ + unsigned char kitlTransport; /* Tells KITL which transport to start */ + + /* The following specify addressing info, only valid if the corresponding + * flag is set in the Flags field. + */ + unsigned int dbgMsgIPAddr; + unsigned short dbgMsgPort; + unsigned int ppshIPAddr; + unsigned short ppshPort; + unsigned int kdbgIPAddr; + unsigned short kdbgPort; +} edbg_os_config_data; + +/* Driver globals structure + * Used to pass driver globals info from RedBoot to WinCE core + */ +#define DRV_GLB_SIGNATURE 0x424C4744 /* "DGLB" */ +#define STD_DRV_GLB_SIGNATURE 0x53475241 /* "ARGS" */ + +typedef struct { + unsigned int signature; /* Signature */ + unsigned int flags; /* Misc flags */ + unsigned int ipAddr; /* IP address of device (net byte order) */ + unsigned int ipGate; /* IP address of gateway (net byte order) */ + unsigned int ipMask; /* Subnet mask */ + unsigned char macAddr[6]; /* Ether address of device (net byte order) */ + edbg_os_config_data edbgConfig; /* EDBG services info */ +} ce_driver_globals; + +#pragma pack(4) + +typedef struct +{ + unsigned long signature; + unsigned short oalVersion; + unsigned short bspVersion; +} OAL_ARGS_HEADER; + +typedef struct _DEVICE_LOCATION +{ + unsigned long IfcType; + unsigned long BusNumber; + unsigned long LogicalLoc; + void *PhysicalLoc; + unsigned long Pin; +} DEVICE_LOCATION; + +typedef struct +{ + unsigned long flags; + DEVICE_LOCATION devLoc; + union { + struct { + unsigned long baudRate; + unsigned long dataBits; + unsigned long stopBits; + unsigned long parity; + }; + struct { + unsigned short mac[3]; + unsigned long ipAddress; + unsigned long ipMask; + unsigned long ipRoute; + }; + }; +} OAL_KITL_ARGS; + +typedef struct +{ + OAL_ARGS_HEADER header; + char deviceId[16]; // Device identification + OAL_KITL_ARGS kitl; + char mtdparts[]; +} ce_std_driver_globals; + - #pragma pack() - +typedef struct { + void *rtiPhysAddr; + unsigned int rtiPhysLen; + void *ePhysAddr; + unsigned int ePhysLen; + unsigned int eChkSum; + + void *eEntryPoint; + void *eRamStart; + unsigned int eRamLen; + ce_driver_globals *eDrvGlb; + + unsigned char parseState; + unsigned int parseChkSum; + int parseLen; + unsigned char *parsePtr; + int section; + + int dataLen; + unsigned char *data; + + int binLen; + int endOfBin; + + edbg_os_config_data edbgConfig; - } __attribute__((packed)) ce_bin; ++} ce_bin; + +/* IPv4 support */ + +/* Socket/connection information */ +struct sockaddr_in { + IPaddr_t sin_addr; + unsigned short sin_port; + unsigned short sin_family; + short sin_len; +}; + +#define AF_INET 1 +#define INADDR_ANY 0 +#ifndef ETH_ALEN +#define ETH_ALEN 6 +#endif + ++enum bootme_state { ++ BOOTME_INIT, ++ BOOTME_DOWNLOAD, ++ BOOTME_DEBUG, ++ BOOTME_DONE, ++ BOOTME_ERROR, ++}; ++ +typedef struct { + int verbose; + int link; ++#ifdef BORKED + struct sockaddr_in locAddr; + struct sockaddr_in srvAddrSend; + struct sockaddr_in srvAddrRecv; ++#else ++ IPaddr_t server_ip; ++#endif + int gotJumpingRequest; - unsigned char seqNum; - unsigned short blockNum; + int dataLen; - int align_offset; - int got_packet_4me; ++// int align_offset; ++// int got_packet_4me; ++// int status; ++ enum bootme_state state; ++ unsigned short blockNum; ++ unsigned char seqNum; ++ unsigned char pad; ++#if 0 + unsigned char data[PKTSIZE_ALIGN]; ++#else ++ unsigned char *data; ++#endif +} ce_net; + +struct timeval { + long tv_sec; /* seconds */ + long tv_usec; /* and microseconds */ +}; + +/* Default UDP ports used for Ethernet download and EDBG messages. May be overriden + * by device in BOOTME message. + */ +#define EDBG_DOWNLOAD_PORT 980 /* For downloading images to bootloader via TFTP */ +#define EDBG_SVC_PORT 981 /* Other types of transfers */ + +/* Byte string for Id field (note - must not conflict with valid TFTP + * opcodes (0-5), as we share the download port with TFTP) + */ +#define EDBG_ID 0x47424445 /* "EDBG" */ + +/* Defs for reserved values of the Service field */ +#define EDBG_SVC_DBGMSG 0 /* Debug messages */ +#define EDBG_SVC_PPSH 1 /* Text shell and PPFS file system */ +#define EDBG_SVC_KDBG 2 /* Kernel debugger */ +#define EDBG_SVC_ADMIN 0xFF /* Administrative messages */ + +/* Commands */ +#define EDBG_CMD_READ_REQ 1 /* Read request */ +#define EDBG_CMD_WRITE_REQ 2 /* Write request */ +#define EDBG_CMD_WRITE 3 /* Host ack */ +#define EDBG_CMD_WRITE_ACK 4 /* Target ack */ +#define EDBG_CMD_ERROR 5 /* Error */ + +/* Service Ids from 3-FE are used for user apps */ +#define NUM_DFLT_EDBG_SERVICES 3 + +/* Size of send and receive windows (except for stop and wait mode) */ +#define EDBG_WINDOW_SIZE 8 + +/* The window size can be negotiated up to this amount if a client provides +* enough memory. + */ +#define EDBG_MAX_WINDOW_SIZE 16 + +/* Max size for an EDBG frame. Based on ethernet MTU - protocol overhead. +* Limited to one MTU because we don't do IP fragmentation on device. + */ +#define EDBG_MAX_DATA_SIZE 1446 + +/* Defs for Flags field. */ +#define EDBG_FL_FROM_DEV 0x01 /* Set if message is from the device */ +#define EDBG_FL_NACK 0x02 /* Set if frame is a nack */ +#define EDBG_FL_ACK 0x04 /* Set if frame is an ack */ +#define EDBG_FL_SYNC 0x08 /* Can be used to reset sequence # to 0 */ +#define EDBG_FL_ADMIN_RESP 0x10 /* For admin messages, indicate whether this is a response */ + +/* Definitions for Cmd field (used for administrative messages) */ +/* Msgs from device */ +#define EDBG_CMD_BOOTME 0 /* Initial bootup message from device */ + +/* Msgs from PC */ +#define EDBG_CMD_SETDEBUG 1 /* Used to set debug zones on device (TBD) */ +#define EDBG_CMD_JUMPIMG 2 /* Command to tell bootloader to jump to existing + * flash or RAM image. Data is same as CMD_OS_CONFIG. */ +#define EDBG_CMD_OS_CONFIG 3 /* Configure OS for debug ethernet services */ +#define EDBG_CMD_QUERYINFO 4 /* "Ping" device, and return information (same fmt as bootme) */ +#define EDBG_CMD_RESET 5 /* Command to have platform perform SW reset (e.g. so it + * can be reprogrammed). Support for this command is + * processor dependant, and may not be implemented + * on all platforms (requires HW mods for Odo). + */ +/* Msgs from device or PC */ +#define EDBG_CMD_SVC_CONFIG 6 +#define EDBG_CMD_SVC_DATA 7 + +#define EDBG_CMD_DEBUGBREAK 8 /* Break into debugger */ + +/* Structures for Data portion of EDBG packets */ +#define EDBG_MAX_DEV_NAMELEN 16 + +/* BOOTME message - Devices broadcast this message when booted to request configuration */ +#define EDBG_CURRENT_BOOTME_VERSION 2 + +/* + * Capability and boot Flags for dwBootFlags in EDBG_BOOTME_DATA + * LOWORD for boot flags, HIWORD for capability flags + */ + +/* Always download image */ +#define EDBG_BOOTFLAG_FORCE_DOWNLOAD 0x00000001 + +/* Support passive-kitl */ +#define EDBG_CAPS_PASSIVEKITL 0x00010000 + +/* Defs for CPUId */ +#define EDBG_CPU_TYPE_SHX 0x10 +#define EDBG_CPU_TYPE_MIPS 0x20 +#define EDBG_CPU_TYPE_X86 0x30 +#define EDBG_CPU_TYPE_ARM 0x40 +#define EDBG_CPU_TYPE_PPC 0x50 +#define EDBG_CPU_TYPE_THUMB 0x60 + +#define EDBG_CPU_SH3 (EDBG_CPU_TYPE_SHX | 0) +#define EDBG_CPU_SH4 (EDBG_CPU_TYPE_SHX | 1) +#define EDBG_CPU_R3000 (EDBG_CPU_TYPE_MIPS | 0) +#define EDBG_CPU_R4101 (EDBG_CPU_TYPE_MIPS | 1) +#define EDBG_CPU_R4102 (EDBG_CPU_TYPE_MIPS | 2) +#define EDBG_CPU_R4111 (EDBG_CPU_TYPE_MIPS | 3) +#define EDBG_CPU_R4200 (EDBG_CPU_TYPE_MIPS | 4) +#define EDBG_CPU_R4300 (EDBG_CPU_TYPE_MIPS | 5) +#define EDBG_CPU_R5230 (EDBG_CPU_TYPE_MIPS | 6) +#define EDBG_CPU_R5432 (EDBG_CPU_TYPE_MIPS | 7) +#define EDBG_CPU_i486 (EDBG_CPU_TYPE_X86 | 0) +#define EDBG_CPU_SA1100 (EDBG_CPU_TYPE_ARM | 0) +#define EDBG_CPU_ARM720 (EDBG_CPU_TYPE_ARM | 1) +#define EDBG_CPU_PPC821 (EDBG_CPU_TYPE_PPC | 0) +#define EDBG_CPU_PPC403 (EDBG_CPU_TYPE_PPC | 1) +#define EDBG_CPU_THUMB720 (EDBG_CPU_TYPE_THUMB | 0) ++ ++typedef enum bootme_state bootme_hand_f(const void *pkt, size_t len); ++ ++int bootme_recv_frame(void *buf, size_t len, int timeout); ++int bootme_send_frame(const void *buf, size_t len); ++//void bootme_init(IPaddr_t server_ip); ++int BootMeRequest(IPaddr_t server_ip, const void *buf, size_t len, int timeout); ++//int ce_download_handler(const void *buf, size_t len); ++int BootMeDownload(bootme_hand_f *pkt_handler); ++int BootMeDebugStart(bootme_hand_f *pkt_handler); +#endif diff --cc net/Makefile index 0544f6bacd,e7764ce932..9e13ed4ce5 --- a/net/Makefile +++ b/net/Makefile @@@ -27,11 -27,15 +27,16 @@@ include $(TOPDIR)/config.m LIB = $(obj)libnet.o ++COBJS-$(CONFIG_CMD_BOOTCE) += bootme.o + COBJS-$(CONFIG_CMD_NET) += arp.o COBJS-$(CONFIG_CMD_NET) += bootp.o + COBJS-$(CONFIG_CMD_CDP) += cdp.o COBJS-$(CONFIG_CMD_DNS) += dns.o COBJS-$(CONFIG_CMD_NET) += eth.o + COBJS-$(CONFIG_CMD_LINK_LOCAL) += link_local.o COBJS-$(CONFIG_CMD_NET) += net.o COBJS-$(CONFIG_CMD_NFS) += nfs.o + COBJS-$(CONFIG_CMD_PING) += ping.o COBJS-$(CONFIG_CMD_RARP) += rarp.o COBJS-$(CONFIG_CMD_SNTP) += sntp.o COBJS-$(CONFIG_CMD_NET) += tftp.o diff --cc net/bootp.c index 621c3752a2,4300f1c2f1..6812929f5f --- a/net/bootp.c +++ b/net/bootp.c @@@ -35,11 -37,8 +37,8 @@@ #define CONFIG_DHCP_MIN_EXT_LEN 64 #endif -ulong BootpID; +static ulong BootpID; int BootpTry; - #ifdef CONFIG_BOOTP_RANDOM_DELAY - static ulong seed1, seed2; - #endif #if defined(CONFIG_CMD_DHCP) static dhcp_state_t dhcp_state = INIT; diff --cc net/bootp.h index 882a060969,ecbcc4d509..a7117528a4 --- a/net/bootp.h +++ b/net/bootp.h @@@ -56,10 -59,13 +59,12 @@@ struct Bootp_t */ /* bootp.c */ -extern ulong BootpID; /* ID of cur BOOTP request */ + extern char BootFile[128]; /* Boot file name */ extern int BootpTry; + /* Send a BOOTP request */ - extern void BootpRequest (void); + extern void BootpRequest(void); /****************** DHCP Support *********************/ extern void DhcpRequest(void); diff --cc net/net.c index c5acf8ff6e,a40cde1e94..facbb5ee05 --- a/net/net.c +++ b/net/net.c @@@ -498,6 -427,11 +427,16 @@@ restart case DNS: DnsStart(); break; + #endif + #if defined(CONFIG_CMD_LINK_LOCAL) + case LINKLOCAL: + link_local_start(); + break; ++#endif ++#if defined(CONFIG_CMD_BOOTCE) ++ case BOOTME: ++ BootmeStart(); ++ break; #endif default: break; @@@ -553,7 -494,7 +499,7 @@@ * Check for a timeout, and run the timeout handler * if we have one. */ -- if (timeHandler && ((get_timer(0) - timeStart) > timeDelta)) { ++ if (timeHandler && ((get_timer(timeStart)) > timeDelta)) { thand_f *x; #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) @@@ -595,8 -538,15 +543,16 @@@ sprintf(buf, "%lX", (unsigned long)load_addr); setenv("fileaddr", buf); } - eth_halt(); - if (protocol != NETCONS) ++ if (protocol != NETCONS) { + eth_halt(); - else ++ } else { + eth_halt_state_only(); ++ } + + eth_set_last_protocol(protocol); + ret = NetBootFileXferSize; + debug_cond(DEBUG_INT_STATE, "--- NetLoop Success!\n"); goto done; case NETLOOP_FAIL: @@@ -1801,7 -1199,7 +1205,6 @@@ NetReceive(uchar *inpkt, int len static int net_check_prereq(enum proto_t protocol) { switch (protocol) { -- /* Fall through */ #if defined(CONFIG_CMD_PING) case PING: if (NetPingIP == 0) { @@@ -1841,6 -1239,6 +1244,7 @@@ common #endif /* Fall through */ ++ case BOOTME: case NETCONS: case TFTPSRV: if (NetOurIP == 0) {