From: Lothar Waßmann Date: Fri, 25 Apr 2014 11:41:08 +0000 (+0200) Subject: karo: tx6: lowlevel_init: various fixes for DDR calibration X-Git-Tag: KARO-TX6-2014-04-28~4 X-Git-Url: https://git.kernelconcepts.de/?p=karo-tx-uboot.git;a=commitdiff_plain;h=387eb10d04cdc406f596a74e214924718ed82a74 karo: tx6: lowlevel_init: various fixes for DDR calibration - remove useless comments - issue manual refresh cycle after disabling automatic refresh - don't enable periodic ZQ calibration until after calibration is done - remove redundant writes to MDMISC - issue MRS commands to select MPR for both banks in case of multiple SDRAM banks used - combine check commands for completion and error bits --- diff --git a/board/karo/tx6/lowlevel_init.S b/board/karo/tx6/lowlevel_init.S index 6ba16d314a..7abaaddc87 100644 --- a/board/karo/tx6/lowlevel_init.S +++ b/board/karo/tx6/lowlevel_init.S @@ -794,6 +794,7 @@ dcd_hdr: MXC_DCD_ITEM(MMDC1_MDSCR, 0x00008000) MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_SET, MMDC1_MDSCR, 0x00004000) MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE) + /* MDCTL */ MXC_DCD_ITEM(MMDC1_MDCTL, MDCTL_VAL) MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_SET, MMDC1_MDMISC, 0x40000000) @@ -802,12 +803,12 @@ dcd_hdr: MXC_DCD_ITEM(MMDC1_MDCFG0, MDCFG0_VAL) MXC_DCD_ITEM(MMDC1_MDCFG1, MDCFG1_VAL) MXC_DCD_ITEM(MMDC1_MDCFG2, MDCFG2_VAL) - MXC_DCD_ITEM(MMDC1_MDRWD, 0x000026d2) /* MDRWD */ + MXC_DCD_ITEM(MMDC1_MDRWD, 0x000026d2) MXC_DCD_ITEM(MMDC1_MDOR, MDOR_VAL) MXC_DCD_ITEM(MMDC1_MDOTC, MDOTC_VAL) MXC_DCD_ITEM(MMDC1_MDPDC, MDPDC_VAL_0) MXC_DCD_ITEM_64(MMDC2_MDPDC, MDPDC_VAL_0) - MXC_DCD_ITEM(MMDC1_MDASP, (PHYS_SDRAM_1_SIZE + SZ_256M) / SZ_32M - 1) /* MDASP */ + MXC_DCD_ITEM(MMDC1_MDASP, (PHYS_SDRAM_1_SIZE + SZ_256M) / SZ_32M - 1) /* CS0 MRS: */ MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(0, 0, mr0_val)) @@ -815,16 +816,17 @@ dcd_hdr: MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(0, 2, mr2_val)) MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(0, 3, 0)) #if BANK_ADDR_BITS > 1 - /* CS1 MRS: MR2 */ + /* CS1 MRS: */ MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(1, 0, mr0_val)) MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(1, 1, mr1_val)) MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(1, 2, mr2_val)) - MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(1, 3, 4)) /* MRS: select MPR */ + MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(1, 3, 0)) #endif MXC_DCD_ITEM(MMDC1_MDREF, 0x0000c000) /* disable refresh */ + MXC_DCD_ITEM(MMDC1_MDSCR, 0x00008020) /* issue one refresh cycle */ - MXC_DCD_ITEM(MMDC1_MPODTCTRL, 0x00022222) /* MPODTCTRL */ + MXC_DCD_ITEM(MMDC1_MPODTCTRL, 0x00022222) MXC_DCD_ITEM_64(MMDC2_MPODTCTRL, 0x00022222) /* DDR3 calibration */ @@ -834,7 +836,7 @@ dcd_hdr: /* ZQ calibration */ MXC_DCD_ITEM(MMDC1_MDSCR, 0x04008010) /* precharge all */ MXC_DCD_ITEM(MMDC1_MDSCR, 0x04008040) /* MRS: ZQ calibration */ - MXC_DCD_ITEM(MMDC1_MPZQHWCTRL, 0xa139002b) + MXC_DCD_ITEM(MMDC1_MPZQHWCTRL, 0xa1390001) MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPZQHWCTRL, 0x00010000) MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE) @@ -873,9 +875,12 @@ dcd_hdr: MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE) MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(0, 1, mr1_val)) /* MRS: end write leveling */ - MXC_DCD_ITEM(MMDC1_MPZQHWCTRL, 0xa138002b) /* DQS gating calibration */ + MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(0, 3, 4)) /* MRS: select MPR */ +#if BANK_ADDR_BITS > 1 + MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(1, 3, 4)) /* MRS: select MPR */ +#endif MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P, SDQS_MASK | 0x7000) /* enable Pullups on DQS pads */ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P, SDQS_MASK | 0x7000) MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P, SDQS_MASK | 0x7000) @@ -885,8 +890,6 @@ dcd_hdr: MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P, SDQS_MASK | 0x7000) MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P, SDQS_MASK | 0x7000) - MXC_DCD_ITEM(MMDC1_MDMISC, MDMISC_VAL) - MXC_DCD_ITEM(MMDC1_MDSCR, 0x00008020) /* issue one refresh cycle */ MXC_DCD_ITEM(MMDC1_MDSCR, 0x04008050) /* precharge all to bank 0 */ @@ -902,8 +905,7 @@ dcd_hdr: MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPDGCTRL0, 0x80000000) MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE) MXC_DCD_ITEM(MMDC1_MPDGCTRL0, 0x50800000) /* choose 32 wait cycles and start DQS calib. */ - MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPDGCTRL0, 0x10000000) - MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPDGCTRL0, 0x00001000) + MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPDGCTRL0, 0x10001000) MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE) /* DRAM_SDQS[0..7] pad config */ @@ -915,33 +917,32 @@ dcd_hdr: MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P, SDQS_MASK) MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P, SDQS_MASK) MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P, SDQS_MASK) - MXC_DCD_ITEM(MMDC1_MDMISC, MDMISC_VAL) /* Read delay calibration */ MXC_DCD_ITEM(MMDC1_MDSCR, 0x04008050) /* precharge all to bank 0 */ MXC_DCD_ITEM(MMDC1_MPRDDLHWCTL, 0x00000030) /* MPRDDLHWCTL: HW_WR_DL_CMP_CYC | HW_RD_DL_EN */ MXC_DCD_ITEM_64(MMDC2_MPRDDLHWCTL, 0x00000030) /* MPRDDLHWCTL: HW_WR_DL_CMP_CYC | HW_RD_DL_EN */ - MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPRDDLHWCTL, 0x00000010) - MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPRDDLHWCTL, 0x0000000f) - MXC_DCD_CMD_CHK_64(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC2_MPRDDLHWCTL, 0x00000010) - MXC_DCD_CMD_CHK_64(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC2_MPRDDLHWCTL, 0x0000000f) + MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPRDDLHWCTL, 0x0000001f) + MXC_DCD_CMD_CHK_64(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC2_MPRDDLHWCTL, 0x0000001f) MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE) MXC_DCD_ITEM(MMDC1_MDSCR, 0x04008050) /* precharge all to bank 0 */ MXC_DCD_ITEM(MMDC1_MPWRDLHWCTL, 0x00000030) /* start WR DL calibration */ - MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPWRDLHWCTL, 0x00000010) - MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPWRDLHWCTL, 0x0000000f) + MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPWRDLHWCTL, 0x0000001f) #if PHYS_SDRAM_1_WIDTH == 64 MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE) MXC_DCD_ITEM(MMDC1_MDSCR, 0x04008050) /* precharge all to bank 0 */ MXC_DCD_ITEM(MMDC2_MPWRDLHWCTL, 0x00000030) /* start WR DL calibration */ - MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC2_MPWRDLHWCTL, 0x00000010) - MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC2_MPWRDLHWCTL, 0x0000000f) + MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC2_MPWRDLHWCTL, 0x0000001f) #endif MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE) MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(0, 3, 0)) /* MRS: select normal data path */ +#if BANK_ADDR_BITS > 1 + MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(1, 3, 0)) /* MRS: select normal data path */ +#endif + MXC_DCD_ITEM(MMDC1_MPZQHWCTRL, 0xa138002b) MXC_DCD_ITEM(MMDC1_MDREF, (3 << 11) | (0 << 14)) /* 4 cycles per 64kHz period (3.9us) */ MXC_DCD_ITEM(MMDC1_MAPSR, 0x00001006) MXC_DCD_ITEM(MMDC1_MDPDC, MDPDC_VAL_1)