From: Lothar Waßmann Date: Fri, 1 Jul 2016 13:41:16 +0000 (+0200) Subject: karo: tx6: configure all pads with explicit pad_ctl values X-Git-Tag: KARO-TX-2016-07-05~1^2~7 X-Git-Url: https://git.kernelconcepts.de/?p=karo-tx-uboot.git;a=commitdiff_plain;h=bf272cb82bf1181b6546910e53650b0cd50c8a55 karo: tx6: configure all pads with explicit pad_ctl values --- diff --git a/board/karo/tx6/tx6qdl.c b/board/karo/tx6/tx6qdl.c index d2d1e8364f..dcc6f175de 100644 --- a/board/karo/tx6/tx6qdl.c +++ b/board/karo/tx6/tx6qdl.c @@ -64,68 +64,85 @@ char __uboot_img_end[0] __attribute__((section(".__uboot_img_end"))); char __csf_data[0] __attribute__((section(".__csf_data"))); #endif +#define TX6_DEFAULT_PAD_CTRL MUX_PAD_CTRL(PAD_CTL_PUS_100K_UP | \ + PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | \ + PAD_CTL_SRE_FAST) +#define TX6_FEC_PAD_CTRL MUX_PAD_CTRL(PAD_CTL_PUS_100K_UP | \ + PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | \ + PAD_CTL_SRE_FAST) +#define TX6_GPIO_PAD_CTRL MUX_PAD_CTRL(PAD_CTL_PUS_22K_UP | \ + PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_34ohm | \ + PAD_CTL_SRE_FAST) +#define TX6_I2C_PAD_CTRL MUX_PAD_CTRL(PAD_CTL_PUS_22K_UP | \ + PAD_CTL_HYS | \ + PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_40ohm | \ + PAD_CTL_SRE_SLOW) + static const iomux_v3_cfg_t const tx6qdl_pads[] = { /* RESET_OUT */ - MX6_PAD_GPIO_17__GPIO7_IO12, + MX6_PAD_GPIO_17__GPIO7_IO12 | TX6_DEFAULT_PAD_CTRL, /* UART pads */ #if CONFIG_MXC_UART_BASE == UART1_BASE - MX6_PAD_SD3_DAT7__UART1_TX_DATA, - MX6_PAD_SD3_DAT6__UART1_RX_DATA, - MX6_PAD_SD3_DAT1__UART1_RTS_B, - MX6_PAD_SD3_DAT0__UART1_CTS_B, + MX6_PAD_SD3_DAT7__UART1_TX_DATA | TX6_DEFAULT_PAD_CTRL, + MX6_PAD_SD3_DAT6__UART1_RX_DATA | TX6_DEFAULT_PAD_CTRL, + MX6_PAD_SD3_DAT1__UART1_RTS_B | TX6_DEFAULT_PAD_CTRL, + MX6_PAD_SD3_DAT0__UART1_CTS_B | TX6_DEFAULT_PAD_CTRL, #endif #if CONFIG_MXC_UART_BASE == UART2_BASE - MX6_PAD_SD4_DAT4__UART2_RX_DATA, - MX6_PAD_SD4_DAT7__UART2_TX_DATA, - MX6_PAD_SD4_DAT5__UART2_RTS_B, - MX6_PAD_SD4_DAT6__UART2_CTS_B, + MX6_PAD_SD4_DAT4__UART2_RX_DATA | TX6_DEFAULT_PAD_CTRL, + MX6_PAD_SD4_DAT7__UART2_TX_DATA | TX6_DEFAULT_PAD_CTRL, + MX6_PAD_SD4_DAT5__UART2_RTS_B | TX6_DEFAULT_PAD_CTRL, + MX6_PAD_SD4_DAT6__UART2_CTS_B | TX6_DEFAULT_PAD_CTRL, #endif #if CONFIG_MXC_UART_BASE == UART3_BASE - MX6_PAD_EIM_D24__UART3_TX_DATA, - MX6_PAD_EIM_D25__UART3_RX_DATA, - MX6_PAD_SD3_RST__UART3_RTS_B, - MX6_PAD_SD3_DAT3__UART3_CTS_B, + MX6_PAD_EIM_D24__UART3_TX_DATA | TX6_DEFAULT_PAD_CTRL, + MX6_PAD_EIM_D25__UART3_RX_DATA | TX6_DEFAULT_PAD_CTRL, + MX6_PAD_SD3_RST__UART3_RTS_B | TX6_DEFAULT_PAD_CTRL, + MX6_PAD_SD3_DAT3__UART3_CTS_B | TX6_DEFAULT_PAD_CTRL, #endif /* internal I2C */ - MX6_PAD_EIM_D28__I2C1_SDA, - MX6_PAD_EIM_D21__I2C1_SCL, + MX6_PAD_EIM_D28__I2C1_SDA | TX6_DEFAULT_PAD_CTRL, + MX6_PAD_EIM_D21__I2C1_SCL | TX6_DEFAULT_PAD_CTRL, /* FEC PHY GPIO functions */ - MX6_PAD_EIM_D20__GPIO3_IO20 | MUX_CFG_SION, /* PHY POWER */ - MX6_PAD_SD3_DAT2__GPIO7_IO06 | MUX_CFG_SION, /* PHY RESET */ - MX6_PAD_SD3_DAT4__GPIO7_IO01, /* PHY INT */ + MX6_PAD_EIM_D20__GPIO3_IO20 | MUX_CFG_SION | + TX6_DEFAULT_PAD_CTRL, /* PHY POWER */ + MX6_PAD_SD3_DAT2__GPIO7_IO06 | MUX_CFG_SION | + TX6_DEFAULT_PAD_CTRL, /* PHY RESET */ + MX6_PAD_SD3_DAT4__GPIO7_IO01 | TX6_DEFAULT_PAD_CTRL, /* PHY INT */ }; static const iomux_v3_cfg_t const tx6qdl_fec_pads[] = { /* FEC functions */ - MX6_PAD_ENET_MDC__ENET_MDC, - MX6_PAD_ENET_MDIO__ENET_MDIO, - MX6_PAD_GPIO_16__ENET_REF_CLK, - MX6_PAD_ENET_RX_ER__ENET_RX_ER, - MX6_PAD_ENET_CRS_DV__ENET_RX_EN, - MX6_PAD_ENET_RXD1__ENET_RX_DATA1, - MX6_PAD_ENET_RXD0__ENET_RX_DATA0, - MX6_PAD_ENET_TX_EN__ENET_TX_EN, - MX6_PAD_ENET_TXD1__ENET_TX_DATA1, - MX6_PAD_ENET_TXD0__ENET_TX_DATA0, + MX6_PAD_ENET_MDC__ENET_MDC | TX6_FEC_PAD_CTRL, + MX6_PAD_ENET_MDIO__ENET_MDIO | TX6_FEC_PAD_CTRL, + MX6_PAD_GPIO_16__ENET_REF_CLK | TX6_FEC_PAD_CTRL, + MX6_PAD_ENET_RX_ER__ENET_RX_ER | TX6_FEC_PAD_CTRL, + MX6_PAD_ENET_CRS_DV__ENET_RX_EN | TX6_FEC_PAD_CTRL, + MX6_PAD_ENET_RXD1__ENET_RX_DATA1 | TX6_FEC_PAD_CTRL, + MX6_PAD_ENET_RXD0__ENET_RX_DATA0 | TX6_FEC_PAD_CTRL, + MX6_PAD_ENET_TX_EN__ENET_TX_EN | TX6_FEC_PAD_CTRL, + MX6_PAD_ENET_TXD1__ENET_TX_DATA1 | TX6_FEC_PAD_CTRL, + MX6_PAD_ENET_TXD0__ENET_TX_DATA0 | TX6_FEC_PAD_CTRL, }; -#define TX6_I2C_GPIO_PAD_CTRL (PAD_CTL_PUS_22K_UP | \ - PAD_CTL_SPEED_MED | \ - PAD_CTL_DSE_34ohm | \ - PAD_CTL_SRE_FAST) - static const iomux_v3_cfg_t const tx6_i2c_gpio_pads[] = { /* internal I2C */ - MX6_PAD_EIM_D28__GPIO3_IO28 | MUX_CFG_SION | MUX_PAD_CTRL(TX6_I2C_GPIO_PAD_CTRL), - MX6_PAD_EIM_D21__GPIO3_IO21 | MUX_CFG_SION | MUX_PAD_CTRL(TX6_I2C_GPIO_PAD_CTRL), + MX6_PAD_EIM_D28__GPIO3_IO28 | MUX_CFG_SION | + TX6_GPIO_PAD_CTRL, + MX6_PAD_EIM_D21__GPIO3_IO21 | MUX_CFG_SION | + TX6_GPIO_PAD_CTRL, }; static const iomux_v3_cfg_t const tx6_i2c_pads[] = { /* internal I2C */ - MX6_PAD_EIM_D28__I2C1_SDA, - MX6_PAD_EIM_D21__I2C1_SCL, + MX6_PAD_EIM_D28__I2C1_SDA | TX6_I2C_PAD_CTRL, + MX6_PAD_EIM_D21__I2C1_SCL | TX6_I2C_PAD_CTRL, }; static const struct gpio const tx6qdl_gpios[] = { @@ -545,43 +562,42 @@ void dram_init_banksize(void) } #ifdef CONFIG_FSL_ESDHC -#define SD_PAD_CTRL (PAD_CTL_PUS_47K_UP | \ - PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ - PAD_CTL_SRE_FAST) +#define SD_PAD_CTRL MUX_PAD_CTRL(PAD_CTL_PUS_47K_UP | \ + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ + PAD_CTL_SRE_FAST) static const iomux_v3_cfg_t mmc0_pads[] = { - MX6_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(SD_PAD_CTRL), - MX6_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(SD_PAD_CTRL), - MX6_PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(SD_PAD_CTRL), - MX6_PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(SD_PAD_CTRL), - MX6_PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(SD_PAD_CTRL), - MX6_PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(SD_PAD_CTRL), + MX6_PAD_SD1_CMD__SD1_CMD | SD_PAD_CTRL, + MX6_PAD_SD1_CLK__SD1_CLK | SD_PAD_CTRL, + MX6_PAD_SD1_DAT0__SD1_DATA0 | SD_PAD_CTRL, + MX6_PAD_SD1_DAT1__SD1_DATA1 | SD_PAD_CTRL, + MX6_PAD_SD1_DAT2__SD1_DATA2 | SD_PAD_CTRL, + MX6_PAD_SD1_DAT3__SD1_DATA3 | SD_PAD_CTRL, /* SD1 CD */ - MX6_PAD_SD3_CMD__GPIO7_IO02, + MX6_PAD_SD3_CMD__GPIO7_IO02 | TX6_GPIO_PAD_CTRL, }; static const iomux_v3_cfg_t mmc1_pads[] = { - MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(SD_PAD_CTRL), - MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(SD_PAD_CTRL), - MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(SD_PAD_CTRL), - MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(SD_PAD_CTRL), - MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(SD_PAD_CTRL), - MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(SD_PAD_CTRL), + MX6_PAD_SD2_CMD__SD2_CMD | SD_PAD_CTRL, + MX6_PAD_SD2_CLK__SD2_CLK | SD_PAD_CTRL, + MX6_PAD_SD2_DAT0__SD2_DATA0 | SD_PAD_CTRL, + MX6_PAD_SD2_DAT1__SD2_DATA1 | SD_PAD_CTRL, + MX6_PAD_SD2_DAT2__SD2_DATA2 | SD_PAD_CTRL, + MX6_PAD_SD2_DAT3__SD2_DATA3 | SD_PAD_CTRL, /* SD2 CD */ - MX6_PAD_SD3_CLK__GPIO7_IO03, + MX6_PAD_SD3_CLK__GPIO7_IO03 | TX6_GPIO_PAD_CTRL, }; #ifdef CONFIG_TX6_EMMC static const iomux_v3_cfg_t mmc3_pads[] = { - MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(SD_PAD_CTRL), - MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(SD_PAD_CTRL), - MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(SD_PAD_CTRL), - MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(SD_PAD_CTRL), - MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(SD_PAD_CTRL), - MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(SD_PAD_CTRL), + MX6_PAD_SD4_CMD__SD4_CMD | SD_PAD_CTRL, + MX6_PAD_SD4_CLK__SD4_CLK | SD_PAD_CTRL, + MX6_PAD_SD4_DAT0__SD4_DATA0 | SD_PAD_CTRL, + MX6_PAD_SD4_DAT1__SD4_DATA1 | SD_PAD_CTRL, + MX6_PAD_SD4_DAT2__SD4_DATA2 | SD_PAD_CTRL, + MX6_PAD_SD4_DAT3__SD4_DATA3 | SD_PAD_CTRL, /* eMMC RESET */ - MX6_PAD_NANDF_ALE__SD4_RESET | MUX_PAD_CTRL(PAD_CTL_PUS_47K_UP | - PAD_CTL_DSE_40ohm), + MX6_PAD_NANDF_ALE__SD4_RESET | SD_PAD_CTRL, }; #endif @@ -772,27 +788,27 @@ void show_activity(int arg) static const iomux_v3_cfg_t stk5_pads[] = { /* SW controlled LED on STK5 baseboard */ - MX6_PAD_EIM_A18__GPIO2_IO20, + MX6_PAD_EIM_A18__GPIO2_IO20 | TX6_GPIO_PAD_CTRL, /* I2C bus on DIMM pins 40/41 */ - MX6_PAD_GPIO_6__I2C3_SDA, - MX6_PAD_GPIO_3__I2C3_SCL, + MX6_PAD_GPIO_6__I2C3_SDA | TX6_I2C_PAD_CTRL, + MX6_PAD_GPIO_3__I2C3_SCL | TX6_I2C_PAD_CTRL, /* TSC200x PEN IRQ */ - MX6_PAD_EIM_D26__GPIO3_IO26, + MX6_PAD_EIM_D26__GPIO3_IO26 | TX6_GPIO_PAD_CTRL, /* EDT-FT5x06 Polytouch panel */ - MX6_PAD_NANDF_CS2__GPIO6_IO15, /* IRQ */ - MX6_PAD_EIM_A16__GPIO2_IO22, /* RESET */ - MX6_PAD_EIM_A17__GPIO2_IO21, /* WAKE */ + MX6_PAD_NANDF_CS2__GPIO6_IO15 | TX6_GPIO_PAD_CTRL, /* IRQ */ + MX6_PAD_EIM_A16__GPIO2_IO22 | TX6_GPIO_PAD_CTRL, /* RESET */ + MX6_PAD_EIM_A17__GPIO2_IO21 | TX6_GPIO_PAD_CTRL, /* WAKE */ /* USBH1 */ - MX6_PAD_EIM_D31__GPIO3_IO31, /* VBUSEN */ - MX6_PAD_EIM_D30__GPIO3_IO30, /* OC */ + MX6_PAD_EIM_D31__GPIO3_IO31 | TX6_GPIO_PAD_CTRL, /* VBUSEN */ + MX6_PAD_EIM_D30__GPIO3_IO30 | TX6_GPIO_PAD_CTRL, /* OC */ /* USBOTG */ - MX6_PAD_EIM_D23__GPIO3_IO23, /* USBOTG ID */ - MX6_PAD_GPIO_7__GPIO1_IO07, /* VBUSEN */ - MX6_PAD_GPIO_8__GPIO1_IO08, /* OC */ + MX6_PAD_EIM_D23__GPIO3_IO23 | TX6_GPIO_PAD_CTRL, /* USBOTG ID */ + MX6_PAD_GPIO_7__GPIO1_IO07 | TX6_GPIO_PAD_CTRL, /* VBUSEN */ + MX6_PAD_GPIO_8__GPIO1_IO08 | TX6_GPIO_PAD_CTRL, /* OC */ }; static const struct gpio stk5_gpios[] = { @@ -1033,42 +1049,42 @@ void lcd_panel_disable(void) static const iomux_v3_cfg_t stk5_lcd_pads[] = { /* LCD RESET */ - MX6_PAD_EIM_D29__GPIO3_IO29, + MX6_PAD_EIM_D29__GPIO3_IO29 | TX6_GPIO_PAD_CTRL, /* LCD POWER_ENABLE */ - MX6_PAD_EIM_EB3__GPIO2_IO31, + MX6_PAD_EIM_EB3__GPIO2_IO31 | TX6_GPIO_PAD_CTRL, /* LCD Backlight (PWM) */ - MX6_PAD_GPIO_1__GPIO1_IO01, + MX6_PAD_GPIO_1__GPIO1_IO01 | TX6_GPIO_PAD_CTRL, #ifndef CONFIG_SYS_LVDS_IF /* Display */ - MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00, - MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01, - MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02, - MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03, - MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04, - MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05, - MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06, - MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07, - MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08, - MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09, - MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10, - MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11, - MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12, - MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13, - MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14, - MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15, - MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16, - MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17, - MX6_PAD_DISP0_DAT18__IPU1_DISP0_DATA18, - MX6_PAD_DISP0_DAT19__IPU1_DISP0_DATA19, - MX6_PAD_DISP0_DAT20__IPU1_DISP0_DATA20, - MX6_PAD_DISP0_DAT21__IPU1_DISP0_DATA21, - MX6_PAD_DISP0_DAT22__IPU1_DISP0_DATA22, - MX6_PAD_DISP0_DAT23__IPU1_DISP0_DATA23, - MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02, /* HSYNC */ - MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03, /* VSYNC */ - MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15, /* OE_ACD */ - MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK, /* LSCLK */ + MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 | TX6_GPIO_PAD_CTRL, + MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 | TX6_GPIO_PAD_CTRL, + MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 | TX6_GPIO_PAD_CTRL, + MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 | TX6_GPIO_PAD_CTRL, + MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 | TX6_GPIO_PAD_CTRL, + MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 | TX6_GPIO_PAD_CTRL, + MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 | TX6_GPIO_PAD_CTRL, + MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 | TX6_GPIO_PAD_CTRL, + MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 | TX6_GPIO_PAD_CTRL, + MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 | TX6_GPIO_PAD_CTRL, + MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 | TX6_GPIO_PAD_CTRL, + MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 | TX6_GPIO_PAD_CTRL, + MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 | TX6_GPIO_PAD_CTRL, + MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 | TX6_GPIO_PAD_CTRL, + MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 | TX6_GPIO_PAD_CTRL, + MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 | TX6_GPIO_PAD_CTRL, + MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 | TX6_GPIO_PAD_CTRL, + MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 | TX6_GPIO_PAD_CTRL, + MX6_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 | TX6_GPIO_PAD_CTRL, + MX6_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 | TX6_GPIO_PAD_CTRL, + MX6_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 | TX6_GPIO_PAD_CTRL, + MX6_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 | TX6_GPIO_PAD_CTRL, + MX6_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 | TX6_GPIO_PAD_CTRL, + MX6_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 | TX6_GPIO_PAD_CTRL, + MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02 | TX6_GPIO_PAD_CTRL, /* HSYNC */ + MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03 | TX6_GPIO_PAD_CTRL, /* VSYNC */ + MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15 | TX6_GPIO_PAD_CTRL, /* OE_ACD */ + MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK | TX6_GPIO_PAD_CTRL, /* LSCLK */ #endif }; @@ -1368,7 +1384,8 @@ static void stk5v5_board_init(void) return; } - imx_iomux_v3_setup_pad(MX6_PAD_DISP0_DAT0__GPIO4_IO21); + imx_iomux_v3_setup_pad(MX6_PAD_DISP0_DAT0__GPIO4_IO21 | + TX6_GPIO_PAD_CTRL); } static void tx6qdl_set_cpu_clock(void) diff --git a/board/karo/tx6/tx6ul.c b/board/karo/tx6/tx6ul.c index 0fc9876098..5ccb68b958 100644 --- a/board/karo/tx6/tx6ul.c +++ b/board/karo/tx6/tx6ul.c @@ -71,95 +71,91 @@ char __uboot_img_end[0] __attribute__((section(".__uboot_img_end"))); char __csf_data[0] __attribute__((section(".__csf_data"))); #endif +#define TX6UL_DEFAULT_PAD_CTRL MUX_PAD_CTRL(PAD_CTL_PUS_100K_UP | \ + PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | \ + PAD_CTL_SRE_FAST) +#define TX6UL_I2C_PAD_CTRL MUX_PAD_CTRL(PAD_CTL_PUS_22K_UP | \ + PAD_CTL_HYS | \ + PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_34ohm | \ + PAD_CTL_SRE_FAST) +#define TX6UL_ENET_PAD_CTRL MUX_PAD_CTRL(PAD_CTL_SPEED_HIGH | \ + PAD_CTL_DSE_48ohm | \ + PAD_CTL_PUS_100K_UP | \ + PAD_CTL_SRE_FAST) +#define TX6UL_GPIO_OUT_PAD_CTRL MUX_PAD_CTRL(PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_60ohm | \ + PAD_CTL_SRE_SLOW) +#define TX6UL_GPIO_IN_PAD_CTRL MUX_PAD_CTRL(PAD_CTL_SPEED_LOW | \ + PAD_CTL_PUS_47K_UP) + + static const iomux_v3_cfg_t const tx6ul_pads[] = { /* UART pads */ #if CONFIG_MXC_UART_BASE == UART1_BASE - MX6_PAD_UART1_TX_DATA__UART1_DCE_TX, - MX6_PAD_UART1_RX_DATA__UART1_DCE_RX, - MX6_PAD_UART1_RTS_B__UART1_DCE_RTS, - MX6_PAD_UART1_CTS_B__UART1_DCE_CTS, + MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | TX6UL_DEFAULT_PAD_CTRL, + MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | TX6UL_DEFAULT_PAD_CTRL, + MX6_PAD_UART1_RTS_B__UART1_DCE_RTS | TX6UL_DEFAULT_PAD_CTRL, + MX6_PAD_UART1_CTS_B__UART1_DCE_CTS | TX6UL_DEFAULT_PAD_CTRL, #endif #if CONFIG_MXC_UART_BASE == UART2_BASE - MX6_PAD_UART2_TX_DATA__UART2_DCE_TX, - MX6_PAD_UART2_RX_DATA__UART2_DCE_RX, - MX6_PAD_UART3_RX_DATA__UART2_DCE_RTS, - MX6_PAD_UART3_TX_DATA__UART2_DCE_CTS, + MX6_PAD_UART2_TX_DATA__UART2_DCE_TX | TX6UL_DEFAULT_PAD_CTRL, + MX6_PAD_UART2_RX_DATA__UART2_DCE_RX | TX6UL_DEFAULT_PAD_CTRL, + MX6_PAD_UART3_RX_DATA__UART2_DCE_RTS | TX6UL_DEFAULT_PAD_CTRL, + MX6_PAD_UART3_TX_DATA__UART2_DCE_CTS | TX6UL_DEFAULT_PAD_CTRL, #endif #if CONFIG_MXC_UART_BASE == UART5_BASE - MX6_PAD_GPIO1_IO04__UART5_DCE_TX, - MX6_PAD_GPIO1_IO05__UART5_DCE_RX, - MX6_PAD_GPIO1_IO08__UART5_DCE_RTS, - MX6_PAD_GPIO1_IO09__UART5_DCE_CTS, + MX6_PAD_GPIO1_IO04__UART5_DCE_TX | TX6UL_DEFAULT_PAD_CTRL, + MX6_PAD_GPIO1_IO05__UART5_DCE_RX | TX6UL_DEFAULT_PAD_CTRL, + MX6_PAD_GPIO1_IO08__UART5_DCE_RTS | TX6UL_DEFAULT_PAD_CTRL, + MX6_PAD_GPIO1_IO09__UART5_DCE_CTS | TX6UL_DEFAULT_PAD_CTRL, #endif - /* internal I2C */ - MX6_PAD_SNVS_TAMPER1__GPIO5_IO01 | MUX_CFG_SION | - MUX_PAD_CTRL(PAD_CTL_DSE_240ohm), /* I2C SCL */ - MX6_PAD_SNVS_TAMPER0__GPIO5_IO00 | MUX_CFG_SION | - MUX_PAD_CTRL(PAD_CTL_DSE_240ohm | PAD_CTL_HYS | - PAD_CTL_ODE), /* I2C SDA */ - /* FEC PHY GPIO functions */ - MX6_PAD_SNVS_TAMPER7__GPIO5_IO07 | MUX_CFG_SION, /* PHY POWER */ - MX6_PAD_SNVS_TAMPER6__GPIO5_IO06 | MUX_CFG_SION, /* PHY RESET */ - MX6_PAD_SNVS_TAMPER5__GPIO5_IO05 | MUX_PAD_CTRL(PAD_CTL_PUS_22K_UP | - PAD_CTL_DSE_40ohm), /* PHY INT */ + MX6_PAD_SNVS_TAMPER7__GPIO5_IO07 | TX6UL_GPIO_OUT_PAD_CTRL, /* PHY POWER */ + MX6_PAD_SNVS_TAMPER6__GPIO5_IO06 | TX6UL_GPIO_OUT_PAD_CTRL, /* PHY RESET */ + MX6_PAD_SNVS_TAMPER5__GPIO5_IO05 | TX6UL_GPIO_IN_PAD_CTRL, /* PHY INT */ }; -#define TX6_ENET_PAD_CTRL (PAD_CTL_SPEED_HIGH | \ - PAD_CTL_DSE_48ohm | \ - PAD_CTL_PUS_100K_UP | \ - PAD_CTL_SRE_FAST) -#define TX6_GPIO_OUT_PAD_CTRL (PAD_CTL_SPEED_LOW | \ - PAD_CTL_DSE_60ohm | \ - PAD_CTL_SRE_SLOW) -#define TX6_GPIO_IN_PAD_CTRL (PAD_CTL_SPEED_LOW | \ - PAD_CTL_PUS_47K_UP) - static const iomux_v3_cfg_t const tx6ul_enet1_pads[] = { /* FEC functions */ MX6_PAD_GPIO1_IO07__ENET1_MDC | MUX_PAD_CTRL(PAD_CTL_DSE_48ohm | PAD_CTL_SPEED_MED), MX6_PAD_GPIO1_IO06__ENET1_MDIO | MUX_PAD_CTRL(PAD_CTL_PUS_100K_UP | - PAD_CTL_DSE_48ohm | - PAD_CTL_SPEED_MED), + PAD_CTL_DSE_48ohm | PAD_CTL_SPEED_MED), MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_CFG_SION | MUX_PAD_CTRL(PAD_CTL_SPEED_MED | - PAD_CTL_DSE_40ohm | - PAD_CTL_SRE_FAST), - MX6_PAD_ENET1_RX_ER__ENET1_RX_ER | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL), - MX6_PAD_ENET1_RX_EN__ENET1_RX_EN | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL), - MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01 | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL), - MX6_PAD_ENET1_RX_DATA0__ENET1_RDATA00 | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL), - MX6_PAD_ENET1_TX_EN__ENET1_TX_EN | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL), - MX6_PAD_ENET1_TX_DATA1__ENET1_TDATA01 | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL), - MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00 | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL), + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST), + MX6_PAD_ENET1_RX_ER__ENET1_RX_ER | TX6UL_ENET_PAD_CTRL, + MX6_PAD_ENET1_RX_EN__ENET1_RX_EN | TX6UL_ENET_PAD_CTRL, + MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01 | TX6UL_ENET_PAD_CTRL, + MX6_PAD_ENET1_RX_DATA0__ENET1_RDATA00 | TX6UL_ENET_PAD_CTRL, + MX6_PAD_ENET1_TX_EN__ENET1_TX_EN | TX6UL_ENET_PAD_CTRL, + MX6_PAD_ENET1_TX_DATA1__ENET1_TDATA01 | TX6UL_ENET_PAD_CTRL, + MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00 | TX6UL_ENET_PAD_CTRL, }; static const iomux_v3_cfg_t const tx6ul_enet2_pads[] = { MX6_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 | MUX_CFG_SION | MUX_PAD_CTRL(PAD_CTL_SPEED_HIGH | - PAD_CTL_DSE_48ohm | - PAD_CTL_SRE_FAST), - MX6_PAD_ENET2_RX_ER__ENET2_RX_ER | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL), - MX6_PAD_ENET2_RX_EN__ENET2_RX_EN | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL), - MX6_PAD_ENET2_RX_DATA1__ENET2_RDATA01 | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL), - MX6_PAD_ENET2_RX_DATA0__ENET2_RDATA00 | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL), - MX6_PAD_ENET2_TX_EN__ENET2_TX_EN | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL), - MX6_PAD_ENET2_TX_DATA1__ENET2_TDATA01 | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL), - MX6_PAD_ENET2_TX_DATA0__ENET2_TDATA00 | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL), + PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST), + MX6_PAD_ENET2_RX_ER__ENET2_RX_ER | TX6UL_ENET_PAD_CTRL, + MX6_PAD_ENET2_RX_EN__ENET2_RX_EN | TX6UL_ENET_PAD_CTRL, + MX6_PAD_ENET2_RX_DATA1__ENET2_RDATA01 | TX6UL_ENET_PAD_CTRL, + MX6_PAD_ENET2_RX_DATA0__ENET2_RDATA00 | TX6UL_ENET_PAD_CTRL, + MX6_PAD_ENET2_TX_EN__ENET2_TX_EN | TX6UL_ENET_PAD_CTRL, + MX6_PAD_ENET2_TX_DATA1__ENET2_TDATA01 | TX6UL_ENET_PAD_CTRL, + MX6_PAD_ENET2_TX_DATA0__ENET2_TDATA00 | TX6UL_ENET_PAD_CTRL, }; -#define TX6_I2C_PAD_CTRL (PAD_CTL_PUS_22K_UP | \ - PAD_CTL_SPEED_MED | \ - PAD_CTL_DSE_34ohm | \ - PAD_CTL_SRE_FAST) - static const iomux_v3_cfg_t const tx6_i2c_gpio_pads[] = { /* internal I2C */ MX6_PAD_SNVS_TAMPER1__GPIO5_IO01 | MUX_CFG_SION | - MUX_PAD_CTRL(TX6_I2C_PAD_CTRL), + MUX_PAD_CTRL(PAD_CTL_DSE_240ohm | PAD_CTL_HYS | + PAD_CTL_ODE), /* I2C SCL */ MX6_PAD_SNVS_TAMPER0__GPIO5_IO00 | MUX_CFG_SION | - MUX_PAD_CTRL(TX6_I2C_PAD_CTRL), + MUX_PAD_CTRL(PAD_CTL_DSE_240ohm | PAD_CTL_HYS | + PAD_CTL_ODE), /* I2C SDA */ }; static const struct gpio const tx6ul_gpios[] = { @@ -459,9 +455,9 @@ int board_init(void) get_hab_status(); ret = gpio_request_array(tx6ul_gpios, ARRAY_SIZE(tx6ul_gpios)); - if (ret < 0) { + if (ret < 0) printf("Failed to request tx6ul_gpios: %d\n", ret); - } + imx_iomux_v3_setup_multiple_pads(tx6ul_pads, ARRAY_SIZE(tx6ul_pads)); /* Address of boot parameters */ @@ -512,30 +508,30 @@ void dram_init_banksize(void) } #ifdef CONFIG_FSL_ESDHC -#define TX6_SD_PAD_CTRL (PAD_CTL_PUS_47K_UP | \ - PAD_CTL_SPEED_MED | \ - PAD_CTL_DSE_40ohm | \ - PAD_CTL_SRE_FAST) +#define TX6UL_SD_PAD_CTRL MUX_PAD_CTRL(PAD_CTL_PUS_47K_UP | \ + PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | \ + PAD_CTL_SRE_FAST) static const iomux_v3_cfg_t mmc0_pads[] = { - MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(TX6_SD_PAD_CTRL), - MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(TX6_SD_PAD_CTRL), - MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(TX6_SD_PAD_CTRL), - MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(TX6_SD_PAD_CTRL), - MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(TX6_SD_PAD_CTRL), - MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(TX6_SD_PAD_CTRL), + MX6_PAD_SD1_CMD__USDHC1_CMD | TX6UL_SD_PAD_CTRL, + MX6_PAD_SD1_CLK__USDHC1_CLK | TX6UL_SD_PAD_CTRL, + MX6_PAD_SD1_DATA0__USDHC1_DATA0 | TX6UL_SD_PAD_CTRL, + MX6_PAD_SD1_DATA1__USDHC1_DATA1 | TX6UL_SD_PAD_CTRL, + MX6_PAD_SD1_DATA2__USDHC1_DATA2 | TX6UL_SD_PAD_CTRL, + MX6_PAD_SD1_DATA3__USDHC1_DATA3 | TX6UL_SD_PAD_CTRL, /* SD1 CD */ - MX6_PAD_NAND_CE1_B__GPIO4_IO14 | MUX_PAD_CTRL(TX6_SD_PAD_CTRL), + MX6_PAD_NAND_CE1_B__GPIO4_IO14 | TX6UL_SD_PAD_CTRL, }; #ifdef CONFIG_TX6_EMMC static const iomux_v3_cfg_t mmc1_pads[] = { - MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(TX6_SD_PAD_CTRL), - MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(TX6_SD_PAD_CTRL), - MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(TX6_SD_PAD_CTRL), - MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(TX6_SD_PAD_CTRL), - MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(TX6_SD_PAD_CTRL), - MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(TX6_SD_PAD_CTRL), + MX6_PAD_NAND_WE_B__USDHC2_CMD | TX6UL_SD_PAD_CTRL, + MX6_PAD_NAND_RE_B__USDHC2_CLK | TX6UL_SD_PAD_CTRL, + MX6_PAD_NAND_DATA00__USDHC2_DATA0 | TX6UL_SD_PAD_CTRL, + MX6_PAD_NAND_DATA01__USDHC2_DATA1 | TX6UL_SD_PAD_CTRL, + MX6_PAD_NAND_DATA02__USDHC2_DATA2 | TX6UL_SD_PAD_CTRL, + MX6_PAD_NAND_DATA03__USDHC2_DATA3 | TX6UL_SD_PAD_CTRL, /* eMMC RESET */ MX6_PAD_NAND_ALE__USDHC2_RESET_B | MUX_PAD_CTRL(PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_40ohm), @@ -694,24 +690,24 @@ static const iomux_v3_cfg_t stk5_pads[] = { MX6_PAD_SNVS_TAMPER9__GPIO5_IO09, /* I2C bus on DIMM pins 40/41 */ - MX6_PAD_GPIO1_IO01__I2C2_SDA | MUX_MODE_SION | MUX_PAD_CTRL(TX6_I2C_PAD_CTRL), - MX6_PAD_GPIO1_IO00__I2C2_SCL | MUX_MODE_SION | MUX_PAD_CTRL(TX6_I2C_PAD_CTRL), + MX6_PAD_GPIO1_IO01__I2C2_SDA | MUX_MODE_SION | TX6UL_I2C_PAD_CTRL, + MX6_PAD_GPIO1_IO00__I2C2_SCL | MUX_MODE_SION | TX6UL_I2C_PAD_CTRL, /* TSC200x PEN IRQ */ - MX6_PAD_JTAG_TMS__GPIO1_IO11 | MUX_PAD_CTRL(TX6_GPIO_IN_PAD_CTRL), + MX6_PAD_JTAG_TMS__GPIO1_IO11 | TX6UL_GPIO_IN_PAD_CTRL, /* EDT-FT5x06 Polytouch panel */ - MX6_PAD_SNVS_TAMPER2__GPIO5_IO02 | MUX_PAD_CTRL(TX6_GPIO_IN_PAD_CTRL), /* IRQ */ - MX6_PAD_SNVS_TAMPER3__GPIO5_IO03 | MUX_PAD_CTRL(TX6_GPIO_OUT_PAD_CTRL), /* RESET */ - MX6_PAD_SNVS_TAMPER8__GPIO5_IO08 | MUX_PAD_CTRL(TX6_GPIO_OUT_PAD_CTRL), /* WAKE */ + MX6_PAD_SNVS_TAMPER2__GPIO5_IO02 | TX6UL_GPIO_IN_PAD_CTRL, /* IRQ */ + MX6_PAD_SNVS_TAMPER3__GPIO5_IO03 | TX6UL_GPIO_OUT_PAD_CTRL, /* RESET */ + MX6_PAD_SNVS_TAMPER8__GPIO5_IO08 | TX6UL_GPIO_OUT_PAD_CTRL, /* WAKE */ /* USBH1 */ - MX6_PAD_GPIO1_IO02__USB_OTG2_PWR | MUX_PAD_CTRL(TX6_GPIO_OUT_PAD_CTRL), /* VBUSEN */ - MX6_PAD_GPIO1_IO03__USB_OTG2_OC | MUX_PAD_CTRL(TX6_GPIO_IN_PAD_CTRL), /* OC */ + MX6_PAD_GPIO1_IO02__USB_OTG2_PWR | TX6UL_GPIO_OUT_PAD_CTRL, /* VBUSEN */ + MX6_PAD_GPIO1_IO03__USB_OTG2_OC | TX6UL_GPIO_IN_PAD_CTRL, /* OC */ /* USBOTG */ - MX6_PAD_UART3_CTS_B__GPIO1_IO26 | MUX_PAD_CTRL(TX6_GPIO_OUT_PAD_CTRL), /* VBUSEN */ - MX6_PAD_UART3_RTS_B__GPIO1_IO27 | MUX_PAD_CTRL(TX6_GPIO_IN_PAD_CTRL), /* OC */ + MX6_PAD_UART3_CTS_B__GPIO1_IO26 | TX6UL_GPIO_OUT_PAD_CTRL, /* VBUSEN */ + MX6_PAD_UART3_RTS_B__GPIO1_IO27 | TX6UL_GPIO_IN_PAD_CTRL, /* OC */ }; static const struct gpio stk5_gpios[] = { @@ -909,11 +905,11 @@ static int lcd_backlight_polarity(void) static const iomux_v3_cfg_t stk5_lcd_pads[] = { #ifdef CONFIG_LCD /* LCD RESET */ - MX6_PAD_LCD_RESET__GPIO3_IO04 | MUX_PAD_CTRL(TX6_GPIO_OUT_PAD_CTRL), + MX6_PAD_LCD_RESET__GPIO3_IO04 | TX6UL_GPIO_OUT_PAD_CTRL, /* LCD POWER_ENABLE */ - MX6_PAD_SNVS_TAMPER4__GPIO5_IO04 | MUX_PAD_CTRL(TX6_GPIO_OUT_PAD_CTRL), + MX6_PAD_SNVS_TAMPER4__GPIO5_IO04 | TX6UL_GPIO_OUT_PAD_CTRL, /* LCD Backlight (PWM) */ - MX6_PAD_NAND_DQS__GPIO4_IO16 | MUX_PAD_CTRL(TX6_GPIO_OUT_PAD_CTRL), + MX6_PAD_NAND_DQS__GPIO4_IO16 | TX6UL_GPIO_OUT_PAD_CTRL, /* Display */ MX6_PAD_LCD_DATA00__LCDIF_DATA00, MX6_PAD_LCD_DATA01__LCDIF_DATA01, @@ -1227,7 +1223,7 @@ static void stk5v5_board_init(void) } imx_iomux_v3_setup_pad(MX6_PAD_LCD_DATA00__GPIO3_IO05 | - MUX_PAD_CTRL(TX6_GPIO_OUT_PAD_CTRL)); + TX6UL_GPIO_OUT_PAD_CTRL); } static void tx6ul_set_cpu_clock(void)