From: Lothar Waßmann Date: Wed, 9 Apr 2014 08:18:28 +0000 (+0200) Subject: arm: mx5: add support for core voltage change when switching clock frequency X-Git-Tag: KARO-TX-2014-04-09~1^2~4 X-Git-Url: https://git.kernelconcepts.de/?p=karo-tx-uboot.git;a=commitdiff_plain;h=f1cd0e93f99e9ff56817d90607286a3d1ea4245c arm: mx5: add support for core voltage change when switching clock frequency --- diff --git a/arch/arm/cpu/armv7/mx5/clock.c b/arch/arm/cpu/armv7/mx5/clock.c index b4db9ab26b..a870b08756 100644 --- a/arch/arm/cpu/armv7/mx5/clock.c +++ b/arch/arm/cpu/armv7/mx5/clock.c @@ -874,11 +874,22 @@ static int config_pll_clk(enum pll_clocks index, struct pll_param *pll_param) return 0; } +static int __adjust_core_voltage_stub(u32 freq) +{ + return 0; +} +int adjust_core_voltage(u32 freq) + __attribute__((weak, alias("__adjust_core_voltage_stub"))); + /* Config CPU clock */ static int config_core_clk(u32 ref, u32 freq) { int ret = 0; struct pll_param pll_param; + u32 cur_freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK); + + if (freq == cur_freq) + return 0; memset(&pll_param, 0, sizeof(struct pll_param)); @@ -890,8 +901,33 @@ static int config_core_clk(u32 ref, u32 freq) ref / 1000000, ref / 1000 % 1000); return ret; } - - return config_pll_clk(PLL1_CLOCK, &pll_param); + if (freq > cur_freq) { + ret = adjust_core_voltage(freq); + if (ret < 0) { + printf("Failed to adjust core voltage for changing ARM clk from %u.%03uMHz to %u.%03uMHz\n", + cur_freq / 1000000, cur_freq / 1000 % 1000, + freq / 1000000, freq / 1000 % 1000); + return ret; + } + ret = config_pll_clk(PLL1_CLOCK, &pll_param); + if (ret) { + adjust_core_voltage(cur_freq); + } + } else { + ret = config_pll_clk(PLL1_CLOCK, &pll_param); + if (ret) { + return ret; + } + ret = adjust_core_voltage(freq); + if (ret < 0) { + printf("Failed to adjust core voltage for changing ARM clk from %u.%03uMHz to %u.%03uMHz\n", + cur_freq / 1000000, cur_freq / 1000 % 1000, + freq / 1000000, freq / 1000 % 1000); + calc_pll_params(ref, cur_freq, &pll_param); + config_pll_clk(PLL1_CLOCK, &pll_param); + } + } + return ret; } static int config_nfc_clk(u32 nfc_clk) diff --git a/arch/arm/include/asm/arch-mx5/clock.h b/arch/arm/include/asm/arch-mx5/clock.h index 1fd3e393f2..6de0077383 100644 --- a/arch/arm/include/asm/arch-mx5/clock.h +++ b/arch/arm/include/asm/arch-mx5/clock.h @@ -92,6 +92,7 @@ u32 imx_get_uartclk(void); u32 imx_get_fecclk(void); unsigned int mxc_get_clock(enum mxc_clock clk); int mxc_set_clock(u32 ref, u32 freq, enum mxc_clock clk); +int adjust_core_voltage(u32 freq); void set_usb_phy_clk(void); void enable_usb_phy1_clk(unsigned char enable); void enable_usb_phy2_clk(unsigned char enable); diff --git a/board/karo/tx53/tx53.c b/board/karo/tx53/tx53.c index 3c01687085..e877b2c44c 100644 --- a/board/karo/tx53/tx53.c +++ b/board/karo/tx53/tx53.c @@ -189,6 +189,8 @@ static void tx53_print_cpuinfo(void) enum LTC3589_REGS { LTC3589_SCR1 = 0x07, + LTC3589_SCR2 = 0x12, + LTC3589_VCCR = 0x20, LTC3589_CLIRQ = 0x21, LTC3589_B1DTV1 = 0x23, LTC3589_B1DTV2 = 0x24, @@ -201,12 +203,15 @@ enum LTC3589_REGS { LTC3589_L2DTV2 = 0x33, }; -#define LTC3589_PGOOD_MASK (1 << 5) +#define LTC3589_BnDTV1_PGOOD_MASK (1 << 5) +#define LTC3589_BnDTV1_SLEW(n) (((n) & 3) << 6) -#define LTC3589_CLK_RATE_LOW (1 << 5) +#define LTC3589_CLK_RATE_LOW (1 << 5) + +#define LTC3589_SCR2_PGOOD_SHUTDWN (1 << 7) #define VDD_LDO2_VAL mV_to_regval(vout_to_vref(1325 * 10, 2)) -#define VDD_CORE_VAL mV_to_regval(vout_to_vref(1240 * 10, 3)) +#define VDD_CORE_VAL mV_to_regval(vout_to_vref(1100 * 10, 3)) #define VDD_SOC_VAL mV_to_regval(vout_to_vref(1325 * 10, 4)) #define VDD_BUCK3_VAL mV_to_regval(vout_to_vref(2500 * 10, 5)) @@ -250,19 +255,23 @@ static struct pmic_regs { u8 val; } ltc3589_regs[] = { { LTC3589_SCR1, 0x15, }, /* burst mode for all regulators except buck boost */ + { LTC3589_SCR2, LTC3589_SCR2_PGOOD_SHUTDWN, }, /* enable shutdown on PGOOD Timeout */ - { LTC3589_L2DTV1, VDD_LDO2_VAL | LTC3589_PGOOD_MASK, }, + { LTC3589_L2DTV1, VDD_LDO2_VAL | LTC3589_BnDTV1_SLEW(3) | LTC3589_BnDTV1_PGOOD_MASK, }, { LTC3589_L2DTV2, VDD_LDO2_VAL | LTC3589_CLK_RATE_LOW, }, - { LTC3589_B1DTV1, VDD_CORE_VAL | LTC3589_PGOOD_MASK, }, + { LTC3589_B1DTV1, VDD_CORE_VAL | LTC3589_BnDTV1_SLEW(3) | LTC3589_BnDTV1_PGOOD_MASK, }, { LTC3589_B1DTV2, VDD_CORE_VAL, }, - { LTC3589_B2DTV1, VDD_SOC_VAL | LTC3589_PGOOD_MASK, }, + { LTC3589_B2DTV1, VDD_SOC_VAL | LTC3589_BnDTV1_SLEW(3) | LTC3589_BnDTV1_PGOOD_MASK, }, { LTC3589_B2DTV2, VDD_SOC_VAL, }, - { LTC3589_B3DTV1, VDD_BUCK3_VAL | LTC3589_PGOOD_MASK, }, + { LTC3589_B3DTV1, VDD_BUCK3_VAL | LTC3589_BnDTV1_SLEW(3) | LTC3589_BnDTV1_PGOOD_MASK, }, { LTC3589_B3DTV2, VDD_BUCK3_VAL, }, + /* Select ref 0 for all regulators and enable slew */ + { LTC3589_VCCR, 0x55, }, + { LTC3589_CLIRQ, 0, }, /* clear all interrupt flags */ }; @@ -305,6 +314,94 @@ static int setup_pmic_voltages(void) return 0; } +static struct { + u32 max_freq; + u32 mV; +} tx53_core_voltages[] = { + { 800000000, 1100, }, + { 1000000000, 1240, }, + { 1200000000, 1350, }, +}; + +int adjust_core_voltage(u32 freq) +{ + int ret; + int i; + + printf("%s@%d\n", __func__, __LINE__); + + for (i = 0; i < ARRAY_SIZE(tx53_core_voltages); i++) { + if (freq <= tx53_core_voltages[i].max_freq) { + int retries = 0; + const int max_tries = 10; + const int delay_us = 1; + u32 mV = tx53_core_voltages[i].mV; + u8 val = mV_to_regval(vout_to_vref(mV * 10, 3)); + u8 v; + + printf("regval[%umV]=%02x\n", mV, val); + + ret = i2c_read(CONFIG_SYS_I2C_SLAVE, LTC3589_B1DTV1, 1, + &v, 1); + if (ret) { + printf("%s: failed to read PMIC register %02x: %d\n", + __func__, LTC3589_B1DTV1, ret); + return ret; + } + printf("Changing reg %02x from %02x to %02x\n", + LTC3589_B1DTV1, v, (v & ~0x1f) | + mV_to_regval(vout_to_vref(mV * 10, 3))); + v &= ~0x1f; + v |= mV_to_regval(vout_to_vref(mV * 10, 3)); + ret = i2c_write(CONFIG_SYS_I2C_SLAVE, LTC3589_B1DTV1, 1, + &v, 1); + if (ret) { + printf("%s: failed to write PMIC register %02x: %d\n", + __func__, LTC3589_B1DTV1, ret); + return ret; + } + ret = i2c_read(CONFIG_SYS_I2C_SLAVE, LTC3589_VCCR, 1, + &v, 1); + if (ret) { + printf("%s: failed to read PMIC register %02x: %d\n", + __func__, LTC3589_VCCR, ret); + return ret; + } + v |= 0x1; + ret = i2c_write(CONFIG_SYS_I2C_SLAVE, LTC3589_VCCR, 1, + &v, 1); + if (ret) { + printf("%s: failed to write PMIC register %02x: %d\n", + __func__, LTC3589_VCCR, ret); + return ret; + } + for (retries = 0; retries < max_tries; retries++) { + ret = i2c_read(CONFIG_SYS_I2C_SLAVE, + LTC3589_VCCR, 1, &v, 1); + if (ret) { + printf("%s: failed to read PMIC register %02x: %d\n", + __func__, LTC3589_VCCR, ret); + return ret; + } + if (!(v & 1)) + break; + udelay(delay_us); + } + if (v & 1) { + printf("change of VDDCORE did not complete after %uµs\n", + retries * delay_us); + return -ETIMEDOUT; + } + + printf("VDDCORE set to %umV after %u loops\n", + DIV_ROUND(vref_to_vout(regval_to_mV(val & 0x1f), 3), + 10), retries); + return 0; + } + } + return -EINVAL; +} + int board_early_init_f(void) { struct mxc_ccm_reg *ccm_regs = (void *)CCM_BASE_ADDR;