karo-tx-uboot.git
6 years agoarm: ti: Increase malloc size to 16MB for armv7 boards
Simon Glass [Tue, 3 Jun 2014 04:04:54 +0000 (22:04 -0600)]
arm: ti: Increase malloc size to 16MB for armv7 boards

The current size of 1MB is not enough use to use DFU. Increase it for
ARMv7 boards, all of which should have 32MB or more SDRAM.

With this change it is possible to do 'dfu mmc 0' on a Beaglebone Black.

Signed-off-by: Simon Glass <sjg@chromium.org>
6 years agomkimage: Automatically make space in FDT when full
Simon Glass [Tue, 3 Jun 2014 04:04:53 +0000 (22:04 -0600)]
mkimage: Automatically make space in FDT when full

When adding hashes or signatures, the target FDT may be full. Detect this
and automatically try again after making 1KB of space.

Signed-off-by: Simon Glass <sjg@chromium.org>
6 years agoImprove error handling in fit_common
Simon Glass [Tue, 3 Jun 2014 04:04:52 +0000 (22:04 -0600)]
Improve error handling in fit_common

Make the error handling common, and make sure the file is always closed
on error. Rename the parameter to be more description and add comments.

Signed-off-by: Simon Glass <sjg@chromium.org>
6 years agofdt: Update functions which write to an FDT to return -ENOSPC
Simon Glass [Tue, 3 Jun 2014 04:04:51 +0000 (22:04 -0600)]
fdt: Update functions which write to an FDT to return -ENOSPC

When writing values into an FDT it is possible that there will be
insufficient space. If the caller gets a useful error then it can
potentially deal with the situation.

Adjust these functions to return -ENOSPC when the FDT is full.

Signed-off-by: Simon Glass <sjg@chromium.org>
6 years agofdt: Add DEV_TREE_BIN option to specify a device tree binary file
Simon Glass [Tue, 3 Jun 2014 04:04:50 +0000 (22:04 -0600)]
fdt: Add DEV_TREE_BIN option to specify a device tree binary file

In some cases, an externally-built device tree binary is required to be
attached to U-Boot. An example is when using image signing, since in that
case the .dtb file must include the public keys.

Add a DEV_TREE_BIN option to the Makefile, and update the documentation.

Usage is something like:

make DEV_TREE_BIN=boot/am335x-boneblack-pubkey.dtb

Signed-off-by: Simon Glass <sjg@chromium.org>
6 years agohash: Export the function to show a hash
Simon Glass [Tue, 3 Jun 2014 04:04:49 +0000 (22:04 -0600)]
hash: Export the function to show a hash

This function is useful for displaying a hash value, so export it.

Signed-off-by: Simon Glass <sjg@chromium.org>
6 years agoam33xx/omap: Allow cache enable for all Sitara/OMAP
Simon Glass [Tue, 3 Jun 2014 04:04:48 +0000 (22:04 -0600)]
am33xx/omap: Allow cache enable for all Sitara/OMAP

Enable the cache for all devices, unless CONFIG_SYS_DCACHE_OFF is defined.
This speeds up the Beaglebone Black boot considerable.

(Tested only on Beaglebone Black with SD card boot)

Signed-off-by: Simon Glass <sjg@chromium.org>
6 years agoCheck that u-boot.bin size looks correct
Simon Glass [Tue, 3 Jun 2014 04:04:47 +0000 (22:04 -0600)]
Check that u-boot.bin size looks correct

Check that the image size matches the size we get from u-boot.bin. If it
doesn't, that generally means that some extra sections are being added to
u-boot.bin, meaning that it is not possible to access data appended to
the U-Boot binary. This is used for device tree, so needs to work.

This problem was introduced by commit b02bfc4. By adding a test we can
prevent a reccurence.

Signed-off-by: Simon Glass <sjg@chromium.org>
6 years agomx31ads: Fix the U-Boot binary output
Simon Glass [Tue, 3 Jun 2014 04:04:46 +0000 (22:04 -0600)]
mx31ads: Fix the U-Boot binary output

Correct the binary output so that image_binary_size is really at the
end of the image.

Signed-off-by: Simon Glass <sjg@chromium.org>
6 years agocm_t335: Fix the U-Boot binary output
Simon Glass [Tue, 3 Jun 2014 04:04:45 +0000 (22:04 -0600)]
cm_t335: Fix the U-Boot binary output

Correct the binary output so that image_binary_size is really at the
end of the image.

Signed-off-by: Simon Glass <sjg@chromium.org>
6 years agoti: am335x: Fix the U-Boot binary output
Simon Glass [Tue, 3 Jun 2014 04:04:44 +0000 (22:04 -0600)]
ti: am335x: Fix the U-Boot binary output

This should include the hash so that image_binary_size is really at the
end of the image, and not some 300 bytes earlier.

Signed-off-by: Simon Glass <sjg@chromium.org>
6 years agotools: include u-boot version of sha256.h
Jeroen Hofstee [Fri, 30 May 2014 13:45:28 +0000 (15:45 +0200)]
tools: include u-boot version of sha256.h

When building tools the u-boot specific sha256.h is required, but the
host version of sha256.h is used when present. This leads to build errors
on FreeBSD which does have a system sha256.h include. Like libfdt_env.h
explicitly include u-boot's sha256.h.

cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
Acked-by: Simon Glass <sjg@chromium.org>
6 years agoMakefile: fix clang warnings due to clang support
Jeroen Hofstee [Fri, 30 May 2014 13:45:27 +0000 (15:45 +0200)]
Makefile: fix clang warnings due to clang support

Building u-boot tools with clang as a host compiler e.g. on
FreeBSD with `gmake HOSTCC=clang CONFIG_USE_PRIVATE_LIBGCC=y tools`
leads to many warnings [1] for every compiler invocation since
commit 598e2d33. Part of mentioned commit imports linux patches:

 - kbuild: LLVMLinux: Adapt warnings for compilation with clang
 - kbuild: LLVMLinux: Add Kbuild support for building kernel with Clang

No version of clang supports the gcc fno-delete-null-pointer-checks
though, but it is only passed to clang. Gcc does not have the clang
specific Qunused-arguments for the target. Furthermore several
warnings are disabled which aren't encountered in u-boot. Since such
a build has worked for quite some time and works after removing these
changes, just remove the clang specific handling to restore normal
building with clang as hostcc.

[1] Actual warnings
-------------------
  GEN     include/autoconf.mk.dep
arm-freebsd-gcc: unrecognized option '-Qunused-arguments'

  HOSTCC  scripts/basic/fixdep
clang: warning: argument unused during compilation:
                '-fno-delete-null-pointer-checks'

cc: Masahiro Yamada <yamada.m@jp.panasonic.com>
Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
6 years agoMerge branch 'master' of git://git.denx.de/u-boot-spi
Tom Rini [Wed, 11 Jun 2014 15:40:11 +0000 (11:40 -0400)]
Merge branch 'master' of git://git.denx.de/u-boot-spi

6 years agoMerge branch 'master' of git://git.denx.de/u-boot-usb
Tom Rini [Wed, 11 Jun 2014 00:37:00 +0000 (20:37 -0400)]
Merge branch 'master' of git://git.denx.de/u-boot-usb

6 years agodfu: Disable default calculation of CRC32
Lukasz Majewski [Tue, 10 Jun 2014 10:25:59 +0000 (12:25 +0200)]
dfu: Disable default calculation of CRC32

Patch (SHA1: bd694244db7bc969954)
dfu: Introduction of the "dfu_hash_algo" env variable for checksum method
setting

already introduced more generic handling of the crc32 calculation.
Up till now the CRC32 of received data was calculated unconditionally.
This patch changes this and from now - by default the crc32 is NOT
calculated anymore.

Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
Cc: Marek Vasut <marex@denx.de>
6 years agousb: ci_udc: terminate ep0 INs with a zlp when required
Stephen Warren [Tue, 10 Jun 2014 21:27:39 +0000 (15:27 -0600)]
usb: ci_udc: terminate ep0 INs with a zlp when required

Sometimes, a zero-length packet is required at the end of an IN
transaction so that the host knows the device is done sending data.
Enhance ci_udc to send a zlp when necessary. See the comments for
more details.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
6 years agousb: ci_udc: clean up all allocations in unregister
Stephen Warren [Tue, 10 Jun 2014 17:02:38 +0000 (11:02 -0600)]
usb: ci_udc: clean up all allocations in unregister

usb_gadget_unregister_driver() is called to tear down the USB device mode
stack. Fix the driver to stop the USB HW (which causes any attached host
to notice the disappearance of the device), and free all allocations
(which obviously prevents memory leaks).

Signed-off-by: Stephen Warren <swarren@nvidia.com>
6 years agousb: ci_udc: fix probe error cleanup
Stephen Warren [Tue, 10 Jun 2014 17:02:37 +0000 (11:02 -0600)]
usb: ci_udc: fix probe error cleanup

If allocation of the ep0 req fails, clean up all the allocations that
were made in ci_udc_probe().

Signed-off-by: Stephen Warren <swarren@nvidia.com>
6 years agousb: ci_udc: fix freeing of ep0 req
Stephen Warren [Tue, 10 Jun 2014 17:02:36 +0000 (11:02 -0600)]
usb: ci_udc: fix freeing of ep0 req

ci_ep_alloc_request() avoids allocating multiple request objects for ep0
by keeping a record of the first req allocated for ep0, and always
returning that instead of allocating a new req. However, if this req is
ever freed, the record of the previous allocation is not cleared, so
ci_ep_alloc_request() will keep returning this stale pointer. Fix
ci_ep_free_request() to clear the record of the previous allocation.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
6 years agousb: ci_udc: call udc_disconnect() from ci_pullup()
Stephen Warren [Tue, 10 Jun 2014 17:02:35 +0000 (11:02 -0600)]
usb: ci_udc: call udc_disconnect() from ci_pullup()

ci_pullup()'s !is_on path contains a cut/paste copy of udc_disconnect().
Remove the duplication by simply calling udc_disconnect() instead.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
6 years agoPrepare v2014.07-rc3 v2014.07-rc3
Tom Rini [Tue, 10 Jun 2014 15:55:44 +0000 (11:55 -0400)]
Prepare v2014.07-rc3

Signed-off-by: Tom Rini <trini@ti.com>
6 years agonet: sh-eth: Fix typo from rESR_RTLF to EESR_RTLF
Nobuhiro Iwamatsu [Wed, 22 Jan 2014 22:52:20 +0000 (07:52 +0900)]
net: sh-eth: Fix typo from rESR_RTLF to EESR_RTLF

'r' of rESR_RTLF is a mistake of E.

Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
6 years agonet: sh-eth: Fix coding style
Nobuhiro Iwamatsu [Wed, 22 Jan 2014 22:52:19 +0000 (07:52 +0900)]
net: sh-eth: Fix coding style

This fixes checkpatch's warning.

Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
6 years agonet: sh-eth: Add support R7S72100 of rmobile
Nobuhiro Iwamatsu [Wed, 22 Jan 2014 22:52:18 +0000 (07:52 +0900)]
net: sh-eth: Add support R7S72100 of rmobile

The R7S72100 of ARM SoC that Renesas manufactured has one Ether port.
This has the same IP SH-Ether. This patch adds support of the R7S72100
in SH-Ether.

Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
6 years agosf: probe: Fix quad bit set path
Poddar, Sourav [Wed, 23 Apr 2014 13:27:03 +0000 (18:57 +0530)]
sf: probe: Fix quad bit set path

Currently, flash quad bit is set in "spi_flash_validate_params" and later
at the end in the same api, we write 0 to status register for few flashes,
thereby overriding the quad bit set. This fix moves the quad bit setting
outside this api in "spi_flash_probe_slave"

Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
6 years agospi: soft_spi: Support NULL din/dout buffers
Andrew Ruder [Thu, 24 Apr 2014 18:39:32 +0000 (13:39 -0500)]
spi: soft_spi: Support NULL din/dout buffers

This mirrors the conventions used in other SPI drivers (kirkwood,
davinci, atmel, et al) where the din/dout buffer can be NULL when the
received/transmitted data isn't important.  This reduces the need for
allocating additional buffers when write-only/read-only functionality is
needed.

In the din == NULL case, the received data is simply not stored.  In the
dout == NULL case, zeroes are transmitted.

Signed-off-by: Andrew Ruder <andrew.ruder@elecsyscorp.com>
Cc: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
6 years agosf: params: Added support for Spansion S25FL512S_512K
Siva Durga Prasad Paladugu [Fri, 25 Apr 2014 13:47:13 +0000 (15:47 +0200)]
sf: params: Added support for Spansion S25FL512S_512K

Added support for Spansion chip "S25FL512S_512K".

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
6 years agoMerge branch 'master' of git://git.denx.de/u-boot-arm
Tom Rini [Sun, 8 Jun 2014 11:58:41 +0000 (07:58 -0400)]
Merge branch 'master' of git://git.denx.de/u-boot-arm

6 years agoMerge branch 'u-boot-ti/master' into 'u-boot-arm/master'
Albert ARIBAUD [Sun, 8 Jun 2014 07:14:19 +0000 (09:14 +0200)]
Merge branch 'u-boot-ti/master' into 'u-boot-arm/master'

6 years agoarm:am43xx: Add TPS65218 support to scale voltages up
Tom Rini [Thu, 5 Jun 2014 15:15:30 +0000 (11:15 -0400)]
arm:am43xx: Add TPS65218 support to scale voltages up

This family is supported by the TPS65218 PMIC.  Implement a scale_vcores
to set the MPU and CORE voltage correctly to the max frequency that is
supported (and what we will be scaling them to in setup_dplls()).

Signed-off-by: Tom Rini <trini@ti.com>
6 years agopower: Add support for the TPS65218 PMIC
Tom Rini [Thu, 5 Jun 2014 15:15:29 +0000 (11:15 -0400)]
power: Add support for the TPS65218 PMIC

Add a driver for the TPS65218 PMIC which is used by TI AM43xx SoCs and
may be used by TI AM335x SoCs.

Signed-off-by: Tom Rini <trini@ti.com>
6 years agoarm:am33xx: Add a scale_vcores() hook
Tom Rini [Thu, 5 Jun 2014 15:15:28 +0000 (11:15 -0400)]
arm:am33xx: Add a scale_vcores() hook

Similar to OMAP4/5 we need to scale the voltage up prior to changing the
clock frequencies up higher.  Add a similar hook to start with.

Signed-off-by: Tom Rini <trini@ti.com>
6 years agoam43xx: Only read the MPU frequency bits of CTRL_DEV_ATTR
Tom Rini [Thu, 5 Jun 2014 15:15:27 +0000 (11:15 -0400)]
am43xx: Only read the MPU frequency bits of CTRL_DEV_ATTR

Signed-off-by: Tom Rini <trini@ti.com>
6 years agoboard/BuR/tseries: cosmetic changes
Hannes Petermaier [Wed, 4 Jun 2014 08:37:12 +0000 (10:37 +0200)]
board/BuR/tseries: cosmetic changes

Cc: trini@ti.com
Signed-off-by: Hannes Petermaier <oe5hpm@oevsv.at>
6 years agoboard/BuR/common: Add CONFIG_CMD_I2C
Hannes Petermaier [Wed, 4 Jun 2014 08:28:39 +0000 (10:28 +0200)]
board/BuR/common: Add CONFIG_CMD_I2C

in almost all cases we need the i2c commands within the u-boot shell.
So we enable them within the common section.

Cc: trini@ti.com
Signed-off-by: Hannes Petermaier <oe5hpm@oevsv.at>
6 years agoboard/BuR/tseries: only run gpmc_init(...) in NAND-build
Hannes Petermaier [Wed, 4 Jun 2014 08:26:29 +0000 (10:26 +0200)]
board/BuR/tseries: only run gpmc_init(...) in NAND-build

if we have no NAND-Chip, we don't need the gpmc-controller and therefore
is no need to init it.

Cc: trini@ti.com
Signed-off-by: Hannes Petermaier <oe5hpm@oevsv.at>
6 years agoboard/BuR/tseries: Add support for using 8-bit on eMMC
Hannes Petermaier [Wed, 4 Jun 2014 08:25:32 +0000 (10:25 +0200)]
board/BuR/tseries: Add support for using 8-bit on eMMC

Cc: trini@ti.com
Signed-off-by: Hannes Petermaier <oe5hpm@oevsv.at>
6 years agoboard/BuR/common: introduce usage of CONFIG_SYS_GENERIC_BOARD
Hannes Petermaier [Wed, 4 Jun 2014 08:22:07 +0000 (10:22 +0200)]
board/BuR/common: introduce usage of CONFIG_SYS_GENERIC_BOARD

Signed-off-by: Hannes Petermaier <oe5hpm@oevsv.at>
6 years agoarch-am33xx: Add defines for timer0-7
Hannes Petermaier [Wed, 4 Jun 2014 08:19:26 +0000 (10:19 +0200)]
arch-am33xx: Add defines for timer0-7

For usage of timer6 within B&R we need this defines to enable clock
modules and clk-source.

Also the 'Timer register bits' are expanded.

By the way we add defines for all timers within AM335x SoC.

Cc: trini@ti.com
Signed-off-by: Hannes Petermaier <oe5hpm@oevsv.at>
6 years agoARM: AM43xx: Fix UART clocks enabling
Lokesh Vutla [Mon, 2 Jun 2014 05:19:03 +0000 (10:49 +0530)]
ARM: AM43xx: Fix UART clocks enabling

After enabling a module, SW has to wait on IDLEST bit
until it is Fully functional. This wait is missing for UART module
and there is a immediate access of UART registers after this. So there
is a chance of hang on this module( This can happen when we are running
from MPU SRAM). So waiting for IDLEST bit.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
6 years agoARM: AM43xx: Fix mmcboot command in EXTRA_ENV_SETTINGS
Lokesh Vutla [Mon, 2 Jun 2014 05:15:38 +0000 (10:45 +0530)]
ARM: AM43xx: Fix mmcboot command in EXTRA_ENV_SETTINGS

loadbootenv expects devtype variable to be set. This is missing in
mmcboot command. With this the following error comes:
U-Boot# run mmcboot
mmc0 is current device
SD/MMC found on device 0
** Bad device usb 0 **
** Bad device usb 0 **
Fixing this by setting devtype as mmc.

Reported-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
6 years agotam3517: fix NAND detection
Jeroen Hofstee [Sat, 31 May 2014 15:08:30 +0000 (17:08 +0200)]
tam3517: fix NAND detection

commit a0a37183bd7 "ARM: omap: merge GPMC initialization code for
all platform" needs CONFIG_NOR, CONFIG_NAND or CONFIG_CMD_ONENAND
to be set to access flash. Add CONFIG_NAND for tam3517 derived
boards to prevent the following error: "nand: error: Unable to
find NAND settings in GPMC Configuration - quitting"

cc: Stefano Babic <sbabic@denx.de>
Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
6 years agokeystone: k2hk: enable support of nand ecclayout command
WingMan Kwok [Thu, 29 May 2014 15:58:16 +0000 (18:58 +0300)]
keystone: k2hk: enable support of nand ecclayout command

Enable support of nand ecclayout command.

Acked-By: Murali Karicheri <m-karicheri2@ti.com>
Acked-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: WingMan Kwok <w-kwok2@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
6 years agokeystone: init: enable UART1 to be able use it from kernel
Murali Karicheri [Thu, 29 May 2014 15:57:12 +0000 (18:57 +0300)]
keystone: init: enable UART1 to be able use it from kernel

Currently PWREMU_MGMT is not configured in the Linux generic UART
driver as this register seems to be specific TI UART IP. So this
needs to be enabled in u-boot to use UART1 from kernel space.

Acked-By: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
6 years agoarm:am33xx: Rework s_init and add board_early_init_f
Tom Rini [Wed, 21 May 2014 16:57:22 +0000 (12:57 -0400)]
arm:am33xx: Rework s_init and add board_early_init_f

With the changes to the i2c framework (and adopting the omap24xx_i2c
driver to them) we can no longer call i2c functions prior to gd having
been set and cleared.  When SPL booting, this is handled by setting gd
to point to SRAM in s_init.  However in the cases where we are loaded
directly by ROM (memory mapped NOR or QSPI) we need to make use of the
normal hooks to slightly delay these calls.

Signed-off-by: Tom Rini <trini@ti.com>
6 years agoarm:am33xx: Make dram_init call sdram_init() in some contexts
Tom Rini [Wed, 21 May 2014 16:57:21 +0000 (12:57 -0400)]
arm:am33xx: Make dram_init call sdram_init() in some contexts

We have two contexts for booting these platforms.  One is SPL which is
roughly: reset, cpu_init_crit, lowlevel_init, s_init, sdram_init, _main,
board_init_f from SPL, ... then U-Boot loads.  The other is a
memory-mapped XIP case (NOR or QSPI) where we do not run an SPL.  In
this case we go, roughly: reset, cpu_init_crit, lowlevel_init, s_init,
_main, regular board_init_f.

In the first case s_init will set a valid gd and then be able to call
sdram_init which in many cases will need i2c (which needs a valid gd for
gd->cur_i2c_bus).  In this second case we must (and are able to and
should) defer sdram_init() into dram_init() called by board_init_f as gd
will have been set in _main and cleared in board_init_f.

Signed-off-by: Tom Rini <trini@ti.com>
6 years agoti: qspi: populate slave device to set flash quad bit.
Sourav Poddar [Mon, 19 May 2014 20:53:38 +0000 (16:53 -0400)]
ti: qspi: populate slave device to set flash quad bit.

The patch populates the slave data which will be used by flash driver to
set the  flash quad enable bit.

Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
6 years agoam43xx_evm: Add qspiboot target
Sourav Poddar [Mon, 19 May 2014 20:53:37 +0000 (16:53 -0400)]
am43xx_evm: Add qspiboot target

The ePOS EVM and EVM SK have QSPI as an option to boot.  Add a qspiboot
target that utilizes QSPI for env and so forth as an example of best
practices.  As QSPI is booted from directly we need to chang
CONFIG_SYS_TEXT_BASE.

Note that on ePOS EVM the QSPI and NAND are mutually exclusive choices
we need to handle that elsewhere, once NAND support is also added.

Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
Signed-off-by: Tom Rini <trini@ti.com>
6 years agoam335x: update README for BCH16
pekon gupta [Mon, 2 Jun 2014 11:44:43 +0000 (17:14 +0530)]
am335x: update README for BCH16

updates documentation with explanation on how to select ECC schemes.

Signed-off-by: Pekon Gupta <pekon@ti.com>
6 years agomtd: nand: omap: add support for BCH16_ECC - NAND driver updates
pekon gupta [Mon, 2 Jun 2014 11:44:42 +0000 (17:14 +0530)]
mtd: nand: omap: add support for BCH16_ECC - NAND driver updates

This patch add support for BCH16_ECC to omap_gpmc driver.

*need to BCH16 ECC scheme*
With newer SLC Flash technologies and MLC NAND, and large densities, pagesizes
Flash devices have become more suspectible to bit-flips. Thus stronger
ECC schemes are required for protecting the data.
But stronger ECC schemes have come with larger-sized ECC syndromes which require
more space in OOB/Spare. This puts constrains like;
(a) BCH16_ECC can correct 16 bit-flips per 512Bytes of data.
(b) BCH16_ECC generates 26-bytes of ECC syndrome / 512B.
Due to (b) this scheme can only be used with NAND devices which have enough
OOB to satisfy following equation:
OOBsize per page >= 26 * (page-size / 512)

Signed-off-by: Pekon Gupta <pekon@ti.com>
6 years agomtd: nand: omap_gpmc: use macro for register definitions
pekon gupta [Mon, 2 Jun 2014 11:44:41 +0000 (17:14 +0530)]
mtd: nand: omap_gpmc: use macro for register definitions

GPMC can support simultaneous processing of 8 512Byte data chunks, in parallel

Signed-off-by: Pekon Gupta <pekon@ti.com>
6 years agoomap3: remove remnant macros GPMC_NAND_ECC_LP_x8_LAYOUT and GPMC_NAND_ECC_LP_x16_LAYOUT
pekon gupta [Mon, 5 May 2014 19:16:20 +0000 (00:46 +0530)]
omap3: remove remnant macros GPMC_NAND_ECC_LP_x8_LAYOUT and GPMC_NAND_ECC_LP_x16_LAYOUT

OMAP3 used GPMC_NAND_ECC_LP_x8_LAYOUT and GPMC_NAND_ECC_LP_x16_LAYOUT macros
to configure GPMC controller for x7 or x8 bit device connected to its interface.
Now this information is encoded in CONFIG_SYS_NAND_DEVICE_WIDTH macro, so above
macros can be completely removed.

Signed-off-by: Pekon Gupta <pekon@ti.com>
6 years agomtd: nand: omap: add CONFIG_SYS_NAND_BUSWIDTH_16BIT to indicate NAND device bus-width
pekon gupta [Mon, 5 May 2014 19:16:19 +0000 (00:46 +0530)]
mtd: nand: omap: add CONFIG_SYS_NAND_BUSWIDTH_16BIT to indicate NAND device bus-width

GPMC controller needs to be configured based on bus-width of the NAND device
connected to it. Also, dynamic detection of NAND bus-width from on-chip ONFI
parameters is not possible in following situations:
SPL:    SPL NAND drivers does not support ONFI parameter reading.
U-boot: GPMC controller iniitalization is done in omap_gpmc.c:board_nand_init()
        which is called before probing for devices, hence any ONFI parameter
        information is not available during GPMC initialization.

Thus, OMAP NAND driver expected board developers to explicitely write GPMC
configurations specific to NAND device attached on board in board files itself.
But this was troublesome for board manufacturers as they need to dive into
lengthy platform & SoC documents to find details of GPMC registers and
appropriate configurations to get NAND device working.

This patch instead adds existing CONFIG_SYS_NAND_BUSWIDTH_16BIT to board config
hich indicates that connected NAND device has x16 bus-width. And then based on
this config GPMC driver itself initializes itself based on NAND bus-width. This
keeps board developers free from knowing GPMC controller specific internals.

Signed-off-by: Pekon Gupta <pekon@ti.com>
6 years agomtd: nand: fix GET/SET_FEATURES address on 16-bit devices
David Mosberger [Mon, 5 May 2014 19:16:18 +0000 (00:46 +0530)]
mtd: nand: fix GET/SET_FEATURES address on 16-bit devices

As per following Sections in ONFI Spec, GET_FEATURES and SET_FEATURES also need
byte-addressing on 16-bit devices.

*Section: Target Initialization"
"The Read ID and Read Parameter Page commands only use the lower 8-bits of the
 data bus. The host shall not issue commands that use a word data width on x16
 devices until the host determines the device supports a 16-bit data bus width
 in the parameter page."

*Section: Bus Width Requirements*
"When the host supports a 16-bit bus width, only data is transferred at the
 16-bit width. All address and command line transfers shall use only the lower
 8-bits of the data bus. During command transfers, the host may place any value
 on the upper 8-bits of the data bus. During address transfers, the host shall
 set the upper 8-bits of the data bus to 00h."

So porting following commit from linux kernel
    commit e34fcb07a6d57411de6e15a47724fbe92c5caa42
    Author: David Mosberger <davidm@egauge.net>  (preserving authorship)
    mtd: nand: fix GET/SET_FEATURES address on 16-bit devices

Signed-off-by: Pekon Gupta <pekon@ti.com>
6 years agomtd: nand: force NAND_CMD_READID onto 8-bit bus
Brian Norris [Mon, 5 May 2014 19:16:17 +0000 (00:46 +0530)]
mtd: nand: force NAND_CMD_READID onto 8-bit bus

As per following Sections in ONFI Spec, NAND_CMD_READID should use only
lower 8-bit for transfering command, address and data even on x16 NAND device.

*Section: Target Initialization"
"The Read ID and Read Parameter Page commands only use the lower 8-bits of the
 data bus. The host shall not issue commands that use a word data width on x16
 devices until the host determines the device supports a 16-bit data bus width
 in the parameter page."

*Section: Bus Width Requirements*
"When the host supports a 16-bit bus width, only data is transferred at the
 16-bit width. All address and command line transfers shall use only the lower
 8-bits of the data bus. During command transfers, the host may place any value
 on the upper 8-bits of the data bus. During address transfers, the host shall
 set the upper 8-bits of the data bus to 00h."

Thus porting  following commit from linux-kernel to ensure that column address
is not altered to align to x16 bus when issuing NAND_CMD_READID command.

    commit 3dad2344e92c6e1aeae42df1c4824f307c51bcc7
    mtd: nand: force NAND_CMD_READID onto 8-bit bus
    Author: Brian Norris <computersforpeace@gmail.com> (preserving authorship)

    The NAND command helpers tend to automatically shift the column address
    for x16 bus devices, since most commands expect a word address, not a
    byte address. The Read ID command, however, expects an 8-bit address
    (i.e., 0x00, 0x20, or 0x40 should not be translated to 0x00, 0x10, or
    0x20).

    This fixes the column address for a few drivers which imitate the
    nand_base defaults.

Signed-off-by: Pekon Gupta <pekon@ti.com>
6 years agomtd: nand: don't use read_buf for 8-bit ONFI transfers
Brian Norris [Mon, 5 May 2014 19:16:16 +0000 (00:46 +0530)]
mtd: nand: don't use read_buf for 8-bit ONFI transfers

Porting below commit from linux-tree, preserving original authorship & commit log
commit bd9c6e99b58255b9de1982711ac9487c9a2f18be
Author:     Brian Norris <computersforpeace@gmail.com>
mtd: nand: don't use read_buf for 8-bit ONFI transfers

  Use a repeated read_byte() instead of read_buf(), since for x16 buswidth
  devices, we need to avoid the upper I/O[16:9] bits. See the following
  commit for reference:

  commit 05f7835975dad6b3b517f9e23415985e648fb875 (from linux-tree)
  Author: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
  Date:   Thu Dec 5 22:22:04 2013 +0100

      mtd: nand: don't use {read,write}_buf for 8-bit transfers

  Now, I think that all barriers to probing ONFI on x16 devices are
  removed, so remove the check from nand_flash_detect_onfi().

Signed-off-by: Pekon Gupta <pekon@ti.com>
6 years agomtd: nand: omap: fix error-codes returned from omap-elm driver
pekon gupta [Fri, 11 Apr 2014 07:25:35 +0000 (12:55 +0530)]
mtd: nand: omap: fix error-codes returned from omap-elm driver

This patch
 omap-elm.c: replaces -ve integer value returned during errorneous condition,
             with proper error-codes.
 omap-gpmc.c: updates omap-gpmc driver to pass error-codes returned from
             omap-elm driver to upper layers

Signed-off-by: Pekon Gupta <pekon@ti.com>
Reviewed-by: Stefan Roese <sr@denx.de>
6 years agomtd: nand: omap_gpmc: minor cleanup of omap_correct_data_bch
pekon gupta [Fri, 11 Apr 2014 07:25:34 +0000 (12:55 +0530)]
mtd: nand: omap_gpmc: minor cleanup of omap_correct_data_bch

This patch tries to avoid some local pointer dereferences, by using common
local variables in omap_correct_data_bch()

Signed-off-by: Pekon Gupta <pekon@ti.com>
Reviewed-by: Stefan Roese <sr@denx.de>
6 years agomtd: nand: omap_gpmc: rename struct nand_bch_priv to struct omap_nand_info
pekon gupta [Fri, 11 Apr 2014 07:25:33 +0000 (12:55 +0530)]
mtd: nand: omap_gpmc: rename struct nand_bch_priv to struct omap_nand_info

This patch renames 'struct nand_bch_priv' which currently holds private data only
for BCH ECC schemes, into 'struct omap_nand_info' so that same can be used for
all ECC schemes

Signed-off-by: Pekon Gupta <pekon@ti.com>
Reviewed-by: Stefan Roese <sr@denx.de>
6 years agomtd: nand: omap_gpmc: remove unused members of 'struct nand_bch_priv'
pekon gupta [Fri, 11 Apr 2014 07:25:32 +0000 (12:55 +0530)]
mtd: nand: omap_gpmc: remove unused members of 'struct nand_bch_priv'

This patch prepares to refactor 'struct nand_bch_priv' -> 'struct omap_nand_info'
And thus performs following clean-ups:
 - remove nand_bch_priv.type: use nand_bch_priv.ecc_scheme instead
 - remove nand_bch_priv.mode: <unused>

Signed-off-by: Pekon Gupta <pekon@ti.com>
Reviewed-by: Stefan Roese <sr@denx.de>
6 years agomtd: nand: omap_elm: use macros for register definitions
pekon gupta [Fri, 11 Apr 2014 07:25:31 +0000 (12:55 +0530)]
mtd: nand: omap_elm: use macros for register definitions

This patch adds macros for following parameters of ELM Hardware engine
 - ELM_MAX_CHANNELS: ELM can process 8 data streams simultaneously
 - ELM_MAX_ERRORS: ELM can detect upto 16 ECC error when using BCH16 scheme

Signed-off-by: Pekon Gupta <pekon@ti.com>
Reviewed-by: Stefan Roese <sr@denx.de>
6 years agomtd: nand: omap_elm: use bch_type instead of nibble count to differentiate between...
pekon gupta [Fri, 11 Apr 2014 07:25:30 +0000 (12:55 +0530)]
mtd: nand: omap_elm: use bch_type instead of nibble count to differentiate between BCH4/BCH8/BCH16

ELM hardware engine support ECC error detection for multiple ECC strengths like
 +------+------------------------+
 |Type  | ECC syndrome length    |
 +------+------------------------+
 |BCH4  | 6.5 bytes = 13 nibbles |
 |BCH8  | 13 byte = 26 nibbles   |
 |BCH16 | 26 bytes = 52 nibbles  |
 +------+------------------------+

Current implementation of omap_elm driver uses ECC syndrom length (in 'nibbles')
to differentiate between BCH4/BCH8/BCH16. This patch replaces it with 'bch_type'

Signed-off-by: Pekon Gupta <pekon@ti.com>
Reviewed-by: Stefan Roese <sr@denx.de>
6 years agomtd: nand: omap_elm: remove #include omap_gpmc.h
pekon gupta [Fri, 11 Apr 2014 07:25:29 +0000 (12:55 +0530)]
mtd: nand: omap_elm: remove #include omap_gpmc.h

There is no dependency of omap_elm.c on omap_gpmc.h

Signed-off-by: Pekon Gupta <pekon@ti.com>
Reviewed-by: Stefan Roese <sr@denx.de>
6 years agoMerge branch 'master' of git://git.denx.de/u-boot-mpc85xx
Tom Rini [Thu, 5 Jun 2014 21:38:30 +0000 (17:38 -0400)]
Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx

6 years agofs: fatwrite: use map_sysmem before use file_fat_write
Wu, Josh [Wed, 4 Jun 2014 03:01:24 +0000 (11:01 +0800)]
fs: fatwrite: use map_sysmem before use file_fat_write

When the map_sysmem, then the fatwrite command can support sandbox.
Following command will show how to use it:
  => sb bind 0 sd.img
  => fatls host 0
  => fatwrite host 0 $memaddr filename $filesize

Signed-off-by: Josh Wu <josh.wu@atmel.com>
Acked-by: Simon Glass <sjg@chromium.org>
6 years agotools: refactor HOSTLOADLIBES_* options
Masahiro Yamada [Thu, 5 Jun 2014 07:41:49 +0000 (16:41 +0900)]
tools: refactor HOSTLOADLIBES_* options

The tools mkimage, dumpimage, fit_info, fit_check_sign
always have the common libraries to be linked,
so HOSTLOADLIBES_* can be consolidated a little bit.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Simon Glass <sjg@chromium.org>
6 years agonand_spl: remove nand_spl infrastructure
Masahiro Yamada [Wed, 4 Jun 2014 01:26:53 +0000 (10:26 +0900)]
nand_spl: remove nand_spl infrastructure

Remove the common infrastructure of nand_spl and
clean-up the code inside ifdef(CONFIG_NAND_U_BOOT)..endif.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
6 years agonand_spl: remove simpc8313 support
Masahiro Yamada [Wed, 4 Jun 2014 01:26:52 +0000 (10:26 +0900)]
nand_spl: remove simpc8313 support

Commit 3d5a335c announced that all the nand_spl boards
would be removed before v2014.07 release.

Also update README.scrapyard.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
6 years agonand_spl: remove MPC8315ERDB_NAND support
Masahiro Yamada [Wed, 4 Jun 2014 01:26:51 +0000 (10:26 +0900)]
nand_spl: remove MPC8315ERDB_NAND support

Commit 3d5a335c announced that all the nand_spl boards
would be removed before v2014.07 release.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
6 years agonand_spl: remove MPC8536DS support
Masahiro Yamada [Wed, 4 Jun 2014 01:26:50 +0000 (10:26 +0900)]
nand_spl: remove MPC8536DS support

Commit 3d5a335c announced that all the nand_spl boards
would be removed before v2014.07 release.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
6 years agonand_spl: remove MPC8569MDS_NAND support
Masahiro Yamada [Wed, 4 Jun 2014 01:26:49 +0000 (10:26 +0900)]
nand_spl: remove MPC8569MDS_NAND support

Commit 3d5a335c announced that all the nand_spl boards
would be removed before v2014.07 release.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
6 years agonand_spl: remove MPC8572DS_NAND support
Masahiro Yamada [Wed, 4 Jun 2014 01:26:48 +0000 (10:26 +0900)]
nand_spl: remove MPC8572DS_NAND support

Commit 3d5a335c announced that all the nand_spl boards
would be removed before v2014.07 release.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
6 years agonand_spl: remove P1023RDS_NAND support
Masahiro Yamada [Wed, 4 Jun 2014 01:26:47 +0000 (10:26 +0900)]
nand_spl: remove P1023RDS_NAND support

Commit 3d5a335c announced that all the nand_spl boards
would be removed before v2014.07 release.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
6 years agokbuild: move cmd_mkimage to scripts/Makefile.lib
Masahiro Yamada [Wed, 4 Jun 2014 01:12:21 +0000 (10:12 +0900)]
kbuild: move cmd_mkimage to scripts/Makefile.lib

Because cmd_mkimage is used in various subdirectories,
it seems reasonable to define it in scripts/Makefile.lib.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
6 years agokbuild: use cmd_shipped instead of cmd_copy
Masahiro Yamada [Wed, 4 Jun 2014 01:11:18 +0000 (10:11 +0900)]
kbuild: use cmd_shipped instead of cmd_copy

We already have cmd_shipped in scripts/Makefile.lib.
Use it rather than defining a new command cmd_copy.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
6 years agoboards.cfg: move many unmaintained boards to Orphan
Masahiro Yamada [Mon, 2 Jun 2014 07:30:53 +0000 (16:30 +0900)]
boards.cfg: move many unmaintained boards to Orphan

Emails to the following addresses have been bouncing.

Albin Tonnerre <albin.tonnerre@free-electrons.com>
Anton Shurpin <shurpin.aa@niistt.ru>
Brent Kandetzki <brentk@teleco.com>
Dan Malek <dan@embeddedalley.com>
Frank Panno <fpanno@delphintech.com>
Gary Jennejohn <garyj@denx.de>
Hayden Fraser <Hayden.Fraser@freescale.com>
Eric Millbrandt <emillbrandt@dekaresearch.com>
Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Hans-Christian Egtvedt <hans-christian.egtvedt@atmel.com>
Kumar Gala <kumar.gala@freescale.com>
Joe D'Abbraccio <ljd015@freescale.com>
John Zhan <zhanz@sinovee.com>
Keith Outwater <Keith_Outwater@mvis.com>
Julien May <julien.may@miromico.ch>
Kári Davíðsson <kd@flaga.is>
Kyle Moffett <Kyle.D.Moffett@boeing.com>
Leo Sartre <lsartre@adeneo-embedded.com>
Mike Dunn <mikedunn@newsguy.com>
Dave Ellis <DGE@sixnetio.com>
Chan-Taek Park <c-park@ti.com>
Jerry Van Baren <gerald.vanbaren@smiths-aerospace.com>

I am Ccing the current working addresses for some of them.

If you want to get back an Orphan board to Active,
please update your email address.

Please do it only if you still have a real hardware to test on.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Albin Tonnerre <albin.tonnerre@gmail.com>
Cc: Anton Shurpin <anton.shurpin@gmail.com>
Cc: Brent Kandetzki <brent.kandetzki@stw-technic.com>
Cc: Dan Malek <dan.malek@konsulko.com>
Cc: Gary Jennejohn <gljennjohn@googlemail.com>
Cc: Haavard Skinnemoen <haavard.skinnemoen@gmail.com> ?
Cc: Hans-Christian Egtvedt <egtvedt@samfundet.no>
Cc: Kumar Gala <galak@kernel.crashing.org>
Cc: Mike Dunn <mikedunn@newsguy.com>
CC: Jerry Van Baren <vanbaren@cideas.com>
6 years agoPrevent a buffer overflow in mkimage when signing with SHA256
Michael van der Westhuizen [Fri, 30 May 2014 18:59:00 +0000 (20:59 +0200)]
Prevent a buffer overflow in mkimage when signing with SHA256

Due to the FIT_MAX_HASH_LEN constant not having been updated
to support SHA256 signatures one will always see a buffer
overflow in fit_image_process_hash when signing images that
use this larger hash.  This is exposed by vboot_test.sh.

Signed-off-by: Michael van der Westhuizen <michael@smart-africa.com>
Acked-by: Simon Glass <sjg@chromium.org>
[trini: Rework a bit so move the exportable parts of hash.h outside of
 !USE_HOSTCC and only need that as a new include to image.h]
Signed-off-by: Tom Rini <trini@ti.com>
6 years agodriver/ddr/fsl: Fix printing unspecified module info for DDR4
York Sun [Thu, 5 Jun 2014 19:32:15 +0000 (12:32 -0700)]
driver/ddr/fsl: Fix printing unspecified module info for DDR4

The offset of module information is at 128, different from DDR3.

Signed-off-by: York Sun <yorksun@freescale.com>
6 years agopowerpc/mpc85xx: Add workaround to enable TDM on T1040
Sandeep Singh [Thu, 5 Jun 2014 13:19:57 +0000 (18:49 +0530)]
powerpc/mpc85xx: Add workaround to enable TDM on T1040

This is a workaround for 32 bit hardware limitation of TDM.
T1040 has 36 bit physical addressing, TDM DMAC register
are 32 bit wide but need to store address of CCSR space
which lies beyond 32 bit address range. This workaround
creats a LAW to enable access of TDM DMA to CCSR by
mapping CCSR to overlap with DDR.
A hole of 16M is created in memory using device tree. This
workaround law is set only if "tdm" is defined in hwconfig.
Also disable POST tests and add LIODN for TDM

Signed-off-by: Sandeep Singh <Sandeep@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
6 years agopowerpc/B4420: Fixed incomplete handling for 0x9d serdes2
poonam aggrwal [Fri, 30 May 2014 18:38:18 +0000 (00:08 +0530)]
powerpc/B4420: Fixed incomplete handling for 0x9d serdes2

Crossbars and IDT were not getting configured for Serdes2 protocol
0x9d for B4420.

Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
6 years agopowerpc/serdes: Add the workaround for erratum A-007186
Shaveta Leekha [Wed, 28 May 2014 08:48:55 +0000 (14:18 +0530)]
powerpc/serdes: Add the workaround for erratum A-007186

SerDes PLL is calibrated at reset. When the junction temperature
delta from the time the PLL is calibrated exceeds +56C/-66C,
jitter may increase and can cause PLL to unlock.

This workaround overwrite the SerDes registers with new values,
to calibrate SerDes registers.
These values are known to work fine for all temperature ranges.

This workaround is valid for B4, T4 and T2 platforms, so
added in their config.

Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
Signed-off-by: Poonam Aggrwal <Poonam.Aggrwal@freescale.com>
[York Sun: replaced typedef ccsr_sfp_regs_t with struct ccsr_sfp_regs]
Reviewed-by: York Sun <yorksun@freescale.com>
6 years agopowerpc/mpc85xx: Add workaround for DDR erratum A004508
York Sun [Fri, 23 May 2014 20:15:00 +0000 (13:15 -0700)]
powerpc/mpc85xx: Add workaround for DDR erratum A004508

When the DDR controller is initialized below a junction temperature of
0°C and then operated above a junction temperature of 65°C, the DDR
controller may cause receive data errors, resulting ECC errors and/or
corrupted data. This erratum applies to the following SoCs and their
variants: MPC8536, MPC8569, MPC8572, P1010, P1020, P1021, P1022, P1023,
P2020.

Signed-off-by: York Sun <yorksun@freescale.com>
6 years agopowerpc/t2080: add serdes2 protocol 0x27
Shengzhou Liu [Thu, 22 May 2014 09:24:59 +0000 (17:24 +0800)]
powerpc/t2080: add serdes2 protocol 0x27

Add a new serdes2 protocol 0x27.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
6 years agopowerpc/espi: remove 80us delay to improve transfer performance
Hou Zhiqiang [Wed, 21 May 2014 02:25:10 +0000 (10:25 +0800)]
powerpc/espi: remove 80us delay to improve transfer performance

Replace 80 mircoseconds delay with polling flag ESPI_EV_TXE.

Signed-off-by: Hou Zhiqiang <B48286@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
6 years agopowerpc/t4rdb: Add alternate serdes protocols to align with A-007186
Chunhe Lan [Tue, 20 May 2014 05:34:28 +0000 (13:34 +0800)]
powerpc/t4rdb: Add alternate serdes protocols to align with A-007186

A-007186: SerDes PLL is calibrated at reset. It is possible
for jitter to increase and cause the PLL to unlock when the
temperature delta from the time the PLL is calibrated exceeds
+56C/-66C when using X VDD of 1.35 V (or +70C/-80C when using
XnVDD of 1.5 V). No issues are seen with LC VCO. The protocols
only using Ring VCOs are impacted.

Workaround:
For all 1.25/2.5/5 GHz protocols, use LC VCO instead of Ring
VCO, this need to use alternate serdes protocols. Alternate
option has the same functionality as the original option; the
only difference being LC VCO rather than Ring VCO.

Signed-off-by: Chunhe Lan <Chunhe.Lan@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
6 years agoboard/t2080qds: some update for ddr
Shengzhou Liu [Tue, 20 May 2014 04:08:20 +0000 (12:08 +0800)]
board/t2080qds: some update for ddr

- add support for 2nd DIMM slot.
- make it work with DIMM which is less than 2GB.

Verified with two 2GB UDIMM MT9JSF25672AZ-2G1K1 in two DIMM slots.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
6 years agopowerpc/t4qds: Add alternate serdes protocols to align with A-007186
Shaohui Xie [Fri, 16 May 2014 02:52:33 +0000 (10:52 +0800)]
powerpc/t4qds: Add alternate serdes protocols to align with A-007186

A-007186: SerDes PLL is calibrated at reset. It is possible for jitter to
increase and cause the PLL to unlock when the temperature delta from the
time the PLL is calibrated exceeds +56C/-66C when using X VDD of 1.35 V
(or +70C/-80C when using XnVDD of 1.5 V). No issues are seen with LC
VCO. Only the protocols using Ring VCOs are impacted.

Workaround:
For all 1.25/2.5/5 GHz protocols, use LC VCO instead of Ring VCO, this need
to use alternate serdes protocols. The alternate option has the same
functionality as the original option; the only difference being LC VCO
rather than Ring VCO.

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
6 years agoboard/t208x: update t2080qds/t2080rdb for errata A-007186
Shengzhou Liu [Thu, 15 May 2014 11:24:11 +0000 (19:24 +0800)]
board/t208x: update t2080qds/t2080rdb for errata A-007186

As errata A-007186, we need to use the alternate serdes
protocol instead of those impacted protocols.

- add support for serdes protocols: 0x1b, 0x50, 0x5e,
  0x64, 0x6a, 0xd2, 0x67, 0x70.
- update t2080_rcw.cfg to adapt to new rcw_66_15 for
  t2080qds and t2080rdb.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
6 years agompc8313, signed fit: enable legacy image format on ids8313 board
Heiko Schocher [Wed, 28 May 2014 09:33:34 +0000 (11:33 +0200)]
mpc8313, signed fit: enable legacy image format on ids8313 board

Enable legacy image format with CONFIG_IMAGE_FORMAT_LEGACY
on the ids8313 board, as it uses signed FIT images for booting
Linux and need the legacy image format.

Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Kim Phillips <kim.phillips@freescale.com>
Cc: Michael Conrad <Michael.Conrad@ids.de>
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Simon Glass <sjg@chromium.org>
6 years agobootm: make use of legacy image format configurable
Heiko Schocher [Wed, 28 May 2014 09:33:33 +0000 (11:33 +0200)]
bootm: make use of legacy image format configurable

make the use of legacy image format configurable through
the config define CONFIG_IMAGE_FORMAT_LEGACY.

When relying on signed FIT images with required signature check
the legacy image format should be disabled. Therefore introduce
this new define and enable legacy image format if CONFIG_FIT_SIGNATURE
is not set. If CONFIG_FIT_SIGNATURE is set disable per default
the legacy image format.

Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Lars Steubesand <lars.steubesand@philips.com>
Cc: Mike Pearce <mike@kaew.be>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Tom Rini <trini@ti.com>
Cc: Michal Simek <monstr@monstr.eu>
Acked-by: Simon Glass <sjg@chromium.org>
6 years agoFDT: Fix DTC repository references
Jon Loeliger [Tue, 27 May 2014 14:12:48 +0000 (09:12 -0500)]
FDT: Fix DTC repository references

The Device Tree Compiler (DTC) used to have its master
repository located on jdl.com.  While it is still there,
its official, new, shiny location is on kernel.org here:

    git://git.kernel.org/pub/scm/utils/dtc/dtc.git

Update a few references to point there instead.

Signed-off-by: Jon Loeliger <jdl@jdl.com>
Acked-by: Simon Glass <sjg@chromium.org>
6 years agodisk: part_efi: add get_partition_info_efi_by_name()
Steve Rae [Mon, 26 May 2014 18:52:24 +0000 (11:52 -0700)]
disk: part_efi: add get_partition_info_efi_by_name()

Add function to find a GPT table entry by name.

Tested on little endian ARMv7 and ARMv8 configurations

Signed-off-by: Steve Rae <srae@broadcom.com>
6 years agodisk: part_efi: clarify lbaint_t usage
Steve Rae [Mon, 26 May 2014 18:52:23 +0000 (11:52 -0700)]
disk: part_efi: clarify lbaint_t usage

- update the comments regarding lbaint_t usage
- cleanup casting of values related to the lbaint_t type
- cleanup of a type that requires a u64

Tested on little endian ARMv7 and ARMv8 configurations

Signed-off-by: Steve Rae <srae@broadcom.com>
6 years agodisk: part_efi: resolve endianness issues
Steve Rae [Mon, 26 May 2014 18:52:22 +0000 (11:52 -0700)]
disk: part_efi: resolve endianness issues

Tested on little endian ARMv7 and ARMv8 configurations

Signed-off-by: Steve Rae <srae@broadcom.com>
6 years agoenv_eeprom: Assign default environment during board_init_f
Siva Durga Prasad Paladugu [Mon, 26 May 2014 14:21:22 +0000 (19:51 +0530)]
env_eeprom: Assign default environment during board_init_f

Assign default environment and set env valid during board_init_f
before relocation as the actual environment will be read from eeprom
later.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Acked-by: Michal Simek <monstr@monstr.eu>
6 years agofat: Define MAX_CLUSTSIZE using CONFIG_FS_FAT_MAX_CLUSTSIZE
Siva Durga Prasad Paladugu [Mon, 26 May 2014 13:48:37 +0000 (19:18 +0530)]
fat: Define MAX_CLUSTSIZE using CONFIG_FS_FAT_MAX_CLUSTSIZE

Define the MAX_CLUSTSIZE to default of 65536 only if
CONFIG_FS_FAT_MAX_CLUSTSIZE is not defined.
This option has been provided to save memory in some
memory constrained cases.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Acked-by: Michal Simek <monstr@monstr.eu>
6 years agoopenrisc: fix relocation code
Franck Jullien [Wed, 21 May 2014 20:43:50 +0000 (22:43 +0200)]
openrisc: fix relocation code

The relocation code can now relocate from anywhere to
the RAM.

The old code assumed that the binary was copied to the RAM
by some PBL and then it just relocated the .text section
from the loaded address to the linked address.

Now, it first checks if vectors are somewhere else than the
linked address. If yes, there are copied to address 0 (or
to the exception vector base address if register EVBAR is
present).

Then, the .text section is relocated from its current location
to the RAM.

Signed-off-by: Franck Jullien <franck.jullien@gmail.com>
6 years agoopenrisc: update SPR registers definition
Franck Jullien [Wed, 21 May 2014 20:43:49 +0000 (22:43 +0200)]
openrisc: update SPR registers definition

The OpenRISC architecture specification v1.0 defines
new SPR registers. This patch adds registers definition
for group 0 and update bit definitions for the CPU
configuration register.

Signed-off-by: Franck Jullien <franck.jullien@gmail.com>
6 years agophy: fix create_phy_by_mask for when its given an actual search mask
Cormier, Jonathan [Wed, 21 May 2014 17:08:52 +0000 (13:08 -0400)]
phy: fix create_phy_by_mask for when its given an actual search mask

get_phy_id returns -EIO when it can't read from a phy at a given addr.  This would cause
create_phy_by_mask to return prematurely before it had tested the other addresses in the provided mask.

Example usage:
Replace
    phydev = phy_connect(bus, phy_addr, dev, phy_if)
with
    phydev = phy_find_by_mask(bus, phy_mask, phy_if)
    if (phydev)
phy_connect_dev(phydev, dev);

Signed-off-by: Cormier, Jonathan <jcormier@criticallink.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>