karo-tx-uboot.git
7 years agoMerge branch 'master' of git://git.denx.de/u-boot-video
Tom Rini [Fri, 7 Jun 2013 12:35:36 +0000 (08:35 -0400)]
Merge branch 'master' of git://git.denx.de/u-boot-video

7 years agoMerge branch 'master' of git://git.denx.de/u-boot-nand-flash
Tom Rini [Fri, 7 Jun 2013 12:34:34 +0000 (08:34 -0400)]
Merge branch 'master' of git://git.denx.de/u-boot-nand-flash

7 years agoinput: Finish simplifing key_matrix_decode_fdt()
Stephen Warren [Thu, 6 Jun 2013 14:48:30 +0000 (10:48 -0400)]
input: Finish simplifing key_matrix_decode_fdt()

[trini: Applied v1 of the series rather than v2, this commit is the
delta from v1 to v2]

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Rini <trini@ti.com>
7 years agocheckpatch.pl: Add 'printf' to logFunctions
Tom Rini [Thu, 6 Jun 2013 13:28:19 +0000 (09:28 -0400)]
checkpatch.pl: Add 'printf' to logFunctions

Signed-off-by: Tom Rini <trini@ti.com>
7 years agoam33xx/omap4+: Move SRAM_SCRATCH_SPACE_ADDR to <asm/arch/omap.h>
Tom Rini [Thu, 6 Jun 2013 12:57:45 +0000 (08:57 -0400)]
am33xx/omap4+: Move SRAM_SCRATCH_SPACE_ADDR to <asm/arch/omap.h>

The location of valid scratch space is dependent on SoC, so move that
there.  On OMAP4+ we continue to use SRAM_SCRATCH_SPACE_ADDR.  On
am33xx/ti814x we want to use what the ROM defines as "public stack"
which is the area after our defined download image space.  Correct the
comment about and location of CONFIG_SPL_TEXT_BASE.

Signed-off-by: Tom Rini <trini@ti.com>
7 years agoARM: bcm2835: add simplefb DT node during bootz/m
Stephen Warren [Mon, 27 May 2013 18:31:18 +0000 (18:31 +0000)]
ARM: bcm2835: add simplefb DT node during bootz/m

Add a DT simple-framebuffer node to DT when booting the Linux kernel.
This will allow the kernel to inherit the framebuffer configuration from
U-Boot, and display a graphical boot console, and even run a full SW-
rendered X server.

Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
Acked-by: Simon Glass <sjg@chromium.org>
7 years agolcd: add functions to set up simplefb device tree
Stephen Warren [Mon, 27 May 2013 18:31:17 +0000 (18:31 +0000)]
lcd: add functions to set up simplefb device tree

simple-framebuffer is a new device tree binding that describes a pre-
configured frame-buffer memory region and its format. The Linux kernel
contains a driver that supports this binding. Implement functions to
create a DT node (or fill in an existing node) with parameters that
describe the framebuffer format that U-Boot is using.

This will be immediately used by the Raspberry Pi board in U-Boot, and
likely will be used by the Samsung ARM ChromeBook support soon too. It
could well be used by many other boards (e.g. Tegra boards with built-in
LCD panels, which aren't yet supported by the Linux kernel).

Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
Acked-by: Simon Glass <sjg@chromium.org>
7 years agoMerge branch 'master' of git://git.denx.de/u-boot-arm
Tom Rini [Wed, 5 Jun 2013 16:45:34 +0000 (12:45 -0400)]
Merge branch 'master' of git://git.denx.de/u-boot-arm

7 years agoMerge branch 'tpm' of git://git.denx.de/u-boot-x86
Tom Rini [Wed, 5 Jun 2013 12:55:35 +0000 (08:55 -0400)]
Merge branch 'tpm' of git://git.denx.de/u-boot-x86

7 years agoam33xx/omap: Move save_omap_boot_params to omap-common/boot-common.c
Tom Rini [Fri, 31 May 2013 16:31:59 +0000 (12:31 -0400)]
am33xx/omap: Move save_omap_boot_params to omap-common/boot-common.c

We need to call the save_omap_boot_params function on am33xx/ti81xx and
other newer TI SoCs, so move the function to boot-common.  Only OMAP4+
has the omap_hw_init_context function so add ifdefs to not call it on
am33xx/ti81xx.  Call save_omap_boot_params from s_init on am33xx/ti81xx
boards.

Reviewed-by: R Sricharan <r.sricharan@ti.com>
Signed-off-by: Tom Rini <trini@ti.com>
7 years agoam33xx: Correct NON_SECURE_SRAM_START/END
Tom Rini [Fri, 31 May 2013 14:48:03 +0000 (10:48 -0400)]
am33xx: Correct NON_SECURE_SRAM_START/END

Prior to Sricharan's cleanup of the boot parameter saving code, we
did not make use of NON_SECURE_SRAM_START on am33xx, so it wasn't a
problem that the address was pointing to the middle of our running SPL.
Correct to point to the base location of the download image area.
Increase CONFIG_SPL_TEXT_BASE to account for this scratch area being
used.  As part of correcting these tests, make use of the fact that
we've always been placing our stack outside of the download image area
(which is fine, once the downloaded image is run, ROM is gone) so
correct the max size test to be the ROM defined top of the download area
to where we link/load at.

Signed-off-by: Tom Rini <trini@ti.com>
---
Changes in v2:
- Fix typo noted by Peter Korsgaard

7 years agoomap-common/hwinit-common.c: Mark omap_rev_string as static
Tom Rini [Fri, 31 May 2013 14:44:23 +0000 (10:44 -0400)]
omap-common/hwinit-common.c: Mark omap_rev_string as static

Only called in this file, mark as static.

Signed-off-by: Tom Rini <trini@ti.com>
7 years agofdt: allow bootdelay to be specified via device tree
Stephen Warren [Tue, 14 May 2013 08:02:56 +0000 (08:02 +0000)]
fdt: allow bootdelay to be specified via device tree

This can be useful to force bootcmd to execute as soon as U-Boot has
started.

My use-case is: An SoC-specific tool pushes U-Boot into RAM, along with
an image to be written to device boot flash, with the DT config property
"bootcmd" set to contain a command to write that image to flash. In this
scenario, we don't want to allow any stale bootdelay value taken from
the current flash content to affect how long it takes before the
flashing process starts.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Acked-by: Gerald Van Baren <vanbaren@cideas.com>
7 years agoinput: simplify key_matrix_decode_fdt()
Stephen Warren [Thu, 23 May 2013 12:09:57 +0000 (12:09 +0000)]
input: simplify key_matrix_decode_fdt()

We know the exact property names that the code wants to process. Look
these up directly with fdt_get_property(), rather than iterating over
all properties within the node, and checking each property's name, in
a convoluted fashion, against the expected name.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
7 years agoinput: fix unaligned access in key_matrix_decode_fdt()
Stephen Warren [Wed, 22 May 2013 08:48:18 +0000 (08:48 +0000)]
input: fix unaligned access in key_matrix_decode_fdt()

Initialized character arrays on the stack can cause gcc to emit code that
performs unaligned accessess. Make the data static to avoid this.

Note that the unaligned accesses are made when copying data to prefix[] on
the stack from .rodata. By making the data static, the copy is completely
avoided. All explicitly written code treats the data as u8[], so will never
cause any unaligned accesses.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
7 years agocommon: board_f: Do not call board_postclk_init twice
Masahiro Yamada [Tue, 21 May 2013 21:08:09 +0000 (21:08 +0000)]
common: board_f: Do not call board_postclk_init twice

The generic-board board_init_f function called board_postclk_init twice.

The first one came from arch/arm/lib/board.c, while the second one
from arch/powerpc/lib/board.c.

This commit deletes the first occurrence.
In addition, the second get_clocks call is moved after
board_postclk_init in order to keep the function call order
both for ARM and PowerPC.
ARM board calles get_clocks function after board_postclk_init.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
7 years agodisk: Fix possible out-of-bounds access in part_efi.c
Marek Vasut [Sun, 19 May 2013 12:53:34 +0000 (12:53 +0000)]
disk: Fix possible out-of-bounds access in part_efi.c

Make sure to never access beyond bounds of either EFI partition name
or DOS partition name. This situation is happening:

part.h:     disk_partition_t->name is 32-byte long
part_efi.h: gpt_entry->partition_name is 36-bytes long

The loop in part_efi.c copies over 36 bytes and thus accesses beyond
the disk_partition_t->name .

Fix this by picking the shortest of source and destination arrays and
make sure the destination array is cleared so the trailing bytes are
zeroed-out and don't cause issues with string manipulation.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Tom Rini <trini@ti.com>
Cc: Simon Glass <sjg@chromium.org>
7 years agosandbox: image: Create a test for loading FIT images
Simon Glass [Thu, 16 May 2013 13:53:28 +0000 (13:53 +0000)]
sandbox: image: Create a test for loading FIT images

The image code is fairly complex with various different options. It would
be useful to have comprehensive tests for this.

As a start, create a script which tries out loading a kernel/ramdisk/fdt
from a FIT and checks that the images appear in the right place in memory.

This uses sandbox which now supports bootm and related features.

Signed-off-by: Simon Glass <sjg@chromium.org>
7 years agobootstage: Remove unused entries related to kernel/ramdisk/fdt load
Simon Glass [Thu, 16 May 2013 13:53:27 +0000 (13:53 +0000)]
bootstage: Remove unused entries related to kernel/ramdisk/fdt load

Now that the code for loading these three images from a FIT is common, we
don't need individual boostage IDs for each of them.

Note: there are some minor changes in the bootstage numbering, particuarly
for kernel loading. I don't believe this matters.

Signed-off-by: Simon Glass <sjg@chromium.org>
7 years agosandbox: image: Adjust FIT image printing to work with sandbox
Simon Glass [Thu, 16 May 2013 13:53:26 +0000 (13:53 +0000)]
sandbox: image: Adjust FIT image printing to work with sandbox

Use map_sysmem() to convert from address to pointer, so that sandbox can
print FIT information without crashing.

Signed-off-by: Simon Glass <sjg@chromium.org>
7 years agoimage: Use fit_image_load() to load kernel
Simon Glass [Thu, 16 May 2013 13:53:25 +0000 (13:53 +0000)]
image: Use fit_image_load() to load kernel

Use the new common code to load a kernel. The functionality should not
change.

Signed-off-by: Simon Glass <sjg@chromium.org>
7 years agosandbox: Adjust bootm command to work with sandbox
Simon Glass [Thu, 16 May 2013 13:53:24 +0000 (13:53 +0000)]
sandbox: Adjust bootm command to work with sandbox

Use map_sysmem() when converting from addresses to pointers, so that
bootm can be used with sandbox.

Signed-off-by: Simon Glass <sjg@chromium.org>
7 years agoimage: Use fit_image_load() to load FDT
Simon Glass [Thu, 16 May 2013 13:53:23 +0000 (13:53 +0000)]
image: Use fit_image_load() to load FDT

Use the new common code to load a flat device tree. Also fix up a few casts
so that this code works with sandbox. Other than that the functionality
should not change.

Signed-off-by: Simon Glass <sjg@chromium.org>
7 years agoimage: Use fit_image_load() to load ramdisk
Simon Glass [Thu, 16 May 2013 13:53:22 +0000 (13:53 +0000)]
image: Use fit_image_load() to load ramdisk

Use the new common code to load a ramdisk. The functionality should not
change.

Signed-off-by: Simon Glass <sjg@chromium.org>
7 years agoimage: Introduce fit_image_load() to load images from FITs
Simon Glass [Thu, 16 May 2013 13:53:21 +0000 (13:53 +0000)]
image: Introduce fit_image_load() to load images from FITs

At present code to load an image from a FIT is duplicated in the three
places where it is needed (kernel, fdt, ramdisk).

The differences between these different code copies is fairly minor.
Create a new function in the fit code which can handle any of the
requirements of those cases.

Signed-off-by: Simon Glass <sjg@chromium.org>
7 years agomkimage: Add map_sysmem() and IH_ARCH_DEFAULT to simplfy building
Simon Glass [Thu, 16 May 2013 13:53:20 +0000 (13:53 +0000)]
mkimage: Add map_sysmem() and IH_ARCH_DEFAULT to simplfy building

These are not actually used in mkimage itself, but the image code (which
is common with mkimage) does use them. To avoid #ifdefs in the image code
just for mkimage, define dummy version of these here. The compiler will
eliminate the dead code anyway.

A better way to handle this might be to split out more things from common.h
so that mkimage can include them. At present any file that mkimage uses
has to be very careful what headers it includes.

Signed-off-by: Simon Glass <sjg@chromium.org>
7 years agobootstage: Introduce sub-IDs for use with image loading
Simon Glass [Thu, 16 May 2013 13:53:19 +0000 (13:53 +0000)]
bootstage: Introduce sub-IDs for use with image loading

Loading a ramdisk, kernel or FDT goes through similar stages. Create
a block of IDs for each task, and define a consistent numbering within
the block. This will allow use of common code for image loading.

Signed-off-by: Simon Glass <sjg@chromium.org>
7 years agomain: Add debug_bootkeys to avoid #ifdefs
Simon Glass [Wed, 15 May 2013 06:24:01 +0000 (06:24 +0000)]
main: Add debug_bootkeys to avoid #ifdefs

Define a simple debug condition at the top of the file, to avoid using
lots of #ifdefs later on.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
7 years agomain: Add debug_parser() to avoid #ifdefs
Simon Glass [Wed, 15 May 2013 06:24:00 +0000 (06:24 +0000)]
main: Add debug_parser() to avoid #ifdefs

Define a simple debug condition at the top of the file, to avoid using
lots of #ifdefs later on.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
7 years agomain: Correct header order
Simon Glass [Wed, 15 May 2013 06:23:59 +0000 (06:23 +0000)]
main: Correct header order

The headers are a bit out of order, so fix them.

Signed-off-by: Simon Glass <sjg@chromium.org>
7 years agomain: Fix typos and checkpatch warnings in command line reading
Simon Glass [Wed, 15 May 2013 06:23:58 +0000 (06:23 +0000)]
main: Fix typos and checkpatch warnings in command line reading

There are a few over-long lines and other checkpatch problems in this area
of the code. Prepare the ground for the next patch by tidying these up.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
7 years agomain: Use get/setenv_ulong()
Simon Glass [Wed, 15 May 2013 06:23:57 +0000 (06:23 +0000)]
main: Use get/setenv_ulong()

These functions are now available, so use them to avoid extra code here.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
7 years agomain: Move boot_delay code into its own function
Simon Glass [Wed, 15 May 2013 06:23:56 +0000 (06:23 +0000)]
main: Move boot_delay code into its own function

Move this code into its own function, since it clutters up main_loop().

Signed-off-by: Simon Glass <sjg@chromium.org>
7 years agomain: Separate out the two abortboot() functions
Simon Glass [Wed, 15 May 2013 06:23:55 +0000 (06:23 +0000)]
main: Separate out the two abortboot() functions

There are two implementations of abortboot(). Turn these into two separate
functions, and create a single abortboot() which calls either one or the
other.

Also it seems that nothing uses abortboot() outside main, so make it static.

At this point there is no further use of CONFIG_MENU in main.c.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
7 years agonet: Add prototype for update_tftp
Simon Glass [Wed, 15 May 2013 06:23:54 +0000 (06:23 +0000)]
net: Add prototype for update_tftp

This function should be declared in net.h.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
7 years agoat91: Correct CONFIG_AUTOBOOT_PROMPT definition for pm9263
Simon Glass [Wed, 15 May 2013 06:23:53 +0000 (06:23 +0000)]
at91: Correct CONFIG_AUTOBOOT_PROMPT definition for pm9263

This is not currently used, since autoboot is not enabled for this
board, but the string is missing a parameter. Add it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Andreas Bießmann <andreas.devel@googlemail.com>
7 years agobug, nand, am33xx: nand->ecc.strength not set in board_nand_init()
Sergey Lapin [Tue, 4 Jun 2013 16:42:43 +0000 (11:42 -0500)]
bug, nand, am33xx: nand->ecc.strength not set in board_nand_init()

commit dfe64e2c89731a3f9950d7acd8681b68df2bae03
Author: Sergey Lapin <slapin@ossfans.org>
Date:   Mon Jan 14 03:46:50 2013 +0000

    mtd: resync with Linux-3.7.1

Introduced runtime bug:

U-Boot 2013.04-00499-g46567df-dirty (Jun 04 2013 - 08:17:08)

I2C:   ready
DRAM:  512 MiB
WARNING: Caches not enabled
NAND:  BUG: failure at nand_base.c:3214/nand_scan_tail()!
BUG!
resetting ...

on boards using drivers/mtd/nand/omap_gpmc.c as in board_nand_init()
nand->ecc.strength is not set. Fix this!

Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Sergey Lapin <slapin@ossfans.org>
Cc: Scott Wood <scottwood@freescale.com>
Cc: Tom Rini <trini@ti.com>
7 years agotpm: Reorganize the I2C TPM driver
Tom Wai-Hong Tam [Fri, 12 Apr 2013 11:04:37 +0000 (11:04 +0000)]
tpm: Reorganize the I2C TPM driver

This patch does a similar code reogranzation from
  http://patchwork.ozlabs.org/patch/132179/
which is based on an old version of code (fdt support and bus selection
still not in). It merges this tidy-up on top of the recent code. It does
not make any logical change.

tpm.c implements the interface defined in tpm.h based on underlying
LPC or I2C TPM driver. tpm.c and the underlying driver communicate
throught tpm_private.h.

Note: Merging the LPC driver with tpm.c is left to future patches.

Change-Id: Ie1384f5f9e3935d3bc9a44adf8de80c5a70a5f2b
Signed-off-by: Tom Wai-Hong Tam <waihong@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agotpm: Add support for new Infineon I2C TPM (SLB 9645 TT 1.2 I2C)
Vincent Palatin [Fri, 12 Apr 2013 11:04:36 +0000 (11:04 +0000)]
tpm: Add support for new Infineon I2C TPM (SLB 9645 TT 1.2 I2C)

Add support for Infineon's new SLB 9645 TT 1.2 I2C TPMs,
which supports clockstretching, combined reads and a bus speed of
up to 400khz. The device also has a new device id.

This is based on the kernel patch provided by Infineon :
https://gerrit.chromium.org/gerrit/42332

Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Luigi Semenzato <semenzato@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Tom Wai-Hong Tam <waihong@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
7 years agox86: config: Reflect the name changes of LPC TPM configs
Tom Wai-Hong Tam [Fri, 12 Apr 2013 11:04:35 +0000 (11:04 +0000)]
x86: config: Reflect the name changes of LPC TPM configs

The new name is more aligned with Linux kernel's naming of TPM driver.

Signed-off-by: Tom Wai-Hong Tam <waihong@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agotpm: Rename generic_lpc_tpm to tpm_tis_lpc
Che-liang Chiou [Fri, 12 Apr 2013 11:04:34 +0000 (11:04 +0000)]
tpm: Rename generic_lpc_tpm to tpm_tis_lpc

The new name is more aligned with Linux kernel's naming of TPM driver.

Signed-off-by: Peter Huewe <peter.huewe@infineon.com>
Signed-off-by: Che-Liang Chiou <clchiou@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Mike Frysinger <vapier@gentoo.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Tom Wai-Hong Tam <waihong@chromium.org>
7 years agoMerge branch 'master' of git://git.denx.de/u-boot-nand-flash
Tom Rini [Fri, 31 May 2013 22:28:47 +0000 (18:28 -0400)]
Merge branch 'master' of git://git.denx.de/u-boot-nand-flash

7 years agomtd: resync with Linux-3.7.1
Sergey Lapin [Mon, 14 Jan 2013 03:46:50 +0000 (03:46 +0000)]
mtd: resync with Linux-3.7.1

This patch is essentially an update of u-boot MTD subsystem to
the state of Linux-3.7.1 with exclusion of some bits:

- the update is concentrated on NAND, no onenand or CFI/NOR/SPI
flashes interfaces are updated EXCEPT for API changes.

- new large NAND chips support is there, though some updates
have got in Linux-3.8.-rc1, (which will follow on top of this patch).

To produce this update I used tag v3.7.1 of linux-stable repository.

The update was made using application of relevant patches,
with changes relevant to U-Boot-only stuff sticked together
to keep bisectability. Then all changes were grouped together
to this patch.

Signed-off-by: Sergey Lapin <slapin@ossfans.org>
[scottwood@freescale.com: some eccstrength and build fixes]
Signed-off-by: Scott Wood <scottwood@freescale.com>
7 years agoarm: factorize relocate_code routine
Albert ARIBAUD [Sun, 19 May 2013 01:48:15 +0000 (01:48 +0000)]
arm: factorize relocate_code routine

Replace all relocate_code routines from ARM start.S files
with a single instance in file arch/arm/lib/relocate.S.
For PXA, this requires moving the dcache unlocking code
from within relocate_code into c_runtime_cpu_setup.

Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Tested-by: Simon Glass <sjg@chromium.org>
7 years agoarm: do not compile relocate_code() for SPL builds
Albert ARIBAUD [Sun, 19 May 2013 01:48:14 +0000 (01:48 +0000)]
arm: do not compile relocate_code() for SPL builds

Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Tested-by: Simon Glass <sjg@chromium.org>
7 years agotx25: copy SPL directly, not using relocate_code.
Albert ARIBAUD [Sun, 19 May 2013 01:48:13 +0000 (01:48 +0000)]
tx25: copy SPL directly, not using relocate_code.

Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Tested-by: Simon Glass <sjg@chromium.org>
7 years agomx31pdk: copy SPL directly, not using relocate_code.
Albert ARIBAUD [Sun, 19 May 2013 01:48:12 +0000 (01:48 +0000)]
mx31pdk: copy SPL directly, not using relocate_code.

Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Tested-by: Simon Glass <sjg@chromium.org>
7 years agoMerge branch 'u-boot/master' into 'u-boot-arm/master'
Albert ARIBAUD [Thu, 30 May 2013 12:45:06 +0000 (14:45 +0200)]
Merge branch 'u-boot/master' into 'u-boot-arm/master'

Conflicts:
common/cmd_fpga.c
drivers/usb/host/ohci-at91.c

7 years agotegra: Define CONFIG_SKIP_LOWLEVEL_INIT for SPL build
Axel Lin [Tue, 21 May 2013 13:45:18 +0000 (13:45 +0000)]
tegra: Define CONFIG_SKIP_LOWLEVEL_INIT for SPL build

Then we can get rid of the #ifdef CONFIG_TEGRA guard in cpu_init_crit.

Signed-off-by: Axel Lin <axel.lin@ingics.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
7 years agoARM: arm720t: Add missing CONFIG_SKIP_LOWLEVEL_INIT guard for cpu_init_crit
Axel Lin [Tue, 21 May 2013 13:44:10 +0000 (13:44 +0000)]
ARM: arm720t: Add missing CONFIG_SKIP_LOWLEVEL_INIT guard for cpu_init_crit

cpu_init_crit() can be skipped, but the code is still enabled requiring a
platform to supply lowlevel_init().

Signed-off-by: Axel Lin <axel.lin@ingics.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
7 years agoARM: tegra: support SKU 7 of Tegra20
Stephen Warren [Fri, 17 May 2013 14:10:15 +0000 (14:10 +0000)]
ARM: tegra: support SKU 7 of Tegra20

Make U-Boot aware of the Tegra20 SKU 7, and treat it identically
to any other Tegra20.

My Whistler board has a SoC with this SKU.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
7 years agoARM: tegra: support SKU 1 of Tegra114
Stephen Warren [Fri, 17 May 2013 14:10:14 +0000 (14:10 +0000)]
ARM: tegra: support SKU 1 of Tegra114

Make U-Boot aware of the Tegra114 SKU 1, and treat it identically
to any other Tegra114.

This value is used on (at least some) Dalmore boards with a production
rather than engineering chip. Such boards are in the hands of some
partners who want to use upstream U-Boot.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
7 years agotegra: always build u-boot-nodtb-tegra.bin
Stephen Warren [Tue, 14 May 2013 08:00:53 +0000 (08:00 +0000)]
tegra: always build u-boot-nodtb-tegra.bin

Even when eventually building u-boot-dtb-tegra.bin, separately building
u-boot-nodtb-tegra.bin can be useful, since building it encapsulates the
SPL padding step. If you want to tweak u-boot.dtb and regenerate
u-boot-dtb-tegra.bin, it is then a simple cat operation.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
7 years agoTegra: clk: always use find_best_divider() for periph clocks
Allen Martin [Fri, 10 May 2013 16:56:55 +0000 (16:56 +0000)]
Tegra: clk: always use find_best_divider() for periph clocks

When adjusting peripheral clocks always use find_best_divider()
instead of clk_get_divider() even when a secondary divider is not
available.  In the case where is requested clock is too slow to be
derived from the parent clock this allows a best effort to get close
to the requested clock.

This comes up for commands like "sf" where the user can pass a clock
speed on the command line or "sspi" where the clock is hardcoded to
1MHz, but the Tegra114 SPI controller can't go that low.

Signed-off-by: Allen Martin <amartin@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
7 years agoTegra: Remove unused/non-existent spl linker script reference
Tom Warren [Wed, 17 Apr 2013 15:24:57 +0000 (08:24 -0700)]
Tegra: Remove unused/non-existent spl linker script reference

Tegra builds use the common u-boot-spl.lds now.

Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
7 years agoTegra: T30: Beaver: Fix board/board_name env vars, s/b beaver, not cardhu
Tom Warren [Tue, 16 Apr 2013 22:57:51 +0000 (15:57 -0700)]
Tegra: T30: Beaver: Fix board/board_name env vars, s/b beaver, not cardhu

Did a 'strings u-boot-dtb-tegra.bin | less' and saw that both
board and board_name == beaver. Didn't test as I have no T30
Beaver board here.

Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
7 years agopowerpc/mpc85xx: Clear L1 D-cache lock
York Sun [Fri, 5 Apr 2013 13:07:13 +0000 (13:07 +0000)]
powerpc/mpc85xx: Clear L1 D-cache lock

dcbi instruction has been used to clear D-cache lock. However, the cache
lock is persistent for e6500 core. Use dcblc to clear the lock explicitly.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
7 years agoSECURE BOOT - Removed deletion of TLB entries code
Ruchika Gupta [Mon, 25 Mar 2013 07:40:25 +0000 (07:40 +0000)]
SECURE BOOT - Removed deletion of TLB entries code

Boot ROM code creates TLB entries for 3.5G space before entering
the u-boot. Earlier we were deleting these entries after early
initialization of CPU. In recent past, code has been added
to invalidate all these entries before relocation of u-boot code.
So this code to delete TLB entries after CPU initialization
is no longer required.

Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com>
Acked-by: Matthew McClintock <msm@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
7 years agopowerpc/b4860qds: Add LAW Target ID and Create LAW entry for Maple
Shaveta Leekha [Mon, 25 Mar 2013 07:40:24 +0000 (07:40 +0000)]
powerpc/b4860qds: Add LAW Target ID and Create LAW entry for Maple

Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
7 years agopowerpc/p5040: fix mdio mux for 10G port
Shaohui Xie [Mon, 25 Mar 2013 07:40:21 +0000 (07:40 +0000)]
powerpc/p5040: fix mdio mux for 10G port

Current driver of p5040 assumes 10G port follows 1G port DTSEC5 in
eth port enum structure, it will assign mdio mux depend on this assumption.
This is not true with Fman V3, which added more 1G ports after port DTSEC5
in eth port enum structure, then 10G ports on p5040 will have wrong mdio mux.
So we use dynamic index for 10G ports instead of hardcoded enum value
when doing mdio mux for 10G ports.

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
7 years agopowerpc/B4: Merge B4420 and B4860 in config_mpc85xx.h
Poonam Aggrwal [Mon, 25 Mar 2013 07:40:20 +0000 (07:40 +0000)]
powerpc/B4: Merge B4420 and B4860 in config_mpc85xx.h

B4420 is a subset of B4860. Merge them in config_mpc85xx.h to simplify
the defines.
- Removed #define CONFIG_SYS_FSL_NUM_CLUSTERS as this is used nowhere.
- defined CONFIG_SYS_NUM_FM1_10GEC to 0 for B4420 as it does not have 10G.

Also move CONFIG_E6500 out of B4860QDSds.h into config_mpc85xx.h.

Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
7 years agosf: spansion: Add support for S25FL128S
Xie Xiaobo [Mon, 25 Mar 2013 07:40:19 +0000 (07:40 +0000)]
sf: spansion: Add support for S25FL128S

SPANSION recommend S25FL128S supersedes S25FL129P, and the two flash
memory have the same device ID and Memory architecture. So they can
use the same config parameters.

Signed-off-by: Xie Xiaobo <X.Xie@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
7 years agopowerpc/p2041: fix serdes reference clock frequency display for PC board
Shaohui Xie [Mon, 25 Mar 2013 07:40:18 +0000 (07:40 +0000)]
powerpc/p2041: fix serdes reference clock frequency display for PC board

PC board has different serdes clock setting with PB board, it uses same
serdes frequency setting on bank2 as on bank1. PC board can be distingushed
from PB board by checking CPLD version, if running on PC board, then fix
the serdes reference clock frequency of bank2.

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
7 years agopowerpc/b4860: fix for Serdes connectivity to SFP's
Shaveta Leekha [Mon, 25 Mar 2013 07:40:17 +0000 (07:40 +0000)]
powerpc/b4860: fix for Serdes connectivity to SFP's

Crossbar switches were wrongly programmed to
route the CPRI lanes to SFP as the connectivity table
was not correct.
Modified it correctly for SFPs connections.

Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
7 years agopowerpc/t4240qds: fix PHY reset timeout issue
Shengzhou Liu [Mon, 25 Mar 2013 07:40:15 +0000 (07:40 +0000)]
powerpc/t4240qds: fix PHY reset timeout issue

QSGMII card has different PHY address against previous SGMII card.
We check the type of card in slots and set correct PHY address to
avoid complainning "PHY reset timed out" during u-boot booting up.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
7 years agopowerpc/t4qds: Add SW7[4] in the DIP switch display
York Sun [Mon, 25 Mar 2013 07:40:14 +0000 (07:40 +0000)]
powerpc/t4qds: Add SW7[4] in the DIP switch display

SW7[4] is the new bit which controls the mapping of eMMC vs SDHC.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
7 years agoEnable XAUI interface for B4860QDS
Suresh Gupta [Mon, 25 Mar 2013 07:40:13 +0000 (07:40 +0000)]
Enable XAUI interface for B4860QDS

- Added SERDES2 PRTCLs = 0x98, 0x9E
- Default Phy Addresses for Teranetics PHY on XAUI card
The PHY addresses of Teranetics PHY on XAUI riser card are assigned
based on the slot it is in. Switches SW4[2:4] and SW6[2:4] on
AMC2PEX-2S On B4860QDS, AMC2PEX card decide the PHY addresses on slot1
        and slot2
- Configure MDIO for 10Gig Mac

Signed-off-by: Suresh Gupta <suresh.gupta@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
7 years agoboard/t4240qds, b4860qds: LAW/TLB for DCSR set to size 32M
Stephen George [Mon, 25 Mar 2013 07:40:12 +0000 (07:40 +0000)]
board/t4240qds, b4860qds: LAW/TLB for DCSR set to size 32M

Debug trace buffers are memory mapped in DCSR space beyond 4M.

Signed-off-by: Stephen George <stephen.george@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
7 years agopowerpc/p5040: enable PBL tool support
Shaohui Xie [Mon, 25 Mar 2013 07:40:11 +0000 (07:40 +0000)]
powerpc/p5040: enable PBL tool support

Provided a default RCW for P5040, then it can use PBL to build
ramboot image.

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
7 years agopowerpc/t4qds: use clock measurement for sysclk and ddr clock
Ed Swarthout [Mon, 25 Mar 2013 07:40:10 +0000 (07:40 +0000)]
powerpc/t4qds: use clock measurement for sysclk and ddr clock

Use QIXIS measurement registers to obtain sysclk and ddr clock. This
allows using non-standard clock speeds, set by directly writing to
clock chip or store the values in qixis clock data eeprom.

Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
7 years agopowerpc/qixis: add clock measurement registers
Ed Swarthout [Mon, 25 Mar 2013 07:40:09 +0000 (07:40 +0000)]
powerpc/qixis: add clock measurement registers

QIXIS includes frequency measurement functions for each major processor
clock input. After reset (and after clocks are stable), QIXIS measures
the clocks against a reference frequency and stores the results in
CLK_FREQ registers. A base register supplies a multiplier which allows
directly obtaining the measured value, without requiring knowledge of
the target system or QIXIS core frequency.

Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
7 years agopowerpc/mpc8xxx: Allow DDR overclock
York Sun [Mon, 25 Mar 2013 07:40:08 +0000 (07:40 +0000)]
powerpc/mpc8xxx: Allow DDR overclock

Allow DDR clock runs faster than SPD specifes. This may cause memory
failure, but the user should know what is going to happen when using
higher than expected DDR clock.

Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
7 years agopowerpc/chassis2: Change core numbering scheme
York Sun [Mon, 25 Mar 2013 07:40:07 +0000 (07:40 +0000)]
powerpc/chassis2: Change core numbering scheme

To align with chassis generation 2 spec, all cores are numbered in sequence.
The cores may reside across multiple clusters. Each cluster has zero to four
cores. The first available core is numbered as core 0. The second available
core is numbered as core 1 and so on.

Core clocks are generated by each clusters. To identify the cluster of each
core, topology registers are examined.

Cluster clock registers are reorganized to be easily indexed.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
7 years agopowerpc/mpc8xxx: Add T1040 and variant SoCs
York Sun [Mon, 25 Mar 2013 07:40:06 +0000 (07:40 +0000)]
powerpc/mpc8xxx: Add T1040 and variant SoCs

T1040 and variants have e5500 cores and are compliant to QorIQ Chassis
Generation 2. The major difference between T1040 and its variants is the
number of cores and the number of L2 switch ports.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
7 years agopowerpc/T4160: Merge T4160 and T4240 in config_mpc85xx.h
York Sun [Mon, 25 Mar 2013 07:40:05 +0000 (07:40 +0000)]
powerpc/T4160: Merge T4160 and T4240 in config_mpc85xx.h

T4160 is a subset of T4240. Merge them in config_mpc85xx.h to simplify
the defines. Also move CONFIG_E6500 out of t4qds.h into config_mpc85xx.h.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
7 years agopowerpc/p5040: enable NAND, SD, SPI boot support
Shaohui Xie [Mon, 25 Mar 2013 07:40:04 +0000 (07:40 +0000)]
powerpc/p5040: enable NAND, SD, SPI boot support

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
7 years agoAdd e6500 L2 replacement policy selection
James Yang [Mon, 25 Mar 2013 07:40:03 +0000 (07:40 +0000)]
Add e6500 L2 replacement policy selection

This is compile-time config.

Signed-off-by: James Yang <James.Yang@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
7 years agoT4240/ramboot: enable PBL tool for T4240
Shaohui Xie [Mon, 25 Mar 2013 07:40:02 +0000 (07:40 +0000)]
T4240/ramboot: enable PBL tool for T4240

Added a default RCW(1_28_6_12) and PBI configure file for T4240, so it can use
PBL tool to produce the ramboot image.

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
7 years agopowerpc/t4240qds: Add VDD override
York Sun [Mon, 25 Mar 2013 07:40:01 +0000 (07:40 +0000)]
powerpc/t4240qds: Add VDD override

Allow VDD voltage overriding with a command. This is an add-on feasture of
VID. To override VDD, use command vdd_override with the value of voltage
in mV, for example

vdd_override <voltage in mV, eg. 1050>

The above example will set the VDD to 1.050 volt. Any wrong value out of
range of 0.8188 to 1.2125 volt or invalid string is ignored.

In addition to the command, if overriding VDD is needed earlier in booting
process, save an variable and reboot:

setenv t4240qds_vdd_mv <voltage in mV>
saveenv

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
7 years agopowerpc/mpc85xx: check if core is disabled for showing status
York Sun [Mon, 25 Mar 2013 07:40:00 +0000 (07:40 +0000)]
powerpc/mpc85xx: check if core is disabled for showing status

"cpu <num> status" should check if core is disabled before printing
the spin table location.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
7 years agonet/phy: fix select line for TN80xx
Shaohui Xie [Mon, 25 Mar 2013 07:39:59 +0000 (07:39 +0000)]
net/phy: fix select line for TN80xx

TN80xx has same PHY ID as TN2020, but it needs different setting to register
30.93 which used to select line, so we read register 30.32 which has
bit 15:12 to indicate PHY hardware version, for TN20xx we will get 3 or 2,
for TN80xx we will get 5 or 4.

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
7 years agoEnable L2 cache parity/ECC error checking
James Yang [Mon, 25 Mar 2013 07:39:58 +0000 (07:39 +0000)]
Enable L2 cache parity/ECC error checking

Signed-off-by: James Yang <James.Yang@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
7 years agopowerpc/t4240qds: Add board detail for bdinfo command
York Sun [Mon, 25 Mar 2013 07:39:24 +0000 (07:39 +0000)]
powerpc/t4240qds: Add board detail for bdinfo command

Print more detail information including core voltage, RCW source, switch
settings, etc. with bdinfo command.

Signed-off-by: York Sun <yorksun@freescale.com>
CC: Wolfgang Denk <wd@denx.de>
CC: Tom Rini <trini@ti.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
7 years agocommon: Update cmd_bdinfo for PPC
York Sun [Tue, 14 May 2013 08:06:39 +0000 (08:06 +0000)]
common: Update cmd_bdinfo for PPC

Add board detail function to print more individual board information.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
7 years agocmd_mem: fix cp command
Masahiro Yamada [Mon, 20 May 2013 21:08:08 +0000 (21:08 +0000)]
cmd_mem: fix cp command

The "cp" command has not worked since
commit 0628ab8ec59834f98ede267edd21ddb8ba0bb57b,
because of the following lines, which set the destination
and the source to the same address.

buf = map_sysmem(addr, bytes);
src = map_sysmem(addr, bytes);

Tested-by: Tom Rini <trini@ti.com>
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
7 years agoext4: assign get_fs()->dev_desc before using it
Stephen Warren [Thu, 23 May 2013 10:22:10 +0000 (10:22 +0000)]
ext4: assign get_fs()->dev_desc before using it

Commit 50ce4c0 "fs/ext4: Support device block sizes != 512 bytes"
modified ext4fs_set_blk_dev() to calculate total_sect based on
get_fs()->dev_desc->log2blksz rather than SECTOR_SIZE. However, this
value wasn't yet assigned. Move the assignment earlier so the code
doesn't crash or hang.

Cc: Egbert Eich <eich@suse.com>
Tested-by: Tom Rini <trini@ti.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
7 years agoarm: Enable -ffunction-sections / -fdata-sections / --gc-sections
Tom Rini [Thu, 25 Apr 2013 07:40:22 +0000 (07:40 +0000)]
arm: Enable -ffunction-sections / -fdata-sections / --gc-sections

While other architectures have enabled these gcc / ld options for some
time on U-Boot itself, ARM has only been doing this on SPL.  Enable this
on full U-Boot as well now.

Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Signed-off-by: Tom Rini <trini@ti.com>
7 years agoARM: Add Seagate GoFlex Home support
Suriyan Ramasami [Thu, 11 Apr 2013 07:17:25 +0000 (07:17 +0000)]
ARM: Add Seagate GoFlex Home support

Add Seagate GoFlex Home support

Start with dockstar configuration
define support for RTC, DATE, SATA and EXT4FS

Signed-off-by: Suriyan Ramasami <suriyan.r@gmail.com>
7 years agoARM: vexpress: enable bootz and hush parser for all VExpress boards
Andre Przywara [Tue, 9 Apr 2013 02:20:33 +0000 (02:20 +0000)]
ARM: vexpress: enable bootz and hush parser for all VExpress boards

Signed-off-by: Andre Przywara <andre.przywara@linaro.org>
7 years agoARM: vexpress: add support for Versatile Express Cortex-A15-TC2
Andre Przywara [Tue, 9 Apr 2013 02:20:32 +0000 (02:20 +0000)]
ARM: vexpress: add support for Versatile Express Cortex-A15-TC2

This adds support for the Cortex-A15-TC2 core tile for the Versatile
Express board by ARM. This is mostly a copy of the A5 support file,
but will be extended later with A15 specific options.

Signed-off-by: Andre Przywara <andre.przywara@linaro.org>
7 years agoARM: vexpress: create A5 specific board config
Ryan Harkin [Tue, 9 Apr 2013 02:20:31 +0000 (02:20 +0000)]
ARM: vexpress: create A5 specific board config

This patch creates a new config for the A5 dual core tile that includes the
generic config for the Versatile Express platform.

The generic config has been modified to provide support for the Extended
Memory Map, as used on the A5 core tile.  A5 does not support the legacy
memory map.

Signed-off-by: Ryan Harkin <ryan.harkin@linaro.org>
Signed-off-by: Andre Przywara <andre.przywara@linaro.org>
7 years agoARM: vexpress: refactoring of Versatile Express CA9x4 support
Ryan Harkin [Tue, 9 Apr 2013 02:20:30 +0000 (02:20 +0000)]
ARM: vexpress: refactoring of Versatile Express CA9x4 support

The current ca9x4_ct_vxp platform contains support for a Versatile
Express motherboard with a quad core A9 core tile.

This patch separates the Versatile Express motherboard code and the
A9 specific code, to ease supporting more core tiles in the next
patches.

Andre: merged the first two of Ryan's original patches and did some
checkpatch fixes.

Signed-off-by: Ryan Harkin <ryan.harkin@linaro.org>
Signed-off-by: Andre Przywara <andre.przywara@linaro.org>
7 years agocfi_flash: return NULL for invalid base address input
Masahiro Yamada [Fri, 17 May 2013 05:50:37 +0000 (14:50 +0900)]
cfi_flash: return NULL for invalid base address input

When base address given was out of valid flash address ranges,
flash_get_info() function returned the pointer to the last
element of flash_info[i] array.

This patch changes this function to return NULL pointer
in such a case, which is more correct behaviour.

The function flash_protect_default() calls flash_protect()
immediately after flash_get_info() invocation.
With this correction, flash_protect() function would be
able to return soon, for NULL flash_info.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Signed-off-by: Stefan Roese <sr@denx.de>
7 years agocosmetic: cfi_flash: delete a space after an unary operator
Masahiro Yamada [Fri, 17 May 2013 05:50:36 +0000 (14:50 +0900)]
cosmetic: cfi_flash: delete a space after an unary operator

Linux Kernel Documentation/CodingStyle says:
 Do not add a space after unary operators such as &, *, ...

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Signed-off-by: Stefan Roese <sr@denx.de>
7 years agocfi_flash: Fix unaligned accesses to cfi_qry structure
Andrew Gabbasov [Tue, 14 May 2013 17:27:52 +0000 (12:27 -0500)]
cfi_flash: Fix unaligned accesses to cfi_qry structure

Packed structure cfi_qry contains unaligned 16- and 32-bits members,
accessing which causes problems when cfi_flash driver is compiled with
-munaligned-access option: flash initialization hangs, probably
due to data error.

Since the structure is supposed to replicate the actual data layout
in CFI Flash chips, the alignment issue can't be fixed in the structure.
So, unaligned fields need using of explicit unaligned access macros.

Signed-off-by: Andrew Gabbasov <andrew_gabbasov@mentor.com>
Reviewed-By: Albert ARIBAUD <albert.u.boot@aribaud.net>
Signed-off-by: Stefan Roese <sr@denx.de>
7 years agonand/fsl_ifc: Convert to self-init
Prabhakar Kushwaha [Thu, 4 Apr 2013 18:44:06 +0000 (18:44 +0000)]
nand/fsl_ifc: Convert to self-init

Convert NAND IFC driver to support CONFIG_SYS_NAND_SELF_INIT.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
7 years agomtd: nand: use ssize_t instead of size_t to prevent infinite loop
htbegin [Fri, 1 Mar 2013 23:00:34 +0000 (23:00 +0000)]
mtd: nand: use ssize_t instead of size_t to prevent infinite loop

When a all 0xFF buffer is passed to drop_ffs, the no-0xFF check loop
will loop forever.
After the fix, If ssize_t i = -1 and size_t l = i + 1, the value of l
will still be 0 as expected.

Signed-off-by: Tao Hou <hotforest@gmail.com>
Cc: Ben Gardiner <bengardiner@nanometrics.ca>
Cc: Scott Wood <scottwood@freescale.com>
7 years agomtd: nand: fix the partial page write condition
htbegin [Fri, 1 Mar 2013 22:59:27 +0000 (22:59 +0000)]
mtd: nand: fix the partial page write condition

When writelen is mtd->writesize - 1, it is still a partial page write

Signed-off-by: Tao Hou <hotforest@gmail.com>
Cc: Scott Wood <scottwood@freescale.com>
7 years agonand: adjust erase/read/write partition/chip size for bad blocks
Harvey Chapman [Tue, 26 Feb 2013 17:57:14 +0000 (17:57 +0000)]
nand: adjust erase/read/write partition/chip size for bad blocks

Adjust the sizes calculated for whole partition/chip operations by
removing the size of bad blocks so we don't try to erase/read/write
past a partition/chip boundary.

Signed-off-by: Harvey Chapman <hchapman@3gfp.com>
7 years agonand/fsl_elbc: detect page size at runtime
Scott Wood [Tue, 26 Feb 2013 13:00:50 +0000 (13:00 +0000)]
nand/fsl_elbc: detect page size at runtime

This avoids needing a separate U-Boot config when some revisions
of a board have small-page NAND and other revisions have large-page
NAND (except for NAND SPL targets).

CONFIG_FSL_ELBC_FMR is removed -- it was never used nor documented, and
it gets in the way of this change.

Signed-off-by: Scott Wood <scottwood@freescale.com>