Pavel Machek [Sun, 13 Jul 2014 11:10:45 +0000 (13:10 +0200)]
socfpga: timer actually counts down
Timer on cyclone5 actually counts down. It took me a while to figure
out, as timer counting in wrong direction actually _can_ be used, it
just appears to tick at extremely high frequency in u-boot.
boards.cfg: keep it sorted filling the board field
The boards.cfg file has allowed to use "-" for the board (= 6th) field
if the board name is the same as the 7th field.
But I notice one problem.
Because tools/reformat.py sorts the lines in the simple alphabetical
order (= the order of character code), some entries for the same board
are not lined up together.
For example, "bf527-ezkit" and "bf527-ezkit-v2" share the same board.
But they are located separately because "bf527-ezkit" fills the board
field with "-" whereas "bf527-ezkit-v2" specifies it explicitely.
The similar things can be seen:
- between "trizepsive" and "polaris"
- between "RRvision" and "RRvision_LCD"
- between "korat" and "korat_perm"
- between "lwmon5" and "lcd4_lwmon5"
This commit was generated by the following command:
Eric Nelson [Wed, 9 Jul 2014 19:27:29 +0000 (12:27 -0700)]
i.MX6DL/S: add drive-strength back to pads DISP0_DAT2/DAT10
The pad settings for DISP0_DATA02 and DISP0_DAT10 were not
set in the same way as DISP0_DAT00-23, causing much flicker
in parallel RGB displays on Dual-Lite and Solo processors.
These settings now match the i.MX6 Dual and Quad core versions.
Note that this fixes a regression in commit b47abc3 and that
this is the second time we've had a regression on these two
pads (See commit e654ddf).
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com> Acked-by: Otavio Salvador <otavio@ossystems.com.br>
Michal Simek [Wed, 9 Jul 2014 14:10:49 +0000 (16:10 +0200)]
doc: Add zynq fragment to git-mailrc file
This is a MIME GnuPG-signed message. If you see this text, it means that
your E-mail or Usenet software does not support MIME signed messages.
The Internet standard for MIME PGP messages, RFC 2015, was published in 1996.
To open this message correctly you will need to install E-mail or Usenet
software that supports modern Internet standards.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Fabio Estevam [Fri, 13 Jun 2014 04:42:37 +0000 (01:42 -0300)]
mx6: soc: Update the comments of set_ldo_voltage()
Commit 3d622b78 (mx6: soc: Introduce set_ldo_voltage()) introduces
set_ldo_voltage() function that can be used to set the voltages
of any of the three LDO regulators controlled by the PMU_REG_CORE register.
Prior to this commit there was a single set_vddsoc() which only configured the
VDDSOC regulator.
Update the comments to align with the new set_ldo_voltage() implementation.
Marek Vasut [Thu, 26 Jun 2014 09:01:30 +0000 (11:01 +0200)]
ARM: m53evk: add needed commands and options
- "env ask", "env grep" and "setexpr" are needed for commissioning
- add support for ext4 file systems
- adjust default environment to use ext4 commands
- add write support for (V)FAT and EXT4
- add bitmap and splashscreen support
- print timestamp information for images
Signed-off-by: Marek Vasut <marex@denx.de> Signed-off-by: Wolfgang Denk <wd@denx.de> Cc: Stefano Babic <sbabic@denx.de>
Marek Vasut [Thu, 26 Jun 2014 09:01:27 +0000 (11:01 +0200)]
ARM: m28evk: add needed commands and options
- "env ask", "env grep" and "setexpr" are needed for commissioning
- add support for ext4 file systems
- adjust default environment to use ext4 commands
- add write support for (V)FAT and EXT4
- add bitmap and splashscreen support
- print timestamp information for images
Signed-off-by: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de>
Tyler Baker [Mon, 23 Jun 2014 18:11:29 +0000 (11:11 -0700)]
TI:omap3: enable CONFIG_CMD_DHCP for omap3_beagle
The following patch re-enables the dhcp functionality on omap3_beagle.
It was removed with df4dbb5df6ab1c1d27b3fd4acbaad69b47095daf when
omap3_beagle was converted to use ti_omap3_common.h. I have tested
beagleboard and beagleboard-xm with this patch and confirmed dhcp is
working.
Commit "2842c1c fit: add sha256 support" badly increased
memory footprint, so some of our boards did not build anymore.
Since monitor base must not be changed I removed some commands
to save memory.
Maybe making sha256 optional for fit would be an option for
the future since it really has some beefy footprint.
Vasili Galka [Mon, 30 Jun 2014 10:00:12 +0000 (13:00 +0300)]
blackfin: Add more dcache functions
Add invalidate_dcache_range() and flush_dcache_range() for the blackfin
architecture. Such functions already exist on this arch with different
names, so just forward the call.
This fixes the build of bf609-ezkit board as it uses
drivers/net/designware.c which requires the above functions.
Vasili Galka [Mon, 30 Jun 2014 09:59:41 +0000 (12:59 +0300)]
m68k: Fix incorrect memory access on M5235
The csarX and cscrX registers in the fbcs_t struct are 16-bit for
CONFIG_M5235 and 32-bit wide otherwise. The code in cpu_init.c
accessed them always as 32-bit, effectively creating a wrong memory
access on M5235. Fixed that by choosing out_be16/out_be32 depending
on whether CONFIG_M5235 is defined or not.
Cc: Jason Jin <Jason.jin@freescale.com> Signed-off-by: Vasili Galka <vvv444@gmail.com>
The option can be used to save the environment in spi flash.
Implementation code is already exist in command/env_sf.c. But
the documentation is missing.
This patch add the details for this option to the README file.
Signed-off-by: Josh Wu <josh.wu@atmel.com> Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Wu, Josh [Tue, 24 Jun 2014 09:31:02 +0000 (17:31 +0800)]
env_fat: use get_device_and_partition() during env save and load
Use get_device_and_partition() is better since:
1. It will call the device initialize function internally. So we can
remove the mmc intialization code to save many lines.
2. It is used by fatls/fatload/fatwrite. So saveenv & load env should
use it too.
3. It can parse the "D:P", "D", "D:", "D:auto" string to get correct
device and partition information by run-time.
Also we remove the FAT_ENV_DEVICE and FAT_ENV_PART. We use a string:
FAT_ENV_DEVICE_AND_PART.
For at91sam9m10g45ek, it is "0". That means use device 0 and if:
a)device 0 has no partition table, use the whole device as a FAT file
system.
b)device 0 has partittion table, use the partition #1.
Refer to the commit: 10a37fd7a4 for details of device & partition string.
Signed-off-by: Josh Wu <josh.wu@atmel.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
am43xx: Update EMIF DDR3 Configuration for AM43x GP
* Boot failures have been discovered due to a combination of routing issues and
non optimal ddr3 timings in the EMIF
* Since ddr3 timings are different after significant board layout changes
different timings are required for alpha, beta and production boards.
Signed-off-by: Franklin S. Cooper Jr <fcooper@ti.com>
Felipe Balbi [Thu, 26 Jun 2014 21:38:05 +0000 (16:38 -0500)]
board: ti: dra7xx: add mux data for UART3
J6 EVM can be built with UART3 as console, but currently
there's nothing muxing UART3 correctly. Likely this only
works because, based on commit log, author was only testing
with UART3 boot and - I assume - ROM code leave UART3 correctly
muxed in that case.
If we want to boot from MMC and still use UART3 as console,
then we need to mux those signals correctly.
Masahiro Yamada [Tue, 24 Jun 2014 13:10:52 +0000 (22:10 +0900)]
build: define CPU only when arch/${ARCH}/cpu/${CPU} exists
The directory arch/${ARCH}/cpu/${CPU} does not exist
in avr32, blackfin, microblaze, nios2, openrisc, sandbox, x86.
These architectures have only one CPU type.
Defining CPU should not be required for such architectures.
This commit allows cpu field (= the 3rd field of boards.cfg)
to be kept blank.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Andreas Bießmann <andreas.devel@googlemail.com> Cc: Simon Glass <sjg@chromium.org> Cc: Sonic Zhang <sonic.zhang@analog.com> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Thomas Chou <thomas@wytron.com.tw> Cc: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
Jeroen Hofstee [Wed, 18 Jun 2014 19:22:35 +0000 (21:22 +0200)]
ARM: emif4: wait for CM_DLL_READYST to be set
The code intends for the CM_DLL_READYST to be set, but
actually polls till any bit is set since the logical
AND is used instead of the bitwise one is used. Fix it.
buildman: fix to display warning message for missing [toolchain] section
Toolchains.__init__ is expected to display a warning message
when the [toolchain] section is missing from ~/.buildman file.
But it never works.
In that case, instead, buildmain fails with an error message
which is difficult to understand:
Traceback (most recent call last):
File "tools/buildman/buildman", line 126, in <module>
control.DoBuildman(options, args)
File "/home/foo/u-boot/tools/buildman/control.py", line 78, in DoBuildman
toolchains = toolchain.Toolchains()
File "/home/foo/u-boot/tools/buildman/toolchain.py", line 106, in __init__
config_fname)
NameError: global name 'config_fname' is not defined
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Simon Glass <sjg@chromium.org> Acked-by: Simon Glass <sjg@chromium.org>
Simon Glass [Thu, 12 Jun 2014 05:27:09 +0000 (23:27 -0600)]
patman: Only apply patches when we know the original HEAD
When patman applies the patches it checks out a new branch, uses 'git am'
to apply the patches one by one, and then tries to go back to the old
branch. If you try this when the branch is 'undefined', this doesn't work
as patman cannot restore the correct branch after applying the patches.
It seems that 'undefined' is created by git and is persistent after it is
created, so that you can end up on quite an old branch.
Add a check for the 'undefined' branch to avoid this.
Reported-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Signed-off-by: Simon Glass <sjg@chromium.org>
Chin Liang See [Tue, 10 Jun 2014 07:23:45 +0000 (02:23 -0500)]
socfpga: Relocate arch common functions away from board
To move the arch common function away from board folder to
arch/arm/cpu/armv7/socfpga folder. Its to avoid code duplication
for other non Altera dev kit which is using socfpga device.
Signed-off-by: Chin Liang See <clsee@altera.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Detlev Zundel <dzu@denx.de> Cc: Pavel Machek <pavel@denx.de> Cc: Dinh Nguyen <dinguyen@altera.com> Acked-by: Detlev Zundel <dzu@denx.de>
Linus Walleij [Mon, 23 Jun 2014 09:15:16 +0000 (11:15 +0200)]
integrator: switch to generic board
Turn on generic board for the integrators, as per the request in
the startup message. Everything just works, tested on the
Integrator/AP and Integrator/CP.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Simon Glass <sjg@chromium.org>
Chin Liang See [Tue, 10 Jun 2014 06:17:42 +0000 (01:17 -0500)]
socfpga: Adding Scan Manager driver
Scan Manager driver will be called to configure the IOCSR
scan chain. This configuration will setup the IO buffer settings
Signed-off-by: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Wolfgang Denk <wd@denx.de> CC: Pavel Machek <pavel@denx.de> Cc: Tom Rini <trini@ti.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Chin Liang See [Tue, 10 Jun 2014 06:10:21 +0000 (01:10 -0500)]
watchdog/denali: Adding DesignWare watchdog driver support
To add the DesignWare watchdog driver support. It required
information such as register base address and clock info from
configuration header file within include/configs folder.
Signed-off-by: Chin Liang See <clsee@altera.com> Cc: Anatolij Gustschin <agust@denx.de> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Heiko Schocher <hs@denx.de> Cc: Tom Rini <trini@ti.com>
In current gpio_set_value() implementation, it always sets the gpio control bit
no matter the value argument is 0 or 1. Thus the GPIOs never set to low.
This patch fixes this bug.
The address bus is used as a mask on read/write operations, so that independent
software drivers can set their GPIO bits without affecting any other pins in a
single write operation. Thus we don't need a read-modify-write to update the
register.
Signed-off-by: Axel Lin <axel.lin@ingics.com> Acked-by: Stefan Roese <sr@denx.de> Reviewed-by: Vipin Kumar <vipin.kumar@st.com> Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com>
York Sun [Mon, 23 Jun 2014 22:15:56 +0000 (15:15 -0700)]
ARMv8/ls2085a_emu: Add LS2085A emulator and simulator board support
LS2085A is an ARMv8 implementation. This adds board support for emulator
and simulator:
Two DDR controllers
UART2 is used as the console
IFC timing is tightened for speedy booting
Support DDR3 and DDR4 as separated targets
Management Complex (MC) is enabled
Support for GIC 500 (based on GICv3 arch)
Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Arnab Basu <arnab.basu@freescale.com> Signed-off-by: J. German Rivera <German.Rivera@freescale.com> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
J. German Rivera [Mon, 23 Jun 2014 22:15:55 +0000 (15:15 -0700)]
armv8/fsl-lsch3: Add support to load and start MC Firmware
Adding support to load and start the Layerscape Management Complex (MC)
firmware. First, the MC GCR register is set to 0 to reset all cores. MC
firmware and DPL images are copied from their location in NOR flash to
DDR. MC registers are updated with the location of these images.
Deasserting the reset bit of MC GCR register releases core 0 to run.
Core 1 will be released by MC firmware. Stop bits are not touched for
this step. U-boot waits for MC until it boots up. In case of a failure,
device tree is updated accordingly. The MC firmware image uses FIT format.
Signed-off-by: J. German Rivera <German.Rivera@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Lijun Pan <Lijun.Pan@freescale.com> Signed-off-by: Shruti Kanetkar <Shruti@Freescale.com>
York Sun [Mon, 23 Jun 2014 22:15:54 +0000 (15:15 -0700)]
ARMv8/FSL_LSCH3: Add FSL_LSCH3 SoC
Freescale LayerScape with Chassis Generation 3 is a set of SoCs with
ARMv8 cores and 3rd generation of Chassis. We use different MMU setup
to support memory map and cache attribute for these SoCs. MMU and cache
are enabled very early to bootst performance, especially for early
development on emulators. After u-boot relocates to DDR, a new MMU
table with QBMan cache access is created in DDR. SMMU pagesize is set
in SMMU_sACR register. Both DDR3 and DDR4 are supported.
Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com> Signed-off-by: Arnab Basu <arnab.basu@freescale.com>
Darwin Rambo [Mon, 9 Jun 2014 18:12:59 +0000 (11:12 -0700)]
arm: Add support for semihosting for armv8 fastmodel targets.
The armv8 ARM Trusted Firmware (ATF) can be used to load various ATF
images and u-boot, and does this for virtual platforms by using
semihosting. This commit extends this idea by allowing u-boot to also
use semihosting to load the kernel/ramdisk/dtb. This eliminates the need
for a bootwrapper and produces a more realistic boot sequence with
virtual models.
Though the semihosting code is quite generic, support for armv7 in
fastmodel is less useful due to the wide range of available silicon
and the lack of a free armv7 fastmodel, so this change contains an
untested armv7 placeholder for the service trap opcode.
Please refer to doc/README.semihosting for a more detailed description
of semihosting and how it is used with the armv8 virtual platforms.
Signed-off-by: Darwin Rambo <drambo@broadcom.com> Cc: trini@ti.com Cc: fenghua@phytium.com.cn Cc: bhupesh.sharma@freescale.com
Stephen Warren [Wed, 25 Jun 2014 16:57:29 +0000 (10:57 -0600)]
i2c: tegra: dump alen in debug statements
Since tegra_i2c_{read,write}'s debug() call dumps the chip address, dump
the address length (alen) too, so the address value can be correctly
interpreted.
Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Yen Lin <yelin@nvidia.com>
Stephen Warren [Wed, 25 Jun 2014 16:57:28 +0000 (10:57 -0600)]
i2c: tegra: write clean data to TX FIFO
The Tegra I2C controller's TX FIFO contains 32-bit words. If the final
FIFO entry of a transaction contains fewer than 4 bytes, the driver
currently fills the unused FIFO bytes with uninitialized data. This can
be confusing when reading back the FIFO content for debugging purposes.
Solve this by explicitly initializing the variable containing FIFO data
before filling it (partially) with data. With this change,
send_recv_packets()'s loop's if (is_write) code mirrors the else (i.e.
read) branch.
Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Yen Lin <yelin@nvidia.com>
This sequence confuses at least the AS3722 PMIC on the Jetson TK1 board,
leading to corrupted read data in some cases. Fix the driver to chain
the transactions together using repeated starts to solve this.
Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Yen Lin <yelin@nvidia.com>
Stephen Warren [Tue, 1 Jul 2014 20:22:27 +0000 (14:22 -0600)]
usb: ci_udc: use var name ep/ci_ep consistently
Almost all of ci_udc.c uses variable name "ep" for a struct usb_ep and
"ci_ep" for a struct ci_ep. This is nice and consistent, and helps people
know what type a variable is without searching for the declaration.
handle_ep_complete() doesn't do this, so fix it to be consistent.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Stephen Warren [Tue, 1 Jul 2014 22:59:08 +0000 (16:59 -0600)]
USB: gadget: atmel: zero out allocated requests
A UDC's alloc_request method should zero out the newly allocated request.
Ensure the Atmel driver does so. This issue was found by code inspection,
following the investigation of an intermittent issue with ci_udc, which
was tracked down to failing to zero out allocated requests following some
of my changes. All other UDC drivers already zero out requests in one
way or another.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
struct ci_req is a purely software structure, and needs no specific
memory alignment. Hence, allocate it with calloc() rather than
memalign(). The use of memalign() was left-over from when struct ci_req
was going to hold the aligned bounce buffer, but this is now dynamically
allocated.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Stephen Warren [Tue, 1 Jul 2014 17:41:17 +0000 (11:41 -0600)]
usb: ci_udc: remove controller.items array
There's no need to store an array of QTD pointers in the controller.
Since the calculation is so simple, just have ci_get_qtd() perform it
at run-time, rather than pre-calculating everything.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
2 QTDs are allocated for each EP. The current allocation scheme aligns
the first QTD in each pair, but simply adds the struct size to calculate
the second QTD's address. This will result in a non-cache-aligned
addresss IF the system's ARCH_DMA_MINALIGN is not 32 bytes (i.e. the
size of struct ept_queue_item).
Similarly, the original ilist_ent_sz calculation aligned the value to
ARCH_DMA_MINALIGN but didn't take the USB HW's 32-byte alignment
requirement into account. This doesn't cause a practical issue unless
ARCH_DMA_MINALIGN < 32 (which I suspect is quite unlikely), but we may
as well fix the code to be explicit, so it's obviously completely
correct.
The new value of ILIST_ENT_SZ takes all alignment requirements into
account, so we can simplify ci_{flush,invalidate}_qtd() by simply using
that macro rather than calling roundup().
Similarly, the calculation of controller.items[i] can be simplified,
since each QTD is evenly spaced at its individual alignment requirement,
rather than each pair being aligned, and entries within the pair being
spaced apart only by structure size.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Stephen Warren [Tue, 1 Jul 2014 17:41:15 +0000 (11:41 -0600)]
usb: ci_udc: lift ilist size calculations to global scope
This will allow functions other than ci_udc_probe() to make use of the
constants in a future change.
This in turn requires converting the const int variables to #defines,
since the initialization of one global const int can't depend on the
value of another const int; the compiler thinks it's non-constant if
that dependency exists.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Stephen Warren [Tue, 1 Jul 2014 17:41:14 +0000 (11:41 -0600)]
usb: ci_udc: don't assume QTDs are adjacent when transmitting ZLPs
Fix ci_ep_submit_next_request()'s ZLP transmission code to explicitly
call ci_get_qtd() to find the address of the other QTD to use. This
will allow us to correctly align each QTD individually in the future,
which may involve leaving a gap between the QTDs.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Stephen Warren [Tue, 1 Jul 2014 17:41:13 +0000 (11:41 -0600)]
usb: ci_udc: fix ci_flush_{qh,qtd} calls in ci_udc_probe()
ci_udc_probe() initializes a pair of QHs and QTDs for each EP. After
each pair has been initialized, the pair is cache-flushed. The
conversion from QH/QTD index [0..2*NUM_END_POINTS) to EP index
[0..NUM_ENDPOINTS] is incorrect; it simply subtracts 1 (which yields
the QH/QTD index of the first entry in the pair) rather than dividing
by two (which scales the range). Fix this.
On my system, this avoids cache debug prints due to requests to flush
unaligned ranges. This is caused because the flush calls happen before
the items[] array entries are initialized for all but EP0.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
projects / karo-tx-uboot.git / log