Tim Harvey [Mon, 18 May 2015 13:56:45 +0000 (06:56 -0700)]
imx: mx6: add get_cpu_temp_grade to obtain cpu temperature grade from OTP
The MX6 has a temperature grade defined by OCOTP_MEM0[7:6] which is at 0x480
in the Fusemap Description Table in the reference manual. Return this value
as well as min/max temperature based on the value.
Note that the IMX6SDLRM and the IMX6SXRM do not indicate this in the
their Fusemap Description Table however Freescale has confirmed that these
eFUSE bits match the description within the IMX6DQRM and that they will
be added to the next revision of the respective reference manuals.
This has been tested with IMX6 Automative and Industrial parts.
Tim Harvey [Mon, 18 May 2015 14:02:25 +0000 (07:02 -0700)]
imx: mx6: display max cpu frequency in print_cpuinfo()
Display the max CPU frequency as well as the current running CPU frequency
if the max CPU frequency is available and differs from the current CPU
frequency.
Before:
CPU: Freescale i.MX6Q rev1.2 at 792 MHz
After - using an 800MHz IMX6DL (running at its max)
CPU: Freescale i.MX6DL rev1.1 at 792 MHz
After - using a 1GHz IMX6Q (not running at its max):
CPU: Freescale i.MX6Q rev1.2 996 MHz (running at 792 MHz)
Cc: Stefan Roese <sr@denx.de> Cc: Eric Nelson <eric.nelson@boundarydevices.com> Cc: Heiko Schocher <hs@denx.de> Cc: Nikita Kiryanov <nikita@compulab.co.il> Cc: Jon Nettleton <jon.nettleton@gmail.com> Cc: Jason Liu <r64343@freescale.com> Cc: Ye Li <b37916@freescale.com> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Christian Gmeiner <christian.gmeiner@gmail.com> Cc: Markus Niebel <Markus.Niebel@tq-group.com> Cc: Peng Fan <b51431@freescale.com> Tested-by: Nikolay Dimitrov <picmaster@mail.bg> Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Tim Harvey [Mon, 18 May 2015 14:02:24 +0000 (07:02 -0700)]
imx: mx6: add get_cpu_speed_grade_hz func to return MHz speed grade from OTP
The IMX6 has four different speed grades determined by eFUSE SPEED_GRADING
indicated by OCOTP_CFG3[17:16] which is at 0x440 in the Fusemap Description
Table. Return this frequency so that it can be used elsewhere.
Note that the IMX6SDLRM and the IMX6SXRM do not indicate this in the
their Fusemap Description Table however Freescale has confirmed that these
eFUSE bits match the description within the IMX6DQRM and that they will
be added to the next revision of the respective reference manuals.
These have been tested with IMX6 Quad/Solo/Dual-light 800Mhz and 1GHz grades.
Tim Harvey [Mon, 18 May 2015 14:07:02 +0000 (07:07 -0700)]
arm: mx6: ddr: set fast-exit on DDR3 if pd_fast_exit specified
Commit fa8b7d66f49f0c7bd41467fe78f6488d8af6976a introduced fast-exit support
to the MMDC however enabling it on the DDR3 got missed. Make sure we enable
it on the DDR3 as well.
Gateworks uses Micron memory as well as Winbond in MX6. We have found in
testing that we need to enable fast-exit for Winbond stability. Gateworks
boards are currently the only boards using the MX6 SPL and enabling
fast-exit mode.
Peng Fan [Mon, 18 May 2015 05:37:25 +0000 (13:37 +0800)]
imx: mx6sx enable SION for i2c pin mux
Enable IOMUX_CONFIG_SION for all I2C pin mux settings, otherwise
we will get erros when doing i2c operations.
error log like the following:
"
wait_for_sr_state: failed sr=81 cr=a0 state=2020
i2c_init_transfer: failed for chip 0xb retry=1
"
Tim Harvey [Thu, 14 May 2015 18:48:04 +0000 (11:48 -0700)]
env_nand: use nand_spl_load_image for readenv if SPL
The readenv() implementation of env_nand uses the mtd layer which is
unnecessary overhead in SPL when we already have a nand_spl_load_image()
function that doesn't need it. Using this instead eliminates the need
to provide a mtd_read for SPL env as well as reduces code (4KB savings in IMX6
SPL).
Signed-off-by: Tim Harvey <tharvey@gateworks.com> Acked-by: Scott Wood <scottwood@freescale.com>
Tim Harvey [Thu, 14 May 2015 13:22:07 +0000 (06:22 -0700)]
imx: ventana: use stack relocation
Certain features we desire require a larger stack than is available by using
iRAM (most notably for us, env_mmc). Relocate the stack to DRAM so that
we can use these features.
Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Tim Harvey [Sat, 9 May 2015 01:28:37 +0000 (18:28 -0700)]
imx: ventana: detect pmic using i2c probe instead of board model
Avoid requiring board-model and probe pmic by its i2c address.
This is in preparation for being able to call pmic_setup() from SPL
and not need board type.
Tim Harvey [Sat, 9 May 2015 01:28:35 +0000 (18:28 -0700)]
imx: ventana: split out common functions between SPL and uboot
Move shared functions used by both SPL and U-Boot to common.c:
- setup_iomux_uart() and uart pad config
- gpio pad config
In the process also moved the following to common.c in preparation for
calling it from the SPL:
- split i2c setup into a shared function
- move pmic init to setup_pmic() function to call directly from
power_init_board()
- split gpio setup into early (iomux and default pin config)
and late (output configuration based on env)
Tim Harvey [Sat, 9 May 2015 01:28:34 +0000 (18:28 -0700)]
imx: ventana: default msata/pci mux to pci before PCI enumeration
PCI enumeration occurs early, before we fully configure our GPIO's. Make
sure we steer the MSATA/PCI mux to PCI in board_init to ensure PCI is
selected before enumeration.
Fabio Estevam [Wed, 11 Mar 2015 20:12:12 +0000 (17:12 -0300)]
mx6: Set shared override bit in PL310 AUX_CTRL register
Having bit 22 cleared in the PL310 Auxiliary Control register (shared
attribute override enable) has the side effect of transforming Normal
Shared Non-cacheable reads into Cacheable no-allocate reads.
Coherent DMA buffers in Linux always have a Cacheable alias via the
kernel linear mapping and the processor can speculatively load cache
lines into the PL310 controller. With bit 22 cleared, Non-cacheable
reads would unexpectedly hit such cache lines leading to buffer
corruption.
This was inspired by a patch from Catalin Marinas [1] and also from recent
discussions in the linux-arm-kernel list [2] where Russell King and Rob Herring
suggested that bootloaders should initialize the cache.
Soeren Moch [Tue, 5 May 2015 21:09:19 +0000 (23:09 +0200)]
tbs2910: only enable vga output for stdout/stderr when hdmi detected
Only enable graphical output for stdout/stderr (and a usb keyboard for stdin)
when a hdmi device is detected.
Serial console is always enabled for stdin/stdout/stderr.
Fabio Estevam [Mon, 4 May 2015 14:22:56 +0000 (11:22 -0300)]
mx6cuboxi: Pull down PAD_ENET_RXD0/RXD1
Configure PAD_ENET_RXD0/RXD1 pads as pull down because these pads are directly
connected to the Atheros 8035/8030 although they should be functional
only in the RMII mode - 8030.
Fabio Estevam [Mon, 4 May 2015 14:22:55 +0000 (11:22 -0300)]
mx6cuboxi: Fix Ethernet PHY detection problem
mx6cuboxi sometimes fails to recognize the Ethernet PHY:
Net: Phy 0 not found
The explanation for this behavior comes from from Rabeeh Khoury:
"The LED_ACT pin on the carrier-one boards had a pull down that
forces the phy address to 0x0; where on CuBox-i and the production
HummingBoard that pin is connected directly to LED that depending
on the pull down strength of the LED it might be sampled as '0' or '1' thus
the phy address might appear as either address 0x0 or 0x4."
"This is AR8035 implementation; in reset stage the LED pin is configured as
input, and pull up/down does matter. In this case it configures the PHY
address.
After reset is deasserted the same LED pin becomes output and then
according to the previous pull/up it should be active high/low"
One way to properly fix this behavior is to place external pull-up/down
resistors in the LED line, but from a software standpoint we can fix it
by telling phy_find_by_mask() to scan the PHY at addresses
0x0 and 0x4.
It is necessary to modify the configuration file for the target
board. It wasn't well documented that to enable any of the secure
boot modes, it is required to add CONFIG_SECURE_BOOT to the board
configuration file.
Nikolay Dimitrov [Wed, 22 Apr 2015 15:37:31 +0000 (18:37 +0300)]
arm: mx6: Clamp MMDC and DDR3 clocks for timing calculations
This is proposal for clamping the MMDC/DDR3 clocks to the maximum supported
frequencies as per imx6 SOC models, and for dynamically calculating valid
clock value based on mem_speed.
Currently the code uses impossible values for mem_speed (1333, 1600 MT/s) for
calculating the DDR timings, and uses fixed clock (528 or 400 MHz) which
doesn't take into account DDR3 memory limitations.
Signed-off-by: Nikolay Dimitrov <picmaster@mail.bg> Cc: Fabio Estevam <festevam@gmail.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Tim Harvey <tharvey@gateworks.com> Cc: Eric Nelson <eric.nelson@boundarydevices.com>
ARM: vf610: Initial integration for Colibri VF50/VF61
This adds initial support for Colibri VF50/VF61 based on Freescale
Vybrid SoC.
- CPU clocked at 396/500 MHz
- DDR3 at 396MHz
- for VF50, use PLL2 as memory clock (synchronous mode)
- for VF61, use PLL1 as memory clock (asynchronous mode)
- Console on UART0 (Colibri UART_A)
- Ethernet on FEC1
- PLL5 based RMII clocking (E.g. No external crystal)
- UART_A and UART_C I/O muxing
- Boot from NAND by default
Tested on Colibri VF50/VF61 booting using serial loader over UART.
Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com> Acked-by: Stefan Agner <stefan@agner.ch>
Vybrid product family consists of several rather similar SoC which
can be determined by softare during boot time. This allows use of
variable ${soc} for Linux device tree files. Detect VF5xx CPU's by
reading the CPU count register. We can determine the second number
of the CPU type (VF6x0) which indicates the presence of a L2 cache.
Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com>
ARM: vf610: Move DDR3 initialization to imx-common
In order to avoid code duplication, move the DDR3 initialization to the
common place under imx-common. Currently ROW_DIFF and COL_DIFF can be
chosen from the board file. The JEDEC timings are specified using a
common ddr3_jedec_timings structure.
Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com>
Cubox-i and Hummingboard support several MX6 SoCs: mx6solo, mx6dual-lite,
mx6dual and mx6quad. Add support for the different SoC/memory sizes
combinations.
DDR initialization values were extracted from Solid-run internal U-boot.
Tested on a CuBox-i4Pro, HummingBoard-i2eX and HummingBoard-i1.
Eric Nelson [Sun, 15 Feb 2015 23:16:07 +0000 (16:16 -0700)]
unzip: add gzwrite command to write compressed image to block device
Add gzwrite command to write gzip-compressed images to block devices.
Input must be gzip-compressed according to RFC1952, since the crc
and file size in the trailer will be confirmed during operation.
The decompressed file size must be specified on the command line
for images with decompressed sizes >= 4GiB because the trailer
only contains the low 32 bits of the original file size.
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
Tim Harvey [Fri, 3 Apr 2015 23:56:16 +0000 (16:56 -0700)]
power: pfuze100: fix LDO_EN bit value
The LDO_EN is bit 4, not value 4. This is only used on the Ventana boards so
we will change it in the header as the other values there are in terms of
values and not bit numbers.
This commit combines catching missing memory and calibration data into
one if() block. It further prints pertinent information in determining
why the failure occurred.
Signed-off-by: Pushpal Sidhu <psidhu@gateworks.com> Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Tim Harvey [Wed, 8 Apr 2015 19:55:02 +0000 (12:55 -0700)]
imx: ventana: set HDMI video in to yuv422bt656 for GW551x-A
The initial revision of the GW551x does not connect enough signals between
the HDMI receiver and the IMX6 CSI for 16bit capture mode necessary for
yuv422smp capture. Future revisions will, but for the initial rev force it
to yuv422bt656 mode which requires an 8bit video data bus.
Tim Harvey [Wed, 8 Apr 2015 19:55:01 +0000 (12:55 -0700)]
imx: ventana: use hdmiinfmt env var to override HDMI capture format
The HDMI receiver used on the GW54xx and GW551x has a 16bit video data bus
interconnect between it and the IMX6 CSI. This can be used in two different
modes, each having advantages and disadvantages. Allow the hdmiinfmt env
var to specify which format is desired (yuv422smp or yuv422bt656).
Tim Harvey [Wed, 8 Apr 2015 19:54:59 +0000 (12:54 -0700)]
imx: ventana: add 'gsc wd' command for enabling and disabling GSC watchdog
This adds information about the Gateworks System Controller to the gsc command
such as the firmware version, firmware CRC and status of the GSC watchdog
(if its enabled and if its tripped).
Additionally the 'gsc wd' command can be used to enable or disable the
watchdog with the following usage:
gsc wd enable [30|60]
gsc wd disable
Note that the GSC registers are battery-backed by the GSC coincell so once
eanbled, they remain enabled across power-cycles or until either the GSC
firmware has been updated or FLASH has been re-programmed by the Gateworks
JTAG adapter.
Tim Harvey [Wed, 8 Apr 2015 19:54:58 +0000 (12:54 -0700)]
imx: ventana: added device-tree display configuration for LVDS displays
Configure kernel device-tree for display from env var. This is useful
to specify the display present when the device-tree supports multiple
non-detectable display configurations.
Tim Harvey [Wed, 8 Apr 2015 19:54:56 +0000 (12:54 -0700)]
imx: ventana: add DT fixup for GW54xx compatibility with older kernels
Certain older kernels in use by some customers erroneously define a uart3
for GW54xx with a pinmux that conflicts with NAND. This will remove
that node to avoid such conflicts.
Tim Harvey [Wed, 8 Apr 2015 19:54:53 +0000 (12:54 -0700)]
imx: ventana: added DT fixup for GW551x-A video input
The GW551x-A revision does not have the CSI0_DATA_EN pin connected, therefore
we need to make sure that signal is not muxed to the CSI_DATA_EN signal
internally and do so by steering it to the unused GPIO5_IO20.
We do this so that the kernel device-tree can properly define the signal for
RevB and beyond boards that do have this hooked up properly and require it.
Tim Harvey [Wed, 8 Apr 2015 19:54:51 +0000 (12:54 -0700)]
imx: ventana: add mem_mb dynamic env var
Certain OS bootscripts need to know how much memory a board has to adjust
kernel parameters (namely Android). This allows those boards to determine
mem size in MB.
Tim Harvey [Wed, 8 Apr 2015 19:54:50 +0000 (12:54 -0700)]
imx: ventana: remove GSC hwmon voltage rail min/max test
The min/max of each depends not only on board but on CPU. Simplify by removing
this rarely needed and difficult to maintain feature and just display the
rails and their values.
Tim Harvey [Wed, 8 Apr 2015 19:54:45 +0000 (12:54 -0700)]
imx: ventana: Add support for GW551x
The GW551x is a small form factor board based on the IMX6 SoC that includes:
* up to 512MB DDR3 memory
* up to 2GB NAND flash
* 1x miniPCIe socket (with USB)
* HDMI out (micro-HDMI)
* HDMI in (micro-HDMI)
* TTL level I/O (supported by GW16111 breakout board):
* I2C
* 2x UART
* CAN
* 2x DIO (GPIO/PWM)
* USB OTG
Tim Harvey [Wed, 8 Apr 2015 19:54:44 +0000 (12:54 -0700)]
imx: ventana: disable IMX6 watchdogs on GW51xx RevA and RevB
A board level errata causes the IMX6 watchdog to be unstable on the GW51xx
RevA and RevB boards which can cause the watchdog to trip extremely early
(under 5seconds) under certain operating conditions. Disable the watchdog
node in the device-tree to work around this issue.
projects / karo-tx-uboot.git / log