karo-tx-uboot.git
5 years agoarm/rpi: Enable dcache
Alexander Stein [Fri, 24 Jul 2015 07:22:15 +0000 (09:22 +0200)]
arm/rpi: Enable dcache

Now that mailbox driver supports cache flush and invalidation, we can
enable dcache.

Signed-off-by: Alexander Stein <alexanders83@web.de>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Tested-by: Stephen Warren <swarren@wwwdotorg.org>
5 years agodwc2: Add dcache support
Alexander Stein [Fri, 24 Jul 2015 07:22:14 +0000 (09:22 +0200)]
dwc2: Add dcache support

This adds dcache support for dwc2. The DMA buffers must be DMA aligned and
is flushed for outgoing transactions before starting transfer. For
ingoing transactions it is invalidated after the transfer has finished.

Signed-off-by: Alexander Stein <alexanders83@web.de>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
[trini: Update to apply again on top of DM patches]
Signed-off-by: Tom Rini <trini@konsulko.com>
5 years agoarm/mach-bcm283x/mbox: Flush and invalidate dcache when using fw mailbox
Alexander Stein [Fri, 24 Jul 2015 07:22:13 +0000 (09:22 +0200)]
arm/mach-bcm283x/mbox: Flush and invalidate dcache when using fw mailbox

When using dcache the setup data for the mailbox must be actually written
into memory before calling into firmware. Thus flush and invalidate the
memory.

Signed-off-by: Alexander Stein <alexanders83@web.de>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Tested-by: Stephen Warren <swarren@wwwdotorg.org>
5 years agoARM: bcm283x: Allocate all mailbox buffers cacheline aligned
Alexander Stein [Fri, 24 Jul 2015 07:22:12 +0000 (09:22 +0200)]
ARM: bcm283x: Allocate all mailbox buffers cacheline aligned

The mailbox buffer is required to be at least 16 bytes aligned, but for
cache invalidation and/or flush it needs to be cacheline aligned.
Use ALLOC_CACHE_ALIGN_BUFFER for all mailbox buffer allocations.

Signed-off-by: Alexander Stein <alexanders83@web.de>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Tested-by: Stephen Warren <swarren@wwwdotorg.org>
5 years agoARM: bcm283x: Define CONFIG_SYS_CACHELINE_SIZE
Alexander Stein [Fri, 24 Jul 2015 07:22:11 +0000 (09:22 +0200)]
ARM: bcm283x: Define CONFIG_SYS_CACHELINE_SIZE

The cacheline is always 32 bytes for arm1176 CPUs, so define it at board
config level for cache handling code.
The ARM Cortex-A7 has a dcache line size of 64 bytes.

Signed-off-by: Alexander Stein <alexanders83@web.de>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Tested-by: Stephen Warren <swarren@wwwdotorg.org>
5 years agoarm1136/arm1176: Merge cache handling code
Alexander Stein [Fri, 24 Jul 2015 07:22:10 +0000 (09:22 +0200)]
arm1136/arm1176: Merge cache handling code

As both cores are similar merge the cache handling code for both CPUs
to arm11 directory.

Signed-off-by: Alexander Stein <alexanders83@web.de>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Tested-by: Stephen Warren <swarren@wwwdotorg.org>
[trini: Add hunk to arch/arm/cpu/arm1136/Makefile]
Signed-off-by: Tom Rini <trini@konsulko.com>
5 years agoarm1136: Remove dead code
Alexander Stein [Fri, 24 Jul 2015 07:22:09 +0000 (09:22 +0200)]
arm1136: Remove dead code

Apparently lcd_panel_disable is not defined anywhere, so no config for
an arm1136 board would have set CONFIG_LCD. Remove the unused code.

Signed-off-by: Alexander Stein <alexanders83@web.de>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Tested-by: Stephen Warren <swarren@wwwdotorg.org>
5 years agosniper: Keypad support, with recovery and fastboot key combinations
Paul Kocialkowski [Mon, 20 Jul 2015 13:17:18 +0000 (15:17 +0200)]
sniper: Keypad support, with recovery and fastboot key combinations

Using the twl4030 keypad allows booting directly into some special boot modes,
such as recovery or fastboot. the VOL+ key will trigger a boot to recovery while
the VOL- key will trigger a boot to fastboot.

The G (gesture) key remains unused at this point.

Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-by: Tom Rini <trini@konsulko.com>
5 years agosniper: Power off when the power on reason is not a valid one
Paul Kocialkowski [Mon, 20 Jul 2015 13:17:17 +0000 (15:17 +0200)]
sniper: Power off when the power on reason is not a valid one

In most cases, userspace will attempt to power off the device with HALT instead
of POWER_OFF, which triggers a reset instead of a proper power off from the
TWL4030. Hence, it is up to the bootloader to actually turn the device off when
there is no reason to turn it on.

A reboot identified with the OMAP reboot mode bits set is acceptable, as well as
a power on reason from either the power button, USB or charger plug.

Other cases should trigger a power off. Note that for the U-Boot reset command
to take effect, we have to fill-in the OMAP reboot bits.

Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-by: Tom Rini <trini@konsulko.com>
5 years agosniper: Power button reset support
Paul Kocialkowski [Mon, 20 Jul 2015 13:17:16 +0000 (15:17 +0200)]
sniper: Power button reset support

This adds support for resetting the device on a long press on the power button.

Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-by: Tom Rini <trini@konsulko.com>
5 years agosniper: Fastboot support
Paul Kocialkowski [Mon, 20 Jul 2015 13:17:15 +0000 (15:17 +0200)]
sniper: Fastboot support

This adds support for the fastboot USB gadget, including flashing to the
internal MMC and reboot to bootloader or not.

Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-by: Tom Rini <trini@konsulko.com>
[trini: Update to use Kconfig for MUSB]
Signed-off-by: Tom Rini <trini@konsulko.com>
5 years agosniper: Pass serial number through ATAG
Paul Kocialkowski [Mon, 20 Jul 2015 13:17:14 +0000 (15:17 +0200)]
sniper: Pass serial number through ATAG

Now that the serial number is correctly defined, we can pass it to the kernel
using the (legacy) ATAG method. It will be automatically passed via device-tree
when enabled.

Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-by: Tom Rini <trini@konsulko.com>
5 years agosniper: Serial number support, obtained from die ID
Paul Kocialkowski [Mon, 20 Jul 2015 13:17:13 +0000 (15:17 +0200)]
sniper: Serial number support, obtained from die ID

The OMAP3 has some die-specific ID bits that we can use to give the device a
(more or less) unique serial number. This is particularly useful for e.g. USB.

Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
5 years agosniper: OMAP3 reboot mode support
Paul Kocialkowski [Mon, 20 Jul 2015 13:17:12 +0000 (15:17 +0200)]
sniper: OMAP3 reboot mode support

This adds support for the omap3 reboot mode mechanism and exports the reboot
mode via an environment variable, that is used in the boot command to make it
possible to boot from the recovery partition.

Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-by: Tom Rini <trini@konsulko.com>
5 years agoLG Optimus Black (P970) codename sniper support
Paul Kocialkowski [Mon, 20 Jul 2015 13:17:11 +0000 (15:17 +0200)]
LG Optimus Black (P970) codename sniper support

The LG Optimus Black (P970) codename sniper is a smartphone that was designed
and manufactured by LG Electronics (LGE) and released back in 2011.

It is using an OMAP3630 SoC GP version, which allows running U-Boot and the
U-Boot SPL from the ground up. This port is aimed at running an Android version
such as Replicant, the fully free Android distribution. However, support for
upstream Linux with device-tree and common GNU/Linux distros boot commands
could be added in the future.

For more information about the journey to freeing this device, please read the
series of blog posts at:
http://code.paulk.fr/article20/a-hacker-s-journey-freeing-a-phone-from-the-ground-up-first-part

Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-by: Tom Rini <trini@konsulko.com>
[trini: Add CONFIG_OF_SUPPORT]
Signed-off-by: Tom Rini <trini@konsulko.com>
5 years agoomap3: Reboot mode support
Paul Kocialkowski [Mon, 20 Jul 2015 13:17:10 +0000 (15:17 +0200)]
omap3: Reboot mode support

Reboot mode is written in scratchpad memory before reboot in the form of a
single char, that is the first letter of the reboot mode string as passed to the
reboot function.

This mechanism is supported on OMAP3 both my the upstream kernel and by various
TI kernels.

It is up to each board to make use of this mechanism or not.

Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-by: Tom Rini <trini@konsulko.com>
5 years agoinput: twl4030: Keypad scan and input
Paul Kocialkowski [Mon, 20 Jul 2015 13:17:09 +0000 (15:17 +0200)]
input: twl4030: Keypad scan and input

This allows scanning the twl4030 keypad, storing the result in a 64-byte long
matrix with the twl4030_keypad_scan function.

Detecting a key at a given column and row is made easier with the
twl4030_keypad_key function.

Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-by: Tom Rini <trini@konsulko.com>
5 years agoinput: TWL4030 input support for power button, USB and charger
Paul Kocialkowski [Mon, 20 Jul 2015 13:17:08 +0000 (15:17 +0200)]
input: TWL4030 input support for power button, USB and charger

This adds support for detecting a few inputs exported by the TWL4030.
Currently-supported inputs are the power button, USB and charger presence.
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
5 years agopower: twl4030: Power off support
Paul Kocialkowski [Mon, 20 Jul 2015 13:17:07 +0000 (15:17 +0200)]
power: twl4030: Power off support

This adds support for powering off (the omap3 SoC) from the twl4030. This is
especially useful when the kernel does not actually power off the device using
this method but reboots and leaves it up to the bootloader to actually turn the
power off.
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Przemyslaw Marczak <p.marczak@samsung.com>
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
5 years agolpc32xx: devkit3250: add spl build support
Vladimir Zapolskiy [Fri, 17 Jul 2015 22:47:11 +0000 (01:47 +0300)]
lpc32xx: devkit3250: add spl build support

The change adds SPL build support to Timll DevKit3250 board, the
generated SPL image can be uploaded over UART5, JTAG or stored on
NAND. SPL is designed to load U-boot image from NAND.

All new NAND chip defines in board configuration are needed by
SPL NAND "simple" framework, the framework is used to reduce
potentially duplicated code from LPC32xx SLC NAND driver.

Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
5 years agolpc32xx: devkit3250: update of board configuration
Vladimir Zapolskiy [Fri, 17 Jul 2015 22:47:10 +0000 (01:47 +0300)]
lpc32xx: devkit3250: update of board configuration

This change adds more peripherals to Timll DevKit3250 board, namely
MAC and SMSC phy, SLC NAND, GPIO, SPI and I2C.

Also the default serial console is changed to UART5, added an option
to pass device tree blob by means of bootm, predefined environment
variables are slightly extended and reserved space on NAND to store
user defined U-boot environment.

Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
5 years agonand: lpc32xx: add SLC NAND controller support
Vladimir Zapolskiy [Sat, 18 Jul 2015 00:07:52 +0000 (03:07 +0300)]
nand: lpc32xx: add SLC NAND controller support

The change adds support of LPC32xx SLC NAND controller.

LPC32xx SoC has two different mutually exclusive NAND controllers to
communicate with single and multiple layer chips.

This simple driver allows to specify NAND chip timings and defines
custom read_buf()/write_buf() operations, because access to 8-bit data
register must be 32-bit aligned.

Support of hardware ECC calculation is not implemented (data
correction is always done by software), since it requires a working
DMA engine.

The driver can be included to an SPL image.

Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Acked-by: Scott Wood <scottwood@freescale.com>
Tested-by: Sylvain Lemieux <slemieux@tycoint.com>
5 years agospl: nand: simple: replace readb() with chip specific read_buf()
Vladimir Zapolskiy [Fri, 17 Jul 2015 22:47:08 +0000 (01:47 +0300)]
spl: nand: simple: replace readb() with chip specific read_buf()

Some NAND controllers define custom functions to read data out,
respect this in order to correctly support bad block handling in
simple SPL NAND framework.

NAND controller specific read_buf() is used even to read 1 byte in
case of connected 8-bit NAND device, it turns out that read_byte()
may become outdated.

Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Cc: Tom Rini <trini@konsulko.com>
Cc: Tom Warren <twarren@nvidia.com>
Acked-by: Scott Wood <scottwood@freescale.com>
5 years agoimage: fix Android ramdisk support when dtb is specified
Rob Herring [Fri, 17 Jul 2015 15:57:17 +0000 (10:57 -0500)]
image: fix Android ramdisk support when dtb is specified

If a dtb is specified on the command-line, the Android boot image ramdisk
will not be found. Fix this so that we can specify the ramdisk address and
dtb address. The syntax is to enter the Android boot image address for
both the kernel and ramdisk.

Signed-off-by: Rob Herring <robh@kernel.org>
5 years agoJFFS2: Use merge sort when parsing filesystem
Mark Tomlinson [Wed, 1 Jul 2015 04:38:29 +0000 (16:38 +1200)]
JFFS2: Use merge sort when parsing filesystem

When building the file system the existing code does an insertion into
a linked list. It attempts to speed this up by keeping a pointer to
where the last entry was inserted but it's still slow.

Now the nodes are just inserted into the list without searching
through for the correct place. This unsorted list is then sorted once
using mergesort after all the entries have been added to the list.
This speeds up the scanning of the flash file system considerably.

Signed-off-by: Mark Tomlinson <mark.tomlinson@alliedtelesis.co.nz>
5 years agoJFFS2: Use CLEANMARKER to reduce scanning time
Mark Tomlinson [Wed, 1 Jul 2015 04:38:28 +0000 (16:38 +1200)]
JFFS2: Use CLEANMARKER to reduce scanning time

If a sector has a CLEANMARKER at the beginning, it indicates that the
entire sector has been erased. Therefore, if this is found, we can skip the
entire block. This was not being done before this patch.

The code now does the same as the kernel does when encountering a
CLEANMARKER. It still checks that the next few words are FFFFFFFF, and if
so, the block is assumed to be empty, and so is skipped.

Signed-off-by: Mark Tomlinson <mark.tomlinson@alliedtelesis.co.nz>
5 years agoJFFS2: Change scansize to match linux kernel
Mark Tomlinson [Wed, 1 Jul 2015 04:38:27 +0000 (16:38 +1200)]
JFFS2: Change scansize to match linux kernel

The scan code is similar to the linux kernel, but the kernel defines a much
smaller size to scan through before deciding a sector is blank. Assuming
that what is in the kernel is OK, make these two match.

On its own, this change makes no difference to scanning of any sectors
which have a clean marker at the beginning, since the entire sector is not
blank.

Signed-off-by: Mark Tomlinson <mark.tomlinson@alliedtelesis.co.nz>
5 years agoJFFS2: Optimize building lists during scan
Mark Tomlinson [Wed, 1 Jul 2015 04:38:26 +0000 (16:38 +1200)]
JFFS2: Optimize building lists during scan

If the flash is slow, reading less from the flash into buffers makes
the process faster.

Signed-off-by: Mark Tomlinson <mark.tomlinson@alliedtelesis.co.nz>
5 years agoJFFS2: Improve speed reading flash files
Mark Tomlinson [Wed, 1 Jul 2015 04:38:25 +0000 (16:38 +1200)]
JFFS2: Improve speed reading flash files

jffs2_1pass_read_inode() would read the entire data for each node
in the filesystem, regardless of whether it was part of the file
to be loaded or not. By only reading the header data for an inode,
and then reading the data only when it is found to be part of the
file to be loaded, much copying of data is saved.

jffs2_1pass_list_inodes() read each inode for every file in the
directory into a buffer. By using NULL as a buffer pointer, NOR
flash simply returns a pointer, and therefore avoids a memory copy.

Signed-off-by: Mark Tomlinson <mark.tomlinson@alliedtelesis.co.nz>
5 years agoJFFS2: Only list each directory entry once
Mark Tomlinson [Wed, 1 Jul 2015 04:38:24 +0000 (16:38 +1200)]
JFFS2: Only list each directory entry once

If multiple versions of a file exist, only the most recent version
should be used. The scheme to write 0 for the inode in older versions
did not work, since this would have required writing to flash.

The only time this caused an issue was listing a directory, where older
versions of the file would still be seen. Since the directory entries
are sorted, just look at the next entry in the list, and if it's the same
move to that entry instead.

Signed-off-by: Mark Tomlinson <mark.tomlinson@alliedtelesis.co.nz>
5 years agoJFFS2: Speed up and fix comparison functions
Mark Tomlinson [Wed, 1 Jul 2015 04:38:23 +0000 (16:38 +1200)]
JFFS2: Speed up and fix comparison functions

Copying complete nodes from flash can be slow if the flash is slow
to read. By only reading the data needed, the sorting operation can
be made much faster.

The directory entry comparison function also had a two bugs. First, it
did not ensure the name was copied, so the name comparison may have
been faulty (although it would have worked with NOR flash).  Second,
setting the ino to zero to ignore the entry did not work, since this
was either writing to a temporary buffer, or (for NOR flash) directly
to flash. Either way, the change was not remembered.

Signed-off-by: Mark Tomlinson <mark.tomlinson@alliedtelesis.co.nz>
5 years agoJFFS2: Return early when file read not necessary
Mark Tomlinson [Wed, 1 Jul 2015 04:38:22 +0000 (16:38 +1200)]
JFFS2: Return early when file read not necessary

If a destination is not provided, jffs2_1pass_read_inode() only
returns the length of the file. In this case, avoid reading all
the data nodes, and return as soon as the length of the file is
known.

Signed-off-by: Mark Tomlinson <mark.tomlinson@alliedtelesis.co.nz>
5 years agoarm: bcmcygnus: Enable Ethernet support
Jiandong Zheng [Wed, 15 Jul 2015 23:28:14 +0000 (16:28 -0700)]
arm: bcmcygnus: Enable Ethernet support

Enable BCM SF2 ethernet and PHY for BCM Cygnus SoC

Signed-off-by: Jiandong Zheng <jdzheng@broadcom.com>
Signed-off-by: Steve Rae <srae@broadcom.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
5 years agoarm, at91: support for sam9260 based smartweb board
Heiko Schocher [Mon, 29 Jun 2015 07:10:48 +0000 (09:10 +0200)]
arm, at91: support for sam9260 based smartweb board

add support for the at91sam9260 based board smartweb from
siemens. SPL is used without serial support, as this
SoC has only 4k sram for running SPL. Here a U-Boot
bootlog:

RomBOOT
>

U-Boot 2015.07-rc2-00109-g4ae828c (Jun 15 2015 - 09:31:16 +0200)

CPU: AT91SAM9260
Crystal frequency:   18.432 MHz
CPU clock        :  198.656 MHz
Master clock     :   99.328 MHz
       Watchdog enabled
DRAM:  64 MiB
WARNING: Caches not enabled
NAND:  256 MiB
In:    serial
Out:   serial
Err:   serial
Net:   macb0
Hit any key to stop autoboot:  0
U-Boot>

Signed-off-by: Heiko Schocher <hs@denx.de>
5 years agonand, atmel: remove udelay in spl_nand_erase_one()
Heiko Schocher [Mon, 29 Jun 2015 07:10:47 +0000 (09:10 +0200)]
nand, atmel: remove udelay in spl_nand_erase_one()

remove unneeded udelay() in this function, as we use
the dev_ready pin.

Signed-off-by: Heiko Schocher <hs@denx.de>
Acked-by: Scott Wood <scottwood@freescale.com>
5 years agospl, common, serial: build SPL without serial support
Heiko Schocher [Mon, 29 Jun 2015 07:10:46 +0000 (09:10 +0200)]
spl, common, serial: build SPL without serial support

This patch enables building SPL without
CONFIG_SPL_SERIAL_SUPPORT support.

Signed-off-by: Heiko Schocher <hs@denx.de>
[trini: Ensure we build arch/arm/imx-common on mx28]
Signed-off-by: Tom Rini <trini@konsulko.com>
5 years agonet: e1000: Increase autoneg timeout to 8 seconds
Stefan Roese [Tue, 11 Aug 2015 15:12:44 +0000 (17:12 +0200)]
net: e1000: Increase autoneg timeout to 8 seconds

The current 4.5 timeout for the autonegotiation are not enough to
complete it on my platform. Using the Intel E1000 PCIe card in the
Marvell db-mv784mp-gp eval board. So lets increase the timeout to
8 seconds.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Simon Glass <sjg@chromium.org>
5 years agotftp.c: fix CONFIG_TFTP_TSIZE for small files
Max Krummenacher [Wed, 5 Aug 2015 15:17:05 +0000 (17:17 +0200)]
tftp.c: fix CONFIG_TFTP_TSIZE for small files

CONFIG_TFTP_TSIZE should limit a tftp downloads progress to 50 '#'
chars. Make this work also for small files.

If the file size is small, i.e. smaller than 2 tftp block sizes the
number of '#' can get much larger. i.e. with a 1 byte file 65000
characters are printed, with a 512 byte file around 500.

When using CONFIG TFTP BLOCKSIZE together with CONFIG_IP_DEFRAG the
issue is more notable.

Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
5 years agoport vexpress to use distro boot commands
Dennis Gilmore [Sun, 28 Jun 2015 19:05:12 +0000 (14:05 -0500)]
port vexpress to use distro boot commands

remove options defined in the distro defaults
add distro bot commands
set scriptaddr value

Signed-off-by: Dennis Gilmore <dennis@ausil.us>
5 years agoMove setting CONFIG_BOOTP_VCI_STRING to before including the vexpress-common header
Dennis Gilmore [Sun, 28 Jun 2015 19:05:11 +0000 (14:05 -0500)]
Move setting CONFIG_BOOTP_VCI_STRING to before including the vexpress-common header

Signed-off-by: Dennis Gilmore <dennis@ausil.us>
5 years agoPXE: if a board has set its own value for CONFIG_BOOTP_VCI_STRING do not set the...
Dennis Gilmore [Sun, 28 Jun 2015 19:05:10 +0000 (14:05 -0500)]
PXE: if a board has set its own value for CONFIG_BOOTP_VCI_STRING do not set the default one. Use the board set value instead

Signed-off-by: Dennis Gilmore <dennis@ausil.us>
5 years agoARM: highbank: remove DRAM bank setup
Rob Herring [Sat, 20 Jun 2015 23:29:55 +0000 (00:29 +0100)]
ARM: highbank: remove DRAM bank setup

On the highbank platform the SoC's management controller firmware
will probe the DRAM modules and populates the initial device tree with
the correct values. Therefore the memory sizes in the DT are already
correct, so remove U-Boot's DRAM bank setup so the memory node is not
"fixed up" by u-boot.

Signed-off-by: Rob Herring <robh@kernel.org>
Signed-off-by: Andre Przywara <osp@andrep.de>
5 years agodm: pmic: max77686: Correct two typos in a comment
Simon Glass [Sun, 9 Aug 2015 15:10:57 +0000 (09:10 -0600)]
dm: pmic: max77686: Correct two typos in a comment

These were pointed out in review but I missed them.

Signed-off-by: Simon Glass <sjg@chromium.org>
5 years agopower: regulator: max77686 correct variable type
Peng Fan [Tue, 28 Jul 2015 14:47:08 +0000 (22:47 +0800)]
power: regulator: max77686 correct variable type

The return type of pmic_read and pmic_write is signed int, so
correct variable 'ret' from type unsigned int to int.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Przemyslaw Marczak <p.marczak@samsung.com>
5 years agofsl: common: pfuze: no use original pfuze code if DM_PMIC
Peng Fan [Fri, 7 Aug 2015 08:43:46 +0000 (16:43 +0800)]
fsl: common: pfuze: no use original pfuze code if DM_PMIC

If enable DM PMIC and REGULATOR, we should not use original power
framework. So need to comment out the pfuze code for original power
framework, when CONFIG_DM_PMIC_PFUZE100 defined.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Przemyslaw Marczak <p.marczak@samsung.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
5 years agopower: regulator: add pfuze100 support
Peng Fan [Fri, 7 Aug 2015 08:43:45 +0000 (16:43 +0800)]
power: regulator: add pfuze100 support

1. Add new regulator driver pfuze100.
   * Introduce struct pfuze100_regulator_desc for maintaining info
     for one regulator.
2. Add new Kconfig entry DM_REGULATOR_PFUZE100 for pfuze100.
3. This driver intends to support PF100, PF200 and PF3000.
4. Add related macro definition in pfuze header file.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Przemyslaw Marczak <p.marczak@samsung.com>
Cc: Simon Glass <sjg@chromium.org>
5 years agopower: pmic: pfuze100 support driver model
Peng Fan [Fri, 7 Aug 2015 08:43:44 +0000 (16:43 +0800)]
power: pmic: pfuze100 support driver model

1. Support driver model for pfuze100.
2. Introduce a new Kconfig entry DM_PMIC_PFUZE100 for pfuze100
3. This driver intends to support PF100, PF200 and PF3000, so add
   the device id into the udevice_id array.
4. Rename PMIC_NUM_OF_REGS macro to PFUZE100_NUM_OF_REGS.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Przemyslaw Marczak <p.marczak@samsung.com>
Cc: Simon Glass <sjg@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
5 years agopower: regulator: update comments for regulator-name
Peng Fan [Fri, 7 Aug 2015 08:43:43 +0000 (16:43 +0800)]
power: regulator: update comments for regulator-name

We do not need that "regulator-name" property must be provided in dts.
If "regulator-name" property is not provided in dts, node name
will chosen for settings '.name' field of uc_pdata.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Przemyslaw Marczak <p.marczak@samsung.com>
Cc: Simon Glass <sjg@chromium.org>
5 years agopower: regulator use node name when no regulator-name
Peng Fan [Fri, 7 Aug 2015 08:43:42 +0000 (16:43 +0800)]
power: regulator use node name when no regulator-name

If there is no property named 'regulator-name' for regulators,
choose node name instead, but not directly return failure value.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Przemyslaw Marczak <p.marczak@samsung.com>
Cc: Simon Glass <sjg@chromium.org>
5 years agopower: pfuze100 correct SWBST macro definition
Peng Fan [Fri, 7 Aug 2015 08:43:41 +0000 (16:43 +0800)]
power: pfuze100 correct SWBST macro definition

According to datasheet, SWBST_MODE starts from bit 2 and it occupies 2 bits.
So SWBST_MODE_MASK should be 0xC, and SWBST_MODE_xx should be ([mode] << 2).

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Przemyslaw Marczak <p.marczak@samsung.com>
Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
5 years agommc: dw_mmc: Avoid using printf() for errors
Simon Glass [Fri, 7 Aug 2015 02:16:27 +0000 (20:16 -0600)]
mmc: dw_mmc: Avoid using printf() for errors

The dw_mmc driver uses printf() in various places.

These bloat the code and cause problems for SPL. Use debug() where possible
and try to return a useful error code instead.

panto: Small rework to make it apply against top of tree.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Pantelis Antoniou <pantelis.antoniou@konsulko.com>
Acked-by: Jaehoon Chung <jh80.chung@samsung.com>
5 years agonet: phy: broadcom: Add BCM Cygnus PHY
Jiandong Zheng [Wed, 15 Jul 2015 23:28:13 +0000 (16:28 -0700)]
net: phy: broadcom: Add BCM Cygnus PHY

Add Ethernet PHY for BCM Cygnus SoC

Signed-off-by: Jiandong Zheng <jdzheng@broadcom.com>
Signed-off-by: Steve Rae <srae@broadcom.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
5 years agonet: phy: delay only if reset handler is registered
Jörg Krause [Wed, 15 Jul 2015 13:18:22 +0000 (15:18 +0200)]
net: phy: delay only if reset handler is registered

With commit e3a77218a256edbe201112a39beeed8adcabae3f the MII bus is only
reset if a reset handler is registered. If there is no reset handler there
is no need to wait for a device to come out of the reset.

Signed-off-by: Jörg Krause <joerg.krause@embedded.rocks>
5 years agonet: phy: fix data type of phy_id
Jörg Krause [Wed, 15 Jul 2015 12:58:49 +0000 (14:58 +0200)]
net: phy: fix data type of phy_id

phy_id is declared as u32 in create_phy_by_mask and in struct phy_device.

Signed-off-by: Jörg Krause <joerg.krause@embedded.rocks>
5 years agoqoriq eth.c bugfix: handle received corrupted frames correctly
Daniel Inderbitzin [Fri, 10 Jul 2015 12:06:02 +0000 (14:06 +0200)]
qoriq eth.c bugfix: handle received corrupted frames correctly

The rxbd is not correctly handled in case of a frame physical error
(FPE) or frame size error (FSE). The rxbd must be cleared and
advanced in case of an error to avoid receive stall.

Signed-off-by: Daniel Inderbitzin <daniel.inderbitzin@gmail.com>
5 years agonet: lpc32xx: add RMII phy mode support
Vladimir Zapolskiy [Mon, 6 Jul 2015 04:22:11 +0000 (07:22 +0300)]
net: lpc32xx: add RMII phy mode support

LPC32xx MAC and clock control configuration requires some minor quirks
to deal with a phy connected by RMII.

It's worth to mention that the kernel and legacy BSP from NXP sets
SUPP_RESET_RMII == (1 << 11) bit, however the description of this bit is
missing in shared LPC32x0 User Manual UM10326 Rev. 3, July 22, 2011
and in LPC32x0 Draft User Mannual Rev. 00.27, November 20, 2008, also
in my tests an SMSC LAN8700 phy device connected over RMII seems to
work correctly without touching this bit.

Add support of RMII, if CONFIG_RMII is defined, this option is aligned
with a number of boards, which already define the same config value.

Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Tested-by: Sylvain Lemieux <slemieux@tycoint.com>
5 years agonet: lpc32xx: improve MAC configuration on reset and initialization
Vladimir Zapolskiy [Mon, 6 Jul 2015 04:22:10 +0000 (07:22 +0300)]
net: lpc32xx: improve MAC configuration on reset and initialization

This change rearranges general MAC configuration and PHY specific
configuration of MAC registers (duplex mode and speed), before this
change set bits related to PHY configuration in MAC2 and COMMAND
registers are rewritten by the following writing to the registers.

Without the change auto negotiation on boot quite often is not
completed in reasonable time:

  Waiting for PHY auto negotiation to complete......... TIMEOUT !

Additionally MAC1_SOFT_RESET clear bit is removed since it is done in
preceding lpc32xx_eth_initialize() and in lpc32xx_eth_halt(), instead
added missing MCFG_RESET_MII_MGMT on device initialization.

Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
5 years agonet: lpc32xx: connect MAC to phy with CONFIG_PHY_ADDR id
Vladimir Zapolskiy [Mon, 29 Jun 2015 00:35:12 +0000 (03:35 +0300)]
net: lpc32xx: connect MAC to phy with CONFIG_PHY_ADDR id

The lpc32xx_eth_phylib_init() function is capable to connect LPC32XX
MAC to some specified phy by phy id, by chance the single user of
lpc32xx_eth has CONFIG_PHY_ADDR set to 0, however other boards may
have non-zero CONFIG_PHY_ADDR value, fix it.

Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Acked-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
5 years agonet: lpc32xx: correct command register reset value
Vladimir Zapolskiy [Sun, 28 Jun 2015 03:03:38 +0000 (06:03 +0300)]
net: lpc32xx: correct command register reset value

According to LPC32x0 User Manual the following bits in Command
register 0x3106_0100 are defined:

  Bit    Symbol
    2  - Unused
    3  RegReset
    4   TxReset
    5   RxReset

Fix wrong (1-bit shifted right) COMMAND_RESETS value, which sets
an unused bit, but neglects RxReset.

Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Acked-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
5 years agonet: davinci_emac: don't teardown inactive rx channel
Jeroen Hofstee [Sun, 7 Jun 2015 15:30:38 +0000 (17:30 +0200)]
net: davinci_emac: don't teardown inactive rx channel

Tearing down an unitialized rx channel causes a pending address hole
event to be queued. When booting linux it will report this pending
as something like "Address Hole seen by USB_OTG  at address 57fff584",
since u-boot did not handled this interrupt. Prevent that by not
tearing down the rx channel, when not receiving.

Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
5 years agonet: Add support for Marvell 88E1510 PHY
Clemens Gruber [Sat, 6 Jun 2015 12:44:58 +0000 (14:44 +0200)]
net: Add support for Marvell 88E1510 PHY

Support the 88E1510 PHY which is very similar to the 88E1518.
I also set the INTn output and configured the LEDs.

Signed-off-by: Clemens Gruber <clemens.gruber@pqgruber.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Hao Zhang <hzhang@ti.com>
Cc: Michal Simek <michal.simek@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
5 years agonet: Improve 88E151x PHY initialization
Clemens Gruber [Sat, 6 Jun 2015 12:44:57 +0000 (14:44 +0200)]
net: Improve 88E151x PHY initialization

- The EEE fixup magic should also be enabled for RGMII
- Improved comments

Signed-off-by: Clemens Gruber <clemens.gruber@pqgruber.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Hao Zhang <hzhang@ti.com>
Cc: Michal Simek <michal.simek@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
5 years agonet: macb: add gmac multi-queue support
Wu, Josh [Wed, 3 Jun 2015 08:45:44 +0000 (16:45 +0800)]
net: macb: add gmac multi-queue support

This patch refer to linux kernel commit: d8b763e1e79f
  net/macb: add TX multiqueue support for gem
  by: Cyrille Pitchen

1. macb driver will check the register to find how many queues support for
this chip.

2. Then as we only use queue0 for tx, so we will set up all other queues
use a dummy descriptor, which USED bit is set. So those queues are not used.

Signed-off-by: Josh Wu <josh.wu@atmel.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
5 years agonet/phy: set led for rtl8211f phy
Shengzhou Liu [Thu, 21 May 2015 10:07:35 +0000 (18:07 +0800)]
net/phy: set led for rtl8211f phy

Initialize LCR rigister to configure
green LED for Link, yellow LED for Active.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
5 years agoe1000: remove unnecessary clearing of SWSM.SWSM_SMBI
Tim Harvey [Tue, 19 May 2015 17:01:20 +0000 (10:01 -0700)]
e1000: remove unnecessary clearing of SWSM.SWSM_SMBI

remove unnecessary clearing of SWSM.SWSM_SMBI when obtaining the SW
semaphore. This was introduced in 951860634fdb557bbb58e0f99215391bc0c29779
while adding i210 support and should be now resolved by releasing the
semaphore when no longer needed.

Cc: Marcel Ziswiler <marcel@ziswiler.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Aneesh Bansal <aneesh.bansal@freescale.com>
Cc: Naveen Burmi <NaveenBurmi@freescale.com>
Cc: Po Liu <po.liu@freescale.com>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Alison Wang <alison.wang@freescale.com>
Cc: Reinhard Arlt <reinhard.arlt@esd-electronics.com>
Cc: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Cc: York Sun <yorksun@freescale.com>
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
5 years agoRevert "e1000: fix sw fw sync on igb i210/i211"
Tim Harvey [Tue, 19 May 2015 17:01:19 +0000 (10:01 -0700)]
Revert "e1000: fix sw fw sync on igb i210/i211"

This reverts commit 17da7120249bfdef877f46be5bbcb3cc01212eb9.

The i210/i211 do have the SW_FW_SYNC (0x5b5c) register and this is what should
be used when acquiring the semaphore.

I believe the issue that this patch was trying to resolve is now resolved
by properly releasing the semaphore once no longer needed.

Cc: Marcel Ziswiler <marcel@ziswiler.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Aneesh Bansal <aneesh.bansal@freescale.com>
Cc: Naveen Burmi <NaveenBurmi@freescale.com>
Cc: Po Liu <po.liu@freescale.com>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Alison Wang <alison.wang@freescale.com>
Cc: Reinhard Arlt <reinhard.arlt@esd-electronics.com>
Cc: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Cc: York Sun <yorksun@freescale.com>
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
5 years agoe1000: releasing semaphore once no longer needed
Tim Harvey [Tue, 19 May 2015 17:01:18 +0000 (10:01 -0700)]
e1000: releasing semaphore once no longer needed

Once the hwsw semaphore is acquired, it must be released when access to the
hw is completed. Without this subsequent calls to acquire will timeout
obtaining the semaphore.

Cc: Marcel Ziswiler <marcel@ziswiler.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Aneesh Bansal <aneesh.bansal@freescale.com>
Cc: Naveen Burmi <NaveenBurmi@freescale.com>
Cc: Po Liu <po.liu@freescale.com>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Alison Wang <alison.wang@freescale.com>
Cc: Reinhard Arlt <reinhard.arlt@esd-electronics.com>
Cc: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Cc: York Sun <yorksun@freescale.com>
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
5 years agommc: dw_mmc: Improve handling of data transfer failure
Marek Vasut [Mon, 27 Jul 2015 20:39:38 +0000 (22:39 +0200)]
mmc: dw_mmc: Improve handling of data transfer failure

In case the data transfer failure happens, instead of returning
immediatelly, make sure the DMA is disabled, status register is
cleared and the bounce buffer is stopped.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Pantelis Antoniou <panto@antoniou-consulting.com>
Cc: Tom Rini <trini@konsulko.com>
5 years agommc: dw_mmc: Zap endless timeout
Marek Vasut [Mon, 27 Jul 2015 20:39:37 +0000 (22:39 +0200)]
mmc: dw_mmc: Zap endless timeout

Endless timeouts are bad, since if we get stuck in one, we have no
way out. Zap this one by implementing proper timeout.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Pantelis Antoniou <panto@antoniou-consulting.com>
Cc: Tom Rini <trini@konsulko.com>
5 years agommc: dw_mmc: Stop bounce buffer even in case of failure
Marek Vasut [Mon, 27 Jul 2015 20:39:36 +0000 (22:39 +0200)]
mmc: dw_mmc: Stop bounce buffer even in case of failure

The driver didn't stop the bounce buffer in case a data transfer
failed. This would lead to memory leakage if the communication
between the CPU and the card is unreliable. Add the missing call
to stop the bounce buffer.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Pantelis Antoniou <panto@antoniou-consulting.com>
Cc: Tom Rini <trini@konsulko.com>
5 years agodm: serial: Add a REQUIRE_SERIAL_CONSOLE option for boards with no serial port
Hans de Goede [Sat, 8 Aug 2015 15:45:18 +0000 (17:45 +0200)]
dm: serial: Add a REQUIRE_SERIAL_CONSOLE option for boards with no serial port

Currently the serial code assumes that there is always at least one serial
port (and panics / crashes due to null pointer dereferences when there is
none).

This makes it impossible to use u-boot on boards where there is no (debug)
serial port, because e.g. all uart pins are muxed to another function.

This commit adds a CONFIG_REQUIRE_SERIAL_CONSOLE Kconfig option, which
defaults to y (preserving existing behavior), which can be set to n on
such boards to make them work.

This commit only implements this for CONFIG_DM_SERIAL=y configs, as allowing
running without a serial port for CONFIG_DM_SERIAL=n configs is non trivial,
and is not necessary at this moment.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Simon Glass <sjg@chromium.org>
5 years agosunxi: display: Add composite video out support
Hans de Goede [Mon, 3 Aug 2015 17:20:26 +0000 (19:20 +0200)]
sunxi: display: Add composite video out support

Add composite video out support.

This only gets enabled on the Mele M3 for now, since that is were it
was tested. It will be enabled on more boards after testing.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
5 years agosunxi: display: Add support for interlaced modes
Hans de Goede [Sun, 2 Aug 2015 14:49:29 +0000 (16:49 +0200)]
sunxi: display: Add support for interlaced modes

Add support for interlaced modes, this is a preparation patch for adding
composite out support.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
5 years agosunxi: display: Add a few extra register and constant defines
Hans de Goede [Mon, 3 Aug 2015 17:45:37 +0000 (19:45 +0200)]
sunxi: display: Add a few extra register and constant defines

Add a few extra sunxi display registers and constant defines.

Also rename some existing defines (e.g. dropping _GCTRL) and make
some more generic (e.g. dropping the 2x scaling from
SUNXI_LCDC_TCON1_TIMING_V_TOTAL).

This is a preparation patch for adding composite video out support.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
5 years agosunxi: display: Correct clk_delay calculations for lcd displays
Hans de Goede [Sun, 2 Aug 2015 15:38:43 +0000 (17:38 +0200)]
sunxi: display: Correct clk_delay calculations for lcd displays

We should only subtract 2 from the vblank time when using tcon1.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
5 years agosunxi: display: Replace #ifdef-ery with helper functions
Hans de Goede [Mon, 3 Aug 2015 21:01:38 +0000 (23:01 +0200)]
sunxi: display: Replace #ifdef-ery with helper functions

All the #ifdef-ery in selecting the default and fallback monitor type is
becoming unyielding and makes the code hard to read, replace it with a few
helper functions.

This will also be useful with the upcoming CHIP board which has display
adapter daughterboards which should be runtime detectable.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
5 years agosunxi: Enable musb in host mode on the Jesurun Q5
Hans de Goede [Tue, 4 Aug 2015 21:49:17 +0000 (23:49 +0200)]
sunxi: Enable musb in host mode on the Jesurun Q5

The Jesurun Q5 has the musb hooked up to an usb-a receptacle, enable it
in host-only mode.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
5 years agosunxi: Do not add a stdout-path alias to dts on boards without a serial port
Hans de Goede [Sat, 1 Aug 2015 12:44:29 +0000 (14:44 +0200)]
sunxi: Do not add a stdout-path alias to dts on boards without a serial port

Do not add a bogus (pointing to a non existing serial port) stdout-path
alias to dts on boards without a serial port.

Note that we still define CONS_INDEX as this is used by the SPL where we do
not use DM_SERIAL and thus CONFIG_REQUIRE_SERIAL_CONSOLE is not honored.

We are getting away with this because the sun5i die actually has
an uart0, which in the A13 package is not routed to the outside,
so we are simply sending SPL bootup messages to the tx pin at the
edge of the die, and they go no further from there...

And sofar we only have one A13 board which does not have a serial
port, all others do have a serial port. This kinda makes sense since
the A13 is a much lower pincount package compared to all the other
sunxi SoCs.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
5 years agosunxi: Add CONFIG_USB0_ID_DET setting to 2 more tablets
Hans de Goede [Sat, 1 Aug 2015 12:42:40 +0000 (14:42 +0200)]
sunxi: Add CONFIG_USB0_ID_DET setting to 2 more tablets

Now that we have code to check the id-pin and detect usb-host adapters
plugged into the otg port that way, enable it on the tablets which I own.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
5 years agosunxi: usb-phy: Never power off the usb ports
Hans de Goede [Wed, 8 Jul 2015 14:44:22 +0000 (16:44 +0200)]
sunxi: usb-phy: Never power off the usb ports

USB devices are not really designed to get the power bounced off and on
at them. Esp. USB powered harddisks do not like this.

Currently we power off the USB ports both on a "usb reset" and when
booting the kernel, causing the usb-power to bounce off and then back
on again.

This patch removes the powering off calls, fixing the undesirable power
bouncing.

Note this requires some special handling for the OTG port:
1) We must skip the external vbus check if we've already enabled our own
vbus to avoid false positives
2) If on an usb reset we no longer detect that the id-pin is grounded, turn
off vbus as that means an external vbus may be present now

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
5 years agosunxi: nand: Add board configuration options
Piotr Zierhoffer [Thu, 23 Jul 2015 12:33:03 +0000 (14:33 +0200)]
sunxi: nand: Add board configuration options

When SPL_NAND_SUNXI option is selected in config, set some configuration
options for sunxi NAND.

This commit also introduces the configurable options in Kconfig.

Signed-off-by: Peter Gielda <pgielda@antmicro.com>
Signed-off-by: Tomasz Gorochowik <tgorochowik@antmicro.com>
Signed-off-by: Mateusz Holenko <mholenko@antmicro.com>
Signed-off-by: Piotr Zierhoffer <pzierhoffer@antmicro.com>
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
5 years agosunxi: nand: Add basic sunxi NAND driver for SPL with DMA support
Piotr Zierhoffer [Thu, 23 Jul 2015 12:33:02 +0000 (14:33 +0200)]
sunxi: nand: Add basic sunxi NAND driver for SPL with DMA support

This driver adds NAND support to SPL.
It was tested on Allwinner A20.

Signed-off-by: Peter Gielda <pgielda@antmicro.com>
Signed-off-by: Tomasz Gorochowik <tgorochowik@antmicro.com>
Signed-off-by: Mateusz Holenko <mholenko@antmicro.com>
Signed-off-by: Piotr Zierhoffer <pzierhoffer@antmicro.com>
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
5 years agosunxi: nand: Add pinmux and clock settings for NAND support
Karol Gugala [Thu, 23 Jul 2015 12:33:01 +0000 (14:33 +0200)]
sunxi: nand: Add pinmux and clock settings for NAND support

To enable NAND flash in sunxi SPL,
pins 0-6, 8-22 and 24 on port C are configured.

Signed-off-by: Karol Gugala <kgugala@antmicro.com>
Signed-off-by: Piotr Zierhoffer <pzierhoffer@antmicro.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
5 years agosunxi: Enable USB DRC on Wexler TAB7200
Aleksei Mamlin [Thu, 30 Jul 2015 17:33:56 +0000 (20:33 +0300)]
sunxi: Enable USB DRC on Wexler TAB7200

Enable the otg/drc usb controller on the Wexler TAB7200 tablet.

Signed-off-by: Aleksei Mamlin <mamlinav@gmail.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
5 years agoarm: socfpga: misc: Add support for printing FPGA type
Dinh Nguyen [Sat, 1 Aug 2015 01:42:10 +0000 (03:42 +0200)]
arm: socfpga: misc: Add support for printing FPGA type

Add code which uses the new functions for obtaining FPGA ID from
the scan manager. This new code prints the FPGA model attached to
the SoCFPGA during boot and sets environment variable "fpgatype",
which can be used to determine the FPGA model in U-Boot scripts.

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Signed-off-by: Marek Vasut <marex@denx.de>
5 years agoarm: socfpga: scan: Add code to get FPGA ID
Dinh Nguyen [Fri, 31 Jul 2015 16:06:50 +0000 (11:06 -0500)]
arm: socfpga: scan: Add code to get FPGA ID

Add code to get the FPGA type for Altera's SoCFPGA family of FPGA. The code
uses the scan manager to send jtag pulses that will return the FPGA ID.

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
5 years agoarm: socfpga: scan: Factor out IO chain programming
Marek Vasut [Sat, 1 Aug 2015 12:28:48 +0000 (14:28 +0200)]
arm: socfpga: scan: Factor out IO chain programming

Factor out the code which sends JTAG instruction followed by data
into separate function to tidy the code up a little.

Signed-off-by: Marek Vasut <marex@denx.de>
Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
5 years agoarm: socfpga: scan: Clean up horrible macros
Marek Vasut [Sat, 1 Aug 2015 01:18:50 +0000 (03:18 +0200)]
arm: socfpga: scan: Clean up horrible macros

Clean up the horrible macros present in the scan_manager.h . Firstly,
the function scan_mgr_io_scan_chain_prg() is static, yet all the macros
are used only within it, thus there is no point in having them in the
header file. Moreover, the macros are just making the code much less
readable, so remove them instead.

Signed-off-by: Marek Vasut <marex@denx.de>
Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
5 years agoarm: socfpga: scan: Introduce generic JTAG accessor
Marek Vasut [Sat, 1 Aug 2015 01:01:25 +0000 (03:01 +0200)]
arm: socfpga: scan: Introduce generic JTAG accessor

Introduce generic function for accessing the JTAG scan chains in the
SCC manager. Make use of this function throughout the SCC manager to
replace the ad-hoc writes to registers and make the code less cryptic.

Signed-off-by: Marek Vasut <marex@denx.de>
Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
5 years agoarm: socfpga: scan: Clean up scan_chain_engine_is_idle()
Marek Vasut [Sat, 1 Aug 2015 00:48:03 +0000 (02:48 +0200)]
arm: socfpga: scan: Clean up scan_chain_engine_is_idle()

Rework this function so it's clear that it is only polling for certain
bits to be cleared. Add kerneldoc. Fix it's return value to be either
0 on success and -ETIMEDOUT on error and propagate this through the
scan manager code.

Signed-off-by: Marek Vasut <marex@denx.de>
Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
5 years agoddr: altera: sequencer: add RW_MGR_MEM_NUMBER_OF_RANKS
Dinh Nguyen [Wed, 5 Aug 2015 03:12:32 +0000 (22:12 -0500)]
ddr: altera: sequencer: add RW_MGR_MEM_NUMBER_OF_RANKS

Fix build error for socfpga_cyclone5_defconfig:

board/altera/socfpga/wrap_sdram_config.c:245:26: error: ‘RW_MGR_MEM_NUMBER_OF_RANKS’ undeclared here (not in a function)
make[2]: *** [spl/board/altera/socfpga/wrap_sdram_config.o] Error 1

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
5 years agoddr: altera: sequencer: Clean checkpatch issues
Marek Vasut [Sun, 2 Aug 2015 17:47:01 +0000 (19:47 +0200)]
ddr: altera: sequencer: Clean checkpatch issues

Fix most of the dangling checkpatch issues, no functional change.
There are still 7 warnings, 1 checks , but those are left in place
for the sake of readability of the code.

Signed-off-by: Marek Vasut <marex@denx.de>
Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
5 years agoddr: altera: sequencer: Clean data types
Marek Vasut [Sun, 2 Aug 2015 17:42:26 +0000 (19:42 +0200)]
ddr: altera: sequencer: Clean data types

Replace uintNN_t with uNN. No functional change.

Signed-off-by: Marek Vasut <marex@denx.de>
Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
5 years agoddr: altera: sequencer: Pluck out misc macros from code
Marek Vasut [Sun, 2 Aug 2015 17:26:55 +0000 (19:26 +0200)]
ddr: altera: sequencer: Pluck out misc macros from code

Actually convert the sequencer code to use socfpga_sdram_misc_config
instead of the various macros. This is just an sed exercise here, no
manual coding needed.

This patch actually removes the need to include any board-specific
files in sequencer.c , so sequencer.c namespace is now no longer
poluted by QTS-generated macros.

Signed-off-by: Marek Vasut <marex@denx.de>
Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
5 years agoddr: altera: sequencer: Zap SEQ_T(INIT|RESET)_CNTR._VAL
Marek Vasut [Sun, 2 Aug 2015 17:24:12 +0000 (19:24 +0200)]
ddr: altera: sequencer: Zap SEQ_T(INIT|RESET)_CNTR._VAL

This is another macro used to obfuscate the real code. The
T(INIT|RESET)_CNTR._VAL is always defined, so this indirection
is unnecessary. Get rid of this.

Signed-off-by: Marek Vasut <marex@denx.de>
Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
5 years agoddr: altera: sequencer: Zap VFIFO_SIZE
Marek Vasut [Sun, 2 Aug 2015 17:21:56 +0000 (19:21 +0200)]
ddr: altera: sequencer: Zap VFIFO_SIZE

Just use READ_VALID_FIFO_SIZE directly, no need for this macro obfuscation.

Signed-off-by: Marek Vasut <marex@denx.de>
Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
5 years agoddr: altera: sequencer: Wrap misc remaining macros
Marek Vasut [Sun, 2 Aug 2015 17:18:47 +0000 (19:18 +0200)]
ddr: altera: sequencer: Wrap misc remaining macros

Introduce structure socfpga_sdram_misc_config to wrap the remaining
misc configuration values in board file. Again, introduce a function,
socfpga_get_sdram_misc_config(), which returns this the structure. This
is almost the final step toward wrapping the nasty QTS generated macros
in board files and reducing the pollution of the namespace.

Signed-off-by: Marek Vasut <marex@denx.de>
Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
5 years agoddr: altera: sequencer: Pluck out IO_* macros from code
Marek Vasut [Sun, 2 Aug 2015 17:10:58 +0000 (19:10 +0200)]
ddr: altera: sequencer: Pluck out IO_* macros from code

Actually convert the sequencer code to use socfpga_sdram_io_config
instead of the IO_* macros. This is just an sed excercise here, no
manual coding needed.

Signed-off-by: Marek Vasut <marex@denx.de>
Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
5 years agoddr: altera: sequencer: Wrap IO_* macros
Marek Vasut [Sun, 2 Aug 2015 17:00:23 +0000 (19:00 +0200)]
ddr: altera: sequencer: Wrap IO_* macros

Introduce structure socfpga_sdram_io_config to wrap the IO configuration
values in board file. Introduce socfpga_get_sdram_io_config() function,
which returns this the structure. This is another step toward wrapping
the nasty QTS generated macros in board files and reducing the pollution
of the namespace.

Signed-off-by: Marek Vasut <marex@denx.de>
Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
5 years agoddr: altera: sequencer: Pluck out RW_MGR_* macros from code
Marek Vasut [Sun, 2 Aug 2015 16:44:06 +0000 (18:44 +0200)]
ddr: altera: sequencer: Pluck out RW_MGR_* macros from code

Actually convert the sequencer code to use socfpga_sdram_rw_mgr_config
instead of the RW_MGR_* macros. This is just an sed exercise here, no
manual coding needed.

Signed-off-by: Marek Vasut <marex@denx.de>
Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>