karo-tx-uboot.git
5 years agoCPCI4052: Remove CONFIG_SYS_LONGHELP
Tom Rini [Tue, 2 Jun 2015 15:12:20 +0000 (11:12 -0400)]
CPCI4052: Remove CONFIG_SYS_LONGHELP

With the change to make sure that CONFIG_CMD_NET is enabled this board
no longer fits into the linker script:

powerpc-linux-ld.bfd: section .resetvec loaded at [fffffffc,ffffffff] overlaps section .u_boot_list loaded at [ffffff58,00000723]
powerpc-linux-ld.bfd: u-boot: section .resetvec lma 0xfffffffc adjusted to 0x724
powerpc-linux-ld.bfd: u-boot: section `.resetvec' can't be allocated in segment 0
LOAD: .data.init .text .rodata .reloc .data .u_boot_list .resetvec
powerpc-linux-ld.bfd: final link failed: File truncated

Drop CONFIG_SYS_LONGHELP to free up space.

Cc: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
5 years agospl: spl_mmc: MMC boot mode provisions checks
Paul Kocialkowski [Mon, 8 Jun 2015 21:05:09 +0000 (23:05 +0200)]
spl: spl_mmc: MMC boot mode provisions checks

This allows using only one of either raw or fs mode for SPL mmc boot, without
the need to have provisions for the other. In particular, a device may have
U-Boot installed on a file system on the mmc, without ever needing to read
U-Boot from raw memory. Thus, there is no reason to provide a sector or
partition for raw mode. This allows this behaviour and still provides a robust
fallback mechanism in case provisions for both modes are defined.

Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
5 years agospl: spl_mmc: Minor cosmetics
Paul Kocialkowski [Wed, 3 Jun 2015 16:48:51 +0000 (18:48 +0200)]
spl: spl_mmc: Minor cosmetics

This switches some printf calls to puts and avoids a test repetition.

Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
5 years agotools/env/fw_env.h: Correct include order
Peter Robinson [Wed, 17 Jun 2015 15:58:32 +0000 (16:58 +0100)]
tools/env/fw_env.h: Correct include order

When building tools-only (or env) we need to be sure that we do use
<linux/kconfig.h> and do not use <generated/autoconf.h>.  This will fix
problems such as running 'make defconfig' or 'make sandbox_config' and
then 'make tools-only'.

Based on the responses below to the thread add linux/kconfig.h higher in
the includes and drop the now unneeded autoconf.h lower down to ensure
the default environment is included correctly

http://lists.denx.de/pipermail/u-boot/2015-June/216849.html

Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
5 years agofix: samsung: common: autoboot.cmd: Correct itbcfg definition
Łukasz Majewski [Wed, 17 Jun 2015 10:49:23 +0000 (12:49 +0200)]
fix: samsung: common: autoboot.cmd: Correct itbcfg definition

This fix is necessary to avoid booting the default ITB configuration.

Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
5 years agommc_write.c: Make mmc_berase do 32bit safe 64bit math
Tom Rini [Fri, 12 Jun 2015 00:53:31 +0000 (20:53 -0400)]
mmc_write.c: Make mmc_berase do 32bit safe 64bit math

We want to see if the requested start or total block count are
unaligned.  We discard the whole numbers and only care about the
remainder.  Update the code to use div_u64_rem here and add a comment.

Cc: Hans de Goede <hdegoede@redhat.com>
Cc: Pantelis Antoniou <pantelis.antoniou@konsulko.com>
Cc: Bernhard Nortmann <bernhard.nortmann@web.de>
Reported-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
Tested-by: Bernhard Nortmann <bernhard.nortmann@web.de>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
5 years agoboard/BuR/tseries: remove lpj= from environment-variable
Hannes Petermaier [Thu, 11 Jun 2015 10:31:54 +0000 (12:31 +0200)]
board/BuR/tseries: remove lpj= from environment-variable

since we have now various processor-speeds it isn't useful anymore to
preinitialize kernels-delay loop.

Rather we want the kernel to calibrate it on every boot.
This wastes around 80ms boottime but is compatible to all CPU-speeds.

Signed-off-by: Hannes Schmelzer <oe5hpm@oevsv.at>
5 years agoboard/BuR/common: support timer5 for pwm-backlight
Hannes Petermaier [Thu, 11 Jun 2015 10:25:43 +0000 (12:25 +0200)]
board/BuR/common: support timer5 for pwm-backlight

in future we support yet another b&r am335x based board, where Timer 5 is
wired to backlight-driver.

So we introduce a new driver-type '2' to setup timer5 instead timer6.

Signed-off-by: Hannes Schmelzer <oe5hpm@oevsv.at>
Reviewed-by: Simon Glass <sjg@chromium.org>
5 years agoti: am335x/am437x/omap5 devices: Fix breakage when CONFIG_CMD_NET is not used
Cooper Jr., Franklin [Wed, 10 Jun 2015 13:54:02 +0000 (08:54 -0500)]
ti: am335x/am437x/omap5 devices: Fix breakage when CONFIG_CMD_NET is not used

Currently there is no default value for NETARGS if CONFIG_CMD_NET=y isn't set.
This results in build errors which was first discovered when trying to run
make env.

By defining a blank NETARGS these errors can be avoided.

Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com>
Tested-by: Maxin B. John <maxin.john@enea.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
5 years agoboards: tam3517-common: enable gpmc prefetch mode
Jeroen Hofstee [Sat, 30 May 2015 08:11:25 +0000 (10:11 +0200)]
boards: tam3517-common: enable gpmc prefetch mode

Since the tam3517 base board has a 16bit wide nand connected to
the gpmc, enable the prefetch mode, since that is now supported.

Cc: Scott Wood <scottwood@freescale.com>
Cc: Tom Rini <trini@konsulko.com>
Cc: pekon gupta <pekon@ti.com>
Cc: Nishanth Menon <nm@ti.com>
Cc: Daniel Mack <zonque@gmail.com>
Cc: Tapani Utriainen <tapani@technexion.com>
Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
Reviewed-by: Tom Rini <trini@konsulko.com>
5 years agomtd: OMAP: Enable GPMC prefetch mode for 16 bit access
Jeroen Hofstee [Sat, 30 May 2015 08:11:24 +0000 (10:11 +0200)]
mtd: OMAP: Enable GPMC prefetch mode for 16 bit access

commit c316f57 "mtd: OMAP: Enable GPMC prefetch mode" only enabled
prefetch mode for 8 bit nand access, this adds 16 bit as well.

Cc: Scott Wood <scottwood@freescale.com>
Cc: Tom Rini <trini@konsulko.com>
Cc: Daniel Mack <zonque@gmail.com>
Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
Reviewed-by: Tom Rini <trini@konsulko.com>
5 years agoomap_gpmc: move prefetch out of CONFIG_NAND_OMAP_ELM
Jeroen Hofstee [Sat, 30 May 2015 08:11:23 +0000 (10:11 +0200)]
omap_gpmc: move prefetch out of CONFIG_NAND_OMAP_ELM

The prefech mode is a feature of the gpmc, not the ELM. An am3517
does not have an elm, but can do prefeches, so move the code out
of the CONFIG_NAND_OMAP_ELM ifdef.

Cc: Scott Wood <scottwood@freescale.com>
Cc: Tom Rini <trini@konsulko.com>
Cc: Daniel Mack <zonque@gmail.com>
Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
Reviewed-by: Tom Rini <trini@konsulko.com>
5 years agoMSI_Primo81_defconfig: enable USB OTG port and keyboard support
Karsten Merker [Sun, 14 Jun 2015 10:08:42 +0000 (12:08 +0200)]
MSI_Primo81_defconfig: enable USB OTG port and keyboard support

The MSI Primo 81 is an Allwinner A31s-based tablet on which the
OTG port is the only accessible USB interface.  The existing
defconfig had VGA console on the LCD enabled, but was missing
keyboard support because the prerequisites for that (sunxi MUSB
support and AXP221 GPIO support) had not been available before.
All previously missing dependencies are available now, so this
patch enables keyboard support and its prerequisites in the
defconfig.

Signed-off-by: Karsten Merker <merker@debian.org>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
5 years agosun6i: cpu_reset: Do not return from cpu_reset()
Hans de Goede [Sun, 14 Jun 2015 14:53:15 +0000 (16:53 +0200)]
sun6i: cpu_reset: Do not return from cpu_reset()

Currently on sun6i after a "reset" the prompt returns and the user can
even type stuff until the watchdog triggers and does the actual reset.

This is somewhat unexpected behavior for the "reset" command, this
commit adds an endless loop to wait for the watchdog to trigger so that
we do not return to the prompt.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
5 years agosunxi: musb: Remove unused sunxi_musb_exit method
Hans de Goede [Sun, 14 Jun 2015 09:58:43 +0000 (11:58 +0200)]
sunxi: musb: Remove unused sunxi_musb_exit method

Remove the unused sunxi_musb_exit method, there is no code in u-boot
calling the exit method, and our implementation was broken as it did
not disable the clocks and asserted reset.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
5 years agosunxi: musb: Do not fully reset the controler from sunxi_musb_disable
Hans de Goede [Sun, 14 Jun 2015 09:55:28 +0000 (11:55 +0200)]
sunxi: musb: Do not fully reset the controler from sunxi_musb_disable

Fully resetting the controller is a too big hammer, and the musb_core will
then afterwards fail to communicate with any endpoints other then 0 as
too much state was cleared.

Instead report vbus low for 200ms which will effectively end the current
session without needing to do a full reset.

This fixes usb mass-storage devices no longer working after a "usb reset"

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
5 years agoomap5: Exclude more environment from SPL builds
Tom Rini [Sat, 13 Jun 2015 00:52:29 +0000 (20:52 -0400)]
omap5: Exclude more environment from SPL builds

In the cases where we make use of environment in SPL we do not need
these defaults compiled in and available.  These are taking up space
that in some cases now prevent linking, so drop.

Signed-off-by: Tom Rini <trini@konsulko.com>
5 years agoboard: add support for Vision System's Baltos Industrial PC
Yegor Yefremov [Fri, 29 May 2015 17:27:29 +0000 (19:27 +0200)]
board: add support for Vision System's Baltos Industrial PC

Vision Systems's Baltos is based on AM335x SoC
from Texas Instruments. This patch adds support
such Industrial PCs in mainline u-boot.

[ balbi@ti.com: updated original patch to current u-boot ]

Signed-off-by: Yegor Yefremov <yegorslists@googlemail.com>
Signed-off-by: Felipe Balbi <balbi@ti.com>
5 years agoARM: DRA7: emif: Fix DDR init sequence during warm reset
Lokesh Vutla [Thu, 4 Jun 2015 04:38:50 +0000 (10:08 +0530)]
ARM: DRA7: emif: Fix DDR init sequence during warm reset

Unlike OMAP5, EMIF PHY used in DRA7 will be left in unknown state after
warm reset, emif needs to be configured to bring it back to a known
state. So configure EMIF during warm reset.

Reported-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
5 years agoavr32: move CONFIG_SYS_GENERIC_BOARD to Kconfig
Masahiro Yamada [Thu, 11 Jun 2015 10:14:50 +0000 (19:14 +0900)]
avr32: move CONFIG_SYS_GENERIC_BOARD to Kconfig

Now all the AVR32 boards have been converted into Generic Board.
Select it in Kconfig and clean up defines in header files.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Andreas Bießmann <andreas.devel@googlemail.com>
5 years agoARM: AM43x: Fix MAX_RAM_BANK_SIZE
Lokesh Vutla [Wed, 10 Jun 2015 10:24:50 +0000 (15:54 +0530)]
ARM: AM43x: Fix MAX_RAM_BANK_SIZE

On AM437x-GP Evm there is 2GB of DDR3 memory available as stated in
AM437x GP EVM HardwareUser's guide http://www.ti.com/lit/ug/spruhw7/spruhw7.pdf.
But MAX_RAM_BANK_SIZE is defined as 1GB.
Fixing MAX_RAM_BANK_SIZE to 2GB on AM43xx.

Reported-by: Shivasharan Nagalikar <shivasharan.nagalikar@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
5 years agoam33xx: Re-enable SW levelling for DDR2
Tom Rini [Fri, 5 Jun 2015 10:21:11 +0000 (15:51 +0530)]
am33xx: Re-enable SW levelling for DDR2

The recent changes for hw leveling on am33xx were not intended for
DDR2 boards, only DDR3. Update emif_sdram_type to take a sdram_config
value to check against. This lets us pass in the value we would use to
configure, when we have not yet configured the board yet.  In other cases
update the call to be as functional as before and check an already
programmed value in.

Tested-by: Yan Liu <yan-liu@ti.com>
Signed-off-by: Tom Rini <trini@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
5 years agoARM: BeagleBoard-x15: Enable i2c5 clocks
Lokesh Vutla [Fri, 5 Jun 2015 09:49:21 +0000 (15:19 +0530)]
ARM: BeagleBoard-x15: Enable i2c5 clocks

On AM57xx evm I2C5 is used to detect the LCD board by reading the
EEPROM present on the bus.
Enable i2c5 clocks to help that.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
5 years agoam43xx_evm: Enable NAND boot
Tom Rini [Fri, 5 Jun 2015 09:43:46 +0000 (12:43 +0300)]
am43xx_evm: Enable NAND boot

Enable booting from NAND on the am437xx-evm.

Signed-off-by: Tom Rini <trini@ti.com>
Signed-off-by: Roger Quadros <rogerq@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
5 years agoam335x_evm: nand: Fix boot from NAND
Roger Quadros [Fri, 5 Jun 2015 09:42:21 +0000 (12:42 +0300)]
am335x_evm: nand: Fix boot from NAND

Use the correct partition names from with the Device Tree blob
and the kernel is picked up. Also use partition name instead of
number for the root filesystem in the kernel boot arguments.

Signed-off-by: Roger Quadros <rogerq@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
5 years agoam335x_evm: am44xx_evm: dra7xx_evm: nand: Fix file-system partition name
Roger Quadros [Fri, 5 Jun 2015 09:42:20 +0000 (12:42 +0300)]
am335x_evm: am44xx_evm: dra7xx_evm: nand: Fix file-system partition name

We almost always use UBIFS for user accessible NAND file systems and
the UBIFS file system might contain more than one volume within the
single NAND partition. The last NAND partition is therefore more
appropriately named as "NAND.file-system" instead of "NAND.rootfs"

The Linux kernel (as of v3.16) also uses "NAND.file-system" to name the
last NAND partition. This patch makes the partition name consistent
between u-boot and the kernel.

Signed-off-by: Roger Quadros <rogerq@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
5 years agoconfigs: am43xx_evm: Enable NAND
Roger Quadros [Fri, 5 Jun 2015 08:09:02 +0000 (11:09 +0300)]
configs: am43xx_evm: Enable NAND

AM43xx EVMs have NAND so enable it.

Signed-off-by: Roger Quadros <rogerq@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
5 years agohighbank: add custom ahci_link_up function
Mark Langsdorf [Thu, 4 Jun 2015 23:58:49 +0000 (00:58 +0100)]
highbank: add custom ahci_link_up function

The Calxeda highbank SOC needs a custom sequence to bring up SATA links,
so override ahci_link_up with custom function to handle combophy setup.

Signed-off-by: Mark Langsdorf <mark.langsdorf@gmail.com>
Signed-off-by: Richard Gibbs
Signed-off-by: Rob Herring <robh@kernel.org>
Signed-off-by: Andre Przywara <osp@andrep.de>
5 years agomx6cuboxi: Fix boot of hummingboard dual-lite
Fabio Estevam [Fri, 29 May 2015 16:00:36 +0000 (13:00 -0300)]
mx6cuboxi: Fix boot of hummingboard dual-lite

Hummingboard dual-lite is picking the incorrect calibration structure.

Fix it so that it can boot.

While at it, also fix p1_mpdgctrl1 register to match Solid-run's
setting.

Reported-by: Andrei Gherzan <andrei@gherzan.ro>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Tested-by: Andrei Gherzan <andrei@gherzan.ro>
5 years agotools/kwboot: Add parameters to set delay and timeout via cmdline
Stefan Roese [Fri, 29 May 2015 11:25:04 +0000 (13:25 +0200)]
tools/kwboot: Add parameters to set delay and timeout via cmdline

To support the Armada 38x, new values for the request-delay and the
response-timeout are needed. As the values already implemented in
this tool (for Kirkwood and Armada XP) don't seem to work here.
To make this more flexible, lets add make those 2 parameters
configurable via the cmdline. Here the new parameters:

-q <req-delay>:  use specific request-delay
-s <resp-timeo>: use specific response-timeout

For the Marvell DB-88F6820 these values are known to work:

One board:
-q 2 -s 1

2nd board:
-q 5 -s 5

So this seems to be even board specific. But with this patch now
those values can be specified and tested via the cmdline.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Kevin Smith <kevin.smith@elecsyscorp.com>
Cc: Dirk Eibach <dirk.eibach@gdsys.cc>
Cc: Luka Perkov <luka.perkov@sartura.hr>
5 years agoarm: mvebu: Update CBAR with SOC regs base
Kevin Smith [Mon, 18 May 2015 16:09:44 +0000 (16:09 +0000)]
arm: mvebu: Update CBAR with SOC regs base

SMP-enabled Linux kernels read the CBAR register in CP15 to find
the address of the SCU registers.  After remapping internal
registers, also update the CBAR so the kernel can find them.

Signed-off-by: Kevin Smith <kevin.smith@elecsyscorp.com>
Acked-by: Stefan Roese <sr@denx.de>
5 years agoarm: mvebu: Disable L2 cache before enabling d-cache
Stefan Roese [Mon, 18 May 2015 16:09:43 +0000 (16:09 +0000)]
arm: mvebu: Disable L2 cache before enabling d-cache

L2 cache may still be enabled by the BootROM. We need to first disable
it before enabling d-cache support.

Signed-off-by: Stefan Roese <sr@denx.de>
Tested-by: Kevin Smith <kevin.smith@elecsyscorp.com>
5 years agotools/kwbimage.c: Correct header size for SPI boot
Kevin Smith [Mon, 16 Mar 2015 14:58:21 +0000 (14:58 +0000)]
tools/kwbimage.c: Correct header size for SPI boot

If defined, the macro CONFIG_SYS_SPI_U_BOOT_OFFS allows a board
to specify the offset of the payload image into the kwb image
file.  This value was being used to locate the image, but was not
used in the "header size" field of the main header.  Move the
use of this macro into the function that returns the header size
so that the same value is used in all places.

Signed-off-by: Kevin Smith <kevin.smith@elecsyscorp.com>
Tested-by: Stefan Roese <sr@denx.de>
5 years agoahci: extend data io wait to 10s
Mark Langsdorf [Thu, 4 Jun 2015 23:58:46 +0000 (00:58 +0100)]
ahci: extend data io wait to 10s

The AHCI driver currently waits 5s before timing out when sending a
data command to a drive. Some drives take upwards of 8s to respond to
the initial data command while they're spinning up. Increase the
data io timeout to 10s so that those drives can be found on initial
scsi scan.

Signed-off-by: Mark Langsdorf <mark.langsdorf@gmail.com>
Signed-off-by: Andre Przywara <osp@andrep.de>
5 years agoahci: support LBA48 data reads for 2+TB drives
Mark Langsdorf [Thu, 4 Jun 2015 23:58:45 +0000 (00:58 +0100)]
ahci: support LBA48 data reads for 2+TB drives

Enable full 48-bit LBA48 data reads by passing the upper word of the
LBA block pointer in bytes 9 and 10 of the FIS.

This allows uboot to load data from any arbitrary sector on a drive
with 2 or more TB of available data connected to an AHCI controller.

Signed-off-by: Mark Langsdorf <mark.langsdorf@gmail.com>
Signed-off-by: Andre Przywara <osp@andrep.de>
[trini: Make use of CONFIG_SYS_64BIT_LBA in a few places to drop
 warnings on platforms that don't enable that feature ]
Signed-off-by: Tom Rini <trini@konsulko.com>
5 years agocmd_scsi: use lbaint_t for LBA values instead of u32
Mark Langsdorf [Thu, 4 Jun 2015 23:58:44 +0000 (00:58 +0100)]
cmd_scsi: use lbaint_t for LBA values instead of u32

Signed-off-by: Mark Langsdorf <mark.langsdorf@gmail.com>
Signed-off-by: Andre Przywara <osp@andrep.de>
5 years agoARM: highbank: add reset support for Calxeda Midway machine
Mark Langsdorf [Thu, 4 Jun 2015 23:58:43 +0000 (00:58 +0100)]
ARM: highbank: add reset support for Calxeda Midway machine

The Calxeda Midway part has A15 cores, which do not have the Highbank
A9's SCU used there for resetting the chip.
Add code to distinguish between the A9 and the A15 and invoke the
appropriate register writes to support the newer part.

Andre: rework detection of Highbank vs. Midway
Rob: fix Andre's reworked detection

Signed-off-by: Mark Langsdorf <mark.langsdorf@gmail.com>
Signed-off-by: Andre Przywara <osp@andrep.de>
Signed-off-by: Rob Herring <robh@kernel.org>
5 years agoARM: highbank: add missing SCU register setup for reset
Rob Herring [Thu, 4 Jun 2015 23:58:42 +0000 (00:58 +0100)]
ARM: highbank: add missing SCU register setup for reset

Andre: assign names to the magic values

Signed-off-by: Rob Herring <robh@kernel.org>
Signed-off-by: Andre Przywara <osp@andrep.de>
5 years agoARM: BeagleBoard-x15: Add mux data
Lokesh Vutla [Thu, 4 Jun 2015 11:12:42 +0000 (16:42 +0530)]
ARM: BeagleBoard-x15: Add mux data

Adding the mux data, manual and virtual mode
settings for BeagleBoard-X15.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Roger Quadros <rogerq@ti.com>
5 years agoARM: BeagleBoard-x15: Enable IO delay recalibration sequence
Lokesh Vutla [Thu, 4 Jun 2015 11:12:41 +0000 (16:42 +0530)]
ARM: BeagleBoard-x15: Enable IO delay recalibration sequence

Enable IO delay recalibration sequence.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
5 years agoARM: DRA7: CPSW: Remove IO delay hack
Lokesh Vutla [Thu, 4 Jun 2015 11:12:40 +0000 (16:42 +0530)]
ARM: DRA7: CPSW: Remove IO delay hack

Now all manual mode configurations are done as part of
IO delay recalibration sequence, remove the hack done for
CPSW.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
5 years agoARM: DRA7-evm: Add mux data
Nishanth Menon [Thu, 4 Jun 2015 11:12:39 +0000 (16:42 +0530)]
ARM: DRA7-evm: Add mux data

Adding the mux data, manual and virtual mode
settings for DRA7-evm.

Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Signed-off-by: Vishal Mahaveer <vishalm@ti.com>
5 years agoARM: DRA7-evm: Enable IO delay recalibration sequence
Lokesh Vutla [Thu, 4 Jun 2015 11:12:38 +0000 (16:42 +0530)]
ARM: DRA7-evm: Enable IO delay recalibration sequence

Enabling IO delay recalibration sequence for DRA7 EVM.
UART and I2C are configured before IO delay recalibration sequence
as these are used earlier and safe to use.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
5 years agoARM: DRA7: Add support for manual mode configuration
Lokesh Vutla [Thu, 4 Jun 2015 11:12:37 +0000 (16:42 +0530)]
ARM: DRA7: Add support for manual mode configuration

In addition to the regular mux configuration, certain pins of DRA7
require to have "manual mode" also programmed, when predefined
delay characteristics cannot be used for the interface.

struct iodelay_cfg_entry is introduced for populating
manual mode IO timings.
For configuring manual mode, along with the normal pad
configuration do the following steps:
- Select MODESELECT field of each assocaited PAD.
  CTRL_CORE_PAD_XXX[8]:MODESELECT = 1(Enable MANUAL_MODE macro along with mux)
- Populate A_DELAY, G_DELAY values that are specified in DATA MANUAL.
  And pass the offset of the CFG_XXX register in iodelay_cfg_entry.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
5 years agoARM: DRA7: Add support for IO delay configuration
Lokesh Vutla [Thu, 4 Jun 2015 11:12:36 +0000 (16:42 +0530)]
ARM: DRA7: Add support for IO delay configuration

On DRA7, in addition to the regular muxing of pins, an additional
hardware module called IODelay which is also expected to be
configured. This "IODelay" module has it's own register space that is
independent of the control module.

It is advocated strongly in TI's official documentation considering
the existing design of the DRA7 family of processors during mux or
IODelay recalibration, there is a potential for a significant glitch
which may cause functional impairment to certain hardware. It is
hence recommended to do muxing as part of IOdelay recalibration.

IODELAY recalibration sequence:
- Complete AVS voltage change on VDD_CORE_L
- Unlock IODLAY config registers.
- Perform IO delay calibration with predefined values.
- Isolate all the IOs
- Update the delay mechanism for each IO with new calibrated values.
- Configure PAD configuration registers
- De-isolate all the IOs.
- Relock IODELAY config registers.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
5 years agoARM: DRA7: Add support for virtual mode configuration
Lokesh Vutla [Thu, 4 Jun 2015 11:12:35 +0000 (16:42 +0530)]
ARM: DRA7: Add support for virtual mode configuration

In addition to the regular mux configuration, certain pins of DRA7
require to have "virtual mode" also programmed.
This allows for predefined delay characteristics to be used by the SoC
to meet timing characterstics needed for the interface.

Provide easy to use macro to do the same.

For configuring virtual mode, along with normal pad configuration add
the following two steps:
- Select MODESELECT field of each assocaited PAD.
  CTRL_CORE_PAD_XXX[8]:MODESELECT = 1
- DELAYMODE filed should be configured with value given in DATA Manual.
  CTRL_CORE_PAD_XXX[7:4]:DELAYMODE =[0-15] (as given in DATA manual).

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
5 years agoARM: DRA7: Add pinctrl register definitions
Lokesh Vutla [Thu, 4 Jun 2015 11:12:34 +0000 (16:42 +0530)]
ARM: DRA7: Add pinctrl register definitions

Adopting the pinctrl register definitions from Linux kernel
to be consistent.
Old definitions will be removed once all the pinctrl data
is adapted to new definitions.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
5 years agoARM: DRA7: Make do_set_mux32() generic
Lokesh Vutla [Thu, 4 Jun 2015 11:12:33 +0000 (16:42 +0530)]
ARM: DRA7: Make do_set_mux32() generic

do_set_mux32() is redefined in dra7xx and beagle_x15 boards.
IO delay recalibration sequence also needs this.
Making it generic to avoid duplication.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
5 years agoARM: DRA7xx: EMIF: Fix DLL_CALIB_CTRL register
Lokesh Vutla [Wed, 3 Jun 2015 11:27:47 +0000 (16:57 +0530)]
ARM: DRA7xx: EMIF: Fix DLL_CALIB_CTRL register

When DLL_CALIB_INTERVAL is set, an extra delay is added
which is not required and it consumes EMIF bandwidth.
So making the DLL_CALIB_CTRL[8:0]DLL_CALIB_INTERVAL bits to 0.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
5 years agoARM: DRA7: Update DDR IO registers
Lokesh Vutla [Wed, 3 Jun 2015 09:13:27 +0000 (14:43 +0530)]
ARM: DRA7: Update DDR IO registers

Update DDR IO register values.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
5 years agoARM: DRA7: Update DDR IO configuration
Lokesh Vutla [Wed, 3 Jun 2015 09:13:26 +0000 (14:43 +0530)]
ARM: DRA7: Update DDR IO configuration

DDRIO_2 and LPDDR2CH1_1 registers are not present
for DRA7. So not configuring these registers for DRA7xx

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
5 years agoARM: DRA7: Add is_dra72x cpu check definition
Lokesh Vutla [Wed, 3 Jun 2015 09:13:25 +0000 (14:43 +0530)]
ARM: DRA7: Add is_dra72x cpu check definition

A generic is_dra72x cpu check is useful for grouping
all the revisions under that. This is used in the
subsequent patches.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
5 years agoARM: DRA72-evm: Enable HW leveling
Lokesh Vutla [Wed, 3 Jun 2015 09:13:24 +0000 (14:43 +0530)]
ARM: DRA72-evm: Enable HW leveling

Updating EMIF registers to enable HW leveling
on DRA72-evm.
Also updating the timing registers.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
5 years agoARM: DRA7-evm: Enable HW leveling
Lokesh Vutla [Wed, 3 Jun 2015 09:13:23 +0000 (14:43 +0530)]
ARM: DRA7-evm: Enable HW leveling

Updating EMIF registers to enable HW leveling
on DRA7-evm.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
5 years agoARM: BeagleBoard-X15: Enable HW leveling
Lokesh Vutla [Wed, 3 Jun 2015 09:13:22 +0000 (14:43 +0530)]
ARM: BeagleBoard-X15: Enable HW leveling

Updating EMIF registers to enable HW leveling
on BeagleBoard-X15.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
5 years agoARM: DRA7: DDR3: Add support for HW leveling
Lokesh Vutla [Wed, 3 Jun 2015 09:13:21 +0000 (14:43 +0530)]
ARM: DRA7: DDR3: Add support for HW leveling

DRA7 EMIF supports Full leveling for DDR3.
Adding support for the Full leveling sequence.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
5 years agokconfiglib: sync with the latest in Kconfiglib project
Masahiro Yamada [Wed, 27 May 2015 02:39:22 +0000 (11:39 +0900)]
kconfiglib: sync with the latest in Kconfiglib project

This commit imports some updates of kconfiglib.py from
https://github.com/ulfalizer/Kconfiglib

 - Warn about and ignore the "allnoconfig_y" Kconfig option
 - Statements in choices inherit menu/if deps
 - Add Symbol.is_allnoconfig_y()
 - Hint that modules are still supported despite warnings.
 - Add warning related to get_defconfig_filename().
 - Fix typo in docs.
 - Allow digits in $-references to symbols.

Signed-off-by: Ulf Magnusson <ulfalizer@gmail.com>
Signed-off-by: Philip Craig <philipjcraig@gmail.com>
Signed-off-by: Jakub Sitnicki <jsitnicki@gmail.com>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
5 years agoNokia RX-51: Fix calculating return address in save_boot_params
Pali Rohár [Tue, 9 Jun 2015 17:05:00 +0000 (19:05 +0200)]
Nokia RX-51: Fix calculating return address in save_boot_params

Commit e11c6c279d823dc0d2f470c5c2e3c0a9854a640f broke calculating lr register
in function save_boot_params() and caused U-Boot to crash at early boot time
on Nokia N900 board.

This patch fix calculating return address in lr register and make Nokia N900
board bootable again. Patch was tested in qemu and also on real N900 HW.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Pali Rohár <pali.rohar@gmail.com>
5 years agocommon/cmd_bdinfo: show gd->board_type
Hannes Schmelzer [Thu, 11 Jun 2015 10:27:09 +0000 (12:27 +0200)]
common/cmd_bdinfo: show gd->board_type

sometimes it is usefull to know if board-detection has
written the correct value into gd->board_type.

For this we add some output to the bdinfo command.

Signed-off-by: Hannes Schmelzer <oe5hpm@oevsv.at>
5 years agoblackfin: fix undefined reference to srand and rand
Masahiro Yamada [Thu, 11 Jun 2015 10:16:43 +0000 (19:16 +0900)]
blackfin: fix undefined reference to srand and rand

Commit 9ba9e85f3f1c (net: Fix NET_RANDOM_ETHADDR dependencies)
accidentally dropped CONFIG_LIB_RAND defines for 14 Blackfin boards.

Prior to that commit, those boards defined CONFIG_LIB_RAND, but not
CONFIG_NET_RANDOM_ETHADDR.  So, commit 9ba9e85f3f1c should not have
touched them, but in fact it ripped CONFIG_LIB_RAND off from all the
header files, which caused undefined reference to srand and rand.
CONFIG_LIB_RAND=y must be revived for such boards.

BTW, this commit indeed makes it better, but even with this fix,
three boards (bf533-stamp, bf538f-ezkit, cm-bf548) still can not
build due to region 'ram' overflowed error.  This was cause by
commit 6eed3786c68c (net: Move the CMD_NET config to defconfigs)
because CMD_NET selects NET, and NET selects REGEX.  Eventually,
some boards were newly enabled with CONFIG_REGEX, increasing the
memory footprint.  A patch is expected to fix the build error.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
5 years agoREADME.scrapyard: add entries for dead AVR32 boards
Masahiro Yamada [Thu, 11 Jun 2015 10:13:49 +0000 (19:13 +0900)]
README.scrapyard: add entries for dead AVR32 boards

Some AVR32 boards were dropped by the following commits:
 9eb45aabe078 (avr32: delete non generic board favr-32-ezkit)
 e36930764471 (avr32: delete non generic board hammerhead)
 c62d2f8fc5c6 (avr32: delete non generic board mimc200)
 e5354b8a9e2a (avr32: delete non generic board's atstk100{3, 4, 6})

Acked-by: Andreas Bießmann <andreas.devel@googlemail.com>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
5 years agodm: usb: tegra: Drop legacy USB code
Simon Glass [Wed, 25 Mar 2015 18:23:06 +0000 (12:23 -0600)]
dm: usb: tegra: Drop legacy USB code

Drop the code that doesn't use driver model for USB.

Signed-off-by: Simon Glass <sjg@chromium.org>
5 years agosandbox: Move CONFIG_SANDBOX_SERIAL to Kconfig
Simon Glass [Fri, 6 Mar 2015 20:19:03 +0000 (13:19 -0700)]
sandbox: Move CONFIG_SANDBOX_SERIAL to Kconfig

Move this over to Kconfig and tidy up.

Signed-off-by: Simon Glass <sjg@chromium.org>
5 years agoRemove SPL undefine of CONFIG_OF_CONTROL
Simon Glass [Tue, 12 May 2015 20:55:07 +0000 (14:55 -0600)]
Remove SPL undefine of CONFIG_OF_CONTROL

Allow SPL to be built with this option so that we can support device tree
control. Disable the simple bus for now in SPL. It may be needed later.

Signed-off-by: Simon Glass <sjg@chromium.org>
5 years agoAdd a simple version of memalign()
Simon Glass [Tue, 12 May 2015 20:55:06 +0000 (14:55 -0600)]
Add a simple version of memalign()

This is used when the full malloc() is not available.

Signed-off-by: Simon Glass <sjg@chromium.org>
5 years agodm: serial: Don't support CONFIG_CONS_INDEX with device tree
Simon Glass [Tue, 12 May 2015 20:55:05 +0000 (14:55 -0600)]
dm: serial: Don't support CONFIG_CONS_INDEX with device tree

This feature should be deprecated for new boards, and significantly adds
to SPL code size. Drop it. Instead, we can use stdout-path in the /chosen
node.

Signed-off-by: Simon Glass <sjg@chromium.org>
5 years agodts: Disable device tree for SPL on all boards
Simon Glass [Tue, 12 May 2015 20:55:04 +0000 (14:55 -0600)]
dts: Disable device tree for SPL on all boards

We plan to enable device tree in SPL by default. Before doing this,
explicitly disable it for all boards.

Signed-off-by: Simon Glass <sjg@chromium.org>
5 years agofdt: arm: Drop device tree padding
Simon Glass [Tue, 12 May 2015 20:55:03 +0000 (14:55 -0600)]
fdt: arm: Drop device tree padding

The 4KB padding doesn't seem necessary since we don't normally adjust the
control device tree file within U-Boot. Also drop the memory table space.

Signed-off-by: Simon Glass <sjg@chromium.org>
5 years agodm: ns16550: Support CONFIG_SYS_NS16550_MEM32 with driver model
Simon Glass [Tue, 12 May 2015 20:55:02 +0000 (14:55 -0600)]
dm: ns16550: Support CONFIG_SYS_NS16550_MEM32 with driver model

This option is used by some boards, so support it with driver model. This
is really ugly - we should rewrite this driver once all users are moved to
driver model.

Signed-off-by: Simon Glass <sjg@chromium.org>
5 years agolcd: Support colour lookup table on 16bpp display in BMP images
Simon Glass [Wed, 13 May 2015 13:02:28 +0000 (07:02 -0600)]
lcd: Support colour lookup table on 16bpp display in BMP images

For 16-bit-per-pixel displays it is useful to support 8 bit-per-pixel
images to reduce image size. Add support for this when drawing BMP images.

Signed-off-by: Simon Glass <sjg@chromium.org>
5 years agoRemove typedefs from bmp_layout.h
Simon Glass [Wed, 13 May 2015 13:02:27 +0000 (07:02 -0600)]
Remove typedefs from bmp_layout.h

We try to avoid typedefs and these ones are easy enough to remove. Before
changing this header in the next patch, remove the typedefs.

Signed-off-by: Simon Glass <sjg@chromium.org>
Suggested-by: Joe Hershberger <joe.hershberger@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
5 years agosandbox: Add an implementation for cleanup_before_linux_select()
Simon Glass [Wed, 13 May 2015 13:02:26 +0000 (07:02 -0600)]
sandbox: Add an implementation for cleanup_before_linux_select()

Support this function so we can use Chrome OS verified boot with sandbox.

Signed-off-by: Simon Glass <sjg@chromium.org>
5 years agoarm: Allow cleanup_before_linux() without disabling caches
Simon Glass [Wed, 13 May 2015 13:02:25 +0000 (07:02 -0600)]
arm: Allow cleanup_before_linux() without disabling caches

This function is used before jumping to U-Boot, but in that case we don't
always want to disable caches.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
5 years agoarm: spl: Add an API to detect when U-Boot is started from SPL
Simon Glass [Wed, 13 May 2015 13:02:24 +0000 (07:02 -0600)]
arm: spl: Add an API to detect when U-Boot is started from SPL

For secure boot systems it is common to have a read-only U-Boot which starts
the machine and jumps to a read-write U-Boot for actual booting the OS. This
allows the read-write U-Boot to be upgraded without risk of permanently
bricking the machine. In the event that the read-write U-Boot is corrupted,
the read-only U-Boot can detect this with a checksum and boot into a
recovery flow.

To support this, add a way to detect when U-Boot is run from SPL as opposed
to some other method, such as booted directly (no SPL) or started from
another source (e.g. a primary U-Boot). This works by putting a special value
in r0.

For now we rely on board-specific code to actually check the register and
set a flag. At some point this could be generalised, perhaps by using a spare
register and passing a flag to _main and/or board_init_f().

This commit does not implement any feature, but merely provides the API for
boards to implement.

Signed-off-by: Simon Glass <sjg@chromium.org>
5 years agodm: usb: Implement usb_detect_change() for driver model
Simon Glass [Wed, 13 May 2015 13:02:23 +0000 (07:02 -0600)]
dm: usb: Implement usb_detect_change() for driver model

Support this function with driver model also (CONFIG_DM_USB).

Signed-off-by: Simon Glass <sjg@chromium.org>
5 years agodm: tegra: usb: Move USB to driver model
Simon Glass [Wed, 6 May 2015 20:00:16 +0000 (14:00 -0600)]
dm: tegra: usb: Move USB to driver model

Somehow this change was dropped in the various merges. I noticed when I
came to turn off the non-driver-model support for Tegra. We need to make
this change (and deal with any problems) before going further.

Change-Id: Ib9389a0d41008014eb0df0df98c27be65bc79ce6
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Marek Vasut <marex@denx.de>
5 years agodm: i2c: Add compatibility functions for dm_i2c_reg_read/write()
Simon Glass [Sat, 16 May 2015 21:01:41 +0000 (15:01 -0600)]
dm: i2c: Add compatibility functions for dm_i2c_reg_read/write()

Add the legacy i2c_reg_read/write() functions to the compatibility layer
so that they can be used when CONFIG_DM_I2C_COMPAT is defined.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Heiko Schocher <hs@denx.de>
5 years agosunxi: Enable CONFIG_SYS_64BIT_LBA when AHCI is used
Bernhard Nortmann [Wed, 10 Jun 2015 08:51:40 +0000 (10:51 +0200)]
sunxi: Enable CONFIG_SYS_64BIT_LBA when AHCI is used

Due to absence of CONFIG_SYS_64BIT_LBA, u-boot-sunxi currently has
no support for the (GPT) partioning scheme of large disks > 2TB.
While the AHCI driver seems to handle this nicely, the problem is
that lbaint_t values get truncated to 32-bit.

This patch sets CONFIG_SYS_64BIT_LBA from sunxi_common.h for all
SoCs that support AHCI (CONFIG_SUNXI_AHCI).

Signed-off-by: Bernhard Nortmann <bernhard.nortmann@web.de>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
5 years agosunxi: Request macpwr gpio before using it
Hans de Goede [Sun, 7 Jun 2015 13:26:42 +0000 (15:26 +0200)]
sunxi: Request macpwr gpio before using it

This fixes ethernet no longer working on boards which use a gpio to enable
the phy.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
5 years agoavr32: delete ancient board.c
Andreas Bießmann [Mon, 11 May 2015 11:07:29 +0000 (13:07 +0200)]
avr32: delete ancient board.c

Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
5 years agoavr32: take maintainership for atstk1002
Andreas Bießmann [Mon, 11 May 2015 11:07:28 +0000 (13:07 +0200)]
avr32: take maintainership for atstk1002

I have this board at work, so I can trun tests on it.

Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
5 years agoavr32: delete non generic board's atstk100{3, 4, 6}
Andreas Bießmann [Mon, 11 May 2015 11:07:27 +0000 (13:07 +0200)]
avr32: delete non generic board's atstk100{3, 4, 6}

Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
5 years agoavr32: delete non generic board mimc200
Andreas Bießmann [Mon, 11 May 2015 11:07:26 +0000 (13:07 +0200)]
avr32: delete non generic board mimc200

Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
5 years agoavr32: delete non generic board hammerhead
Andreas Bießmann [Mon, 11 May 2015 11:07:25 +0000 (13:07 +0200)]
avr32: delete non generic board hammerhead

Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
5 years agoavr32: delete non generic board favr-32-ezkit
Andreas Bießmann [Mon, 11 May 2015 11:07:24 +0000 (13:07 +0200)]
avr32: delete non generic board favr-32-ezkit

Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
5 years agoatngw100: convert to generic board
Andreas Bießmann [Sat, 23 May 2015 21:09:15 +0000 (23:09 +0200)]
atngw100: convert to generic board

Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
5 years agoodroid: dts: cleanup of MAX77686 regulators
Przemyslaw Marczak [Mon, 18 May 2015 15:56:47 +0000 (17:56 +0200)]
odroid: dts: cleanup of MAX77686 regulators

This commit cleanup MAX77686 regulator node by:
- remove the sub-nodes of unconnected regulators
- remove the "regulator-compatible" properties of all regulators

This prevents printing init errors for the regulators,
with duplicated name strings.

Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
5 years agotegra: config: nyan-big: Add options required by Chrome OS boot
Simon Glass [Fri, 5 Jun 2015 20:39:46 +0000 (14:39 -0600)]
tegra: config: nyan-big: Add options required by Chrome OS boot

We need to match the device tree in the FIT with the U-Boot model so we
can automatically select the right device tree. Also adjust the load address
so that the device tree is not in the way when a zImage kernel tries to
extract itself.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
5 years agotegra: Replace 'Norrin' with 'Nyan-big' and fix typo
Simon Glass [Fri, 5 Jun 2015 20:39:45 +0000 (14:39 -0600)]
tegra: Replace 'Norrin' with 'Nyan-big' and fix typo

With the rename the MAINTAINER file was not updated. Fix it and the
'Chrombook' typo in Kconfig.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
5 years agotegra: config: Allow Chrome OS environment settings to be included
Simon Glass [Fri, 5 Jun 2015 20:39:44 +0000 (14:39 -0600)]
tegra: config: Allow Chrome OS environment settings to be included

Bring these in if they are provided by the board.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
5 years agotegra: nyan-big: Add additional clock and kernel init
Simon Glass [Fri, 5 Jun 2015 20:39:43 +0000 (14:39 -0600)]
tegra: nyan-big: Add additional clock and kernel init

We need to turn on all audio-related clocks for the Chrome OS kernel to
boot. Otherwise it will hang when trying to enable audio.

Also for Linux set up graphics driver video protection.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
5 years agotegra: Allow board-specific init
Simon Glass [Fri, 5 Jun 2015 20:39:42 +0000 (14:39 -0600)]
tegra: Allow board-specific init

Add a hook to allows boards to add their own init to board_init().

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
5 years agotegra: lcd: Tidy up clock init
Simon Glass [Fri, 5 Jun 2015 20:39:41 +0000 (14:39 -0600)]
tegra: lcd: Tidy up clock init

Use the correct function for clock init.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
5 years agotegra: Increase maximum arguments to 32
Simon Glass [Fri, 5 Jun 2015 20:39:40 +0000 (14:39 -0600)]
tegra: Increase maximum arguments to 32

When setting up large environment variables we can exceed 16 arguemnts.
Increase this to avoid problems.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
5 years agotegra: Add missing tegra124 peripherals
Simon Glass [Fri, 5 Jun 2015 20:39:39 +0000 (14:39 -0600)]
tegra: Add missing tegra124 peripherals

There are some missing entries in the tables. Add them.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
5 years agotegra: Introduce SRAM repair on tegra124
Simon Glass [Fri, 5 Jun 2015 20:39:38 +0000 (14:39 -0600)]
tegra: Introduce SRAM repair on tegra124

This is required in order to avoid instability when running from caches
after the kernel starts.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
5 years agotegra: clock: Adjust PLL access to avoid a warning
Simon Glass [Fri, 5 Jun 2015 20:39:37 +0000 (14:39 -0600)]
tegra: clock: Adjust PLL access to avoid a warning

A harmless but confusing warning is displayed when looking up the
DisplayPort PLL. Correct this.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
5 years agotegra: clock: Support enabling external clocks
Simon Glass [Fri, 5 Jun 2015 20:39:36 +0000 (14:39 -0600)]
tegra: clock: Support enabling external clocks

Add a simple function to enable external clocks.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
5 years agotegra: spi: Support slow SPI rates
Simon Glass [Fri, 5 Jun 2015 20:39:35 +0000 (14:39 -0600)]
tegra: spi: Support slow SPI rates

Use the oscillator as the source clock when we cannot achieve a low-enough
speed with the peripheral clock. This happens when we request 3MHz on a SPI
clock, for example.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
5 years agodm: tegra: cros_ec: Enable Chrome OS EC on Nyan-big
Simon Glass [Fri, 5 Jun 2015 20:39:34 +0000 (14:39 -0600)]
dm: tegra: cros_ec: Enable Chrome OS EC on Nyan-big

Enable the EC and keyboard, using the SPI bus.

The EC driver requires a particular format and a deactivation delay. Also
U-Boot does not support interrupts.

For now, adjust the device tree to comply. At some point we should tidy
this up to support interrupts and make tegra and exynos use the same setup.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>