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(parent: 7185adb) | patch
MIPS: make cache operation mode configurable
authorDaniel Schwierzeck <daniel.schwierzeck@googlemail.com>
Wed, 27 Jul 2011 11:22:38 +0000 (13:22 +0200)
committerShinya Kuribayashi <skuribay@pobox.com>
Sun, 31 Jul 2011 14:26:41 +0000 (23:26 +0900)
commitab2a98b11716364bc5a8c43cdfa7fee176cda1d8
treef6d237d468eec036180a987fa99a8f58aa907e89tree | snapshot
parent7185adb48ef1e5b0f05263a7f791de340ddddeb2commit | diff
MIPS: make cache operation mode configurable

Currently the cache operation mode is hard-coded to
CONF_CM_CACHABLE_NONCOHERENT. This is not appropiate for CPUs or SOCs
which operate at a different mode.

This patch makes the cache operation mode configurable via board config.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
Acked-by: Thomas Langer <thomas.langer@lantiq.com>
Signed-off-by: Shinya Kuribayashi <skuribay@pobox.com>
arch/mips/cpu/mips32/start.S diff | blob | history
UBoot for KaRo TX COM modules