From 025eb6e0b8378f5d3232c89e7a12746ddd9002bf Mon Sep 17 00:00:00 2001 From: =?utf8?q?Lothar=20Wa=C3=9Fmann?= Date: Tue, 28 Oct 2014 11:06:42 +0100 Subject: [PATCH] karo: tx53: adjust SDRAM row address bits for 4Gib chips --- board/karo/tx53/lowlevel_init.S | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/board/karo/tx53/lowlevel_init.S b/board/karo/tx53/lowlevel_init.S index 566667cd8e..32a2ec722e 100644 --- a/board/karo/tx53/lowlevel_init.S +++ b/board/karo/tx53/lowlevel_init.S @@ -174,6 +174,10 @@ dcd_end: #if SDRAM_SIZE < 2048 /* 512/1024MiB SDRAM: NT5CB128M16FP-DII */ + +#define ROW_ADDR_BITS 14 +#define COL_ADDR_BITS 10 + /* ESDCFG0 0x0c */ NS_VAL tRFC, 160, 1, 255 /* clks - 1 (0..255) */ CK_MAX tXS, NS_TO_CK(CK_TO_NS(tRFC + 1) + 10), 5, 1, 255 /* clks - 1 (0..255) tRFC + 10 */ @@ -202,6 +206,10 @@ CK_MAX tRRD, NS_TO_CK(10), 4, 1, 7 /* clks - 1 (0..7) */ CK_MAX tXPR, NS_TO_CK(CK_TO_NS(tRFC + 1) + 10), 5, 1, 255 /* clks - 1 (0..255) max(tRFC + 10, 5CK) */ #else /* 4096MiB SDRAM: IM4G16D3EABG-125I */ + +#define ROW_ADDR_BITS 15 +#define COL_ADDR_BITS 10 + /* ESDCFG0 0x0c */ NS_VAL tRFC, 260, 1, 255 /* clks - 1 (0..255) */ CK_MAX tXS, NS_TO_CK(CK_TO_NS(tRFC + 1) + 10), 5, 1, 255 /* clks - 1 (0..255) tRFC + 10 */ @@ -269,9 +277,6 @@ CK_MAX tCKSRE, NS_TO_CK(10), 5, 0, 7 (PWDT << 8) \ ) -#define ROW_ADDR_BITS 14 -#define COL_ADDR_BITS 10 - #define Rtt_Nom 1 /* ODT: 0: off 1: RZQ/4 2: RZQ/2 3: RZQ/6 4: RZQ/12 5: RZQ/8 */ #define Rtt_WR 0 /* Dynamic ODT: 0: off 1: RZQ/4 2: RZQ/2 */ #define DLL_DISABLE 0 -- 2.39.2