From 38807829898c6c9f8f1cfab3386912cad43e9b81 Mon Sep 17 00:00:00 2001 From: =?utf8?q?Lothar=20Wa=C3=9Fmann?= Date: Mon, 27 Aug 2012 15:00:50 +0200 Subject: [PATCH 1/1] nand: am33xx_nand: Use a special scan_bbt routine to switch ECC mode scan_bbt requires the ECC mode to be set to HW 0 to detect the factory bad block markers. Everyone else requires ECC mode '2'. Thus switch ECC mode in scan_bbt only to prevent confusion in userspace (env partition requiring to be written with different ECC mode than everything else). --- drivers/mtd/nand/am33xx_nand.c | 21 ++++++++++++++++++--- 1 file changed, 18 insertions(+), 3 deletions(-) diff --git a/drivers/mtd/nand/am33xx_nand.c b/drivers/mtd/nand/am33xx_nand.c index efc420aafe..b59a98d1aa 100644 --- a/drivers/mtd/nand/am33xx_nand.c +++ b/drivers/mtd/nand/am33xx_nand.c @@ -827,14 +827,27 @@ void am33xx_nand_switch_ecc(nand_ecc_modes_t hardware, int32_t mode) nand->options &= ~NAND_OWN_BUFFERS; return; } -#endif -#ifdef CONFIG_SPL_BUILD +static int am33xx_scan_bbt(struct mtd_info *mtd) +{ + int ret; + + am33xx_nand_switch_ecc(NAND_ECC_HW, 0); + ret = nand_default_bbt(mtd); + am33xx_nand_switch_ecc(NAND_ECC_HW, 2); + return ret; +} +#else /* CONFIG_SPL_BUILD */ /* Check wait pin as dev ready indicator */ static int am33xx_spl_dev_ready(struct mtd_info *mtd) { return gpmc_cfg->status & (1 << 8); } + +static int am33xx_scan_bbt(struct mtd_info *mtd) +{ + return 0; +} #endif /* @@ -884,6 +897,8 @@ int board_nand_init(struct nand_chip *nand) nand->cmd_ctrl = am33xx_nand_hwcontrol; nand->options = NAND_NO_PADDING | NAND_CACHEPRG | NAND_NO_AUTOINCR; + nand->scan_bbt = am33xx_scan_bbt; + /* If we are 16 bit dev, our gpmc config tells us that */ if ((readl(&gpmc_cfg->cs[cs].config1) & 0x3000) == 0x1000) { nand->options |= NAND_BUSWIDTH_16; @@ -901,7 +916,7 @@ int board_nand_init(struct nand_chip *nand) /* For undocumented reasons we need to currently keep our environment * in 1-bit ECC so we configure ourself thusly. */ nand_curr_device = 0; - am33xx_nand_switch_ecc(NAND_ECC_HW, 0); + am33xx_nand_switch_ecc(NAND_ECC_HW, 2); #else /* The NAND chip present requires that we have written data in with * at least 4-bit ECC so we configure outself for that in SPL. -- 2.39.2