From 5d76e203c0ad4a926d5e7c436f3c170f4039c583 Mon Sep 17 00:00:00 2001
From: =?utf8?q?Lothar=20Wa=C3=9Fmann?= <LW@KARO-electronics.de>
Date: Thu, 8 Feb 2018 17:32:36 +0100
Subject: [PATCH] arm: mx6ull: initialize AIPS-TZ3 bus

---
 arch/arm/cpu/armv7/mx6/soc.c             | 15 ++++++++-------
 arch/arm/include/asm/arch-mx6/imx-regs.h |  7 +++++--
 2 files changed, 13 insertions(+), 9 deletions(-)

diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c
index 6f74175c57..784af734a0 100644
--- a/arch/arm/cpu/armv7/mx6/soc.c
+++ b/arch/arm/cpu/armv7/mx6/soc.c
@@ -152,7 +152,7 @@ u32 get_cpu_speed_grade_hz(void)
 	case OCOTP_CFG3_SPEED_850MHZ:
 		if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D))
 			return 852000000;
-	/* Valid for IMX6SX/IMX6SDL/IMX6DQ */
+	/* Valid for IMX6SX/IMX6SDL/IMX6DQ/IMX6ULL */
 	case OCOTP_CFG3_SPEED_800MHZ:
 		return 792000000;
 	}
@@ -214,13 +214,12 @@ u32 __weak get_board_rev(void)
 void init_aips(void)
 {
 	struct aipstz_regs *aips1, *aips2;
-#ifdef CONFIG_SOC_MX6SX
+#ifdef AIPS3_CONFIG_BASE_ADDR
 	struct aipstz_regs *aips3;
 #endif
-
 	aips1 = (struct aipstz_regs *)AIPS1_BASE_ADDR;
 	aips2 = (struct aipstz_regs *)AIPS2_BASE_ADDR;
-#ifdef CONFIG_SOC_MX6SX
+#ifdef AIPS3_CONFIG_BASE_ADDR
 	aips3 = (struct aipstz_regs *)AIPS3_CONFIG_BASE_ADDR;
 #endif
 
@@ -249,7 +248,7 @@ void init_aips(void)
 	writel(0x00000000, &aips2->opacr3);
 	writel(0x00000000, &aips2->opacr4);
 
-#ifdef CONFIG_SOC_MX6SX
+#ifdef AIPS3_CONFIG_BASE_ADDR
 	/*
 	 * Set all MPROTx to be non-bufferable, trusted for R/W,
 	 * not forced to user-mode.
@@ -404,7 +403,8 @@ static void imx_set_wdog_powerdown(bool enable)
 	struct wdog_regs *wdog2 = (struct wdog_regs *)WDOG2_BASE_ADDR;
 	struct wdog_regs *wdog3 = (struct wdog_regs *)WDOG3_BASE_ADDR;
 
-	if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL))
+	if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL) ||
+	    is_cpu_type(MXC_CPU_MX6ULL))
 		writew(enable, &wdog3->wmcr);
 
 	/* Write to the PDE (Power Down Enable) bit */
@@ -628,7 +628,8 @@ void s_init(void)
 	u32 mask528;
 	u32 reg, periph1, periph2;
 
-	if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL))
+	if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL) ||
+	    is_cpu_type(MXC_CPU_MX6ULL))
 		return;
 
 	/* Due to hardware limitation, on MX6Q we need to gate/ungate all PFDs
diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h
index 350a252f4b..1739b80d9a 100644
--- a/arch/arm/include/asm/arch-mx6/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx6/imx-regs.h
@@ -92,7 +92,7 @@
 #define AIPS1_ARB_END_ADDR		0x020FFFFF
 #define AIPS2_ARB_BASE_ADDR		0x02100000
 #define AIPS2_ARB_END_ADDR		0x021FFFFF
-/* AIPS3 only on i.MX6SX */
+/* AIPS3 only on i.MX6SX && i.MX6ULL */
 #define AIPS3_ARB_BASE_ADDR		0x02200000
 #define AIPS3_ARB_END_ADDR		0x022FFFFF
 #ifdef CONFIG_SOC_MX6SX
@@ -322,8 +322,11 @@
 #define PWM8_BASE_ADDR			(AIPS3_ARB_BASE_ADDR + 0xB0000)
 #endif
 #define MX6SX_WDOG3_BASE_ADDR		(AIPS3_ARB_BASE_ADDR + 0x88000)
+#ifdef CONFIG_SOC_MX6ULL
+#define AIPS3_CONFIG_BASE_ADDR		(AIPS3_ARB_BASE_ADDR + 0x7C000)
+#endif
 
-/* only for i.MX6SX/UL */
+/* only for i.MX6SX/UL/ULL */
 #define WDOG3_BASE_ADDR ((is_cpu_type(MXC_CPU_MX6UL) ||			\
 			  is_cpu_type(MXC_CPU_MX6ULL)) ?		\
 			 MX6UL_WDOG3_BASE_ADDR :  MX6SX_WDOG3_BASE_ADDR)
-- 
2.39.2