From 65c16a636831ce3ebfad406b205e3a5399b9c2c1 Mon Sep 17 00:00:00 2001 From: =?utf8?q?Lothar=20Wa=C3=9Fmann?= Date: Thu, 21 Nov 2013 18:26:27 +0100 Subject: [PATCH] karo: tx6u: fix definition and setup of UART1 SEL_INPUT register --- board/karo/tx6/lowlevel_init.S | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/board/karo/tx6/lowlevel_init.S b/board/karo/tx6/lowlevel_init.S index 1831b0cafc..d6dafcbc22 100644 --- a/board/karo/tx6/lowlevel_init.S +++ b/board/karo/tx6/lowlevel_init.S @@ -622,8 +622,8 @@ ivt_end: #define IOMUXC_SW_PAD_CTL_GRP_B4DS 0x020e07a0 #define IOMUXC_SW_PAD_CTL_GRP_B5DS 0x020e07a4 #define IOMUXC_SW_PAD_CTL_GRP_B6DS 0x020e07a8 -#define IOMUXC_UART1_UART_RTS_B_SELECT_INPUT 0x020e091c -#define IOMUXC_UART1_UART_RX_DATA_SELECT_INPUT 0x020e0920 +#define IOMUXC_UART1_UART_RTS_B_SELECT_INPUT 0x020e08f8 +#define IOMUXC_UART1_UART_RX_DATA_SELECT_INPUT 0x020e08fc #endif dcd_hdr: @@ -651,7 +651,11 @@ dcd_start: /* UART1 pad config */ MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7, 0x00000001) /* UART1 TXD */ MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6, 0x00000001) /* UART1 RXD */ +#ifdef CONFIG_MX6Q MXC_DCD_ITEM(IOMUXC_UART1_UART_RX_DATA_SELECT_INPUT, 0x00000003) /* UART1 RXD INPUT_SEL */ +#else + MXC_DCD_ITEM(IOMUXC_UART1_UART_RX_DATA_SELECT_INPUT, 0x00000002) /* UART1 RXD INPUT_SEL */ +#endif MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0, 0x00000001) /* UART1 CTS */ MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1, 0x00000001) /* UART1 RTS */ MXC_DCD_ITEM(IOMUXC_UART1_UART_RTS_B_SELECT_INPUT, 0x00000003) /* UART1 RTS INPUT_SEL */ -- 2.39.2