From 7e8b48898a6b2f9ccaa8163be6102da4f6c0b3c0 Mon Sep 17 00:00:00 2001 From: =?utf8?q?Lothar=20Wa=C3=9Fmann?= Date: Thu, 26 Nov 2015 15:37:48 +0100 Subject: [PATCH] karo: tx6ul: set VIDEO_PLL to 648MHz by default --- board/karo/tx6/tx6ul_ll_init.S | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/board/karo/tx6/tx6ul_ll_init.S b/board/karo/tx6/tx6ul_ll_init.S index d3a33ab178..c587d75f51 100644 --- a/board/karo/tx6/tx6ul_ll_init.S +++ b/board/karo/tx6/tx6ul_ll_init.S @@ -592,12 +592,12 @@ dcd_hdr: #else MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR6, CCGR(1)) /* default: 0x00fc3003 USDHC1 */ #endif - MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE) - - MXC_DCD_ITEM(0x020c80a0, 0x80082029) /* set video PLL to 984MHz */ - MXC_DCD_ITEM(0x020c80b0, 0x00065b9a) - MXC_DCD_ITEM(0x020c80c0, 0x000f4240) + MXC_DCD_ITEM(IOMUXC_GPR1, 0x00020000) /* default: 0x0f400005 ENET1_TX_CLK output */ + MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE) + MXC_DCD_ITEM(0x020c80b0, 0) + MXC_DCD_ITEM(0x020c80c0, 1) + MXC_DCD_ITEM(0x020c80a0, 0x0010201b) /* set video PLL to 648MHz */ /* IOMUX: */ MXC_DCD_ITEM(IOMUXC_GPR0, 0x00000000) MXC_DCD_ITEM(IOMUXC_GPR1, 0x0f460005) /* default: 0x0f400005 ENET1_TX_CLK output */ -- 2.39.2