From 862445cb66508b2574d57ba12228d59a5ff66ea1 Mon Sep 17 00:00:00 2001 From: =?utf8?q?Lothar=20Wa=C3=9Fmann?= Date: Tue, 20 Oct 2015 13:28:03 +0200 Subject: [PATCH] karo: tx6: change DGCTRL init values depending on SoC type --- board/karo/tx6/lowlevel_init.S | 22 ++++++++++++++++------ 1 file changed, 16 insertions(+), 6 deletions(-) diff --git a/board/karo/tx6/lowlevel_init.S b/board/karo/tx6/lowlevel_init.S index 39d15ef4c7..e8d44801c5 100644 --- a/board/karo/tx6/lowlevel_init.S +++ b/board/karo/tx6/lowlevel_init.S @@ -888,12 +888,22 @@ dcd_hdr: MXC_DCD_ITEM_32(MMDC1_MPWLDECTRL1, (WL_DLY_DQS3 << 16) | (WL_DLY_DQS2 << 0)) MXC_DCD_ITEM_64(MMDC2_MPWLDECTRL0, (WL_DLY_DQS5 << 16) | (WL_DLY_DQS4 << 0)) MXC_DCD_ITEM_64(MMDC2_MPWLDECTRL1, (WL_DLY_DQS7 << 16) | (WL_DLY_DQS6 << 0)) - - MXC_DCD_ITEM(MMDC1_MPDGCTRL0, 0x42300230) - MXC_DCD_ITEM(MMDC1_MPDGCTRL1, 0x02300230) - MXC_DCD_ITEM_64(MMDC2_MPDGCTRL0, 0x42300230) - MXC_DCD_ITEM_64(MMDC2_MPDGCTRL1, 0x02300230) - +#if defined(CONFIG_SOC_MX6Q) + MXC_DCD_ITEM(MMDC1_MPDGCTRL0, 0x43430349) + MXC_DCD_ITEM_32(MMDC1_MPDGCTRL1, 0x03330334) + MXC_DCD_ITEM_64(MMDC2_MPDGCTRL0, 0x434b0351) + MXC_DCD_ITEM_64(MMDC2_MPDGCTRL1, 0x033d030e) +#elif defined(CONFIG_SOC_MX6DL) + MXC_DCD_ITEM(MMDC1_MPDGCTRL0, 0x423a0236) + MXC_DCD_ITEM_32(MMDC1_MPDGCTRL1, 0x02210227) + MXC_DCD_ITEM_64(MMDC2_MPDGCTRL0, 0x42240226) + MXC_DCD_ITEM_64(MMDC2_MPDGCTRL1, 0x02120223) +#elif defined(CONFIG_SOC_MX6S) + MXC_DCD_ITEM(MMDC1_MPDGCTRL0, 0x42490244) + MXC_DCD_ITEM_32(MMDC1_MPDGCTRL1, 0x022f0238) +#else +#error No DGCTRL settings for selected SoC +#endif MXC_DCD_ITEM(MMDC1_MPRDDLCTL, 0x40404040) /* DQ RD Delay default values */ MXC_DCD_ITEM(MMDC1_MPWRDLCTL, 0x40404040) /* DQ WR Delay default values */ MXC_DCD_ITEM_64(MMDC2_MPRDDLCTL, 0x40404040) /* DQ RD Delay default values */ -- 2.39.2