From a55fbdf7cd5811df8978a626f1948427bd1cf5d9 Mon Sep 17 00:00:00 2001 From: =?utf8?q?Lothar=20Wa=C3=9Fmann?= Date: Wed, 1 Aug 2012 13:44:32 +0200 Subject: [PATCH] Add Ka-Ro TX48 support --- arch/arm/dts/am33xx.dtsi | 158 ++++++ board/karo/dts/tx48.dts | 115 +++++ board/karo/tx48/Makefile | 45 ++ board/karo/tx48/config.mk | 2 + board/karo/tx48/spl.c | 409 +++++++++++++++ board/karo/tx48/tx48.c | 982 +++++++++++++++++++++++++++++++++++++ board/karo/tx48/u-boot.lds | 96 ++++ boards.cfg | 1 + include/configs/tx48.h | 351 +++++++++++++ tools/logos/karo.bmp | Bin 0 -> 26146 bytes 10 files changed, 2159 insertions(+) create mode 100644 arch/arm/dts/am33xx.dtsi create mode 100644 board/karo/dts/tx48.dts create mode 100644 board/karo/tx48/Makefile create mode 100644 board/karo/tx48/config.mk create mode 100644 board/karo/tx48/spl.c create mode 100644 board/karo/tx48/tx48.c create mode 100644 board/karo/tx48/u-boot.lds create mode 100644 include/configs/tx48.h create mode 100644 tools/logos/karo.bmp diff --git a/arch/arm/dts/am33xx.dtsi b/arch/arm/dts/am33xx.dtsi new file mode 100644 index 0000000000..edee62f338 --- /dev/null +++ b/arch/arm/dts/am33xx.dtsi @@ -0,0 +1,158 @@ +/* + * Device Tree Source for AM33XX SoC + * + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +/include/ "skeleton.dtsi" + +/ { + compatible = "ti,am33xx"; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; + serial4 = &uart4; + serial5 = &uart5; + }; + + cpus { + cpu@0 { + compatible = "arm,cortex-a8"; + }; + }; + + /* + * The soc node represents the soc top level view. It is uses for IPs + * that are not memory mapped in the MPU view or for the MPU itself. + */ + soc { + compatible = "ti,omap-infra"; + mpu { + compatible = "ti,omap3-mpu"; + ti,hwmods = "mpu"; + }; + }; + + /* + * XXX: Use a flat representation of the AM33XX interconnect. + * The real AM33XX interconnect network is quite complex.Since + * that will not bring real advantage to represent that in DT + * for the moment, just use a fake OCP bus entry to represent + * the whole bus hierarchy. + */ + ocp { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + ti,hwmods = "l3_main"; + + intc: interrupt-controller@48200000 { + compatible = "ti,omap2-intc"; + interrupt-controller; + #interrupt-cells = <1>; + ti,intc-size = <128>; + reg = <0x48200000 0x1000>; + }; + + gpio0: gpio@44e07000 { + compatible = "ti,omap4-gpio"; + ti,hwmods = "gpio1"; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <1>; + }; + + gpio1: gpio@4804C000 { + compatible = "ti,omap4-gpio"; + ti,hwmods = "gpio2"; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <1>; + }; + + gpio2: gpio@481AC000 { + compatible = "ti,omap4-gpio"; + ti,hwmods = "gpio3"; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <1>; + }; + + gpio3: gpio@481AE000 { + compatible = "ti,omap4-gpio"; + ti,hwmods = "gpio4"; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <1>; + }; + + uart0: serial@44E09000 { + compatible = "ti,omap3-uart"; + ti,hwmods = "uart1"; + clock-frequency = <48000000>; + }; + + uart1: serial@48022000 { + compatible = "ti,omap3-uart"; + ti,hwmods = "uart2"; + clock-frequency = <48000000>; + }; + + uart2: serial@48024000 { + compatible = "ti,omap3-uart"; + ti,hwmods = "uart3"; + clock-frequency = <48000000>; + }; + + uart3: serial@481A6000 { + compatible = "ti,omap3-uart"; + ti,hwmods = "uart4"; + clock-frequency = <48000000>; + }; + + uart4: serial@481A8000 { + compatible = "ti,omap3-uart"; + ti,hwmods = "uart5"; + clock-frequency = <48000000>; + }; + + uart5: serial@481AA000 { + compatible = "ti,omap3-uart"; + ti,hwmods = "uart6"; + clock-frequency = <48000000>; + }; + + i2c0: i2c@44E0B000 { + compatible = "ti,omap4-i2c"; + #address-cells = <1>; + #size-cells = <0>; + ti,hwmods = "i2c1"; + }; + + i2c1: i2c@4802A000 { + compatible = "ti,omap4-i2c"; + #address-cells = <1>; + #size-cells = <0>; + ti,hwmods = "i2c2"; + }; + + i2c2: i2c@4819C000 { + compatible = "ti,omap4-i2c"; + #address-cells = <1>; + #size-cells = <0>; + ti,hwmods = "i2c3"; + }; + }; +}; diff --git a/board/karo/dts/tx48.dts b/board/karo/dts/tx48.dts new file mode 100644 index 0000000000..bdf6bff453 --- /dev/null +++ b/board/karo/dts/tx48.dts @@ -0,0 +1,115 @@ +/* + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +/dts-v1/; + +/include/ ARCH_CPU_DTS + +/ { + model = "Ka-Ro electronics TX48 module"; + compatible = "karo,tx48", "ti,am33xx"; + + memory { + device_type = "memory"; + reg = <0x80000000 0x10000000>; /* 256 MB */ + }; + + i2c@44E0B000 { + rtc1: ds1339@68 { + compatible = "dallas,ds1339"; + reg = <0x68>; + trickle-charge = <0xa5>; + }; + + pmic: lt3589@48 { + compatible = "lt,lt3589"; + reg = <0x48>; + }; + + codec: sgtl5000@0a { + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + VDDA-supply = <®_2p5v>; + VDDIO-supply = <®_3p3v>; + }; + + touchscreen: tsc2007@48 { + compatible = "ti,tsc2007"; + reg = <0x48>; + interrupt-parent = <&gpio3>; + interrupts = <16 0>; + pendown-gpio = <&gpio3 16 1>; + model = "2007"; + x-plate-ohms = <660>; + }; + + polytouch: edt-ft5x06@38 { + compatible = "edt,edt-ft5x06"; + reg = <0x38>; + interrupt-parent = <&gpio1>; + interrupts = <17>; + reset-switch = <&edt_ft5x06_reset>; + wake-switch = <&edt_ft5x06_wake>; + }; + }; + + gpio-switch { + compatible = "gpio-switch"; + + can_xvr_enable: can-xcvr-enable { + gpio = <&gpio0 22 1>; + label = "Flexcan Transceiver Enable"; + gpio-shared; + }; + + lcd_power: lcd-power { + compatible = "linux,gpio-switch"; + gpio = <&gpio1 22 0>; + label = "LCD Power Enable"; + }; + + lcd_reset: lcd-reset { + compatible = "linux,gpio-switch"; + gpio = <&gpio1 19 1>; + label = "LCD Reset"; + init-state = <1>; + }; + + edt_ft5x06_reset: edt-ft5x06-reset { + compatible = "linux,gpio-switch"; + gpio = <&gpio1 18 1>; + label = "EDT-FT5x06 RESET"; + }; + + edt_ft5x06_wake: edt-ft5x06-wake { + compatible = "linux,gpio-switch"; + gpio = <&gpio1 27 0>; + label = "EDT-FT5x06 WAKE"; + init-state = <1>; + }; + }; + + regulators { + compatible = "simple-bus"; + + reg_2p5v: 2p5v { + compatible = "regulator-fixed"; + regulator-name = "2P5V"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + }; + + reg_3p3v: 3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; +}; diff --git a/board/karo/tx48/Makefile b/board/karo/tx48/Makefile new file mode 100644 index 0000000000..3211545216 --- /dev/null +++ b/board/karo/tx48/Makefile @@ -0,0 +1,45 @@ +# +# Makefile +# +# Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation version 2. +# +# This program is distributed "as is" WITHOUT ANY WARRANTY of any +# kind, whether express or implied; without even the implied warranty +# of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +ifeq ($(CONFIG_SPL_BUILD),) +COBJS := tx48.o +else +COBJS := spl.o +endif +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(call cmd_link_o_target, $(OBJS) $(SOBJS)) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/karo/tx48/config.mk b/board/karo/tx48/config.mk new file mode 100644 index 0000000000..fe2cf22741 --- /dev/null +++ b/board/karo/tx48/config.mk @@ -0,0 +1,2 @@ +PLATFORM_CPPFLAGS += -Werror +LOGO_BMP = logos/karo.bmp diff --git a/board/karo/tx48/spl.c b/board/karo/tx48/spl.c new file mode 100644 index 0000000000..829aafa01d --- /dev/null +++ b/board/karo/tx48/spl.c @@ -0,0 +1,409 @@ +/* + * board/karo/tx48/spl.c + * Copyright (C) 2012 Lothar Waßmann + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define TX48_LED_GPIO AM33XX_GPIO_NR(1, 26) +#define TX48_ETH_PHY_RST_GPIO AM33XX_GPIO_NR(3, 8) +#define TX48_LCD_RST_GPIO AM33XX_GPIO_NR(1, 19) +#define TX48_LCD_PWR_GPIO AM33XX_GPIO_NR(1, 22) +#define TX48_LCD_BACKLIGHT_GPIO AM33XX_GPIO_NR(3, 14) + +#define GMII_SEL (CTRL_BASE + 0x650) + +/* UART Defines */ +#define UART_SYSCFG_OFFSET 0x54 +#define UART_SYSSTS_OFFSET 0x58 + +#define UART_RESET (0x1 << 1) +#define UART_CLK_RUNNING_MASK 0x1 +#define UART_SMART_IDLE_EN (0x1 << 0x3) + +/* Timer Defines */ +#define TSICR_REG 0x54 +#define TIOCP_CFG_REG 0x10 +#define TCLR_REG 0x38 + +/* RGMII mode define */ +#define RGMII_MODE_ENABLE 0xA +#define RMII_MODE_ENABLE 0x5 +#define MII_MODE_ENABLE 0x0 + +#define NO_OF_MAC_ADDR 1 +#define ETH_ALEN 6 + +#define MUX_CFG(value, offset) { \ + __raw_writel(value, (CTRL_BASE + (offset))); \ + } + +/* PAD Control Fields */ +#define SLEWCTRL (0x1 << 6) +#define RXACTIVE (0x1 << 5) +#define PULLUP_EN (0x1 << 4) /* Pull UP Selection */ +#define PULLUDEN (0x0 << 3) /* Pull up enabled */ +#define PULLUDDIS (0x1 << 3) /* Pull up disabled */ +#define MODE(val) (val) + +/* + * PAD CONTROL OFFSETS + * Field names corresponds to the pad signal name + */ +struct pad_signals { + int gpmc_ad0; + int gpmc_ad1; + int gpmc_ad2; + int gpmc_ad3; + int gpmc_ad4; + int gpmc_ad5; + int gpmc_ad6; + int gpmc_ad7; + int gpmc_ad8; + int gpmc_ad9; + int gpmc_ad10; + int gpmc_ad11; + int gpmc_ad12; + int gpmc_ad13; + int gpmc_ad14; + int gpmc_ad15; + int gpmc_a0; + int gpmc_a1; + int gpmc_a2; + int gpmc_a3; + int gpmc_a4; + int gpmc_a5; + int gpmc_a6; + int gpmc_a7; + int gpmc_a8; + int gpmc_a9; + int gpmc_a10; + int gpmc_a11; + int gpmc_wait0; + int gpmc_wpn; + int gpmc_be1n; + int gpmc_csn0; + int gpmc_csn1; + int gpmc_csn2; + int gpmc_csn3; + int gpmc_clk; + int gpmc_advn_ale; + int gpmc_oen_ren; + int gpmc_wen; + int gpmc_be0n_cle; + int lcd_data0; + int lcd_data1; + int lcd_data2; + int lcd_data3; + int lcd_data4; + int lcd_data5; + int lcd_data6; + int lcd_data7; + int lcd_data8; + int lcd_data9; + int lcd_data10; + int lcd_data11; + int lcd_data12; + int lcd_data13; + int lcd_data14; + int lcd_data15; + int lcd_vsync; + int lcd_hsync; + int lcd_pclk; + int lcd_ac_bias_en; + int mmc0_dat3; + int mmc0_dat2; + int mmc0_dat1; + int mmc0_dat0; + int mmc0_clk; + int mmc0_cmd; + int mii1_col; + int mii1_crs; + int mii1_rxerr; + int mii1_txen; + int mii1_rxdv; + int mii1_txd3; + int mii1_txd2; + int mii1_txd1; + int mii1_txd0; + int mii1_txclk; + int mii1_rxclk; + int mii1_rxd3; + int mii1_rxd2; + int mii1_rxd1; + int mii1_rxd0; + int rmii1_refclk; + int mdio_data; + int mdio_clk; + int spi0_sclk; + int spi0_d0; + int spi0_d1; + int spi0_cs0; + int spi0_cs1; + int ecap0_in_pwm0_out; + int uart0_ctsn; + int uart0_rtsn; + int uart0_rxd; + int uart0_txd; + int uart1_ctsn; + int uart1_rtsn; + int uart1_rxd; + int uart1_txd; + int i2c0_sda; + int i2c0_scl; + int mcasp0_aclkx; + int mcasp0_fsx; + int mcasp0_axr0; + int mcasp0_ahclkr; + int mcasp0_aclkr; + int mcasp0_fsr; + int mcasp0_axr1; + int mcasp0_ahclkx; + int xdma_event_intr0; + int xdma_event_intr1; + int nresetin_out; + int porz; + int nnmi; + int osc0_in; + int osc0_out; + int rsvd1; + int tms; + int tdi; + int tdo; + int tck; + int ntrst; + int emu0; + int emu1; + int osc1_in; + int osc1_out; + int pmic_power_en; + int rtc_porz; + int rsvd2; + int ext_wakeup; + int enz_kaldo_1p8v; + int usb0_dm; + int usb0_dp; + int usb0_ce; + int usb0_id; + int usb0_vbus; + int usb0_drvvbus; + int usb1_dm; + int usb1_dp; + int usb1_ce; + int usb1_id; + int usb1_vbus; + int usb1_drvvbus; + int ddr_resetn; + int ddr_csn0; + int ddr_cke; + int ddr_ck; + int ddr_nck; + int ddr_casn; + int ddr_rasn; + int ddr_wen; + int ddr_ba0; + int ddr_ba1; + int ddr_ba2; + int ddr_a0; + int ddr_a1; + int ddr_a2; + int ddr_a3; + int ddr_a4; + int ddr_a5; + int ddr_a6; + int ddr_a7; + int ddr_a8; + int ddr_a9; + int ddr_a10; + int ddr_a11; + int ddr_a12; + int ddr_a13; + int ddr_a14; + int ddr_a15; + int ddr_odt; + int ddr_d0; + int ddr_d1; + int ddr_d2; + int ddr_d3; + int ddr_d4; + int ddr_d5; + int ddr_d6; + int ddr_d7; + int ddr_d8; + int ddr_d9; + int ddr_d10; + int ddr_d11; + int ddr_d12; + int ddr_d13; + int ddr_d14; + int ddr_d15; + int ddr_dqm0; + int ddr_dqm1; + int ddr_dqs0; + int ddr_dqsn0; + int ddr_dqs1; + int ddr_dqsn1; + int ddr_vref; + int ddr_vtp; + int ddr_strben0; + int ddr_strben1; + int ain7; + int ain6; + int ain5; + int ain4; + int ain3; + int ain2; + int ain1; + int ain0; + int vrefp; + int vrefn; +}; + +struct pin_mux { + short reg_offset; + uint8_t val; +}; + +#define PAD_CTRL_BASE 0x800 +#define OFFSET(x) (unsigned int) (&((struct pad_signals *) \ + (PAD_CTRL_BASE))->x) + +static struct pin_mux tx48_pins[] = { + /* STK5 LED */ +// { OFFSET(gpmc_a10), MODE(7), }, +#ifdef CONFIG_CMD_NAND + { OFFSET(gpmc_ad0), MODE(0) | PULLUP_EN | RXACTIVE, }, /* NAND AD0 */ + { OFFSET(gpmc_ad1), MODE(0) | PULLUP_EN | RXACTIVE, }, /* NAND AD1 */ + { OFFSET(gpmc_ad2), MODE(0) | PULLUP_EN | RXACTIVE, }, /* NAND AD2 */ + { OFFSET(gpmc_ad3), MODE(0) | PULLUP_EN | RXACTIVE, }, /* NAND AD3 */ + { OFFSET(gpmc_ad4), MODE(0) | PULLUP_EN | RXACTIVE, }, /* NAND AD4 */ + { OFFSET(gpmc_ad5), MODE(0) | PULLUP_EN | RXACTIVE, }, /* NAND AD5 */ + { OFFSET(gpmc_ad6), MODE(0) | PULLUP_EN | RXACTIVE, }, /* NAND AD6 */ + { OFFSET(gpmc_ad7), MODE(0) | PULLUP_EN | RXACTIVE, }, /* NAND AD7 */ + { OFFSET(gpmc_wait0), MODE(0) | RXACTIVE | PULLUP_EN, }, /* NAND WAIT */ + { OFFSET(gpmc_wpn), MODE(7) | PULLUP_EN | RXACTIVE, }, /* NAND_WPN */ + { OFFSET(gpmc_csn0), MODE(0) | PULLUDEN, }, /* NAND_CS0 */ + { OFFSET(gpmc_advn_ale), MODE(0) | PULLUDEN, }, /* NAND_ADV_ALE */ + { OFFSET(gpmc_oen_ren), MODE(0) | PULLUDEN, }, /* NAND_OE */ + { OFFSET(gpmc_wen), MODE(0) | PULLUDEN, }, /* NAND_WEN */ + { OFFSET(gpmc_be0n_cle), MODE(0) | PULLUDEN, }, /* NAND_BE_CLE */ +#endif + /* I2C0 */ + { OFFSET(i2c0_sda), MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL, }, /* I2C_DATA */ + { OFFSET(i2c0_scl), MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL, }, /* I2C_SCLK */ + +#ifndef CONFIG_NO_ETH + /* RMII1 */ + { OFFSET(mii1_crs), MODE(1) | RXACTIVE, }, /* RMII1_CRS */ + { OFFSET(mii1_rxerr), MODE(1) | RXACTIVE | PULLUDEN, }, /* RMII1_RXERR */ + { OFFSET(mii1_txen), MODE(1), }, /* RMII1_TXEN */ + { OFFSET(mii1_txd1), MODE(1), }, /* RMII1_TXD1 */ + { OFFSET(mii1_txd0), MODE(1), }, /* RMII1_TXD0 */ + { OFFSET(mii1_rxd1), MODE(1) | RXACTIVE | PULLUP_EN, }, /* RMII1_RXD1 */ + { OFFSET(mii1_rxd0), MODE(1) | RXACTIVE | PULLUP_EN, }, /* RMII1_RXD0 */ + { OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN, }, /* MDIO_DATA */ + { OFFSET(mdio_clk), MODE(0) | PULLUP_EN, }, /* MDIO_CLK */ + { OFFSET(rmii1_refclk), MODE(0) | RXACTIVE, }, /* RMII1_REFCLK */ + { OFFSET(emu0), MODE(7) | RXACTIVE}, /* nINT */ + { OFFSET(emu1), MODE(7), }, /* nRST */ +#endif +}; + +static struct pin_mux tx48_mmc_pins[] = { +#ifdef CONFIG_OMAP_HSMMC + /* MMC1 */ + { OFFSET(mii1_rxd2), MODE(4) | RXACTIVE | PULLUP_EN, }, /* MMC1_DAT3 */ + { OFFSET(mii1_rxd3), MODE(4) | RXACTIVE | PULLUP_EN, }, /* MMC1_DAT2 */ + { OFFSET(mii1_rxclk), MODE(4) | RXACTIVE | PULLUP_EN, }, /* MMC1_DAT1 */ + { OFFSET(mii1_txclk), MODE(4) | RXACTIVE | PULLUP_EN, }, /* MMC1_DAT0 */ + { OFFSET(gpmc_csn1), MODE(2) | RXACTIVE | PULLUP_EN, }, /* MMC1_CLK */ + { OFFSET(gpmc_csn2), MODE(2) | RXACTIVE | PULLUP_EN, }, /* MMC1_CMD */ + { OFFSET(mcasp0_fsx), MODE(4) | RXACTIVE, }, /* MMC1_CD */ +#endif +}; + +/* + * Configure the pin mux for the module + */ +static inline void tx48_set_pin_mux(const struct pin_mux *pin_mux, + int num_pins) +{ + int i; + + for (i = 0; i < num_pins; i++) + MUX_CFG(pin_mux[i].val, pin_mux[i].reg_offset); +} + +#ifdef CONFIG_SPL_BOARD_INIT +void spl_board_init(void) +{ + tx48_set_pin_mux(tx48_pins, ARRAY_SIZE(tx48_pins)); + + /* Configure LED GPIO as output */ + gpio_direction_output(TX48_LED_GPIO, 1); + + /* Configure LCD power/reset GPIOs */ + gpio_direction_output(TX48_LCD_PWR_GPIO, 0); + gpio_direction_output(TX48_LCD_RST_GPIO, 0); + gpio_direction_output(TX48_LCD_BACKLIGHT_GPIO, 0); + + gpmc_init(); +} +#endif /* CONFIG_SPL_BOARD_INIT */ + +static struct pin_mux tx48_uart0_pins[] = { + /* UART0 for early boot messages */ + { OFFSET(uart0_rxd), MODE(0) | PULLUP_EN | RXACTIVE, }, /* UART0_RXD */ + { OFFSET(uart0_txd), MODE(0) | PULLUDEN, }, /* UART0_TXD */ + + /* UART1 */ + { OFFSET(uart1_rxd), MODE(0) | PULLUP_EN | RXACTIVE, }, /* UART1_RXD */ + { OFFSET(uart1_txd), MODE(0) | PULLUDEN, }, /* UART1_TXD */ + + /* UART5 */ + { OFFSET(mii1_rxdv), MODE(3) | PULLUP_EN | RXACTIVE, }, /* UART1_RXD */ + { OFFSET(mii1_col), MODE(3) | PULLUDEN, }, /* UART1_TXD */ +}; + +/* + * early system init of muxing and clocks. + */ +void enable_uart0_pin_mux(void) +{ + tx48_set_pin_mux(tx48_uart0_pins, ARRAY_SIZE(tx48_uart0_pins)); +} + +void enable_mmc0_pin_mux(void) +{ + tx48_set_pin_mux(tx48_mmc_pins, ARRAY_SIZE(tx48_mmc_pins)); +} diff --git a/board/karo/tx48/tx48.c b/board/karo/tx48/tx48.c new file mode 100644 index 0000000000..bfede72491 --- /dev/null +++ b/board/karo/tx48/tx48.c @@ -0,0 +1,982 @@ +/* + * tx48.c + * Copyright (C) 2012 Lothar Waßmann + * + * based on evm.c + * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define TX48_LED_GPIO AM33XX_GPIO_NR(1, 26) +#define TX48_ETH_PHY_RST_GPIO AM33XX_GPIO_NR(3, 8) +#define TX48_LCD_RST_GPIO AM33XX_GPIO_NR(1, 19) +#define TX48_LCD_PWR_GPIO AM33XX_GPIO_NR(1, 22) +#define TX48_LCD_BACKLIGHT_GPIO AM33XX_GPIO_NR(3, 14) + +#define GMII_SEL (CTRL_BASE + 0x650) + +/* UART Defines */ +#define UART_SYSCFG_OFFSET 0x54 +#define UART_SYSSTS_OFFSET 0x58 + +#define UART_RESET (0x1 << 1) +#define UART_CLK_RUNNING_MASK 0x1 +#define UART_SMART_IDLE_EN (0x1 << 0x3) + +/* Timer Defines */ +#define TSICR_REG 0x54 +#define TIOCP_CFG_REG 0x10 +#define TCLR_REG 0x38 + +/* RGMII mode define */ +#define RGMII_MODE_ENABLE 0xA +#define RMII_MODE_ENABLE 0x5 +#define MII_MODE_ENABLE 0x0 + +#define NO_OF_MAC_ADDR 1 +#define ETH_ALEN 6 + +#define MUX_CFG(value, offset) { \ + __raw_writel(value, (CTRL_BASE + (offset))); \ + } + +/* PAD Control Fields */ +#define SLEWCTRL (0x1 << 6) +#define RXACTIVE (0x1 << 5) +#define PULLUP_EN (0x1 << 4) /* Pull UP Selection */ +#define PULLUDEN (0x0 << 3) /* Pull up enabled */ +#define PULLUDDIS (0x1 << 3) /* Pull up disabled */ +#define MODE(val) (val) + +/* + * PAD CONTROL OFFSETS + * Field names corresponds to the pad signal name + */ +struct pad_signals { + int gpmc_ad0; + int gpmc_ad1; + int gpmc_ad2; + int gpmc_ad3; + int gpmc_ad4; + int gpmc_ad5; + int gpmc_ad6; + int gpmc_ad7; + int gpmc_ad8; + int gpmc_ad9; + int gpmc_ad10; + int gpmc_ad11; + int gpmc_ad12; + int gpmc_ad13; + int gpmc_ad14; + int gpmc_ad15; + int gpmc_a0; + int gpmc_a1; + int gpmc_a2; + int gpmc_a3; + int gpmc_a4; + int gpmc_a5; + int gpmc_a6; + int gpmc_a7; + int gpmc_a8; + int gpmc_a9; + int gpmc_a10; + int gpmc_a11; + int gpmc_wait0; + int gpmc_wpn; + int gpmc_be1n; + int gpmc_csn0; + int gpmc_csn1; + int gpmc_csn2; + int gpmc_csn3; + int gpmc_clk; + int gpmc_advn_ale; + int gpmc_oen_ren; + int gpmc_wen; + int gpmc_be0n_cle; + int lcd_data0; + int lcd_data1; + int lcd_data2; + int lcd_data3; + int lcd_data4; + int lcd_data5; + int lcd_data6; + int lcd_data7; + int lcd_data8; + int lcd_data9; + int lcd_data10; + int lcd_data11; + int lcd_data12; + int lcd_data13; + int lcd_data14; + int lcd_data15; + int lcd_vsync; + int lcd_hsync; + int lcd_pclk; + int lcd_ac_bias_en; + int mmc0_dat3; + int mmc0_dat2; + int mmc0_dat1; + int mmc0_dat0; + int mmc0_clk; + int mmc0_cmd; + int mii1_col; + int mii1_crs; + int mii1_rxerr; + int mii1_txen; + int mii1_rxdv; + int mii1_txd3; + int mii1_txd2; + int mii1_txd1; + int mii1_txd0; + int mii1_txclk; + int mii1_rxclk; + int mii1_rxd3; + int mii1_rxd2; + int mii1_rxd1; + int mii1_rxd0; + int rmii1_refclk; + int mdio_data; + int mdio_clk; + int spi0_sclk; + int spi0_d0; + int spi0_d1; + int spi0_cs0; + int spi0_cs1; + int ecap0_in_pwm0_out; + int uart0_ctsn; + int uart0_rtsn; + int uart0_rxd; + int uart0_txd; + int uart1_ctsn; + int uart1_rtsn; + int uart1_rxd; + int uart1_txd; + int i2c0_sda; + int i2c0_scl; + int mcasp0_aclkx; + int mcasp0_fsx; + int mcasp0_axr0; + int mcasp0_ahclkr; + int mcasp0_aclkr; + int mcasp0_fsr; + int mcasp0_axr1; + int mcasp0_ahclkx; + int xdma_event_intr0; + int xdma_event_intr1; + int nresetin_out; + int porz; + int nnmi; + int osc0_in; + int osc0_out; + int rsvd1; + int tms; + int tdi; + int tdo; + int tck; + int ntrst; + int emu0; + int emu1; + int osc1_in; + int osc1_out; + int pmic_power_en; + int rtc_porz; + int rsvd2; + int ext_wakeup; + int enz_kaldo_1p8v; + int usb0_dm; + int usb0_dp; + int usb0_ce; + int usb0_id; + int usb0_vbus; + int usb0_drvvbus; + int usb1_dm; + int usb1_dp; + int usb1_ce; + int usb1_id; + int usb1_vbus; + int usb1_drvvbus; + int ddr_resetn; + int ddr_csn0; + int ddr_cke; + int ddr_ck; + int ddr_nck; + int ddr_casn; + int ddr_rasn; + int ddr_wen; + int ddr_ba0; + int ddr_ba1; + int ddr_ba2; + int ddr_a0; + int ddr_a1; + int ddr_a2; + int ddr_a3; + int ddr_a4; + int ddr_a5; + int ddr_a6; + int ddr_a7; + int ddr_a8; + int ddr_a9; + int ddr_a10; + int ddr_a11; + int ddr_a12; + int ddr_a13; + int ddr_a14; + int ddr_a15; + int ddr_odt; + int ddr_d0; + int ddr_d1; + int ddr_d2; + int ddr_d3; + int ddr_d4; + int ddr_d5; + int ddr_d6; + int ddr_d7; + int ddr_d8; + int ddr_d9; + int ddr_d10; + int ddr_d11; + int ddr_d12; + int ddr_d13; + int ddr_d14; + int ddr_d15; + int ddr_dqm0; + int ddr_dqm1; + int ddr_dqs0; + int ddr_dqsn0; + int ddr_dqs1; + int ddr_dqsn1; + int ddr_vref; + int ddr_vtp; + int ddr_strben0; + int ddr_strben1; + int ain7; + int ain6; + int ain5; + int ain4; + int ain3; + int ain2; + int ain1; + int ain0; + int vrefp; + int vrefn; +}; + +struct pin_mux { + short reg_offset; + uint8_t val; +}; + +#define PAD_CTRL_BASE 0x800 +#define OFFSET(x) (unsigned int) (&((struct pad_signals *) \ + (PAD_CTRL_BASE))->x) +/* + * Configure the pin mux for the module + */ +static void tx48_set_pin_mux(const struct pin_mux *pin_mux, + int num_pins) +{ + int i; + + for (i = 0; i < num_pins; i++) + MUX_CFG(pin_mux[i].val, pin_mux[i].reg_offset); +} + +#define PRM_RSTST_GLOBAL_COLD_RST (1 << 0) +#define PRM_RSTST_GLOBAL_WARM_SW_RST (1 << 1) +#define PRM_RSTST_WDT1_RST (1 << 4) +#define PRM_RSTST_EXTERNAL_WARM_RST (1 << 5) +#define PRM_RSTST_ICEPICK_RST (1 << 9) + +struct prm_device { + unsigned int prmrstctrl; /* offset 0x00 */ + unsigned int prmrsttime; /* offset 0x04 */ + unsigned int prmrstst; /* offset 0x08 */ + /* ... */ +}; + +/* + * Basic board specific setup + */ +static const struct pin_mux stk5_pads[] = { + /* heartbeat LED */ + { OFFSET(gpmc_a10), MODE(7) | PULLUDEN, }, + /* LCD RESET */ + { OFFSET(gpmc_a3), MODE(7) | PULLUDEN, }, + /* LCD POWER_ENABLE */ + { OFFSET(gpmc_a6), MODE(7) | PULLUDEN, }, + /* LCD Backlight (PWM) */ + { OFFSET(mcasp0_aclkx), MODE(7) | PULLUDEN, }, +}; + +static const struct pin_mux stk5_lcd_pads[] = { + /* LCD data bus */ + { OFFSET(lcd_data0), MODE(0) | PULLUDEN, }, + { OFFSET(lcd_data1), MODE(0) | PULLUDEN, }, + { OFFSET(lcd_data2), MODE(0) | PULLUDEN, }, + { OFFSET(lcd_data3), MODE(0) | PULLUDEN, }, + { OFFSET(lcd_data4), MODE(0) | PULLUDEN, }, + { OFFSET(lcd_data5), MODE(0) | PULLUDEN, }, + { OFFSET(lcd_data6), MODE(0) | PULLUDEN, }, + { OFFSET(lcd_data7), MODE(0) | PULLUDEN, }, + { OFFSET(lcd_data8), MODE(0) | PULLUDEN, }, + { OFFSET(lcd_data9), MODE(0) | PULLUDEN, }, + { OFFSET(lcd_data10), MODE(0) | PULLUDEN, }, + { OFFSET(lcd_data11), MODE(0) | PULLUDEN, }, + { OFFSET(lcd_data12), MODE(0) | PULLUDEN, }, + { OFFSET(lcd_data13), MODE(0) | PULLUDEN, }, + { OFFSET(lcd_data14), MODE(0) | PULLUDEN, }, + { OFFSET(lcd_data15), MODE(0) | PULLUDEN, }, + /* LCD control signals */ + { OFFSET(lcd_hsync), MODE(0) | PULLUDEN, }, + { OFFSET(lcd_vsync), MODE(0) | PULLUDEN, }, + { OFFSET(lcd_pclk), MODE(0) | PULLUDEN, }, + { OFFSET(lcd_ac_bias_en), MODE(0) | PULLUDEN, }, +}; + +static const struct gpio stk5_gpios[] = { + { AM33XX_GPIO_NR(1, 26), GPIOF_OUTPUT_INIT_LOW, "HEARTBEAT LED", }, +}; + +static const struct gpio stk5_lcd_gpios[] = { + { AM33XX_GPIO_NR(1, 19), GPIOF_OUTPUT_INIT_HIGH, "LCD RESET", }, + { AM33XX_GPIO_NR(1, 22), GPIOF_OUTPUT_INIT_HIGH, "LCD POWER", }, + { AM33XX_GPIO_NR(3, 14), GPIOF_OUTPUT_INIT_LOW, "LCD BACKLIGHT", }, +}; + +static const struct gpio stk5_no_lcd_gpios[] = { + { AM33XX_GPIO_NR(1, 19), GPIOF_OUTPUT_INIT_LOW, "LCD RESET", }, + { AM33XX_GPIO_NR(1, 22), GPIOF_OUTPUT_INIT_LOW, "LCD POWER", }, + { AM33XX_GPIO_NR(3, 14), GPIOF_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", }, +}; + +static const struct pin_mux stk5v5_pads[] = { + /* CAN transceiver control */ + { OFFSET(gpmc_ad8), MODE(7) | PULLUDEN, }, +}; + +static const struct gpio stk5v5_gpios[] = { + { AM33XX_GPIO_NR(0, 22), GPIOF_OUTPUT_INIT_HIGH, "CAN XCVR", }, +}; + +static u32 prm_rstst __attribute__((section(".data"))); + +#ifdef CONFIG_LCD +static u16 tx48_cmap[256]; +vidinfo_t panel_info = { + /* set to max. size supported by SoC */ + .vl_col = 1366, + .vl_row = 768, + + .vl_bpix = LCD_COLOR24, /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */ + .cmap = tx48_cmap, +}; + +static struct da8xx_panel tx48_lcd_panel = { + .name = "640x480MR@60", + .width = 640, + .height = 480, + .hfp = 12, + .hbp = 144, + .hsw = 30, + .vfp = 10, + .vbp = 35, + .vsw = 3, + .pxl_clk = 25000000, + .invert_pxl_clk = 1, +}; + +void *lcd_base; /* Start of framebuffer memory */ +void *lcd_console_address; /* Start of console buffer */ + +int lcd_line_length; +int lcd_color_fg; +int lcd_color_bg; + +short console_col; +short console_row; + +void lcd_initcolregs(void) +{ +} + +void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue) +{ +} + +void lcd_enable(void) +{ + /* HACK ALERT: + * global variable from common/lcd.c + * Set to 0 here to prevent messages from going to LCD + * rather than serial console + */ + lcd_is_enabled = 0; +} + +void lcd_disable(void) +{ +} + +void lcd_panel_disable(void) +{ +} + +static int lcd_enabled = 1; + +static inline int tx48_load_splashimage(void) +{ + int ret = 0; +#if defined(CONFIG_SPLASH_SCREEN) && defined(CONFIG_LCD) + int do_nand(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]); + cmd_tbl_t *cmd = find_cmd("nand"); + char *loadaddr = getenv("splashimage"); + char *argv[] = { + "nand", + "read", + loadaddr, + "logo", + }; + const int argc = ARRAY_SIZE(argv); + unsigned long la; + + if (!loadaddr) + return 0; + + if (tstc() || (prm_rstst & PRM_RSTST_WDT1_RST)) { + return -ENODEV; + } + + if (!cmd) + return -EINVAL; + + la = simple_strtoul(loadaddr, NULL, 16); + if (la == 0) + return -EINVAL; + + /* clear BMP header in memory */ + memset((void *)la, 0, 64); + + ret = do_nand(cmd, 0, argc, argv); + if (ret) { + printf("Failed to load logo: %d\n", ret); + return ret; + } +#endif + return ret; +} + +void lcd_ctrl_init(void *lcdbase) +{ + int color_depth = 24; + char *vm; + unsigned long val; + struct da8xx_panel *p = &tx48_lcd_panel; + int refresh = 60; + + if (!lcd_enabled) { + printf("LCD disabled\n"); + return; + } + + if (tstc() || (prm_rstst & PRM_RSTST_WDT1_RST)) { + lcd_enabled = 0; + return; + } + + vm = getenv("video_mode"); + if (vm == NULL) { + lcd_enabled = 0; + return; + } + + strncpy((char *)p->name, vm, sizeof(p->name)); + + val = simple_strtoul(vm, &vm, 0); + if (val != 0) { + if (val > panel_info.vl_col) + val = panel_info.vl_col; + p->width = val; + panel_info.vl_col = val; + } + if (*vm == 'x') { + val = simple_strtoul(vm + 1, &vm, 0); + if (val > panel_info.vl_row) + val = panel_info.vl_row; + p->height = val; + panel_info.vl_row = val; + } + while (*vm != '\0') { + switch (*vm) { + case 'M': + case 'R': + vm++; + break; + + case '-': + color_depth = simple_strtoul(vm + 1, &vm, 10); + break; + + case '@': + refresh = simple_strtoul(vm + 1, &vm, 10); + break; + + default: + debug("Ignoring '%c'\n", *vm); + vm++; + } + } + switch (color_depth) { + case 8: + panel_info.vl_bpix = 3; + break; + + case 16: + panel_info.vl_bpix = 4; + break; + + case 24: + panel_info.vl_bpix = 5; + break; + + default: + printf("Invalid color_depth %u from video_mode '%s'; using default: %u\n", + color_depth, getenv("video_mode"), 24); + } + lcd_line_length = NBITS(panel_info.vl_bpix) / 8 * panel_info.vl_col; + p->pxl_clk = refresh * + (p->width + p->hfp + p->hbp + p->hsw) * + (p->height + p->vfp + p->vbp + p->vsw); + debug("Pixel clock set to %u.%03uMHz\n", + p->pxl_clk / 1000000, p->pxl_clk / 1000 % 1000); + + tx48_set_pin_mux(stk5_lcd_pads, ARRAY_SIZE(stk5_lcd_pads)); + debug("Initializing FB driver\n"); + da8xx_video_init(&tx48_lcd_panel, color_depth); + + if (tx48_load_splashimage() == 0) { + debug("Initializing LCD controller\n"); + video_hw_init(); + } else { + debug("Skipping initialization of LCD controller\n"); + } +} + +ulong calc_fbsize(void) +{ + return panel_info.vl_row * panel_info.vl_col * 2 * + NBITS(panel_info.vl_bpix) / 8; +} +#else +#define lcd_enabled 0 +#endif /* CONFIG_LCD */ + +static void stk5_board_init(void) +{ + tx48_set_pin_mux(stk5_pads, ARRAY_SIZE(stk5_pads)); + + if (lcd_enabled) { + tx48_set_pin_mux(stk5_lcd_pads, ARRAY_SIZE(stk5_lcd_pads)); + } + gpio_request_array(stk5_no_lcd_gpios, + ARRAY_SIZE(stk5_no_lcd_gpios)); +} + +static void stk5v3_board_init(void) +{ + stk5_board_init(); +} + +static void stk5v5_board_init(void) +{ + stk5_board_init(); + tx48_set_pin_mux(stk5v5_pads, ARRAY_SIZE(stk5v5_pads)); + gpio_request_array(stk5v5_gpios, ARRAY_SIZE(stk5v5_gpios)); +} + +/* called with default environment! */ +static void tx48_move_fdt(void) +{ + unsigned long fdt_addr = getenv_ulong("fdtcontroladdr", 16, 0); + void *fdt = NULL; + +#ifdef CONFIG_OF_EMBED + fdt = _binary_dt_dtb_start; +#elif defined CONFIG_OF_SEPARATE + fdt = (void *)(_end_ofs + _TEXT_BASE); +#endif + if (fdt && fdt_addr != 0) { + if (fdt_check_header(fdt) == 0) { + size_t fdt_len = fdt_totalsize(fdt); + + memmove((void *)fdt_addr, fdt, fdt_len); + } else { + printf("ERROR: No valid FDT found at %p\n", fdt); + } + } +} + +/* called with default environment! */ +int board_init(void) +{ + /* mach type passed to kernel */ + gd->bd->bi_arch_number = -1; + + /* address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; + + return 0; +} + +static void show_reset_cause(u32 prm_rstst) +{ + const char *dlm = ""; + + printf("RESET cause: "); + if (prm_rstst & PRM_RSTST_GLOBAL_COLD_RST) { + printf("%sPOR", dlm); + dlm = " | "; + } + if (prm_rstst & PRM_RSTST_GLOBAL_WARM_SW_RST) { + printf("%sSW", dlm); + dlm = " | "; + } + if (prm_rstst & PRM_RSTST_WDT1_RST) { + printf("%sWATCHDOG", dlm); + dlm = " | "; + } + if (prm_rstst & PRM_RSTST_EXTERNAL_WARM_RST) { + printf("%sWARM", dlm); + dlm = " | "; + } + if (prm_rstst & PRM_RSTST_ICEPICK_RST) { + printf("%sJTAG", dlm); + dlm = " | "; + } + if (*dlm == '\0') + printf("unknown"); + + printf(" RESET\n"); +} + +/* called with default environment! */ +int checkboard(void) +{ + struct prm_device *prmdev = (struct prm_device *)PRM_DEVICE; + + prm_rstst = readl(&prmdev->prmrstst); + show_reset_cause(prm_rstst); + + printf("Board: Ka-Ro TX48-7020\n"); + + tx48_move_fdt(); + +#ifdef TIMER_TEST + { + unsigned long start = get_timer(0); + unsigned long last = gd->tbl; + unsigned long loop = 0; + unsigned long cnt = 0; + struct gptimer *timer_base = (struct gptimer *)CONFIG_SYS_TIMERBASE; + + printf("clock tick rate: %lu.%03lukHz\n", + gd->timer_rate_hz / 1000, gd->timer_rate_hz % 1000); + printf("ticks/us=%lu\n", gd->timer_rate_hz / CONFIG_SYS_HZ / 1000); + + while (!tstc()) { + unsigned long elapsed = get_timer(start); + unsigned long diff = gd->tbl - last; + + loop++; + last = gd->tbl; + + printf("loop %4lu: t=%08lx diff=%08lx steps=%5lu elapsed time: %4lu", + loop, gd->tbl, diff, cnt, elapsed / CONFIG_SYS_HZ); + cnt = 0; + while (get_timer(elapsed + start) < CONFIG_SYS_HZ) { + cnt++; + udelay(10); + } + printf(" tcrr=%08x\n", readl(&timer_base->tcrr)); + } + } +#endif + return 0; +} + +/* called with environment from NAND or MMC */ +int board_late_init(void) +{ + const char *baseboard; + const char *arch_number = getenv("linux_id"); + + if (arch_number) + gd->bd->bi_arch_number = simple_strtoul(arch_number, NULL, 0); + + baseboard = getenv("baseboard"); + if (!baseboard) + return 0; + + if (strncmp(baseboard, "stk5", 4) == 0) { + printf("Baseboard: %s\n", baseboard); + if ((strlen(baseboard) == 4) || + strcmp(baseboard, "stk5-v3") == 0) { + stk5v3_board_init(); + } else if (strcmp(baseboard, "stk5-v5") == 0) { + stk5v5_board_init(); + } else { + printf("WARNING: Unsupported STK5 board rev.: %s\n", + baseboard + 4); + } + } else { + printf("WARNING: Unsupported baseboard: '%s'\n", + baseboard); + return -EINVAL; + } + + if (lcd_enabled) { + gpio_set_value(TX48_LCD_PWR_GPIO, 1); + gpio_set_value(TX48_LCD_RST_GPIO, 1); + udelay(200000); + gpio_set_value(TX48_LCD_BACKLIGHT_GPIO, 0); + } + return 0; +} + +#ifdef CONFIG_DRIVER_TI_CPSW +static void tx48_phy_init(char *name, int addr) +{ + debug("%s: Resetting ethernet PHY\n", __func__); + + gpio_direction_output(TX48_ETH_PHY_RST_GPIO, 0); + + udelay(25000); + + /* Release nRST */ + gpio_set_value(TX48_ETH_PHY_RST_GPIO, 1); +} + +static void cpsw_control(int enabled) +{ + /* nothing for now */ + /* TODO : VTP was here before */ +} + +static struct cpsw_slave_data cpsw_slaves[] = { + { + .slave_reg_ofs = 0x208, + .sliver_reg_ofs = 0xd80, + .phy_id = 0, + }, +}; + +static struct cpsw_platform_data cpsw_data = { + .mdio_base = CPSW_MDIO_BASE, + .cpsw_base = CPSW_BASE, + .mdio_div = 0xff, + .channels = 8, + .cpdma_reg_ofs = 0x800, + .slaves = ARRAY_SIZE(cpsw_slaves), + .slave_data = cpsw_slaves, + .ale_reg_ofs = 0xd00, + .ale_entries = 1024, + .host_port_reg_ofs = 0x108, + .hw_stats_reg_ofs = 0x900, + .mac_control = (1 << 5) /* MIIEN */, + .control = cpsw_control, + .phy_init = tx48_phy_init, + .gigabit_en = 0, + .host_port_num = 0, + .version = CPSW_CTRL_VERSION_2, +}; + +int board_eth_init(bd_t *bis) +{ + uint8_t mac_addr[ETH_ALEN]; + uint32_t mac_hi, mac_lo; + + /* try reading mac address from efuse */ + mac_lo = __raw_readl(MAC_ID0_LO); + mac_hi = __raw_readl(MAC_ID0_HI); + + mac_addr[0] = mac_hi & 0xFF; + mac_addr[1] = (mac_hi & 0xFF00) >> 8; + mac_addr[2] = (mac_hi & 0xFF0000) >> 16; + mac_addr[3] = (mac_hi & 0xFF000000) >> 24; + mac_addr[4] = mac_lo & 0xFF; + mac_addr[5] = (mac_lo & 0xFF00) >> 8; + + if (is_valid_ether_addr(mac_addr)) { + debug("MAC addr set to: %02x:%02x:%02x:%02x:%02x:%02x\n", + mac_addr[0], mac_addr[1], mac_addr[2], + mac_addr[3], mac_addr[4], mac_addr[5]); + eth_setenv_enetaddr("ethaddr", mac_addr); + } else { + printf("ERROR: Did not find a valid mac address in e-fuse\n"); + } + + __raw_writel(RMII_MODE_ENABLE, MAC_MII_SEL); + __raw_writel(0x5D, GMII_SEL); + return cpsw_register(&cpsw_data); +} +#endif /* CONFIG_DRIVER_TI_CPSW */ + +#ifndef CONFIG_SPL_BUILD +#ifdef CONFIG_NAND_AM33XX +/****************************************************************************** + * Command to switch between NAND HW and SW ecc + *****************************************************************************/ +static int do_switch_ecc(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) +{ + int type = 0; + + if (argc < 2) + goto usage; + + if (strncmp(argv[1], "hw", 2) == 0) { + if (argc == 3) + type = simple_strtoul(argv[2], NULL, 10); + am33xx_nand_switch_ecc(NAND_ECC_HW, type); + } + else if (strncmp(argv[1], "sw", 2) == 0) + am33xx_nand_switch_ecc(NAND_ECC_SOFT, 0); + else + goto usage; + + return 0; + +usage: + printf("Usage: nandecc %s\n", cmdtp->usage); + return 1; +} + +U_BOOT_CMD( + nandecc, 3, 1, do_switch_ecc, + "Switch NAND ECC calculation algorithm b/w hardware and software", + "[sw|hw ] \n" + " [sw|hw]- Switch b/w hardware(hw) & software(sw) ecc algorithm\n" + " hw_type- 0 for Hamming code\n" + " 1 for bch4\n" + " 2 for bch8\n" + " 3 for bch16\n" +); + +#endif /* CONFIG_NAND_AM33XX */ +#endif /* CONFIG_SPL_BUILD */ + +enum { + LED_STATE_INIT = -1, + LED_STATE_OFF, + LED_STATE_ON, +}; + +void show_activity(int arg) +{ + static int led_state = LED_STATE_INIT; + static ulong last; + + if (led_state == LED_STATE_INIT) { + last = get_timer(0); + gpio_set_value(TX48_LED_GPIO, 1); + led_state = LED_STATE_ON; + } else { + if (get_timer(last) > CONFIG_SYS_HZ) { + last = get_timer(0); + if (led_state == LED_STATE_ON) { + gpio_set_value(TX48_LED_GPIO, 0); + } else { + gpio_set_value(TX48_LED_GPIO, 1); + } + led_state = 1 - led_state; + } + } +} + +#ifdef CONFIG_OF_BOARD_SETUP +#ifdef CONFIG_FDT_FIXUP_PARTITIONS +#include +#include +struct node_info nodes[] = { + { "ti,omap2-nand", MTD_DEV_TYPE_NAND, }, +}; + +#else +#define fdt_fixup_mtdparts(b,n,c) do { } while (0) +#endif /* CONFIG_FDT_FIXUP_PARTITIONS */ + +static const char *tx48_touchpanels[] = { + "ti,tsc2007", + "edt,edt-ft5x06", +}; + +static void tx48_fixup_touchpanel(void *blob) +{ + int i; + const char *model = getenv("touchpanel"); + + for (i = 0; i < ARRAY_SIZE(tx48_touchpanels); i++) { + int offs; + const char *tp = tx48_touchpanels[i]; + + if (model != NULL && strcmp(model, tp) == 0) + continue; + + tp = strchr(tp, ','); + if (tp != NULL && *tp != '\0' && strcmp(model, tp + 1) == 0) + continue; + + offs = fdt_node_offset_by_compatible(blob, -1, + tx48_touchpanels[i]); + if (offs < 0) { + debug("node '%s' not found: %d\n", + tx48_touchpanels[i], offs); + continue; + } + debug("Removing node '%s' at offset %d\n", + tx48_touchpanels[i], offs); + fdt_del_node(blob, offs); + } +} + +void ft_board_setup(void *blob, bd_t *bd) +{ + fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes)); + fdt_fixup_ethernet(blob); + + tx48_fixup_touchpanel(blob); +} +#endif /* CONFIG_OF_BOARD_SETUP */ diff --git a/board/karo/tx48/u-boot.lds b/board/karo/tx48/u-boot.lds new file mode 100644 index 0000000000..27b836637c --- /dev/null +++ b/board/karo/tx48/u-boot.lds @@ -0,0 +1,96 @@ +/* + * Copyright (c) 2004-2008 Texas Instruments + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + karo_ce_magic = CONFIG_SYS_TEXT_BASE; + + . = ALIGN(4); + .text : + { + __image_copy_start = .; + CPUDIR/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } + + . = ALIGN(4); + .data : { + *(.data) + } + + . = ALIGN(4); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + + __image_copy_end = .; + + .rel.dyn : { + __rel_dyn_start = .; + *(.rel*) + __rel_dyn_end = .; + } + + .dynsym : { + __dynsym_start = .; + *(.dynsym) + } + + _end = .; + + /* + * Deprecated: this MMU section is used by pxa at present but + * should not be used by new boards/CPUs. + */ + . = ALIGN(4096); + .mmutable : { + *(.mmutable) + } + + .bss __rel_dyn_start (OVERLAY) : { + __bss_start = .; + *(.bss) + . = ALIGN(4); + __bss_end__ = .; + } + + /DISCARD/ : { *(.dynstr*) } + /DISCARD/ : { *(.dynamic*) } + /DISCARD/ : { *(.plt*) } + /DISCARD/ : { *(.interp*) } + /DISCARD/ : { *(.gnu*) } +} diff --git a/boards.cfg b/boards.cfg index f2df37135e..27e9ce3ff3 100644 --- a/boards.cfg +++ b/boards.cfg @@ -186,6 +186,7 @@ integratorap_cm946es arm arm946es integrator armltd integratorcp_cm946es arm arm946es integrator armltd - integratorcp:CM946ES ca9x4_ct_vxp arm armv7 vexpress armltd am335x_evm arm armv7 am335x ti am33xx +tx48 arm armv7 tx48 karo am33xx highbank arm armv7 highbank - highbank efikamx arm armv7 efikamx - mx5 efikamx:MACH_TYPE=MACH_TYPE_MX51_EFIKAMX,IMX_CONFIG=board/efikamx/imximage_mx.cfg efikasb arm armv7 efikamx - mx5 efikamx:MACH_TYPE=MACH_TYPE_MX51_EFIKASB,IMX_CONFIG=board/efikamx/imximage_sb.cfg diff --git a/include/configs/tx48.h b/include/configs/tx48.h new file mode 100644 index 0000000000..6f6cd87c77 --- /dev/null +++ b/include/configs/tx48.h @@ -0,0 +1,351 @@ +/* + * tx48.h + * + * Copyright (C) 2012 Lothar Waßmann + * + * based on: am335x_evm + * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __TX48_H +#define __TX48_H + +#include +#include + +/* + * Ka-Ro TX48 board - SoC configuration + */ +#define CONFIG_AM33XX +#define CONFIG_AM33XX_GPIO +#define CONFIG_SYS_HZ 1000 /* Ticks per second */ +#define CONFIG_SHOW_ACTIVITY +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO +#define CONFIG_BOARD_LATE_INIT +#define CONFIG_SPLASH_SCREEN +#define CONFIG_SPLASH_SCREEN_ALIGN +#define CONFIG_VIDEO_DA8XX +#define DAVINCI_LCD_CNTL_BASE 0x4830e000 + +/* LCD Logo and Splash screen support */ +#define CONFIG_LCD +#ifdef CONFIG_LCD +#define CONFIG_LCD_LOGO +#define LCD_BPP LCD_COLOR24 +#define CONFIG_CMD_BMP +#define CONFIG_VIDEO_BMP_RLE8 +#endif /* CONFIG_LCD */ + +/* Clock Defines */ +#define V_OSCK 24000000 /* Clock output from T2 */ +#define V_SCLK V_OSCK + +/* + * Memory configuration options + */ +#define CONFIG_SYS_SDRAM_DDR3 +#define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of SDRAM */ +#define PHYS_SDRAM_1 0x80000000 /* SDRAM Bank #1 */ +#define PHYS_SDRAM_1_SIZE SZ_256M +#define CONFIG_MAX_RAM_BANK_SIZE SZ_1G + +#define CONFIG_STACKSIZE SZ_64K +#define CONFIG_SYS_MALLOC_LEN SZ_4M + +#define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1 + (64 * 1024 * 1024)) +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \ + (8 * 1024 * 1024)) + + +/* + * U-Boot general configurations + */ +#define CONFIG_SYS_LONGHELP +#define CONFIG_SYS_PROMPT "TX48 U-Boot > " +#define CONFIG_SYS_CBSIZE 2048 /* Console I/O buffer size */ +#define CONFIG_SYS_PBSIZE \ + (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) + /* Print buffer size */ +#define CONFIG_SYS_MAXARGS 64 /* Max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + /* Boot argument buffer size */ +#define CONFIG_VERSION_VARIABLE /* U-BOOT version */ +#define CONFIG_AUTO_COMPLETE /* Command auto complete */ +#define CONFIG_CMDLINE_EDITING /* Command history etc */ + +#define CONFIG_SYS_64BIT_VSPRINTF +#define CONFIG_SYS_NO_FLASH + +/* + * Flattened Device Tree (FDT) support +*/ +#define CONFIG_OF_LIBFDT +#define CONFIG_OF_CONTROL +#define CONFIG_OF_EMBED +#define CONFIG_OF_BOARD_SETUP +#define CONFIG_DEFAULT_DEVICE_TREE tx48 +#define CONFIG_ARCH_DEVICE_TREE am33xx + +/* + * Boot Linux + */ +#define xstr(s) str(s) +#define str(s) #s + +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_BOOTDELAY 3 +#define CONFIG_ZERO_BOOTDELAY_CHECK +#define CONFIG_SYS_AUTOLOAD "no" +#define CONFIG_BOOTFILE "uImage" +#define CONFIG_BOOTARGS "console=ttymxc0,115200 ro debug panic=1" +#define CONFIG_BOOTCOMMAND "run bootcmd_nand" +#define CONFIG_LOADADDR 0x81000000 +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR +#define CONFIG_U_BOOT_IMG_SIZE SZ_1M +#define CONFIG_HW_WATCHDOG + +/* + * Extra Environments + */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "autostart=no\0" \ + "baseboard=stk5-v3\0" \ + "bootargs_mmc=run default_bootargs;set bootargs ${bootargs}" \ + " root=/dev/mmcblk0p3 rootwait\0" \ + "bootargs_nand=run default_bootargs;set bootargs ${bootargs}" \ + " root=/dev/mtdblock3 rootfstype=jffs2\0" \ + "nfsroot=/tftpboot/rootfs\0" \ + "bootargs_nfs=run default_bootargs;set bootargs ${bootargs}" \ + " root=/dev/nfs ip=dhcp nfsroot=${serverip}:${nfsroot},nolock\0"\ + "bootcmd_mmc=set autostart no;run bootargs_mmc;" \ + "mmc read ${loadaddr} " \ + xstr(CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR) \ + " 3000;run bootm_cmd\0" \ + "bootcmd_nand=set autostart no;run bootargs_nand;" \ + "nboot linux;run bootm_cmd\0" \ + "bootcmd_net=set autostart no;run bootargs_nfs;dhcp;" \ + "run bootm_cmd\0" \ + "bootm_cmd=fdt addr ${fdtcontroladdr};fdt board;" \ + "bootm ${loadaddr} - ${fdtaddr}\0" \ + "default_bootargs=set bootargs " CONFIG_BOOTARGS \ + " ${mtdparts} video=${video_mode} ${append_bootargs}\0" \ + "fdtcontroladdr=80004000\0" \ + "mtdids=" MTDIDS_DEFAULT "\0" \ + "mtdparts=" MTDPARTS_DEFAULT "\0" \ + "touchpanel=tsc2007\0" \ + "video_mode=640x480MR-24@60\0" + +#define MTD_NAME "omap2-nand.0" +#define MTDIDS_DEFAULT "nand0=" MTD_NAME +#define CONFIG_FDT_FIXUP_PARTITIONS + +/* + * U-Boot Commands + */ +#include +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_MMC +#define CONFIG_CMD_NAND +#define CONFIG_CMD_MTDPARTS +#define CONFIG_CMD_BOOTCE + +/* + * Serial Driver + */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE (-4) +#define CONFIG_SYS_NS16550_CLK 48000000 +#define CONFIG_SYS_NS16550_COM1 0x44e09000 /* UART0 */ + +/* + * Ethernet Driver + */ +#ifdef CONFIG_CMD_NET +#define CONFIG_DRIVER_TI_CPSW +#define CONFIG_MII +#define CONFIG_CMD_MII +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_PING +#define CONFIG_BOOTP_DNS +#define CONFIG_BOOTP_DNS2 +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_SUBNETMASK + +#define CONFIG_NET_RETRY_COUNT 10 +#define CONFIG_NET_MULTI +#define CONFIG_PHY_GIGE +#endif + +/* + * NAND flash driver + */ +#ifdef CONFIG_CMD_NAND +#define CONFIG_MTD_DEVICE +#define CONFIG_ENV_IS_IN_NAND +#define CONFIG_NAND_AM33XX +#define GPMC_NAND_ECC_LP_x16_LAYOUT +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x20000 +#define CONFIG_SYS_NAND_PAGE_SIZE 2048 +#define CONFIG_SYS_NAND_OOBSIZE 64 +#define CONFIG_SYS_NAND_ECCSIZE 512 +#define CONFIG_SYS_NAND_ECCBYTES 14 +#define CONFIG_SYS_NAND_ECCSTEPS 4 + +#define CONFIG_SYS_MAX_FLASH_SECT 1024 +#define CONFIG_SYS_MAX_FLASH_BANKS 1 +#define CONFIG_SYS_NAND_MAX_CHIPS 1 +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_USE_FLASH_BBT +#ifdef CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_OVERWRITE +#define CONFIG_ENV_OFFSET (CONFIG_U_BOOT_IMG_SIZE + CONFIG_SYS_NAND_U_BOOT_OFFS) +#define CONFIG_ENV_SIZE 0x20000 /* 128 KiB */ +#if 0 +#define CONFIG_ENV_OFFSET_REDUND 0x20000 +#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE +#endif +#endif +#define CONFIG_SYS_NAND_BASE 0x08000000 /* must be defined but value is irrelevant */ +#define NAND_BASE CONFIG_SYS_NAND_BASE +#endif /* CONFIG_CMD_NAND */ + +/* + * MMC Driver + */ +#ifdef CONFIG_CMD_MMC +#ifndef CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_IS_IN_MMC +#endif +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_OMAP_HSMMC +#define CONFIG_OMAP_MMC_DEV_1 + +#define CONFIG_BOOT_PARTITION_ACCESS +#define CONFIG_DOS_PARTITION +#define CONFIG_CMD_FAT +#define CONFIG_CMD_EXT2 + +/* + * Environments on MMC + */ +#ifdef CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_ENV_OVERWRITE +/* Associated with the MMC layout defined in mmcops.c */ +#define CONFIG_ENV_OFFSET 0x400 /* 1 KB */ +#define CONFIG_ENV_SIZE (0x20000 - 0x400) /* 127 KB */ +#define CONFIG_DYNAMIC_MMC_DEVNO +#endif /* CONFIG_ENV_IS_IN_MMC */ +#endif /* CONFIG_CMD_MMC */ + +#ifdef CONFIG_ENV_OFFSET_REDUND +#define MTDPARTS_DEFAULT "mtdparts=" MTD_NAME ":" \ + "128k(u-boot-spl)," \ + "1m(u-boot)," \ + xstr(CONFIG_ENV_SIZE) \ + "(env)," \ + xstr(CONFIG_ENV_SIZE) \ + "(env2),4m(linux),16m(rootfs),-(userfs)" +#else +#define MTDPARTS_DEFAULT "mtdparts=" MTD_NAME ":" \ + "128k(u-boot-spl)," \ + "1m(u-boot)," \ + xstr(CONFIG_ENV_SIZE) \ + "(env),4m(linux),16m(rootfs),-(userfs)" +#endif + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define SRAM0_SIZE SZ_64K +#define CONFIG_SYS_INIT_SP_ADDR 0x4030B7FC +#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR + + /* Platform/Board specific defs */ +#define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */ +#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ + +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE { 110, 300, 600, 1200, 2400, \ + 4800, 9600, 14400, 19200, 28800, 38400, 56000, 57600, 115200 } + +/* + * select serial console configuration + */ +#define CONFIG_CONS_INDEX 1 +#define CONFIG_SYS_CONSOLE_INFO_QUIET + +/* Defines for SPL */ +#define CONFIG_SPL +#define CONFIG_SPL_BOARD_INIT +#define CONFIG_SPL_TEXT_BASE 0x402F0400 +#define CONFIG_SPL_MAX_SIZE (46 * 1024) +#define CONFIG_SPL_GPIO_SUPPORT +#ifdef CONFIG_NAND_AM33XX +#define CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SPL_NAND_SIMPLE +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \ + CONFIG_SYS_NAND_PAGE_SIZE) +#define CONFIG_SYS_NAND_BLOCK_SIZE SZ_128K +#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS +#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ + 10, 11, 12, 13, 14, 15, 16, 17, \ + 18, 19, 20, 21, 22, 23, 24, 25, \ + 26, 27, 28, 29, 30, 31, 32, 33, \ + 34, 35, 36, 37, 38, 39, 40, 41, \ + 42, 43, 44, 45, 46, 47, 48, 49, \ + 50, 51, 52, 53, 54, 55, 56, 57, } +#endif + +#define CONFIG_SPL_BSS_START_ADDR 0x80000000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ + +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ +#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */ +#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1 +#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot-tx48.img" +#define CONFIG_SPL_MMC_SUPPORT +#define CONFIG_SPL_FAT_SUPPORT +#define CONFIG_SPL_I2C_SUPPORT + +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBDISK_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_YMODEM_SUPPORT +#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" + +/* + * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM + * 64 bytes before this address should be set aside for u-boot.img's + * header. That is 0x800FFFC0--0x80100000 should not be used for any + * other needs. + */ +#define CONFIG_SYS_TEXT_BASE 0x80800000 +#define CONFIG_SYS_SPL_MALLOC_START 0x80208000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 + +/* Since SPL did pll and ddr initialization for us, + * we don't need to do it twice. + */ +#ifndef CONFIG_SPL_BUILD +#define CONFIG_SKIP_LOWLEVEL_INIT +#endif + +/* Unsupported features */ +#undef CONFIG_USE_IRQ + +#endif /* __TX48_H */ diff --git a/tools/logos/karo.bmp b/tools/logos/karo.bmp new file mode 100644 index 0000000000000000000000000000000000000000..45f9cd57859d424552efe4a3e0dd1e4576d8087f GIT binary patch literal 26146 zcmeI4yN)bNR)(v)tGja7CF_<|NSI>*1{O#dSP0>bJs^RE10y6%95CPw0F8r*G;e|s z0tZYU0Rc7^8l64g|F4M1h^(&e-bZ^^@1r?!&d!X>ic7{9YsDqA`geZ#gFl_w{eV>bKakF)z9|Nrcl|NMVuzx!AJKKqBi``g)X|IL5Te(NV6XMgdJ z|26y3PrsS{>%aW-?63dnz1KN(KqXfcdKYKzkSuc`WBO#``zAP zuBb>D5y|)#(d@a5(@4sxx+~y}lgw>lV!m4S$L(r+jFj8=$4zTIJkICy%}uLRWx>4P zua+zRE!ExIErd`sK%sPa2%~<+wLR|pUP`!=7W(bbBT5xWc0eVC z4E>#gJa+3LhS;rp<7V|8HX=TM>gl!h?I!bhJ~98W9N@AWcHRCM z1WeD&_plt+1FJ`A9yIZTYCoWok{#BJfTLvAU3c7fQsb@@SYu{TtarhDZy|E*R;xAH z`y*Gz3e>wJWgZzp!;X=$-*?C1Xg#+sENT+X^yhv%RLSniR(@XR*h~$nN@(RNZBxgz z6RvBlDm-6A)QMO8hlO%IK6UED^>AzCvhBcuV>j%EuIC1U(AZ!;bltEYaH0UvBeHve z6?0+SquG$ek*KGTr9gyL0u(8FM@|A7Jh0pkYnY#cITh{z-|b+nQMB9bWC&=)QIo@R zLGMpGz3Ruq9NrC6@oVHMpk~_8q@)D{qLDvqgs9fyBvRZ#fx1A;f6|m33jX+n4&nAU z2hIcZTEg{c767GosIi!%$0EG%@IV9Y>#TVzQP!Lep`}^(Qd453+?Z=K-y3E0}8=3c#QbM0Kw2OX!cAGM=_so4u?ano9^_C;6U=ZQC; zV9MO#2HDHZJw6tVW!Y>NO#!)a&)$oMi}$MAy$A7NE;dJ5RGHf0C?}<3#y#$LV8AL9 zrIj5MIY5dfj0FmLHf6Sh>lovh+_g1Xrv-(pn#I z*DOznQLzfBWYW8JCyU8? z_kD;b=3aKw-zXotr=^)@Q>~$;jfCWc9No=97Wz_7r8q-mK}#bP(n^P~Y{vH3EwK{N zmm9Vu5gYlrGNj0=O67D{31ZUN-iCSD_Sz83>^8=D${eIMV#zi|+Hg0Sn&RA+x`3Dq z>OphCxr$iKA7xkB5HXEc@i+F;25c~WEWOh12^}LCJ92t|s|8r>*NKa0Bx&{slwM?5 zq1yy#4=%S-Na@ODdMG_%?eG+RL&d3C_f7F^C zF2QVA>LMHFSLEvwU-HlAYkGpm-@haAq~|6R9WD$61uXhL2OK6Y;+-7FWeEF0f@aEP zvi9TCQD4IAe26FHsj#NbB;qVg&P>_0t1Y?a?x|g!$aCb;NU%C+%iFZ+=S?&JQ**OC z!0JroFC*&KPWGba<59 z4X44OLQc#ahzr5cT1ge5D4<;H_|MM#MFww5Y;F6SvRo6|n0f!Mc3o|=k)_)+;><{Q z(a7P9EK^l#Kb(#-+d0mKj2Yy^IW|=wNx8_AN++P06pGT4+_m2OZpL%&Mt6TD%%juY z&zXk1KKP{m7nAm1e;Qbm2$``3G-D2~iK4h8rdz5)A)+GEw>F?c?Y^6AueBQHJm*)# zTs$(6k+d-hR!U3vK(^!rmD84tCm@wzf)bpMS!}T#aGV(DCr=-D9(?Y}$E~fR4!A$GMyH zJv!Z?;E(`?xR`L_!XDdZGRfXW#gvG<%-QE2?m%ICii~cw~ zM3R&5pOYwA=J#@UD(U{=S>}|bbR_N{SiC=^u(POwiBoYJ2G5pNs%<qI5p2Bfdr)`a4`^aULUlO?9-NzuwdfPDUEAN8@O0i zx}xQR?2%s<=+;1=mX;x5HTtR9YB+mMuuLv$K4>aS18F_m1_L7zPimH274QnMVgtnK#G{w1r;3Z+prH%QGf639LUf? z{pq~X+01?_akFsEoCd+72N7VgzKlpX!NT84^6m^vjFD>(+h`OG@zG#se|tHJ>^A7*%f2)fDZa+UceS?jUyJ*8`g)zWI? zgK@9KH0xG~F!1-!P5TcO^HE%!W35&%+g0L-oq_fiS};cocr=)wwQ1{b|4~$GXTx0Q zg1hAhlu^oT&6IYc&7GL(?I)l(hcQK%YZBnwo(x@vK+M-b7fG?lYNN|ia8Ck^7dZy` zZnrrjs_{UihY4#O@aH-I1?G8z7V_2-3lb3gs$_nKq+K;Mkk7^-n*r|C5UMgzm{><) z)s?uie3Z;vj62i0hP?Frbml;g?sSluIxjXD0$a$h zA&)hOGbUcvS_T}=WngHKpynt#0Y1601&8P9w1p>MxJmVg-I{mt&V$qmDeM1^Z7U}g zE=}3XtGwmnq0p-5^A>r1rd zJHDM7^o5OdorlxV!D#>?!vFiDEW*mOfs^pt_Nhsp(#3p)QM9Sia;?ZJDG|t)oqk@( zy2CHezNxfQsL=*rU1MS>IPYGVs;dRX3+Dm}q{iTrR_*i_4~J3b;GF<{{2sG7mHL+`7tnf?oLxBMQu+60`!jLGg{82lSd0T{)Jg(_2jc_`lV_n0y9E{W(!5^8c5mGSC=h~~u((lk?_HSq)CVt%?&oc8Uei&#D z5Uu;#z0r6%1uK}gU1)QVCF)^QrgKl|c{s$N5M~vDOScGEO1U4ZHGCdY&#}1BbA5NkZ;>A5 z>fIpmk8v8q=vMcF+1;EkP}gsm5WCSae9b(18rC|4G5eEV1Z~9}Jzonp2{zYg{$7hU z&Qr7mg}CSmJc`Zwp6wo#t;~8*qP4$6+t1#b@e2y}_G?b_l*j48+*Ust!nInr3l&-k zo1~_)#O35X5s*Y}+z<8KFX$Q>wiu$TL-qT7ajD8(rgKEc3NElmjml-)F5>WJrp7&r zea?aYu4AR5$1?M{`^w|<^j*hqMwkq5W9AEU;W9I6Ut-RLOcZvPBz}{?Zw`W@?Z8qC zZq{?yZw=jqoJY_+kGWz+E-f}vG1rXVv-;N>frX!bC*k>Ay+FG3oMK#~+aamyOeS05 z0HoVuLM@~*lv#y z2|Af*uK{Bm5WD14KyAz9fUPw|%qk_rRptgMg&y6e(8VBR>wcb>SQ!YrySwK(f;tQ6 z9=84^Jr4o`7KUBlJ??Y{tdC>#O!1();?ym=R8Bjjo4A@e_0v|JxrUyr z`KejiXG@eGK(c6cNl4dS?>_6C-<(y2H%VtP&Dr5c2|EQ*Byy8HwiQ`Y?ovxnPxbM@KCm zql9uIwKWeT$jVS8;+j2bQ!>iRS0)2C4;XfavKQdIapJT}ZRaU?z|Q;f{FHh!Cqx7* zTYmQyoxsAmt>DXryyQ+0tcR!~%W}@gqU8yR&}v-1{Xd>Z%=5!3|J13_60P&z!d(5O zf2`X>l_2J0a&6bjIB4<3+C7GYU$PwHv|Y@-+z*s(rmW|4gN-ag_DpIlPnViOfPG+vudaqW!R~z9>l(x+1KtGJe8gsxt zJwU?TTXRhkjT`f3;?nbw)!w^u&Q~?!ftL_dznmm8m+DshDrPSo2KZLTBxs zfss&_bgaY*bAhZJ z888#8@mYhR=cUs>uSd*_6JN8orvjZMl)BdI7`c>OF|W5++LuMAV_0kJUO1a;_7>=8~}B@_|$bxcG~XF%7SUP%kOhQ5dY_}KY_xRcjU*9!O|@orAEBwcf}#3%QC z!tzNsJ*D9JspTUqKmY7iecOD|gr8?@5~g7{H6U-DVr-?zUl1I5>d<^q;qP3lQ`XkDV0^<~M0=*=QD z<3y99H4*w;*O!=I)B*F3kLFU>IJsut?3(haoA>Q?r|YeloxqBC%n8=>#$r#wM<&T* zH{#o;5FsJI)@k!N$1BL;=ueN5erN2QUEGZDWks6LzZ%EE#Pq$IJ64x^KIbtqS|v1p zYQlT2@}889xkrRgVZ90{1(LJ!s|L9wuiv+&LpC{6YCbl=?0ZJmO`iA=0r7jiLyb6R z^(B=)MiiTI*zhL(75CO3DRR)EbyI#a{^(NkEVmBO#mUIhqU6&p1#&an#7geX-n#Is znfMbmjhs%?r^)uc-;SkR0FM$?zIK725o9p}Njj{j5!k zd%x9NYNp=+ior;?4UO>()at*h-0FlFIl@>KlfBPH>W|L40ED=|+LzxU0eQXuL0qX~$p;;y@8 ePyFK4r6Yk$$2Tmv9N&g=?5Etvvfh-d)ctd94*XvL literal 0 HcmV?d00001 -- 2.39.2