From ae0d60ba0b7b6ff5401b076839db500066efc95e Mon Sep 17 00:00:00 2001 From: =?utf8?q?Lothar=20Wa=C3=9Fmann?= Date: Mon, 22 Jul 2013 12:31:31 +0200 Subject: [PATCH] imx: mx6: unify source code for TX6Q and TX6DL --- arch/arm/cpu/armv7/mx5/Makefile | 4 +- arch/arm/cpu/armv7/mx6/asm-offsets.c | 63 ++ arch/arm/include/asm/arch-mx6/mx6dl_pins.h | 149 --- board/karo/{tx6dl => tx6}/Makefile | 2 +- board/karo/{tx6q => tx6}/config.mk | 6 +- board/karo/{tx6dl => tx6}/flash.c | 0 board/karo/{tx6dl => tx6}/lowlevel_init.S | 38 +- board/karo/{tx6dl/tx6dl.c => tx6/tx6qdl.c} | 326 ++++-- board/karo/{tx6q => tx6}/u-boot.lds | 2 +- board/karo/tx6dl/config.mk | 32 - board/karo/tx6dl/u-boot.lds | 85 -- board/karo/tx6q/Makefile | 47 - board/karo/tx6q/flash.c | 662 ------------ board/karo/tx6q/lowlevel_init.S | 609 ----------- board/karo/tx6q/tx6q.c | 1059 -------------------- boards.cfg | 12 +- include/configs/{tx6dl.h => tx6.h} | 62 +- include/configs/tx6q.h | 339 ------- 18 files changed, 353 insertions(+), 3144 deletions(-) create mode 100644 arch/arm/cpu/armv7/mx6/asm-offsets.c delete mode 100644 arch/arm/include/asm/arch-mx6/mx6dl_pins.h rename board/karo/{tx6dl => tx6}/Makefile (98%) rename board/karo/{tx6q => tx6}/config.mk (67%) rename board/karo/{tx6dl => tx6}/flash.c (100%) rename board/karo/{tx6dl => tx6}/lowlevel_init.S (97%) rename board/karo/{tx6dl/tx6dl.c => tx6/tx6qdl.c} (77%) rename board/karo/{tx6q => tx6}/u-boot.lds (97%) delete mode 100644 board/karo/tx6dl/config.mk delete mode 100644 board/karo/tx6dl/u-boot.lds delete mode 100644 board/karo/tx6q/Makefile delete mode 100644 board/karo/tx6q/flash.c delete mode 100644 board/karo/tx6q/lowlevel_init.S delete mode 100644 board/karo/tx6q/tx6q.c rename include/configs/{tx6dl.h => tx6.h} (87%) delete mode 100644 include/configs/tx6q.h diff --git a/arch/arm/cpu/armv7/mx5/Makefile b/arch/arm/cpu/armv7/mx5/Makefile index c84ea05de2..6f8404ab64 100644 --- a/arch/arm/cpu/armv7/mx5/Makefile +++ b/arch/arm/cpu/armv7/mx5/Makefile @@ -28,9 +28,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(SOC).o COBJS = soc.o clock.o -ifneq ($(CONFIG_SYS_MX5_IOMUX_V3),) - COBJS += iomux-v3.o -else +ifeq ($(CONFIG_SYS_MX5_IOMUX_V3),) COBJS += iomux.o endif SOBJS = lowlevel_init.o diff --git a/arch/arm/cpu/armv7/mx6/asm-offsets.c b/arch/arm/cpu/armv7/mx6/asm-offsets.c new file mode 100644 index 0000000000..77699c2cd0 --- /dev/null +++ b/arch/arm/cpu/armv7/mx6/asm-offsets.c @@ -0,0 +1,63 @@ +/* + * Adapted from Linux v2.6.36 kernel: arch/powerpc/kernel/asm-offsets.c + * + * This program is used to generate definitions needed by + * assembly language modules. + * + * We use the technique used in the OSF Mach kernel code: + * generate asm statements containing #defines, + * compile this file to assembler, and then extract the + * #defines from the assembly-language output. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + */ + +#include +#include +#include + +#include + +int main(void) +{ + DEFINE(CCM_CCR, offsetof(struct mxc_ccm_reg, ccr)); + DEFINE(CCM_CCDR, offsetof(struct mxc_ccm_reg, ccdr)); + DEFINE(CCM_CSR, offsetof(struct mxc_ccm_reg, csr)); + DEFINE(CCM_CCSR, offsetof(struct mxc_ccm_reg, ccsr)); + DEFINE(CCM_CACRR, offsetof(struct mxc_ccm_reg, cacrr)); + DEFINE(CCM_CBCDR, offsetof(struct mxc_ccm_reg, cbcdr)); + DEFINE(CCM_CBCMR, offsetof(struct mxc_ccm_reg, cbcmr)); + DEFINE(CCM_CSCMR1, offsetof(struct mxc_ccm_reg, cscmr1)); + DEFINE(CCM_CSCMR2, offsetof(struct mxc_ccm_reg, cscmr2)); + DEFINE(CCM_CSCDR1, offsetof(struct mxc_ccm_reg, cscdr1)); + DEFINE(CCM_CS1CDR, offsetof(struct mxc_ccm_reg, cs1cdr)); + DEFINE(CCM_CS2CDR, offsetof(struct mxc_ccm_reg, cs2cdr)); + DEFINE(CCM_CDCDR, offsetof(struct mxc_ccm_reg, cdcdr)); + DEFINE(CCM_CHSCCDR, offsetof(struct mxc_ccm_reg, chsccdr)); + DEFINE(CCM_CSCDR2, offsetof(struct mxc_ccm_reg, cscdr2)); + DEFINE(CCM_CSCDR3, offsetof(struct mxc_ccm_reg, cscdr3)); + DEFINE(CCM_CSCDR4, offsetof(struct mxc_ccm_reg, cscdr4)); + DEFINE(CCM_CDHIPR, offsetof(struct mxc_ccm_reg, cdhipr)); + DEFINE(CCM_CDCR, offsetof(struct mxc_ccm_reg, cdcr)); + DEFINE(CCM_CTOR, offsetof(struct mxc_ccm_reg, ctor)); + DEFINE(CCM_CLPCR, offsetof(struct mxc_ccm_reg, clpcr)); + DEFINE(CCM_CISR, offsetof(struct mxc_ccm_reg, cisr)); + DEFINE(CCM_CIMR, offsetof(struct mxc_ccm_reg, cimr)); + DEFINE(CCM_CCOSR, offsetof(struct mxc_ccm_reg, ccosr)); + DEFINE(CCM_CGPR, offsetof(struct mxc_ccm_reg, cgpr)); + DEFINE(CCM_CCGR0, offsetof(struct mxc_ccm_reg, CCGR0)); + DEFINE(CCM_CCGR1, offsetof(struct mxc_ccm_reg, CCGR1)); + DEFINE(CCM_CCGR2, offsetof(struct mxc_ccm_reg, CCGR2)); + DEFINE(CCM_CCGR3, offsetof(struct mxc_ccm_reg, CCGR3)); + DEFINE(CCM_CCGR4, offsetof(struct mxc_ccm_reg, CCGR4)); + DEFINE(CCM_CCGR5, offsetof(struct mxc_ccm_reg, CCGR5)); + DEFINE(CCM_CCGR6, offsetof(struct mxc_ccm_reg, CCGR6)); + DEFINE(CCM_CCGR7, offsetof(struct mxc_ccm_reg, CCGR7)); + DEFINE(CCM_CMEOR, offsetof(struct mxc_ccm_reg, cmeor)); + + DEFINE(ANATOP_PLL_ENET, offsetof(struct anatop_regs, pll_enet)); + return 0; +} diff --git a/arch/arm/include/asm/arch-mx6/mx6dl_pins.h b/arch/arm/include/asm/arch-mx6/mx6dl_pins.h deleted file mode 100644 index 79e2c4f5a4..0000000000 --- a/arch/arm/include/asm/arch-mx6/mx6dl_pins.h +++ /dev/null @@ -1,149 +0,0 @@ -/* - * Copyright (C) 2012 Freescale Semiconductor, Inc. All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - * - */ - -#ifndef __ASM_ARCH_MX6_MX6DL_PINS_H__ -#define __ASM_ARCH_MX6_MX6DL_PINS_H__ - -#include - -/* Use to set PAD control */ -#define PAD_CTL_HYS (1 << 16) -#define PAD_CTL_PUS_100K_DOWN (0 << 14) -#define PAD_CTL_PUS_47K_UP (1 << 14) -#define PAD_CTL_PUS_100K_UP (2 << 14) -#define PAD_CTL_PUS_22K_UP (3 << 14) - -#define PAD_CTL_PUE (1 << 13) -#define PAD_CTL_PKE (1 << 12) -#define PAD_CTL_ODE (1 << 11) -#define PAD_CTL_SPEED_LOW (1 << 6) -#define PAD_CTL_SPEED_MED (2 << 6) -#define PAD_CTL_SPEED_HIGH (3 << 6) -#define PAD_CTL_DSE_DISABLE (0 << 3) -#define PAD_CTL_DSE_240ohm (1 << 3) -#define PAD_CTL_DSE_120ohm (2 << 3) -#define PAD_CTL_DSE_80ohm (3 << 3) -#define PAD_CTL_DSE_60ohm (4 << 3) -#define PAD_CTL_DSE_48ohm (5 << 3) -#define PAD_CTL_DSE_40ohm (6 << 3) -#define PAD_CTL_DSE_34ohm (7 << 3) -#define PAD_CTL_SRE_FAST (1 << 0) -#define PAD_CTL_SRE_SLOW (0 << 0) - -#define IOMUX_CONFIG_SION 0x10 -#define NO_MUX_I 0 -#define NO_PAD_I 0 -enum { - MX6DL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK = IOMUX_PAD(0x03B0, 0x009C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6DL_PAD_DI0_PIN15__IPU1_DI0_PIN15 = IOMUX_PAD(0x03B4, 0x00A0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6DL_PAD_DI0_PIN2__IPU1_DI0_PIN2 = IOMUX_PAD(0x03B8, 0x00A4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6DL_PAD_DI0_PIN3__IPU1_DI0_PIN3 = IOMUX_PAD(0x03BC, 0x00A8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6DL_PAD_DI0_PIN4__GPIO_4_20 = IOMUX_PAD(0x03C0, 0x00AC, 5, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6DL_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0 = IOMUX_PAD(0x03C4, 0x00B0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6DL_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1 = IOMUX_PAD(0x03C8, 0x00B4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6DL_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10 = IOMUX_PAD(0x03CC, 0x00B8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6DL_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11 = IOMUX_PAD(0x03D0, 0x00BC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6DL_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12 = IOMUX_PAD(0x03D4, 0x00C0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6DL_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13 = IOMUX_PAD(0x03D8, 0x00C4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6DL_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14 = IOMUX_PAD(0x03DC, 0x00C8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6DL_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15 = IOMUX_PAD(0x03E0, 0x00CC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6DL_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16 = IOMUX_PAD(0x03E4, 0x00D0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6DL_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17 = IOMUX_PAD(0x03E8, 0x00D4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6DL_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18 = IOMUX_PAD(0x03EC, 0x00D8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6DL_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19 = IOMUX_PAD(0x03F0, 0x00DC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6DL_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2 = IOMUX_PAD(0x03F4, 0x00E0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6DL_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20 = IOMUX_PAD(0x03F8, 0x00E4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6DL_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21 = IOMUX_PAD(0x03FC, 0x00E8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6DL_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22 = IOMUX_PAD(0x0400, 0x00EC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6DL_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23 = IOMUX_PAD(0x0404, 0x00F0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6DL_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3 = IOMUX_PAD(0x0408, 0x00F4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6DL_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4 = IOMUX_PAD(0x040C, 0x00F8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6DL_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5 = IOMUX_PAD(0x0410, 0x00FC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6DL_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6 = IOMUX_PAD(0x0414, 0x0100, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6DL_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7 = IOMUX_PAD(0x0418, 0x0104, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6DL_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8 = IOMUX_PAD(0x041C, 0x0108, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6DL_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9 = IOMUX_PAD(0x0420, 0x010C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6DL_PAD_EIM_D16__ECSPI1_SCLK = IOMUX_PAD(0x0514, 0x0144, 1, 0x07D8, 2, 0), - MX6DL_PAD_EIM_D17__ECSPI1_MISO = IOMUX_PAD(0x0518, 0x0148, 1, 0x07DC, 2, 0), - MX6DL_PAD_EIM_D18__ECSPI1_MOSI = IOMUX_PAD(0x051C, 0x014C, 1, 0x07E0, 2, 0), - MX6DL_PAD_EIM_D19__GPIO_3_19 = IOMUX_PAD(0x0520, 0x0150, 5, 0x0000, 0, 0), - MX6DL_PAD_EIM_D21__GPIO_3_21 = IOMUX_PAD(0x0528, 0x0158, 5, 0x0000, 0, 0), - MX6DL_PAD_EIM_D21__I2C1_SCL = IOMUX_PAD(0x0528, 0x0158, 6 | IOMUX_CONFIG_SION, 0x0868, 1, 0), - MX6DL_PAD_EIM_D23__GPIO_3_23 = IOMUX_PAD(0x0530, 0x0160, 5, 0x0000, 0, 0), - MX6DL_PAD_EIM_D26__UART2_TXD = IOMUX_PAD(0x053C, 0x016C, 4, 0x0000, 0, 0), - MX6DL_PAD_EIM_D27__UART2_RXD = IOMUX_PAD(0x0540, 0x0170, 4, 0x0904, 1, 0), - MX6DL_PAD_EIM_D28__I2C1_SDA = IOMUX_PAD(0x0544, 0x0174, 1 | IOMUX_CONFIG_SION, 0x086C, 1, 0), - MX6DL_PAD_EIM_D28__GPIO_3_28 = IOMUX_PAD(0x0544, 0x0174, 5, 0x0000, 0, 0), - MX6DL_PAD_ENET_MDC__ENET_MDC = IOMUX_PAD(0x05B8, 0x01E8, 1, 0x0000, 0, 0), - MX6DL_PAD_ENET_MDIO__ENET_MDIO = IOMUX_PAD(0x05BC, 0x01EC, 1, 0x0810, 0, 0), - MX6DL_PAD_ENET_REF_CLK__ENET_TX_CLK = IOMUX_PAD(0x05C0, 0x01F0, 1, 0x0000, 0, 0), - MX6DL_PAD_ENET_RXD0__GPIO_1_27 = IOMUX_PAD(0x05C8, 0x01F8, 5, 0x0000, 0, 0), - MX6DL_PAD_GPIO_16__GPIO_7_11 = IOMUX_PAD(0x05E4, 0x0214, 5, 0x0000, 0, 0), - MX6DL_PAD_GPIO_16__I2C3_SDA = IOMUX_PAD(0x05E4, 0x0214, 6 | IOMUX_CONFIG_SION, 0x087C, 1, 0), - MX6DL_PAD_GPIO_17__GPIO_7_12 = IOMUX_PAD(0x05E8, 0x0218, 5, 0x0000, 0, 0), - MX6DL_PAD_GPIO_18__GPIO_7_13 = IOMUX_PAD(0x05EC, 0x021C, 5, 0x0000, 0, 0), - MX6DL_PAD_GPIO_19__GPIO_4_5 = IOMUX_PAD(0x05F0, 0x0220, 5, 0x0000, 0, 0), - MX6DL_PAD_GPIO_5__GPIO_1_5 = IOMUX_PAD(0x0600, 0x0230, 5, 0x0000, 0, 0), - MX6DL_PAD_GPIO_5__I2C3_SCL = IOMUX_PAD(0x0600, 0x0230, 6 | IOMUX_CONFIG_SION, 0x0878, 2, 0), - MX6DL_PAD_KEY_COL3__I2C2_SCL = IOMUX_PAD(0x0638, 0x0250, 4 | IOMUX_CONFIG_SION, 0x0870, 1, 0), - MX6DL_PAD_KEY_COL3__GPIO_4_12 = IOMUX_PAD(0x0638, 0x0250, 5, 0x0000, 0, 0), - MX6DL_PAD_KEY_ROW3__I2C2_SDA = IOMUX_PAD(0x064C, 0x0264, 4 | IOMUX_CONFIG_SION, 0x0874, 1, 0), - MX6DL_PAD_KEY_ROW3__GPIO_4_13 = IOMUX_PAD(0x064C, 0x0264, 5, 0x0000, 0, 0), - MX6DL_PAD_NANDF_D1__GPIO_2_1 = IOMUX_PAD(0x0670, 0x0288, 5, 0x0000, 0, 0), - MX6DL_PAD_NANDF_D2__GPIO_2_2 = IOMUX_PAD(0x0674, 0x028C, 5, 0x0000, 0, 0), - MX6DL_PAD_NANDF_D3__GPIO_2_3 = IOMUX_PAD(0x0678, 0x0290, 5, 0x0000, 0, 0), - MX6DL_PAD_NANDF_D4__GPIO_2_4 = IOMUX_PAD(0x067C, 0x0294, 5, 0x0000, 0, 0), - MX6DL_PAD_NANDF_D6__GPIO_2_6 = IOMUX_PAD(0x0684, 0x029C, 5, 0x0000, 0, 0), - MX6DL_PAD_RGMII_RD0__ENET_RGMII_RD0 = IOMUX_PAD(0x0694, 0x02AC, 1, 0x0818, 1, 0), - MX6DL_PAD_RGMII_RD0__GPIO_6_25 = IOMUX_PAD(0x0694, 0x02AC, 5, 0x0000, 0, 0), - MX6DL_PAD_RGMII_RD1__ENET_RGMII_RD1 = IOMUX_PAD(0x0698, 0x02B0, 1, 0x081C, 1, 0), - MX6DL_PAD_RGMII_RD1__GPIO_6_27 = IOMUX_PAD(0x0698, 0x02B0, 5, 0x0000, 0, 0), - MX6DL_PAD_RGMII_RD2__ENET_RGMII_RD2 = IOMUX_PAD(0x069C, 0x02B4, 1, 0x0820, 1, 0), - MX6DL_PAD_RGMII_RD2__GPIO_6_28 = IOMUX_PAD(0x069C, 0x02B4, 5, 0x0000, 0, 0), - MX6DL_PAD_RGMII_RD3__ENET_RGMII_RD3 = IOMUX_PAD(0x06A0, 0x02B8, 1, 0x0824, 1, 0), - MX6DL_PAD_RGMII_RD3__GPIO_6_29 = IOMUX_PAD(0x06A0, 0x02B8, 5, 0x0000, 0, 0), - MX6DL_PAD_RGMII_RX_CTL__RGMII_RX_CTL = IOMUX_PAD(0x06A4, 0x02BC, 1, 0x0828, 1, 0), - MX6DL_PAD_RGMII_RX_CTL__GPIO_6_24 = IOMUX_PAD(0x06A4, 0x02BC, 5, 0x0000, 0, 0), - MX6DL_PAD_RGMII_RXC__ENET_RGMII_RXC = IOMUX_PAD(0x06A8, 0x02C0, 1, 0x0814, 1, 0), - MX6DL_PAD_RGMII_RXC__GPIO_6_30 = IOMUX_PAD(0x06A8, 0x02C0, 5, 0x0000, 0, 0), - MX6DL_PAD_RGMII_TD0__ENET_RGMII_TD0 = IOMUX_PAD(0x06AC, 0x02C4, 1, 0x0000, 0, 0), - MX6DL_PAD_RGMII_TD1__ENET_RGMII_TD1 = IOMUX_PAD(0x06B0, 0x02C8, 1, 0x0000, 0, 0), - MX6DL_PAD_RGMII_TD2__ENET_RGMII_TD2 = IOMUX_PAD(0x06B4, 0x02CC, 1, 0x0000, 0, 0), - MX6DL_PAD_RGMII_TD3__ENET_RGMII_TD3 = IOMUX_PAD(0x06B8, 0x02D0, 1, 0x0000, 0, 0), - MX6DL_PAD_RGMII_TX_CTL__RGMII_TX_CTL = IOMUX_PAD(0x06BC, 0x02D4, 1, 0x0000, 0, 0), - MX6DL_PAD_RGMII_TXC__ENET_RGMII_TXC = IOMUX_PAD(0x06C0, 0x02D8, 1, 0x0000, 0, 0), - MX6DL_PAD_SD1_CMD__GPIO_1_18 = IOMUX_PAD(0x06C8, 0x02E0, 5, 0x0000, 0, 0), - MX6DL_PAD_SD1_DAT3__GPIO_1_21 = IOMUX_PAD(0x06D8, 0x02F0, 5, 0x0000, 0, 0), - MX6DL_PAD_SD3_CLK__USDHC3_CLK = IOMUX_PAD(0x06F4, 0x030C, 0, 0x0934, 1, 0), - MX6DL_PAD_SD3_CMD__USDHC3_CMD = IOMUX_PAD(0x06F8, 0x0310, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0), - MX6DL_PAD_SD3_DAT0__USDHC3_DAT0 = IOMUX_PAD(0x06FC, 0x0314, 0, 0x0000, 0, 0), - MX6DL_PAD_SD3_DAT1__USDHC3_DAT1 = IOMUX_PAD(0x0700, 0x0318, 0, 0x0000, 0, 0), - MX6DL_PAD_SD3_DAT2__USDHC3_DAT2 = IOMUX_PAD(0x0704, 0x031C, 0, 0x0000, 0, 0), - MX6DL_PAD_SD3_DAT3__USDHC3_DAT3 = IOMUX_PAD(0x0708, 0x0320, 0, 0x0000, 0, 0), - MX6DL_PAD_SD3_DAT5__GPIO_7_0 = IOMUX_PAD(0x0710, 0x0328, 5, 0x0000, 0, 0), - MX6DL_PAD_SD3_DAT6__UART1_RXD = IOMUX_PAD(0x0714, 0x032C, 1, 0x08FC, 2, 0), - MX6DL_PAD_SD3_DAT7__UART1_TXD = IOMUX_PAD(0x0718, 0x0330, 1, 0x0000, 0, 0), - MX6DL_PAD_SD4_CLK__USDHC4_CLK = IOMUX_PAD(0x0720, 0x0338, 0, 0x0938, 1, 0), - MX6DL_PAD_SD4_CMD__USDHC4_CMD = IOMUX_PAD(0x0724, 0x033C, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0), - MX6DL_PAD_SD4_DAT0__USDHC4_DAT0 = IOMUX_PAD(0x0728, 0x0340, 1, 0x0000, 0, 0), - MX6DL_PAD_SD4_DAT1__USDHC4_DAT1 = IOMUX_PAD(0x072C, 0x0344, 1, 0x0000, 0, 0), - MX6DL_PAD_SD4_DAT2__USDHC4_DAT2 = IOMUX_PAD(0x0730, 0x0348, 1, 0x0000, 0, 0), - MX6DL_PAD_SD4_DAT3__USDHC4_DAT3 = IOMUX_PAD(0x0734, 0x034C, 1, 0x0000, 0, 0), -}; -#endif /* __ASM_ARCH_MX6_MX6DL_PINS_H__ */ diff --git a/board/karo/tx6dl/Makefile b/board/karo/tx6/Makefile similarity index 98% rename from board/karo/tx6dl/Makefile rename to board/karo/tx6/Makefile index 550ae30a56..3167331744 100644 --- a/board/karo/tx6dl/Makefile +++ b/board/karo/tx6/Makefile @@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).o -COBJS := tx6dl.o +COBJS := tx6qdl.o SOBJS := lowlevel_init.o ifeq ($(CONFIG_CMD_ROMUPDATE),y) COBJS += flash.o diff --git a/board/karo/tx6q/config.mk b/board/karo/tx6/config.mk similarity index 67% rename from board/karo/tx6q/config.mk rename to board/karo/tx6/config.mk index a00e7e9c62..70600265de 100644 --- a/board/karo/tx6q/config.mk +++ b/board/karo/tx6/config.mk @@ -5,9 +5,5 @@ CONFIG_SYS_TEXT_BASE := 0x27800000 LOGO_BMP = logos/karo.bmp #PLATFORM_CPPFLAGS += -DDEBUG -PLATFORM_CPPFLAGS += -Wno-unused-but-set-variable - +#PLATFORM_CPPFLAGS += -Wno-unused-but-set-variable PLATFORM_CPPFLAGS += -Werror -#ifneq ($(CONFIG_SPL_BUILD),y) -# ALL-y += $(obj)u-boot.sb -#endif diff --git a/board/karo/tx6dl/flash.c b/board/karo/tx6/flash.c similarity index 100% rename from board/karo/tx6dl/flash.c rename to board/karo/tx6/flash.c diff --git a/board/karo/tx6dl/lowlevel_init.S b/board/karo/tx6/lowlevel_init.S similarity index 97% rename from board/karo/tx6dl/lowlevel_init.S rename to board/karo/tx6/lowlevel_init.S index f1fc604a6c..250bbf959a 100644 --- a/board/karo/tx6dl/lowlevel_init.S +++ b/board/karo/tx6/lowlevel_init.S @@ -1,6 +1,11 @@ #include -#include +#include #include +#include + +#ifndef CCM_CCR +#error asm-offsets not included +#endif #define DEBUG_LED_BIT 20 #define LED_GPIO_BASE GPIO2_BASE_ADDR @@ -319,16 +324,6 @@ ivt_end: #define DDR_ADDR_MASK 0 #define DDR_CTRL_MASK (DDR_MODE_MASK | DSE_MASK) -#define CCM_CCR 0x020c4000 -#define CCM_CS2CDR 0x020c402c -#define CCM_CCGR0 0x020c4068 -#define CCM_CCGR1 0x020c406c -#define CCM_CCGR2 0x020c4070 -#define CCM_CCGR3 0x020c4074 -#define CCM_CCGR4 0x020c4078 -#define CCM_CCGR5 0x020c407c -#define CCM_CCGR6 0x020c4080 -#define CCM_ANALOG_PLL_ENET 0x020c80e0 #define MMDC1_MDCTL 0x021b0000 #define MMDC1_MDPDC 0x021b0004 #define MMDC1_MDOTC 0x021b0008 @@ -552,7 +547,6 @@ ivt_end: #define IOMUXC_UART1_UART_RX_DATA_SELECT_INPUT 0x020e0920 #endif - dcd_hdr: .word CPU_2_BE_32((0xd2 << 24) | ((dcd_end - .) << 8) | DCD_VERSION) dcd_start: @@ -560,18 +554,18 @@ dcd_start: /* RESET_OUT GPIO_7_12 */ MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_GPIO17, 0x00000005) - MXC_DCD_ITEM(CCM_CS2CDR, 0x006336c1) /* CS2CDR default: 0x007236c1 */ + MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CS2CDR, 0x006336c1) /* CS2CDR default: 0x007236c1 */ - MXC_DCD_ITEM(CCM_ANALOG_PLL_ENET, 0x00002001) /* ENET PLL */ + MXC_DCD_ITEM(ANATOP_BASE_ADDR + ANATOP_PLL_ENET, 0x00002001) /* ENET PLL */ /* enable all relevant clocks... */ - MXC_DCD_ITEM(CCM_CCGR0, 0xf0c03f3f) /* default: 0xf0c03f0f APBH-DMA */ - MXC_DCD_ITEM(CCM_CCGR1, 0xf0fc0c00) /* default: 0xf0fc0000 */ - MXC_DCD_ITEM(CCM_CCGR2, 0xfc3ff0cc) /* default: 0xfc3ff00c I2C1 */ - MXC_DCD_ITEM(CCM_CCGR3, 0x3ff00000) /* default: 0x3ff00000 */ - MXC_DCD_ITEM(CCM_CCGR4, 0xff00ff00) /* default: 0x0000ff00 GPMI BCH */ - MXC_DCD_ITEM(CCM_CCGR5, 0xff033f0f) /* default: 0xf0033f0f UART1 */ - MXC_DCD_ITEM(CCM_CCGR6, 0xffff03ff) /* default: 0xffff0003 USDHC4 (for APBH-DMA!) USDHC3 (for BCH!) */ + MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR0, 0xf0c03f3f) /* default: 0xf0c03f0f APBH-DMA */ + MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR1, 0xf0fc0c00) /* default: 0xf0fc0000 */ + MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR2, 0xfc3ff0cc) /* default: 0xfc3ff00c I2C1 */ + MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR3, 0x3ff00000) /* default: 0x3ff00000 */ + MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR4, 0xff00ff00) /* default: 0x0000ff00 GPMI BCH */ + MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR5, 0xff033f0f) /* default: 0xf0033f0f UART1 */ + MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR6, 0xffff03ff) /* default: 0xffff0003 USDHC4 (for APBH-DMA!) USDHC3 (for BCH!) */ /* IOMUX: */ MXC_DCD_ITEM(IOMUXC_GPR1, 0x48640005) /* default: 0x48400005 ENET_CLK output */ @@ -726,7 +720,7 @@ ddr_calib: MXC_DCD_ITEM(MMDC1_MDOR, MDOR_VAL) MXC_DCD_ITEM(MMDC1_MDOTC, MDOTC_VAL) MXC_DCD_ITEM(MMDC1_MDPDC, MDPDC_VAL_0) - MXC_DCD_ITEM(MMDC1_MDASP, 0x00000017) /* MDASP */ + MXC_DCD_ITEM(MMDC1_MDASP, (PHYS_SDRAM_1_SIZE + SZ_256M) / SZ_32M - 1) /* MDASP */ /* CS0 MRS: */ MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(0, 0, mr0_val)) diff --git a/board/karo/tx6dl/tx6dl.c b/board/karo/tx6/tx6qdl.c similarity index 77% rename from board/karo/tx6dl/tx6dl.c rename to board/karo/tx6/tx6qdl.c index 7d6a291cf1..27c007ef17 100644 --- a/board/karo/tx6dl/tx6dl.c +++ b/board/karo/tx6/tx6qdl.c @@ -19,9 +19,7 @@ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA */ -#ifndef DEBUG #define DEBUG -#endif //#define TIMER_TEST #include @@ -47,16 +45,16 @@ #include "../common/karo.h" -#define TX6DL_FEC_RST_GPIO IMX_GPIO_NR(7, 6) -#define TX6DL_FEC_PWR_GPIO IMX_GPIO_NR(3, 20) -#define TX6DL_FEC_INT_GPIO IMX_GPIO_NR(2, 4) -#define TX6DL_LED_GPIO IMX_GPIO_NR(2, 20) +#define TX6_FEC_RST_GPIO IMX_GPIO_NR(7, 6) +#define TX6_FEC_PWR_GPIO IMX_GPIO_NR(3, 20) +#define TX6_FEC_INT_GPIO IMX_GPIO_NR(2, 4) +#define TX6_LED_GPIO IMX_GPIO_NR(2, 20) -#define TX6DL_LCD_PWR_GPIO IMX_GPIO_NR(2, 31) -#define TX6DL_LCD_RST_GPIO IMX_GPIO_NR(3, 29) -#define TX6DL_LCD_BACKLIGHT_GPIO IMX_GPIO_NR(1, 1) +#define TX6_LCD_PWR_GPIO IMX_GPIO_NR(2, 31) +#define TX6_LCD_RST_GPIO IMX_GPIO_NR(3, 29) +#define TX6_LCD_BACKLIGHT_GPIO IMX_GPIO_NR(1, 1) -#define TX6DL_RESET_OUT_GPIO IMX_GPIO_NR(7, 12) +#define TX6_RESET_OUT_GPIO IMX_GPIO_NR(7, 12) #define TEMPERATURE_MIN -40 #define TEMPERATURE_HOT 80 @@ -64,9 +62,9 @@ DECLARE_GLOBAL_DATA_PTR; -#define MUX_CFG_SION IOMUX_PAD(0, 0, IOMUX_CONFIG_SION, 0, 0, 0) +#define MUX_CFG_SION IOMUX_PAD(0, 0, MUX_CONFIG_SION, 0, 0, 0) -static const iomux_v3_cfg_t tx6dl_pads[] = { +static const iomux_v3_cfg_t tx6qdl_pads[] = { /* NAND flash pads */ MX6_PAD_NANDF_CLE__RAWNAND_CLE, MX6_PAD_NANDF_ALE__RAWNAND_ALE, @@ -116,7 +114,7 @@ static const iomux_v3_cfg_t tx6dl_pads[] = { MX6_PAD_SD3_DAT4__GPIO_7_1, /* PHY INT */ }; -static const iomux_v3_cfg_t tx6dl_fec_pads[] = { +static const iomux_v3_cfg_t tx6qdl_fec_pads[] = { /* FEC functions */ MX6_PAD_ENET_MDC__ENET_MDC, MX6_PAD_ENET_MDIO__ENET_MDIO, @@ -130,11 +128,11 @@ static const iomux_v3_cfg_t tx6dl_fec_pads[] = { MX6_PAD_ENET_TXD0__ENET_TDATA_0, }; -static const struct gpio tx6dl_gpios[] = { - { TX6DL_RESET_OUT_GPIO, GPIOF_OUTPUT_INIT_HIGH, "#RESET_OUT", }, - { TX6DL_FEC_PWR_GPIO, GPIOF_OUTPUT_INIT_HIGH, "FEC PHY PWR", }, - { TX6DL_FEC_RST_GPIO, GPIOF_OUTPUT_INIT_LOW, "FEC PHY RESET", }, - { TX6DL_FEC_INT_GPIO, GPIOF_INPUT, "FEC PHY INT", }, +static const struct gpio tx6qdl_gpios[] = { + { TX6_RESET_OUT_GPIO, GPIOF_OUTPUT_INIT_HIGH, "#RESET_OUT", }, + { TX6_FEC_PWR_GPIO, GPIOF_OUTPUT_INIT_HIGH, "FEC PHY PWR", }, + { TX6_FEC_RST_GPIO, GPIOF_OUTPUT_INIT_LOW, "FEC PHY RESET", }, + { TX6_FEC_INT_GPIO, GPIOF_INPUT, "FEC PHY INT", }, }; /* @@ -304,8 +302,8 @@ static int setup_pmic_voltages(void) int board_early_init_f(void) { - gpio_request_array(tx6dl_gpios, ARRAY_SIZE(tx6dl_gpios)); - imx_iomux_v3_setup_multiple_pads(tx6dl_pads, ARRAY_SIZE(tx6dl_pads)); + gpio_request_array(tx6qdl_gpios, ARRAY_SIZE(tx6qdl_gpios)); + imx_iomux_v3_setup_multiple_pads(tx6qdl_pads, ARRAY_SIZE(tx6qdl_pads)); return 0; } @@ -316,7 +314,9 @@ int board_init(void) /* Address of boot parameters */ gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x1000; -#if 1 +#ifdef CONFIG_OF_LIBFDT + gd->bd->bi_arch_number = -1; +#else gd->bd->bi_arch_number = 4429; #endif ret = setup_pmic_voltages(); @@ -370,12 +370,12 @@ static const iomux_v3_cfg_t mmc1_pads[] = { MX6_PAD_SD3_CLK__GPIO_7_3, }; -static struct tx6dl_esdhc_cfg { +static struct tx6q_esdhc_cfg { const iomux_v3_cfg_t *pads; int num_pads; enum mxc_clock clkid; struct fsl_esdhc_cfg cfg; -} tx6dl_esdhc_cfg[] = { +} tx6qdl_esdhc_cfg[] = { { .pads = mmc0_pads, .num_pads = ARRAY_SIZE(mmc0_pads), @@ -398,11 +398,11 @@ static struct tx6dl_esdhc_cfg { }, }; -static inline struct tx6dl_esdhc_cfg *to_tx6dl_esdhc_cfg(struct fsl_esdhc_cfg *cfg) +static inline struct tx6q_esdhc_cfg *to_tx6q_esdhc_cfg(struct fsl_esdhc_cfg *cfg) { void *p = cfg; - return p - offsetof(struct tx6dl_esdhc_cfg, cfg); + return p - offsetof(struct tx6q_esdhc_cfg, cfg); } int board_mmc_getcd(struct mmc *mmc) @@ -413,7 +413,8 @@ int board_mmc_getcd(struct mmc *mmc) return cfg->cd_gpio; debug("SD card %d is %spresent\n", - to_tx6dl_esdhc_cfg(cfg) - tx6dl_esdhc_cfg, gpio_get_value(cfg->cd_gpio) ? "NOT " : ""); + to_tx6q_esdhc_cfg(cfg) - tx6qdl_esdhc_cfg, + gpio_get_value(cfg->cd_gpio) ? "NOT " : ""); return !gpio_get_value(cfg->cd_gpio); } @@ -421,16 +422,16 @@ int board_mmc_init(bd_t *bis) { int i; - for (i = 0; i < ARRAY_SIZE(tx6dl_esdhc_cfg); i++) { + for (i = 0; i < ARRAY_SIZE(tx6qdl_esdhc_cfg); i++) { struct mmc *mmc; - struct fsl_esdhc_cfg *cfg = &tx6dl_esdhc_cfg[i].cfg; + struct fsl_esdhc_cfg *cfg = &tx6qdl_esdhc_cfg[i].cfg; if (i >= CONFIG_SYS_FSL_ESDHC_NUM) break; - cfg->sdhc_clk = mxc_get_clock(tx6dl_esdhc_cfg[i].clkid); - imx_iomux_v3_setup_multiple_pads(tx6dl_esdhc_cfg[i].pads, - tx6dl_esdhc_cfg[i].num_pads); + cfg->sdhc_clk = mxc_get_clock(tx6qdl_esdhc_cfg[i].clkid); + imx_iomux_v3_setup_multiple_pads(tx6qdl_esdhc_cfg[i].pads, + tx6qdl_esdhc_cfg[i].num_pads); debug("%s: Initializing MMC slot %d\n", __func__, i); fsl_esdhc_initialize(bis, cfg); @@ -463,10 +464,10 @@ int board_eth_init(bd_t *bis) /* delay at least 21ms for the PHY internal POR signal to deassert */ udelay(22000); - imx_iomux_v3_setup_multiple_pads(tx6dl_fec_pads, ARRAY_SIZE(tx6dl_fec_pads)); + imx_iomux_v3_setup_multiple_pads(tx6qdl_fec_pads, ARRAY_SIZE(tx6qdl_fec_pads)); /* Deassert RESET to the external phy */ - gpio_set_value(TX6DL_FEC_RST_GPIO, 1); + gpio_set_value(TX6_FEC_RST_GPIO, 1); ret = cpu_eth_init(bis); if (ret) @@ -497,7 +498,7 @@ void show_activity(int arg) if (led_state == LED_STATE_INIT) { last = get_timer(0); - gpio_set_value(TX6DL_LED_GPIO, 1); + gpio_set_value(TX6_LED_GPIO, 1); led_state = LED_STATE_ON; blink_rate = calc_blink_rate(check_cpu_temperature(0)); } else { @@ -505,9 +506,9 @@ void show_activity(int arg) blink_rate = calc_blink_rate(check_cpu_temperature(0)); last = get_timer_masked(); if (led_state == LED_STATE_ON) { - gpio_set_value(TX6DL_LED_GPIO, 0); + gpio_set_value(TX6_LED_GPIO, 0); } else { - gpio_set_value(TX6DL_LED_GPIO, 1); + gpio_set_value(TX6_LED_GPIO, 1); } led_state = 1 - led_state; } @@ -570,7 +571,7 @@ static const iomux_v3_cfg_t stk5_pads[] = { }; static const struct gpio stk5_gpios[] = { - { TX6DL_LED_GPIO, GPIOF_OUTPUT_INIT_LOW, "HEARTBEAT LED", }, + { TX6_LED_GPIO, GPIOF_OUTPUT_INIT_LOW, "HEARTBEAT LED", }, { IMX_GPIO_NR(3, 23), GPIOF_INPUT, "USBOTG ID", }, { IMX_GPIO_NR(1, 8), GPIOF_INPUT, "USBOTG OC", }, @@ -588,21 +589,136 @@ vidinfo_t panel_info = { .vl_bpix = LCD_COLOR24, /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */ }; -static struct fb_videomode tx6dl_fb_mode = { - /* Standard VGA timing */ - .name = "VGA", - .refresh = 60, - .xres = 640, - .yres = 480, - .pixclock = KHZ2PICOS(25175), - .left_margin = 48, - .hsync_len = 96, - .right_margin = 16, - .upper_margin = 31, - .vsync_len = 2, - .lower_margin = 12, - .sync = FB_SYNC_CLK_LAT_FALL, - .vmode = FB_VMODE_NONINTERLACED, +static struct fb_videomode tx6_fb_modes[] = { + { + /* Standard VGA timing */ + .name = "VGA", + .refresh = 60, + .xres = 640, + .yres = 480, + .pixclock = KHZ2PICOS(25175), + .left_margin = 48, + .hsync_len = 96, + .right_margin = 16, + .upper_margin = 31, + .vsync_len = 2, + .lower_margin = 12, + .sync = FB_SYNC_CLK_LAT_FALL, + }, + { + /* Emerging ETV570 640 x 480 display. Syncs low active, + * DE high active, 115.2 mm x 86.4 mm display area + * VGA compatible timing + */ + .name = "ETV570", + .refresh = 60, + .xres = 640, + .yres = 480, + .pixclock = KHZ2PICOS(25175), + .left_margin = 114, + .hsync_len = 30, + .right_margin = 16, + .upper_margin = 32, + .vsync_len = 3, + .lower_margin = 10, + .sync = FB_SYNC_CLK_LAT_FALL, + }, + { + /* Emerging ET0350G0DH6 320 x 240 display. + * 70.08 mm x 52.56 mm display area. + */ + .name = "ET0350", + .refresh = 60, + .xres = 320, + .yres = 240, + .pixclock = KHZ2PICOS(6500), + .left_margin = 68 - 34, + .hsync_len = 34, + .right_margin = 20, + .upper_margin = 18 - 3, + .vsync_len = 3, + .lower_margin = 4, + .sync = FB_SYNC_CLK_LAT_FALL, + }, + { + /* Emerging ET0430G0DH6 480 x 272 display. + * 95.04 mm x 53.856 mm display area. + */ + .name = "ET0430", + .refresh = 60, + .xres = 480, + .yres = 272, + .pixclock = KHZ2PICOS(9000), + .left_margin = 2, + .hsync_len = 41, + .right_margin = 2, + .upper_margin = 2, + .vsync_len = 10, + .lower_margin = 2, + .sync = FB_SYNC_CLK_LAT_FALL, + }, + { + /* Emerging ET0500G0DH6 800 x 480 display. + * 109.6 mm x 66.4 mm display area. + */ + .name = "ET0500", + .refresh = 60, + .xres = 800, + .yres = 480, + .pixclock = KHZ2PICOS(33260), + .left_margin = 216 - 128, + .hsync_len = 128, + .right_margin = 1056 - 800 - 216, + .upper_margin = 35 - 2, + .vsync_len = 2, + .lower_margin = 525 - 480 - 35, + .sync = FB_SYNC_CLK_LAT_FALL, + }, + { + /* Emerging ETQ570G0DH6 320 x 240 display. + * 115.2 mm x 86.4 mm display area. + */ + .name = "ETQ570", + .refresh = 60, + .xres = 320, + .yres = 240, + .pixclock = KHZ2PICOS(6400), + .left_margin = 38, + .hsync_len = 30, + .right_margin = 30, + .upper_margin = 16, /* 15 according to datasheet */ + .vsync_len = 3, /* TVP -> 1>x>5 */ + .lower_margin = 4, /* 4.5 according to datasheet */ + .sync = FB_SYNC_CLK_LAT_FALL, + }, + { + /* Emerging ET0700G0DH6 800 x 480 display. + * 152.4 mm x 91.44 mm display area. + */ + .name = "ET0700", + .refresh = 60, + .xres = 800, + .yres = 480, + .pixclock = KHZ2PICOS(33260), + .left_margin = 216 - 128, + .hsync_len = 128, + .right_margin = 1056 - 800 - 216, + .upper_margin = 35 - 2, + .vsync_len = 2, + .lower_margin = 525 - 480 - 35, + .sync = FB_SYNC_CLK_LAT_FALL, + }, + { + /* unnamed entry for assigning parameters parsed from 'video_mode' string */ + .refresh = 60, + .left_margin = 48, + .hsync_len = 96, + .right_margin = 16, + .upper_margin = 31, + .vsync_len = 2, + .lower_margin = 12, + .sync = FB_SYNC_CLK_LAT_FALL, + }, }; static int lcd_enabled = 1; @@ -619,11 +735,11 @@ void lcd_enable(void) karo_load_splashimage(1); if (lcd_enabled) { debug("Switching LCD on\n"); - gpio_set_value(TX6DL_LCD_PWR_GPIO, 1); + gpio_set_value(TX6_LCD_PWR_GPIO, 1); udelay(100); - gpio_set_value(TX6DL_LCD_RST_GPIO, 1); + gpio_set_value(TX6_LCD_RST_GPIO, 1); udelay(300000); - gpio_set_value(TX6DL_LCD_BACKLIGHT_GPIO, 0); + gpio_set_value(TX6_LCD_BACKLIGHT_GPIO, 0); } } @@ -667,9 +783,9 @@ static const iomux_v3_cfg_t stk5_lcd_pads[] = { }; static const struct gpio stk5_lcd_gpios[] = { - { TX6DL_LCD_RST_GPIO, GPIOF_OUTPUT_INIT_LOW, "LCD RESET", }, - { TX6DL_LCD_PWR_GPIO, GPIOF_OUTPUT_INIT_LOW, "LCD POWER", }, - { TX6DL_LCD_BACKLIGHT_GPIO, GPIOF_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", }, + { TX6_LCD_RST_GPIO, GPIOF_OUTPUT_INIT_LOW, "LCD RESET", }, + { TX6_LCD_PWR_GPIO, GPIOF_OUTPUT_INIT_LOW, "LCD POWER", }, + { TX6_LCD_BACKLIGHT_GPIO, GPIOF_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", }, }; void lcd_ctrl_init(void *lcdbase) @@ -678,7 +794,8 @@ void lcd_ctrl_init(void *lcdbase) char *vm; unsigned long val; int refresh = 60; - struct fb_videomode *p = &tx6dl_fb_mode; + struct fb_videomode *p = &tx6_fb_modes[0]; + struct fb_videomode fb_mode; int xres_set = 0, yres_set = 0, bpp_set = 0, refresh_set = 0; int pix_fmt = 0; ipu_di_clk_parent_t di_clk_parent = DI_PCLK_PLL3; @@ -695,12 +812,35 @@ void lcd_ctrl_init(void *lcdbase) return; } + karo_fdt_move_fdt(); + vm = getenv("video_mode"); if (vm == NULL) { debug("Disabling LCD\n"); lcd_enabled = 0; return; } + if (karo_fdt_get_fb_mode(working_fdt, vm, &fb_mode) == 0) { + p = &fb_mode; + debug("Using video mode from FDT\n"); + vm += strlen(vm); + if (fb_mode.xres < panel_info.vl_col) + panel_info.vl_col = fb_mode.xres; + if (fb_mode.yres < panel_info.vl_row) + panel_info.vl_row = fb_mode.yres; + } + if (p->name != NULL) + debug("Trying compiled-in video modes\n"); + while (p->name != NULL) { + if (strcmp(p->name, vm) == 0) { + debug("Using video mode: '%s'\n", p->name); + vm += strlen(vm); + break; + } + p++; + } + if (*vm != '\0') + debug("Trying to decode video_mode: '%s'\n", vm); while (*vm != '\0') { if (*vm >= '0' && *vm <= '9') { char *end; @@ -781,18 +921,15 @@ void lcd_ctrl_init(void *lcdbase) vm++; } } - switch (color_depth) { - case 8: - panel_info.vl_bpix = 3; - break; - - case 16: - panel_info.vl_bpix = 4; - break; - - case 18: - case 24: - panel_info.vl_bpix = 5; + if (p->xres == 0 || p->yres == 0) { + printf("Invalid video mode: %s\n", getenv("video_mode")); + lcd_enabled = 0; + printf("Supported video modes are:"); + for (p = &tx6_fb_modes[0]; p->name != NULL; p++) { + printf(" %s", p->name); + } + printf("\n"); + return; } p->pixclock = KHZ2PICOS(refresh * @@ -853,7 +990,7 @@ static void stk5v5_board_init(void) imx_iomux_v3_setup_pad(MX6_PAD_DISP0_DAT0__GPIO_4_21); } -static void tx6dl_set_cpu_clock(void) +static void tx6qdl_set_cpu_clock(void) { unsigned long cpu_clk = getenv_ulong("cpu_clk", 10, 0); @@ -895,7 +1032,7 @@ int board_late_init(void) int ret = 0; const char *baseboard; - tx6dl_set_cpu_clock(); + tx6qdl_set_cpu_clock(); karo_fdt_move_fdt(); baseboard = getenv("baseboard"); @@ -923,39 +1060,20 @@ int board_late_init(void) exit: tx6_init_mac(); - gpio_set_value(TX6DL_RESET_OUT_GPIO, 1); + gpio_set_value(TX6_RESET_OUT_GPIO, 1); return ret; } -#define iomux_field(v,f) (((iomux_v3_cfg_t)(v) << f##_SHIFT) & f##_MASK) - -#define chk_iomux_field(f1,f2) ({ \ - iomux_v3_cfg_t __c = iomux_field(~0, f1); \ - if (__c & f2##_MASK) { \ - printf("%18s[%016llx] overlaps with:\n%18s[%016llx]\n", \ - #f1, f1##_MASK, \ - #f2, f2##_MASK); \ - } \ - (__c & f2##_MASK) != 0; \ -}) - -#define chk_iomux_bit(f1,f2) ({ \ - iomux_v3_cfg_t __c = iomux_field(~0, f1); \ - if (__c & f2) { \ - printf("%18s[%016llx] overlaps with:\n%18s[%016llx]\n", \ - #f1, f1##_MASK, \ - #f2, (iomux_v3_cfg_t)f2); \ - } \ - (__c & f2) != 0; \ -}) - int checkboard(void) { print_cpuinfo(); - +#if defined(CONFIG_MX6Q) + printf("Board: Ka-Ro TX6Q\n"); +#elif defined(CONFIG_MX6DL) printf("Board: Ka-Ro TX6DL\n"); - - printf("mtdparts='%s'\n", MTDPARTS_DEFAULT); +#else +#error Unsupported i.MX6 variant selected +#endif #ifdef TIMER_TEST { @@ -1024,13 +1142,15 @@ struct node_info nodes[] = { #define fdt_fixup_mtdparts(b,n,c) do { } while (0) #endif -static void tx6dl_fixup_flexcan(void *blob) +static void tx6qdl_fixup_flexcan(void *blob) { const char *baseboard = getenv("baseboard"); if (baseboard && strcmp(baseboard, "stk5-v5") == 0) return; - /* TODO: handle flexcan transceiver GPIO */ + + karo_fdt_del_prop(blob, "fsl,p1010-flexcan", 0x02090000, "transceiver-switch"); + karo_fdt_del_prop(blob, "fsl,p1010-flexcan", 0x02094000, "transceiver-switch"); } void ft_board_setup(void *blob, bd_t *bd) @@ -1039,7 +1159,7 @@ void ft_board_setup(void *blob, bd_t *bd) fdt_fixup_ethernet(blob); karo_fdt_fixup_touchpanel(blob); - karo_fdt_fixup_usb_otg(blob, "", 0); - tx6dl_fixup_flexcan(blob); + karo_fdt_fixup_usb_otg(blob, "usbotg", "fsl,usbphy"); + tx6qdl_fixup_flexcan(blob); } #endif diff --git a/board/karo/tx6q/u-boot.lds b/board/karo/tx6/u-boot.lds similarity index 97% rename from board/karo/tx6q/u-boot.lds rename to board/karo/tx6/u-boot.lds index bcbafe9801..f8eaef056f 100644 --- a/board/karo/tx6q/u-boot.lds +++ b/board/karo/tx6/u-boot.lds @@ -29,7 +29,7 @@ SECTIONS . = ALIGN(4); .text : { - board/karo/tx6q/lowlevel_init.o (.text*) + board/karo/tx6/lowlevel_init.o (.text*) __image_copy_start = .; CPUDIR/start.o (.text*) *(.text*) diff --git a/board/karo/tx6dl/config.mk b/board/karo/tx6dl/config.mk deleted file mode 100644 index 61ca972433..0000000000 --- a/board/karo/tx6dl/config.mk +++ /dev/null @@ -1,32 +0,0 @@ -# stack is allocated below CONFIG_SYS_TEXT_BASE -CONFIG_SYS_TEXT_BASE := 0x27800000 -#CONFIG_SYS_TEXT_BASE := 0x17800000 -#CONFIG_SPL_TEXT_BASE := 0x00000000 - -LOGO_BMP = logos/karo.bmp -#PLATFORM_CPPFLAGS += -DDEBUG -#PLATFORM_CPPFLAGS += -Wno-unused-but-set-variable - -# calculate U_BOOT_IMG_SIZE to be at least 3 eraseblocks larger than the maximum expected image size -ifneq ($(CONFIG_SYS_NAND_ERASE_SIZE),) -CONFIG_U_BOOT_IMG_SIZE = $(shell echo 'e=$(CONFIG_SYS_NAND_ERASE_SIZE);s=640*1024;s + e%s%e + 3*e' | bc) -CONFIG_SYS_USERFS_SIZE = $(shell expr \( $(CONFIG_SYS_NAND_BLOCKS) - 9 \) \* $(CONFIG_SYS_NAND_ERASE_SIZE) - $(CONFIG_U_BOOT_IMG_SIZE) - 36 \* 1048576) -CONFIG_SYS_USERFS_SIZE2 = $(shell expr \( $(CONFIG_SYS_NAND_BLOCKS) - 12 \) \* $(CONFIG_SYS_NAND_ERASE_SIZE) - $(CONFIG_U_BOOT_IMG_SIZE) - 36 \* 1048576) - -PLATFORM_CPPFLAGS += -DCONFIG_U_BOOT_IMG_SIZE=$(CONFIG_U_BOOT_IMG_SIZE) -PLATFORM_CPPFLAGS += -DCONFIG_SYS_U_BOOT_PART_SIZE=$(shell printf "%uk" `expr $(CONFIG_U_BOOT_IMG_SIZE) / 1024`) -PLATFORM_CPPFLAGS += -DCONFIG_SYS_U_BOOT_OFFSET=$(shell printf "0x%x" `expr $(CONFIG_SYS_NAND_ERASE_SIZE)`) -PLATFORM_CPPFLAGS += -DCONFIG_SYS_ENV_PART_SIZE=$(shell printf "%uk" `expr 3 \* $(CONFIG_SYS_NAND_ERASE_SIZE) / 1024`) -PLATFORM_CPPFLAGS += -DCONFIG_SYS_USERFS_PART_SIZE=$(shell printf "%uk" `expr $(CONFIG_SYS_USERFS_SIZE) / 1024`) -PLATFORM_CPPFLAGS += -DCONFIG_SYS_USERFS_PART_SIZE2=$(shell printf "%uk" `expr $(CONFIG_SYS_USERFS_SIZE) / 1024`) -PLATFORM_CPPFLAGS += -DCONFIG_SYS_DTB_PART_SIZE=$(shell printf "%uk" `expr $(CONFIG_SYS_NAND_ERASE_SIZE) / 1024`) -PLATFORM_CPPFLAGS += -DCONFIG_SYS_NAND_BBT_SIZE=$(shell printf "%uk" `expr 4 \* $(CONFIG_SYS_NAND_ERASE_SIZE) / 1024`) -PLATFORM_CPPFLAGS += -DCONFIG_SYS_NAND_BBT_OFFSET=$(shell printf "0x%x" `expr \( $(CONFIG_SYS_NAND_BLOCKS) - 4 \) \* $(CONFIG_SYS_NAND_ERASE_SIZE)`) -endif - -PLATFORM_CPPFLAGS += -Werror -PLATFORM_CPPFLAGS += -DDEBUG - -#ifneq ($(CONFIG_SPL_BUILD),y) -# ALL-y += $(obj)u-boot.sb -#endif diff --git a/board/karo/tx6dl/u-boot.lds b/board/karo/tx6dl/u-boot.lds deleted file mode 100644 index a1b0fc32ce..0000000000 --- a/board/karo/tx6dl/u-boot.lds +++ /dev/null @@ -1,85 +0,0 @@ -/* - * (C) Copyright 2012 Lothar Waßmann - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -ENTRY(_start) -SECTIONS -{ - . = 0x00000000; - - . = ALIGN(4); - .text : - { - board/karo/tx6dl/lowlevel_init.o (.text*) - __image_copy_start = .; - CPUDIR/start.o (.text*) - *(.text*) - } - - . = ALIGN(4); - .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } - - . = ALIGN(4); - .data : { - *(.data*) - } - - . = ALIGN(4); - - . = .; - - . = ALIGN(4); - .u_boot_list : { - #include - } - - . = ALIGN(4); - - __image_copy_end = .; - - .rel.dyn : { - __rel_dyn_start = .; - *(.rel*) - __rel_dyn_end = .; - } - - .dynsym : { - __dynsym_start = .; - *(.dynsym) - } - - _end = .; - __u_boot_img_size = _end - _start; - - .bss __rel_dyn_start (OVERLAY) : { - __bss_start = .; - *(.bss) - . = ALIGN(4); - __bss_end__ = .; - } - - /DISCARD/ : { *(.dynstr*) } - /DISCARD/ : { *(.dynamic*) } - /DISCARD/ : { *(.plt*) } - /DISCARD/ : { *(.interp*) } - /DISCARD/ : { *(.gnu*) } -} diff --git a/board/karo/tx6q/Makefile b/board/karo/tx6q/Makefile deleted file mode 100644 index be98fabf19..0000000000 --- a/board/karo/tx6q/Makefile +++ /dev/null @@ -1,47 +0,0 @@ -# -# (C) Copyright 2009 DENX Software Engineering -# Author: John Rigby -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := tx6q.o -SOBJS := lowlevel_init.o -ifeq ($(CONFIG_CMD_ROMUPDATE),y) - COBJS += flash.o -endif - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -######################################################################### - -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/karo/tx6q/flash.c b/board/karo/tx6q/flash.c deleted file mode 100644 index 6b0c40cd55..0000000000 --- a/board/karo/tx6q/flash.c +++ /dev/null @@ -1,662 +0,0 @@ -#include -#include -#include -#include - -#include - -#include -#include -#include -#include -#include - -#if CONFIG_SYS_NAND_U_BOOT_OFFS < 0x20000 -#error CONFIG_SYS_NAND_U_BOOT_OFFS must be >= 128kIB -#endif - -struct mx6_nand_timing { - u8 data_setup; - u8 data_hold; - u8 address_setup; - u8 dsample_time; - u8 nand_timing_state; - u8 tREA; - u8 tRLOH; - u8 tRHOH; -}; - -struct mx6_fcb { - u32 checksum; - u32 fingerprint; - u32 version; - struct mx6_nand_timing timing; - u32 page_data_size; - u32 total_page_size; - u32 sectors_per_block; - u32 number_of_nands; /* not used by ROM code */ - u32 total_internal_die; /* not used by ROM code */ - u32 cell_type; /* not used by ROM code */ - u32 ecc_blockn_type; - u32 ecc_block0_size; - u32 ecc_blockn_size; - u32 ecc_block0_type; - u32 metadata_size; - u32 ecc_blocks_per_page; - u32 rsrvd1[6]; /* not used by ROM code */ - u32 bch_mode; /* erase_threshold */ - u32 rsrvd2[2]; - u32 fw1_start_page; - u32 fw2_start_page; - u32 fw1_sectors; - u32 fw2_sectors; - u32 dbbt_search_area; - u32 bb_mark_byte; - u32 bb_mark_startbit; - u32 bb_mark_phys_offset; - u32 bch_type; - u32 rsrvd3[8]; /* Toggle NAND timing parameters */ - u32 disbbm; - u32 bb_mark_spare_offset; - u32 rsrvd4[9]; /* ONFI NAND parameters */ - u32 disbb_search; -}; - -struct mx6_dbbt_header { - u32 checksum; - u32 fingerprint; - u32 version; - u32 number_bb; - u32 number_pages; - u8 spare[492]; -}; - -struct mx6_dbbt { - u32 nand_number; - u32 number_bb; - u32 bb_num[2040 / 4]; -}; - -#define BF_VAL(v, bf) (((v) & bf##_MASK) >> bf##_OFFSET) - -static nand_info_t *mtd = &nand_info[0]; - -extern void *_start; - -#define BIT(v,n) (((v) >> (n)) & 0x1) - -static inline void memdump(const void *addr, size_t len) -{ - const char *buf = addr; - int i; - - for (i = 0; i < len; i++) { - if (i % 16 == 0) { - if (i > 0) - printf("\n"); - printf("%p:", &buf[i]); - } - printf(" %02x", buf[i]); - } - printf("\n"); -} - -static u8 calculate_parity_13_8(u8 d) -{ - u8 p = 0; - - p |= (BIT(d, 6) ^ BIT(d, 5) ^ BIT(d, 3) ^ BIT(d, 2)) << 0; - p |= (BIT(d, 7) ^ BIT(d, 5) ^ BIT(d, 4) ^ BIT(d, 2) ^ BIT(d, 1)) << 1; - p |= (BIT(d, 7) ^ BIT(d, 6) ^ BIT(d, 5) ^ BIT(d, 1) ^ BIT(d, 0)) << 2; - p |= (BIT(d, 7) ^ BIT(d, 4) ^ BIT(d, 3) ^ BIT(d, 0)) << 3; - p |= (BIT(d, 6) ^ BIT(d, 4) ^ BIT(d, 3) ^ BIT(d, 2) ^ BIT(d, 1) ^ BIT(d, 0)) << 4; - return p; -} - -static void encode_hamming_13_8(void *_src, void *_ecc, size_t size) -{ - int i; - u8 *src = _src; - u8 *ecc = _ecc; - - for (i = 0; i < size; i++) - ecc[i] = calculate_parity_13_8(src[i]); -} - -static u32 calc_chksum(void *buf, size_t size) -{ - u32 chksum = 0; - u8 *bp = buf; - size_t i; - - for (i = 0; i < size; i++) { - chksum += bp[i]; - } - return ~chksum; -} - -/* - Physical organisation of data in NAND flash: - metadata - payload chunk 0 (may be empty) - ecc for metadata + payload chunk 0 - payload chunk 1 - ecc for payload chunk 1 -... - payload chunk n - ecc for payload chunk n - */ - -static int calc_bb_offset(nand_info_t *mtd, struct mx6_fcb *fcb) -{ - int bb_mark_offset; - int chunk_data_size = fcb->ecc_blockn_size * 8; - int chunk_ecc_size = (fcb->ecc_blockn_type << 1) * 13; - int chunk_total_size = chunk_data_size + chunk_ecc_size; - int bb_mark_chunk, bb_mark_chunk_offs; - - bb_mark_offset = (mtd->writesize - fcb->metadata_size) * 8; - if (fcb->ecc_block0_size == 0) - bb_mark_offset -= (fcb->ecc_block0_type << 1) * 13; - - bb_mark_chunk = bb_mark_offset / chunk_total_size; - bb_mark_chunk_offs = bb_mark_offset - (bb_mark_chunk * chunk_total_size); - if (bb_mark_chunk_offs > chunk_data_size) { - printf("Unsupported ECC layout; BB mark resides in ECC data: %u\n", - bb_mark_chunk_offs); - return -EINVAL; - } - bb_mark_offset -= bb_mark_chunk * chunk_ecc_size; - return bb_mark_offset; -} - -#define pr_fcb_val(p, n) debug("%s=%08x(%d)\n", #n, (p)->n, (p)->n) - -static struct mx6_fcb *create_fcb(void *buf, int fw1_start_block, - int fw2_start_block, size_t fw_size) -{ - struct gpmi_regs *gpmi_base = (struct gpmi_regs *)GPMI_BASE_ADDRESS; - struct bch_regs *bch_base = (struct bch_regs *)BCH_BASE_ADDRESS; - u32 fl0, fl1; - u32 t0; - int metadata_size; - int bb_mark_bit_offs; - struct mx6_fcb *fcb; - int fcb_offs; - - if (gpmi_base == NULL || bch_base == NULL) { - return ERR_PTR(-ENOMEM); - } - - fl0 = readl(&bch_base->hw_bch_flash0layout0); - fl1 = readl(&bch_base->hw_bch_flash0layout1); - t0 = readl(&gpmi_base->hw_gpmi_timing0); - - metadata_size = BF_VAL(fl0, BCH_FLASHLAYOUT0_META_SIZE); - - fcb = buf + ALIGN(metadata_size, 4); - fcb_offs = (void *)fcb - buf; - - memset(buf, 0xff, fcb_offs); - memset(fcb, 0x00, sizeof(*fcb)); - memset(fcb + 1, 0xff, mtd->erasesize - fcb_offs - sizeof(*fcb)); - - strncpy((char *)&fcb->fingerprint, "FCB ", 4); - fcb->version = cpu_to_be32(1); - - fcb->disbb_search = 1; - fcb->disbbm = 1; - - /* ROM code assumes GPMI clock of 25 MHz */ - fcb->timing.data_setup = BF_VAL(t0, GPMI_TIMING0_DATA_SETUP) * 40; - fcb->timing.data_hold = BF_VAL(t0, GPMI_TIMING0_DATA_HOLD) * 40; - fcb->timing.address_setup = BF_VAL(t0, GPMI_TIMING0_ADDRESS_SETUP) * 40; - - fcb->page_data_size = mtd->writesize; - fcb->total_page_size = mtd->writesize + mtd->oobsize; - fcb->sectors_per_block = mtd->erasesize / mtd->writesize; - - fcb->ecc_block0_type = BF_VAL(fl0, BCH_FLASHLAYOUT0_ECC0); - fcb->ecc_block0_size = BF_VAL(fl0, BCH_FLASHLAYOUT0_DATA0_SIZE) * 4; - fcb->ecc_blockn_type = BF_VAL(fl1, BCH_FLASHLAYOUT1_ECCN); - fcb->ecc_blockn_size = BF_VAL(fl1, BCH_FLASHLAYOUT1_DATAN_SIZE) * 4; - - pr_fcb_val(fcb, ecc_block0_type); - pr_fcb_val(fcb, ecc_blockn_type); - pr_fcb_val(fcb, ecc_block0_size); - pr_fcb_val(fcb, ecc_blockn_size); - - fcb->metadata_size = BF_VAL(fl0, BCH_FLASHLAYOUT0_META_SIZE); - fcb->ecc_blocks_per_page = BF_VAL(fl0, BCH_FLASHLAYOUT0_NBLOCKS); - fcb->bch_mode = readl(&bch_base->hw_bch_mode); - fcb->bch_type = 0; /* BCH20 */ - - fcb->fw1_start_page = fw1_start_block * mtd->erasesize / mtd->writesize; - fcb->fw1_sectors = DIV_ROUND_UP(fw_size, mtd->writesize); - - if (fw2_start_block != 0 && fw2_start_block < mtd->size / mtd->erasesize) { - fcb->fw2_start_page = fw2_start_block * mtd->erasesize / mtd->writesize; - fcb->fw2_sectors = fcb->fw1_sectors; - } - - fcb->dbbt_search_area = 1; - - bb_mark_bit_offs = calc_bb_offset(mtd, fcb); - if (bb_mark_bit_offs < 0) - return ERR_PTR(bb_mark_bit_offs); - fcb->bb_mark_byte = bb_mark_bit_offs / 8; - fcb->bb_mark_startbit = bb_mark_bit_offs % 8; - fcb->bb_mark_phys_offset = mtd->writesize; - - pr_fcb_val(fcb, bb_mark_byte); - pr_fcb_val(fcb, bb_mark_startbit); - pr_fcb_val(fcb, bb_mark_phys_offset); - - fcb->checksum = calc_chksum(&fcb->fingerprint, 512 - 4); - return fcb; -} - -static inline int find_fcb(void *ref, int page) -{ - int ret = 0; - struct nand_chip *chip = mtd->priv; - void *buf = malloc(mtd->erasesize); - - if (buf == NULL) { - return -ENOMEM; - } - chip->select_chip(mtd, 0); - chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page); - ret = chip->ecc.read_page_raw(mtd, chip, buf, page); - if (ret) { - printf("Failed to read FCB from page %u: %d\n", page, ret); - return ret; - } - chip->select_chip(mtd, -1); - if (memcmp(buf, ref, mtd->writesize) == 0) { - debug("Found FCB in page %u (%08x)\n", - page, page * mtd->writesize); - ret = 1; - } - free(buf); - return ret; -} - -static int write_fcb(void *buf, int block) -{ - int ret; - struct nand_chip *chip = mtd->priv; - int page = block * mtd->erasesize / mtd->writesize; - - ret = find_fcb(buf, page); - if (ret > 0) { - printf("FCB at block %d is up to date\n", block); - return 0; - } - - ret = nand_erase(mtd, block * mtd->erasesize, mtd->erasesize); - if (ret) { - printf("Failed to erase FCB block %u\n", block); - return ret; - } - - printf("Writing FCB to block %d @ %08x\n", block, - block * mtd->erasesize); - chip->select_chip(mtd, 0); - ret = chip->write_page(mtd, chip, buf, page, 0, 1); - if (ret) { - printf("Failed to write FCB to block %u: %d\n", block, ret); - } - chip->select_chip(mtd, -1); - - return ret; -} - -struct mx6_ivt { - u32 magic; - u32 entry; - u32 rsrvd1; - void *dcd; - void *boot_data; - void *self; - void *csf; - u32 rsrvd2; -}; - -struct mx6_boot_data { - u32 start; - u32 length; - u32 plugin; -}; - -static size_t count_good_blocks(int start, int end) -{ - size_t max_len = (end - start + 1); - int block; - - for (block = start; block <= end; block++) { - if (nand_block_isbad(mtd, block * mtd->erasesize)) - max_len--; - } - return max_len; -} - -static int find_ivt(void *buf) -{ - struct mx6_ivt *ivt_hdr = buf + 0x400; - - if ((ivt_hdr->magic & 0xff0000ff) != 0x400000d1) - return 0; - - return 1; -} - -static inline void *reloc(void *dst, void *base, void *ptr) -{ - return dst + (ptr - base); -} - -static int patch_ivt(void *buf, size_t fsize) -{ - struct mx6_ivt *ivt_hdr = buf + 0x400; - struct mx6_boot_data *boot_data; - - if (!find_ivt(buf)) { - printf("No IVT found in image at %p\n", buf); - return -EINVAL; - } - boot_data = reloc(ivt_hdr, ivt_hdr->self, ivt_hdr->boot_data); - boot_data->length = fsize; - - return 0; -} - -#define chk_overlap(a,b) \ - ((a##_start_block <= b##_end_block && \ - a##_end_block >= b##_start_block) || \ - (b##_start_block <= a##_end_block && \ - b##_end_block >= a##_start_block)) - -#define fail_if_overlap(a,b,m1,m2) do { \ - if (chk_overlap(a, b)) { \ - printf("%s blocks %lu..%lu overlap %s in blocks %lu..%lu!\n", \ - m1, a##_start_block, a##_end_block, \ - m2, b##_start_block, b##_end_block); \ - return -EINVAL; \ - } \ -} while (0) - -#ifdef CONFIG_ENV_IS_IN_NAND -#ifndef CONFIG_ENV_OFFSET_REDUND -#define TOTAL_ENV_SIZE CONFIG_ENV_RANGE -#else -#define TOTAL_ENV_SIZE (CONFIG_ENV_RANGE * 2) -#endif -#endif - -#define pr_fcb_offset(n) printf("%s: %04x (%d)\n", #n, \ - offsetof(struct mx6_fcb, n), offsetof(struct mx6_fcb, n)) - -int do_update(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) -{ - int ret; - const unsigned long fcb_start_block = 0, fcb_end_block = 0; - int erase_size = mtd->erasesize; - int page_size = mtd->writesize; - void *buf; - char *load_addr; - char *file_size; - size_t size = 0; - void *addr = NULL; - struct mx6_fcb *fcb; - unsigned long mtd_num_blocks = mtd->size / mtd->erasesize; -#ifdef CONFIG_ENV_IS_IN_NAND - unsigned long env_start_block = CONFIG_ENV_OFFSET / mtd->erasesize; - unsigned long env_end_block = env_start_block + - DIV_ROUND_UP(TOTAL_ENV_SIZE, mtd->erasesize) - 1; -#endif - int optind; - int fw1_set = 0; - int fw2_set = 0; - unsigned long fw1_start_block = 0, fw1_end_block; - unsigned long fw2_start_block = 0, fw2_end_block; - unsigned long fw_num_blocks; - unsigned long extra_blocks = 2; - nand_erase_options_t erase_opts = { 0, }; - size_t max_len1, max_len2; - - for (optind = 1; optind < argc; optind++) { - if (strcmp(argv[optind], "-f") == 0) { - if (optind >= argc - 1) { - printf("Option %s requires an argument\n", - argv[optind]); - return -EINVAL; - } - optind++; - fw1_start_block = simple_strtoul(argv[optind], NULL, 0); - if (fw1_start_block >= mtd_num_blocks) { - printf("Block number %lu is out of range: 0..%lu\n", - fw1_start_block, mtd_num_blocks - 1); - return -EINVAL; - } - fw1_set = 1; - } else if (strcmp(argv[optind], "-r") == 0) { - if (optind < argc - 1 && argv[optind + 1][0] != '-') { - optind++; - fw2_start_block = simple_strtoul(argv[optind], - NULL, 0); - if (fw2_start_block >= mtd_num_blocks) { - printf("Block number %lu is out of range: 0..%lu\n", - fw2_start_block, - mtd_num_blocks - 1); - return -EINVAL; - } - } - fw2_set = 1; - } else if (strcmp(argv[optind], "-e") == 0) { - if (optind >= argc - 1) { - printf("Option %s requires an argument\n", - argv[optind]); - return -EINVAL; - } - optind++; - extra_blocks = simple_strtoul(argv[optind], NULL, 0); - if (extra_blocks >= mtd_num_blocks) { - printf("Extra block count %lu is out of range: 0..%lu\n", - extra_blocks, - mtd_num_blocks - 1); - return -EINVAL; - } - } else if (argv[optind][0] == '-') { - printf("Unrecognized option %s\n", argv[optind]); - return -EINVAL; - } else { - break; - } - } - - load_addr = getenv("fileaddr"); - file_size = getenv("filesize"); - - if (argc - optind < 1 && load_addr == NULL) { - printf("Load address not specified\n"); - return -EINVAL; - } - if (argc - optind < 2 && file_size == NULL) { - printf("WARNING: Image size not specified; overwriting whole uboot partition\n"); - } - if (argc > optind) { - load_addr = NULL; - addr = (void *)simple_strtoul(argv[optind], NULL, 16); - optind++; - } - if (argc > optind) { - file_size = NULL; - size = simple_strtoul(argv[optind], NULL, 16); - optind++; - } - if (load_addr != NULL) { - addr = (void *)simple_strtoul(load_addr, NULL, 16); - printf("Using default load address %p\n", addr); - } - if (file_size != NULL) { - size = simple_strtoul(file_size, NULL, 16); - printf("Using default file size %08x\n", size); - } - if (size > 0) - fw_num_blocks = DIV_ROUND_UP(size, mtd->erasesize); - else - fw_num_blocks = CONFIG_U_BOOT_IMG_SIZE / mtd->erasesize - extra_blocks; - - if (!fw1_set) { - fw1_start_block = CONFIG_SYS_NAND_U_BOOT_OFFS / mtd->erasesize; - fw1_end_block = fw1_start_block + fw_num_blocks + extra_blocks - 1; - } else { - fw1_end_block = fw1_start_block + fw_num_blocks + extra_blocks - 1; - } - - if (fw2_set && fw2_start_block == 0) { - fw2_start_block = fw1_end_block + 1; - fw2_end_block = fw2_start_block + fw_num_blocks + extra_blocks - 1; - } else { - fw2_end_block = fw2_start_block + fw_num_blocks + extra_blocks - 1; - } - -#ifdef CONFIG_ENV_IS_IN_NAND - fail_if_overlap(fcb, env, "FCB", "Environment"); - fail_if_overlap(fw1, env, "FW1", "Environment"); -#endif - fail_if_overlap(fcb, fw1, "FCB", "FW1"); - if (fw2_set) { - fail_if_overlap(fcb, fw2, "FCB", "FW2"); -#ifdef CONFIG_ENV_IS_IN_NAND - fail_if_overlap(fw2, env, "FW2", "Environment"); -#endif - fail_if_overlap(fw1, fw2, "FW1", "FW2"); - } - - buf = malloc(erase_size); - if (buf == NULL) { - printf("Failed to allocate buffer\n"); - return -ENOMEM; - } - - /* search for bad blocks in FW1 block range */ - max_len1 = count_good_blocks(fw1_start_block, fw1_end_block); - printf("%u good blocks in %lu..%lu\n", - max_len1, fw1_start_block, fw1_end_block); - if (fw_num_blocks > max_len1) { - printf("Too many bad blocks in FW1 block range: %lu..%lu; max blocks: %u\n", - fw1_end_block + 1 - fw_num_blocks - extra_blocks, - fw1_end_block, max_len1); - return -EINVAL; - } - - /* search for bad blocks in FW2 block range */ - max_len2 = count_good_blocks(fw2_start_block, fw2_end_block); - if (fw2_start_block > 0 && fw_num_blocks > max_len2) { - printf("Too many bad blocks in FW2 block range: %lu..%lu\n", - fw2_end_block + 1 - fw_num_blocks - extra_blocks, - fw2_end_block); - return -EINVAL; - } - - fcb = create_fcb(buf, fw1_start_block, fw2_start_block, - ALIGN(fw_num_blocks * mtd->erasesize, mtd->writesize)); - if (IS_ERR(fcb)) { - printf("Failed to initialize FCB: %ld\n", PTR_ERR(fcb)); - return PTR_ERR(fcb); - } - encode_hamming_13_8(fcb, (void *)fcb + 512, 512); - - ret = write_fcb(buf, fcb_start_block); - if (ret) { - printf("Failed to write FCB to block %lu\n", fcb_start_block); - return ret; - } - - if (ret) { - } - - ret = patch_ivt(addr, size ?: fw_num_blocks * mtd->erasesize); - if (ret) { - return ret; - } - - printf("Programming U-Boot image from %p to block %lu\n", - addr, fw1_start_block); - if (size & (page_size - 1)) { - memset(addr + size, 0xff, size & (page_size - 1)); - size = ALIGN(size, page_size); - } - - erase_opts.offset = fcb->fw1_start_page * page_size; - erase_opts.length = (fw1_end_block - fw1_start_block + 1) * - mtd->erasesize; - erase_opts.quiet = 1; - - printf("Erasing flash @ %08llx..%08llx\n", erase_opts.offset, - erase_opts.offset + erase_opts.length - 1); - - ret = nand_erase_opts(mtd, &erase_opts); - if (ret) { - printf("Failed to erase flash: %d\n", ret); - return ret; - } - if (size == 0) - max_len1 *= mtd->erasesize; - else - max_len1 = size; - - printf("Programming flash @ %08x..%08x from %p\n", - fcb->fw1_start_page * page_size, - fcb->fw1_start_page * page_size + max_len1 - 1, addr); - ret = nand_write_skip_bad(mtd, fcb->fw1_start_page * page_size, - &max_len1, addr, WITH_DROP_FFS); - if (ret) { - printf("Failed to program flash: %d\n", ret); - return ret; - } - if (fw2_start_block == 0) { - return ret; - } - - printf("Programming redundant U-Boot image to block %lu\n", - fw2_start_block); - erase_opts.offset = fcb->fw2_start_page * page_size; - erase_opts.length = (fw2_end_block - fw2_start_block + 1) * - mtd->erasesize; - printf("Erasing flash @ %08llx..%08llx\n", erase_opts.offset, - erase_opts.offset + erase_opts.length - 1); - - ret = nand_erase_opts(mtd, &erase_opts); - if (ret) { - printf("Failed to erase flash: %d\n", ret); - return ret; - } - if (size == 0) - max_len2 *= mtd->erasesize; - else - max_len2 = size; - printf("Programming flash @ %08x..%08x from %p\n", - fcb->fw2_start_page * page_size, - fcb->fw2_start_page * page_size + max_len2 - 1, addr); - ret = nand_write_skip_bad(mtd, fcb->fw2_start_page * page_size, - &max_len2, addr, WITH_DROP_FFS); - if (ret) { - printf("Failed to program flash: %d\n", ret); - return ret; - } - return ret; -} - -U_BOOT_CMD(romupdate, 11, 0, do_update, - "Creates an FCB data structure and writes an U-Boot image to flash\n", - "[-f #] [-r [#]] [-e #] [
] []\n" - "\t-f #\twrite bootloader image at block #\n" - "\t-r\twrite redundant bootloader image at next free block after first image\n" - "\t-r #\twrite redundant bootloader image at block #\n" - "\t-e #\tspecify number of redundant blocks per boot loader image (default 2)\n" - "\t
\tRAM address of bootloader image (default: ${fileaddr}\n" - "\t\tlength of bootloader image in RAM (default: ${filesize}" - ); diff --git a/board/karo/tx6q/lowlevel_init.S b/board/karo/tx6q/lowlevel_init.S deleted file mode 100644 index 4785e9dc5b..0000000000 --- a/board/karo/tx6q/lowlevel_init.S +++ /dev/null @@ -1,609 +0,0 @@ -#include -#include -#include - -#define DEBUG_LED_BIT 20 -#define LED_GPIO_BASE GPIO2_BASE_ADDR -#define LED_MUX_OFFSET 0x0ec -#define LED_MUX_MODE 0x15 - -#define SDRAM_CLK CONFIG_SYS_SDRAM_CLK - -#ifdef PHYS_SDRAM_2_SIZE -#define SDRAM_SIZE (PHYS_SDRAM_1_SIZE + PHYS_SDRAM_2_SIZE) -#else -#define SDRAM_SIZE PHYS_SDRAM_1_SIZE -#endif - -#define CPU_2_BE_32(l) \ - ((((l) << 24) & 0xFF000000) | \ - (((l) << 8) & 0x00FF0000) | \ - (((l) >> 8) & 0x0000FF00) | \ - (((l) >> 24) & 0x000000FF)) - -#define CHECK_DCD_ADDR(a) ( \ - ((a) >= 0x020E0000 && (a) <= 0x020E3FFF) /* IOMUXC */ || \ - ((a) >= 0x020C4000 && (a) <= 0x020C7FFF) /* CCM */ || \ - ((a) >= 0x020C8000 && (a) <= 0x020C8FFF) /* ANALOG */ || \ - ((a) >= 0x021B0000 && (a) <= 0x021B7FFF) /* MMDC */ || \ - ((a) >= 0x00907000 && (a) <= 0x00937FF0) /* OCRAM */ || \ - ((a) >= 0x08000000 && (a) <= 0x0FFEFFFF) /* EIM (CS0) */ || \ - ((a) >= 0x10000000 && (a) <= 0xFFFFFFFF) /* SDRAM */) - - .macro mxc_dcd_item addr, val - .ifne CHECK_DCD_ADDR(\addr) - .word CPU_2_BE_32(\addr), CPU_2_BE_32(\val) - .else - .error "Address \addr not accessible from DCD" - .endif - .endm - -#define MXC_DCD_ITEM(addr, val) mxc_dcd_item addr, val - -#define MXC_DCD_CMD_SZ_BYTE 1 -#define MXC_DCD_CMD_SZ_SHORT 2 -#define MXC_DCD_CMD_SZ_WORD 4 -#define MXC_DCD_CMD_FLAG_WRITE 0x0 -#define MXC_DCD_CMD_FLAG_CLR 0x1 -#define MXC_DCD_CMD_FLAG_SET 0x3 -#define MXC_DCD_CMD_FLAG_CHK_ANY (1 << 0) -#define MXC_DCD_CMD_FLAG_CHK_SET (1 << 1) -#define MXC_DCD_CMD_FLAG_CHK_CLR (0 << 1) - -#define MXC_DCD_CMD_WRT(type, flags, next) \ - .word CPU_2_BE_32((0xcc << 24) | (((next) - .) << 8) | ((flags) << 3) | (type)) - -#define MXC_DCD_CMD_CHK(type, flags, addr, mask) \ - .word CPU_2_BE_32((0xcf << 24) | (12 << 8) | ((flags) << 3) | (type)),\ - CPU_2_BE_32(addr), CPU_2_BE_32(mask) - -#define MXC_DCD_CMD_CHK_CNT(type, flags, addr, mask, count) \ - .word CPU_2_BE_32((0xcf << 24) | (16 << 8) | ((flags) << 3) | (type)),\ - CPU_2_BE_32(addr), CPU_2_BE_32(mask), CPU_2_BE_32(count) - -#define MXC_DCD_CMD_NOP \ - .word CPU_2_BE_32((0xc0 << 24) | (4 << 8)) - -#define CK_TO_NS(ck) (((ck) * 1000 + SDRAM_CLK / 2) / SDRAM_CLK) -#define NS_TO_CK(ns) (((ns) * SDRAM_CLK + 999) / 1000) - - .macro CK_VAL, name, clks, offs, max - .iflt \clks - \offs - .set \name, 0 - .else - .ifle \clks - \offs - \max - .set \name, \clks - \offs - .else - .error "Value \clks out of range for parameter \name" - .endif - .endif - .endm - - .macro NS_VAL, name, ns, offs, max - .iflt \ns - \offs - .set \name, 0 - .else - CK_VAL \name, NS_TO_CK(\ns), \offs, \max - .endif - .endm - - .macro CK_MAX, name, ck1, ck2, offs, max - .ifgt \ck1 - \ck2 - CK_VAL \name, \ck1, \offs, \max - .else - CK_VAL \name, \ck2, \offs, \max - .endif - .endm - -#define MDMISC_DDR_TYPE_DDR3 0 -#define MDMISC_DDR_TYPE_LPDDR2 1 -#define MDMISC_DDR_TYPE_DDR2 2 - -#define DIV_ROUND_UP(m,d) (((m) + (d) - 1) / (d)) - -#define MDOR_CLK_PERIOD_ns 15258 /* base clock for MDOR values */ - -/* DDR3 SDRAM */ -#if SDRAM_SIZE > PHYS_SDRAM_1_SIZE -#define BANK_ADDR_BITS 2 -#else -#define BANK_ADDR_BITS 1 -#endif -#define SDRAM_BURST_LENGTH 8 -#define RALAT 5 -#define WALAT 0 -#define BI_ON 1 -#define ADDR_MIRROR 1 -#define DDR_TYPE MDMISC_DDR_TYPE_DDR3 - -/* 512/1024MiB SDRAM: NT5CB128M16P-CG */ -/* MDCFG0 0x0c */ -NS_VAL tRFC, 160, 1, 255 /* clks - 1 (0..255) */ -CK_MAX tXS, tRFC + 1 + NS_TO_CK(10), 5, 1, 255 /* clks - 1 (0..255) tRFC + 10 */ -CK_MAX tXP, 3, NS_TO_CK(6), 1, 7 /* clks - 1 (0..7) */ /* max(6ns, 3*CK) */ -CK_MAX tXPDLL, NS_TO_CK(24), 2, 1, 15 /* clks - 1 (0..15) */ -NS_VAL tFAW, 45, 1, 31 /* clks - 1 (0..31) */ -CK_VAL tCL, 8, 3, 8 /* clks - 3 (0..8) CAS Latency */ - -/* MDCFG1 0x10 */ -NS_VAL tRCD, 14, 1, 7 /* clks - 1 (0..7) */ -NS_VAL tRP, 14, 1, 7 /* clks - 1 (0..7) */ -NS_VAL tRC, 50, 1, 31 /* clks - 1 (0..31) */ -NS_VAL tRAS, 36, 1, 31 /* clks - 1 (0..31) */ -CK_VAL tRPA, 0, 0, 1 /* clks (0..1) */ -NS_VAL tWR, 15, 1, 15 /* clks - 1 (0..15) */ -CK_VAL tMRD, 4, 1, 15 /* clks - 1 (0..15) */ -CK_VAL tCWL, 6, 2, 6 /* clks - 2 (0..6) */ - -/* MDCFG2 0x14 */ -CK_VAL tDLLK, 512, 1, 511 /* clks - 1 (0..511) */ -CK_MAX tRTP, 4, NS_TO_CK(8), 1, 7 /* clks - 1 (0..7) */ -CK_MAX tWTR, 4, NS_TO_CK(8), 1, 7 /* clks - 1 (0..7) */ -CK_MAX tRRD, 4, NS_TO_CK(8), 1, 7 /* clks - 1 (0..7) */ - -/* MDOR 0x30 */ -CK_MAX tXPR, NS_TO_CK(CK_TO_NS(tRFC + 1) + 10), 5, 1, 255 /* clks - 1 (0..255) max(tRFC + 10, 5CK) */ -#define tSDE_RST (DIV_ROUND_UP(200000, MDOR_CLK_PERIOD_ns) + 2) -#define tRST_CKE (DIV_ROUND_UP(500000, MDOR_CLK_PERIOD_ns) + 2) - -/* MDOTC 0x08 */ -NS_VAL tAOFPD, 9, 1, 7 /* clks - 1 (0..7) */ -NS_VAL tAONPD, 9, 1, 7 /* clks - 1 (0..7) */ -CK_VAL tANPD, tCWL + 1, 1, 15 /* clks - 1 (0..15) */ -CK_VAL tAXPD, tCWL + 1, 1, 15 /* clks - 1 (0..15) */ -CK_VAL tODTLon tCWL, 1, 7 /* clks - 1 (0..7) */ -CK_VAL tODTLoff tCWL, 1, 31 /* clks - 1 (0..31) */ - -/* MDPDC 0x04 */ -CK_MAX tCKE, NS_TO_CK(6), 3, 1, 7 -CK_MAX tCKSRX, NS_TO_CK(10), 5, 0, 7 -CK_MAX tCKSRE, NS_TO_CK(10), 5, 0, 7 - -#define PRCT 0 -#define PWDT 5 -#define SLOW_PD 0 -#define BOTH_CS_PD 1 - -#define MDPDC_VAL_0 ( \ - (PRCT << 28) | \ - (PRCT << 24) | \ - (tCKE << 16) | \ - (SLOW_PD << 7) | \ - (BOTH_CS_PD << 6) | \ - (tCKSRX << 3) | \ - (tCKSRE << 0) \ - ) - -#define MDPDC_VAL_1 (MDPDC_VAL_0 | \ - (PWDT << 12) | \ - (PWDT << 8) \ - ) - -#define ROW_ADDR_BITS 14 -#define COL_ADDR_BITS 10 - - .iflt tWR - 7 - .set mr0_val, ((1 << 8) /* DLL Reset */ | \ - ((tWR + 1 - 4) << 9) | \ - (((tCL + 3) - 4) << 4)) - .else - .set mr0_val, ((1 << 8) /* DLL Reset */ | \ - (((tWR + 1) / 2) << 9) | \ - (((tCL + 3) - 4) << 4)) - .endif - -#define MDSCR_MRS_VAL(cs, mr, val) (((val) << 16) | \ - (1 << 15) /* CON REQ */ | \ - (3 << 4) /* MRS command */ | \ - ((cs) << 3) | \ - ((mr) << 0)) - -#define mr1_val 0x0040 -#define mr2_val 0x0408 - -#define MDCFG0_VAL ( \ - (tRFC << 24) | \ - (tXS << 16) | \ - (tXP << 13) | \ - (tXPDLL << 9) | \ - (tFAW << 4) | \ - (tCL << 0)) \ - -#define MDCFG1_VAL ( \ - (tRCD << 29) | \ - (tRP << 26) | \ - (tRC << 21) | \ - (tRAS << 16) | \ - (tRPA << 15) | \ - (tWR << 9) | \ - (tMRD << 5) | \ - (tCWL << 0)) \ - -#define MDCFG2_VAL ( \ - (tDLLK << 16) | \ - (tRTP << 6) | \ - (tWTR << 3) | \ - (tRRD << 0)) - -#define BURST_LEN (SDRAM_BURST_LENGTH / 8) /* 0: 4 byte 1: 8 byte */ -#define MDCTL_VAL (((ROW_ADDR_BITS - 11) << 24) | \ - ((COL_ADDR_BITS - 9) << 20) | \ - (BURST_LEN << 19) | \ - (2 << 16) | /* SDRAM bus width */ \ - ((-1) << (32 - BANK_ADDR_BITS))) - -#define MDMISC_VAL ((ADDR_MIRROR << 19) | \ - (WALAT << 16) | \ - (BI_ON << 12) | \ - (0x3 << 9) | \ - (RALAT << 6) | \ - (DDR_TYPE << 3)) - -#define MDOR_VAL ((tXPR << 16) | (tSDE_RST << 8) | (tRST_CKE << 0)) - -#define MDOTC_VAL ((tAOFPD << 27) | \ - (tAONPD << 24) | \ - (tANPD << 20) | \ - (tAXPD << 16) | \ - (tODTLon << 12) | \ - (tODTLoff << 4)) - -fcb_start: - b _start - .org 0x400 -ivt_header: - .word CPU_2_BE_32((0xd1 << 24) | (32 << 8) | 0x40) -app_start_addr: - .long _start - .long 0x0 -dcd_ptr: - .long dcd_hdr -boot_data_ptr: - .word boot_data -self_ptr: - .word ivt_header -app_code_csf: - .word 0x0 - .word 0x0 -boot_data: - .long fcb_start -image_len: - .long CONFIG_U_BOOT_IMG_SIZE -plugin: - .word 0 -ivt_end: -#define DCD_VERSION 0x40 - -#define CLKCTL_CCGR0 0x68 -#define CLKCTL_CCGR1 0x6c -#define CLKCTL_CCGR2 0x70 -#define CLKCTL_CCGR3 0x74 -#define CLKCTL_CCGR4 0x78 -#define CLKCTL_CCGR5 0x7c -#define CLKCTL_CCGR6 0x80 -#define CLKCTL_CCGR7 0x84 -#define CLKCTL_CMEOR 0x88 - -#define DDR_SEL_VAL 3 -#define DSE_VAL 6 -#define ODT_VAL 2 - -#define DDR_SEL_SHIFT 18 -#define DDR_MODE_SHIFT 17 -#define ODT_SHIFT 8 -#define DSE_SHIFT 3 -#define HYS_SHIFT 16 -#define PKE_SHIFT 12 -#define PUE_SHIFT 13 -#define PUS_SHIFT 14 - -#define DDR_SEL_MASK (DDR_SEL_VAL << DDR_SEL_SHIFT) -#define DDR_MODE_MASK (1 << DDR_MODE_SHIFT) -#define DSE_MASK (DSE_VAL << DSE_SHIFT) -#define ODT_MASK (ODT_VAL << ODT_SHIFT) - -#define DQM_MASK (DDR_MODE_MASK | DSE_MASK) -#define SDQS_MASK DSE_MASK -#define SDODT_MASK (DSE_MASK | (1 << PKE_SHIFT) | (1 << PUE_SHIFT) | (0 << PUS_SHIFT)) -#define SDCLK_MASK (DDR_MODE_MASK | DSE_MASK) -#define SDCKE_MASK ((1 << PKE_SHIFT) | (1 << PUE_SHIFT) | (0 << PUS_SHIFT)) -#define DDR_ADDR_MASK 0 -#define DDR_CTRL_MASK (DDR_MODE_MASK | DSE_MASK) - -dcd_hdr: - .word CPU_2_BE_32((0xd2 << 24) | ((dcd_end - .) << 8) | DCD_VERSION) -dcd_start: - MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, ddr_reset) - /* RESET_OUT GPIO_7_12 */ - MXC_DCD_ITEM(0x020e024c, 0x00000005) - - MXC_DCD_ITEM(0x020c402c, 0x006336c1) /* CS2CDR default: 0x007236c1 */ - - MXC_DCD_ITEM(0x020c80e0, 0x00002001) /* ENET PLL */ - - /* enable all relevant clocks... */ - MXC_DCD_ITEM(0x020c4068, 0xf0c03f3f) /* default: 0xf0c03f0f APBH-DMA */ - MXC_DCD_ITEM(0x020c406c, 0xf0fc0c00) /* default: 0xf0fc0000 */ - MXC_DCD_ITEM(0x020c4070, 0xfc3ff0cc) /* default: 0xfc3ff00c I2C1 */ - MXC_DCD_ITEM(0x020c4074, 0x3ff00000) /* default: 0x3ff00000 */ - MXC_DCD_ITEM(0x020c4078, 0xff00ff00) /* default: 0x0000ff00 GPMI BCH */ - MXC_DCD_ITEM(0x020c407c, 0xff033f0f) /* default: 0xf0033f0f UART1 */ - MXC_DCD_ITEM(0x020c4080, 0xffff03ff) /* default: 0xffff0003 USDHC4 (for APBH-DMA!) USDHC3 (for BCH!) */ - - /* IOMUX: */ - MXC_DCD_ITEM(0x020e0004, 0x48640005) /* default: 0x48400005 ENET_CLK output */ - /* UART1 pad config */ - MXC_DCD_ITEM(0x020e02a8, 0x00000001) /* UART1 TXD */ - MXC_DCD_ITEM(0x020e02ac, 0x00000001) /* UART1 RXD */ - MXC_DCD_ITEM(0x020e0920, 0x00000003) /* UART1 RXD INPUT_SEL */ - MXC_DCD_ITEM(0x020e02c0, 0x00000001) /* UART1 CTS */ - MXC_DCD_ITEM(0x020e02c4, 0x00000001) /* UART1 RTS */ - MXC_DCD_ITEM(0x020e091c, 0x00000003) /* UART1 RTS INPUT_SEL */ - - /* NAND */ - MXC_DCD_ITEM(0x020e02d4, 0x00000000) /* NANDF_CLE: NANDF_CLE */ - MXC_DCD_ITEM(0x020e02d8, 0x00000000) /* NANDF_ALE: NANDF_ALE */ - MXC_DCD_ITEM(0x020e02dc, 0x00000000) /* NANDF_WP_B: NANDF_WPn */ - MXC_DCD_ITEM(0x020e02e0, 0x00000000) /* NANDF_RB0: NANDF_READY0 */ - MXC_DCD_ITEM(0x020e02e4, 0x00000000) /* NANDF_CS0: NANDF_CS0 */ - MXC_DCD_ITEM(0x020e02f4, 0x00000001) /* SD4_CMD: NANDF_RDn */ - MXC_DCD_ITEM(0x020e02f8, 0x00000001) /* SD4_CLK: NANDF_WRn */ - MXC_DCD_ITEM(0x020e02fc, 0x00000000) /* NANDF_D0: NANDF_D0 */ - MXC_DCD_ITEM(0x020e0300, 0x00000000) /* NANDF_D1: NANDF_D1 */ - MXC_DCD_ITEM(0x020e0304, 0x00000000) /* NANDF_D2: NANDF_D2 */ - MXC_DCD_ITEM(0x020e0308, 0x00000000) /* NANDF_D3: NANDF_D3 */ - MXC_DCD_ITEM(0x020e030c, 0x00000000) /* NANDF_D4: NANDF_D4 */ - MXC_DCD_ITEM(0x020e0310, 0x00000000) /* NANDF_D5: NANDF_D5 */ - MXC_DCD_ITEM(0x020e0314, 0x00000000) /* NANDF_D6: NANDF_D6 */ - MXC_DCD_ITEM(0x020e0318, 0x00000000) /* NANDF_D7: NANDF_D7 */ - - /* ext. mem CS */ - MXC_DCD_ITEM(0x020e02ec, 0x00000000) /* NANDF_CS2: NANDF_CS2 */ - /* DRAM_DQM[0..7] */ - MXC_DCD_ITEM(0x020e05ac, DQM_MASK) - MXC_DCD_ITEM(0x020e05b4, DQM_MASK) - MXC_DCD_ITEM(0x020e0528, DQM_MASK) - MXC_DCD_ITEM(0x020e0520, DQM_MASK) - MXC_DCD_ITEM(0x020e0514, DQM_MASK) - MXC_DCD_ITEM(0x020e0510, DQM_MASK) - MXC_DCD_ITEM(0x020e05bc, DQM_MASK) - MXC_DCD_ITEM(0x020e05c4, DQM_MASK) - /* DRAM_A[0..15] */ - MXC_DCD_ITEM(0x020e052c, DDR_ADDR_MASK) - MXC_DCD_ITEM(0x020e0530, DDR_ADDR_MASK) - MXC_DCD_ITEM(0x020e0534, DDR_ADDR_MASK) - MXC_DCD_ITEM(0x020e0538, DDR_ADDR_MASK) - MXC_DCD_ITEM(0x020e053c, DDR_ADDR_MASK) - MXC_DCD_ITEM(0x020e0540, DDR_ADDR_MASK) - MXC_DCD_ITEM(0x020e0544, DDR_ADDR_MASK) - MXC_DCD_ITEM(0x020e0548, DDR_ADDR_MASK) - MXC_DCD_ITEM(0x020e054c, DDR_ADDR_MASK) - MXC_DCD_ITEM(0x020e0550, DDR_ADDR_MASK) - MXC_DCD_ITEM(0x020e0554, DDR_ADDR_MASK) - MXC_DCD_ITEM(0x020e0558, DDR_ADDR_MASK) - MXC_DCD_ITEM(0x020e055c, DDR_ADDR_MASK) - MXC_DCD_ITEM(0x020e0560, DDR_ADDR_MASK) - MXC_DCD_ITEM(0x020e0564, DDR_ADDR_MASK) - MXC_DCD_ITEM(0x020e0568, DDR_ADDR_MASK) - /* DRAM_CAS */ - MXC_DCD_ITEM(0x020e056c, DDR_CTRL_MASK) - /* DRAM_RAS */ - MXC_DCD_ITEM(0x020e0578, DDR_CTRL_MASK) - /* DRAM_SDCLK[0..1] */ - MXC_DCD_ITEM(0x020e0588, SDCLK_MASK) - MXC_DCD_ITEM(0x020e0594, SDCLK_MASK) - /* DRAM_RESET */ - MXC_DCD_ITEM(0x020e057c, DDR_CTRL_MASK) - /* DRAM_SDCKE[0..1] */ - MXC_DCD_ITEM(0x020e0590, SDCKE_MASK) - MXC_DCD_ITEM(0x020e0598, SDCKE_MASK) - /* DRAM_SDBA[0..2] */ - MXC_DCD_ITEM(0x020e0580, 0x00000000) - MXC_DCD_ITEM(0x020e0584, 0x00000000) - MXC_DCD_ITEM(0x020e058c, 0x00000000) - /* DRAM_SDODT[0..1] */ - MXC_DCD_ITEM(0x020e059c, SDODT_MASK) - MXC_DCD_ITEM(0x020e05a0, SDODT_MASK) - /* DRAM_B[0..7]DS */ - MXC_DCD_ITEM(0x020e0784, DSE_MASK) - MXC_DCD_ITEM(0x020e0788, DSE_MASK) - MXC_DCD_ITEM(0x020e0794, DSE_MASK) - MXC_DCD_ITEM(0x020e079c, DSE_MASK) - MXC_DCD_ITEM(0x020e07a0, DSE_MASK) - MXC_DCD_ITEM(0x020e07a4, DSE_MASK) - MXC_DCD_ITEM(0x020e07a8, DSE_MASK) - MXC_DCD_ITEM(0x020e0748, DSE_MASK) - /* ADDDS */ - MXC_DCD_ITEM(0x020e074c, DSE_MASK) - /* DDRMODE_CTL */ - MXC_DCD_ITEM(0x020e0750, DDR_MODE_MASK) - /* DDRPKE */ - MXC_DCD_ITEM(0x020e0758, 0x00000000) - /* DDRMODE */ - MXC_DCD_ITEM(0x020e0774, DDR_MODE_MASK) - /* CTLDS */ - MXC_DCD_ITEM(0x020e078c, DSE_MASK) - /* DDR_TYPE */ - MXC_DCD_ITEM(0x020e0798, DDR_SEL_MASK) - /* DDRPK */ - MXC_DCD_ITEM(0x020e0768, 1 << PUE_SHIFT) - /* DDRHYS */ - MXC_DCD_ITEM(0x020e0770, 0x00000000) - /* TERM_CTL[0..7] */ - MXC_DCD_ITEM(0x020e0754, ODT_MASK) - MXC_DCD_ITEM(0x020e075c, ODT_MASK) - MXC_DCD_ITEM(0x020e0760, ODT_MASK) - MXC_DCD_ITEM(0x020e0764, ODT_MASK) - MXC_DCD_ITEM(0x020e076c, ODT_MASK) - MXC_DCD_ITEM(0x020e0778, ODT_MASK) - MXC_DCD_ITEM(0x020e077c, ODT_MASK) - MXC_DCD_ITEM(0x020e0780, ODT_MASK) - - /* SDRAM initialization */ - /* MPRDDQBY[0..7]DL */ - MXC_DCD_ITEM(0x021b081c, 0x33333333) - MXC_DCD_ITEM(0x021b481c, 0x33333333) - MXC_DCD_ITEM(0x021b0820, 0x33333333) - MXC_DCD_ITEM(0x021b4820, 0x33333333) - MXC_DCD_ITEM(0x021b0824, 0x33333333) - MXC_DCD_ITEM(0x021b4824, 0x33333333) - MXC_DCD_ITEM(0x021b0828, 0x33333333) - MXC_DCD_ITEM(0x021b4828, 0x33333333) - /* MDMISC */ - MXC_DCD_ITEM(0x021b0018, MDMISC_VAL | 2) /* reset MMDC FSM */ -ddr_reset: - MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b0018, 0x00000002) - MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, con_ack) - - /* MSDSCR Conf Req */ - MXC_DCD_ITEM(0x021b001c, 0x00008000) -con_ack: - MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_SET, 0x021b001c, 0x00004000) - MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, ddr_calib) - /* MDCTL */ - MXC_DCD_ITEM(0x021b0000, MDCTL_VAL) -ddr_calib: - MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_SET, 0x021b0018, 0x40000000) - MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, zq_calib) - - MXC_DCD_ITEM(0x021b000c, MDCFG0_VAL) - MXC_DCD_ITEM(0x021b0010, MDCFG1_VAL) - MXC_DCD_ITEM(0x021b0014, MDCFG2_VAL) - MXC_DCD_ITEM(0x021b002c, 0x000026d2) /* MDRWD */ - MXC_DCD_ITEM(0x021b0030, MDOR_VAL) - MXC_DCD_ITEM(0x021b0008, MDOTC_VAL) - MXC_DCD_ITEM(0x021b0004, MDPDC_VAL_0) - MXC_DCD_ITEM(0x021b0040, 0x00000027) /* MDASP */ - - /* CS0 MRS: */ - MXC_DCD_ITEM(0x021b001c, MDSCR_MRS_VAL(0, 0, mr0_val)) - MXC_DCD_ITEM(0x021b001c, MDSCR_MRS_VAL(0, 1, mr1_val)) - MXC_DCD_ITEM(0x021b001c, MDSCR_MRS_VAL(0, 2, mr2_val)) - MXC_DCD_ITEM(0x021b001c, MDSCR_MRS_VAL(0, 3, 0)) -#if BANK_ADDR_BITS > 1 - /* CS1 MRS: MR2 */ - MXC_DCD_ITEM(0x021b001c, MDSCR_MRS_VAL(1, 0, mr0_val)) - MXC_DCD_ITEM(0x021b001c, MDSCR_MRS_VAL(1, 1, mr1_val)) - MXC_DCD_ITEM(0x021b001c, MDSCR_MRS_VAL(1, 2, mr2_val)) - MXC_DCD_ITEM(0x021b001c, MDSCR_MRS_VAL(1, 3, 4)) /* MRS: select MPR */ -#endif - MXC_DCD_ITEM(0x021b0020, 0x0000c000) /* disable refresh */ - - MXC_DCD_ITEM(0x021b0818, 0x00011112) /* MPODTCTRL */ - MXC_DCD_ITEM(0x021b4818, 0x00011112) - - /* DDR3 calibration */ - MXC_DCD_ITEM(0x021b0890, 0x00000003) /* select default compare pattern for DQ calibration */ - MXC_DCD_ITEM(0x021b0404, 0x00011007) - - /* ZQ calibration */ - MXC_DCD_ITEM(0x021b001c, 0x04008010) /* precharge all */ - MXC_DCD_ITEM(0x021b001c, 0x04008040) /* MRS: ZQ calibration */ - - MXC_DCD_ITEM(0x021b4800, 0xa138002b) - MXC_DCD_ITEM(0x021b0800, 0xa139002b) -zq_calib: - MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b0800, 0x00010000) - MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, wl_calib) - - /* Write leveling */ - MXC_DCD_ITEM(0x021b4800, 0xa1380000) - MXC_DCD_ITEM(0x021b0800, 0xa1380000) - - MXC_DCD_ITEM(0x021b001c, MDSCR_MRS_VAL(0, 3, 4)) /* MRS: select MPR */ - MXC_DCD_ITEM(0x021b001c, 0x00808231) /* MRS: start write leveling */ - - MXC_DCD_ITEM(0x021b0808, 0x00000001) /* initiate Write leveling */ -wl_calib: - MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b0808, 0x00000001) - MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b0808, 0x00000f00) - MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b4808, 0x00000001) - MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b4808, 0x00000f00) - MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, dqs_fifo_reset) - - MXC_DCD_ITEM(0x021b0800, 0xa138002b) - MXC_DCD_ITEM(0x021b4800, 0xa138002b) - - MXC_DCD_ITEM(0x021b001c, MDSCR_MRS_VAL(0, 1, mr1_val)) /* MRS: end write leveling */ - - /* DQS gating calibration */ - MXC_DCD_ITEM(0x020e05a8, SDQS_MASK | 0x7000) /* enable Pullups on DQS pads */ - MXC_DCD_ITEM(0x020e05b0, SDQS_MASK | 0x7000) - MXC_DCD_ITEM(0x020e0524, SDQS_MASK | 0x7000) - MXC_DCD_ITEM(0x020e051c, SDQS_MASK | 0x7000) - MXC_DCD_ITEM(0x020e0518, SDQS_MASK | 0x7000) - MXC_DCD_ITEM(0x020e050c, SDQS_MASK | 0x7000) - MXC_DCD_ITEM(0x020e05b8, SDQS_MASK | 0x7000) - MXC_DCD_ITEM(0x020e05c0, SDQS_MASK | 0x7000) - MXC_DCD_ITEM(0x021b0018, MDMISC_VAL | (7 << 6) | (3 << 16)) /* RALAT/WALAT max. */ - - MXC_DCD_ITEM(0x021b001c, 0x00008020) /* issue one refresh cycle */ - MXC_DCD_ITEM(0x021b001c, 0x04008050) /* precharge all to bank 0 */ - - MXC_DCD_ITEM(0x021b0848, 0x40404040) /* DQ RD Delay default values */ - MXC_DCD_ITEM(0x021b4848, 0x40404040) - MXC_DCD_ITEM(0x021b0850, 0x40404040) /* DQ WR Delay default values */ - MXC_DCD_ITEM(0x021b4850, 0x40404040) - MXC_DCD_ITEM(0x021b48b8, 0x00000800) - MXC_DCD_ITEM(0x021b08b8, 0x00000800) - - MXC_DCD_ITEM(0x021b083c, 0x80000000) /* issue fifo reset */ -dqs_fifo_reset: - MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b083c, 0x80000000) - MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, dqs_fifo_reset2) - MXC_DCD_ITEM(0x021b083c, 0x80000000) /* issue 2nd fifo reset */ -dqs_fifo_reset2: - MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b083c, 0x80000000) - MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, dqs_calib) - MXC_DCD_ITEM(0x021b083c, 0x50800000) /* choose 32 wait cycles and start DQS calib. */ -dqs_calib: - MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b083c, 0x10000000) - MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b083c, 0x00001000) - MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b483c, 0x10000000) - MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b483c, 0x00001000) - MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, rd_dl_calib) - - /* DRAM_SDQS[0..7] pad config */ - MXC_DCD_ITEM(0x020e05a8, SDQS_MASK) - MXC_DCD_ITEM(0x020e05b0, SDQS_MASK) - MXC_DCD_ITEM(0x020e0524, SDQS_MASK) - MXC_DCD_ITEM(0x020e051c, SDQS_MASK) - MXC_DCD_ITEM(0x020e0518, SDQS_MASK) - MXC_DCD_ITEM(0x020e050c, SDQS_MASK) - MXC_DCD_ITEM(0x020e05b8, SDQS_MASK) - MXC_DCD_ITEM(0x020e05c0, SDQS_MASK) - - MXC_DCD_ITEM(0x021b0018, MDMISC_VAL) - - /* Read delay calibration */ - MXC_DCD_ITEM(0x021b001c, 0x04008050) /* precharge all to bank 0 */ - MXC_DCD_ITEM(0x021b0860, 0x00000030) /* MPRDDLHWCTL: HW_RD_DL_EN */ -rd_dl_calib: - MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b0860, 0x00000010) - MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b4860, 0x00000010) - MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b0860, 0x0000000f) - MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b4860, 0x0000000f) - MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, wr_dl_calib) - - MXC_DCD_ITEM(0x021b001c, 0x04008050) /* precharge all to bank 0 */ - MXC_DCD_ITEM(0x021b0864, 0x00000030) /* start WR DL calibration */ -wr_dl_calib: - MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b0864, 0x00000010) - MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b4864, 0x00000010) - MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b0864, 0x0000000f) - MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b4864, 0x0000000f) - MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, con_ack_clr) - - MXC_DCD_ITEM(0x021b001c, MDSCR_MRS_VAL(0, 3, 0)) /* MRS: select normal data path */ - MXC_DCD_ITEM(0x021b0020, 0x00005800) /* MDREF */ - MXC_DCD_ITEM(0x021b0404, 0x00011006) /* MAPSR */ - MXC_DCD_ITEM(0x021b0004, MDPDC_VAL_1) - - /* MDSCR: Normal operation */ - MXC_DCD_ITEM(0x021b001c, 0x00000000) -con_ack_clr: - MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b001c, 0x00004000) -dcd_end: - .ifgt dcd_end - dcd_start - 1768 - .error "DCD too large!" - .endif diff --git a/board/karo/tx6q/tx6q.c b/board/karo/tx6q/tx6q.c deleted file mode 100644 index 6a95857679..0000000000 --- a/board/karo/tx6q/tx6q.c +++ /dev/null @@ -1,1059 +0,0 @@ -/* - * Copyright (C) 2012 Lothar Waßmann - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -//#define DEBUG -//#define TIMER_TEST - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "../common/karo.h" - -#define TX6Q_FEC_RST_GPIO IMX_GPIO_NR(7, 6) -#define TX6Q_FEC_PWR_GPIO IMX_GPIO_NR(3, 20) -#define TX6Q_FEC_INT_GPIO IMX_GPIO_NR(2, 4) -#define TX6Q_LED_GPIO IMX_GPIO_NR(2, 20) - -#define TX6Q_LCD_PWR_GPIO IMX_GPIO_NR(2, 31) -#define TX6Q_LCD_RST_GPIO IMX_GPIO_NR(3, 29) -#define TX6Q_LCD_BACKLIGHT_GPIO IMX_GPIO_NR(1, 1) - -#define TX6Q_RESET_OUT_GPIO IMX_GPIO_NR(7, 12) - -#define TEMPERATURE_MIN -40 -#define TEMPERATURE_HOT 80 -#define TEMPERATURE_MAX 125 - -DECLARE_GLOBAL_DATA_PTR; - -#define MUX_CFG_SION IOMUX_PAD(0, 0, IOMUX_CONFIG_SION, 0, 0, 0) - -static const iomux_v3_cfg_t tx6q_pads[] = { - /* NAND flash pads */ - MX6Q_PAD_NANDF_CLE__RAWNAND_CLE, - MX6Q_PAD_NANDF_ALE__RAWNAND_ALE, - MX6Q_PAD_NANDF_WP_B__RAWNAND_RESETN, - MX6Q_PAD_NANDF_RB0__RAWNAND_READY0, - MX6Q_PAD_NANDF_CS0__RAWNAND_CE0N, - MX6Q_PAD_SD4_CMD__RAWNAND_RDN, - MX6Q_PAD_SD4_CLK__RAWNAND_WRN, - MX6Q_PAD_NANDF_D0__RAWNAND_D0, - MX6Q_PAD_NANDF_D1__RAWNAND_D1, - MX6Q_PAD_NANDF_D2__RAWNAND_D2, - MX6Q_PAD_NANDF_D3__RAWNAND_D3, - MX6Q_PAD_NANDF_D4__RAWNAND_D4, - MX6Q_PAD_NANDF_D5__RAWNAND_D5, - MX6Q_PAD_NANDF_D6__RAWNAND_D6, - MX6Q_PAD_NANDF_D7__RAWNAND_D7, - - /* RESET_OUT */ - MX6Q_PAD_GPIO_17__GPIO_7_12, - - /* UART pads */ -#if CONFIG_MXC_UART_BASE == UART1_BASE - MX6Q_PAD_SD3_DAT7__UART1_TXD, - MX6Q_PAD_SD3_DAT6__UART1_RXD, - MX6Q_PAD_SD3_DAT1__UART1_RTS, - MX6Q_PAD_SD3_DAT0__UART1_CTS, -#endif -#if CONFIG_MXC_UART_BASE == UART2_BASE - MX6Q_PAD_SD4_DAT4__UART2_RXD, - MX6Q_PAD_SD4_DAT7__UART2_TXD, - MX6Q_PAD_SD4_DAT5__UART2_RTS, - MX6Q_PAD_SD4_DAT6__UART2_CTS, -#endif -#if CONFIG_MXC_UART_BASE == UART3_BASE - MX6Q_PAD_EIM_D24__UART3_TXD, - MX6Q_PAD_EIM_D25__UART3_RXD, - MX6Q_PAD_SD3_RST__UART3_RTS, - MX6Q_PAD_SD3_DAT3__UART3_CTS, -#endif - /* internal I2C */ - MX6Q_PAD_EIM_D28__I2C1_SDA, - MX6Q_PAD_EIM_D21__I2C1_SCL, - - /* FEC PHY GPIO functions */ - MX6Q_PAD_EIM_D20__GPIO_3_20 | MUX_CFG_SION, /* PHY POWER */ - MX6Q_PAD_SD3_DAT2__GPIO_7_6 | MUX_CFG_SION, /* PHY RESET */ - MX6Q_PAD_SD3_DAT4__GPIO_7_1, /* PHY INT */ -}; - -static const iomux_v3_cfg_t tx6q_fec_pads[] = { - /* FEC functions */ - MX6Q_PAD_ENET_MDC__ENET_MDC, - MX6Q_PAD_ENET_MDIO__ENET_MDIO, - MX6Q_PAD_GPIO_16__ENET_ANATOP_ETHERNET_REF_OUT, - MX6Q_PAD_ENET_RX_ER__ENET_RX_ER, - MX6Q_PAD_ENET_CRS_DV__ENET_RX_EN, - MX6Q_PAD_ENET_RXD1__ENET_RDATA_1, - MX6Q_PAD_ENET_RXD0__ENET_RDATA_0, - MX6Q_PAD_ENET_TX_EN__ENET_TX_EN, - MX6Q_PAD_ENET_TXD1__ENET_TDATA_1, - MX6Q_PAD_ENET_TXD0__ENET_TDATA_0, -}; - -static const struct gpio tx6q_gpios[] = { - { TX6Q_RESET_OUT_GPIO, GPIOF_OUTPUT_INIT_HIGH, "#RESET_OUT", }, - { TX6Q_FEC_PWR_GPIO, GPIOF_OUTPUT_INIT_HIGH, "FEC PHY PWR", }, - { TX6Q_FEC_RST_GPIO, GPIOF_OUTPUT_INIT_LOW, "FEC PHY RESET", }, - { TX6Q_FEC_INT_GPIO, GPIOF_INPUT, "FEC PHY INT", }, -}; - -/* - * Functions - */ -/* placed in section '.data' to prevent overwriting relocation info - * overlayed with bss - */ -static u32 wrsr __attribute__((section(".data"))); - -#define WRSR_POR (1 << 4) -#define WRSR_TOUT (1 << 1) -#define WRSR_SFTW (1 << 0) - -static void print_reset_cause(void) -{ - struct src *src_regs = (struct src *)SRC_BASE_ADDR; - void __iomem *wdt_base = (void __iomem *)WDOG1_BASE_ADDR; - u32 srsr; - char *dlm = ""; - - printf("Reset cause: "); - - srsr = readl(&src_regs->srsr); - wrsr = readw(wdt_base + 4); - - if (wrsr & WRSR_POR) { - printf("%sPOR", dlm); - dlm = " | "; - } - if (srsr & 0x00004) { - printf("%sCSU", dlm); - dlm = " | "; - } - if (srsr & 0x00008) { - printf("%sIPP USER", dlm); - dlm = " | "; - } - if (srsr & 0x00010) { - if (wrsr & WRSR_SFTW) { - printf("%sSOFT", dlm); - dlm = " | "; - } - if (wrsr & WRSR_TOUT) { - printf("%sWDOG", dlm); - dlm = " | "; - } - } - if (srsr & 0x00020) { - printf("%sJTAG HIGH-Z", dlm); - dlm = " | "; - } - if (srsr & 0x00040) { - printf("%sJTAG SW", dlm); - dlm = " | "; - } - if (srsr & 0x10000) { - printf("%sWARM BOOT", dlm); - dlm = " | "; - } - if (dlm[0] == '\0') - printf("unknown"); - - printf("\n"); -} - -int read_cpu_temperature(void); -int check_cpu_temperature(int boot); - -static void print_cpuinfo(void) -{ - u32 cpurev = get_cpu_rev(); - char *cpu_str = "?"; - - switch ((cpurev >> 12) & 0xff) { - case MXC_CPU_MX6SL: - cpu_str = "SL"; - break; - case MXC_CPU_MX6DL: - cpu_str = "DL"; - break; - case MXC_CPU_MX6SOLO: - cpu_str = "SOLO"; - break; - case MXC_CPU_MX6Q: - cpu_str = "Q"; - break; - } - - printf("CPU: Freescale i.MX6%s rev%d.%d at %d MHz\n", - cpu_str, - (cpurev & 0x000F0) >> 4, - (cpurev & 0x0000F) >> 0, - mxc_get_clock(MXC_ARM_CLK) / 1000000); - - print_reset_cause(); - check_cpu_temperature(1); -} - -#define LTC3676_DVB2A 0x0C -#define LTC3676_DVB2B 0x0D -#define LTC3676_DVB4A 0x10 -#define LTC3676_DVB4B 0x11 - -#define VDD_SOC_mV (1375 + 50) -#define VDD_CORE_mV (1375 + 50) - -#define mV_to_regval(mV) (((mV) * 360 / 330 - 825 + 1) / 25) -#define regval_to_mV(v) (((v) * 25 + 825) * 330 / 360) - -static int setup_pmic_voltages(void) -{ - int ret; - unsigned char value; - - i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); - - ret = i2c_probe(CONFIG_SYS_I2C_SLAVE); - if (ret != 0) { - printf("Failed to initialize I2C\n"); - return ret; - } - - ret = i2c_read(CONFIG_SYS_I2C_SLAVE, 0x11, 1, &value, 1); - if (ret) { - printf("%s: i2c_read error: %d\n", __func__, ret); - return ret; - } - - /* VDDCORE/VDDSOC default 1.375V is not enough, considering - pfuze tolerance and IR drop and ripple, need increase - to 1.425V for SabreSD */ - - value = 0x39; /* VB default value & PGOOD not forced when slewing */ - ret = i2c_write(CONFIG_SYS_I2C_SLAVE, LTC3676_DVB2B, 1, &value, 1); - if (ret) { - printf("%s: failed to write PMIC DVB2B register: %d\n", - __func__, ret); - return ret; - } - ret = i2c_write(CONFIG_SYS_I2C_SLAVE, LTC3676_DVB4B, 1, &value, 1); - if (ret) { - printf("%s: failed to write PMIC DVB4B register: %d\n", - __func__, ret); - return ret; - } - - value = mV_to_regval(VDD_SOC_mV); - ret = i2c_write(CONFIG_SYS_I2C_SLAVE, LTC3676_DVB2A, 1, &value, 1); - if (ret) { - printf("%s: failed to write PMIC DVB2A register: %d\n", - __func__, ret); - return ret; - } - printf("VDDSOC set to %dmV\n", regval_to_mV(value)); - - value = mV_to_regval(VDD_CORE_mV); - ret = i2c_write(CONFIG_SYS_I2C_SLAVE, LTC3676_DVB4A, 1, &value, 1); - if (ret) { - printf("%s: failed to write PMIC DVB4A register: %d\n", - __func__, ret); - return ret; - } - printf("VDDCORE set to %dmV\n", regval_to_mV(value)); - return 0; -} - -int board_early_init_f(void) -{ - gpio_request_array(tx6q_gpios, ARRAY_SIZE(tx6q_gpios)); - imx_iomux_v3_setup_multiple_pads(tx6q_pads, ARRAY_SIZE(tx6q_pads)); - - return 0; -} - -int board_init(void) -{ - int ret; - - /* Address of boot parameters */ - gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x1000; -#if 1 - gd->bd->bi_arch_number = 4429; -#endif - ret = setup_pmic_voltages(); - if (ret) { - printf("Failed to setup PMIC voltages\n"); - hang(); - } - return 0; -} - -int dram_init(void) -{ - /* dram_init must store complete ramsize in gd->ram_size */ - gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, - PHYS_SDRAM_1_SIZE); - return 0; -} - -void dram_init_banksize(void) -{ - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = get_ram_size((void *)PHYS_SDRAM_1, - PHYS_SDRAM_1_SIZE); -#if CONFIG_NR_DRAM_BANKS > 1 - gd->bd->bi_dram[1].start = PHYS_SDRAM_2; - gd->bd->bi_dram[1].size = get_ram_size((void *)PHYS_SDRAM_2, - PHYS_SDRAM_2_SIZE); -#endif -} - -#ifdef CONFIG_CMD_MMC -static const iomux_v3_cfg_t mmc0_pads[] = { - MX6Q_PAD_SD1_CMD__USDHC1_CMD, - MX6Q_PAD_SD1_CLK__USDHC1_CLK, - MX6Q_PAD_SD1_DAT0__USDHC1_DAT0, - MX6Q_PAD_SD1_DAT1__USDHC1_DAT1, - MX6Q_PAD_SD1_DAT2__USDHC1_DAT2, - MX6Q_PAD_SD1_DAT3__USDHC1_DAT3, - /* SD1 CD */ - MX6Q_PAD_SD3_CMD__GPIO_7_2, -}; - -static const iomux_v3_cfg_t mmc1_pads[] = { - MX6Q_PAD_SD2_CMD__USDHC2_CMD, - MX6Q_PAD_SD2_CLK__USDHC2_CLK, - MX6Q_PAD_SD2_DAT0__USDHC2_DAT0, - MX6Q_PAD_SD2_DAT1__USDHC2_DAT1, - MX6Q_PAD_SD2_DAT2__USDHC2_DAT2, - MX6Q_PAD_SD2_DAT3__USDHC2_DAT3, - /* SD2 CD */ - MX6Q_PAD_SD3_CLK__GPIO_7_3, -}; - -static struct tx6q_esdhc_cfg { - const iomux_v3_cfg_t *pads; - int num_pads; - enum mxc_clock clkid; - struct fsl_esdhc_cfg cfg; -} tx6q_esdhc_cfg[] = { - { - .pads = mmc0_pads, - .num_pads = ARRAY_SIZE(mmc0_pads), - .clkid = MXC_ESDHC_CLK, - .cfg = { - .esdhc_base = (void __iomem *)USDHC1_BASE_ADDR, - .cd_gpio = IMX_GPIO_NR(7, 2), - .wp_gpio = -EINVAL, - }, - }, - { - .pads = mmc1_pads, - .num_pads = ARRAY_SIZE(mmc1_pads), - .clkid = MXC_ESDHC2_CLK, - .cfg = { - .esdhc_base = (void __iomem *)USDHC2_BASE_ADDR, - .cd_gpio = IMX_GPIO_NR(7, 3), - .wp_gpio = -EINVAL, - }, - }, -}; - -static inline struct tx6q_esdhc_cfg *to_tx6q_esdhc_cfg(struct fsl_esdhc_cfg *cfg) -{ - void *p = cfg; - - return p - offsetof(struct tx6q_esdhc_cfg, cfg); -} - -int board_mmc_getcd(struct mmc *mmc) -{ - struct fsl_esdhc_cfg *cfg = mmc->priv; - - if (cfg->cd_gpio < 0) - return cfg->cd_gpio; - - debug("SD card %d is %spresent\n", - to_tx6q_esdhc_cfg(cfg) - tx6q_esdhc_cfg, gpio_get_value(cfg->cd_gpio) ? "NOT " : ""); - return !gpio_get_value(cfg->cd_gpio); -} - -int board_mmc_init(bd_t *bis) -{ - int i; - - for (i = 0; i < ARRAY_SIZE(tx6q_esdhc_cfg); i++) { - struct mmc *mmc; - struct fsl_esdhc_cfg *cfg = &tx6q_esdhc_cfg[i].cfg; - - if (i >= CONFIG_SYS_FSL_ESDHC_NUM) - break; - - cfg->sdhc_clk = mxc_get_clock(tx6q_esdhc_cfg[i].clkid); - imx_iomux_v3_setup_multiple_pads(tx6q_esdhc_cfg[i].pads, - tx6q_esdhc_cfg[i].num_pads); - - debug("%s: Initializing MMC slot %d\n", __func__, i); - fsl_esdhc_initialize(bis, cfg); - - mmc = find_mmc_device(i); - if (mmc == NULL) - continue; - if (board_mmc_getcd(mmc) > 0) - mmc_init(mmc); - } - return 0; -} -#endif /* CONFIG_CMD_MMC */ - -#ifdef CONFIG_FEC_MXC - -#define FEC_PAD_CTL (PAD_CTL_DVS | PAD_CTL_DSE_HIGH | \ - PAD_CTL_SRE_FAST) -#define FEC_PAD_CTL2 (PAD_CTL_DVS | PAD_CTL_SRE_FAST) -#define GPIO_PAD_CTL (PAD_CTL_DVS | PAD_CTL_DSE_HIGH) - -#ifndef ETH_ALEN -#define ETH_ALEN 6 -#endif - -int board_eth_init(bd_t *bis) -{ - int ret; - - /* delay at least 21ms for the PHY internal POR signal to deassert */ - udelay(22000); - - imx_iomux_v3_setup_multiple_pads(tx6q_fec_pads, ARRAY_SIZE(tx6q_fec_pads)); - - /* Deassert RESET to the external phy */ - gpio_set_value(TX6Q_FEC_RST_GPIO, 1); - - ret = cpu_eth_init(bis); - if (ret) - printf("cpu_eth_init() failed: %d\n", ret); - - return ret; -} -#endif /* CONFIG_FEC_MXC */ - -enum { - LED_STATE_INIT = -1, - LED_STATE_OFF, - LED_STATE_ON, -}; - -static inline int calc_blink_rate(int tmp) -{ - return CONFIG_SYS_HZ + CONFIG_SYS_HZ / 10 - - (tmp - TEMPERATURE_MIN) * CONFIG_SYS_HZ / - (TEMPERATURE_HOT - TEMPERATURE_MIN); -} - -void show_activity(int arg) -{ - static int led_state = LED_STATE_INIT; - static int blink_rate; - static ulong last; - - if (led_state == LED_STATE_INIT) { - last = get_timer(0); - gpio_set_value(TX6Q_LED_GPIO, 1); - led_state = LED_STATE_ON; - blink_rate = calc_blink_rate(check_cpu_temperature(0)); - } else { - if (get_timer(last) > blink_rate) { - blink_rate = calc_blink_rate(check_cpu_temperature(0)); - last = get_timer_masked(); - if (led_state == LED_STATE_ON) { - gpio_set_value(TX6Q_LED_GPIO, 0); - } else { - gpio_set_value(TX6Q_LED_GPIO, 1); - } - led_state = 1 - led_state; - } - } -} - -static const iomux_v3_cfg_t stk5_pads[] = { - /* SW controlled LED on STK5 baseboard */ - MX6Q_PAD_EIM_A18__GPIO_2_20, - - /* LCD data pins */ - MX6Q_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0, - MX6Q_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1, - MX6Q_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2, - MX6Q_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3, - MX6Q_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4, - MX6Q_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5, - MX6Q_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6, - MX6Q_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7, - MX6Q_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8, - MX6Q_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9, - MX6Q_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10, - MX6Q_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11, - MX6Q_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12, - MX6Q_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13, - MX6Q_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14, - MX6Q_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15, - MX6Q_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16, - MX6Q_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17, - MX6Q_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18, - MX6Q_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19, - MX6Q_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20, - MX6Q_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21, - MX6Q_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22, - MX6Q_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23, - MX6Q_PAD_DI0_PIN2__IPU1_DI0_PIN2, /* HSYNC */ - MX6Q_PAD_DI0_PIN3__IPU1_DI0_PIN3, /* VSYNC */ - MX6Q_PAD_DI0_PIN15__IPU1_DI0_PIN15, /* OE_ACD */ - MX6Q_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK, /* LSCLK */ - - /* I2C bus on DIMM pins 40/41 */ - MX6Q_PAD_GPIO_6__I2C3_SDA, - MX6Q_PAD_GPIO_3__I2C3_SCL, - - /* TSC200x PEN IRQ */ - MX6Q_PAD_EIM_D26__GPIO_3_26, - - /* EDT-FT5x06 Polytouch panel */ - MX6Q_PAD_NANDF_CS2__GPIO_6_15, /* IRQ */ - MX6Q_PAD_EIM_A16__GPIO_2_22, /* RESET */ - MX6Q_PAD_EIM_A17__GPIO_2_21, /* WAKE */ - - /* USBH1 */ - MX6Q_PAD_EIM_D31__GPIO_3_31, /* VBUSEN */ - MX6Q_PAD_EIM_D30__GPIO_3_30, /* OC */ - /* USBOTG */ - MX6Q_PAD_EIM_D23__GPIO_3_23, /* USBOTG ID */ - MX6Q_PAD_GPIO_7__GPIO_1_7, /* VBUSEN */ - MX6Q_PAD_GPIO_8__GPIO_1_8, /* OC */ - - /* DEBUG */ - MX6Q_PAD_GPIO_0__CCM_CLKO, - MX6Q_PAD_NANDF_CS2__CCM_CLKO2, -}; - -static const struct gpio stk5_gpios[] = { - { TX6Q_LED_GPIO, GPIOF_OUTPUT_INIT_LOW, "HEARTBEAT LED", }, - - { IMX_GPIO_NR(3, 23), GPIOF_INPUT, "USBOTG ID", }, - { IMX_GPIO_NR(1, 8), GPIOF_INPUT, "USBOTG OC", }, - { IMX_GPIO_NR(1, 7), GPIOF_OUTPUT_INIT_LOW, "USBOTG VBUS enable", }, - { IMX_GPIO_NR(3, 30), GPIOF_INPUT, "USBH1 OC", }, - { IMX_GPIO_NR(3, 31), GPIOF_OUTPUT_INIT_LOW, "USBH1 VBUS enable", }, -}; - -#ifdef CONFIG_LCD -vidinfo_t panel_info = { - /* set to max. size supported by SoC */ - .vl_col = 1920, - .vl_row = 1080, - - .vl_bpix = LCD_COLOR24, /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */ -}; - -static struct fb_videomode tx6q_fb_mode = { - /* Standard VGA timing */ - .name = "VGA", - .refresh = 60, - .xres = 640, - .yres = 480, - .pixclock = KHZ2PICOS(25175), - .left_margin = 48, - .hsync_len = 96, - .right_margin = 16, - .upper_margin = 31, - .vsync_len = 2, - .lower_margin = 12, - .sync = FB_SYNC_CLK_LAT_FALL, - .vmode = FB_VMODE_NONINTERLACED, -}; - -static int lcd_enabled = 1; - -void lcd_enable(void) -{ - /* HACK ALERT: - * global variable from common/lcd.c - * Set to 0 here to prevent messages from going to LCD - * rather than serial console - */ - lcd_is_enabled = 0; - - karo_load_splashimage(1); - if (lcd_enabled) { - debug("Switching LCD on\n"); - gpio_set_value(TX6Q_LCD_PWR_GPIO, 1); - udelay(100); - gpio_set_value(TX6Q_LCD_RST_GPIO, 1); - udelay(300000); - gpio_set_value(TX6Q_LCD_BACKLIGHT_GPIO, 0); - } -} - -static const iomux_v3_cfg_t stk5_lcd_pads[] = { - /* LCD RESET */ - MX6Q_PAD_EIM_D29__GPIO_3_29, - /* LCD POWER_ENABLE */ - MX6Q_PAD_EIM_EB3__GPIO_2_31, - /* LCD Backlight (PWM) */ - MX6Q_PAD_GPIO_1__GPIO_1_1, - - /* Display */ - MX6Q_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK, - MX6Q_PAD_DI0_PIN15__IPU1_DI0_PIN15, - MX6Q_PAD_DI0_PIN2__IPU1_DI0_PIN2, - MX6Q_PAD_DI0_PIN3__IPU1_DI0_PIN3, - MX6Q_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0, - MX6Q_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1, - MX6Q_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2, - MX6Q_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3, - MX6Q_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4, - MX6Q_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5, - MX6Q_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6, - MX6Q_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7, - MX6Q_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8, - MX6Q_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9, - MX6Q_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10, - MX6Q_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11, - MX6Q_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12, - MX6Q_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13, - MX6Q_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14, - MX6Q_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15, - MX6Q_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16, - MX6Q_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17, - MX6Q_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18, - MX6Q_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19, - MX6Q_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20, - MX6Q_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21, - MX6Q_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22, - MX6Q_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23, - - /* LVDS option */ - MX6Q_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3, - MX6Q_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2, - MX6Q_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK, - MX6Q_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1, - MX6Q_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0, - MX6Q_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3, - MX6Q_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK, - MX6Q_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2, - MX6Q_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1, - MX6Q_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0, -}; - -static const struct gpio stk5_lcd_gpios[] = { - { TX6Q_LCD_RST_GPIO, GPIOF_OUTPUT_INIT_LOW, "LCD RESET", }, - { TX6Q_LCD_PWR_GPIO, GPIOF_OUTPUT_INIT_LOW, "LCD POWER", }, - { TX6Q_LCD_BACKLIGHT_GPIO, GPIOF_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", }, -}; - -void lcd_ctrl_init(void *lcdbase) -{ - int color_depth = 24; - char *vm; - unsigned long val; - int refresh = 60; - struct fb_videomode *p = &tx6q_fb_mode; - int xres_set = 0, yres_set = 0, bpp_set = 0, refresh_set = 0; - int pix_fmt = 0; - ipu_di_clk_parent_t di_clk_parent = DI_PCLK_PLL3; - unsigned long di_clk_rate = 65000000; - - if (!lcd_enabled) { - debug("LCD disabled\n"); - return; - } - - if (tstc() || (wrsr & WRSR_TOUT)) { - debug("Disabling LCD\n"); - lcd_enabled = 0; - return; - } - - vm = getenv("video_mode"); - if (vm == NULL) { - debug("Disabling LCD\n"); - lcd_enabled = 0; - return; - } - while (*vm != '\0') { - if (*vm >= '0' && *vm <= '9') { - char *end; - - val = simple_strtoul(vm, &end, 0); - if (end > vm) { - if (!xres_set) { - if (val > panel_info.vl_col) - val = panel_info.vl_col; - p->xres = val; - panel_info.vl_col = val; - xres_set = 1; - } else if (!yres_set) { - if (val > panel_info.vl_row) - val = panel_info.vl_row; - p->yres = val; - panel_info.vl_row = val; - yres_set = 1; - } else if (!bpp_set) { - switch (val) { - case 24: - if (pix_fmt == IPU_PIX_FMT_LVDS666) - pix_fmt = IPU_PIX_FMT_LVDS888; - /* fallthru */ - case 16: - case 8: - color_depth = val; - break; - - case 18: - if (pix_fmt == IPU_PIX_FMT_LVDS666) { - color_depth = val; - break; - } - /* fallthru */ - default: - printf("Invalid color depth: '%.*s' in video_mode; using default: '%u'\n", - end - vm, vm, color_depth); - } - bpp_set = 1; - } else if (!refresh_set) { - refresh = val; - refresh_set = 1; - } - } - vm = end; - } - switch (*vm) { - case '@': - bpp_set = 1; - /* fallthru */ - case '-': - yres_set = 1; - /* fallthru */ - case 'x': - xres_set = 1; - /* fallthru */ - case 'M': - case 'R': - vm++; - break; - - default: - if (!pix_fmt) { - char *tmp; - - if (strncmp(vm, "LVDS", 4) == 0) { - pix_fmt = IPU_PIX_FMT_LVDS666; - di_clk_parent = DI_PCLK_LDB; - } else { - pix_fmt = IPU_PIX_FMT_RGB24; - } - tmp = strchr(vm, ':'); - if (tmp) - vm = tmp; - } - if (*vm != '\0') - vm++; - } - } - switch (color_depth) { - case 8: - panel_info.vl_bpix = 3; - break; - - case 16: - panel_info.vl_bpix = 4; - break; - - case 18: - case 24: - panel_info.vl_bpix = 5; - } - - p->pixclock = KHZ2PICOS(refresh * - (p->xres + p->left_margin + p->right_margin + p->hsync_len) * - (p->yres + p->upper_margin + p->lower_margin + p->vsync_len) - / 1000); - debug("Pixel clock set to %lu.%03lu MHz\n", - PICOS2KHZ(p->pixclock) / 1000, - PICOS2KHZ(p->pixclock) % 1000); - - gpio_request_array(stk5_lcd_gpios, ARRAY_SIZE(stk5_lcd_gpios)); - imx_iomux_v3_setup_multiple_pads(stk5_lcd_pads, - ARRAY_SIZE(stk5_lcd_pads)); - - debug("Initializing FB driver\n"); - if (!pix_fmt) - pix_fmt = IPU_PIX_FMT_RGB24; - else if (pix_fmt == IPU_PIX_FMT_LVDS666) { - writel(0x01, IOMUXC_BASE_ADDR + 8); - } else if (pix_fmt == IPU_PIX_FMT_LVDS888) { - writel(0x21, IOMUXC_BASE_ADDR + 8); - } - if (pix_fmt != IPU_PIX_FMT_RGB24) { - struct mxc_ccm_reg *ccm_regs = (struct mxc_ccm_reg *)CCM_BASE_ADDR; - /* enable LDB & DI0 clock */ - writel(readl(&ccm_regs->CCGR3) | (3 << 12) | (3 << 2), - &ccm_regs->CCGR3); - } - - if (karo_load_splashimage(0) == 0) { - debug("Initializing LCD controller\n"); - ipuv3_fb_init(p, 0, pix_fmt, di_clk_parent, di_clk_rate, -1); - } else { - debug("Skipping initialization of LCD controller\n"); - } -} -#else -#define lcd_enabled 0 -#endif /* CONFIG_LCD */ - -static void stk5_board_init(void) -{ - gpio_request_array(stk5_gpios, ARRAY_SIZE(stk5_gpios)); - imx_iomux_v3_setup_multiple_pads(stk5_pads, ARRAY_SIZE(stk5_pads)); -} - -static void stk5v3_board_init(void) -{ - stk5_board_init(); -} - -static void stk5v5_board_init(void) -{ - stk5_board_init(); - - gpio_request_one(IMX_GPIO_NR(4, 21), GPIOF_OUTPUT_INIT_HIGH, - "Flexcan Transceiver"); - imx_iomux_v3_setup_pad(MX6Q_PAD_DISP0_DAT0__GPIO_4_21); -} - -static void tx6q_set_cpu_clock(void) -{ - unsigned long cpu_clk = getenv_ulong("cpu_clk", 10, 0); - - if (tstc() || (wrsr & WRSR_TOUT)) - return; - - if (cpu_clk == 0 || cpu_clk == mxc_get_clock(MXC_ARM_CLK) / 1000000) - return; - - if (mxc_set_clock(CONFIG_SYS_MX6_HCLK, cpu_clk, MXC_ARM_CLK) == 0) { - cpu_clk = mxc_get_clock(MXC_ARM_CLK); - printf("CPU clock set to %lu.%03lu MHz\n", - cpu_clk / 1000000, cpu_clk / 1000 % 1000); - } else { - printf("Failed to set CPU clock to %lu MHz\n", cpu_clk); - } -} - -static void tx6_init_mac(void) -{ - u8 mac[ETH_ALEN]; - char mac_str[ETH_ALEN * 3] = ""; - - imx_get_mac_from_fuse(-1, mac); - if (!is_valid_ether_addr(mac)) { - printf("No valid MAC address programmed\n"); - return; - } - - snprintf(mac_str, sizeof(mac_str), "%02x:%02x:%02x:%02x:%02x:%02x", - mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]); - setenv("ethaddr", mac_str); - printf("MAC addr from fuse: %02x:%02x:%02x:%02x:%02x:%02x\n", - mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]); -} - -int board_late_init(void) -{ - int ret = 0; - const char *baseboard; - - tx6q_set_cpu_clock(); - karo_fdt_move_fdt(); - - baseboard = getenv("baseboard"); - if (!baseboard) - goto exit; - - printf("Baseboard: %s\n", baseboard); - - if (strncmp(baseboard, "stk5", 4) == 0) { - if ((strlen(baseboard) == 4) || - strcmp(baseboard, "stk5-v3") == 0) { - stk5v3_board_init(); - } else if (strcmp(baseboard, "stk5-v5") == 0) { - stk5v5_board_init(); - } else { - printf("WARNING: Unsupported STK5 board rev.: %s\n", - baseboard + 4); - } - } else { - printf("WARNING: Unsupported baseboard: '%s'\n", - baseboard); - ret = -EINVAL; - } - -exit: - tx6_init_mac(); - - gpio_set_value(TX6Q_RESET_OUT_GPIO, 1); - return ret; -} - -#define iomux_field(v,f) (((iomux_v3_cfg_t)(v) << f##_SHIFT) & f##_MASK) - -#define chk_iomux_field(f1,f2) ({ \ - iomux_v3_cfg_t __c = iomux_field(~0, f1); \ - if (__c & f2##_MASK) { \ - printf("%18s[%016llx] overlaps with:\n%18s[%016llx]\n", \ - #f1, f1##_MASK, \ - #f2, f2##_MASK); \ - } \ - (__c & f2##_MASK) != 0; \ -}) - -#define chk_iomux_bit(f1,f2) ({ \ - iomux_v3_cfg_t __c = iomux_field(~0, f1); \ - if (__c & f2) { \ - printf("%18s[%016llx] overlaps with:\n%18s[%016llx]\n", \ - #f1, f1##_MASK, \ - #f2, (iomux_v3_cfg_t)f2); \ - } \ - (__c & f2) != 0; \ -}) - -int checkboard(void) -{ - print_cpuinfo(); - - printf("Board: Ka-Ro TX6Q\n"); - -#ifdef TIMER_TEST - { - struct mxc_gpt { - unsigned int control; - unsigned int prescaler; - unsigned int status; - unsigned int nouse[6]; - unsigned int counter; - }; - const int us_delay = 10; - unsigned long start = get_timer(0); - unsigned long last = gd->arch.tbl; - unsigned long loop = 0; - unsigned long cnt = 0; - static struct mxc_gpt *timer_base = (struct mxc_gpt *)GPT1_BASE_ADDR; - - printf("GPT prescaler=%u\n", readl(&timer_base->prescaler) + 1); - printf("clock tick rate: %lu.%03lukHz\n", - gd->arch.timer_rate_hz / 1000, gd->arch.timer_rate_hz % 1000); - printf("ticks/us=%lu\n", gd->arch.timer_rate_hz / CONFIG_SYS_HZ / 1000); - - while (!tstc()) { - unsigned long elapsed = get_timer(start); - unsigned long diff = gd->arch.tbl - last; - - loop++; - last = gd->arch.tbl; - - printf("loop %4lu: t=%08lx diff=%08lx steps=%6lu elapsed time: %4lu", - loop, gd->arch.tbl, diff, cnt, elapsed / CONFIG_SYS_HZ); - cnt = 0; - while (get_timer(elapsed + start) < CONFIG_SYS_HZ) { - cnt++; - udelay(us_delay); - } - printf(" counter=%08x udelay(%u)=%lu.%03luus\n", - readl(&timer_base->counter), us_delay, - 1000000000 / cnt / 1000, 1000000000 / cnt % 1000); - } - } -#endif - return 0; -} - -#ifdef CONFIG_SERIAL_TAG -void get_board_serial(struct tag_serialnr *serialnr) -{ - struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE; - struct fuse_bank0_regs *fuse = (void *)iim->bank[0].fuse_regs; - - serialnr->low = readl(&fuse->cfg0); - serialnr->high = readl(&fuse->cfg1); -} -#endif - -#if defined(CONFIG_OF_BOARD_SETUP) -#ifdef CONFIG_FDT_FIXUP_PARTITIONS -#include -#include -struct node_info nodes[] = { - { "fsl,imx6q-gpmi-nand", MTD_DEV_TYPE_NAND, }, -}; - -#else -#define fdt_fixup_mtdparts(b,n,c) do { } while (0) -#endif - -static void tx6q_fixup_flexcan(void *blob) -{ - const char *baseboard = getenv("baseboard"); - - if (baseboard && strcmp(baseboard, "stk5-v5") == 0) - return; - - karo_fdt_del_prop(blob, "fsl,p1010-flexcan", 0x02090000, "transceiver-switch"); - karo_fdt_del_prop(blob, "fsl,p1010-flexcan", 0x02094000, "transceiver-switch"); -} - -void ft_board_setup(void *blob, bd_t *bd) -{ - fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes)); - fdt_fixup_ethernet(blob); - - karo_fdt_fixup_touchpanel(blob); - karo_fdt_fixup_usb_otg(blob, "", 0); - tx6q_fixup_flexcan(blob); -} -#endif diff --git a/boards.cfg b/boards.cfg index 5ed914f482..64d2620cc8 100644 --- a/boards.cfg +++ b/boards.cfg @@ -261,12 +261,12 @@ tx53-xx20 arm armv7 tx53 karo mx5 tx53-xx21 arm armv7 tx53 karo mx5 tx53:NR_DRAM_BANKS=2,SYS_TX53_HWREV_2 tx53-xx30 arm armv7 tx53 karo mx5 tx53:NR_DRAM_BANKS=1 tx53-xx31 arm armv7 tx53 karo mx5 tx53:NR_DRAM_BANKS=2 -tx6dl arm armv7 tx6dl karo mx6 -tx6dl_mfg arm armv7 tx6dl karo mx6 tx6dl:MFG -tx6dl_noenv arm armv7 tx6dl karo mx6 tx6dl:ENV_IS_NOWHERE -tx6q arm armv7 tx6q karo mx6 -tx6q_mfg arm armv7 tx6q karo mx6 tx6q:MFG -tx6q_noenv arm armv7 tx6q karo mx6 tx6q:ENV_IS_NOWHERE +tx6dl arm armv7 tx6 karo mx6 tx6:MX6DL +tx6dl_mfg arm armv7 tx6 karo mx6 tx6:MX6DL,MFG +tx6dl_noenv arm armv7 tx6 karo mx6 tx6:MX6DL,ENV_IS_NOWHERE +tx6q arm armv7 tx6 karo mx6 tx6:MX6Q +tx6q_mfg arm armv7 tx6 karo mx6 tx6:MX6Q,MFG +tx6q_noenv arm armv7 tx6 karo mx6 tx6:MX6Q,ENV_IS_NOWHERE mx6qarm2 arm armv7 mx6qarm2 freescale mx6 mx6qarm2:IMX_CONFIG=board/freescale/mx6qarm2/imximage.cfg mx6qsabreauto arm armv7 mx6qsabreauto freescale mx6 mx6qsabreauto:IMX_CONFIG=board/freescale/mx6qsabreauto/imximage.cfg mx6qsabrelite arm armv7 mx6qsabrelite freescale mx6 mx6qsabrelite:IMX_CONFIG=board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg diff --git a/include/configs/tx6dl.h b/include/configs/tx6.h similarity index 87% rename from include/configs/tx6dl.h rename to include/configs/tx6.h index b6cab454ef..d482a7ab7f 100644 --- a/include/configs/tx6dl.h +++ b/include/configs/tx6.h @@ -10,16 +10,15 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ -#ifndef __TX6DL_H -#define __TX6DL_H +#ifndef __TX6_H +#define __TX6_H #include /* - * Ka-Ro TX6DL board - SoC configuration + * Ka-Ro TX6 board - SoC configuration */ #define CONFIG_MX6 -#define CONFIG_MX6DL #define CONFIG_SYS_MX6_HCLK 24000000 #define CONFIG_SYS_MX6_CLK32 32768 #define CONFIG_SYS_HZ 1000 /* Ticks per second */ @@ -50,19 +49,29 @@ */ #define CONFIG_NR_DRAM_BANKS 1 /* # of SDRAM banks */ #define PHYS_SDRAM_1 0x10000000 /* Base address of bank 1 */ +#ifdef CONFIG_MX6Q +#define PHYS_SDRAM_1_SIZE SZ_1G +#define PHYS_SDRAM_1_WIDTH 64 +#define CONFIG_SYS_SDRAM_CLK 528 +#else #define PHYS_SDRAM_1_SIZE SZ_512M #define PHYS_SDRAM_1_WIDTH 32 +#define CONFIG_SYS_SDRAM_CLK 400 +#endif #define CONFIG_STACKSIZE SZ_128K #define CONFIG_SYS_MALLOC_LEN SZ_8M #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1 /* Memtest start address */ #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + SZ_4M) -#define CONFIG_SYS_SDRAM_CLK 400 /* * U-Boot general configurations */ #define CONFIG_SYS_LONGHELP +#ifdef CONFIG_MX6Q +#define CONFIG_SYS_PROMPT "TX6Q U-Boot > " +#else #define CONFIG_SYS_PROMPT "TX6DL U-Boot > " +#endif #define CONFIG_SYS_CBSIZE 2048 /* Console I/O buffer size */ #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ sizeof(CONFIG_SYS_PROMPT) + 16) /* Print buffer size */ @@ -85,8 +94,13 @@ #define CONFIG_FDT_FIXUP_PARTITIONS #define CONFIG_OF_EMBED #define CONFIG_OF_BOARD_SETUP +#ifdef CONFIG_MX6Q +#define CONFIG_DEFAULT_DEVICE_TREE tx6q +#define CONFIG_ARCH_DEVICE_TREE mx6q +#else #define CONFIG_DEFAULT_DEVICE_TREE tx6dl #define CONFIG_ARCH_DEVICE_TREE mx6dl +#endif #define CONFIG_SYS_FDT_ADDR (PHYS_SDRAM_1 + SZ_16M) #endif /* CONFIG_OF_LIBFDT */ #endif /* CONFIG_MFG */ @@ -94,8 +108,8 @@ /* * Boot Linux */ -#define xstr(s) str(s) -#define str(s) #s +#define xstr(s) str(s) +#define str(s) #s #define __pfx(x, s) (x##s) #define _pfx(x, s) __pfx(x, s) @@ -155,6 +169,7 @@ "run bootm_cmd\0" \ "bootm_cmd=fdt boardsetup;bootm ${loadaddr} - ${fdtaddr}\0" \ "cpu_clk=800\0" \ + "bootdelay=-1\0" \ "default_bootargs=set bootargs " CONFIG_BOOTARGS \ " video=${video_mode} ${append_bootargs}\0" \ "fdtaddr=11000000\0" \ @@ -252,17 +267,17 @@ #define CONFIG_MTD_DEBUG #define CONFIG_MTD_DEBUG_VERBOSE 4 #endif +#ifndef CONFIG_SYS_NAND_ERASE_SIZE +#define CONFIG_SYS_NAND_ERASE_SIZE SZ_128K +#endif #define CONFIG_NAND_MXS -#define CONFIG_NAND_PAGE_SIZE 2048 -#define CONFIG_NAND_OOB_SIZE 64 -#define CONFIG_NAND_PAGES_PER_BLOCK 64 +#define CONFIG_NAND_MXS_NO_BBM_SWAP #define CONFIG_APBH_DMA #define CONFIG_APBH_DMA_BURST #define CONFIG_APBH_DMA_BURST8 -#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x20000 +#define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SYS_NAND_ERASE_SIZE #define CONFIG_CMD_NAND_TRIMFFS #define CONFIG_SYS_MXS_DMA_CHANNEL 4 -#define CONFIG_SYS_MAX_FLASH_SECT 1024 #define CONFIG_SYS_MAX_FLASH_BANKS 1 #define CONFIG_SYS_NAND_MAX_CHIPS 1 #define CONFIG_SYS_MAX_NAND_DEVICE 1 @@ -276,17 +291,17 @@ #define CONFIG_ENV_OFFSET (CONFIG_U_BOOT_IMG_SIZE + CONFIG_SYS_NAND_U_BOOT_OFFS) #define CONFIG_ENV_SIZE SZ_128K -#define CONFIG_ENV_RANGE 0x60000 +#define CONFIG_ENV_RANGE (3 * CONFIG_SYS_NAND_ERASE_SIZE) #ifdef CONFIG_ENV_OFFSET_REDUND -#define CONFIG_SYS_ENV_PART_STR xstr(CONFIG_ENV_RANGE) \ +#define CONFIG_SYS_ENV_PART_STR xstr(CONFIG_SYS_ENV_PART_SIZE) \ "(env)," \ - xstr(CONFIG_ENV_RANGE) \ + xstr(CONFIG_SYS_ENV_PART_SIZE) \ "(env2)," -#define CONFIG_SYS_USERFS_PART_STR "91520k(userfs)" +#define CONFIG_SYS_USERFS_PART_STR xstr(CONFIG_SYS_USERFS_PART_SIZE) "(userfs)" #else -#define CONFIG_SYS_ENV_PART_STR xstr(CONFIG_ENV_RANGE) \ +#define CONFIG_SYS_ENV_PART_STR xstr(CONFIG_SYS_ENV_PART_SIZE) \ "(env)," -#define CONFIG_SYS_USERFS_PART_STR "91904k(userfs)" +#define CONFIG_SYS_USERFS_PART_STR xstr(CONFIG_SYS_USERFS_PART_SIZE2) "(userfs)" #endif /* CONFIG_ENV_OFFSET_REDUND */ /* @@ -326,10 +341,15 @@ #endif #define MTDPARTS_DEFAULT "mtdparts=" MTD_NAME ":" \ - "1m@" xstr(CONFIG_SYS_NAND_U_BOOT_OFFS) "(u-boot)," \ + xstr(CONFIG_SYS_U_BOOT_PART_SIZE) \ + "@" xstr(CONFIG_SYS_U_BOOT_OFFSET) \ + "(u-boot)," \ CONFIG_SYS_ENV_PART_STR \ - "4m(linux),32m(rootfs),256k(dtb)," \ - CONFIG_SYS_USERFS_PART_STR ",512k@0x7f80000(bbt)ro" + "4m(linux),32m(rootfs)," CONFIG_SYS_USERFS_PART_STR "," \ + xstr(CONFIG_SYS_DTB_PART_SIZE) \ + "(dtb)," \ + xstr(CONFIG_SYS_NAND_BBT_SIZE) \ + "@" xstr(CONFIG_SYS_NAND_BBT_OFFSET) "(bbt)ro" #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \ diff --git a/include/configs/tx6q.h b/include/configs/tx6q.h deleted file mode 100644 index 6f62113162..0000000000 --- a/include/configs/tx6q.h +++ /dev/null @@ -1,339 +0,0 @@ -/* - * Copyright (C) 2012 - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation version 2. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ -#ifndef __TX6Q_H -#define __TX6Q_H - -#include - -/* - * Ka-Ro TX6Q board - SoC configuration - */ -#define CONFIG_MX6 -#define CONFIG_MX6Q -#define CONFIG_SYS_MX6_HCLK 24000000 -#define CONFIG_SYS_MX6_CLK32 32768 -#define CONFIG_SYS_HZ 1000 /* Ticks per second */ -#define CONFIG_SHOW_ACTIVITY -#define CONFIG_ARCH_CPU_INIT -#define CONFIG_DISPLAY_BOARDINFO -#define CONFIG_BOARD_LATE_INIT -#define CONFIG_BOARD_EARLY_INIT_F - -#ifndef CONFIG_MFG -/* LCD Logo and Splash screen support */ -#define CONFIG_LCD -#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE -#ifdef CONFIG_LCD -#define CONFIG_SPLASH_SCREEN -#define CONFIG_SPLASH_SCREEN_ALIGN -#define CONFIG_VIDEO_IPUV3 -#define CONFIG_IPU_CLKRATE 266000000 -#define CONFIG_LCD_LOGO -#define LCD_BPP LCD_COLOR24 -#define CONFIG_CMD_BMP -#define CONFIG_VIDEO_BMP_RLE8 -#endif /* CONFIG_LCD */ -#endif /* CONFIG_MFG */ - -/* - * Memory configuration options - */ -#define CONFIG_NR_DRAM_BANKS 1 /* # of SDRAM banks */ -#define PHYS_SDRAM_1 0x10000000 /* Base address of bank 1 */ -#define PHYS_SDRAM_1_SIZE SZ_1G -#define CONFIG_STACKSIZE SZ_128K -#define CONFIG_SYS_MALLOC_LEN SZ_8M -#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1 /* Memtest start address */ -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + SZ_4M) -#define CONFIG_SYS_SDRAM_CLK 528 - -/* - * U-Boot general configurations - */ -#define CONFIG_SYS_LONGHELP -#define CONFIG_SYS_PROMPT "TX6Q U-Boot > " -#define CONFIG_SYS_CBSIZE 2048 /* Console I/O buffer size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) /* Print buffer size */ -#define CONFIG_SYS_MAXARGS 64 /* Max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - /* Boot argument buffer size */ -#define CONFIG_VERSION_VARIABLE /* U-BOOT version */ -#define CONFIG_AUTO_COMPLETE /* Command auto complete */ -#define CONFIG_CMDLINE_EDITING /* Command history etc */ - -#define CONFIG_SYS_64BIT_VSPRINTF -#define CONFIG_SYS_NO_FLASH - -/* - * Flattened Device Tree (FDT) support -*/ -#ifndef CONFIG_MFG -#define CONFIG_OF_LIBFDT -#ifdef CONFIG_OF_LIBFDT -#define CONFIG_FDT_FIXUP_PARTITIONS -#define CONFIG_OF_EMBED -#define CONFIG_OF_BOARD_SETUP -#define CONFIG_DEFAULT_DEVICE_TREE tx6q -#define CONFIG_ARCH_DEVICE_TREE mx6q -#define CONFIG_SYS_FDT_ADDR (PHYS_SDRAM_1 + SZ_16M) -#endif /* CONFIG_OF_LIBFDT */ -#endif /* CONFIG_MFG */ - -/* - * Boot Linux - */ -#define xstr(s) str(s) -#define str(s) #s -#define __pfx(x, s) (x##s) -#define _pfx(x, s) __pfx(x, s) - -#define CONFIG_CMDLINE_TAG -#define CONFIG_INITRD_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_SERIAL_TAG -#ifndef CONFIG_MFG -#define CONFIG_BOOTDELAY 1 -#else -#define CONFIG_BOOTDELAY 0 -#endif -#define CONFIG_ZERO_BOOTDELAY_CHECK -#define CONFIG_SYS_AUTOLOAD "no" -#ifndef CONFIG_MFG -#define CONFIG_BOOTFILE "uImage" -#define CONFIG_BOOTARGS "console=ttymxc0,115200 ro debug panic=1" -#define CONFIG_BOOTCOMMAND "run bootcmd_nand" -#else -#define CONFIG_BOOTCOMMAND "env import " xstr(CONFIG_BOOTCMD_MFG_LOADADDR) ";run bootcmd_mfg" -#define CONFIG_BOOTCMD_MFG_LOADADDR 10500000 -#define CONFIG_DELAY_ENVIRONMENT -#endif /* CONFIG_MFG */ -#define CONFIG_LOADADDR 18000000 -#define CONFIG_SYS_LOAD_ADDR _pfx(0x, CONFIG_LOADADDR) -#define CONFIG_U_BOOT_IMG_SIZE SZ_1M -#define CONFIG_IMX_WATCHDOG -#define CONFIG_WATCHDOG_TIMEOUT_MSECS 3000 - -/* - * Extra Environments - */ -#ifndef CONFIG_MFG -#ifdef CONFIG_ENV_IS_NOWHERE -#define CONFIG_EXTRA_ENV_SETTINGS \ - "autostart=no\0" \ - "autoload=no\0" \ - "bootdelay=-1\0" \ - "fdtaddr=11000000\0" \ - "mtdids=" MTDIDS_DEFAULT "\0" \ - "mtdparts=" MTDPARTS_DEFAULT "\0" -#else -#define CONFIG_EXTRA_ENV_SETTINGS \ - "autostart=no\0" \ - "baseboard=stk5-v3\0" \ - "bootargs_mmc=run default_bootargs;set bootargs ${bootargs}" \ - " root=/dev/mmcblk0p3 rootwait\0" \ - "bootargs_nand=run default_bootargs;set bootargs ${bootargs}" \ - " root=/dev/mtdblock3 rootfstype=jffs2\0" \ - "bootargs_nfs=run default_bootargs;set bootargs ${bootargs}" \ - " root=/dev/nfs ip=dhcp nfsroot=${serverip}:${nfsroot},nolock\0"\ - "bootcmd_mmc=set autostart no;run bootargs_mmc;" \ - "fatload mmc 0 ${loadaddr} uImage;run bootm_cmd\0" \ - "bootcmd_nand=set autostart no;run bootargs_nand;" \ - "nboot linux;run bootm_cmd\0" \ - "bootcmd_net=set autostart no;run bootargs_nfs;dhcp;" \ - "run bootm_cmd\0" \ - "bootm_cmd=fdt boardsetup;bootm ${loadaddr} - ${fdtaddr}\0" \ - "cpu_clk=800\0" \ - "default_bootargs=set bootargs " CONFIG_BOOTARGS \ - " video=${video_mode} ${append_bootargs}\0" \ - "fdtaddr=11000000\0" \ - "mtdids=" MTDIDS_DEFAULT "\0" \ - "mtdparts=" MTDPARTS_DEFAULT "\0" \ - "nfsroot=/tftpboot/rootfs\0" \ - "otg_mode=device\0" \ - "touchpanel=tsc2007\0" \ - "video_mode=VGA-1:640x480MR-24@60\0" -#endif /* CONFIG_ENV_IS_NOWHERE */ -#endif /* CONFIG_MFG */ - -#define MTD_NAME "gpmi-nand" -#define MTDIDS_DEFAULT "nand0=" MTD_NAME -#define CONFIG_SYS_NAND_ONFI_DETECTION - -/* - * U-Boot Commands - */ -#include -#define CONFIG_CMD_CACHE -#define CONFIG_CMD_MMC -#define CONFIG_CMD_NAND -#define CONFIG_CMD_MTDPARTS -#define CONFIG_CMD_BOOTCE -#define CONFIG_CMD_TIME -#define CONFIG_CMD_I2C - -/* - * Serial Driver - */ -#define CONFIG_MXC_UART -#define CONFIG_MXC_UART_BASE UART1_BASE -#define CONFIG_BAUDRATE 115200 /* Default baud rate */ -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, } -#define CONFIG_SYS_CONSOLE_INFO_QUIET - -/* - * GPIO driver - */ -#define CONFIG_MXC_GPIO - -/* - * Ethernet Driver - */ -#define CONFIG_FEC_MXC -#ifdef CONFIG_FEC_MXC -/* This is required for the FEC driver to work with cache enabled */ -#define CONFIG_SYS_ARM_CACHE_WRITETHROUGH - -#define IMX_FEC_BASE ENET_BASE_ADDR -#define CONFIG_FEC_MXC_PHYADDR 0 -#define CONFIG_PHYLIB -#define CONFIG_PHY_SMSC -#define CONFIG_MII -#define CONFIG_FEC_XCV_TYPE RMII -#define CONFIG_GET_FEC_MAC_ADDR_FROM_IIM -#define CONFIG_CMD_MII -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_PING -/* Add for working with "strict" DHCP server */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_DNS -#endif - -/* - * I2C Configs - */ -#ifdef CONFIG_CMD_I2C -#define CONFIG_HARD_I2C 1 -#define CONFIG_I2C_MXC 1 -#define CONFIG_SYS_I2C_BASE I2C1_BASE_ADDR -#define CONFIG_SYS_I2C_MX6_PORT1 -#define CONFIG_SYS_I2C_SPEED 10000 -#define CONFIG_SYS_I2C_SLAVE 0x3c -#define CONFIG_MX6_INTER_LDO_BYPASS 0 -#endif - -#ifndef CONFIG_ENV_IS_NOWHERE -/* define one of the following options: -#define CONFIG_ENV_IS_IN_NAND -#define CONFIG_ENV_IS_IN_MMC -*/ -#define CONFIG_ENV_IS_IN_NAND -#endif -#define CONFIG_ENV_OVERWRITE - -/* - * NAND flash driver - */ -#ifdef CONFIG_CMD_NAND -#define CONFIG_MTD_DEVICE -#if 0 -#define CONFIG_MTD_DEBUG -#define CONFIG_MTD_DEBUG_VERBOSE 4 -#endif -#define CONFIG_NAND_MXS -#define CONFIG_NAND_MXS_NO_BBM_SWAP -#define CONFIG_APBH_DMA -#define CONFIG_APBH_DMA_BURST -#define CONFIG_APBH_DMA_BURST8 -#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x20000 -#define CONFIG_CMD_NAND_TRIMFFS -#define CONFIG_SYS_MXS_DMA_CHANNEL 4 -#define CONFIG_SYS_MAX_FLASH_SECT 1024 -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -#define CONFIG_SYS_NAND_MAX_CHIPS 1 -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_5_ADDR_CYCLE -#define CONFIG_SYS_NAND_USE_FLASH_BBT -#define CONFIG_SYS_NAND_BASE 0x00000000 -#define CONFIG_CMD_ROMUPDATE -#else -#undef CONFIG_ENV_IS_IN_NAND -#endif /* CONFIG_CMD_NAND */ - -#define CONFIG_ENV_OFFSET (CONFIG_U_BOOT_IMG_SIZE + CONFIG_SYS_NAND_U_BOOT_OFFS) -#define CONFIG_ENV_SIZE SZ_128K -#define CONFIG_ENV_RANGE 0x60000 -#ifdef CONFIG_ENV_OFFSET_REDUND -#define CONFIG_SYS_ENV_PART_STR xstr(CONFIG_ENV_RANGE) \ - "(env)," \ - xstr(CONFIG_ENV_RANGE) \ - "(env2)," -#define CONFIG_SYS_USERFS_PART_STR "91520k(userfs)" -#else -#define CONFIG_SYS_ENV_PART_STR xstr(CONFIG_ENV_RANGE) \ - "(env)," -#define CONFIG_SYS_USERFS_PART_STR "91904k(userfs)" -#endif /* CONFIG_ENV_OFFSET_REDUND */ - -/* - * MMC Driver - */ -#ifdef CONFIG_CMD_MMC -#define CONFIG_MMC -#define CONFIG_GENERIC_MMC -#define CONFIG_FSL_ESDHC -#define CONFIG_FSL_USDHC -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 -#define CONFIG_SYS_FSL_ESDHC_NUM 2 - -#define CONFIG_DOS_PARTITION -#define CONFIG_CMD_FAT -#define CONFIG_CMD_EXT2 - -/* - * Environments on MMC - */ -#ifdef CONFIG_ENV_IS_IN_MMC -#define CONFIG_SYS_MMC_ENV_DEV 0 -#undef CONFIG_ENV_OFFSET -#undef CONFIG_ENV_SIZE -/* Associated with the MMC layout defined in mmcops.c */ -#define CONFIG_ENV_OFFSET SZ_1K -#define CONFIG_ENV_SIZE (SZ_128K - CONFIG_ENV_OFFSET) -#define CONFIG_DYNAMIC_MMC_DEVNO -#endif /* CONFIG_ENV_IS_IN_MMC */ -#else -#undef CONFIG_ENV_IS_IN_MMC -#endif /* CONFIG_CMD_MMC */ - -#ifdef CONFIG_ENV_IS_NOWHERE -#undef CONFIG_ENV_SIZE -#define CONFIG_ENV_SIZE SZ_4K -#endif - -#define MTDPARTS_DEFAULT "mtdparts=" MTD_NAME ":" \ - "1m@" xstr(CONFIG_SYS_NAND_U_BOOT_OFFS) "(u-boot)," \ - CONFIG_SYS_ENV_PART_STR \ - "4m(linux),32m(rootfs),256k(dtb)," \ - CONFIG_SYS_USERFS_PART_STR ",512k@0x7f80000(bbt)ro" - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \ - GENERATED_GBL_DATA_SIZE) - -#ifdef CONFIG_CMD_IIM -#define CONFIG_IMX_IIM -#endif - -#endif /* __CONFIG_H */ -- 2.39.2