From b0e91436ce6f447f18cf25c4f59e6ce05056e5f8 Mon Sep 17 00:00:00 2001 From: =?utf8?q?Lothar=20Wa=C3=9Fmann?= Date: Mon, 3 Apr 2017 13:29:40 +0200 Subject: [PATCH] karo: add support for TX6UL-5012 --- board/karo/tx6/tx6ul.c | 2 +- board/karo/tx6/tx6ul_ll_init.S | 40 +++++++++++++++++++++++++++--- configs/tx6ul-5012_defconfig | 36 +++++++++++++++++++++++++++ configs/tx6ul-5012_mfg_defconfig | 34 +++++++++++++++++++++++++ configs/tx6ul-5012_noenv_defconfig | 34 +++++++++++++++++++++++++ configs/tx6ul-5012_sec_defconfig | 36 +++++++++++++++++++++++++++ 6 files changed, 177 insertions(+), 5 deletions(-) create mode 100644 configs/tx6ul-5012_defconfig create mode 100644 configs/tx6ul-5012_mfg_defconfig create mode 100644 configs/tx6ul-5012_noenv_defconfig create mode 100644 configs/tx6ul-5012_sec_defconfig diff --git a/board/karo/tx6/tx6ul.c b/board/karo/tx6/tx6ul.c index 193f690990..7db844a07c 100644 --- a/board/karo/tx6/tx6ul.c +++ b/board/karo/tx6/tx6ul.c @@ -432,7 +432,7 @@ static bool tx6ul_temp_check_enabled = true; static inline u8 tx6ul_mem_suffix(void) { #ifdef CONFIG_TX6_NAND - return '0'; + return CONFIG_SYS_SDRAM_CHIP_SIZE / 1024 * 2 + '0'; #else return '1'; #endif diff --git a/board/karo/tx6/tx6ul_ll_init.S b/board/karo/tx6/tx6ul_ll_init.S index bdd2214c9a..16201058f8 100644 --- a/board/karo/tx6/tx6ul_ll_init.S +++ b/board/karo/tx6/tx6ul_ll_init.S @@ -94,6 +94,7 @@ dcd_end: #define CK_TO_NS(ck) (((ck) * 1000 + SDRAM_CLK / 2) / SDRAM_CLK) #define NS_TO_CK(ns) (((ns) * SDRAM_CLK + 999) / 1000) #define NS_TO_CK10(ns) DIV_ROUND_UP(NS_TO_CK(ns), 10) +#define NS_TO_CK100(ns) DIV_ROUND_UP(NS_TO_CK(ns), 100) #define PS_TO_CK(ps) DIV_ROUND_UP(NS_TO_CK(ps), 1000) .macro CK_VAL, name, clks, offs, max @@ -133,7 +134,7 @@ dcd_end: #define MDOR_CLK_PERIOD_ns 15258 /* base clock for MDOR values */ /* DDR3 SDRAM */ -#if SDRAM_SIZE > PHYS_SDRAM_1_SIZE +#ifdef PHYS_SDRAM_2_SIZE #define BANK_ADDR_BITS 2 #else #define BANK_ADDR_BITS 1 @@ -165,6 +166,11 @@ dcd_end: #error SDRAM clock out of range: 303 .. 800 #endif +#if SDRAM_SIZE <= SZ_256M +/* 256MiB SDRAM: NT5CB128M16FP-DII */ +#define ROW_ADDR_BITS 14 +#define COL_ADDR_BITS 10 + /* MDCFG0 0x0c */ NS_VAL tRFC, 160, 1, 255 /* clks - 1 (0..255) */ CK_MAX tXS, NS_TO_CK(CK_TO_NS(tRFC + 1) + 10), 5, 1, 255 /* clks - 1 (0..255) tRFC + 10 */ @@ -188,6 +194,35 @@ CK_VAL tDLLK, 512, 1, 511 /* clks - 1 (0..511) */ /* (Jedec Standard) */ CK_MAX tRTP, NS_TO_CK10(75), 4, 1, 7 /* clks - 1 (0..7) */ /* max(4tCK, 7.5ns) */ CK_MAX tWTR, NS_TO_CK10(75), 4, 1, 7 /* clks - 1 (0..7) */ /* max(4tCK, 7.5ns) */ CK_MAX tRRD, NS_TO_CK(10), 4, 1, 7 /* clks - 1 (0..7) (MT41K128M16JT: 6ns) */ +#else +/* 512MiB SDRAM: IM4G16D3EABG-125I */ +#define ROW_ADDR_BITS 15 +#define COL_ADDR_BITS 10 + +/* MDCFG0 0x0c */ +NS_VAL tRFC, 260, 1, 255 /* clks - 1 (0..255) */ +CK_MAX tXS, NS_TO_CK(CK_TO_NS(tRFC + 1) + 10), 5, 1, 255 /* clks - 1 (0..255) tRFC + 10 */ +CK_MAX tXP, NS_TO_CK(6), 3, 1, 7 /* clks - 1 (0..7) */ /* max(3tCK, 7.5ns) */ +CK_MAX tXPDLL, NS_TO_CK(24), 2, 1, 15 /* clks - 1 (0..15) */ +NS_VAL tFAW, 30, 1, 31 /* clks - 1 (0..31) */ +CK_VAL tCL, CL_VAL, 3, 8 /* clks - 3 (0..8) CAS Latency */ + +/* MDCFG1 0x10 */ +CK_VAL tRCD, NS_TO_CK100(1375), 1, 7 /* clks - 1 (0..7) */ /* 13.75 */ +CK_VAL tRP, NS_TO_CK100(1375), 1, 7 /* clks - 1 (0..7) */ /* 13.75 */ +CK_VAL tRC, NS_TO_CK100(4875), 1, 31 /* clks - 1 (0..31) */ /* 48.75 */ +CK_VAL tRAS, NS_TO_CK(35), 1, 31 /* clks - 1 (0..31) */ /* 35 */ +CK_VAL tRPA, 1, 0, 1 /* clks (0..1) */ +NS_VAL tWR, 15, 1, 15 /* clks - 1 (0..15) */ +CK_VAL tMRD, 4, 1, 15 /* clks - 1 (0..15) */ +CK_VAL tCWL, CWL_VAL, 2, 6 /* clks - 2 (0..6) */ + +/* MDCFG2 0x14 */ +CK_VAL tDLLK, 512, 1, 511 /* clks - 1 (0..511) */ +CK_MAX tRTP, NS_TO_CK10(75), 4, 1, 7 /* clks - 1 (0..7) */ /* max(4tCK, 7.5ns) */ +CK_MAX tWTR, NS_TO_CK10(75), 4, 1, 7 /* clks - 1 (0..7) */ /* max(4tCK, 7.5ns) */ +CK_MAX tRRD, NS_TO_CK10(75), 4, 1, 7 /* clks - 1 (0..7) */ /* max(4tCK, 7.5ns) */ +#endif /* MDOR 0x30 */ CK_MAX tXPR, NS_TO_CK(CK_TO_NS(tRFC + 1) + 10), 5, 1, 255 /* clks - 1 (0..255) max(tRFC + 10, 5CK) */ @@ -227,9 +262,6 @@ CK_MAX tCKSRE, NS_TO_CK(10), 5, 0, 7 (PWDT << 8) \ ) -#define ROW_ADDR_BITS 14 -#define COL_ADDR_BITS 10 - #define Rtt_Nom 1 /* ODT: 0: off 1: RZQ/4 2: RZQ/2 3: RZQ/6 4: RZQ/12 5: RZQ/8 */ #define Rtt_WR 0 /* Dynamic ODT: 0: off 1: RZQ/4 2: RZQ/2 */ #define DLL_DISABLE 0 diff --git a/configs/tx6ul-5012_defconfig b/configs/tx6ul-5012_defconfig new file mode 100644 index 0000000000..3ee395e80c --- /dev/null +++ b/configs/tx6ul-5012_defconfig @@ -0,0 +1,36 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_SOC_MX6UL=y +CONFIG_TARGET_TX6=y +CONFIG_TARGET_TX6UL_NAND=y +CONFIG_TX6_UBOOT=y +CONFIG_BOOTP_DNS=y +CONFIG_BOOTP_GATEWAY=y +CONFIG_BOOTP_SUBNETMASK=y +CONFIG_CMD_BMP=y +CONFIG_CMD_BOOTCE=y +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_FUSE=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_MII=y +CONFIG_CMD_MMC=y +CONFIG_CMD_MTDPARTS=y +CONFIG_CMD_NAND=y +CONFIG_CMD_NAND_TRIMFFS=y +CONFIG_CMD_PING=y +CONFIG_CMD_TIME=y +CONFIG_DOS_PARTITION=y +CONFIG_ENV_IS_IN_NAND=y +CONFIG_FEC_MXC=y +CONFIG_IMX_WATCHDOG=y +CONFIG_LCD=y +CONFIG_MMC=y +CONFIG_NET=y +CONFIG_NETDEVICES=y +CONFIG_PHY_SMSC=y +CONFIG_SYS_PROMPT="TX6UL U-Boot > " +CONFIG_SYS_SDRAM_CHIP_SIZE=1024 diff --git a/configs/tx6ul-5012_mfg_defconfig b/configs/tx6ul-5012_mfg_defconfig new file mode 100644 index 0000000000..665f9a2bc3 --- /dev/null +++ b/configs/tx6ul-5012_mfg_defconfig @@ -0,0 +1,34 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_SOC_MX6UL=y +CONFIG_TARGET_TX6=y +CONFIG_TARGET_TX6UL_NAND=y +CONFIG_TX6_UBOOT_MFG=y +CONFIG_BOOTP_DNS=y +CONFIG_BOOTP_GATEWAY=y +CONFIG_BOOTP_SUBNETMASK=y +CONFIG_CMD_BMP=y +CONFIG_CMD_BOOTCE=y +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_FUSE=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_MII=y +CONFIG_CMD_MMC=y +CONFIG_CMD_MTDPARTS=y +CONFIG_CMD_NAND=y +CONFIG_CMD_NAND_TRIMFFS=y +CONFIG_CMD_PING=y +CONFIG_CMD_TIME=y +CONFIG_DOS_PARTITION=y +CONFIG_ENV_IS_IN_NAND=y +CONFIG_FEC_MXC=y +CONFIG_IMX_WATCHDOG=y +CONFIG_MMC=y +CONFIG_NET=y +CONFIG_NETDEVICES=y +CONFIG_PHY_SMSC=y +CONFIG_SYS_PROMPT="TX6UL U-Boot > " +CONFIG_SYS_SDRAM_CHIP_SIZE=1024 diff --git a/configs/tx6ul-5012_noenv_defconfig b/configs/tx6ul-5012_noenv_defconfig new file mode 100644 index 0000000000..b6e7947eef --- /dev/null +++ b/configs/tx6ul-5012_noenv_defconfig @@ -0,0 +1,34 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_SOC_MX6UL=y +CONFIG_TARGET_TX6=y +CONFIG_TARGET_TX6UL_NAND=y +CONFIG_TX6_UBOOT_NOENV=y +CONFIG_BOOTP_DNS=y +CONFIG_BOOTP_GATEWAY=y +CONFIG_BOOTP_SUBNETMASK=y +CONFIG_CMD_BMP=y +CONFIG_CMD_BOOTCE=y +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_FUSE=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_MII=y +CONFIG_CMD_MMC=y +CONFIG_CMD_MTDPARTS=y +CONFIG_CMD_NAND=y +CONFIG_CMD_NAND_TRIMFFS=y +CONFIG_CMD_PING=y +CONFIG_CMD_TIME=y +CONFIG_DOS_PARTITION=y +CONFIG_ENV_IS_IN_NAND=y +CONFIG_FEC_MXC=y +CONFIG_IMX_WATCHDOG=y +CONFIG_MMC=y +CONFIG_NET=y +CONFIG_NETDEVICES=y +CONFIG_PHY_SMSC=y +CONFIG_SYS_PROMPT="TX6UL U-Boot > " +CONFIG_SYS_SDRAM_CHIP_SIZE=1024 diff --git a/configs/tx6ul-5012_sec_defconfig b/configs/tx6ul-5012_sec_defconfig new file mode 100644 index 0000000000..a805bca4bd --- /dev/null +++ b/configs/tx6ul-5012_sec_defconfig @@ -0,0 +1,36 @@ +CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT" +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_SOC_MX6UL=y +CONFIG_TARGET_TX6=y +CONFIG_TARGET_TX6UL_NAND=y +CONFIG_TX6_UBOOT=y +CONFIG_BOOTP_DNS=y +CONFIG_BOOTP_GATEWAY=y +CONFIG_BOOTP_SUBNETMASK=y +CONFIG_CMD_BMP=y +CONFIG_CMD_BOOTCE=y +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_FUSE=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_MII=y +CONFIG_CMD_MMC=y +CONFIG_CMD_MTDPARTS=y +CONFIG_CMD_NAND=y +CONFIG_CMD_NAND_TRIMFFS=y +CONFIG_CMD_PING=y +CONFIG_CMD_TIME=y +CONFIG_DOS_PARTITION=y +CONFIG_ENV_IS_IN_NAND=y +CONFIG_FEC_MXC=y +CONFIG_IMX_WATCHDOG=y +CONFIG_LCD=y +CONFIG_MMC=y +CONFIG_NET=y +CONFIG_NETDEVICES=y +CONFIG_PHY_SMSC=y +CONFIG_SYS_PROMPT="TX6UL U-Boot > " +CONFIG_SYS_SDRAM_CHIP_SIZE=1024 -- 2.39.2