From b2eb6f032df14ca256a04d1fc146d0f3c303e041 Mon Sep 17 00:00:00 2001 From: "Wu, Josh" Date: Mon, 27 Jul 2015 11:40:17 +0800 Subject: [PATCH] ARM: cache: implement a default weak flush_cache() function Current many cpu use the same flush_cache() function, which just call the flush_dcache_range(). So implement a weak flush_cache() for all the cpus to use. In original weak flush_cache() in arch/arm/lib/cache.c, there has some code for ARM1136 & ARM926ejs. But in the arch/arm/cpu/arm1136/cpu.c and arch/arm/cpu/arm926ejs/cache.c, there implements a real flush_cache() function as well. That means the original code for ARM1136 & ARM926ejs in weak flush_cache() of arch/arm/lib/cache.c is totally useless. So in this patch remove such code in flush_cache() and only call flush_dcache_range(). Signed-off-by: Josh Wu --- arch/arm/cpu/arm11/cpu.c | 9 --------- arch/arm/cpu/arm926ejs/cache.c | 9 --------- arch/arm/cpu/armv7/cache_v7.c | 13 ------------- arch/arm/cpu/armv8/cache_v8.c | 8 -------- arch/arm/lib/cache.c | 28 +++++----------------------- 5 files changed, 5 insertions(+), 62 deletions(-) diff --git a/arch/arm/cpu/arm11/cpu.c b/arch/arm/cpu/arm11/cpu.c index 06dee0fc1b..1e4c2142b1 100644 --- a/arch/arm/cpu/arm11/cpu.c +++ b/arch/arm/cpu/arm11/cpu.c @@ -110,11 +110,6 @@ void flush_dcache_range(unsigned long start, unsigned long stop) asm volatile("mcr p15, 0, %0, c7, c10, 4" : : "r" (0)); } -void flush_cache(unsigned long start, unsigned long size) -{ - flush_dcache_range(start, start + size); -} - #else /* #ifndef CONFIG_SYS_DCACHE_OFF */ void invalidate_dcache_all(void) { @@ -123,10 +118,6 @@ void invalidate_dcache_all(void) void flush_dcache_all(void) { } - -void flush_cache(unsigned long start, unsigned long size) -{ -} #endif /* #ifndef CONFIG_SYS_DCACHE_OFF */ #if !defined(CONFIG_SYS_ICACHE_OFF) || !defined(CONFIG_SYS_DCACHE_OFF) diff --git a/arch/arm/cpu/arm926ejs/cache.c b/arch/arm/cpu/arm926ejs/cache.c index 99d1a139b0..e5c1a6ae6c 100644 --- a/arch/arm/cpu/arm926ejs/cache.c +++ b/arch/arm/cpu/arm926ejs/cache.c @@ -69,11 +69,6 @@ void flush_dcache_range(unsigned long start, unsigned long stop) asm volatile("mcr p15, 0, %0, c7, c10, 4\n" : : "r"(0)); } - -void flush_cache(unsigned long start, unsigned long size) -{ - flush_dcache_range(start, start + size); -} #else /* #ifndef CONFIG_SYS_DCACHE_OFF */ void invalidate_dcache_all(void) { @@ -82,10 +77,6 @@ void invalidate_dcache_all(void) void flush_dcache_all(void) { } - -void flush_cache(unsigned long start, unsigned long size) -{ -} #endif /* #ifndef CONFIG_SYS_DCACHE_OFF */ /* diff --git a/arch/arm/cpu/armv7/cache_v7.c b/arch/arm/cpu/armv7/cache_v7.c index 1dcceb846f..4a6207a740 100644 --- a/arch/arm/cpu/armv7/cache_v7.c +++ b/arch/arm/cpu/armv7/cache_v7.c @@ -288,15 +288,6 @@ void mmu_page_table_flush(unsigned long start, unsigned long stop) flush_dcache_range(start, stop); v7_inval_tlb(); } - -/* - * Flush range from all levels of d-cache/unified-cache used: - * Affects the range [start, start + size - 1] - */ -void flush_cache(unsigned long start, unsigned long size) -{ - flush_dcache_range(start, start + size); -} #else /* #ifndef CONFIG_SYS_DCACHE_OFF */ void invalidate_dcache_all(void) { @@ -310,10 +301,6 @@ void arm_init_before_mmu(void) { } -void flush_cache(unsigned long start, unsigned long size) -{ -} - void mmu_page_table_flush(unsigned long start, unsigned long stop) { } diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c index cd160c4b63..835f6a6525 100644 --- a/arch/arm/cpu/armv8/cache_v8.c +++ b/arch/arm/cpu/armv8/cache_v8.c @@ -253,11 +253,3 @@ void __weak enable_caches(void) icache_enable(); dcache_enable(); } - -/* - * Flush range from all levels of d-cache/unified-cache - */ -void flush_cache(unsigned long start, unsigned long size) -{ - flush_dcache_range(start, start + size); -} diff --git a/arch/arm/lib/cache.c b/arch/arm/lib/cache.c index a690e0b53c..cd13db3440 100644 --- a/arch/arm/lib/cache.c +++ b/arch/arm/lib/cache.c @@ -10,31 +10,13 @@ #include #include +/* + * Flush range from all levels of d-cache/unified-cache. + * Affects the range [start, start + size - 1]. + */ __weak void flush_cache(unsigned long start, unsigned long size) { -#if defined(CONFIG_CPU_ARM1136) - -#if !defined(CONFIG_SYS_ICACHE_OFF) - asm("mcr p15, 0, r1, c7, c5, 0"); /* invalidate I cache */ -#endif - -#if !defined(CONFIG_SYS_DCACHE_OFF) - asm("mcr p15, 0, r1, c7, c14, 0"); /* Clean+invalidate D cache */ -#endif - -#endif /* CONFIG_CPU_ARM1136 */ - -#ifdef CONFIG_CPU_ARM926EJS -#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF)) - asm( - /* test and clean, page 2-23 of arm926ejs manual */ - "0: mrc p15, 0, r15, c7, c10, 3\n\t" "bne 0b\n" - /* flush write buffer as well (page 2-22) */ - "mcr p15, 0, %0, c7, c10, 4" : : "r"(0) : "memory" - ); -#endif -#endif /* CONFIG_CPU_ARM926EJS */ - return; + flush_dcache_range(start, start + size); } /* -- 2.39.2