From c325916563ac67ec5f86748060c2909a9b960bee Mon Sep 17 00:00:00 2001 From: Gabor Juhos Date: Thu, 13 Jun 2013 12:59:34 +0200 Subject: [PATCH] MIPS: mips32/cache.S: save return address in t9 register Synchronize the code with mips64/cache.S, in order to allow further unifications. Signed-off-by: Gabor Juhos Cc: Daniel Schwierzeck --- arch/mips/cpu/mips32/cache.S | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/mips/cpu/mips32/cache.S b/arch/mips/cpu/mips32/cache.S index 40bb46e5b6..fc13d3faab 100644 --- a/arch/mips/cpu/mips32/cache.S +++ b/arch/mips/cpu/mips32/cache.S @@ -18,7 +18,7 @@ #define CONFIG_SYS_MIPS_CACHE_MODE CONF_CM_CACHABLE_NONCOHERENT #endif -#define RA t8 +#define RA t9 /* * 16kB is the maximum size of instruction and data caches on MIPS 4K, -- 2.39.2