From c619a0dd89c609e2d7b0468f7da0728621524473 Mon Sep 17 00:00:00 2001 From: =?utf8?q?Lothar=20Wa=C3=9Fmann?= Date: Thu, 23 Feb 2012 13:42:25 +0100 Subject: [PATCH] applied patches from Freescale and Ka-Ro --- Makefile | 53 +- README.KARO | 38 + board/freescale/mx23_evk/Makefile | 52 + board/freescale/mx23_evk/config.mk | 6 + board/freescale/mx23_evk/lowlevel_init.S | 36 + board/freescale/mx23_evk/mx23_evk.c | 158 + board/freescale/mx23_evk/u-boot.lds | 51 + board/freescale/mx25_3stack/Makefile | 53 + board/freescale/mx25_3stack/config.mk | 3 + board/freescale/mx25_3stack/dcdheader.S | 99 + board/freescale/mx25_3stack/lowlevel_init.S | 97 + board/freescale/mx25_3stack/mx25_3stack.c | 489 + board/freescale/mx25_3stack/u-boot.lds | 62 + board/freescale/mx28_evk/Makefile | 52 + board/freescale/mx28_evk/config.mk | 6 + board/freescale/mx28_evk/lowlevel_init.S | 36 + board/freescale/mx28_evk/mx28_evk.c | 253 + board/freescale/mx28_evk/u-boot.lds | 51 + board/freescale/mx31_3stack/Makefile | 47 + board/freescale/mx31_3stack/config.mk | 3 + board/freescale/mx31_3stack/lowlevel_init.S | 248 + board/freescale/mx31_3stack/mx31_3stack.c | 75 + board/freescale/mx31_3stack/u-boot.lds | 72 + board/freescale/mx35_3stack/Makefile | 50 + .../freescale/mx35_3stack/board-mx35_3stack.h | 107 + board/freescale/mx35_3stack/config.mk | 3 + board/freescale/mx35_3stack/flash_header.S | 108 + board/freescale/mx35_3stack/lowlevel_init.S | 441 + board/freescale/mx35_3stack/mx35_3stack.c | 460 + board/freescale/mx35_3stack/u-boot.lds | 77 + board/freescale/mx50_arm2/Makefile | 49 + board/freescale/mx50_arm2/config.mk | 7 + board/freescale/mx50_arm2/flash_header.S | 791 ++ board/freescale/mx50_arm2/lowlevel_init.S | 207 + board/freescale/mx50_arm2/mx50_arm2.c | 950 ++ board/freescale/mx50_arm2/u-boot.lds | 73 + board/freescale/mx51_3stack/Makefile | 49 + .../freescale/mx51_3stack/board-mx51_3stack.h | 64 + board/freescale/mx51_3stack/config.mk | 3 + board/freescale/mx51_3stack/flash_header.S | 113 + board/freescale/mx51_3stack/lowlevel_init.S | 365 + board/freescale/mx51_3stack/mx51_3stack.c | 1102 ++ board/freescale/mx51_3stack/u-boot.lds | 73 + board/freescale/mx51_bbg/Makefile | 49 + board/freescale/mx51_bbg/board-imx51.h | 64 + board/freescale/mx51_bbg/config.mk | 7 + board/freescale/mx51_bbg/flash_header.S | 112 + board/freescale/mx51_bbg/lowlevel_init.S | 326 + board/freescale/mx51_bbg/mx51_bbg.c | 1145 ++ board/freescale/mx51_bbg/u-boot.lds | 73 + board/freescale/mx53_evk/Makefile | 49 + board/freescale/mx53_evk/config.mk | 3 + board/freescale/mx53_evk/flash_header.S | 250 + board/freescale/mx53_evk/lowlevel_init.S | 219 + board/freescale/mx53_evk/mx53_evk.c | 850 ++ board/freescale/mx53_evk/u-boot.lds | 73 + board/karo/tx28/Makefile | 55 + board/karo/tx28/config.mk | 3 + board/karo/tx28/flash.c | 583 + board/karo/tx28/lowlevel_init.S | 36 + board/karo/tx28/tx28.c | 268 + board/karo/tx28/u-boot.lds | 51 + common/Makefile | 7 + common/cmd_bootce.c | 1305 ++ common/cmd_bootm.c | 7 + common/cmd_clk.c | 90 + common/cmd_iim.c | 95 + common/cmd_mmc.c | 134 +- common/cmd_nvedit.c | 5 +- common/cmd_pata.c | 203 + common/cmd_sata.c | 12 +- common/env_common.c | 6 + common/env_mmc.c | 162 + common/lcd.c | 48 +- common/main.c | 31 +- cpu/arm1136/cpu.c | 79 +- cpu/arm1136/mx31/Makefile | 2 + cpu/arm1136/mx31/generic.c | 1 + cpu/arm1136/mx31/nand_load.S | 160 + cpu/arm1136/mx35/Makefile | 48 + cpu/arm1136/mx35/crm_regs.h | 258 + cpu/arm1136/mx35/generic.c | 388 + cpu/arm1136/mx35/iomux.c | 149 + cpu/arm1136/mx35/mxc_nand_load.S | 261 + cpu/arm1136/mx35/serial.c | 220 + cpu/arm1136/mx35/timer.c | 132 + cpu/arm1136/start.S | 171 +- cpu/arm926ejs/cpu.c | 1 + cpu/arm926ejs/mx23/Makefile | 47 + cpu/arm926ejs/mx23/config.mk | 2 + cpu/arm926ejs/mx23/reset.S | 45 + cpu/arm926ejs/mx23/spi.c | 255 + cpu/arm926ejs/mx23/timer.c | 245 + cpu/arm926ejs/mx25/Makefile | 45 + cpu/arm926ejs/mx25/generic.c | 136 + cpu/arm926ejs/mx25/gpio.c | 113 + cpu/arm926ejs/mx25/iomux.c | 153 + cpu/arm926ejs/mx25/serial.c | 231 + cpu/arm926ejs/mx25/timer.c | 132 + cpu/arm926ejs/mx28/Makefile | 47 + cpu/arm926ejs/mx28/config.mk | 2 + cpu/arm926ejs/mx28/generic.c | 298 + cpu/arm926ejs/mx28/mmcops.c | 555 + cpu/arm926ejs/mx28/pinctrl.c | 141 + cpu/arm926ejs/mx28/reset.S | 44 + cpu/arm926ejs/mx28/serial.c | 107 + cpu/arm926ejs/mx28/timer.c | 234 + cpu/arm926ejs/start.S | 2 +- cpu/arm_cortexa8/Makefile | 2 +- cpu/arm_cortexa8/config.mk | 11 +- cpu/arm_cortexa8/cpu.c | 102 +- cpu/arm_cortexa8/mx50/Makefile | 48 + cpu/arm_cortexa8/mx50/cache.c | 44 + cpu/arm_cortexa8/mx50/crm_regs.h | 646 + cpu/arm_cortexa8/mx50/generic.c | 1013 ++ cpu/arm_cortexa8/mx50/interrupts.c | 39 + cpu/arm_cortexa8/mx50/iomux.c | 137 + cpu/arm_cortexa8/mx50/serial.c | 226 + cpu/arm_cortexa8/mx50/timer.c | 127 + cpu/arm_cortexa8/mx51/Makefile | 51 + cpu/arm_cortexa8/mx51/cache.c | 44 + cpu/arm_cortexa8/mx51/crm_regs.h | 669 + cpu/arm_cortexa8/mx51/generic.c | 279 + cpu/arm_cortexa8/mx51/interrupts.c | 47 + cpu/arm_cortexa8/mx51/iomux.c | 199 + cpu/arm_cortexa8/mx51/mxc_nand_load.S | 167 + cpu/arm_cortexa8/mx51/serial.c | 226 + cpu/arm_cortexa8/mx51/timer.c | 127 + cpu/arm_cortexa8/mx53/Makefile | 48 + cpu/arm_cortexa8/mx53/cache.c | 44 + cpu/arm_cortexa8/mx53/crm_regs.h | 752 ++ cpu/arm_cortexa8/mx53/generic.c | 993 ++ cpu/arm_cortexa8/mx53/interrupts.c | 39 + cpu/arm_cortexa8/mx53/iomux.c | 148 + cpu/arm_cortexa8/mx53/serial.c | 226 + cpu/arm_cortexa8/mx53/timer.c | 127 + cpu/arm_cortexa8/start.S | 4 + disk/part.c | 5 + drivers/block/Makefile | 2 + drivers/block/ahci.c | 5 +- drivers/block/dwc_ahsata.c | 1119 ++ drivers/block/dwc_ahsata.h | 333 + drivers/block/mxc_ata.c | 454 + drivers/block/mxc_ata.h | 90 + drivers/i2c/mxc_i2c.c | 207 +- drivers/input/Makefile | 1 + drivers/input/mxc_keyb.c | 598 + drivers/misc/Makefile | 1 + drivers/misc/imx_iim.c | 343 + drivers/mmc/Makefile | 3 + drivers/mmc/imx_esdhc.c | 505 + drivers/mmc/imx_ssp_mmc.c | 385 + drivers/mmc/mmc.c | 510 +- drivers/mtd/nand/Makefile | 3 + drivers/mtd/nand/mx31_nand.c | 968 ++ drivers/mtd/nand/mxc_nand.c | 1348 ++ drivers/mtd/nand/mxs_gpmi.c | 1613 +++ drivers/mtd/nand/mxs_gpmi.h | 361 + drivers/mtd/nand/nand.c | 2 +- drivers/mtd/nand/nand_base.c | 12 +- drivers/mtd/nand/nand_bbt.c | 363 +- drivers/mtd/nand/nand_device_info.c | 2296 ++++ drivers/mtd/nand/nand_device_info.h | 144 + drivers/mtd/nand/nand_ids.c | 21 +- drivers/mtd/spi/Makefile | 3 + drivers/mtd/spi/imx_spi_nor_atmel.c | 532 + drivers/mtd/spi/imx_spi_nor_sst.c | 564 + drivers/mtd/spi/spi_flash_internal.h | 1 + drivers/net/smc911x.c | 16 +- drivers/net/smc911x.h | 25 +- drivers/serial/Makefile | 2 + drivers/serial/stmp3xxx_dbguart.c | 114 + drivers/serial/stmp3xxx_dbguart.h | 61 + drivers/spi/Makefile | 4 + drivers/spi/imx_cspi.c | 255 + drivers/spi/imx_ecspi.c | 302 + drivers/spi/imx_spi_cpld.c | 118 + drivers/spi/imx_spi_pmic.c | 131 + drivers/video/Makefile | 2 + drivers/video/mx2fb.c | 125 + drivers/video/mxc_epdc_fb.c | 446 + drivers/video/mxc_epdc_fb.h | 299 + fs/ubifs/super.c | 1 + fs/ubifs/ubifs.c | 72 +- fs/ubifs/ubifs.h | 32 - include/ahci.h | 14 +- include/asm-arm/arch-mx23/clkctrl.h | 64 + include/asm-arm/arch-mx23/dbguart.h | 30 + include/asm-arm/arch-mx23/mx23.h | 40 + include/asm-arm/arch-mx23/ocotp.h | 69 + include/asm-arm/arch-mx23/pinmux.h | 42 + include/asm-arm/arch-mx23/spi.h | 69 + include/asm-arm/arch-mx23/ssp.h | 100 + include/asm-arm/arch-mx23/timrot.h | 63 + include/asm-arm/arch-mx25/gpio.h | 33 + include/asm-arm/arch-mx25/imx_spi_cpld.h | 46 + include/asm-arm/arch-mx25/iomux.h | 220 + include/asm-arm/arch-mx25/mx25-regs.h | 380 + include/asm-arm/arch-mx25/mx25.h | 46 + include/asm-arm/arch-mx25/mx25_pins.h | 259 + include/asm-arm/arch-mx25/mxc_nand.h | 228 + include/asm-arm/arch-mx28/mx28.h | 131 + include/asm-arm/arch-mx28/mxs_gpmi-bch-regs.h | 310 + include/asm-arm/arch-mx28/mxs_gpmi-regs.h | 456 + include/asm-arm/arch-mx28/pinctrl.h | 222 + include/asm-arm/arch-mx28/regs-clkctrl.h | 635 + include/asm-arm/arch-mx28/regs-enet.h | 3562 ++++++ include/asm-arm/arch-mx28/regs-ocotp.h | 239 + include/asm-arm/arch-mx28/regs-pinctrl.h | 2674 ++++ include/asm-arm/arch-mx28/regs-ssp.h | 471 + include/asm-arm/arch-mx28/regs-timrot.h | 293 + include/asm-arm/arch-mx28/regs-uartdbg.h | 301 + include/asm-arm/arch-mx31/mx31-regs.h | 97 + include/asm-arm/arch-mx35/iomux.h | 290 + include/asm-arm/arch-mx35/mmu.h | 172 + include/asm-arm/arch-mx35/mx35.h | 297 + include/asm-arm/arch-mx35/mx35_pins.h | 342 + include/asm-arm/arch-mx35/mxc_nand.h | 228 + include/asm-arm/arch-mx50/imx_spi_pmic.h | 33 + include/asm-arm/arch-mx50/iomux.h | 230 + include/asm-arm/arch-mx50/mmu.h | 174 + include/asm-arm/arch-mx50/mx50.h | 331 + include/asm-arm/arch-mx50/mx50_pins.h | 285 + include/asm-arm/arch-mx51/imx_spi_pmic.h | 33 + include/asm-arm/arch-mx51/iomux.h | 240 + include/asm-arm/arch-mx51/keypad.h | 65 + include/asm-arm/arch-mx51/mmu.h | 215 + include/asm-arm/arch-mx51/mx51.h | 493 + include/asm-arm/arch-mx51/mx51_pins.h | 370 + include/asm-arm/arch-mx51/mxc_nand.h | 391 + include/asm-arm/arch-mx53/iomux.h | 249 + include/asm-arm/arch-mx53/mmu.h | 174 + include/asm-arm/arch-mx53/mx53.h | 438 + include/asm-arm/arch-mx53/mx53_pins.h | 374 + include/asm-arm/bitops.h | 81 +- .../asm-arm/cache-cp15.h | 104 +- include/asm-arm/clock.h | 44 + include/asm-arm/dma-mapping.h | 1 + include/asm-arm/fec.h | 284 + include/asm-arm/imx_iim.h | 71 + include/asm-arm/io.h | 12 +- include/asm-arm/mach-types.h | 10251 +++++++++++++++- include/asm-arm/mmu.h | 118 + include/asm-arm/proc-armv/system.h | 30 - include/configs/mx23_evk.h | 154 + include/configs/mx25_3stack.h | 282 + include/configs/mx25_3stack_mfg.h | 262 + include/configs/mx28_evk.h | 160 + include/configs/mx31_3stack.h | 163 + include/configs/mx35_3stack.h | 253 + include/configs/mx35_3stack_mfg.h | 255 + include/configs/mx35_3stack_mmc.h | 273 + include/configs/mx50_arm2.h | 284 + include/configs/mx50_arm2_iram.h | 194 + include/configs/mx50_arm2_lpddr2.h | 286 + include/configs/mx50_arm2_mfg.h | 253 + include/configs/mx51_3stack.h | 267 + include/configs/mx51_3stack_android.h | 322 + include/configs/mx51_bbg.h | 274 + include/configs/mx51_bbg_android.h | 326 + include/configs/mx51_bbg_mfg.h | 235 + include/configs/mx53_arm2.h | 274 + include/configs/mx53_arm2_ddr3.h | 256 + include/configs/mx53_evk.h | 273 + include/configs/mx53_evk_mfg.h | 217 + include/configs/triton320.h | 266 + include/configs/tx28.h | 218 + include/environment.h | 23 + include/fsl_esdhc.h | 29 +- include/imx_spi.h | 96 + include/imx_spi_nor.h | 70 + include/imx_ssp_mmc.h | 50 + include/lcd.h | 61 + include/linux/bitops.h | 83 + include/linux/mtd/bbm.h | 93 +- include/linux/mtd/nand.h | 13 +- include/mmc.h | 39 +- include/mx2fb.h | 47 + include/mxc_keyb.h | 201 + include/nand.h | 2 +- include/net.h | 1 + include/pata.h | 35 + include/wince.h | 450 + lib_arm/Makefile | 3 - lib_arm/board.c | 206 +- lib_arm/eabi_compat.c | 5 + lib_generic/vsprintf.c | 25 +- net/eth.c | 25 +- post/board/netta/dsp.c | 2 + tools/Makefile | 5 + 290 files changed, 73595 insertions(+), 769 deletions(-) create mode 100644 README.KARO create mode 100644 board/freescale/mx23_evk/Makefile create mode 100644 board/freescale/mx23_evk/config.mk create mode 100644 board/freescale/mx23_evk/lowlevel_init.S create mode 100644 board/freescale/mx23_evk/mx23_evk.c create mode 100644 board/freescale/mx23_evk/u-boot.lds create mode 100644 board/freescale/mx25_3stack/Makefile create mode 100644 board/freescale/mx25_3stack/config.mk create mode 100644 board/freescale/mx25_3stack/dcdheader.S create mode 100644 board/freescale/mx25_3stack/lowlevel_init.S create mode 100644 board/freescale/mx25_3stack/mx25_3stack.c create mode 100644 board/freescale/mx25_3stack/u-boot.lds create mode 100644 board/freescale/mx28_evk/Makefile create mode 100644 board/freescale/mx28_evk/config.mk create mode 100644 board/freescale/mx28_evk/lowlevel_init.S create mode 100644 board/freescale/mx28_evk/mx28_evk.c create mode 100644 board/freescale/mx28_evk/u-boot.lds create mode 100644 board/freescale/mx31_3stack/Makefile create mode 100644 board/freescale/mx31_3stack/config.mk create mode 100644 board/freescale/mx31_3stack/lowlevel_init.S create mode 100644 board/freescale/mx31_3stack/mx31_3stack.c create mode 100644 board/freescale/mx31_3stack/u-boot.lds create mode 100644 board/freescale/mx35_3stack/Makefile create mode 100644 board/freescale/mx35_3stack/board-mx35_3stack.h create mode 100644 board/freescale/mx35_3stack/config.mk create mode 100644 board/freescale/mx35_3stack/flash_header.S create mode 100644 board/freescale/mx35_3stack/lowlevel_init.S create mode 100644 board/freescale/mx35_3stack/mx35_3stack.c create mode 100644 board/freescale/mx35_3stack/u-boot.lds create mode 100644 board/freescale/mx50_arm2/Makefile create mode 100644 board/freescale/mx50_arm2/config.mk create mode 100644 board/freescale/mx50_arm2/flash_header.S create mode 100644 board/freescale/mx50_arm2/lowlevel_init.S create mode 100644 board/freescale/mx50_arm2/mx50_arm2.c create mode 100644 board/freescale/mx50_arm2/u-boot.lds create mode 100644 board/freescale/mx51_3stack/Makefile create mode 100644 board/freescale/mx51_3stack/board-mx51_3stack.h create mode 100644 board/freescale/mx51_3stack/config.mk create mode 100644 board/freescale/mx51_3stack/flash_header.S create mode 100644 board/freescale/mx51_3stack/lowlevel_init.S create mode 100644 board/freescale/mx51_3stack/mx51_3stack.c create mode 100644 board/freescale/mx51_3stack/u-boot.lds create mode 100644 board/freescale/mx51_bbg/Makefile create mode 100644 board/freescale/mx51_bbg/board-imx51.h create mode 100644 board/freescale/mx51_bbg/config.mk create mode 100644 board/freescale/mx51_bbg/flash_header.S create mode 100644 board/freescale/mx51_bbg/lowlevel_init.S create mode 100644 board/freescale/mx51_bbg/mx51_bbg.c create mode 100644 board/freescale/mx51_bbg/u-boot.lds create mode 100644 board/freescale/mx53_evk/Makefile create mode 100644 board/freescale/mx53_evk/config.mk create mode 100644 board/freescale/mx53_evk/flash_header.S create mode 100644 board/freescale/mx53_evk/lowlevel_init.S create mode 100644 board/freescale/mx53_evk/mx53_evk.c create mode 100644 board/freescale/mx53_evk/u-boot.lds create mode 100644 board/karo/tx28/Makefile create mode 100644 board/karo/tx28/config.mk create mode 100644 board/karo/tx28/flash.c create mode 100644 board/karo/tx28/lowlevel_init.S create mode 100644 board/karo/tx28/tx28.c create mode 100644 board/karo/tx28/u-boot.lds create mode 100644 common/cmd_bootce.c create mode 100644 common/cmd_clk.c create mode 100644 common/cmd_iim.c create mode 100644 common/cmd_pata.c create mode 100644 common/env_mmc.c create mode 100644 cpu/arm1136/mx31/nand_load.S create mode 100644 cpu/arm1136/mx35/Makefile create mode 100644 cpu/arm1136/mx35/crm_regs.h create mode 100644 cpu/arm1136/mx35/generic.c create mode 100644 cpu/arm1136/mx35/iomux.c create mode 100644 cpu/arm1136/mx35/mxc_nand_load.S create mode 100644 cpu/arm1136/mx35/serial.c create mode 100644 cpu/arm1136/mx35/timer.c create mode 100644 cpu/arm926ejs/mx23/Makefile create mode 100644 cpu/arm926ejs/mx23/config.mk create mode 100644 cpu/arm926ejs/mx23/reset.S create mode 100644 cpu/arm926ejs/mx23/spi.c create mode 100644 cpu/arm926ejs/mx23/timer.c create mode 100644 cpu/arm926ejs/mx25/Makefile create mode 100644 cpu/arm926ejs/mx25/generic.c create mode 100644 cpu/arm926ejs/mx25/gpio.c create mode 100644 cpu/arm926ejs/mx25/iomux.c create mode 100644 cpu/arm926ejs/mx25/serial.c create mode 100644 cpu/arm926ejs/mx25/timer.c create mode 100644 cpu/arm926ejs/mx28/Makefile create mode 100644 cpu/arm926ejs/mx28/config.mk create mode 100644 cpu/arm926ejs/mx28/generic.c create mode 100644 cpu/arm926ejs/mx28/mmcops.c create mode 100644 cpu/arm926ejs/mx28/pinctrl.c create mode 100644 cpu/arm926ejs/mx28/reset.S create mode 100644 cpu/arm926ejs/mx28/serial.c create mode 100644 cpu/arm926ejs/mx28/timer.c create mode 100644 cpu/arm_cortexa8/mx50/Makefile create mode 100644 cpu/arm_cortexa8/mx50/cache.c create mode 100644 cpu/arm_cortexa8/mx50/crm_regs.h create mode 100644 cpu/arm_cortexa8/mx50/generic.c create mode 100644 cpu/arm_cortexa8/mx50/interrupts.c create mode 100644 cpu/arm_cortexa8/mx50/iomux.c create mode 100644 cpu/arm_cortexa8/mx50/serial.c create mode 100644 cpu/arm_cortexa8/mx50/timer.c create mode 100644 cpu/arm_cortexa8/mx51/Makefile create mode 100644 cpu/arm_cortexa8/mx51/cache.c create mode 100644 cpu/arm_cortexa8/mx51/crm_regs.h create mode 100644 cpu/arm_cortexa8/mx51/generic.c create mode 100644 cpu/arm_cortexa8/mx51/interrupts.c create mode 100644 cpu/arm_cortexa8/mx51/iomux.c create mode 100644 cpu/arm_cortexa8/mx51/mxc_nand_load.S create mode 100644 cpu/arm_cortexa8/mx51/serial.c create mode 100644 cpu/arm_cortexa8/mx51/timer.c create mode 100644 cpu/arm_cortexa8/mx53/Makefile create mode 100644 cpu/arm_cortexa8/mx53/cache.c create mode 100644 cpu/arm_cortexa8/mx53/crm_regs.h create mode 100644 cpu/arm_cortexa8/mx53/generic.c create mode 100644 cpu/arm_cortexa8/mx53/interrupts.c create mode 100644 cpu/arm_cortexa8/mx53/iomux.c create mode 100644 cpu/arm_cortexa8/mx53/serial.c create mode 100644 cpu/arm_cortexa8/mx53/timer.c create mode 100644 drivers/block/dwc_ahsata.c create mode 100644 drivers/block/dwc_ahsata.h create mode 100644 drivers/block/mxc_ata.c create mode 100644 drivers/block/mxc_ata.h create mode 100644 drivers/input/mxc_keyb.c create mode 100644 drivers/misc/imx_iim.c create mode 100644 drivers/mmc/imx_esdhc.c create mode 100644 drivers/mmc/imx_ssp_mmc.c create mode 100644 drivers/mtd/nand/mx31_nand.c create mode 100644 drivers/mtd/nand/mxc_nand.c create mode 100644 drivers/mtd/nand/mxs_gpmi.c create mode 100644 drivers/mtd/nand/mxs_gpmi.h create mode 100644 drivers/mtd/nand/nand_device_info.c create mode 100644 drivers/mtd/nand/nand_device_info.h create mode 100644 drivers/mtd/spi/imx_spi_nor_atmel.c create mode 100644 drivers/mtd/spi/imx_spi_nor_sst.c create mode 100644 drivers/serial/stmp3xxx_dbguart.c create mode 100644 drivers/serial/stmp3xxx_dbguart.h create mode 100644 drivers/spi/imx_cspi.c create mode 100644 drivers/spi/imx_ecspi.c create mode 100644 drivers/spi/imx_spi_cpld.c create mode 100644 drivers/spi/imx_spi_pmic.c create mode 100644 drivers/video/mx2fb.c create mode 100644 drivers/video/mxc_epdc_fb.c create mode 100644 drivers/video/mxc_epdc_fb.h create mode 100644 include/asm-arm/arch-mx23/clkctrl.h create mode 100644 include/asm-arm/arch-mx23/dbguart.h create mode 100644 include/asm-arm/arch-mx23/mx23.h create mode 100644 include/asm-arm/arch-mx23/ocotp.h create mode 100644 include/asm-arm/arch-mx23/pinmux.h create mode 100644 include/asm-arm/arch-mx23/spi.h create mode 100644 include/asm-arm/arch-mx23/ssp.h create mode 100644 include/asm-arm/arch-mx23/timrot.h create mode 100644 include/asm-arm/arch-mx25/gpio.h create mode 100644 include/asm-arm/arch-mx25/imx_spi_cpld.h create mode 100644 include/asm-arm/arch-mx25/iomux.h create mode 100644 include/asm-arm/arch-mx25/mx25-regs.h create mode 100644 include/asm-arm/arch-mx25/mx25.h create mode 100644 include/asm-arm/arch-mx25/mx25_pins.h create mode 100644 include/asm-arm/arch-mx25/mxc_nand.h create mode 100644 include/asm-arm/arch-mx28/mx28.h create mode 100644 include/asm-arm/arch-mx28/mxs_gpmi-bch-regs.h create mode 100644 include/asm-arm/arch-mx28/mxs_gpmi-regs.h create mode 100644 include/asm-arm/arch-mx28/pinctrl.h create mode 100644 include/asm-arm/arch-mx28/regs-clkctrl.h create mode 100644 include/asm-arm/arch-mx28/regs-enet.h create mode 100644 include/asm-arm/arch-mx28/regs-ocotp.h create mode 100644 include/asm-arm/arch-mx28/regs-pinctrl.h create mode 100644 include/asm-arm/arch-mx28/regs-ssp.h create mode 100644 include/asm-arm/arch-mx28/regs-timrot.h create mode 100644 include/asm-arm/arch-mx28/regs-uartdbg.h create mode 100644 include/asm-arm/arch-mx35/iomux.h create mode 100644 include/asm-arm/arch-mx35/mmu.h create mode 100644 include/asm-arm/arch-mx35/mx35.h create mode 100644 include/asm-arm/arch-mx35/mx35_pins.h create mode 100644 include/asm-arm/arch-mx35/mxc_nand.h create mode 100644 include/asm-arm/arch-mx50/imx_spi_pmic.h create mode 100644 include/asm-arm/arch-mx50/iomux.h create mode 100644 include/asm-arm/arch-mx50/mmu.h create mode 100644 include/asm-arm/arch-mx50/mx50.h create mode 100644 include/asm-arm/arch-mx50/mx50_pins.h create mode 100644 include/asm-arm/arch-mx51/imx_spi_pmic.h create mode 100644 include/asm-arm/arch-mx51/iomux.h create mode 100644 include/asm-arm/arch-mx51/keypad.h create mode 100644 include/asm-arm/arch-mx51/mmu.h create mode 100644 include/asm-arm/arch-mx51/mx51.h create mode 100644 include/asm-arm/arch-mx51/mx51_pins.h create mode 100644 include/asm-arm/arch-mx51/mxc_nand.h create mode 100644 include/asm-arm/arch-mx53/iomux.h create mode 100644 include/asm-arm/arch-mx53/mmu.h create mode 100644 include/asm-arm/arch-mx53/mx53.h create mode 100644 include/asm-arm/arch-mx53/mx53_pins.h rename lib_arm/cache-cp15.c => include/asm-arm/cache-cp15.h (57%) create mode 100644 include/asm-arm/clock.h create mode 100644 include/asm-arm/fec.h create mode 100644 include/asm-arm/imx_iim.h create mode 100644 include/asm-arm/mmu.h create mode 100644 include/configs/mx23_evk.h create mode 100644 include/configs/mx25_3stack.h create mode 100644 include/configs/mx25_3stack_mfg.h create mode 100644 include/configs/mx28_evk.h create mode 100644 include/configs/mx31_3stack.h create mode 100644 include/configs/mx35_3stack.h create mode 100644 include/configs/mx35_3stack_mfg.h create mode 100644 include/configs/mx35_3stack_mmc.h create mode 100644 include/configs/mx50_arm2.h create mode 100644 include/configs/mx50_arm2_iram.h create mode 100644 include/configs/mx50_arm2_lpddr2.h create mode 100644 include/configs/mx50_arm2_mfg.h create mode 100644 include/configs/mx51_3stack.h create mode 100644 include/configs/mx51_3stack_android.h create mode 100644 include/configs/mx51_bbg.h create mode 100644 include/configs/mx51_bbg_android.h create mode 100644 include/configs/mx51_bbg_mfg.h create mode 100644 include/configs/mx53_arm2.h create mode 100644 include/configs/mx53_arm2_ddr3.h create mode 100644 include/configs/mx53_evk.h create mode 100644 include/configs/mx53_evk_mfg.h create mode 100644 include/configs/triton320.h create mode 100644 include/configs/tx28.h create mode 100644 include/imx_spi.h create mode 100644 include/imx_spi_nor.h create mode 100644 include/imx_ssp_mmc.h create mode 100644 include/mx2fb.h create mode 100644 include/mxc_keyb.h create mode 100644 include/pata.h create mode 100644 include/wince.h diff --git a/Makefile b/Makefile index e4499d707c..db708fd4f9 100644 --- a/Makefile +++ b/Makefile @@ -30,8 +30,6 @@ U_BOOT_VERSION = $(VERSION).$(PATCHLEVEL).$(SUBLEVEL)$(EXTRAVERSION) else U_BOOT_VERSION = $(VERSION).$(PATCHLEVEL)$(EXTRAVERSION) endif -TIMESTAMP_FILE = $(obj)include/timestamp_autogenerated.h -VERSION_FILE = $(obj)include/version_autogenerated.h HOSTARCH := $(shell uname -m | \ sed -e s/i.86/i386/ \ @@ -128,6 +126,9 @@ src := endif export obj src +TIMESTAMP_FILE = $(obj)include/timestamp_autogenerated.h +VERSION_FILE = $(obj)include/version_autogenerated.h + # Make sure CDPATH settings don't interfere unexport CDPATH @@ -3204,13 +3205,26 @@ apollon_config : unconfig @$(MKCONFIG) $(@:_config=) arm arm1136 apollon NULL omap24xx @echo "CONFIG_ONENAND_U_BOOT = y" >> $(obj)include/config.mk +mx23_evk_config : unconfig + @$(MKCONFIG) $(@:_config=) arm arm926ejs mx23_evk freescale mx23 + +mx25_3stack_mfg_config \ +mx25_3stack_config : unconfig + @$(MKCONFIG) $(@:_config=) arm arm926ejs mx25_3stack freescale mx25 + +mx28_evk_config : unconfig + @$(MKCONFIG) $(@:_config=) arm arm926ejs mx28_evk freescale mx28 + +tx28_config : unconfig + @$(MKCONFIG) $(@:_config=) arm arm926ejs tx28 karo mx28 + imx31_litekit_config : unconfig @$(MKCONFIG) $(@:_config=) arm arm1136 imx31_litekit NULL mx31 imx31_phycore_eet_config \ imx31_phycore_config : unconfig @mkdir -p $(obj)include - @if [ -n "$(findstring _eet_,$@)" ]; then \ + @if [ -n "$(findstring _eet_,$@)" ]; then \ echo "#define CONFIG_IMX31_PHYCORE_EET" >> $(obj)include/config.h; \ fi @$(MKCONFIG) -a imx31_phycore arm arm1136 imx31_phycore NULL mx31 @@ -3229,6 +3243,39 @@ mx31pdk_nand_config : unconfig fi @$(MKCONFIG) -a mx31pdk arm arm1136 mx31pdk freescale mx31 +mx31_3stack_config : unconfig + @$(MKCONFIG) $(@:_config=) arm arm1136 mx31_3stack freescale mx31 + +mx35_3stack_config \ +mx35_3stack_mfg_config \ +mx35_3stack_mmc_config: unconfig + @$(MKCONFIG) $(@:_config=) arm arm1136 mx35_3stack freescale mx35 + +mx50_arm2_lpddr2_config \ +mx50_arm2_iram_config \ +mx50_arm2_config \ +mx50_arm2_mfg_config : unconfig + @[ -z "$(findstring iram_,$@)" ] || \ + { echo "TEXT_BASE = 0xF8008400" >$(obj)board/freescale/mx50_arm2/config.tmp ; \ + echo "... with iram configuration" ; \ + } + @$(MKCONFIG) $(@:_config=) arm arm_cortexa8 mx50_arm2 freescale mx50 + +mx51_bbg_android_config \ +mx51_bbg_mfg_config \ +mx51_bbg_config : unconfig + @$(MKCONFIG) $(@:_config=) arm arm_cortexa8 mx51_bbg freescale mx51 + +mx51_3stack_android_config \ +mx51_3stack_config : unconfig + @$(MKCONFIG) $(@:_config=) arm arm_cortexa8 mx51_3stack freescale mx51 + +mx53_evk_mfg_config \ +mx53_arm2_ddr3_config \ +mx53_arm2_config \ +mx53_evk_config : unconfig + @$(MKCONFIG) $(@:_config=) arm arm_cortexa8 mx53_evk freescale mx53 + omap2420h4_config : unconfig @$(MKCONFIG) $(@:_config=) arm arm1136 omap2420h4 NULL omap24xx diff --git a/README.KARO b/README.KARO new file mode 100644 index 0000000000..20fc3a6193 --- /dev/null +++ b/README.KARO @@ -0,0 +1,38 @@ + Building U-Boot for TX28 + ======================== + +Unpacking the source +-------------------- +mkdir u-boot +cd u-boot +tar -xzf /cdrom/U-Boot/u-boot-src.tar.bz2 +sudo tar -C / -xzf /cdrom/Tools/Linux/elftosb.tgz + +Compiling U-Boot +---------------- +cd u-boot-2009.08 +export ARCH=arm +export CROSS_COMPILE=arm-926ejs-linux-gnueabi- +make tx28_config +make u-boot_ivt.sb + + +Flashing U-Boot Image +--------------------- +Load the U-Boot image with sbloader (either the Windows version or the +Linux version) and use the builtin 'romupdate' command to program the +image into the flash. + +Put the u-boot_ivt.sb file in the TFTP server data directory (usually +/tftpboot). + +Load the U-Boot image: +Enter the following commands at the U-Boot prompt +set autostart no +set autoload yes +set bootfile u-boot_ivt.sb +bootp +romupdate + +Power down the module, make sure the BOOT_MODE jumper (ST3) is removed +and re-apply power to start from flash. diff --git a/board/freescale/mx23_evk/Makefile b/board/freescale/mx23_evk/Makefile new file mode 100644 index 0000000000..010bbee886 --- /dev/null +++ b/board/freescale/mx23_evk/Makefile @@ -0,0 +1,52 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := mx23_evk.o +SOBJS := lowlevel_init.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### + diff --git a/board/freescale/mx23_evk/config.mk b/board/freescale/mx23_evk/config.mk new file mode 100644 index 0000000000..7b57ec37ad --- /dev/null +++ b/board/freescale/mx23_evk/config.mk @@ -0,0 +1,6 @@ +# +# image should be loaded at 0x41008000 +# +LDSCRIPT := $(SRCTREE)/board/$(VENDOR)/$(BOARD)/u-boot.lds + +TEXT_BASE = 0x41008000 diff --git a/board/freescale/mx23_evk/lowlevel_init.S b/board/freescale/mx23_evk/lowlevel_init.S new file mode 100644 index 0000000000..7e7811aa6c --- /dev/null +++ b/board/freescale/mx23_evk/lowlevel_init.S @@ -0,0 +1,36 @@ +/* + * Board specific setup info + * + * (C) Copyright 2009-2010 Freescale Semiconductor, Inc. + * + * (C) Copyright 2003, ARM Ltd. + * Philippe Robin, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +/* Set up the platform, once the cpu has been initialized */ +.globl lowlevel_init +lowlevel_init: + + /* All SDRAM settings are done by sdram_prep */ + mov pc, lr diff --git a/board/freescale/mx23_evk/mx23_evk.c b/board/freescale/mx23_evk/mx23_evk.c new file mode 100644 index 0000000000..343c6d6d1b --- /dev/null +++ b/board/freescale/mx23_evk/mx23_evk.c @@ -0,0 +1,158 @@ +/* + * + * (c) 2008 Embedded Alley Solutions, Inc. + * + * (C) Copyright 2009-2010 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define KHz 1000 +#define MHz (1000 * KHz) + +static void set_pinmux(void) +{ + +#if defined(CONFIG_SPI_SSP1) + + /* Configure SSP1 pins for ENC28j60: 8maA */ + REG_CLR(PINCTRL_BASE + PINCTRL_MUXSEL(4), 0x00003fff); + + REG_CLR(PINCTRL_BASE + PINCTRL_DRIVE(8), 0X03333333); + REG_SET(PINCTRL_BASE + PINCTRL_DRIVE(8), 0x01111111); + + REG_CLR(PINCTRL_BASE + PINCTRL_PULL(2), 0x0000003f); +#endif + +#if defined(CONFIG_SPI_SSP2) + + /* Configure SSP2 pins for ENC28j60: 8maA */ + REG_CLR(PINCTRL_BASE + PINCTRL_MUXSEL(0), 0x00000fc3); + REG_SET(PINCTRL_BASE + PINCTRL_MUXSEL(0), 0x00000a82); + + REG_CLR(PINCTRL_BASE + PINCTRL_MUXSEL(1), 0x00030300); + REG_SET(PINCTRL_BASE + PINCTRL_MUXSEL(1), 0x00020200); + + REG_CLR(PINCTRL_BASE + PINCTRL_DRIVE(0), 0X00333003); + REG_SET(PINCTRL_BASE + PINCTRL_DRIVE(0), 0x00111001); + + REG_CLR(PINCTRL_BASE + PINCTRL_DRIVE(2), 0x00030000); + REG_SET(PINCTRL_BASE + PINCTRL_DRIVE(2), 0x00010000); + + REG_CLR(PINCTRL_BASE + PINCTRL_DRIVE(3), 0x00000003); + REG_SET(PINCTRL_BASE + PINCTRL_DRIVE(3), 0x00000001); + + REG_CLR(PINCTRL_BASE + PINCTRL_PULL(0), 0x00100039); +#endif + +} + +#define IO_DIVIDER 18 +static void set_clocks(void) +{ + u32 ssp_source_clk, ssp_clk; + u32 ssp_div = 1; + u32 val = 0; + + /* + * Configure 480Mhz IO clock + */ + + /* Ungate IO_CLK and set divider */ + REG_CLR(CLKCTRL_BASE + CLKCTRL_FRAC, FRAC_CLKGATEIO); + REG_CLR(CLKCTRL_BASE + CLKCTRL_FRAC, 0x3f << FRAC_IOFRAC); + REG_SET(CLKCTRL_BASE + CLKCTRL_FRAC, IO_DIVIDER << FRAC_IOFRAC); + + /* + * Set SSP CLK to desired value + */ + + /* Calculate SSP_CLK divider relatively to 480Mhz IO_CLK*/ + ssp_source_clk = 480 * MHz; + ssp_clk = CONFIG_SSP_CLK; + ssp_div = (ssp_source_clk + ssp_clk - 1) / ssp_clk; + + /* Enable SSP clock */ + val = REG_RD(CLKCTRL_BASE + CLKCTRL_SSP); + val &= ~SSP_CLKGATE; + REG_WR(CLKCTRL_BASE + CLKCTRL_SSP, val); + + /* Wait while clock is gated */ + while (REG_RD(CLKCTRL_BASE + CLKCTRL_SSP) & SSP_CLKGATE) + ; + + /* Set SSP clock divider */ + val &= ~(0x1ff << SSP_DIV); + val |= ssp_div << SSP_DIV; + REG_WR(CLKCTRL_BASE + CLKCTRL_SSP, val); + + /* Wait until new divider value is set */ + while (REG_RD(CLKCTRL_BASE + CLKCTRL_SSP) & SSP_BUSY) + ; + + /* Set SSP clock source to IO_CLK */ + REG_SET(CLKCTRL_BASE + CLKCTRL_CLKSEQ, CLKSEQ_BYPASS_SSP); + REG_CLR(CLKCTRL_BASE + CLKCTRL_CLKSEQ, CLKSEQ_BYPASS_SSP); +} + +int dram_init(void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + + return 0; +} + +int board_init(void) +{ + /* arch number of Freescale STMP 378x development board */ + gd->bd->bi_arch_number = MACH_TYPE_MX23EVK; + + /* adress of boot parameters */ + gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR; + + set_clocks(); + + set_pinmux(); + + /* Configure SPI on SSP1 or SSP2 */ + spi_init(); + + return 0; +} + +int misc_init_r(void) +{ + return 0; +} + +int checkboard(void) +{ + printf("Board: MX23 EVK. \n"); + return 0; +} diff --git a/board/freescale/mx23_evk/u-boot.lds b/board/freescale/mx23_evk/u-boot.lds new file mode 100644 index 0000000000..82cb8e311a --- /dev/null +++ b/board/freescale/mx23_evk/u-boot.lds @@ -0,0 +1,51 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + . = ALIGN(4); + .text : + { + cpu/arm926ejs/start.o (.text) + *(.text) + } + .rodata : { *(.rodata) } + . = ALIGN(4); + .data : { *(.data) } + . = ALIGN(4); + .got : { *(.got) } + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss (NOLOAD) : { *(.bss) } + _end = .; +} diff --git a/board/freescale/mx25_3stack/Makefile b/board/freescale/mx25_3stack/Makefile new file mode 100644 index 0000000000..ac308fed62 --- /dev/null +++ b/board/freescale/mx25_3stack/Makefile @@ -0,0 +1,53 @@ +# +# (c) Copyright 2009 Freescale Semiconductor +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := mx25_3stack.o +SOBJS := lowlevel_init.o dcdheader.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/freescale/mx25_3stack/config.mk b/board/freescale/mx25_3stack/config.mk new file mode 100644 index 0000000000..083613a245 --- /dev/null +++ b/board/freescale/mx25_3stack/config.mk @@ -0,0 +1,3 @@ +LDSCRIPT := $(SRCTREE)/board/$(VENDOR)/$(BOARD)/u-boot.lds + +TEXT_BASE = 0x83F00000 diff --git a/board/freescale/mx25_3stack/dcdheader.S b/board/freescale/mx25_3stack/dcdheader.S new file mode 100644 index 0000000000..2bd61ed434 --- /dev/null +++ b/board/freescale/mx25_3stack/dcdheader.S @@ -0,0 +1,99 @@ +/* + * Copyright (c) 2009 Freescale Semiconductor + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +#include +#include + +.extern reset + +#define DCDGEN(i,type, addr, data) \ +dcd_##i: ;\ + .long type ;\ + .long addr ;\ + .long data + +.globl _initheader +_initheader: + b reset + .org 0x400 +app_code_jump_v: .long reset +app_code_barker: .long 0xB1 +app_code_csf: .long 0 +hwcfg_ptr_ptr: .long hwcfg_ptr +super_root_key: .long 0 +hwcfg_ptr: .long dcd_data +app_dest_ptr: .long TEXT_BASE +dcd_data: .long 0xB17219E9 + +#ifdef MXC_MEMORY_MDDR +dcd_len: .long 12*15 +#else +dcd_len: .long 12*24 +#endif + +/* WEIM config-CS5 init -- CPLD */ +DCDGEN( 1, 4, 0xB8002050, 0x0000D843) /* CS5_CSCRU */ +DCDGEN( 2, 4, 0xB8002054, 0x22252521) /* CS5_CSCRL */ +DCDGEN( 3, 4, 0xB8002058, 0x22220A00) /* CS5_CSCRA */ +#ifdef MXC_MEMORY_MDDR +/* MDDR init */ +DCDGEN( 4, 4, 0xB8001010, 0x00000004) /* enable mDDR */ +DCDGEN( 5, 4, 0xB8001000, 0x92100000) /* precharge command */ +DCDGEN( 6, 1, 0x80000400, 0x12344321) /* precharge all dummy write */ +DCDGEN( 7, 4, 0xB8001000, 0xA2100000) /* auto-refresh command */ +DCDGEN( 8, 4, 0x80000000, 0x12344321) /* dummy write for refresh */ +DCDGEN( 9, 4, 0x80000000, 0x12344321) /* dummy write for refresh */ +DCDGEN(10, 4, 0xB8001000, 0xB2100000) /* Load Mode Reg command - cas=3 bl=8 */ +DCDGEN(11, 1, 0x80000033, 0xda) /* dummy write -- address has the mode bits */ +DCDGEN(12, 1, 0x81000000, 0xff) /* dummy write -- address has the mode bits */ +DCDGEN(13, 4, 0xB8001000, 0x82216880) +DCDGEN(14, 4, 0xB8001004, 0x00295729) +#else +/* DDR2 init */ +DCDGEN( 4, 4, 0xB8001004, 0x0076E83A) /* initial value for ESDCFG0 */ +DCDGEN( 5, 4, 0xB8001010, 0x00000204) /* ESD_MISC */ +DCDGEN( 6, 4, 0xB8001000, 0x92210000) /* CS0 precharge command */ +DCDGEN( 7, 4, 0x80000f00, 0x12344321) /* precharge all dummy write */ +DCDGEN( 8, 4, 0xB8001000, 0xB2210000) /* Load Mode Register command */ +DCDGEN( 9, 1, 0x82000000, 0xda) /* dummy write Load EMR2 */ +DCDGEN(10, 1, 0x83000000, 0xda) /* dummy write Load EMR3 */ +DCDGEN(11, 1, 0x81000400, 0xda) /* dummy write Load EMR1; enable DLL */ +DCDGEN(12, 1, 0x80000333, 0xda) /* dummy write Load MR; reset DLL */ + +DCDGEN(13, 4, 0xB8001000, 0x92210000) /* CS0 precharge command */ +DCDGEN(14, 1, 0x80000400, 0x12345678) /* precharge all dummy write */ + +DCDGEN(15, 4, 0xB8001000, 0xA2210000) /* select manual refresh mode */ +DCDGEN(16, 4, 0x80000000, 0x87654321) /* manual refresh */ +DCDGEN(17, 4, 0x80000000, 0x87654321) /* manual refresh twice */ + +DCDGEN(18, 4, 0xB8001000, 0xB2210000) /* Load Mode Register command */ +DCDGEN(19, 1, 0x80000233, 0xda) /* Load MR; CL=3, BL=8, end DLL reset */ +DCDGEN(20, 1, 0x81000780, 0xda) /* Load EMR1; OCD default */ +DCDGEN(21, 1, 0x81000400, 0xda) /* Load EMR1; OCD exit */ +DCDGEN(22, 4, 0xB8001000, 0x82216080) /* normal mode */ +DCDGEN(23, 4, 0x43FAC454, 0x00001000) /* IOMUXC_SW_PAD_CTL_GRP_DDRTYPE(1-5) */ +#endif + +DCDGEN(99, 4, 0x53F80008, 0x20034000) /* CLKCTL ARM=400 AHB=133 */ +card_cfg: .long UBOOT_IMAGE_SIZE diff --git a/board/freescale/mx25_3stack/lowlevel_init.S b/board/freescale/mx25_3stack/lowlevel_init.S new file mode 100644 index 0000000000..69e8b84fdd --- /dev/null +++ b/board/freescale/mx25_3stack/lowlevel_init.S @@ -0,0 +1,97 @@ +/* + * Copyright (c) 2009 Freescale Semiconductor + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +.macro REG reg, val + ldr r2, =\reg + ldr r3, =\val + str r3, [r2] +.endm + +.macro REG8 reg, val + ldr r2, =\reg + ldr r3, =\val + strb r3, [r2] +.endm + +.globl lowlevel_init +lowlevel_init: + + REG 0x53F80008, 0x20034000 // ARM clk = 399, AHB clk = 133 + + /* Init Debug Board CS5 */ + REG 0xB8002050, 0x0000D843 + REG 0xB8002054, 0x22252521 + REG 0xB8002058, 0x22220A00 + + /* MAX (Multi-Layer AHB Crossbar Switch) setup */ + /* MAX - priority for MX25 is (SDHC2/SDMA)>USBOTG>RTIC>IAHB>DAHB */ + ldr r0, =MAX_BASE + ldr r1, =0x00002143 + str r1, [r0, #0x000] /* for S0 */ + str r1, [r0, #0x100] /* for S1 */ + str r1, [r0, #0x200] /* for S2 */ + str r1, [r0, #0x300] /* for S3 */ + str r1, [r0, #0x400] /* for S4 */ + /* SGPCR - always park on last master */ + ldr r1, =0x10 + str r1, [r0, #0x010] /* for S0 */ + str r1, [r0, #0x110] /* for S1 */ + str r1, [r0, #0x210] /* for S2 */ + str r1, [r0, #0x310] /* for S3 */ + str r1, [r0, #0x410] /* for S4 */ + /* MGPCR - restore default values */ + ldr r1, =0x0 + str r1, [r0, #0x800] /* for M0 */ + str r1, [r0, #0x900] /* for M1 */ + str r1, [r0, #0xA00] /* for M2 */ + str r1, [r0, #0xB00] /* for M3 */ + str r1, [r0, #0xC00] /* for M4 */ + + /* M3IF setup */ + ldr r1, =M3IF_BASE + ldr r0, =0x00000001 + str r0, [r1] /* M3IF control reg */ + + /* default CLKO to 1/32 of the ARM core */ + ldr r0, =CCM_MCR + ldr r1, =CCM_MCR + bic r1, r1, #0x00F00000 + bic r1, r1, #0x7F000000 + mov r2, #0x5F000000 + add r2, r2, #0x00200000 + orr r1, r1, r2 + str r1, [r0] + + /* enable all the clocks */ + ldr r2, =0x1FFFFFFF + ldr r0, =CCM_CGR0 + str r2, [r0] + ldr r2, =0xFFFFFFFF + ldr r0, =CCM_CGR1 + str r2, [r0] + ldr r2, =0x000FDFFF + ldr r0, =CCM_CGR2 + str r2, [r0] + mov pc, lr + diff --git a/board/freescale/mx25_3stack/mx25_3stack.c b/board/freescale/mx25_3stack/mx25_3stack.c new file mode 100644 index 0000000000..2dc7130f52 --- /dev/null +++ b/board/freescale/mx25_3stack/mx25_3stack.c @@ -0,0 +1,489 @@ +/* + * (c) Copyright 2009-2010 Freescale Semiconductor + * + * (c) 2007 Pengutronix, Sascha Hauer + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#ifdef CONFIG_LCD +#include +#include +#endif + +#ifdef CONFIG_GET_FEC_MAC_ADDR_FROM_IIM +#include +#endif + +#ifdef CONFIG_CMD_MMC +#include +#include +#endif + +DECLARE_GLOBAL_DATA_PTR; + +static u32 system_rev; +#ifdef CONFIG_LCD +char lcd_cmap[256]; +#endif + +u32 get_board_rev(void) +{ + return system_rev; +} + +static inline void setup_soc_rev(void) +{ + int reg; + reg = __REG(IIM_BASE + IIM_SREV); + if (!reg) { + reg = __REG(ROMPATCH_REV); + reg <<= 4; + } else + reg += CHIP_REV_1_0; + system_rev = 0x25000 + (reg & 0xFF); +} + +inline int is_soc_rev(int rev) +{ + return (system_rev & 0xFF) - rev; +} + +int dram_init(void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + + return 0; +} + +#ifdef CONFIG_CMD_MMC + +struct fsl_esdhc_cfg esdhc_cfg[2] = { + {MMC_SDHC1_BASE, 1, 1}, + {MMC_SDHC2_BASE, 1, 1}, +}; + +int esdhc_gpio_init(bd_t *bis) +{ + s32 status = 0; + u32 index = 0; + u32 val = 0; + + for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; + ++index) { + switch (index) { + case 0: + /* Pins */ + writel(0x10, IOMUXC_BASE + 0x190); /* SD1_CMD */ + writel(0x10, IOMUXC_BASE + 0x194); /* SD1_CLK */ + writel(0x00, IOMUXC_BASE + 0x198); /* SD1_DATA0 */ + writel(0x00, IOMUXC_BASE + 0x19c); /* SD1_DATA1 */ + writel(0x00, IOMUXC_BASE + 0x1a0); /* SD1_DATA2 */ + writel(0x00, IOMUXC_BASE + 0x1a4); /* SD1_DATA3 */ + writel(0x06, IOMUXC_BASE + 0x094); /* D12 (SD1_DATA4) */ + writel(0x06, IOMUXC_BASE + 0x090); /* D13 (SD1_DATA5) */ + writel(0x06, IOMUXC_BASE + 0x08c); /* D14 (SD1_DATA6) */ + writel(0x06, IOMUXC_BASE + 0x088); /* D15 (SD1_DATA7) */ + writel(0x05, IOMUXC_BASE + 0x010); /* A14 (SD1_WP) */ + writel(0x05, IOMUXC_BASE + 0x014); /* A15 (SD1_DET) */ + + /* Pads */ + writel(0xD1, IOMUXC_BASE + 0x388); /* SD1_CMD */ + writel(0xD1, IOMUXC_BASE + 0x38c); /* SD1_CLK */ + writel(0xD1, IOMUXC_BASE + 0x390); /* SD1_DATA0 */ + writel(0xD1, IOMUXC_BASE + 0x394); /* SD1_DATA1 */ + writel(0xD1, IOMUXC_BASE + 0x398); /* SD1_DATA2 */ + writel(0xD1, IOMUXC_BASE + 0x39c); /* SD1_DATA3 */ + writel(0xD1, IOMUXC_BASE + 0x28c); /* D12 (SD1_DATA4) */ + writel(0xD1, IOMUXC_BASE + 0x288); /* D13 (SD1_DATA5) */ + writel(0xD1, IOMUXC_BASE + 0x284); /* D14 (SD1_DATA6) */ + writel(0xD1, IOMUXC_BASE + 0x280); /* D15 (SD1_DATA7) */ + writel(0xD1, IOMUXC_BASE + 0x230); /* A14 (SD1_WP) */ + writel(0xD1, IOMUXC_BASE + 0x234); /* A15 (SD1_DET) */ + + /* + * Set write protect and card detect gpio as inputs + * A14 (SD1_WP) and A15 (SD1_DET) + */ + val = ~(3 << 0) & readl(GPIO1_BASE + GPIO_GDIR); + writel(val, GPIO1_BASE + GPIO_GDIR); + break; + case 1: + /* Pins */ + writel(0x16, IOMUXC_BASE + 0x0e8); /* LD8 (SD1_CMD) */ + writel(0x16, IOMUXC_BASE + 0x0ec); /* LD9 (SD1_CLK) */ + writel(0x06, IOMUXC_BASE + 0x0f0); /* LD10 (SD1_DATA0)*/ + writel(0x06, IOMUXC_BASE + 0x0f4); /* LD11 (SD1_DATA1)*/ + writel(0x06, IOMUXC_BASE + 0x0f8); /* LD12 (SD1_DATA2)*/ + writel(0x06, IOMUXC_BASE + 0x0fc); /* LD13 (SD1_DATA3)*/ + /* CSI_D2 (SD1_DATA4) */ + writel(0x02, IOMUXC_BASE + 0x120); + /* CSI_D3 (SD1_DATA5) */ + writel(0x02, IOMUXC_BASE + 0x124); + /* CSI_D4 (SD1_DATA6) */ + writel(0x02, IOMUXC_BASE + 0x128); + /* CSI_D5 (SD1_DATA7) */ + writel(0x02, IOMUXC_BASE + 0x12c); + + /* Pads */ + writel(0xD1, IOMUXC_BASE + 0x2e0); /* LD8 (SD1_CMD) */ + writel(0xD1, IOMUXC_BASE + 0x2e4); /* LD9 (SD1_CLK) */ + writel(0xD1, IOMUXC_BASE + 0x2e8); /* LD10 (SD1_DATA0)*/ + writel(0xD1, IOMUXC_BASE + 0x2ec); /* LD11 (SD1_DATA1)*/ + writel(0xD1, IOMUXC_BASE + 0x2f0); /* LD12 (SD1_DATA2)*/ + writel(0xD1, IOMUXC_BASE + 0x2f4); /* LD13 (SD1_DATA3)*/ + /* CSI_D2 (SD1_DATA4) */ + writel(0xD1, IOMUXC_BASE + 0x318); + /* CSI_D3 (SD1_DATA5) */ + writel(0xD1, IOMUXC_BASE + 0x31c); + /* CSI_D4 (SD1_DATA6) */ + writel(0xD1, IOMUXC_BASE + 0x320); + /* CSI_D5 (SD1_DATA7) */ + writel(0xD1, IOMUXC_BASE + 0x324); + break; + default: + printf("Warning: you configured more ESDHC controller" + "(%d) as supported by the board(2)\n", + CONFIG_SYS_FSL_ESDHC_NUM); + return status; + break; + } + status |= fsl_esdhc_initialize(bis, &esdhc_cfg[index]); + } + return 0; +} + +int board_mmc_init(bd_t *bis) +{ + if (!esdhc_gpio_init(bis)) + return 0; + else + return -1; +} +#endif + +s32 spi_get_cfg(struct imx_spi_dev_t *dev) +{ + switch (dev->slave.cs) { + case 0: + /* cpld */ + dev->base = CSPI1_BASE; + dev->freq = 25000000; + dev->ss_pol = IMX_SPI_ACTIVE_LOW; + dev->ss = 0; + dev->fifo_sz = 32; + dev->us_delay = 0; + break; + default: + printf("Invalid Bus ID! \n"); + break; + } + + return 0; +} + +void spi_io_init(struct imx_spi_dev_t *dev) +{ + switch (dev->base) { + case CSPI1_BASE: + writel(0, IOMUXC_BASE + 0x180); /* CSPI1 SCLK */ + writel(0x1C0, IOMUXC_BASE + 0x5c4); + writel(0, IOMUXC_BASE + 0x184); /* SPI_RDY */ + writel(0x1E0, IOMUXC_BASE + 0x5c8); + writel(0, IOMUXC_BASE + 0x170); /* MOSI */ + writel(0x1C0, IOMUXC_BASE + 0x5b4); + writel(0, IOMUXC_BASE + 0x174); /* MISO */ + writel(0x1C0, IOMUXC_BASE + 0x5b8); + writel(0, IOMUXC_BASE + 0x17C); /* SS1 */ + writel(0x1E0, IOMUXC_BASE + 0x5C0); + break; + default: + break; + } +} + +#ifdef CONFIG_LCD + +vidinfo_t panel_info = { + vl_refresh:60, + vl_col:640, + vl_row:480, + vl_pixclock:39683, + vl_left_margin:45, + vl_right_margin:114, + vl_upper_margin:33, + vl_lower_margin:11, + vl_hsync:1, + vl_vsync:1, + vl_sync : FB_SYNC_CLK_LAT_FALL, + vl_mode:0, + vl_flag:0, + vl_bpix:4, + cmap : (void *)lcd_cmap, +}; + +void lcdc_hw_init(void) +{ + /* Set VSTBY_REQ as GPIO3[17] on ALT5 */ + mxc_request_iomux(MX25_PIN_VSTBY_REQ, MUX_CONFIG_ALT5); + + /* Set GPIO3[17] as output */ + writel(0x20000, GPIO3_BASE + 0x04); + + /* Set GPIOE as LCDC_LD[16] on ALT2 */ + mxc_request_iomux(MX25_PIN_GPIO_E, MUX_CONFIG_ALT2); + + /* Set GPIOF as LCDC_LD[17] on ALT2 */ + mxc_request_iomux(MX25_PIN_GPIO_F, MUX_CONFIG_ALT2); + + /* Enable pull up on LCDC_LD[16] */ + mxc_iomux_set_pad(MX25_PIN_GPIO_E, + PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PU); + + /* Enable pull up on LCDC_LD[17] */ + mxc_iomux_set_pad(MX25_PIN_GPIO_F, + PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PU); + + /* Enable Pull/Keeper for pad LSCKL */ + mxc_iomux_set_pad(MX25_PIN_LSCLK, + PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PUD | + PAD_CTL_100K_PU | PAD_CTL_SRE_FAST); + + gd->fb_base = CONFIG_FB_BASE; +} + +#ifdef CONFIG_SPLASH_SCREEN +int setup_splash_img() +{ +#ifdef CONFIG_SPLASH_IS_IN_MMC + int mmc_dev = CONFIG_SPLASH_IMG_MMC_DEV; + ulong offset = CONFIG_SPLASH_IMG_OFFSET; + ulong size = CONFIG_SPLASH_IMG_SIZE; + ulong addr = 0; + char *s = NULL; + struct mmc *mmc = find_mmc_device(mmc_dev); + uint blk_start, blk_cnt, n; + + s = getenv("splashimage"); + + if (NULL == s) { + puts("env splashimage not found!\n"); + return -1; + } + addr = simple_strtoul(s, NULL, 16); + + if (!mmc) { + printf("MMC Device %d not found\n", + mmc_dev); + return -1; + } + + if (mmc_init(mmc)) { + puts("MMC init failed\n"); + return -1; + } + + blk_start = ALIGN(offset, mmc->read_bl_len) / mmc->read_bl_len; + blk_cnt = ALIGN(size, mmc->read_bl_len) / mmc->read_bl_len; + n = mmc->block_dev.block_read(mmc_dev, blk_start, + blk_cnt, (u_char *)addr); + flush_cache((ulong)addr, blk_cnt * mmc->read_bl_len); + + return (n == blk_cnt) ? 0 : -1; +#endif +} +#endif +#endif + +#ifdef CONFIG_GET_FEC_MAC_ADDR_FROM_IIM + +int fec_get_mac_addr(unsigned char *mac) +{ + u32 *iim0_mac_base = + (u32 *)(IIM_BASE + IIM_BANK_AREA_0_OFFSET + + CONFIG_IIM_MAC_ADDR_OFFSET); + int i; + + for (i = 0; i < 6; ++i, ++iim0_mac_base) + mac[i] = readl(iim0_mac_base); + + return 0; +} +#endif + +int board_init(void) +{ + +#ifdef CONFIG_MFG + /* MFG firmware need reset usb to avoid host crash firstly */ +#define USBCMD 0x140 + int val = readl(USB_BASE + USBCMD); + val &= ~0x1; /*RS bit*/ + writel(val, USB_BASE + USBCMD); +#endif + + setup_soc_rev(); + + /* setup pins for UART1 */ + /* UART 1 IOMUX Configs */ + mxc_request_iomux(MX25_PIN_UART1_RXD, MUX_CONFIG_FUNC); + mxc_request_iomux(MX25_PIN_UART1_TXD, MUX_CONFIG_FUNC); + mxc_request_iomux(MX25_PIN_UART1_RTS, MUX_CONFIG_FUNC); + mxc_request_iomux(MX25_PIN_UART1_CTS, MUX_CONFIG_FUNC); + mxc_iomux_set_pad(MX25_PIN_UART1_RXD, + PAD_CTL_HYS_SCHMITZ | PAD_CTL_PKE_ENABLE | + PAD_CTL_PUE_PUD | PAD_CTL_100K_PU); + mxc_iomux_set_pad(MX25_PIN_UART1_TXD, + PAD_CTL_PUE_PUD | PAD_CTL_100K_PD); + mxc_iomux_set_pad(MX25_PIN_UART1_RTS, + PAD_CTL_HYS_SCHMITZ | PAD_CTL_PKE_ENABLE | + PAD_CTL_PUE_PUD | PAD_CTL_100K_PU); + mxc_iomux_set_pad(MX25_PIN_UART1_CTS, + PAD_CTL_PUE_PUD | PAD_CTL_100K_PD); + + /* setup pins for FEC */ + mxc_request_iomux(MX25_PIN_FEC_TX_CLK, MUX_CONFIG_FUNC); + mxc_request_iomux(MX25_PIN_FEC_RX_DV, MUX_CONFIG_FUNC); + mxc_request_iomux(MX25_PIN_FEC_RDATA0, MUX_CONFIG_FUNC); + mxc_request_iomux(MX25_PIN_FEC_TDATA0, MUX_CONFIG_FUNC); + mxc_request_iomux(MX25_PIN_FEC_TX_EN, MUX_CONFIG_FUNC); + mxc_request_iomux(MX25_PIN_FEC_MDC, MUX_CONFIG_FUNC); + mxc_request_iomux(MX25_PIN_FEC_MDIO, MUX_CONFIG_FUNC); + mxc_request_iomux(MX25_PIN_FEC_RDATA1, MUX_CONFIG_FUNC); + mxc_request_iomux(MX25_PIN_FEC_TDATA1, MUX_CONFIG_FUNC); + mxc_request_iomux(MX25_PIN_POWER_FAIL, MUX_CONFIG_FUNC); /* PHY INT */ + +#define FEC_PAD_CTL1 (PAD_CTL_HYS_SCHMITZ | PAD_CTL_PUE_PUD | \ + PAD_CTL_PKE_ENABLE) +#define FEC_PAD_CTL2 (PAD_CTL_PUE_PUD) + + mxc_iomux_set_pad(MX25_PIN_FEC_TX_CLK, FEC_PAD_CTL1); + mxc_iomux_set_pad(MX25_PIN_FEC_RX_DV, FEC_PAD_CTL1); + mxc_iomux_set_pad(MX25_PIN_FEC_RDATA0, FEC_PAD_CTL1); + mxc_iomux_set_pad(MX25_PIN_FEC_TDATA0, FEC_PAD_CTL2); + mxc_iomux_set_pad(MX25_PIN_FEC_TX_EN, FEC_PAD_CTL2); + mxc_iomux_set_pad(MX25_PIN_FEC_MDC, FEC_PAD_CTL2); + mxc_iomux_set_pad(MX25_PIN_FEC_MDIO, FEC_PAD_CTL1 | PAD_CTL_22K_PU); + mxc_iomux_set_pad(MX25_PIN_FEC_RDATA1, FEC_PAD_CTL1); + mxc_iomux_set_pad(MX25_PIN_FEC_TDATA1, FEC_PAD_CTL2); + mxc_iomux_set_pad(MX25_PIN_POWER_FAIL, FEC_PAD_CTL1); + + /* + * Set up the FEC_RESET_B and FEC_ENABLE GPIO pins. + * Assert FEC_RESET_B, then power up the PHY by asserting + * FEC_ENABLE, at the same time lifting FEC_RESET_B. + * + * FEC_RESET_B: gpio2[3] is ALT 5 mode of pin D12 + * FEC_ENABLE_B: gpio4[8] is ALT 5 mode of pin A17 + */ + mxc_request_iomux(MX25_PIN_A17, MUX_CONFIG_ALT5); /* FEC_EN */ + mxc_request_iomux(MX25_PIN_D12, MUX_CONFIG_ALT5); /* FEC_RESET_B */ + + mxc_iomux_set_pad(MX25_PIN_A17, PAD_CTL_ODE_OpenDrain); + mxc_iomux_set_pad(MX25_PIN_D12, 0); + + mxc_set_gpio_direction(MX25_PIN_A17, 0); /* FEC_EN */ + mxc_set_gpio_direction(MX25_PIN_D12, 0); /* FEC_RESET_B */ + + /* drop PHY power */ + mxc_set_gpio_dataout(MX25_PIN_A17, 0); /* FEC_EN */ + + /* assert reset */ + mxc_set_gpio_dataout(MX25_PIN_D12, 0); /* FEC_RESET_B */ + udelay(2); /* spec says 1us min */ + + /* turn on PHY power and lift reset */ + mxc_set_gpio_dataout(MX25_PIN_A17, 1); /* FEC_EN */ + mxc_set_gpio_dataout(MX25_PIN_D12, 1); /* FEC_RESET_B */ + +#define I2C_PAD_CTL (PAD_CTL_HYS_SCHMITZ | PAD_CTL_PKE_ENABLE | \ + PAD_CTL_PUE_PUD | PAD_CTL_100K_PU | PAD_CTL_ODE_OpenDrain) + + mxc_request_iomux(MX25_PIN_I2C1_CLK, MUX_CONFIG_SION); + mxc_request_iomux(MX25_PIN_I2C1_DAT, MUX_CONFIG_SION); + mxc_iomux_set_pad(MX25_PIN_I2C1_CLK, 0x1E8); + mxc_iomux_set_pad(MX25_PIN_I2C1_DAT, 0x1E8); + +#ifdef CONFIG_LCD + lcdc_hw_init(); +#endif + + gd->bd->bi_arch_number = MACH_TYPE_MX25_3DS; /* board id for linux */ + gd->bd->bi_boot_params = 0x80000100; /* address of boot parameters */ + + return 0; + +#undef FEC_PAD_CTL1 +#undef FEC_PAD_CTL2 +#undef I2C_PAD_CTL +} + +#ifdef BOARD_LATE_INIT +int board_late_init(void) +{ + u8 reg[4]; + + /* Turn PMIC On*/ + reg[0] = 0x09; + i2c_write(0x54, 0x02, 1, reg, 1); + +#ifdef CONFIG_IMX_SPI_CPLD + mxc_cpld_spi_init(); +#endif + +#ifdef CONFIG_SPLASH_SCREEN + if (!setup_splash_img()) + printf("Read splash screen failed!\n"); +#endif + + return 0; +} +#endif + + +int checkboard(void) +{ + printf("Board: i.MX25 MAX PDK (3DS)\n"); + return 0; +} + +int board_eth_init(bd_t *bis) +{ + int rc = -ENODEV; +#if defined(CONFIG_SMC911X) + rc = smc911x_initialize(0, CONFIG_SMC911X_BASE); +#endif + + cpu_eth_init(bis); + + return rc; +} + diff --git a/board/freescale/mx25_3stack/u-boot.lds b/board/freescale/mx25_3stack/u-boot.lds new file mode 100644 index 0000000000..8d611562f9 --- /dev/null +++ b/board/freescale/mx25_3stack/u-boot.lds @@ -0,0 +1,62 @@ +/* + * (c) Copyright 2009 Freescale Semiconductor + * + * January 2004 - Changed to support H4 device + * Copyright (c) 2004 Texas Instruments + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + board/freescale/mx25_3stack/dcdheader.o (.text) + cpu/arm926ejs/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} diff --git a/board/freescale/mx28_evk/Makefile b/board/freescale/mx28_evk/Makefile new file mode 100644 index 0000000000..312bd63a71 --- /dev/null +++ b/board/freescale/mx28_evk/Makefile @@ -0,0 +1,52 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := mx28_evk.o +SOBJS := lowlevel_init.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### + diff --git a/board/freescale/mx28_evk/config.mk b/board/freescale/mx28_evk/config.mk new file mode 100644 index 0000000000..7b57ec37ad --- /dev/null +++ b/board/freescale/mx28_evk/config.mk @@ -0,0 +1,6 @@ +# +# image should be loaded at 0x41008000 +# +LDSCRIPT := $(SRCTREE)/board/$(VENDOR)/$(BOARD)/u-boot.lds + +TEXT_BASE = 0x41008000 diff --git a/board/freescale/mx28_evk/lowlevel_init.S b/board/freescale/mx28_evk/lowlevel_init.S new file mode 100644 index 0000000000..1c62a315ac --- /dev/null +++ b/board/freescale/mx28_evk/lowlevel_init.S @@ -0,0 +1,36 @@ +/* + * Board specific setup info + * + * Copyright (C) 2010 Freescale Semiconductor, Inc. + * + * (C) Copyright 2003, ARM Ltd. + * Philippe Robin, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +/* Set up the platform, once the cpu has been initialized */ +.globl lowlevel_init +lowlevel_init: + + /* All SDRAM settings are done by sdram_prep */ + mov pc, lr diff --git a/board/freescale/mx28_evk/mx28_evk.c b/board/freescale/mx28_evk/mx28_evk.c new file mode 100644 index 0000000000..814c5b08aa --- /dev/null +++ b/board/freescale/mx28_evk/mx28_evk.c @@ -0,0 +1,253 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include + +#include +#include + +/* This should be removed after it's added into mach-types.h */ +#ifndef MACH_TYPE_MX28EVK +#define MACH_TYPE_MX28EVK 2531 +#endif + +DECLARE_GLOBAL_DATA_PTR; + +#ifdef CONFIG_IMX_SSP_MMC + +/* MMC pins */ +static struct pin_desc mmc0_pins_desc[] = { + { PINID_SSP0_DATA0, PIN_FUN1, PAD_8MA, PAD_3V3, 1 }, + { PINID_SSP0_DATA1, PIN_FUN1, PAD_8MA, PAD_3V3, 1 }, + { PINID_SSP0_DATA2, PIN_FUN1, PAD_8MA, PAD_3V3, 1 }, + { PINID_SSP0_DATA3, PIN_FUN1, PAD_8MA, PAD_3V3, 1 }, + { PINID_SSP0_DATA4, PIN_FUN1, PAD_8MA, PAD_3V3, 1 }, + { PINID_SSP0_DATA5, PIN_FUN1, PAD_8MA, PAD_3V3, 1 }, + { PINID_SSP0_DATA6, PIN_FUN1, PAD_8MA, PAD_3V3, 1 }, + { PINID_SSP0_DATA7, PIN_FUN1, PAD_8MA, PAD_3V3, 1 }, + { PINID_SSP0_CMD, PIN_FUN1, PAD_8MA, PAD_3V3, 1 }, + { PINID_SSP0_DETECT, PIN_FUN1, PAD_8MA, PAD_3V3, 1 }, + { PINID_SSP0_SCK, PIN_FUN1, PAD_8MA, PAD_3V3, 1 }, +}; + +static struct pin_desc mmc1_pins_desc[] = { + { PINID_GPMI_D00, PIN_FUN2, PAD_8MA, PAD_3V3, 1 }, + { PINID_GPMI_D01, PIN_FUN2, PAD_8MA, PAD_3V3, 1 }, + { PINID_GPMI_D02, PIN_FUN2, PAD_8MA, PAD_3V3, 1 }, + { PINID_GPMI_D03, PIN_FUN2, PAD_8MA, PAD_3V3, 1 }, + { PINID_GPMI_D04, PIN_FUN2, PAD_8MA, PAD_3V3, 1 }, + { PINID_GPMI_D05, PIN_FUN2, PAD_8MA, PAD_3V3, 1 }, + { PINID_GPMI_D06, PIN_FUN2, PAD_8MA, PAD_3V3, 1 }, + { PINID_GPMI_D07, PIN_FUN2, PAD_8MA, PAD_3V3, 1 }, + { PINID_GPMI_RDY1, PIN_FUN2, PAD_8MA, PAD_3V3, 1 }, + { PINID_GPMI_RDY0, PIN_FUN2, PAD_8MA, PAD_3V3, 1 }, + { PINID_GPMI_WRN, PIN_FUN2, PAD_8MA, PAD_3V3, 1 } +}; + +static struct pin_group mmc0_pins = { + .pins = mmc0_pins_desc, + .nr_pins = ARRAY_SIZE(mmc0_pins_desc) +}; + +static struct pin_group mmc1_pins = { + .pins = mmc1_pins_desc, + .nr_pins = ARRAY_SIZE(mmc1_pins_desc) +}; + +struct imx_ssp_mmc_cfg ssp_mmc_cfg[2] = { + {REGS_SSP0_BASE, HW_CLKCTRL_SSP0, BM_CLKCTRL_CLKSEQ_BYPASS_SSP0}, + {REGS_SSP1_BASE, HW_CLKCTRL_SSP1, BM_CLKCTRL_CLKSEQ_BYPASS_SSP1}, +}; +#endif + +/* ENET pins */ +static struct pin_desc enet_pins_desc[] = { + { PINID_ENET0_MDC, PIN_FUN1, PAD_8MA, PAD_3V3, 1 }, + { PINID_ENET0_MDIO, PIN_FUN1, PAD_8MA, PAD_3V3, 1 }, + { PINID_ENET0_RX_EN, PIN_FUN1, PAD_8MA, PAD_3V3, 1 }, + { PINID_ENET0_RXD0, PIN_FUN1, PAD_8MA, PAD_3V3, 1 }, + { PINID_ENET0_RXD1, PIN_FUN1, PAD_8MA, PAD_3V3, 1 }, + { PINID_ENET0_TX_EN, PIN_FUN1, PAD_8MA, PAD_3V3, 1 }, + { PINID_ENET0_TXD0, PIN_FUN1, PAD_8MA, PAD_3V3, 1 }, + { PINID_ENET0_TXD1, PIN_FUN1, PAD_8MA, PAD_3V3, 1 }, + { PINID_ENET_CLK, PIN_FUN1, PAD_8MA, PAD_3V3, 1 } +}; + +static struct pin_group enet_pins = { + .pins = enet_pins_desc, + .nr_pins = ARRAY_SIZE(enet_pins_desc) +}; + +/* + * Functions + */ +int board_init(void) +{ + /* Will change it for MX28 EVK later */ + gd->bd->bi_arch_number = MACH_TYPE_MX28EVK; + /* Adress of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; + + return 0; +} + +int dram_init(void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + + return 0; +} + +#ifdef CONFIG_IMX_SSP_MMC + +#ifdef CONFIG_DYNAMIC_MMC_DEVNO +int get_mmc_env_devno() +{ + unsigned long global_boot_mode; + + global_boot_mode = REG_RD_ADDR(GLOBAL_BOOT_MODE_ADDR); + return ((global_boot_mode & 0xf) == BOOT_MODE_SD1) ? 1 : 0; +} +#endif + +#define PINID_SSP0_GPIO_WP PINID_SSP1_SCK +#define PINID_SSP1_GPIO_WP PINID_GPMI_RESETN + +u32 ssp_mmc_is_wp(struct mmc *mmc) +{ + return (mmc->block_dev.dev == 0) ? + pin_gpio_get(PINID_SSP0_GPIO_WP) : + pin_gpio_get(PINID_SSP1_GPIO_WP); +} + +int ssp_mmc_gpio_init(bd_t *bis) +{ + s32 status = 0; + u32 index = 0; + + for (index = 0; index < CONFIG_SYS_SSP_MMC_NUM; + ++index) { + switch (index) { + case 0: + /* Set up MMC pins */ + pin_set_group(&mmc0_pins); + + /* Power on the card slot 0 */ + pin_set_type(PINID_PWM3, PIN_GPIO); + pin_gpio_direction(PINID_PWM3, 1); + pin_gpio_set(PINID_PWM3, 0); + + /* Wait 10 ms for card ramping up */ + udelay(10000); + + /* Set up SD0 WP pin */ + pin_set_type(PINID_SSP0_GPIO_WP, PIN_GPIO); + pin_gpio_direction(PINID_SSP0_GPIO_WP, 0); + + break; + case 1: + /* Set up MMC pins */ + pin_set_group(&mmc1_pins); + + /* Power on the card slot 1 */ + pin_set_type(PINID_PWM4, PIN_GPIO); + pin_gpio_direction(PINID_PWM4, 1); + pin_gpio_set(PINID_PWM4, 0); + + /* Wait 10 ms for card ramping up */ + udelay(10000); + + /* Set up SD1 WP pin */ + pin_set_type(PINID_SSP1_GPIO_WP, PIN_GPIO); + pin_gpio_direction(PINID_SSP1_GPIO_WP, 0); + + break; + default: + printf("Warning: you configured more ssp mmc controller" + "(%d) as supported by the board(2)\n", + CONFIG_SYS_SSP_MMC_NUM); + return status; + } + status |= imx_ssp_mmc_initialize(bis, &ssp_mmc_cfg[index]); + } + + return status; +} + +int board_mmc_init(bd_t *bis) +{ + if (!ssp_mmc_gpio_init(bis)) + return 0; + else + return -1; +} + +#endif + +#ifdef CONFIG_MXC_FEC +#ifdef CONFIG_GET_FEC_MAC_ADDR_FROM_IIM +int fec_get_mac_addr(unsigned char *mac) +{ + u32 val; + + /*set this bit to open the OTP banks for reading*/ + REG_WR(REGS_OCOTP_BASE, HW_OCOTP_CTRL_SET, + BM_OCOTP_CTRL_RD_BANK_OPEN); + + /*wait until OTP contents are readable*/ + while (BM_OCOTP_CTRL_BUSY & REG_RD(REGS_OCOTP_BASE, HW_OCOTP_CTRL)) + udelay(100); + + mac[0] = 0x00; + mac[1] = 0x04; + val = REG_RD(REGS_OCOTP_BASE, HW_OCOTP_CUSTn(0)); + mac[2] = (val >> 24) & 0xFF; + mac[3] = (val >> 16) & 0xFF; + mac[4] = (val >> 8) & 0xFF; + mac[5] = (val >> 0) & 0xFF; + return 0; +} +#endif +#endif + +void enet_board_init(void) +{ + /* Set up ENET pins */ + pin_set_group(&enet_pins); + + /* Power on the external phy */ + pin_set_type(PINID_SSP1_DATA3, PIN_GPIO); + pin_gpio_direction(PINID_SSP1_DATA3, 1); + pin_gpio_set(PINID_SSP1_DATA3, 0); + + /* Reset the external phy */ + pin_set_type(PINID_ENET0_RX_CLK, PIN_GPIO); + pin_gpio_direction(PINID_ENET0_RX_CLK, 1); + pin_gpio_set(PINID_ENET0_RX_CLK, 0); + udelay(200); + pin_gpio_set(PINID_ENET0_RX_CLK, 1); +} diff --git a/board/freescale/mx28_evk/u-boot.lds b/board/freescale/mx28_evk/u-boot.lds new file mode 100644 index 0000000000..b7efe6d72c --- /dev/null +++ b/board/freescale/mx28_evk/u-boot.lds @@ -0,0 +1,51 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + . = ALIGN(4); + .text : + { + cpu/arm926ejs/start.o (.text) + *(.text) + } + .rodata : { *(.rodata) } + . = ALIGN(4); + .data : { *(.data) } + . = ALIGN(4); + .got : { *(.got) } + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss (NOLOAD) : { *(.bss) } + _end = .; +} diff --git a/board/freescale/mx31_3stack/Makefile b/board/freescale/mx31_3stack/Makefile new file mode 100644 index 0000000000..836c19cfe0 --- /dev/null +++ b/board/freescale/mx31_3stack/Makefile @@ -0,0 +1,47 @@ +# +# Copyright (C) 2008, Guennadi Liakhovetski +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := mx31_3stack.o +SOBJS := lowlevel_init.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/freescale/mx31_3stack/config.mk b/board/freescale/mx31_3stack/config.mk new file mode 100644 index 0000000000..f8fc7dd70e --- /dev/null +++ b/board/freescale/mx31_3stack/config.mk @@ -0,0 +1,3 @@ +LDSCRIPT := $(SRCTREE)/board/$(VENDOR)/$(BOARD)/u-boot.lds + +TEXT_BASE = 0x87f00000 diff --git a/board/freescale/mx31_3stack/lowlevel_init.S b/board/freescale/mx31_3stack/lowlevel_init.S new file mode 100644 index 0000000000..bd0de81a2a --- /dev/null +++ b/board/freescale/mx31_3stack/lowlevel_init.S @@ -0,0 +1,248 @@ +/* + * Copyright (C) 2008, Guennadi Liakhovetski + * Copyright (C) 2008, Freescale Semiconductor + * Modifications for MX31 3Stack board + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +.macro REG reg, val + ldr r2, =\reg + ldr r3, =\val + str r3, [r2] +.endm + +.macro REG8 reg, val + ldr r2, =\reg + ldr r3, =\val + strb r3, [r2] +.endm + +.macro DELAY loops + ldr r2, =\loops +1: + subs r2, r2, #1 + nop + bcs 1b +.endm + +.macro init_aips + /* + * Set all MPROTx to be non-bufferable, trusted for R/W, + * not forced to user-mode. + */ + ldr r0, =0x43F00000 + ldr r1, =0x77777777 + str r1, [r0, #0x00] + str r1, [r0, #0x04] + ldr r0, =0x53F00000 + str r1, [r0, #0x00] + str r1, [r0, #0x04] + + /* + * Clear the on and off peripheral modules Supervisor Protect bit + * for SDMA to access them. Did not change the AIPS control registers + * (offset 0x20) access type + */ + ldr r0, =0x43F00000 + ldr r1, =0x0 + str r1, [r0, #0x40] + str r1, [r0, #0x44] + str r1, [r0, #0x48] + str r1, [r0, #0x4C] + ldr r1, [r0, #0x50] + and r1, r1, #0x00FFFFFF + str r1, [r0, #0x50] + + ldr r0, =0x53F00000 + ldr r1, =0x0 + str r1, [r0, #0x40] + str r1, [r0, #0x44] + str r1, [r0, #0x48] + str r1, [r0, #0x4C] + ldr r1, [r0, #0x50] + and r1, r1, #0x00FFFFFF + str r1, [r0, #0x50] +.endm /* init_aips */ + +.macro init_max + ldr r0, =0x43F04000 + /* MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 */ + ldr r1, =0x00302154 + str r1, [r0, #0x000] /* for S0 */ + str r1, [r0, #0x100] /* for S1 */ + str r1, [r0, #0x200] /* for S2 */ + str r1, [r0, #0x300] /* for S3 */ + str r1, [r0, #0x400] /* for S4 */ + /* SGPCR - always park on last master */ + ldr r1, =0x10 + str r1, [r0, #0x010] /* for S0 */ + str r1, [r0, #0x110] /* for S1 */ + str r1, [r0, #0x210] /* for S2 */ + str r1, [r0, #0x310] /* for S3 */ + str r1, [r0, #0x410] /* for S4 */ + /* MGPCR - restore default values */ + ldr r1, =0x0 + str r1, [r0, #0x800] /* for M0 */ + str r1, [r0, #0x900] /* for M1 */ + str r1, [r0, #0xA00] /* for M2 */ + str r1, [r0, #0xB00] /* for M3 */ + str r1, [r0, #0xC00] /* for M4 */ + str r1, [r0, #0xD00] /* for M5 */ +.endm /* init_max */ + +.macro init_m3if + /* Configure M3IF registers */ + ldr r1, =0xB8003000 + /* + * M3IF Control Register (M3IFCTL) + * MRRP[0] = L2CC0 not on priority list (0 << 0) = 0x00000000 + * MRRP[1] = L2CC1 not on priority list (0 << 0) = 0x00000000 + * MRRP[2] = MBX not on priority list (0 << 0) = 0x00000000 + * MRRP[3] = MAX1 not on priority list (0 << 0) = 0x00000000 + * MRRP[4] = SDMA not on priority list (0 << 0) = 0x00000000 + * MRRP[5] = MPEG4 not on priority list (0 << 0) = 0x00000000 + * MRRP[6] = IPU1 on priority list (1 << 6) = 0x00000040 + * MRRP[7] = IPU2 not on priority list (0 << 0) = 0x00000000 + * ------------ + * 0x00000040 + */ + ldr r0, =0x00000040 + str r0, [r1] /* M3IF control reg */ +.endm /* init_m3if */ + +.macro init_drive_strength + /* + * Disable maximum drive strength SDRAM/DDR lines by clearing DSE1 bits + * in SW_PAD_CTL registers + */ + + /* SDCLK */ + ldr r1, =0x43FAC200 + ldr r0, [r1, #0x6C] + bic r0, r0, #(1 << 12) + str r0, [r1, #0x6C] + + /* CAS */ + ldr r0, [r1, #0x70] + bic r0, r0, #(1 << 22) + str r0, [r1, #0x70] + + /* RAS */ + ldr r0, [r1, #0x74] + bic r0, r0, #(1 << 2) + str r0, [r1, #0x74] + + /* CS2 (CSD0) */ + ldr r0, [r1, #0x7C] + bic r0, r0, #(1 << 22) + str r0, [r1, #0x7C] + + /* DQM3 */ + ldr r0, [r1, #0x84] + bic r0, r0, #(1 << 22) + str r0, [r1, #0x84] + + /* DQM2, DQM1, DQM0, SD31-SD0, A25-A0, MA10 (0x288..0x2DC) */ + ldr r2, =22 /* (0x2E0 - 0x288) / 4 = 22 */ +pad_loop: + ldr r0, [r1, #0x88] + bic r0, r0, #(1 << 22) + bic r0, r0, #(1 << 12) + bic r0, r0, #(1 << 2) + str r0, [r1, #0x88] + add r1, r1, #4 + subs r2, r2, #0x1 + bne pad_loop +.endm /* init_drive_strength */ + +.section ".text.init", "x" + +.globl lowlevel_init +lowlevel_init: + + ldr r0, =0x40000015 /* start from AIPS 2GB region */ + mcr p15, 0, r0, c15, c2, 4 + + init_aips + + init_max + + init_m3if + + init_drive_strength + + /* Image Processing Unit: */ + /* Too early to switch display on? */ + REG IPU_CONF, IPU_CONF_DI_EN + /* Clock Control Module: */ + REG CCM_CCMR, 0x074B0BF5 /* Use CKIH, MCU PLL off */ + + DELAY 0x40000 + + REG CCM_CCMR, 0x074B0BF5 | CCMR_MPE /* MCU PLL on */ + /* Switch to MCU PLL */ + REG CCM_CCMR, (0x074B0BF5 | CCMR_MPE) & ~CCMR_MDS + + /* 532-133-66.5 */ + ldr r0, =CCM_BASE + ldr r1, =0xFF871D58 + /* PDR0 */ + str r1, [r0, #0x4] + ldr r1, MPCTL_PARAM_532 + /* MPCTL */ + str r1, [r0, #0x10] + + /* Set UPLL=240MHz, USB=60MHz */ + ldr r1, =0x49FCFE7F + /* PDR1 */ + str r1, [r0, #0x8] + ldr r1, UPCTL_PARAM_240 + /* UPCTL */ + str r1, [r0, #0x14] + /* default CLKO to 1/8 of the ARM core */ + mov r1, #0x000002C0 + add r1, r1, #0x00000006 + /* COSR */ + str r1, [r0, #0x1c] + + /* initial CSD0 MDDR */ + REG 0xB8001004, 0x0075E73A + REG 0xB8001010, 0x00000002 /* reset */ + REG 0xB8001010, 0x00000004 + DELAY 0x10000 + + REG 0xB8001000, 0x92100000 + REG 0x80000F00, 0x0 + REG 0xB8001000, 0xA2100000 + REG 0x80000000, 0x0 + REG 0xB8001000, 0xB2100000 + REG8 0x80000033, 0x0 + REG8 0x81000000, 0xff + REG 0xB8001000, 0x82226080 + REG 0x80000000, 0x0 + REG 0xB8001010, 0x0000000c + + mov r13, ip + /* copy blocks of total uboot to DDR */ + b mxc_nand_load + +MPCTL_PARAM_532: + .word (((1-1) << 26) + ((52-1) << 16) + (10 << 10) + (12 << 0)) +UPCTL_PARAM_240: + .word (((2-1) << 26) + ((13-1) << 16) + (9 << 10) + (3 << 0)) diff --git a/board/freescale/mx31_3stack/mx31_3stack.c b/board/freescale/mx31_3stack/mx31_3stack.c new file mode 100644 index 0000000000..c8dd7ce0ee --- /dev/null +++ b/board/freescale/mx31_3stack/mx31_3stack.c @@ -0,0 +1,75 @@ +/* + * Copyright (C) 2008, Guennadi Liakhovetski + * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. + * Modifications for MX31 3Stack board + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +int dram_init(void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + + return 0; +} + +int board_init(void) +{ + /* CS5: Debug board for ethernet */ + __REG(CSCR_U(5)) = 0x0000D843; + __REG(CSCR_L(5)) = 0x22252521; + __REG(CSCR_A(5)) = 0x22220A00; + + /* setup pins for UART1 */ + mx31_gpio_mux(MUX_RXD1__UART1_RXD_MUX); + mx31_gpio_mux(MUX_TXD1__UART1_TXD_MUX); + mx31_gpio_mux(MUX_RTS1__UART1_RTS_B); + mx31_gpio_mux(MUX_CTS1__UART1_CTS_B); + + /* SPI2 */ + mx31_gpio_mux((MUX_CTL_FUNC << 8) | MUX_CTL_CSPI2_SS2); + mx31_gpio_mux((MUX_CTL_FUNC << 8) | MUX_CTL_CSPI2_SCLK); + mx31_gpio_mux((MUX_CTL_FUNC << 8) | MUX_CTL_CSPI2_SPI_RDY); + mx31_gpio_mux((MUX_CTL_FUNC << 8) | MUX_CTL_CSPI2_MOSI); + mx31_gpio_mux((MUX_CTL_FUNC << 8) | MUX_CTL_CSPI2_MISO); + mx31_gpio_mux((MUX_CTL_FUNC << 8) | MUX_CTL_CSPI2_SS0); + mx31_gpio_mux((MUX_CTL_FUNC << 8) | MUX_CTL_CSPI2_SS1); + + /* start SPI2 clock */ + __REG(CCM_CGR2) = __REG(CCM_CGR2) | (3 << 4); + + gd->bd->bi_arch_number = MACH_TYPE_MX31_3DS; /* board id for linux */ + gd->bd->bi_boot_params = 0x80000100; /* adress of boot parameters */ + + return 0; +} + +int checkboard(void) +{ + printf("Board: MX31 3Stack\n"); + return 0; +} diff --git a/board/freescale/mx31_3stack/u-boot.lds b/board/freescale/mx31_3stack/u-boot.lds new file mode 100644 index 0000000000..b26def75da --- /dev/null +++ b/board/freescale/mx31_3stack/u-boot.lds @@ -0,0 +1,72 @@ +/* + * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(reset) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + * (.text.head) /* arm reset handler */ + * (.text.init) /* lowlevel initial */ + * (.text.load) /* nand copy and load */ + * (.text.setup) + board/freescale/mx31_3stack/libmx31_3stack.a (.text) + lib_arm/libarm.a (.text) + net/libnet.a (.text) + drivers/mtd/libmtd.a (.text) + + . = DEFINED(env_offset) ? env_offset : .; + common/env_embedded.o(.text) + + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} diff --git a/board/freescale/mx35_3stack/Makefile b/board/freescale/mx35_3stack/Makefile new file mode 100644 index 0000000000..d310b8250b --- /dev/null +++ b/board/freescale/mx35_3stack/Makefile @@ -0,0 +1,50 @@ +# +# Copyright (C) 2007, Guennadi Liakhovetski +# +# (C) Copyright 2008-2009 Freescale Semiconductor, Inc. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := mx35_3stack.o +SOBJS := lowlevel_init.o +SOBJS += flash_header.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/freescale/mx35_3stack/board-mx35_3stack.h b/board/freescale/mx35_3stack/board-mx35_3stack.h new file mode 100644 index 0000000000..82667ac29c --- /dev/null +++ b/board/freescale/mx35_3stack/board-mx35_3stack.h @@ -0,0 +1,107 @@ +/* + * + * (c) 2007 Pengutronix, Sascha Hauer + * + * (C) Copyright 2008-2009 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __BOARD_MX35_3STACK_H +#define __BOARD_MX35_3STACK_H + +#define UNALIGNED_ACCESS_ENABLE +#define LOW_INT_LATENCY_ENABLE +#define BRANCH_PREDICTION_ENABLE + +#define L2CC_AUX_CTL_CONFIG 0x00030024 + +#define AIPS_MPR_CONFIG 0x77777777 +#define AIPS_OPACR_CONFIG 0x00000000 + +/* MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 */ +#define MAX_MPR_CONFIG 0x00302154 +/* SGPCR - always park on last master */ +#define MAX_SGPCR_CONFIG 0x00000010 +/* MGPCR - restore default values */ +#define MAX_MGPCR_CONFIG 0x00000000 + +/* + * M3IF Control Register (M3IFCTL) + * MRRP[0] = L2CC0 not on priority list (0 << 0) = 0x00000000 + * MRRP[1] = L2CC1 not on priority list (0 << 0) = 0x00000000 + * MRRP[2] = MBX not on priority list (0 << 0) = 0x00000000 + * MRRP[3] = MAX1 not on priority list (0 << 0) = 0x00000000 + * MRRP[4] = SDMA not on priority list (0 << 0) = 0x00000000 + * MRRP[5] = MPEG4 not on priority list (0 << 0) = 0x00000000 + * MRRP[6] = IPU1 on priority list (1 << 6) = 0x00000040 + * MRRP[7] = IPU2 not on priority list (0 << 0) = 0x00000000 + * ------------ + * 0x00000040 + */ +#define M3IF_CONFIG 0x00000040 + +#define DBG_BASE_ADDR WEIM_CTRL_CS5 +#define DBG_CSCR_U_CONFIG 0x0000D843 +#define DBG_CSCR_L_CONFIG 0x22252521 +#define DBG_CSCR_A_CONFIG 0x22220A00 + +#define CCM_CCMR_CONFIG 0x003F4208 +#define CCM_PDR0_CONFIG 0x00801000 + +#define PLL_BRM_OFFSET 31 +#define PLL_PD_OFFSET 26 +#define PLL_MFD_OFFSET 16 +#define PLL_MFI_OFFSET 10 + +#define _PLL_BRM(x) ((x) << PLL_BRM_OFFSET) +#define _PLL_PD(x) (((x) - 1) << PLL_PD_OFFSET) +#define _PLL_MFD(x) (((x) - 1) << PLL_MFD_OFFSET) +#define _PLL_MFI(x) ((x) << PLL_MFI_OFFSET) +#define _PLL_MFN(x) (x) +#define _PLL_SETTING(brm, pd, mfd, mfi, mfn) \ + (_PLL_BRM(brm) | _PLL_PD(pd) | _PLL_MFD(mfd) | _PLL_MFI(mfi) |\ + _PLL_MFN(mfn)) + +#define CCM_MPLL_532_HZ _PLL_SETTING(1, 1, 12, 11, 1) +#define CCM_MPLL_399_HZ _PLL_SETTING(0, 1, 16, 8, 5) +#define CCM_PPLL_300_HZ _PLL_SETTING(0, 1, 4, 6, 1) + +/*MEMORY SETING*/ +#define ESDCTL_0x92220000 0x92220000 +#define ESDCTL_0xA2220000 0xA2220000 +#define ESDCTL_0xB2220000 0xB2220000 +#define ESDCTL_0x82228080 0x82228080 + +#define ESDCTL_PRECHARGE 0x00000400 + +#define ESDCTL_MDDR_CONFIG 0x007FFC3F +#define ESDCTL_MDDR_MR 0x00000033 +#define ESDCTL_MDDR_EMR 0x02000000 + +#define ESDCTL_DDR2_CONFIG 0x007FFC3F +#define ESDCTL_DDR2_EMR2 0x04000000 +#define ESDCTL_DDR2_EMR3 0x06000000 +#define ESDCTL_DDR2_EN_DLL 0x02000400 +#define ESDCTL_DDR2_RESET_DLL 0x00000333 +#define ESDCTL_DDR2_MR 0x00000233 +#define ESDCTL_DDR2_OCD_DEFAULT 0x02000780 + +#define ESDCTL_DELAY_LINE5 0x00F49F00 +#endif /* __BOARD_MX35_3STACK_H */ diff --git a/board/freescale/mx35_3stack/config.mk b/board/freescale/mx35_3stack/config.mk new file mode 100644 index 0000000000..848787d0f9 --- /dev/null +++ b/board/freescale/mx35_3stack/config.mk @@ -0,0 +1,3 @@ +LDSCRIPT := $(SRCTREE)/board/$(VENDOR)/$(BOARD)/u-boot.lds + +TEXT_BASE = 0x87800000 diff --git a/board/freescale/mx35_3stack/flash_header.S b/board/freescale/mx35_3stack/flash_header.S new file mode 100644 index 0000000000..b662669f80 --- /dev/null +++ b/board/freescale/mx35_3stack/flash_header.S @@ -0,0 +1,108 @@ +/* + * Copyright 2009 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include "board-mx35_3stack.h" + +#ifdef CONFIG_FLASH_HEADER +#ifndef CONFIG_FLASH_HEADER_OFFSET +# error "Must define the offset of flash header" +#endif + +/* Flash header setup */ +#define DCDGEN(i,type, addr, data) \ +dcd_##i: ;\ + .long type ;\ + .long addr ;\ + .long data + +#define GEN_FHEADERADDR(x) (x) + +.section ".text.flasheader", "x" + b _start + .org CONFIG_FLASH_HEADER_OFFSET +app_code_jump_v: .long GEN_FHEADERADDR(_start) +app_code_barker: .long CONFIG_FLASH_HEADER_BARKER +app_code_csf: .long 0 +hwcfg_ptr_ptr: .long GEN_FHEADERADDR(hwcfg_ptr) +super_root_key: .long 0 +hwcfg_ptr: .long GEN_FHEADERADDR(dcd_data) +app_dest_ptr: .long TEXT_BASE +dcd_data: .long 0xB17219E9 +#ifdef MEMORY_MDDR_ENABLE + .long (dcd_data_end - dcd_data - 8) + +//WEIM config-CS5 init +DCDGEN(1, 4, 0xB8002054, 0x444a4541) +DCDGEN(1_1, 4, 0xB8002050, 0x0000dcf6) +DCDGEN(1_2, 4, 0xB8002058, 0x44443302) +//MDDR init +//enable mDDR +DCDGEN(2, 4, 0xB8001010, 0x00000004) +//reset delay time +DCDGEN(3, 4, 0xB8001010, 0x0000000C) +DCDGEN(4, 4, 0xB800100C, 0x007ffc3f) +DCDGEN(5, 4, 0xB800100C, 0x007ffc3f) +DCDGEN(6, 4, 0xB8001004, 0x007ffc3f) +DCDGEN(7, 4, 0xB8001000, 0x92220000) +DCDGEN(8, 1, 0x80000400, 0xda) +DCDGEN(9, 4, 0xB8001000, 0xA2220000) +DCDGEN(10, 4, 0x80000000, 0x87654321) +DCDGEN(11, 4, 0x80000000, 0x87654321) +DCDGEN(12, 4, 0xB8001000, 0xB2220000) +DCDGEN(13, 1, 0x80000033, 0xda) +DCDGEN(14, 1, 0x82000000, 0xda) +DCDGEN(15, 4, 0xB8001000, 0x82226080) +DCDGEN(16, 4, 0xB8001010, 0x00000004) +DCDGEN(17, 4, 0xB8001008, 0x00002000) + +#else + .long 240 + +//WEIM config-CS5 init +DCDGEN(1, 4, 0xB8002050, 0x0000d843) +DCDGEN(1_1, 4, 0xB8002054, 0x22252521) +DCDGEN(1_2, 4, 0xB8002058, 0x22220a00) + +//DDR2 init +DCDGEN(2, 4, 0xB8001010, 0x00000304) +DCDGEN(3, 4, 0xB8001010, 0x0000030C) +DCDGEN(4, 4, 0xB8001004, 0x007ffc3f) +DCDGEN(5, 4, 0xB8001000, 0x92220000) +DCDGEN(6, 4, 0x80000400, 0x12345678) +DCDGEN(7, 4, 0xB8001000, 0xA2220000) +DCDGEN(8, 4, 0x80000000, 0x87654321) +DCDGEN(9, 4, 0x80000000, 0x87654321) +DCDGEN(10, 4, 0xB8001000, 0xB2220000) +DCDGEN(11, 1, 0x80000233, 0xda) +DCDGEN(12, 1, 0x82000780, 0xda) +DCDGEN(13, 1, 0x82000400, 0xda) +DCDGEN(14, 4, 0xB8001000, 0x82226080) +DCDGEN(15, 4, 0xB8001004, 0x007ffc3f) +DCDGEN(16, 4, 0xB800100C, 0x007ffc3f) +DCDGEN(17, 4, 0xB8001010, 0x00000304) +DCDGEN(18, 4, 0xB8001008, 0x00002000) + +#endif +dcd_data_end: + +//CARD_FLASH_CFG_PARMS_T---length +card_cfg: .long 0x100000 +#endif diff --git a/board/freescale/mx35_3stack/lowlevel_init.S b/board/freescale/mx35_3stack/lowlevel_init.S new file mode 100644 index 0000000000..64a20bda02 --- /dev/null +++ b/board/freescale/mx35_3stack/lowlevel_init.S @@ -0,0 +1,441 @@ +/* + * Copyright (C) 2007, Guennadi Liakhovetski + * + * (C) Copyright 2008-2010 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include "board-mx35_3stack.h" + +/* + * return soc version + * 0x10: TO1 + * 0x20: TO2 + * 0x30: TO3 + */ +.macro check_soc_version ret, tmp + ldr \tmp, =IIM_BASE_ADDR + ldr \ret, [\tmp, #IIM_SREV] + cmp \ret, #0x00 + moveq \tmp, #ROMPATCH_REV + ldreq \ret, [\tmp] + moveq \ret, \ret, lsl #4 + addne \ret, \ret, #0x10 +.endm + +/* + * L2CC Cache setup/invalidation/disable + */ +.macro init_l2cc + /* Disable L2 cache first */ + mov r0, #L2CC_BASE_ADDR + ldr r1, [r0, #L2_CACHE_CTL_REG] + bic r1, r1, #0x1 + str r1, [r0, #L2_CACHE_CTL_REG] + + /* + * Configure L2 Cache: + * - 128k size(16k way) + * - 8-way associativity + * - 0 ws TAG/VALID/DIRTY + * - 4 ws DATA R/W + */ + ldr r1, [r0, #L2_CACHE_AUX_CTL_REG] + and r1, r1, #0xFE000000 + ldr r2, =L2CC_AUX_CTL_CONFIG + orr r1, r1, r2 + str r1, [r0, #L2_CACHE_AUX_CTL_REG] + + /* Workaournd for TO1 DDR issue:WT*/ + check_soc_version r1, r2 + cmp r1, #CHIP_REV_2_0 + ldrlo r1, [r0, #L2_CACHE_DBG_CTL_REG] + orrlo r1, r1, #2 + strlo r1, [r0, #L2_CACHE_DBG_CTL_REG] + + /* Invalidate L2 */ + mov r1, #0x000000FF + str r1, [r0, #L2_CACHE_INV_WAY_REG] +1: + /* Poll Invalidate By Way register */ + ldr r2, [r0, #L2_CACHE_INV_WAY_REG] + cmp r2, #0 + bne 1b +.endm /* init_l2cc */ + +/* AIPS setup - Only setup MPROTx registers. + * The PACR default values are good.*/ +.macro init_aips + /* + * Set all MPROTx to be non-bufferable, trusted for R/W, + * not forced to user-mode. + */ + ldr r0, =AIPS1_BASE_ADDR + ldr r1, =AIPS_MPR_CONFIG + str r1, [r0, #0x00] + str r1, [r0, #0x04] + ldr r0, =AIPS2_BASE_ADDR + str r1, [r0, #0x00] + str r1, [r0, #0x04] + + /* + * Clear the on and off peripheral modules Supervisor Protect bit + * for SDMA to access them. Did not change the AIPS control registers + * (offset 0x20) access type + */ + ldr r0, =AIPS1_BASE_ADDR + ldr r1, =AIPS_OPACR_CONFIG + str r1, [r0, #0x40] + str r1, [r0, #0x44] + str r1, [r0, #0x48] + str r1, [r0, #0x4C] + str r1, [r0, #0x50] + ldr r0, =AIPS2_BASE_ADDR + str r1, [r0, #0x40] + str r1, [r0, #0x44] + str r1, [r0, #0x48] + str r1, [r0, #0x4C] + str r1, [r0, #0x50] +.endm /* init_aips */ + +/* MAX (Multi-Layer AHB Crossbar Switch) setup */ +.macro init_max + ldr r0, =MAX_BASE_ADDR + /* MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 */ + ldr r1, =MAX_MPR_CONFIG + str r1, [r0, #0x000] /* for S0 */ + str r1, [r0, #0x100] /* for S1 */ + str r1, [r0, #0x200] /* for S2 */ + str r1, [r0, #0x300] /* for S3 */ + str r1, [r0, #0x400] /* for S4 */ + /* SGPCR - always park on last master */ + ldr r1, =MAX_SGPCR_CONFIG + str r1, [r0, #0x010] /* for S0 */ + str r1, [r0, #0x110] /* for S1 */ + str r1, [r0, #0x210] /* for S2 */ + str r1, [r0, #0x310] /* for S3 */ + str r1, [r0, #0x410] /* for S4 */ + /* MGPCR - restore default values */ + ldr r1, =MAX_MGPCR_CONFIG + str r1, [r0, #0x800] /* for M0 */ + str r1, [r0, #0x900] /* for M1 */ + str r1, [r0, #0xA00] /* for M2 */ + str r1, [r0, #0xB00] /* for M3 */ + str r1, [r0, #0xC00] /* for M4 */ + str r1, [r0, #0xD00] /* for M5 */ +.endm /* init_max */ + +/* M3IF setup */ +.macro init_m3if + /* Configure M3IF registers */ + ldr r1, =M3IF_BASE_ADDR + /* + * M3IF Control Register (M3IFCTL) + * MRRP[0] = L2CC0 not on priority list (0 << 0) = 0x00000000 + * MRRP[1] = L2CC1 not on priority list (0 << 0) = 0x00000000 + * MRRP[2] = MBX not on priority list (0 << 0) = 0x00000000 + * MRRP[3] = MAX1 not on priority list (0 << 0) = 0x00000000 + * MRRP[4] = SDMA not on priority list (0 << 0) = 0x00000000 + * MRRP[5] = MPEG4 not on priority list (0 << 0) = 0x00000000 + * MRRP[6] = IPU1 on priority list (1 << 6) = 0x00000040 + * MRRP[7] = IPU2 not on priority list (0 << 0) = 0x00000000 + * ------------ + * 0x00000040 + */ + ldr r0, =M3IF_CONFIG + str r0, [r1] /* M3IF control reg */ +.endm /* init_m3if */ + +/* To support 133MHz DDR */ +.macro init_drive_strength +/* + mov r0, #0x2 + ldr r1, =IOMUXC_BASE_ADDR + add r1, r1, #0x368 + add r2, r1, #0x4C8 - 0x368 +1: str r0, [r1], #4 + cmp r1, r2 + ble 1b +*/ +.endm /* init_drive_strength */ + +/* CPLD on CS5 setup */ +.macro init_debug_board + ldr r0, =DBG_BASE_ADDR + ldr r1, =DBG_CSCR_U_CONFIG + str r1, [r0, #0x00] + ldr r1, =DBG_CSCR_L_CONFIG + str r1, [r0, #0x04] + ldr r1, =DBG_CSCR_A_CONFIG + str r1, [r0, #0x08] +.endm /* init_debug_board */ + +/* clock setup */ +.macro init_clock + ldr r0, =CCM_BASE_ADDR + + /* default CLKO to 1/32 of the ARM core*/ + ldr r1, [r0, #CLKCTL_COSR] + bic r1, r1, #0x00000FF00 + bic r1, r1, #0x0000000FF + mov r2, #0x00006C00 + add r2, r2, #0x67 + orr r1, r1, r2 + str r1, [r0, #CLKCTL_COSR] + + ldr r2, =CCM_CCMR_CONFIG + str r2, [r0, #CLKCTL_CCMR] + + check_soc_version r1, r2 + cmp r1, #CHIP_REV_2_0 + ldrhs r3, =CCM_MPLL_532_HZ + bhs 1f + ldr r2, [r0, #CLKCTL_PDR0] + tst r2, #CLKMODE_CONSUMER + ldrne r3, =CCM_MPLL_532_HZ /* consumer path*/ + ldreq r3, =CCM_MPLL_399_HZ /* auto path*/ +1: + str r3, [r0, #CLKCTL_MPCTL] + + ldr r1, =CCM_PPLL_300_HZ + str r1, [r0, #CLKCTL_PPCTL] + + ldr r1, =CCM_PDR0_CONFIG + bic r1, r1, #0x800000 + str r1, [r0, #CLKCTL_PDR0] + + ldr r1, [r0, #CLKCTL_CGR0] + orr r1, r1, #0x0C300000 + str r1, [r0, #CLKCTL_CGR0] + + ldr r1, [r0, #CLKCTL_CGR1] + orr r1, r1, #0x00000C00 + orr r1, r1, #0x00000003 + str r1, [r0, #CLKCTL_CGR1] +.endm /* init_clock */ + +.macro setup_sdram + ldr r0, =ESDCTL_BASE_ADDR + mov r3, #0x2000 + str r3, [r0, #0x0] + str r3, [r0, #0x8] + + /*ip(r12) has used to save lr register in upper calling*/ + mov fp, lr + + mov r5, #0x00 + mov r2, #0x00 + mov r1, #CSD0_BASE_ADDR + bl setup_sdram_bank + cmp r3, #0x0 + orreq r5, r5, #1 + eorne r2, r2, #0x1 + blne setup_sdram_bank + + mov lr, fp + + check_soc_version r3, r4 + cmp r1, #CHIP_REV_2_0 + bhs 1f + cmp r5, #0 + movne r3, #L2CC_BASE_ADDR + ldrne r4, [r3, #L2_CACHE_AUX_CTL_REG] + orrne r4, r4, #0x1000 + strne r4, [r3, #L2_CACHE_AUX_CTL_REG] +1: + ldr r3, =ESDCTL_DELAY_LINE5 + str r3, [r0, #0x30] +.endm /* setup_sdram */ + +.section ".text.init", "x" + +.globl lowlevel_init +lowlevel_init: + /* Platform CHIP level init*/ +#ifdef TURN_OFF_IMPRECISE_ABORT + mrs r0, cpsr + bic r0, r0, #0x100 + msr cpsr, r0 +#endif + + mrc 15, 0, r1, c1, c0, 0 + +#ifndef BRANCH_PREDICTION_ENABLE + mrc 15, 0, r0, c1, c0, 1 + bic r0, r0, #7 + mcr 15, 0, r0, c1, c0, 1 +#else + mrc 15, 0, r0, c1, c0, 1 + orr r0, r0, #7 + mcr 15, 0, r0, c1, c0, 1 + orr r1, r1, #(1<<11) +#endif + +#ifdef UNALIGNED_ACCESS_ENABLE + orr r1, r1, #(1<<22) +#endif + +#ifdef LOW_INT_LATENCY_ENABLE + orr r1, r1, #(1<<21) +#endif + mcr 15, 0, r1, c1, c0, 0 + + mov r0, #0 +#ifdef BRANCH_PREDICTION_ENABLE + mcr 15, 0, r0, c15, c2, 4 +#endif + mcr 15, 0, r0, c7, c7, 0 /* invalidate I cache and D cache */ + mcr 15, 0, r0, c8, c7, 0 /* invalidate TLBs */ + mcr 15, 0, r0, c7, c10, 4 /* Drain the write buffer */ + + /* initializes very early AIPS, what for? + * Then it also initializes Multi-Layer AHB Crossbar Switch, + * M3IF */ + /* Also setup the Peripheral Port Remap register inside the core */ + ldr r0, =0x40000015 /* start from AIPS 2GB region */ + mcr p15, 0, r0, c15, c2, 4 + + init_l2cc + + init_aips + + init_max + + init_m3if + + init_drive_strength + + init_clock + init_debug_board + + cmp pc, #PHYS_SDRAM_1 + blo init_sdram_start + cmp pc, #(PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE) + blo skip_sdram_setup + +init_sdram_start: + /*init_sdram*/ + setup_sdram +skip_sdram_setup: + mov r0, #NFC_BASE_ADDR + add r1, r0, #NFC_BUF_SIZE + cmp pc, r0 + movlo pc, lr + cmp pc, r1 + movhi pc, lr + /* return from mxc_nand_load */ + /* r12 saved upper lr*/ + b mxc_nand_load + +/* + * r0: ESDCTL control base, r1: sdram slot base + * r2: DDR type(0:DDR2, 1:MDDR) r3, r4:working base + */ +setup_sdram_bank: + mov r3, #0xE /*0xA + 0x4*/ + tst r2, #0x1 + orreq r3, r3, #0x300 /*DDR2*/ + str r3, [r0, #0x10] + bic r3, r3, #0x00A + str r3, [r0, #0x10] + beq 2f + + mov r3, #0x20000 +1: subs r3, r3, #1 + bne 1b + +2: tst r2, #0x1 + ldreq r3, =ESDCTL_DDR2_CONFIG + ldrne r3, =ESDCTL_MDDR_CONFIG + cmp r1, #CSD1_BASE_ADDR + strlo r3, [r0, #0x4] + strhs r3, [r0, #0xC] + + ldr r3, =ESDCTL_0x92220000 + strlo r3, [r0, #0x0] + strhs r3, [r0, #0x8] + mov r3, #0xDA + ldr r4, =ESDCTL_PRECHARGE + strb r3, [r1, r4] + + tst r2, #0x1 + bne skip_set_mode + + cmp r1, #CSD1_BASE_ADDR + ldr r3, =ESDCTL_0xB2220000 + strlo r3, [r0, #0x0] + strhs r3, [r0, #0x8] + mov r3, #0xDA + ldr r4, =ESDCTL_DDR2_EMR2 + strb r3, [r1, r4] + ldr r4, =ESDCTL_DDR2_EMR3 + strb r3, [r1, r4] + ldr r4, =ESDCTL_DDR2_EN_DLL + strb r3, [r1, r4] + ldr r4, =ESDCTL_DDR2_RESET_DLL + strb r3, [r1, r4] + + ldr r3, =ESDCTL_0x92220000 + strlo r3, [r0, #0x0] + strhs r3, [r0, #0x8] + mov r3, #0xDA + ldr r4, =ESDCTL_PRECHARGE + strb r3, [r1, r4] + +skip_set_mode: + cmp r1, #CSD1_BASE_ADDR + ldr r3, =ESDCTL_0xA2220000 + strlo r3, [r0, #0x0] + strhs r3, [r0, #0x8] + mov r3, #0xDA + strb r3, [r1] + strb r3, [r1] + + ldr r3, =ESDCTL_0xB2220000 + strlo r3, [r0, #0x0] + strhs r3, [r0, #0x8] + tst r2, #0x1 + ldreq r4, =ESDCTL_DDR2_MR + ldrne r4, =ESDCTL_MDDR_MR + mov r3, #0xDA + strb r3, [r1, r4] + ldreq r4, =ESDCTL_DDR2_OCD_DEFAULT + streqb r3, [r1, r4] + ldreq r4, =ESDCTL_DDR2_EN_DLL + ldrne r4, =ESDCTL_MDDR_EMR + strb r3, [r1, r4] + + cmp r1, #CSD1_BASE_ADDR + ldr r3, =ESDCTL_0x82228080 + strlo r3, [r0, #0x0] + strhs r3, [r0, #0x8] + + tst r2, #0x1 + moveq r4, #0x20000 + movne r4, #0x200 +1: subs r4, r4, #1 + bne 1b + + str r3, [r1, #0x100] + ldr r4, [r1, #0x100] + cmp r3, r4 + movne r3, #1 + moveq r3, #0 + + mov pc, lr diff --git a/board/freescale/mx35_3stack/mx35_3stack.c b/board/freescale/mx35_3stack/mx35_3stack.c new file mode 100644 index 0000000000..c3c96838d7 --- /dev/null +++ b/board/freescale/mx35_3stack/mx35_3stack.c @@ -0,0 +1,460 @@ +/* + * Copyright (C) 2007, Guennadi Liakhovetski + * + * (C) Copyright 2008-2010 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#ifdef CONFIG_CMD_MMC +#include +#include +#endif + +#ifdef CONFIG_ARCH_MMU +#include +#include +#endif + +DECLARE_GLOBAL_DATA_PTR; + +static u32 system_rev; + +u32 get_board_rev(void) +{ + return system_rev; +} + +static inline void setup_soc_rev(void) +{ + int reg; + reg = __REG(IIM_BASE_ADDR + IIM_SREV); + if (!reg) { + reg = __REG(ROMPATCH_REV); + reg <<= 4; + } else + reg += CHIP_REV_1_0; + system_rev = 0x35000 + (reg & 0xFF); +} + +static inline void set_board_rev(int rev) +{ + system_rev = (system_rev & ~(0xF << 8)) | (rev & 0xF) << 8; +} + +int is_soc_rev(int rev) +{ + return (system_rev & 0xFF) - rev; +} + +#ifdef CONFIG_ARCH_MMU +void board_mmu_init(void) +{ + unsigned long ttb_base = PHYS_SDRAM_1 + 0x4000; + unsigned long i; + + /* + * Set the TTB register + */ + asm volatile ("mcr p15,0,%0,c2,c0,0" : : "r"(ttb_base) /*:*/); + + /* + * Set the Domain Access Control Register + */ + i = ARM_ACCESS_DACR_DEFAULT; + asm volatile ("mcr p15,0,%0,c3,c0,0" : : "r"(i) /*:*/); + + /* + * First clear all TT entries - ie Set them to Faulting + */ + memset((void *)ttb_base, 0, ARM_FIRST_LEVEL_PAGE_TABLE_SIZE); + /* Actual Virtual Size Attributes Function */ + /* Base Base MB cached? buffered? access permissions */ + /* xxx00000 xxx00000 */ + X_ARM_MMU_SECTION(0x000, 0xF00, 0x1, + ARM_UNCACHEABLE, ARM_UNBUFFERABLE, + ARM_ACCESS_PERM_RW_RW); /* ROM */ + X_ARM_MMU_SECTION(0x100, 0x100, 0x1, + ARM_UNCACHEABLE, ARM_UNBUFFERABLE, + ARM_ACCESS_PERM_RW_RW); /* iRAM */ + X_ARM_MMU_SECTION(0x300, 0x300, 0x1, + ARM_UNCACHEABLE, ARM_UNBUFFERABLE, + ARM_ACCESS_PERM_RW_RW); /* L2CC */ + /* Internal Regsisters upto SDRAM*/ + X_ARM_MMU_SECTION(0x400, 0x400, 0x400, + ARM_UNCACHEABLE, ARM_UNBUFFERABLE, + ARM_ACCESS_PERM_RW_RW); + X_ARM_MMU_SECTION(0x800, 0x000, 0x80, + ARM_CACHEABLE, ARM_BUFFERABLE, + ARM_ACCESS_PERM_RW_RW); /* SDRAM 0:128M*/ + X_ARM_MMU_SECTION(0x800, 0x800, 0x80, + ARM_CACHEABLE, ARM_BUFFERABLE, + ARM_ACCESS_PERM_RW_RW); /* SDRAM 0:128M*/ + X_ARM_MMU_SECTION(0x800, 0x880, 0x80, + ARM_UNCACHEABLE, ARM_UNBUFFERABLE, + ARM_ACCESS_PERM_RW_RW); /* SDRAM 0:128M*/ + X_ARM_MMU_SECTION(0x900, 0x900, 0x80, + ARM_CACHEABLE, ARM_BUFFERABLE, + ARM_ACCESS_PERM_RW_RW); /* SDRAM 1:128M*/ + X_ARM_MMU_SECTION(0xA00, 0xA00, 0x40, + ARM_CACHEABLE, ARM_BUFFERABLE, + ARM_ACCESS_PERM_RW_RW); /* Flash */ + X_ARM_MMU_SECTION(0xB00, 0xB00, 0x20, + ARM_CACHEABLE, ARM_BUFFERABLE, + ARM_ACCESS_PERM_RW_RW); /* PSRAM */ + /* ESDCTL, WEIM, M3IF, EMI, NFC, External I/O */ + X_ARM_MMU_SECTION(0xB20, 0xB20, 0x1E0, + ARM_UNCACHEABLE, ARM_UNBUFFERABLE, + ARM_ACCESS_PERM_RW_RW); + + /* Enable MMU */ + MMU_ON(); +} +#endif + +int dram_init(void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + + return 0; +} + +int board_init(void) +{ + int pad; + +#ifdef CONFIG_MFG +/* MFG firmware need reset usb to avoid host crash firstly */ +#define USBCMD 0x53FF4140 + int val = readl(USBCMD); + val &= ~0x1; /*RS bit*/ + writel(val, USBCMD); +#endif + + setup_soc_rev(); + + /* enable clocks */ + __REG(CCM_BASE_ADDR + CLKCTL_CGR0) |= 0x003F0000; + __REG(CCM_BASE_ADDR + CLKCTL_CGR1) |= 0x00030FFF; + + /* setup pins for I2C1 */ + mxc_request_iomux(MX35_PIN_I2C1_CLK, MUX_CONFIG_SION); + mxc_request_iomux(MX35_PIN_I2C1_DAT, MUX_CONFIG_SION); + + pad = (PAD_CTL_HYS_SCHMITZ | PAD_CTL_PKE_ENABLE \ + | PAD_CTL_PUE_PUD | PAD_CTL_ODE_OpenDrain); + + mxc_iomux_set_pad(MX35_PIN_I2C1_CLK, pad); + mxc_iomux_set_pad(MX35_PIN_I2C1_DAT, pad); + + /* setup pins for FEC */ + mxc_request_iomux(MX35_PIN_FEC_TX_CLK, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_FEC_RX_CLK, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_FEC_RX_DV, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_FEC_COL, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_FEC_RDATA0, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_FEC_TDATA0, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_FEC_TX_EN, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_FEC_MDC, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_FEC_MDIO, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_FEC_TX_ERR, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_FEC_RX_ERR, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_FEC_CRS, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_FEC_RDATA1, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_FEC_TDATA1, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_FEC_RDATA2, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_FEC_TDATA2, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_FEC_RDATA3, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_FEC_TDATA3, MUX_CONFIG_FUNC); + + pad = (PAD_CTL_DRV_3_3V | PAD_CTL_PUE_PUD | PAD_CTL_ODE_CMOS | \ + PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_SLOW); + + mxc_iomux_set_pad(MX35_PIN_FEC_TX_CLK, pad | PAD_CTL_HYS_SCHMITZ | \ + PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD); + mxc_iomux_set_pad(MX35_PIN_FEC_RX_CLK, pad | PAD_CTL_HYS_SCHMITZ | \ + PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD); + mxc_iomux_set_pad(MX35_PIN_FEC_RX_DV, pad | PAD_CTL_HYS_SCHMITZ | \ + PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD); + mxc_iomux_set_pad(MX35_PIN_FEC_COL, pad | PAD_CTL_HYS_SCHMITZ | \ + PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD); + mxc_iomux_set_pad(MX35_PIN_FEC_RDATA0, pad | PAD_CTL_HYS_SCHMITZ | \ + PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD); + mxc_iomux_set_pad(MX35_PIN_FEC_TDATA0, pad | PAD_CTL_HYS_CMOS | \ + PAD_CTL_PKE_NONE | PAD_CTL_100K_PD); + mxc_iomux_set_pad(MX35_PIN_FEC_TX_EN, pad | PAD_CTL_HYS_CMOS | \ + PAD_CTL_PKE_NONE | PAD_CTL_100K_PD); + mxc_iomux_set_pad(MX35_PIN_FEC_MDC, pad | PAD_CTL_HYS_CMOS | \ + PAD_CTL_PKE_NONE | PAD_CTL_100K_PD); + mxc_iomux_set_pad(MX35_PIN_FEC_MDIO, pad | PAD_CTL_HYS_SCHMITZ | \ + PAD_CTL_PKE_ENABLE | PAD_CTL_22K_PU); + mxc_iomux_set_pad(MX35_PIN_FEC_TX_ERR, pad | PAD_CTL_HYS_CMOS | \ + PAD_CTL_PKE_NONE | PAD_CTL_100K_PD); + mxc_iomux_set_pad(MX35_PIN_FEC_RX_ERR, pad | PAD_CTL_HYS_SCHMITZ | \ + PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD); + mxc_iomux_set_pad(MX35_PIN_FEC_CRS, pad | PAD_CTL_HYS_SCHMITZ | \ + PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD); + mxc_iomux_set_pad(MX35_PIN_FEC_RDATA1, pad | PAD_CTL_HYS_SCHMITZ | \ + PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD); + mxc_iomux_set_pad(MX35_PIN_FEC_TDATA1, pad | PAD_CTL_HYS_CMOS | \ + PAD_CTL_PKE_NONE | PAD_CTL_100K_PD); + mxc_iomux_set_pad(MX35_PIN_FEC_RDATA2, pad | PAD_CTL_HYS_SCHMITZ | \ + PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD); + mxc_iomux_set_pad(MX35_PIN_FEC_TDATA2, pad | PAD_CTL_HYS_CMOS | \ + PAD_CTL_PKE_NONE | PAD_CTL_100K_PD); + mxc_iomux_set_pad(MX35_PIN_FEC_RDATA3, pad | PAD_CTL_HYS_SCHMITZ | \ + PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD); + mxc_iomux_set_pad(MX35_PIN_FEC_TDATA3, pad | PAD_CTL_HYS_CMOS | \ + PAD_CTL_PKE_NONE | PAD_CTL_100K_PD); + + gd->bd->bi_arch_number = MACH_TYPE_MX35_3DS; /* board id for linux */ + gd->bd->bi_boot_params = 0x80000100; /* address of boot parameters */ + + return 0; +} + +#ifdef BOARD_LATE_INIT +static inline int board_detect(void) +{ + u8 buf[4]; + int id; + + if (i2c_read(0x08, 0x7, 1, buf, 3) < 0) { + printf("board_late_init: read PMIC@0x08:0x7 fail\n"); + return 0; + } + id = (buf[0] << 16) + (buf[1] << 8) + buf[2]; + printf("PMIC@0x08:0x7 is %x\n", id); + id = (id >> 6) & 0x7; + if (id == 0x7) { + set_board_rev(1); + return 1; + } + set_board_rev(0); + return 0; +} + +int board_late_init(void) +{ + u8 reg[3]; + int i; + + if (board_detect()) { + mxc_request_iomux(MX35_PIN_WATCHDOG_RST, MUX_CONFIG_SION | + MUX_CONFIG_ALT1); + printf("i.MX35 CPU board version 2.0\n"); + if (i2c_read(0x08, 0x1E, 1, reg, 3)) { + printf("board_late_init: read PMIC@0x08:0x1E fail\n"); + return 0; + } + reg[2] |= 0x3; + if (i2c_write(0x08, 0x1E, 1, reg, 3)) { + printf("board_late_init: write PMIC@0x08:0x1E fail\n"); + return 0; + } + if (i2c_read(0x08, 0x20, 1, reg, 3)) { + printf("board_late_init: read PMIC@0x08:0x20 fail\n"); + return 0; + } + reg[2] |= 0x1; + if (i2c_write(0x08, 0x20, 1, reg, 3)) { + printf("board_late_init: write PMIC@0x08:0x20 fail\n"); + return 0; + } + mxc_request_iomux(MX35_PIN_COMPARE, MUX_CONFIG_GPIO); + mxc_iomux_set_input(MUX_IN_GPIO1_IN_5, INPUT_CTL_PATH0); + __REG(GPIO1_BASE_ADDR + 0x04) |= 1 << 5; + __REG(GPIO1_BASE_ADDR) |= 1 << 5; + } else + printf("i.MX35 CPU board version 1.0\n"); + + if (i2c_read(0x69, 0x20, 1, reg, 1) < 0) { + printf("board_late_init: read PMIC@0x69:0x20 fail\n"); + return 0; + } + + reg[0] |= 0x4; + if (i2c_write(0x69, 0x20, 1, reg, 1) < 0) { + printf("board_late_init: write back PMIC@0x69:0x20 fail\n"); + return 0; + } + + for (i = 0; i < 1000; i++) + udelay(200); + + if (i2c_read(0x69, 0x1A, 1, reg, 1) < 0) { + printf("board_late_init: read PMIC@0x69:0x1A fail\n"); + return 0; + } + + reg[0] &= 0x7F; + if (i2c_write(0x69, 0x1A, 1, reg, 1) < 0) { + printf("board_late_init: write back PMIC@0x69:0x1A fail\n"); + return 0; + } + for (i = 0; i < 1000; i++) + udelay(200); + + reg[0] |= 0x80; + if (i2c_write(0x69, 0x1A, 1, reg, 1) < 0) { + printf("board_late_init: 2st write back PMIC@0x69:0x1A fail\n"); + return 0; + } + + return 0; +} +#endif + +int checkboard(void) +{ + printf("Board: MX35 3STACK "); + + if (system_rev & CHIP_REV_2_0) + printf("2.0 ["); + else + printf("1.0 ["); + + switch (__REG(CCM_BASE_ADDR + CLKCTL_RCSR) & 0x0F) { + case 0x0000: + printf("POR"); + break; + case 0x0002: + printf("JTAG"); + break; + case 0x0004: + printf("RST"); + break; + case 0x0008: + printf("WDT"); + break; + default: + printf("unknown"); + } + printf("]\n"); + return 0; +} + +#if defined(CONFIG_SMC911X) +extern int smc911x_initialize(u8 dev_num, int base_addr); +#endif + +int board_eth_init(bd_t *bis) +{ + int rc = -ENODEV; +#if defined(CONFIG_SMC911X) + rc = smc911x_initialize(0, CONFIG_SMC911X_BASE); +#endif + + cpu_eth_init(bis); + + return rc; +} + +#ifdef CONFIG_CMD_MMC + +struct fsl_esdhc_cfg esdhc_cfg[2] = { + {MMC_SDHC1_BASE_ADDR, 1, 1}, + {MMC_SDHC2_BASE_ADDR, 1, 1}, +}; + +int esdhc_gpio_init(bd_t *bis) +{ + u32 pad_val = 0, index = 0; + s32 status = 0; + + /* IOMUX PROGRAMMING */ + for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; + ++index) { + switch (index) { + case 0: + pad_val = PAD_CTL_PUE_PUD | PAD_CTL_PKE_ENABLE | + PAD_CTL_HYS_SCHMITZ | PAD_CTL_DRV_HIGH | + PAD_CTL_100K_PD | PAD_CTL_SRE_FAST; + mxc_request_iomux(MX35_PIN_SD1_CMD, + MUX_CONFIG_FUNC | MUX_CONFIG_SION); + mxc_iomux_set_pad(MX35_PIN_SD1_CMD, pad_val); + + pad_val = PAD_CTL_PUE_PUD | PAD_CTL_PKE_ENABLE | + PAD_CTL_HYS_SCHMITZ | PAD_CTL_DRV_HIGH | + PAD_CTL_100K_PU | PAD_CTL_SRE_FAST; + mxc_request_iomux(MX35_PIN_SD1_CLK, + MUX_CONFIG_FUNC | MUX_CONFIG_SION); + mxc_iomux_set_pad(MX35_PIN_SD1_CLK, pad_val); + mxc_request_iomux(MX35_PIN_SD1_DATA0, + MUX_CONFIG_FUNC); + mxc_iomux_set_pad(MX35_PIN_SD1_DATA0, pad_val); + mxc_request_iomux(MX35_PIN_SD1_DATA3, + MUX_CONFIG_FUNC); + mxc_iomux_set_pad(MX35_PIN_SD1_DATA3, pad_val); + + break; + case 1: + mxc_request_iomux(MX35_PIN_SD2_CLK, + MUX_CONFIG_FUNC | MUX_CONFIG_SION); + mxc_request_iomux(MX35_PIN_SD2_CMD, + MUX_CONFIG_FUNC | MUX_CONFIG_SION); + mxc_request_iomux(MX35_PIN_SD2_DATA0, + MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_SD2_DATA3, + MUX_CONFIG_FUNC); + + pad_val = PAD_CTL_PUE_PUD | PAD_CTL_PKE_ENABLE | + PAD_CTL_HYS_SCHMITZ | PAD_CTL_DRV_MAX | + PAD_CTL_100K_PD | PAD_CTL_SRE_FAST; + mxc_iomux_set_pad(MX35_PIN_SD2_CMD, pad_val); + + pad_val = PAD_CTL_PUE_PUD | PAD_CTL_PKE_ENABLE | + PAD_CTL_HYS_SCHMITZ | PAD_CTL_DRV_HIGH | + PAD_CTL_100K_PU | PAD_CTL_SRE_FAST; + mxc_iomux_set_pad(MX35_PIN_SD2_CLK, pad_val); + mxc_iomux_set_pad(MX35_PIN_SD2_DATA0, pad_val); + mxc_iomux_set_pad(MX35_PIN_SD2_DATA3, pad_val); + + break; + default: + printf("Warning: you configured more ESDHC controller" + "(%d) as supported by the board(2)\n", + CONFIG_SYS_FSL_ESDHC_NUM); + return status; + break; + } + status |= fsl_esdhc_initialize(bis, &esdhc_cfg[index]); + } + + return status; +} + +int board_mmc_init(bd_t *bis) +{ + if (!esdhc_gpio_init(bis)) + return 0; + else + return -1; +} +#endif diff --git a/board/freescale/mx35_3stack/u-boot.lds b/board/freescale/mx35_3stack/u-boot.lds new file mode 100644 index 0000000000..c0156b56a0 --- /dev/null +++ b/board/freescale/mx35_3stack/u-boot.lds @@ -0,0 +1,77 @@ +/* + * January 2004 - Changed to support H4 device + * Copyright (c) 2004 Texas Instruments + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * (C) Copyright 2008-2009 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + board/freescale/mx35_3stack/flash_header.o (.text.flasheader) + *(.text.head) /*arm startup code*/ + *(.text.init) /*platform lowlevel initial code*/ + *(.text.load) /*load bootloader*/ + *(.text.setup) /*platform post lowlevel initial code*/ + *(.text.vect) /*platform post lowlevel initial code*/ + board/freescale/mx35_3stack/libmx35_3stack.a (.text) + lib_arm/libarm.a (.text) + net/libnet.a (.text) + drivers/mtd/libmtd.a (.text) + drivers/mmc/libmmc.a (.text) + + . = DEFINED(env_offset) ? env_offset : .; + common/env_embedded.o(.text) + + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} diff --git a/board/freescale/mx50_arm2/Makefile b/board/freescale/mx50_arm2/Makefile new file mode 100644 index 0000000000..2bbcde3d8a --- /dev/null +++ b/board/freescale/mx50_arm2/Makefile @@ -0,0 +1,49 @@ +# +# Copyright (C) 2007, Guennadi Liakhovetski +# +# (C) Copyright 2010 Freescale Semiconductor, Inc. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := mx50_arm2.o +SOBJS := lowlevel_init.o flash_header.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/freescale/mx50_arm2/config.mk b/board/freescale/mx50_arm2/config.mk new file mode 100644 index 0000000000..fcb4c00e24 --- /dev/null +++ b/board/freescale/mx50_arm2/config.mk @@ -0,0 +1,7 @@ +LDSCRIPT := $(SRCTREE)/board/$(VENDOR)/$(BOARD)/u-boot.lds + +sinclude $(OBJTREE)/board/$(VENDOR)/$(BOARD)/config.tmp + +ifndef TEXT_BASE + TEXT_BASE = 0x77800000 +endif diff --git a/board/freescale/mx50_arm2/flash_header.S b/board/freescale/mx50_arm2/flash_header.S new file mode 100644 index 0000000000..fbab4f5bfb --- /dev/null +++ b/board/freescale/mx50_arm2/flash_header.S @@ -0,0 +1,791 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +#ifdef CONFIG_FLASH_HEADER +#ifndef CONFIG_FLASH_HEADER_OFFSET +# error "Must define the offset of flash header" +#endif + +.section ".text.flasheader", "x" + b _start + .org CONFIG_FLASH_HEADER_OFFSET + +/* First IVT to copy the plugin that initializes the system into OCRAM */ +ivt_header: .long 0x402000D1 /* Tag=0xD1, Len=0x0020, Ver=0x40 */ +app_code_jump_v: .long 0xF8006458 /* Plugin entry point */ +reserv1: .long 0x0 +dcd_ptr: .long 0x0 +boot_data_ptr: .long 0xF8006420 +self_ptr: .long 0xF8006400 +app_code_csf: .long 0x0 /* reserve 4K for csf */ +reserv2: .long 0x0 +boot_data: .long 0xF8006000 +image_len: .long 8*1024 /* Can copy upto 72K, OCRAM free space */ +plugin: .long 0x1 /* Enable plugin flag */ + +/* Second IVT to give entry point into the bootloader copied to DDR */ +ivt2_header: .long 0x402000D1 //Tag=0xD1, Len=0x0020, Ver=0x40 +app2_code_jump_v: .long _start // Entry point for the bootloader +reserv3: .long 0x0 +dcd2_ptr: .long 0x0 +boot_data2_ptr: .long boot_data2 +self_ptr2: .long ivt2_header +app_code_csf2: .long 0x0 // reserve 4K for csf +reserv4: .long 0x0 +boot_data2: .long TEXT_BASE +image_len2: .long _end - TEXT_BASE +plugin2: .long 0x0 + +/*============================================================================= + * Here starts the plugin code + *===========================================================================*/ + +plugin_start: +/* Save the return address and the function arguments */ + push {r0-r2, lr} + +/*============================================================================= + *init script for codex LPDDR1-200MHz CPU board + *===========================================================================*/ + +/* Setup PLL1 to be 800 MHz */ + ldr r0, =CCM_BASE_ADDR + +/* Switch ARM domain to be clocked from LP-APM */ + mov r1, #0x4 + str r1, [r0, #CLKCTL_CCSR] + + ldr r0, =PLL1_BASE_ADDR + ldr r1, =0x1232 + str r1, [r0, #PLL_DP_CTL] /* Set DPLL ON (set UPEN bit); BRMO=1 */ + ldr r1, =0x2 + str r1, [r0, #PLL_DP_CONFIG] /* Enable auto-restart AREN bit */ + + ldr r1, =DP_OP_800 + str r1, [r0, #PLL_DP_OP] + str r1, [r0, #PLL_DP_HFS_OP] + + ldr r1, =DP_MFD_800 + str r1, [r0, #PLL_DP_MFD] + str r1, [r0, #PLL_DP_HFS_MFD] + + ldr r1, =DP_MFN_800 + str r1, [r0, #PLL_DP_MFN] + str r1, [r0, #PLL_DP_HFS_MFN] + + /* Now restart PLL */ + ldr r1, =0x1232 + str r1, [r0, #PLL_DP_CTL] +wait_pll1_lock: + ldr r1, [r0, #PLL_DP_CTL] + ands r1, r1, #0x1 + beq wait_pll1_lock + +/* Switch ARM back to PLL1 */ + ldr r0, =CCM_BASE_ADDR + ldr r1, =0x0 + str r1, [r0,#CLKCTL_CCSR] + +/*============================================================================= + * Enable all clocks (they are disabled by ROM code) + *===========================================================================*/ + + mov r1, #0xffffffff + str r1, [r0, #0x68] + str r1, [r0, #0x6c] + str r1, [r0, #0x70] + str r1, [r0, #0x74] + str r1, [r0, #0x78] + str r1, [r0, #0x7c] + str r1, [r0, #0x80] + str r1, [r0, #0x84] + +#if defined(CONFIG_LPDDR2) + +/* DDR clock setting -- Set DDR to be div 3 to get 266MHz */ +/* setmem /32 0x53FD4098 = 0x80000003 */ + ldr r1, =0x80000003 + str r1, [r0, #0x98] + +/* poll to make sure DDR dividers take effect */ +1: + ldr r1, [r0, #0x8c] + ands r1, r1, #0x4 + bne 1b + +/*============================================================================= + * IOMUX + *===========================================================================*/ + ldr r0, =0x53fa8000 + mov r1, #0x04000000 + str r1, [r0, #0x6ac] + mov r2, #0x00380000 + str r2, [r0, #0x6a4] + str r2, [r0, #0x668] + str r2, [r0, #0x698] + str r2, [r0, #0x6a0] + str r2, [r0, #0x6a8] + str r2, [r0, #0x6b4] + str r2, [r0, #0x498] + str r2, [r0, #0x49c] + str r2, [r0, #0x4f0] + str r2, [r0, #0x500] + str r2, [r0, #0x4c8] + str r2, [r0, #0x528] + str r2, [r0, #0x4f4] + str r2, [r0, #0x4fc] + str r2, [r0, #0x4cc] + str r2, [r0, #0x524] + +/*============================================================================= + * DDR setting + *===========================================================================*/ + + ldr r0, =DATABAHN_BASE_ADDR +/* setmem /32 0x14000000 = 0x00000500 */ + ldr r1, =0x00000500 + str r1, [r0, #0x0] +/* setmem /32 0x14000004 = 0x00000000 */ + ldr r1, =0x00000000 + str r1, [r0, #0x4] +/* setmem /32 0x14000008 = 0x0000001b */ + ldr r1, =0x0000001b + str r1, [r0, #0x8] +/* setmem /32 0x1400000c = 0x0000d056 */ + ldr r1, =0x0000d056 + str r1, [r0, #0xc] +/* setmem /32 0x14000010 = 0x0000010b */ + ldr r1, =0x0000010b + str r1, [r0, #0xc] +/* setmem /32 0x14000014 = 0x00000a6b */ + ldr r1, =0x00000a6b + str r1, [r0, #0x14] +/* setmem /32 0x14000018 = 0x02020d0c */ + ldr r1, =0x02020d0c + str r1, [r0, #0x18] +/* setmem /32 0x1400001c = 0x0c110302 */ + ldr r1, =0x0c110302 + str r1, [r0, #0x1c] +/* setmem /32 0x14000020 = 0x05020503 */ + ldr r1, =0x05020503 + str r1, [r0, #0x20] +/* setmem /32 0x14000024 = 0x00000105 */ + ldr r1, =0x00000105 + str r1, [r0, #0x24] +/* setmem /32 0x14000028 = 0x01000403 */ + ldr r1, =0x01000403 + str r1, [r0, #0x28] +/* setmem /32 0x1400002c = 0x09040501 */ + ldr r1, =0x09040501 + str r1, [r0, #0x2c] +/* setmem /32 0x14000030 = 0x02000000 */ + ldr r1, =0x02000000 + str r1, [r0, #0x30] +/* setmem /32 0x14000034 = 0x00000e02 */ + ldr r1, =0x00000e02 + str r1, [r0, #0x34] +/* setmem /32 0x14000038 = 0x00000006 */ + ldr r1, =0x00000006 + str r1, [r0, #0x38] +/* setmem /32 0x1400003c = 0x00002301 */ + ldr r1, =0x00002301 + str r1, [r0, #0x3c] +/* setmem /32 0x14000040 = 0x00050408 */ + ldr r1, =0x00050408 + str r1, [r0, #0x40] +/* setmem /32 0x14000044 = 0x00000300 */ + ldr r1, =0x00000300 + str r1, [r0, #0x44] +/* setmem /32 0x14000048 = 0x00260026 */ + ldr r1, =0x00260026 + str r1, [r0, #0x48] +/* setmem /32 0x1400004c = 0x00010000 */ + ldr r1, =0x00010000 + str r1, [r0, #0x4c] +/* setmem /32 0x1400005c = 0x02000000 */ + ldr r1, =0x02000000 + str r1, [r0, #0x5c] +/* setmem /32 0x14000060 = 0x00000002 */ + ldr r1, =0x00000002 + str r1, [r0, #0x60] +/* setmem /32 0x14000064 = 0x00000000 */ + ldr r1, =0x00000000 + str r1, [r0, #0x64] +/* setmem /32 0x14000068 = 0x00000000 */ + ldr r1, =0x00000000 + str r1, [r0, #0x68] +/* setmem /32 0x1400006c = 0x00040042 */ + ldr r1, =0x00040042 + str r1, [r0, #0x6c] +/* setmem /32 0x14000070 = 0x00000001 */ + ldr r1, =0x00000001 + str r1, [r0, #0x70] +/* setmem /32 0x14000074 = 0x00000000 */ + ldr r1, =0x00000001 + str r1, [r0, #0x74] +/* setmem /32 0x14000078 = 0x00040042 */ + ldr r1, =0x00040042 + str r1, [r0, #0x78] +/* setmem /32 0x1400007c = 0x00000001 */ + ldr r1, =0x00000001 + str r1, [r0, #0x7c] +/* setmem /32 0x14000080 = 0x010b0000 */ + ldr r1, =0x010b0000 + str r1, [r0, #0x80] +/* setmem /32 0x14000084 = 0x00000060 */ + ldr r1, =0x00000060 + str r1, [r0, #0x84] +/* setmem /32 0x14000088 = 0x02400018 */ + ldr r1, =0x02400018 + str r1, [r0, #0x88] +/* setmem /32 0x1400008c = 0x01000e00 */ + ldr r1, =0x01000e00 + str r1, [r0, #0x8c] +/* setmem /32 0x14000090 = 0x0a010101 */ + ldr r1, =0x0a010101 + str r1, [r0, #0x90] +/* setmem /32 0x14000094 = 0x01011f1f */ + ldr r1, =0x01011f1f + str r1, [r0, #0x94] +/* setmem /32 0x14000098 = 0x01010101 */ + ldr r1, =0x01010101 + str r1, [r0, #0x98] +/* setmem /32 0x1400009c = 0x00030101 */ + ldr r1, =0x00030101 + str r1, [r0, #0x9c] +/* setmem /32 0x140000a0 = 0x00010000 */ + ldr r1, =0x00010000 + str r1, [r0, #0xa0] +/* setmem /32 0x140000a4 = 0x00010000 */ + ldr r1, =0x00010000 + str r1, [r0, #0xa4] +/* setmem /32 0x140000a8 = 0x00000000 */ + ldr r1, =0x00000000 + str r1, [r0, #0xa8] +/* setmem /32 0x140000ac = 0x0000ffff */ + ldr r1, =0x0000ffff + str r1, [r0, #0xac] +/* setmem /32 0x140000c8 = 0x02020101 */ + ldr r1, =0x02020101 + str r1, [r0, #0xc8] +/* setmem /32 0x140000cc = 0x01000000 */ + ldr r1, =0x01000000 + str r1, [r0, #0xcc] +/* setmem /32 0x140000d0 = 0x01000201 */ + ldr r1, =0x01000201 + str r1, [r0, #0xd0] +/* setmem /32 0x140000d4 = 0x00000200 */ + ldr r1, =0x00000200 + str r1, [r0, #0xd4] +/* setmem /32 0x140000d8 = 0x00000102 */ + ldr r1, =0x00000102 + str r1, [r0, #0xd8] +/* setmem /32 0x140000dc = 0x0000ffff */ + ldr r1, =0x0000ffff + str r1, [r0, #0xdc] +/* setmem /32 0x140000e0 = 0x0000ffff */ + ldr r1, =0x0000ffff + str r1, [r0, #0xdc] +/* setmem /32 0x140000e4 = 0x02020000 */ + ldr r1, =0x02020000 + str r1, [r0, #0xe4] +/* setmem /32 0x140000e8 = 0x02020202 */ + ldr r1, =0x02020202 + str r1, [r0, #0xe8] +/* setmem /32 0x140000ec = 0x00000202 */ + ldr r1, =0x00000202 + str r1, [r0, #0xec] +/* setmem /32 0x140000f0 = 0x01010064 */ + ldr r1, =0x01010064 + str r1, [r0, #0xf0] +/* setmem /32 0x140000f4 = 0x01010101 */ + ldr r1, =0x01010101 + str r1, [r0, #0xf4] +/* setmem /32 0x140000f8 = 0x00010101 */ + ldr r1, =0x00010101 + str r1, [r0, #0xf8] +/* setmem /32 0x140000fc = 0x00000064 */ + ldr r1, =0x00000064 + str r1, [r0, #0xfc] +/* setmem /32 0x14000100 = 0x00000000 */ + ldr r1, =0x00000000 + str r1, [r0, #0x100] +/* setmem /32 0x14000104 = 0x02000802 */ + ldr r1, =0x02000802 + str r1, [r0, #0x104] +/* setmem /32 0x14000108 = 0x04080000 */ + ldr r1, =0x04080000 + str r1, [r0, #0x108] +/* setmem /32 0x1400010c = 0x04080408 */ + ldr r1, =0x04080408 + str r1, [r0, #0x10c] +/* setmem /32 0x14000110 = 0x04080408 */ + ldr r1, =0x04080408 + str r1, [r0, #0x110] +/* setmem /32 0x14000114 = 0x03060408 */ + ldr r1, =0x03060408 + str r1, [r0, #0x114] +/* setmem /32 0x14000118 = 0x01010002 */ + ldr r1, =0x01010002 + str r1, [r0, #0x118] +/* setmem /32 0x1400011c = 0x00000000 */ + ldr r1, =0x00000000 + str r1, [r0, #0x11c] +/* setmem /32 0x14000200 = 0x00000000 */ + ldr r1, =0x00000000 + str r1, [r0, #0x200] +/* setmem /32 0x14000204 = 0x00000000 */ + ldr r1, =0x00000000 + str r1, [r0, #0x204] +/* setmem /32 0x14000208 = 0xf5003a27 */ + ldr r1, =0xf5003a27 + str r1, [r0, #0x208] +/* setmem /32 0x1400020c = 0x074002e1 */ + ldr r1, =0x074002e1 + str r1, [r0, #0x20c] +/* setmem /32 0x14000210 = 0xf5003a27 */ + ldr r1, =0xf5003a27 + str r1, [r0, #0x210] +/* setmem /32 0x14000214 = 0x074002e1 */ + ldr r1, =0x074002e1 + str r1, [r0, #0x214] +/* setmem /32 0x14000218 = 0xf5003a27 */ + ldr r1, =0xf5003a27 + str r1, [r0, #0x218] +/* setmem /32 0x1400021c = 0x074002e1 */ + ldr r1, =0x074002e1 + str r1, [r0, #0x21c] +/* setmem /32 0x14000220 = 0xf5003a27 */ + ldr r1, =0xf5003a27 + str r1, [r0, #0x220] +/* setmem /32 0x14000224 = 0x074002e1 */ + ldr r1, =0x074002e1 + str r1, [r0, #0x224] +/* setmem /32 0x14000228 = 0xf5003a27 */ + ldr r1, =0xf5003a27 + str r1, [r0, #0x228] +/* setmem /32 0x1400022c = 0x074002e1 */ + ldr r1, =0x074002e1 + str r1, [r0, #0x22c] +/* setmem /32 0x14000230 = 0x00000000 */ + ldr r1, =0x00000000 + str r1, [r0, #0x230] +/* setmem /32 0x14000234 = 0x00810006 */ + ldr r1, =0x00810006 + str r1, [r0, #0x234] +/* setmem /32 0x14000238 = 0x20099414 */ + ldr r1, =0x20099414 + str r1, [r0, #0x238] +/* setmem /32 0x1400023c = 0x000a1401 */ + ldr r1, =0x000a1401 + str r1, [r0, #0x23c] +/* setmem /32 0x14000240 = 0x20099414 */ + ldr r1, =0x20099414 + str r1, [r0, #0x240] +/* setmem /32 0x14000244 = 0x000a1401 */ + ldr r1, =0x000a1401 + str r1, [r0, #0x244] +/* setmem /32 0x14000248 = 0x20099414 */ + ldr r1, =0x20099414 + str r1, [r0, #0x248] +/* setmem /32 0x1400024c = 0x000a1401 */ + ldr r1, =0x000a1401 + str r1, [r0, #0x24c] +/* setmem /32 0x14000250 = 0x20099414 */ + ldr r1, =0x20099414 + str r1, [r0, #0x250] +/* setmem /32 0x14000254 = 0x000a1401 */ + ldr r1, =0x000a1401 + str r1, [r0, #0x254] +/* setmem /32 0x14000258 = 0x20099414 */ + ldr r1, =0x000a1401 + str r1, [r0, #0x258] +/* setmem /32 0x1400025c = 0x000a1401 */ + ldr r1, =0x000a1401 + str r1, [r0, #0x25c] + +/* Start ddr */ +/* setmem /32 0x14000000 = 0x00000501 // bit[0]: start */ + ldr r1, =0x00000501 + str r1, [r0, #0x0] +/* poll to make sure it is done */ +1: + ldr r1, [r0, #0xa8] + ands r1, r1, #0x10 + beq 1b +#else + +/*================================================================== + * lpddr1-mddr + *=================================================================*/ + +/* DDR clock setting -- Set DDR to be div 4 to get 200MHz */ +/* setmem /32 0x53FD4098 = 0x80000004 */ + ldr r1, =0x80000004 + str r1, [r0, #0x98] + +/* poll to make sure DDR dividers take effect */ +1: + ldr r1, [r0, #0x8c] + ands r1, r1, #0x4 + bne 1b + +/*================================================================== + * IOMUX + *=================================================================*/ + ldr r0, =0x53fa8600 + mov r1, #0x02000000 + mov r3, #0x00200000 + mov r2, #0x0 + str r1, [r0, #0xac] + str r2, [r0, #0x6c] + str r2, [r0, #0x8c] + str r3, [r0, #0xa4] + str r3, [r0, #0x68] + str r3, [r0, #0x98] + str r3, [r0, #0xa0] + str r3, [r0, #0xa8] + str r3, [r0, #0xb4] + + ldr r0, =0x53fa8400 + str r3, [r0, #0x98] + str r3, [r0, #0x9c] + str r3, [r0, #0xf0] + str r3, [r0, #0x100] + str r3, [r0, #0xc8] + str r3, [r0, #0x128] + str r3, [r0, #0xf4] + str r3, [r0, #0xfc] + str r3, [r0, #0xcc] + str r3, [r0, #0x124] + str r2, [r0, #0x270] + +/*============================================================== + * DDR setting + *=============================================================*/ + ldr r0, =DATABAHN_BASE_ADDR +/* setmem /32 0x14000000 = 0x00000100 */ + ldr r1, =0x00000100 + str r1, [r0, #0x0] +/* setmem /32 0x14000008 = 0x00009c40 */ + ldr r1, =0x00009c40 + str r1, [r0, #0x8] +/* setmem /32 0x14000014 = 0x02000000 */ + ldr r1, =0x02000000 + str r1, [r0, #0x14] +/* setmem /32 0x14000018 = 0x01010706 */ + ldr r1, =0x01010706 + str r1, [r0, #0x018] +/* setmem /32 0x1400001c = 0x080b0201 */ + ldr r1, =0x080b0201 + str r1, [r0, #0x01c] +/* setmem /32 0x14000020 = 0x02000303 */ + ldr r1, =0x02000303 + str r1, [r0, #0x020] +/* setmem /32 0x14000024 = 0x0136b002 */ + ldr r1, =0x0136b002 + str r1, [r0, #0x024] +/* setmem /32 0x14000028 = 0x01000101 */ + ldr r1, =0x01000101 + str r1, [r0, #0x028] +/* setmem /32 0x1400002c = 0x06030301 */ + ldr r1, =0x06030301 + str r1, [r0, #0x02c] +/* setmem /32 0x14000030 = 0x00000000 */ + ldr r1, =0x00000000 + str r1, [r0, #0x030] +/* setmem /32 0x14000034 = 0x00000a02 */ + ldr r1, =0x00000a02 + str r1, [r0, #0x034] +/* setmem /32 0x14000038 = 0x00000003 */ + ldr r1, =0x00000003 + str r1, [r0, #0x038] +/* setmem /32 0x1400003c = 0x00001401 */ + ldr r1, =0x00001401 + str r1, [r0, #0x03c] +/* setmem /32 0x14000040 = 0x0005030f */ + ldr r1, =0x0005030f + str r1, [r0, #0x040] +/* setmem /32 0x14000044 = 0x00000200 */ + ldr r1, =0x00000200 + str r1, [r0, #0x044] +/* setmem /32 0x14000048 = 0x00180018 */ + ldr r1, =0x00180018 + str r1, [r0, #0x048] +/* setmem /32 0x1400004c = 0x00010000 */ + ldr r1, =0x00010000 + str r1, [r0, #0x04c] +/* setmem /32 0x1400005c = 0x01000000 */ + ldr r1, =0x01000000 + str r1, [r0, #0x05c] +/* setmem /32 0x14000060 = 0x00000001 */ + ldr r1, =0x00000001 + str r1, [r0, #0x060] +/* setmem /32 0x14000064 = 0x00000000 */ + ldr r1, =0x00000000 + str r1, [r0, #0x064] +/* setmem /32 0x14000068 = 0x00320000 */ + ldr r1, =0x00320000 + str r1, [r0, #0x068] +/* setmem /32 0x1400006c = 0x00000000 */ + ldr r1, =0x00000000 + str r1, [r0, #0x06c] +/* setmem /32 0x14000070 = 0x00000000 */ + ldr r1, =0x00000000 + str r1, [r0, #0x070] +/* setmem /32 0x14000074 = 0x00320000 */ + ldr r1, =0x00320000 + str r1, [r0, #0x074] +/* setmem /32 0x14000080 = 0x02000000 */ + ldr r1, =0x02000000 + str r1, [r0, #0x080] +/* setmem /32 0x14000084 = 0x00000100 */ + ldr r1, =0x00000100 + str r1, [r0, #0x084] +/* setmem /32 0x14000088 = 0x02400040 */ + ldr r1, =0x02400040 + str r1, [r0, #0x088] +/* setmem /32 0x1400008c = 0x01000000 */ + ldr r1, =0x01000000 + str r1, [r0, #0x08c] +/* setmem /32 0x14000090 = 0x0a000100 */ + ldr r1, =0x0a000100 + str r1, [r0, #0x090] +/* setmem /32 0x14000094 = 0x01011f1f */ + ldr r1, =0x01011f1f + str r1, [r0, #0x094] +/* setmem /32 0x14000098 = 0x01010101 */ + ldr r1, =0x01010101 + str r1, [r0, #0x098] +/* setmem /32 0x1400009c = 0x00030101 */ + ldr r1, =0x00030101 + str r1, [r0, #0x09c] +/* setmem /32 0x140000a4 = 0x00010000 */ + ldr r1, =0x00010000 + str r1, [r0, #0x0a4] +/* setmem /32 0x140000ac = 0x0000ffff */ + ldr r1, =0x0000ffff + str r1, [r0, #0x0ac] +/* setmem /32 0x140000c8 = 0x02020101 */ + ldr r1, =0x02020101 + str r1, [r0, #0x0c8] +/* setmem /32 0x140000cc = 0x00000000 */ + ldr r1, =0x00000000 + str r1, [r0, #0x0cc] +/* setmem /32 0x140000d0 = 0x01000202 */ + ldr r1, =0x01000202 + str r1, [r0, #0x0d0] +/* setmem /32 0x140000d4 = 0x02030302 */ + ldr r1, =0x02030302 + str r1, [r0, #0x0d4] +/* setmem /32 0x140000d8 = 0x00000001 */ + ldr r1, =0x00000001 + str r1, [r0, #0x0d8] +/* setmem /32 0x140000dc = 0x0000ffff */ + ldr r1, =0x0000ffff + str r1, [r0, #0x0dc] +/* setmem /32 0x140000e0 = 0x0000ffff */ + ldr r1, =0x0000ffff + str r1, [r0, #0x0e0] +/* setmem /32 0x140000e4 = 0x02020000 */ + ldr r1, =0x02020000 + str r1, [r0, #0x0e4] +/* setmem /32 0x140000e8 = 0x02020202 */ + ldr r1, =0x02020202 + str r1, [r0, #0x0e8] +/* setmem /32 0x140000ec = 0x00000202 */ + ldr r1, =0x00000202 + str r1, [r0, #0x0ec] +/* setmem /32 0x140000f0 = 0x01010064 */ + ldr r1, =0x01010064 + str r1, [r0, #0x0f0] +/* setmem /32 0x140000f4 = 0x01010101 */ + ldr r1, =0x01010101 + str r1, [r0, #0x0f4] +/* setmem /32 0x140000f8 = 0x00010101 */ + ldr r1, =0x00010101 + str r1, [r0, #0x0f8] +/* setmem /32 0x140000fc = 0x00000064 */ + ldr r1, =0x00000064 + str r1, [r0, #0x0fc] +/* setmem /32 0x14000104 = 0x02000602 */ + ldr r1, =0x02000602 + str r1, [r0, #0x0104] +/* setmem /32 0x14000108 = 0x06120000 */ + ldr r1, =0x06120000 + str r1, [r0, #0x0108] +/* setmem /32 0x1400010c = 0x06120612 */ + ldr r1, =0x06120612 + str r1, [r0, #0x010c] +/* setmem /32 0x14000110 = 0x06120612 */ + ldr r1, =0x06120612 + str r1, [r0, #0x0110] +/* setmem /32 0x14000114 = 0x01030612 */ + ldr r1, =0x01030612 + str r1, [r0, #0x0114] +/* setmem /32 0x14000118 = 0x01010002 */ + ldr r1, =0x01010002 + str r1, [r0, #0x0118] + +/*============================================================= + * DDR PHY setting + *===========================================================*/ + +/* setmem /32 0x14000200 = 0x00000000 */ + ldr r1, =0x00000000 + str r1, [r0, #0x200] +/* setmem /32 0x14000204 = 0x00000000 */ + ldr r1, =0x00000000 + str r1, [r0, #0x0204] + +/* setmem /32 0x14000208 = 0xf5002725 */ + ldr r1, =0xf5002725 + str r1, [r0, #0x0208] +/* setmem /32 0x14000210 = 0xf5002725 */ + ldr r1, =0xf5002725 + str r1, [r0, #0x210] +/* setmem /32 0x14000218 = 0xf5002725 */ + ldr r1, =0xf5002725 + str r1, [r0, #0x218] +/* setmem /32 0x14000220 = 0xf5002725 */ + ldr r1, =0xf5002725 + str r1, [r0, #0x0220] +/* setmem /32 0x14000228 = 0xf5002725 */ + ldr r1, =0xf5002725 + str r1, [r0, #0x0228] + +/* setmem /32 0x1400020c = 0x070002d0 */ + ldr r1, =0x070002d0 + str r1, [r0, #0x020c] + +/* setmem /32 0x14000214 = 0x074002d0 */ + ldr r1, =0x074002d0 + str r1, [r0, #0x0214] + +/* setmem /32 0x1400021c = 0x074002d0 */ + ldr r1, =0x074002d0 + str r1, [r0, #0x021c] + +/* setmem /32 0x14000224 = 0x074002d0 */ + ldr r1, =0x074002d0 + str r1, [r0, #0x0224] + +/* setmem /32 0x1400022c = 0x074002d0 */ + ldr r1, =0x074002d0 + str r1, [r0, #0x022c] +/* setmem /32 0x14000230 = 0x00000000 */ + ldr r1, =0x00000000 + str r1, [r0, #0x0230] +/* setmem /32 0x14000234 = 0x00800006 */ + ldr r1, =0x00800006 + str r1, [r0, #0x0234] + +/* setmem /32 0x14000238 = 0x200e1014 */ + ldr r1, =0x200e1014 + str r1, [r0, #0x0238] +/* setmem /32 0x14000240 = 0x200e1014 */ + ldr r1, =0x200e1014 + str r1, [r0, #0x0240] +/* setmem /32 0x14000248 = 0x200e1014 */ + ldr r1, =0x200e1014 + str r1, [r0, #0x0248] +/* setmem /32 0x14000250 = 0x200e1014 */ + ldr r1, =0x200e1014 + str r1, [r0, #0x0250] +/* setmem /32 0x14000258 = 0x200e1014 */ + ldr r1, =0x200e1014 + str r1, [r0, #0x0258] + +/* setmem /32 0x1400023c = 0x000d9f01 */ + ldr r1, =0x000d9f01 + str r1, [r0, #0x023c] +/* setmem /32 0x14000244 = 0x000d9f01 */ + ldr r1, =0x000d9f01 + str r1, [r0, #0x0244] +/* setmem /32 0x1400024c = 0x000d9f01 */ + ldr r1, =0x000d9f01 + str r1, [r0, #0x024c] +/* setmem /32 0x14000254 = 0x000d9f01 */ + ldr r1, =0x000d9f01 + str r1, [r0, #0x0254] +/* setmem /32 0x1400025c = 0x000d9f01 */ + ldr r1, =0x000d9f01 + str r1, [r0, #0x025c] + +/* Start ddr */ +/* setmem /32 0x14000000 = 0x00000101 // bit[0]: start */ + ldr r1, =0x00000101 + str r1, [r0, #0x0] +/* poll to make sure it is done */ +1: + ldr r1, [r0, #0xa8] + ands r1, r1, #0x10 + beq 1b + +#endif + +/* + * The following is to fill in those arguments for this ROM function + * pu_irom_hwcnfg_setup(void **start, size_t *bytes, const void *boot_data) + * + * This function is used to copy data from the storage media into DDR. + + * start - Initial (possibly partial) image load address on entry. + * Final image load address on exit. + * bytes - Initial (possibly partial) image size on entry. + * Final image size on exit. + * boot_data - Initial @ref ivt Boot Data load address. + */ + adr r0, DDR_DEST_ADDR + adr r1, COPY_SIZE + adr r2, BOOT_DATA + +before_calling_rom___pu_irom_hwcnfg_setup: + mov r4, #0x2a00 + add r4, r4, #0x19 + blx r4 // This address might change in future ROM versions +after_calling_rom___pu_irom_hwcnfg_setup: + + +/* To return to ROM from plugin, we need to fill in these argument. + * Here is what need to do: + * Need to construct the paramters for this function before return to ROM: + * plugin_download(void **start, size_t *bytes, UINT32 *ivt_offset) + */ + pop {r0-r2, lr} + ldr r3, DDR_DEST_ADDR + str r3, [r0] + ldr r3, COPY_SIZE + str r3, [r1] + mov r3, #0x400 /* Point to the second IVT table at offset 0x42C */ + add r3, r3, #0x2C + str r3, [r2] + mov r0, #1 + bx lr /* return back to ROM code */ + +DDR_DEST_ADDR: .word 0x77800000 +COPY_SIZE: .word 0x40000 +BOOT_DATA: .word 0x77800000 + .word 0x40000 /*data be copied by pu_irom_hwcnfg_setup()*/ + .word 0 + +#endif diff --git a/board/freescale/mx50_arm2/lowlevel_init.S b/board/freescale/mx50_arm2/lowlevel_init.S new file mode 100644 index 0000000000..4e031c71e0 --- /dev/null +++ b/board/freescale/mx50_arm2/lowlevel_init.S @@ -0,0 +1,207 @@ +/* + * Copyright (C) 2007, Guennadi Liakhovetski + * + * Copyright (C) 2010 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +/* + * L2CC Cache setup/invalidation/disable + */ +.macro init_l2cc + /* explicitly disable L2 cache */ + mrc 15, 0, r0, c1, c0, 1 + bic r0, r0, #0x2 + mcr 15, 0, r0, c1, c0, 1 + + /* reconfigure L2 cache aux control reg */ + mov r0, #0xC0 /* tag RAM */ + add r0, r0, #0x4 /* data RAM */ + orr r0, r0, #(1 << 24) /* disable write allocate delay */ + orr r0, r0, #(1 << 23) /* disable write allocate combine */ + orr r0, r0, #(1 << 22) /* disable write allocate */ + + mcr 15, 1, r0, c9, c0, 2 +.endm /* init_l2cc */ + +/* AIPS setup - Only setup MPROTx registers. + * The PACR default values are good.*/ +.macro init_aips + /* + * Set all MPROTx to be non-bufferable, trusted for R/W, + * not forced to user-mode. + */ + ldr r0, =AIPS1_BASE_ADDR + ldr r1, =0x77777777 + str r1, [r0, #0x0] + str r1, [r0, #0x4] + ldr r0, =AIPS2_BASE_ADDR + str r1, [r0, #0x0] + str r1, [r0, #0x4] +.endm /* init_aips */ + +.macro setup_pll pll, freq + ldr r0, =\pll + ldr r1, =0x00001232 + str r1, [r0, #PLL_DP_CTL] + mov r1, #0x2 + str r1, [r0, #PLL_DP_CONFIG] + + ldr r1, W_DP_OP_\freq + str r1, [r0, #PLL_DP_OP] + str r1, [r0, #PLL_DP_HFS_OP] + + ldr r1, W_DP_MFD_\freq + str r1, [r0, #PLL_DP_MFD] + str r1, [r0, #PLL_DP_HFS_MFD] + + ldr r1, W_DP_MFN_\freq + str r1, [r0, #PLL_DP_MFN] + str r1, [r0, #PLL_DP_HFS_MFN] + + ldr r1, =0x00001232 + str r1, [r0, #PLL_DP_CTL] +1: ldr r1, [r0, #PLL_DP_CTL] + ands r1, r1, #0x1 + beq 1b +.endm + +.macro init_clock + + setup_pll PLL3_BASE_ADDR, 400 + + /* Switch peripheral to PLL3 */ + /* Set periph_clk_sel[1:0]=0b10 to PLL3 */ + + ldr r0, CCM_BASE_ADDR_W + ldr r1, [r0, #CLKCTL_CBCDR] + orr r1, r1, #(3 << 25) + eor r1, r1, #(3 << 25) + orr r1, r1, #(2 << 25) + str r1, [r0, #CLKCTL_CBCDR] + + /* make sure change is effective */ +1: ldr r1, [r0, #CLKCTL_CDHIPR] + cmp r1, #0x0 + bne 1b + + setup_pll PLL2_BASE_ADDR, CONFIG_SYS_PLL2_FREQ + + /* Switch peripheral to PLL2 */ + /* Set periph_clk_sel[1:0]=0b01 to PLL2 */ + + ldr r0, CCM_BASE_ADDR_W + ldr r1, [r0, #CLKCTL_CBCDR] + orr r1, r1, #(3 << 25) + eor r1, r1, #(3 << 25) + orr r1, r1, #(1 << 25) + + orr r1, r1, #(CONFIG_SYS_AHB_PODF << 10) + orr r1, r1, #(CONFIG_SYS_AXIA_PODF << 16) + orr r1, r1, #(CONFIG_SYS_AXIB_PODF << 19) + str r1, [r0, #CLKCTL_CBCDR] + + /* make sure change is effective */ +1: ldr r1, [r0, #CLKCTL_CDHIPR] + cmp r1, #0x0 + bne 1b + + setup_pll PLL3_BASE_ADDR, 216 + + /* Set the platform clock dividers */ + ldr r0, PLATFORM_BASE_ADDR_W + ldr r1, PLATFORM_CLOCK_DIV_W + str r1, [r0, #PLATFORM_ICGC] + + /* ARM2 run at full speed */ + ldr r0, CCM_BASE_ADDR_W + mov r1, #0 + str r1, [r0, #CLKCTL_CACRR] + + /* make sure change is effective */ +1: ldr r1, [r0, #CLKCTL_CDHIPR] + cmp r1, #0x0 + bne 1b + + /* Restore the default values in the Gate registers */ + ldr r1, =0xFFFFFFFF + str r1, [r0, #CLKCTL_CCGR0] + str r1, [r0, #CLKCTL_CCGR1] + str r1, [r0, #CLKCTL_CCGR2] + str r1, [r0, #CLKCTL_CCGR3] + str r1, [r0, #CLKCTL_CCGR4] + str r1, [r0, #CLKCTL_CCGR5] + str r1, [r0, #CLKCTL_CCGR6] + str r1, [r0, #CLKCTL_CCGR7] + + /* for cko - for ARM div by 8 */ + mov r1, #0x000A0000 + add r1, r1, #0x00000F0 + str r1, [r0, #CLKCTL_CCOSR] +.endm + +.section ".text.init", "x" + +.globl lowlevel_init +lowlevel_init: + +#ifdef ENABLE_IMPRECISE_ABORT + mrs r1, spsr /* save old spsr */ + mrs r0, cpsr /* read out the cpsr */ + bic r0, r0, #0x100 /* clear the A bit */ + msr spsr, r0 /* update spsr */ + add lr, pc, #0x8 /* update lr */ + movs pc, lr /* update cpsr */ + nop + nop + nop + nop + msr spsr, r1 /* restore old spsr */ +#endif + + /* ARM errata ID #468414 */ + mrc 15, 0, r1, c1, c0, 1 + orr r1, r1, #(1 << 5) /* enable L1NEON bit */ + mcr 15, 0, r1, c1, c0, 1 + + init_l2cc + + init_aips + + init_clock /* not finished */ + + mov pc, lr + +/* Board level setting value */ +CCM_BASE_ADDR_W: .word CCM_BASE_ADDR +W_DP_OP_800: .word DP_OP_800 +W_DP_MFD_800: .word DP_MFD_800 +W_DP_MFN_800: .word DP_MFN_800 +W_DP_OP_600: .word DP_OP_600 +W_DP_MFD_600: .word DP_MFD_600 +W_DP_MFN_600: .word DP_MFN_600 +W_DP_OP_400: .word DP_OP_400 +W_DP_MFD_400: .word DP_MFD_400 +W_DP_MFN_400: .word DP_MFN_400 +W_DP_OP_216: .word DP_OP_216 +W_DP_MFD_216: .word DP_MFD_216 +W_DP_MFN_216: .word DP_MFN_216 +PLATFORM_BASE_ADDR_W: .word ARM_BASE_ADDR +PLATFORM_CLOCK_DIV_W: .word 0x00000124 diff --git a/board/freescale/mx50_arm2/mx50_arm2.c b/board/freescale/mx50_arm2/mx50_arm2.c new file mode 100644 index 0000000000..0494ea7ebd --- /dev/null +++ b/board/freescale/mx50_arm2/mx50_arm2.c @@ -0,0 +1,950 @@ +/* + * Copyright (C) 2007, Guennadi Liakhovetski + * + * (C) Copyright 2009-2010 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include + +#ifdef CONFIG_IMX_CSPI +#include +#include +#endif + +#if CONFIG_I2C_MXC +#include +#endif + +#ifdef CONFIG_CMD_MMC +#include +#include +#endif + +#ifdef CONFIG_ARCH_MMU +#include +#include +#endif + +#ifdef CONFIG_CMD_CLOCK +#include +#endif + +#ifdef CONFIG_MXC_EPDC +#include +#endif + +DECLARE_GLOBAL_DATA_PTR; + +static u32 system_rev; +static enum boot_device boot_dev; +u32 mx51_io_base_addr; + +static inline void setup_boot_device(void) +{ + uint soc_sbmr = readl(SRC_BASE_ADDR + 0x4); + uint bt_mem_ctl = (soc_sbmr & 0x000000FF) >> 4 ; + uint bt_mem_type = (soc_sbmr & 0x00000008) >> 3; + + switch (bt_mem_ctl) { + case 0x0: + if (bt_mem_type) + boot_dev = ONE_NAND_BOOT; + else + boot_dev = WEIM_NOR_BOOT; + break; + case 0x2: + if (bt_mem_type) + boot_dev = SATA_BOOT; + else + boot_dev = PATA_BOOT; + break; + case 0x3: + if (bt_mem_type) + boot_dev = SPI_NOR_BOOT; + else + boot_dev = I2C_BOOT; + break; + case 0x4: + case 0x5: + boot_dev = SD_BOOT; + break; + case 0x6: + case 0x7: + boot_dev = MMC_BOOT; + break; + case 0x8 ... 0xf: + boot_dev = NAND_BOOT; + break; + default: + boot_dev = UNKNOWN_BOOT; + break; + } +} + +enum boot_device get_boot_device(void) +{ + return boot_dev; +} + +u32 get_board_rev(void) +{ + return system_rev; +} + +static inline void setup_soc_rev(void) +{ + system_rev = 0x50000 | CHIP_REV_1_0; +} + +static inline void setup_board_rev(int rev) +{ + system_rev |= (rev & 0xF) << 8; +} + +inline int is_soc_rev(int rev) +{ + return (system_rev & 0xFF) - rev; +} + +#ifdef CONFIG_ARCH_MMU +void board_mmu_init(void) +{ + unsigned long ttb_base = PHYS_SDRAM_1 + 0x4000; + unsigned long i; + + /* + * Set the TTB register + */ + asm volatile ("mcr p15,0,%0,c2,c0,0" : : "r"(ttb_base) /*:*/); + + /* + * Set the Domain Access Control Register + */ + i = ARM_ACCESS_DACR_DEFAULT; + asm volatile ("mcr p15,0,%0,c3,c0,0" : : "r"(i) /*:*/); + + /* + * First clear all TT entries - ie Set them to Faulting + */ + memset((void *)ttb_base, 0, ARM_FIRST_LEVEL_PAGE_TABLE_SIZE); + /* Actual Virtual Size Attributes Function */ + /* Base Base MB cached? buffered? access permissions */ + /* xxx00000 xxx00000 */ + X_ARM_MMU_SECTION(0x000, 0x000, 0x10, + ARM_UNCACHEABLE, ARM_UNBUFFERABLE, + ARM_ACCESS_PERM_RW_RW); /* ROM, 16M */ + X_ARM_MMU_SECTION(0x070, 0x070, 0x010, + ARM_UNCACHEABLE, ARM_UNBUFFERABLE, + ARM_ACCESS_PERM_RW_RW); /* IRAM */ + X_ARM_MMU_SECTION(0x100, 0x100, 0x040, + ARM_UNCACHEABLE, ARM_UNBUFFERABLE, + ARM_ACCESS_PERM_RW_RW); /* SATA */ + X_ARM_MMU_SECTION(0x180, 0x180, 0x100, + ARM_UNCACHEABLE, ARM_UNBUFFERABLE, + ARM_ACCESS_PERM_RW_RW); /* IPUv3M */ + X_ARM_MMU_SECTION(0x200, 0x200, 0x200, + ARM_UNCACHEABLE, ARM_UNBUFFERABLE, + ARM_ACCESS_PERM_RW_RW); /* GPU */ + X_ARM_MMU_SECTION(0x400, 0x400, 0x300, + ARM_UNCACHEABLE, ARM_UNBUFFERABLE, + ARM_ACCESS_PERM_RW_RW); /* periperals */ + X_ARM_MMU_SECTION(0x700, 0x700, 0x400, + ARM_CACHEABLE, ARM_BUFFERABLE, + ARM_ACCESS_PERM_RW_RW); /* CSD0 1G */ + X_ARM_MMU_SECTION(0x700, 0xB00, 0x400, + ARM_UNCACHEABLE, ARM_UNBUFFERABLE, + ARM_ACCESS_PERM_RW_RW); /* CSD0 1G */ + X_ARM_MMU_SECTION(0xF00, 0xF00, 0x100, + ARM_UNCACHEABLE, ARM_UNBUFFERABLE, + ARM_ACCESS_PERM_RW_RW); /* CS1 EIM control*/ + X_ARM_MMU_SECTION(0xF80, 0xF80, 0x001, + ARM_UNCACHEABLE, ARM_UNBUFFERABLE, + ARM_ACCESS_PERM_RW_RW); /* iRam */ + + /* Workaround for arm errata #709718 */ + /* Setup PRRR so device is always mapped to non-shared */ + asm volatile ("mrc p15, 0, %0, c10, c2, 0" : "=r"(i) : /*:*/); + i &= (~(3 << 0x10)); + asm volatile ("mcr p15, 0, %0, c10, c2, 0" : : "r"(i) /*:*/); + + /* Enable MMU */ + MMU_ON(); +} +#endif + +int dram_init(void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + return 0; +} + +static void setup_uart(void) +{ + + /* UART1 RXD */ + mxc_request_iomux(MX50_PIN_UART1_RXD, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX50_PIN_UART1_RXD, 0x1E4); + mxc_iomux_set_input(MUX_IN_UART1_IPP_UART_RXD_MUX_SELECT_INPUT, 0x1); + + /* UART1 TXD */ + mxc_request_iomux(MX50_PIN_UART1_TXD, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX50_PIN_UART1_TXD, 0x1E4); +} + +#ifdef CONFIG_I2C_MXC +static void setup_i2c(unsigned int module_base) +{ + switch (module_base) { + case I2C1_BASE_ADDR: + /* i2c1 SDA */ + mxc_request_iomux(MX50_PIN_I2C1_SDA, + IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); + mxc_iomux_set_pad(MX50_PIN_I2C1_SDA, PAD_CTL_SRE_FAST | + PAD_CTL_ODE_OPENDRAIN_ENABLE | + PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU | + PAD_CTL_HYS_ENABLE); + /* i2c1 SCL */ + mxc_request_iomux(MX50_PIN_I2C1_SCL, + IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); + mxc_iomux_set_pad(MX50_PIN_I2C1_SCL, PAD_CTL_SRE_FAST | + PAD_CTL_ODE_OPENDRAIN_ENABLE | + PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU | + PAD_CTL_HYS_ENABLE); + break; + case I2C2_BASE_ADDR: + /* i2c2 SDA */ + mxc_request_iomux(MX50_PIN_I2C2_SDA, + IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); + mxc_iomux_set_pad(MX50_PIN_I2C2_SDA, + PAD_CTL_SRE_FAST | + PAD_CTL_ODE_OPENDRAIN_ENABLE | + PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU | + PAD_CTL_HYS_ENABLE); + + /* i2c2 SCL */ + mxc_request_iomux(MX50_PIN_I2C2_SCL, + IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); + mxc_iomux_set_pad(MX50_PIN_I2C2_SCL, + PAD_CTL_SRE_FAST | + PAD_CTL_ODE_OPENDRAIN_ENABLE | + PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU | + PAD_CTL_HYS_ENABLE); + break; + case I2C3_BASE_ADDR: + /* i2c3 SDA */ + mxc_request_iomux(MX50_PIN_I2C3_SDA, + IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); + mxc_iomux_set_pad(MX50_PIN_I2C3_SDA, + PAD_CTL_SRE_FAST | + PAD_CTL_ODE_OPENDRAIN_ENABLE | + PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU | + PAD_CTL_HYS_ENABLE); + + /* i2c3 SCL */ + mxc_request_iomux(MX50_PIN_I2C3_SCL, + IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); + mxc_iomux_set_pad(MX50_PIN_I2C3_SCL, + PAD_CTL_SRE_FAST | + PAD_CTL_ODE_OPENDRAIN_ENABLE | + PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU | + PAD_CTL_HYS_ENABLE); + break; + default: + printf("Invalid I2C base: 0x%x\n", module_base); + break; + } +} + +#endif + +#ifdef CONFIG_IMX_CSPI +s32 spi_get_cfg(struct imx_spi_dev_t *dev) +{ + switch (dev->slave.cs) { + case 0: + /* PMIC */ + dev->base = CSPI3_BASE_ADDR; + dev->freq = 25000000; + dev->ss_pol = IMX_SPI_ACTIVE_HIGH; + dev->ss = 0; + dev->fifo_sz = 32; + dev->us_delay = 0; + break; + case 1: + /* SPI-NOR */ + dev->base = CSPI3_BASE_ADDR; + dev->freq = 25000000; + dev->ss_pol = IMX_SPI_ACTIVE_LOW; + dev->ss = 1; + dev->fifo_sz = 32; + dev->us_delay = 0; + break; + default: + printf("Invalid Bus ID! \n"); + } + + return 0; +} + +void spi_io_init(struct imx_spi_dev_t *dev) +{ + switch (dev->base) { + case CSPI3_BASE_ADDR: + mxc_request_iomux(MX50_PIN_CSPI_MOSI, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX50_PIN_CSPI_MOSI, 0x4); + + mxc_request_iomux(MX50_PIN_CSPI_MISO, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX50_PIN_CSPI_MISO, 0x4); + + if (dev->ss == 0) { + /* de-select SS1 of instance: cspi */ + mxc_request_iomux(MX50_PIN_ECSPI1_MOSI, + IOMUX_CONFIG_ALT1); + + mxc_request_iomux(MX50_PIN_CSPI_SS0, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX50_PIN_CSPI_SS0, 0xE4); + } else if (dev->ss == 1) { + /* de-select SS0 of instance: cspi */ + mxc_request_iomux(MX50_PIN_CSPI_SS0, IOMUX_CONFIG_ALT1); + + mxc_request_iomux(MX50_PIN_ECSPI1_MOSI, + IOMUX_CONFIG_ALT2); + mxc_iomux_set_pad(MX50_PIN_ECSPI1_MOSI, 0xE4); + mxc_iomux_set_input( + MUX_IN_CSPI_IPP_IND_SS1_B_SELECT_INPUT, 0x1); + } + + mxc_request_iomux(MX50_PIN_CSPI_SCLK, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX50_PIN_CSPI_SCLK, 0x4); + break; + case CSPI2_BASE_ADDR: + case CSPI1_BASE_ADDR: + /* ecspi1-2 fall through */ + break; + default: + break; + } +} +#endif + +#ifdef CONFIG_MXC_FEC + +#ifdef CONFIG_GET_FEC_MAC_ADDR_FROM_IIM + +#define HW_OCOTP_MACn(n) (0x00000250 + (n) * 0x10) + +int fec_get_mac_addr(unsigned char *mac) +{ + u32 *ocotp_mac_base = + (u32 *)(OCOTP_CTRL_BASE_ADDR + HW_OCOTP_MACn(0)); + int i; + + for (i = 0; i < 6; ++i, ++ocotp_mac_base) + mac[6 - 1 - i] = readl(++ocotp_mac_base); + + return 0; +} +#endif + +static void setup_fec(void) +{ + volatile unsigned int reg; + + /*FEC_MDIO*/ + mxc_request_iomux(MX50_PIN_SSI_RXC, IOMUX_CONFIG_ALT6); + mxc_iomux_set_pad(MX50_PIN_SSI_RXC, 0xC); + mxc_iomux_set_input(MUX_IN_FEC_FEC_MDI_SELECT_INPUT, 0x1); + + /*FEC_MDC*/ + mxc_request_iomux(MX50_PIN_SSI_RXFS, IOMUX_CONFIG_ALT6); + mxc_iomux_set_pad(MX50_PIN_SSI_RXFS, 0x004); + + /* FEC RXD1 */ + mxc_request_iomux(MX50_PIN_DISP_D3, IOMUX_CONFIG_ALT2); + mxc_iomux_set_pad(MX50_PIN_DISP_D3, 0x0); + mxc_iomux_set_input(MUX_IN_FEC_FEC_RDATA_1_SELECT_INPUT, 0x0); + + /* FEC RXD0 */ + mxc_request_iomux(MX50_PIN_DISP_D4, IOMUX_CONFIG_ALT2); + mxc_iomux_set_pad(MX50_PIN_DISP_D4, 0x0); + mxc_iomux_set_input(MUX_IN_FEC_FEC_RDATA_0_SELECT_INPUT, 0x0); + + /* FEC TXD1 */ + mxc_request_iomux(MX50_PIN_DISP_D6, IOMUX_CONFIG_ALT2); + mxc_iomux_set_pad(MX50_PIN_DISP_D6, 0x004); + + /* FEC TXD0 */ + mxc_request_iomux(MX50_PIN_DISP_D7, IOMUX_CONFIG_ALT2); + mxc_iomux_set_pad(MX50_PIN_DISP_D7, 0x004); + + /* FEC TX_EN */ + mxc_request_iomux(MX50_PIN_DISP_D5, IOMUX_CONFIG_ALT2); + mxc_iomux_set_pad(MX50_PIN_DISP_D5, 0x004); + + /* FEC TX_CLK */ + mxc_request_iomux(MX50_PIN_DISP_D0, IOMUX_CONFIG_ALT2); + mxc_iomux_set_pad(MX50_PIN_DISP_D0, 0x0); + mxc_iomux_set_input(MUX_IN_FEC_FEC_TX_CLK_SELECT_INPUT, 0x0); + + /* FEC RX_ER */ + mxc_request_iomux(MX50_PIN_DISP_D1, IOMUX_CONFIG_ALT2); + mxc_iomux_set_pad(MX50_PIN_DISP_D1, 0x0); + mxc_iomux_set_input(MUX_IN_FEC_FEC_RX_ER_SELECT_INPUT, 0); + + /* FEC CRS */ + mxc_request_iomux(MX50_PIN_DISP_D2, IOMUX_CONFIG_ALT2); + mxc_iomux_set_pad(MX50_PIN_DISP_D2, 0x0); + mxc_iomux_set_input(MUX_IN_FEC_FEC_RX_DV_SELECT_INPUT, 0); + + /* phy reset: gpio4-6 */ + mxc_request_iomux(MX50_PIN_KEY_COL3, IOMUX_CONFIG_ALT1); + + reg = readl(GPIO4_BASE_ADDR + 0x0); + reg &= ~0x40; + writel(reg, GPIO4_BASE_ADDR + 0x0); + + reg = readl(GPIO4_BASE_ADDR + 0x4); + reg |= 0x40; + writel(reg, GPIO4_BASE_ADDR + 0x4); + + udelay(500); + + reg = readl(GPIO4_BASE_ADDR + 0x0); + reg |= 0x40; + writel(reg, GPIO4_BASE_ADDR + 0x0); +} +#endif + +#ifdef CONFIG_CMD_MMC + +struct fsl_esdhc_cfg esdhc_cfg[3] = { + {MMC_SDHC1_BASE_ADDR, 1, 1}, + {MMC_SDHC2_BASE_ADDR, 1, 1}, + {MMC_SDHC3_BASE_ADDR, 1, 1}, +}; + + +#ifdef CONFIG_DYNAMIC_MMC_DEVNO +int get_mmc_env_devno() +{ + uint soc_sbmr = readl(SRC_BASE_ADDR + 0x4); + int mmc_devno = 0; + + switch (soc_sbmr & 0x00300000) { + default: + case 0x0: + mmc_devno = 0; + break; + case 0x00100000: + mmc_devno = 1; + break; + case 0x00200000: + mmc_devno = 2; + break; + } + + return mmc_devno; +} +#endif + + +int esdhc_gpio_init(bd_t *bis) +{ + s32 status = 0; + u32 index = 0; + + for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; + ++index) { + switch (index) { + case 0: + mxc_request_iomux(MX50_PIN_SD1_CMD, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX50_PIN_SD1_CLK, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX50_PIN_SD1_D0, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX50_PIN_SD1_D1, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX50_PIN_SD1_D2, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX50_PIN_SD1_D3, IOMUX_CONFIG_ALT0); + + mxc_iomux_set_pad(MX50_PIN_SD1_CMD, 0x1E4); + mxc_iomux_set_pad(MX50_PIN_SD1_CLK, 0xD4); + mxc_iomux_set_pad(MX50_PIN_SD1_D0, 0x1D4); + mxc_iomux_set_pad(MX50_PIN_SD1_D1, 0x1D4); + mxc_iomux_set_pad(MX50_PIN_SD1_D2, 0x1D4); + mxc_iomux_set_pad(MX50_PIN_SD1_D3, 0x1D4); + + break; + case 1: + mxc_request_iomux(MX50_PIN_SD2_CMD, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX50_PIN_SD2_CLK, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX50_PIN_SD2_D0, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX50_PIN_SD2_D1, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX50_PIN_SD2_D2, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX50_PIN_SD2_D3, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX50_PIN_SD2_D4, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX50_PIN_SD2_D5, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX50_PIN_SD2_D6, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX50_PIN_SD2_D7, IOMUX_CONFIG_ALT0); + + mxc_iomux_set_pad(MX50_PIN_SD2_CMD, 0x14); + mxc_iomux_set_pad(MX50_PIN_SD2_CLK, 0xD4); + mxc_iomux_set_pad(MX50_PIN_SD2_D0, 0x1D4); + mxc_iomux_set_pad(MX50_PIN_SD2_D1, 0x1D4); + mxc_iomux_set_pad(MX50_PIN_SD2_D2, 0x1D4); + mxc_iomux_set_pad(MX50_PIN_SD2_D3, 0x1D4); + mxc_iomux_set_pad(MX50_PIN_SD2_D4, 0x1D4); + mxc_iomux_set_pad(MX50_PIN_SD2_D5, 0x1D4); + mxc_iomux_set_pad(MX50_PIN_SD2_D6, 0x1D4); + mxc_iomux_set_pad(MX50_PIN_SD2_D7, 0x1D4); + + break; + case 2: + mxc_request_iomux(MX50_PIN_SD3_CMD, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX50_PIN_SD3_CLK, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX50_PIN_SD3_D0, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX50_PIN_SD3_D1, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX50_PIN_SD3_D2, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX50_PIN_SD3_D3, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX50_PIN_SD3_D4, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX50_PIN_SD3_D5, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX50_PIN_SD3_D6, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX50_PIN_SD3_D7, IOMUX_CONFIG_ALT0); + + mxc_iomux_set_pad(MX50_PIN_SD3_CMD, 0x1E4); + mxc_iomux_set_pad(MX50_PIN_SD3_CLK, 0xD4); + mxc_iomux_set_pad(MX50_PIN_SD3_D0, 0x1D4); + mxc_iomux_set_pad(MX50_PIN_SD3_D1, 0x1D4); + mxc_iomux_set_pad(MX50_PIN_SD3_D2, 0x1D4); + mxc_iomux_set_pad(MX50_PIN_SD3_D3, 0x1D4); + mxc_iomux_set_pad(MX50_PIN_SD3_D4, 0x1D4); + mxc_iomux_set_pad(MX50_PIN_SD3_D5, 0x1D4); + mxc_iomux_set_pad(MX50_PIN_SD3_D6, 0x1D4); + mxc_iomux_set_pad(MX50_PIN_SD3_D7, 0x1D4); + + break; + default: + printf("Warning: you configured more ESDHC controller" + "(%d) as supported by the board(2)\n", + CONFIG_SYS_FSL_ESDHC_NUM); + return status; + break; + } + status |= fsl_esdhc_initialize(bis, &esdhc_cfg[index]); + } + + return status; +} + +int board_mmc_init(bd_t *bis) +{ + if (!esdhc_gpio_init(bis)) + return 0; + else + return -1; +} + +#endif + +#ifdef CONFIG_MXC_EPDC +#ifdef CONFIG_SPLASH_SCREEN +int setup_splash_img() +{ +#ifdef CONFIG_SPLASH_IS_IN_MMC + int mmc_dev = get_mmc_env_devno(); + ulong offset = CONFIG_SPLASH_IMG_OFFSET; + ulong size = CONFIG_SPLASH_IMG_SIZE; + ulong addr = 0; + char *s = NULL; + struct mmc *mmc = find_mmc_device(mmc_dev); + uint blk_start, blk_cnt, n; + + s = getenv("splashimage"); + + if (NULL == s) { + puts("env splashimage not found!\n"); + return -1; + } + addr = simple_strtoul(s, NULL, 16); + + if (!mmc) { + printf("MMC Device %d not found\n", + mmc_dev); + return -1; + } + + if (mmc_init(mmc)) { + puts("MMC init failed\n"); + return -1; + } + + blk_start = ALIGN(offset, mmc->read_bl_len) / mmc->read_bl_len; + blk_cnt = ALIGN(size, mmc->read_bl_len) / mmc->read_bl_len; + n = mmc->block_dev.block_read(mmc_dev, blk_start, + blk_cnt, (u_char *)addr); + flush_cache((ulong)addr, blk_cnt * mmc->read_bl_len); + + return (n == blk_cnt) ? 0 : -1; +#endif +} +#endif + +vidinfo_t panel_info = { + .vl_refresh = 60, + .vl_col = 800, + .vl_row = 600, + .vl_pixclock = 17700000, + .vl_left_margin = 8, + .vl_right_margin = 142, + .vl_upper_margin = 4, + .vl_lower_margin = 10, + .vl_hsync = 20, + .vl_vsync = 4, + .vl_sync = 0, + .vl_mode = 0, + .vl_flag = 0, + .vl_bpix = 3, + cmap:0, +}; + +static void setup_epdc_power() +{ + unsigned int reg; + + /* Setup epdc voltage */ + + /* EPDC PWRSTAT - GPIO3[28] for PWR_GOOD status */ + mxc_request_iomux(MX50_PIN_EPDC_PWRSTAT, IOMUX_CONFIG_ALT1); + + /* EPDC VCOM0 - GPIO4[21] for VCOM control */ + mxc_request_iomux(MX50_PIN_EPDC_VCOM0, IOMUX_CONFIG_ALT1); + /* Set as output */ + reg = readl(GPIO4_BASE_ADDR + 0x4); + reg |= (1 << 21); + writel(reg, GPIO4_BASE_ADDR + 0x4); + + /* UART4 TXD - GPIO6[16] for EPD PMIC WAKEUP */ + mxc_request_iomux(MX50_PIN_UART4_TXD, IOMUX_CONFIG_ALT1); + /* Set as output */ + reg = readl(GPIO6_BASE_ADDR + 0x4); + reg |= (1 << 16); + writel(reg, GPIO6_BASE_ADDR + 0x4); +} + +void epdc_power_on() +{ + unsigned int reg; + + /* Set PMIC Wakeup to high - enable Display power */ + reg = readl(GPIO6_BASE_ADDR + 0x0); + reg |= (1 << 16); + writel(reg, GPIO6_BASE_ADDR + 0x0); + + /* Wait for PWRGOOD == 1 */ + while (1) { + reg = readl(GPIO3_BASE_ADDR + 0x0); + if (!(reg & (1 << 28))) + break; + + udelay(100); + } + + /* Enable VCOM */ + reg = readl(GPIO4_BASE_ADDR + 0x0); + reg |= (1 << 21); + writel(reg, GPIO4_BASE_ADDR + 0x0); + + reg = readl(GPIO4_BASE_ADDR + 0x0); + + udelay(500); +} + +void epdc_power_off() +{ + unsigned int reg; + /* Set PMIC Wakeup to low - disable Display power */ + reg = readl(GPIO6_BASE_ADDR + 0x0); + reg |= 0 << 16; + writel(reg, GPIO6_BASE_ADDR + 0x0); + + /* Disable VCOM */ + reg = readl(GPIO4_BASE_ADDR + 0x0); + reg |= 0 << 21; + writel(reg, GPIO4_BASE_ADDR + 0x0); +} + +int setup_waveform_file() +{ +#ifdef CONFIG_WAVEFORM_FILE_IN_MMC + int mmc_dev = get_mmc_env_devno(); + ulong offset = CONFIG_WAVEFORM_FILE_OFFSET; + ulong size = CONFIG_WAVEFORM_FILE_SIZE; + ulong addr = CONFIG_WAVEFORM_BUF_ADDR; + char *s = NULL; + struct mmc *mmc = find_mmc_device(mmc_dev); + uint blk_start, blk_cnt, n; + + if (!mmc) { + printf("MMC Device %d not found\n", + mmc_dev); + return -1; + } + + if (mmc_init(mmc)) { + puts("MMC init failed\n"); + return -1; + } + + blk_start = ALIGN(offset, mmc->read_bl_len) / mmc->read_bl_len; + blk_cnt = ALIGN(size, mmc->read_bl_len) / mmc->read_bl_len; + n = mmc->block_dev.block_read(mmc_dev, blk_start, + blk_cnt, (u_char *)addr); + flush_cache((ulong)addr, blk_cnt * mmc->read_bl_len); + + return (n == blk_cnt) ? 0 : -1; +#else + return -1; +#endif +} + +static void setup_epdc() +{ + unsigned int reg; + + /* epdc iomux settings */ + mxc_request_iomux(MX50_PIN_EPDC_D0, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX50_PIN_EPDC_D1, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX50_PIN_EPDC_D2, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX50_PIN_EPDC_D3, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX50_PIN_EPDC_D4, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX50_PIN_EPDC_D5, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX50_PIN_EPDC_D6, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX50_PIN_EPDC_D7, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX50_PIN_EPDC_GDCLK, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX50_PIN_EPDC_GDSP, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX50_PIN_EPDC_GDOE, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX50_PIN_EPDC_GDRL, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX50_PIN_EPDC_SDCLK, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX50_PIN_EPDC_SDOE, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX50_PIN_EPDC_SDLE, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX50_PIN_EPDC_SDSHR, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX50_PIN_EPDC_BDR0, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX50_PIN_EPDC_SDCE0, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX50_PIN_EPDC_SDCE1, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX50_PIN_EPDC_SDCE2, IOMUX_CONFIG_ALT0); + + + /*** epdc Maxim PMIC settings ***/ + + /* EPDC PWRSTAT - GPIO3[28] for PWR_GOOD status */ + mxc_request_iomux(MX50_PIN_EPDC_PWRSTAT, IOMUX_CONFIG_ALT1); + + /* EPDC VCOM0 - GPIO4[21] for VCOM control */ + mxc_request_iomux(MX50_PIN_EPDC_VCOM0, IOMUX_CONFIG_ALT1); + + /* UART4 TXD - GPIO6[16] for EPD PMIC WAKEUP */ + mxc_request_iomux(MX50_PIN_UART4_TXD, IOMUX_CONFIG_ALT1); + + + /*** Set pixel clock rates for EPDC ***/ + + /* EPDC AXI clk and EPDC PIX clk from PLL1 */ + reg = readl(CCM_BASE_ADDR + CLKCTL_CLKSEQ_BYPASS); + reg &= ~(0x3 << 4); + reg |= (0x2 << 4) | (0x2 << 12); + writel(reg, CCM_BASE_ADDR + CLKCTL_CLKSEQ_BYPASS); + + /* EPDC AXI clk enable and set to 200MHz (800/4) */ + reg = readl(CCM_BASE_ADDR + 0xA8); + reg &= ~((0x3 << 30) | 0x3F); + reg |= (0x2 << 30) | 0x4; + writel(reg, CCM_BASE_ADDR + 0xA8); + + /* EPDC PIX clk enable and set to 20MHz (800/40) */ + reg = readl(CCM_BASE_ADDR + 0xA0); + reg &= ~((0x3 << 30) | (0x3 << 12) | 0x3F); + reg |= (0x2 << 30) | (0x1 << 12) | 0x2D; + writel(reg, CCM_BASE_ADDR + 0xA0); + + panel_info.epdc_data.working_buf_addr = CONFIG_WORKING_BUF_ADDR; + panel_info.epdc_data.waveform_buf_addr = CONFIG_WAVEFORM_BUF_ADDR; + + panel_info.epdc_data.wv_modes.mode_init = 0; + panel_info.epdc_data.wv_modes.mode_du = 1; + panel_info.epdc_data.wv_modes.mode_gc4 = 3; + panel_info.epdc_data.wv_modes.mode_gc8 = 2; + panel_info.epdc_data.wv_modes.mode_gc16 = 2; + panel_info.epdc_data.wv_modes.mode_gc32 = 2; + + setup_epdc_power(); + + /* Assign fb_base */ + gd->fb_base = CONFIG_FB_BASE; +} +#endif + +#ifdef CONFIG_IMX_CSPI +static void setup_power(void) +{ + struct spi_slave *slave; + unsigned int val; + unsigned int reg; + + puts("PMIC Mode: SPI\n"); + + /* Enable VGEN1 to enable ethernet */ + slave = spi_pmic_probe(); + + val = pmic_reg(slave, 30, 0, 0); + val |= 0x3; + pmic_reg(slave, 30, val, 1); + + val = pmic_reg(slave, 32, 0, 0); + val |= 0x1; + pmic_reg(slave, 32, val, 1); + + /* Enable VCAM */ + val = pmic_reg(slave, 33, 0, 0); + val |= 0x40; + pmic_reg(slave, 33, val, 1); + + spi_pmic_free(slave); +} + +void setup_voltage_cpu(void) +{ + /* Currently VDDGP 1.05v + * no one tell me we need increase the core + * voltage to let CPU run at 800Mhz, not do it + */ + + /* Raise the core frequency to 800MHz */ + writel(0x0, CCM_BASE_ADDR + CLKCTL_CACRR); + +} +#endif + +int board_init(void) +{ +#ifdef CONFIG_MFG +/* MFG firmware need reset usb to avoid host crash firstly */ +#define USBCMD 0x140 + int val = readl(OTG_BASE_ADDR + USBCMD); + val &= ~0x1; /*RS bit*/ + writel(val, OTG_BASE_ADDR + USBCMD); +#endif + /* boot device */ + setup_boot_device(); + + /* soc rev */ + setup_soc_rev(); + + /* arch id for linux */ + gd->bd->bi_arch_number = MACH_TYPE_MX50_ARM2; + + /* boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; + + /* iomux for uart */ + setup_uart(); + +#ifdef CONFIG_MXC_FEC + /* iomux for fec */ + setup_fec(); +#endif + +#ifdef CONFIG_MXC_EPDC + setup_epdc(); +#endif + + return 0; +} + +int board_late_init(void) +{ +#ifdef CONFIG_IMX_CSPI + setup_power(); +#endif + return 0; +} + +int checkboard(void) +{ + printf("Board: MX50 ARM2 board\n"); + + printf("Boot Reason: ["); + + switch (__REG(SRC_BASE_ADDR + 0x8)) { + case 0x0001: + printf("POR"); + break; + case 0x0009: + printf("RST"); + break; + case 0x0010: + case 0x0011: + printf("WDOG"); + break; + default: + printf("unknown"); + } + printf("]\n"); + + printf("Boot Device: "); + switch (get_boot_device()) { + case WEIM_NOR_BOOT: + printf("NOR\n"); + break; + case ONE_NAND_BOOT: + printf("ONE NAND\n"); + break; + case PATA_BOOT: + printf("PATA\n"); + break; + case SATA_BOOT: + printf("SATA\n"); + break; + case I2C_BOOT: + printf("I2C\n"); + break; + case SPI_NOR_BOOT: + printf("SPI NOR\n"); + break; + case SD_BOOT: + printf("SD\n"); + break; + case MMC_BOOT: + printf("MMC\n"); + break; + case NAND_BOOT: + printf("NAND\n"); + break; + case UNKNOWN_BOOT: + default: + printf("UNKNOWN\n"); + break; + } + + return 0; +} diff --git a/board/freescale/mx50_arm2/u-boot.lds b/board/freescale/mx50_arm2/u-boot.lds new file mode 100644 index 0000000000..07478dd837 --- /dev/null +++ b/board/freescale/mx50_arm2/u-boot.lds @@ -0,0 +1,73 @@ +/* + * January 2004 - Changed to support H4 device + * Copyright (c) 2004 Texas Instruments + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * (C) Copyright 2010 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + board/freescale/mx50_arm2/flash_header.o (.text.flasheader) + cpu/arm_cortexa8/start.o + board/freescale/mx50_arm2/libmx50_arm2.a (.text) + lib_arm/libarm.a (.text) + net/libnet.a (.text) + drivers/mtd/libmtd.a (.text) + drivers/mmc/libmmc.a (.text) + + . = DEFINED(env_offset) ? env_offset : .; + common/env_embedded.o(.text) + + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} diff --git a/board/freescale/mx51_3stack/Makefile b/board/freescale/mx51_3stack/Makefile new file mode 100644 index 0000000000..f665a2db4e --- /dev/null +++ b/board/freescale/mx51_3stack/Makefile @@ -0,0 +1,49 @@ +# +# Copyright (C) 2007, Guennadi Liakhovetski +# +# (C) Copyright 2009 Freescale Semiconductor, Inc. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := mx51_3stack.o +SOBJS := lowlevel_init.o flash_header.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/freescale/mx51_3stack/board-mx51_3stack.h b/board/freescale/mx51_3stack/board-mx51_3stack.h new file mode 100644 index 0000000000..d7c30c1c34 --- /dev/null +++ b/board/freescale/mx51_3stack/board-mx51_3stack.h @@ -0,0 +1,64 @@ +/* + * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#ifndef __BOARD_FREESCALE_BOARD_MX51_3STACK_H__ +#define __BOARD_FREESCALE_BOARD_MX51_3STACK_H__ + +/*! + * @defgroup BRDCFG_MX51 Board Configuration Options + * @ingroup MSL_MX51 + */ + +/*! + * @file mx51_3stack/board-mx51_3stack.h + * + * @brief This file contains all the board level configuration options. + * + * It currently hold the options defined for MX51 3Stack Platform. + * + * @ingroup BRDCFG_MX51 + */ + +/* CPLD offsets */ +#define PBC_LED_CTRL (0x20000) +#define PBC_SB_STAT (0x20008) +#define PBC_ID_AAAA (0x20040) +#define PBC_ID_5555 (0x20048) +#define PBC_VERSION (0x20050) +#define PBC_ID_CAFE (0x20058) +#define PBC_INT_STAT (0x20010) +#define PBC_INT_MASK (0x20038) +#define PBC_INT_REST (0x20020) +#define PBC_SW_RESET (0x20060) + +/* LED switchs */ +#define LED_SWITCH_REG 0x00 +/* buttons */ +#define SWITCH_BUTTONS_REG 0x08 +/* status, interrupt */ +#define INTR_STATUS_REG 0x10 +#define INTR_MASK_REG 0x38 +#define INTR_RESET_REG 0x20 +/* magic word for debug CPLD */ +#define MAGIC_NUMBER1_REG 0x40 +#define MAGIC_NUMBER2_REG 0x48 +/* CPLD code version */ +#define CPLD_CODE_VER_REG 0x50 +/* magic word for debug CPLD */ +#define MAGIC_NUMBER3_REG 0x58 +/* module reset register*/ +#define MODULE_RESET_REG 0x60 +/* CPU ID and Personality ID */ +#define MCU_BOARD_ID_REG 0x68 + +#endif /* __BOARD_FREESCALE_BOARD_MX51_3STACK_H__ */ diff --git a/board/freescale/mx51_3stack/config.mk b/board/freescale/mx51_3stack/config.mk new file mode 100644 index 0000000000..705aa34f28 --- /dev/null +++ b/board/freescale/mx51_3stack/config.mk @@ -0,0 +1,3 @@ +LDSCRIPT := $(SRCTREE)/board/$(VENDOR)/$(BOARD)/u-boot.lds + +TEXT_BASE = 0x97800000 diff --git a/board/freescale/mx51_3stack/flash_header.S b/board/freescale/mx51_3stack/flash_header.S new file mode 100644 index 0000000000..bbfa474bc2 --- /dev/null +++ b/board/freescale/mx51_3stack/flash_header.S @@ -0,0 +1,113 @@ +/* + * Copyright 2009 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include "board-mx51_3stack.h" + +#ifdef CONFIG_FLASH_HEADER +#ifndef CONFIG_FLASH_HEADER_OFFSET +# error "Must define the offset of flash header" +#endif +#define MXC_DCD_ITEM(i, type, addr, val) \ +dcd_node_##i: \ + .word type ; \ + .word addr ; \ + .word val ; \ + +.section ".text.flasheader", "x" + b _start + .org CONFIG_FLASH_HEADER_OFFSET +app_code_jump_v: .word _start +app_code_code_barker: .word CONFIG_FLASH_HEADER_BARKER +app_code_csf: .word 0 +dcd_ptr_ptr: .word dcd_ptr +super_root_key: .word 0 +dcd_ptr: .word dcd_array_start +app_dest_ptr: .word TEXT_BASE +dcd_array_start: +magic: .word 0xB17219E9 +dcd_array_size: .word dcd_data_end - dcd_array_start - 8 +/* DCD */ +/* DDR2 IOMUX configuration */ +MXC_DCD_ITEM(1, 4, IOMUXC_BASE_ADDR + 0x8a0, 0x200) +MXC_DCD_ITEM(2, 4, IOMUXC_BASE_ADDR + 0x50c, 0x20c5) +MXC_DCD_ITEM(3, 4, IOMUXC_BASE_ADDR + 0x510, 0x20c5) +MXC_DCD_ITEM(4, 4, IOMUXC_BASE_ADDR + 0x83c, 0x2) +MXC_DCD_ITEM(5, 4, IOMUXC_BASE_ADDR + 0x848, 0x2) +MXC_DCD_ITEM(6, 4, IOMUXC_BASE_ADDR + 0x4b8, 0xe7) +MXC_DCD_ITEM(7, 4, IOMUXC_BASE_ADDR + 0x4bc, 0x45) +MXC_DCD_ITEM(8, 4, IOMUXC_BASE_ADDR + 0x4c0, 0x45) +MXC_DCD_ITEM(9, 4, IOMUXC_BASE_ADDR + 0x4c4, 0x45) +MXC_DCD_ITEM(10, 4, IOMUXC_BASE_ADDR + 0x4c8, 0x45) +MXC_DCD_ITEM(11, 4, IOMUXC_BASE_ADDR + 0x820, 0x0) +MXC_DCD_ITEM(12, 4, IOMUXC_BASE_ADDR + 0x4a4, 0x3) +MXC_DCD_ITEM(13, 4, IOMUXC_BASE_ADDR + 0x4a8, 0x3) +MXC_DCD_ITEM(14, 4, IOMUXC_BASE_ADDR + 0x4ac, 0xe3) +MXC_DCD_ITEM(15, 4, IOMUXC_BASE_ADDR + 0x4b0, 0xe3) +MXC_DCD_ITEM(16, 4, IOMUXC_BASE_ADDR + 0x4b4, 0xe3) +MXC_DCD_ITEM(17, 4, IOMUXC_BASE_ADDR + 0x4cc, 0xe3) +MXC_DCD_ITEM(18, 4, IOMUXC_BASE_ADDR + 0x4d0, 0xe2) +/* Set drive strength to MAX */ +MXC_DCD_ITEM(19, 4, IOMUXC_BASE_ADDR + 0x82c, 0x6) +MXC_DCD_ITEM(20, 4, IOMUXC_BASE_ADDR + 0x8a4, 0x6) +MXC_DCD_ITEM(21, 4, IOMUXC_BASE_ADDR + 0x8ac, 0x6) +MXC_DCD_ITEM(22, 4, IOMUXC_BASE_ADDR + 0x8b8, 0x6) +/* 13 ROW, 10 COL, 32Bit, SREF=4 Micron Model */ +/* CAS=3, BL=4 */ +MXC_DCD_ITEM(23, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCTL0, 0x82a20000) +MXC_DCD_ITEM(24, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCTL1, 0x82a20000) +MXC_DCD_ITEM(25, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDMISC, 0x000ad0d0) +MXC_DCD_ITEM(26, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCFG0, 0x333574aa) +MXC_DCD_ITEM(27, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCFG1, 0x333574aa) +/* Init DRAM on CS0 */ +MXC_DCD_ITEM(28, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x04008008) +MXC_DCD_ITEM(29, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0000801a) +MXC_DCD_ITEM(30, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0000801b) +MXC_DCD_ITEM(31, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00448019) +MXC_DCD_ITEM(32, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x07328018) +MXC_DCD_ITEM(33, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x04008008) +MXC_DCD_ITEM(34, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008010) +MXC_DCD_ITEM(35, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008010) +MXC_DCD_ITEM(36, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x06328018) +MXC_DCD_ITEM(37, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x03808019) +MXC_DCD_ITEM(38, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00408019) +MXC_DCD_ITEM(39, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008000) +/* Init DRAM on CS1 */ +MXC_DCD_ITEM(40, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0400800c) +MXC_DCD_ITEM(41, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0000801e) +MXC_DCD_ITEM(42, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0000801f) +MXC_DCD_ITEM(43, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0000801d) +MXC_DCD_ITEM(44, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0732801c) +MXC_DCD_ITEM(45, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0400800c) +MXC_DCD_ITEM(46, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008014) +MXC_DCD_ITEM(47, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008014) +MXC_DCD_ITEM(48, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0632801c) +MXC_DCD_ITEM(49, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0380801d) +MXC_DCD_ITEM(50, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0040801d) +MXC_DCD_ITEM(51, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008004) +MXC_DCD_ITEM(52, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCTL0, 0xb2a20000) +MXC_DCD_ITEM(53, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCTL1, 0xb2a20000) +MXC_DCD_ITEM(54, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDMISC, 0x000ad6d0) +MXC_DCD_ITEM(55, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCDLYGD, 0x90000000) +MXC_DCD_ITEM(56, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00000000) +dcd_data_end: +//image_len: .word 0x80000 +image_len: .word __u_boot_cmd_end - TEXT_BASE +#endif diff --git a/board/freescale/mx51_3stack/lowlevel_init.S b/board/freescale/mx51_3stack/lowlevel_init.S new file mode 100644 index 0000000000..b473f06940 --- /dev/null +++ b/board/freescale/mx51_3stack/lowlevel_init.S @@ -0,0 +1,365 @@ +/* + * Copyright (C) 2007, Guennadi Liakhovetski + * + * (C) Copyright 2009-2010 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include "board-mx51_3stack.h" + +/* + * return soc version + * 0x10: TO1 + * 0x20: TO2 + * 0x30: TO3 + */ +.macro check_soc_version ret, tmp +.endm + +/* + * L2CC Cache setup/invalidation/disable + */ +.macro init_l2cc + /* explicitly disable L2 cache */ + mrc 15, 0, r0, c1, c0, 1 + bic r0, r0, #0x2 + mcr 15, 0, r0, c1, c0, 1 + + /* reconfigure L2 cache aux control reg */ + mov r0, #0xC0 /* tag RAM */ + add r0, r0, #0x4 /* data RAM */ + orr r0, r0, #(1 << 24) /* disable write allocate delay */ + orr r0, r0, #(1 << 23) /* disable write allocate combine */ + orr r0, r0, #(1 << 22) /* disable write allocate */ + + ldr r1, =0x00000000 + ldr r3, [r1, #ROM_SI_REV] + cmp r3, #0x10 /* r3 contains the silicon rev */ + /* disable write combine for TO 2 and lower */ + orrls r0, r0, #(1 << 25) + + mcr 15, 1, r0, c9, c0, 2 +.endm /* init_l2cc */ + +/* AIPS setup - Only setup MPROTx registers. + * The PACR default values are good.*/ +.macro init_aips + /* + * Set all MPROTx to be non-bufferable, trusted for R/W, + * not forced to user-mode. + */ + ldr r0, =AIPS1_BASE_ADDR + ldr r1, =0x77777777 + str r1, [r0, #0x0] + str r1, [r0, #0x4] + ldr r0, =AIPS2_BASE_ADDR + str r1, [r0, #0x0] + str r1, [r0, #0x4] + /* + * Clear the on and off peripheral modules Supervisor Protect bit + * for SDMA to access them. Did not change the AIPS control registers + * (offset 0x20) access type + */ +.endm /* init_aips */ + +/* MAX (Multi-Layer AHB Crossbar Switch) setup */ +.macro init_max +.endm /* init_max */ + +/* M4IF setup */ +.macro init_m4if + /* VPU and IPU given higher priority (0x4) + * IPU accesses with ID=0x1 given highest priority (=0xA) + */ + ldr r0, =M4IF_BASE_ADDR + + ldr r1, =0x00000203 + str r1, [r0, #0x40] + + ldr r1, =0x0 + str r1, [r0, #0x44] + + ldr r1, =0x00120125 + str r1, [r0, #0x9C] + + ldr r1, =0x001901A3 + str r1, [r0, #0x48] +.endm /* init_m4if */ + +/* To support 133MHz DDR */ +.macro init_drive_strength +.endm /* init_drive_strength */ + +/* CPLD on CS5 setup */ +.macro init_debug_board +.endm /* init_debug_board */ + +.macro setup_pll pll, freq + ldr r2, =\pll + ldr r1, =0x00001232 + str r1, [r2, #PLL_DP_CTL] /* Set DPLL ON (set UPEN bit): BRMO=1 */ + mov r1, #0x2 + str r1, [r2, #PLL_DP_CONFIG] /* Enable auto-restart AREN bit */ + + str r3, [r2, #PLL_DP_OP] + str r3, [r2, #PLL_DP_HFS_OP] + + str r4, [r2, #PLL_DP_MFD] + str r4, [r2, #PLL_DP_HFS_MFD] + + str r5, [r2, #PLL_DP_MFN] + str r5, [r2, #PLL_DP_HFS_MFN] + + ldr r1, =0x00001232 + str r1, [r2, #PLL_DP_CTL] +1: ldr r1, [r2, #PLL_DP_CTL] + ands r1, r1, #0x1 + beq 1b +.endm + +.macro init_clock + ldr r0, =CCM_BASE_ADDR + + /* Gate of clocks to the peripherals first */ + ldr r1, =0x3FFFFFFF + str r1, [r0, #CLKCTL_CCGR0] + ldr r1, =0x0 + str r1, [r0, #CLKCTL_CCGR1] + str r1, [r0, #CLKCTL_CCGR2] + str r1, [r0, #CLKCTL_CCGR3] + + ldr r1, =0x00030000 + str r1, [r0, #CLKCTL_CCGR4] + ldr r1, =0x00FFF030 + str r1, [r0, #CLKCTL_CCGR5] + ldr r1, =0x00000300 + str r1, [r0, #CLKCTL_CCGR6] + + /* Disable IPU and HSC dividers */ + mov r1, #0x60000 + str r1, [r0, #CLKCTL_CCDR] + + /* Make sure to switch the DDR away from PLL 1 */ + ldr r1, =0x19239145 + str r1, [r0, #CLKCTL_CBCDR] + /* make sure divider effective */ +1: ldr r1, [r0, #CLKCTL_CDHIPR] + cmp r1, #0x0 + bne 1b + + /* Switch ARM to step clock */ + mov r1, #0x4 + str r1, [r0, #CLKCTL_CCSR] + + mov r3, #DP_OP_800 + mov r4, #DP_MFD_800 + mov r5, #DP_MFN_800 + setup_pll PLL1_BASE_ADDR + mov r3, #DP_OP_665 + mov r4, #DP_MFD_665 + mov r5, #DP_MFN_665 + setup_pll PLL3_BASE_ADDR + + /* Switch peripheral to PLL 3 */ + ldr r0, =CCM_BASE_ADDR + ldr r1, =0x000010C0 + str r1, [r0, #CLKCTL_CBCMR] + ldr r1, =0x13239145 + str r1, [r0, #CLKCTL_CBCDR] + + mov r3, #DP_OP_665 + mov r4, #DP_MFD_665 + mov r5, #DP_MFN_665 + setup_pll PLL2_BASE_ADDR + + /* Switch peripheral to PLL2 */ + ldr r0, =CCM_BASE_ADDR + ldr r1, =0x19239145 + str r1, [r0, #CLKCTL_CBCDR] + ldr r1, =0x000020C0 + str r1, [r0, #CLKCTL_CBCMR] + + mov r3, #DP_OP_216 + mov r4, #DP_MFD_216 + mov r5, #DP_MFN_216 + setup_pll PLL3_BASE_ADDR + + /* Set the platform clock dividers */ + ldr r0, =ARM_BASE_ADDR + ldr r1, =0x00000725 + str r1, [r0, #0x14] + + ldr r0, =CCM_BASE_ADDR + /* Run TO 3.0 at Full speed, for other TO's wait + till we increase VDDGP */ + ldr r1, =0x0 + ldr r3, [r1, #ROM_SI_REV] + cmp r3, #0x10 + movls r1, #0x1 + movhi r1, #0 + str r1, [r0, #CLKCTL_CACRR] + + /* Switch ARM back to PLL 1 */ + mov r1, #0 + str r1, [r0, #CLKCTL_CCSR] + + /* setup the rest */ + /* Use lp_apm (24MHz) source for perclk */ + ldr r1, =0x000020C2 + str r1, [r0, #CLKCTL_CBCMR] + /* ddr clock from PLL 1, all perclk dividers are 1 since using 24MHz */ +#ifdef CONFIG_IMX51_MDDR + ldr r1, =0x61E35100 +#else + ldr r1, =0x59E35100 +#endif + str r1, [r0, #CLKCTL_CBCDR] + + /* Restore the default values in the Gate registers */ + ldr r1, =0xFFFFFFFF + str r1, [r0, #CLKCTL_CCGR0] + str r1, [r0, #CLKCTL_CCGR1] + str r1, [r0, #CLKCTL_CCGR2] + str r1, [r0, #CLKCTL_CCGR3] + str r1, [r0, #CLKCTL_CCGR4] + str r1, [r0, #CLKCTL_CCGR5] + str r1, [r0, #CLKCTL_CCGR6] + + /* Use PLL 2 for UART's, get 66.5MHz from it */ + ldr r1, =0xA5A2A020 + str r1, [r0, #CLKCTL_CSCMR1] + ldr r1, =0x00C30321 + str r1, [r0, #CLKCTL_CSCDR1] + + /* make sure divider effective */ +1: ldr r1, [r0, #CLKCTL_CDHIPR] + cmp r1, #0x0 + bne 1b + + mov r1, #0x0 + str r1, [r0, #CLKCTL_CCDR] + + /* for cko - for ARM div by 8 */ + mov r1, #0x000A0000 + add r1, r1, #0x00000F0 + str r1, [r0, #CLKCTL_CCOSR] +.endm + +.macro setup_wdog + ldr r0, =WDOG1_BASE_ADDR + mov r1, #0x30 + strh r1, [r0] +.endm + +.macro setup_sdram + ldr r0, =ESDCTL_BASE_ADDR + /* Set CSD0 */ + mov r1, #0x80000000 + str r1, [r0, #ESDCTL_ESDCTL0] + /* Precharge command */ + ldr r1, DDR_PERCHARGE_CMD + str r1, [r0, #ESDCTL_ESDSCR] + /* 2 refresh commands */ + ldr r1, DDR_REFRESH_CMD + str r1, [r0, #ESDCTL_ESDSCR] + str r1, [r0, #ESDCTL_ESDSCR] + /* LMR with CAS=3 and BL=3 */ + ldr r1, DDR_LMR1_W + str r1, [r0, #ESDCTL_ESDSCR] + /* 13 ROW, 10 COL, 32Bit, SREF=4 Micron Model */ + ldr r1, DDR_LMR_CMD + str r1, [r0, #ESDCTL_ESDCTL0] + /* Timing parameters */ + ldr r1, DDR_TIMING_W + str r1, [r0, #ESDCTL_ESDCFG0] + /* MDDR enable, RLAT=2 */ + ldr r1, DDR_MISC_W + str r1, [r0, #ESDCTL_ESDMISC] + /* Normal mode */ + mov r1, #0x00000000 + str r1, [r0, #ESDCTL_ESDSCR] +1: +.endm /* setup_sdram */ + +.section ".text.init", "x" + +.globl lowlevel_init +lowlevel_init: + ldr r1, =0x00000000 + ldr r3, [r1, #ROM_SI_REV] + ldr r0, =GPC_BASE_ADDR + cmp r3, #0x10 // r3 contains the silicon rev + ldrls r1, =0x1FC00000 + ldrhi r1, =0x1A800000 + str r1, [r0, #4] + +#ifdef ENABLE_IMPRECISE_ABORT + mrs r1, spsr /* save old spsr */ + mrs r0, cpsr /* read out the cpsr */ + bic r0, r0, #0x100 /* clear the A bit */ + msr spsr, r0 /* update spsr */ + add lr, pc, #0x8 /* update lr */ + movs pc, lr /* update cpsr */ + nop + nop + nop + nop + msr spsr, r1 /* restore old spsr */ +#endif + + /* ARM errata ID #468414 */ + mrc 15, 0, r1, c1, c0, 1 + orr r1, r1, #(1 << 5) /* enable L1NEON bit */ + mcr 15, 0, r1, c1, c0, 1 + + init_l2cc + + init_aips + + + init_max + + init_m4if + + init_drive_strength + + cmp pc, #PHYS_SDRAM_1 + blo do_sdram_setup + cmp pc, #(PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE) + blo init_clock_start + +do_sdram_setup: + setup_sdram + +init_clock_start: + init_clock + init_debug_board + /*init_sdram*/ + + /* return from mxc_nand_load */ + /* r12 saved upper lr*/ + b mxc_nand_load + +/* Board level setting value */ +DDR_PERCHARGE_CMD: .word 0x04008008 +DDR_REFRESH_CMD: .word 0x00008010 +DDR_LMR1_W: .word 0x00338018 +DDR_LMR_CMD: .word 0xB2220000 +DDR_TIMING_W: .word 0xB02567A9 +DDR_MISC_W: .word 0x000A0104 diff --git a/board/freescale/mx51_3stack/mx51_3stack.c b/board/freescale/mx51_3stack/mx51_3stack.c new file mode 100644 index 0000000000..1289118213 --- /dev/null +++ b/board/freescale/mx51_3stack/mx51_3stack.c @@ -0,0 +1,1102 @@ +/* + * Copyright (C) 2007, Guennadi Liakhovetski + * + * (C) Copyright 2009-2010 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include "board-mx51_3stack.h" +#include + +#ifdef CONFIG_CMD_MMC +#include +#include +#endif + +#ifdef CONFIG_ARCH_MMU +#include +#include +#endif + +#ifdef CONFIG_FSL_ANDROID +#include +#include +#include +#include +#include +#include +#include +#endif + +DECLARE_GLOBAL_DATA_PTR; + +static u32 system_rev; +static enum boot_device boot_dev; +u32 mx51_io_base_addr; + +static inline void setup_boot_device(void) +{ + uint *fis_addr = (uint *)IRAM_BASE_ADDR; + + switch (*fis_addr) { + case NAND_FLASH_BOOT: + boot_dev = NAND_BOOT; + break; + case SPI_NOR_FLASH_BOOT: + boot_dev = SPI_NOR_BOOT; + break; + case MMC_FLASH_BOOT: + boot_dev = MMC_BOOT; + break; + default: + { + uint soc_sbmr = readl(SRC_BASE_ADDR + 0x4); + uint bt_mem_ctl = soc_sbmr & 0x00000003; + uint bt_mem_type = (soc_sbmr & 0x00000180) >> 7; + + switch (bt_mem_ctl) { + case 0x3: + if (bt_mem_type == 0) + boot_dev = MMC_BOOT; + else if (bt_mem_type == 3) + boot_dev = SPI_NOR_BOOT; + else + boot_dev = UNKNOWN_BOOT; + break; + case 0x1: + boot_dev = NAND_BOOT; + break; + default: + boot_dev = UNKNOWN_BOOT; + } + } + break; + } +} + +enum boot_device get_boot_device(void) +{ + return boot_dev; +} + +u32 get_board_rev(void) +{ + return system_rev; +} + +static inline void setup_soc_rev(void) +{ + int reg; +#ifdef CONFIG_ARCH_MMU + reg = __REG(0x20000000 + ROM_SI_REV); /* Virtual address */ +#else + reg = __REG(ROM_SI_REV); /* Virtual address */ +#endif + + switch (reg) { + case 0x02: + system_rev = 0x51000 | CHIP_REV_1_1; + break; + case 0x10: + system_rev = 0x51000 | CHIP_REV_2_0; + break; + default: + system_rev = 0x51000 | CHIP_REV_1_0; + } +} + +static inline void set_board_rev(int rev) +{ + system_rev |= (rev & 0xF) << 8; +} + +inline int is_soc_rev(int rev) +{ + return (system_rev & 0xFF) - rev; +} + +#ifdef CONFIG_ARCH_MMU +void board_mmu_init(void) +{ + unsigned long ttb_base = PHYS_SDRAM_1 + 0x4000; + unsigned long i; + + /* + * Set the TTB register + */ + asm volatile ("mcr p15, 0, %0, c2, c0, 0" : : "r"(ttb_base) /*:*/); + + /* + * Set the Domain Access Control Register + */ + i = ARM_ACCESS_DACR_DEFAULT; + asm volatile ("mcr p15, 0, %0, c3, c0, 0" : : "r"(i) /*:*/); + + /* + * First clear all TT entries - ie Set them to Faulting + */ + memset((void *)ttb_base, 0, ARM_FIRST_LEVEL_PAGE_TABLE_SIZE); + /* Actual Virtual Size Attributes Function */ + /* Base Base MB cached? buffered? access permissions */ + /* xxx00000 xxx00000 */ + X_ARM_MMU_SECTION(0x000, 0x200, 0x1, + ARM_UNCACHEABLE, ARM_UNBUFFERABLE, + ARM_ACCESS_PERM_RW_RW); /* ROM */ + X_ARM_MMU_SECTION(0x1FF, 0x1FF, 0x001, + ARM_UNCACHEABLE, ARM_UNBUFFERABLE, + ARM_ACCESS_PERM_RW_RW); /* IRAM */ + X_ARM_MMU_SECTION(0x300, 0x300, 0x100, + ARM_UNCACHEABLE, ARM_UNBUFFERABLE, + ARM_ACCESS_PERM_RW_RW); /* GPU */ + X_ARM_MMU_SECTION(0x400, 0x400, 0x200, + ARM_UNCACHEABLE, ARM_UNBUFFERABLE, + ARM_ACCESS_PERM_RW_RW); /* IPUv3D */ + X_ARM_MMU_SECTION(0x600, 0x600, 0x300, + ARM_UNCACHEABLE, ARM_UNBUFFERABLE, + ARM_ACCESS_PERM_RW_RW); /* periperals */ + X_ARM_MMU_SECTION(0x900, 0x000, 0x080, + ARM_CACHEABLE, ARM_BUFFERABLE, + ARM_ACCESS_PERM_RW_RW); /* SDRAM */ + X_ARM_MMU_SECTION(0x900, 0x900, 0x080, + ARM_CACHEABLE, ARM_BUFFERABLE, + ARM_ACCESS_PERM_RW_RW); /* SDRAM */ + X_ARM_MMU_SECTION(0x900, 0x980, 0x080, + ARM_UNCACHEABLE, ARM_UNBUFFERABLE, + ARM_ACCESS_PERM_RW_RW); /* SDRAM 0:128M*/ + X_ARM_MMU_SECTION(0xA00, 0xA00, 0x100, + ARM_CACHEABLE, ARM_BUFFERABLE, + ARM_ACCESS_PERM_RW_RW); /* SDRAM */ + X_ARM_MMU_SECTION(0xB80, 0xB80, 0x10, + ARM_UNCACHEABLE, ARM_UNBUFFERABLE, + ARM_ACCESS_PERM_RW_RW); /* CS1 EIM control*/ + X_ARM_MMU_SECTION(0xCC0, 0xCC0, 0x040, + ARM_UNCACHEABLE, ARM_UNBUFFERABLE, + ARM_ACCESS_PERM_RW_RW); /* CS4/5/NAND Flash buffer */ + + /* Workaround for arm errata #709718 */ + /* Setup PRRR so device is always mapped to non-shared */ + asm volatile ("mrc p15, 0, %0, c10, c2, 0" : "=r"(i) : /*:*/); + i &= (~(3 << 0x10)); + asm volatile ("mcr p15, 0, %0, c10, c2, 0" : : "r"(i) /*:*/); + + /* Enable MMU */ + MMU_ON(); +} +#endif + +int dram_init(void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + return 0; +} + +static void setup_uart(void) +{ + unsigned int pad = PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE | + PAD_CTL_PUE_PULL | PAD_CTL_DRV_HIGH; + mxc_request_iomux(MX51_PIN_UART1_RXD, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX51_PIN_UART1_RXD, pad | PAD_CTL_SRE_FAST); + mxc_request_iomux(MX51_PIN_UART1_TXD, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX51_PIN_UART1_TXD, pad | PAD_CTL_SRE_FAST); + mxc_request_iomux(MX51_PIN_UART1_RTS, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX51_PIN_UART1_RTS, pad); + mxc_request_iomux(MX51_PIN_UART1_CTS, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX51_PIN_UART1_CTS, pad); +} + +void setup_nfc(void) +{ + /* Enable NFC IOMUX */ + mxc_request_iomux(MX51_PIN_NANDF_CS0, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX51_PIN_NANDF_CS1, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX51_PIN_NANDF_CS2, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX51_PIN_NANDF_CS3, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX51_PIN_NANDF_CS4, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX51_PIN_NANDF_CS5, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX51_PIN_NANDF_CS6, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX51_PIN_NANDF_CS7, IOMUX_CONFIG_ALT0); +} + +static void setup_expio(void) +{ + u32 reg; + /* CS5 setup */ + mxc_request_iomux(MX51_PIN_EIM_CS5, IOMUX_CONFIG_ALT0); + writel(0x00410089, WEIM_BASE_ADDR + 0x78 + CSGCR1); + writel(0x00000002, WEIM_BASE_ADDR + 0x78 + CSGCR2); + /* RWSC=50, RADVA=2, RADVN=6, OEA=0, OEN=0, RCSA=0, RCSN=0 */ + writel(0x32260000, WEIM_BASE_ADDR + 0x78 + CSRCR1); + /* APR = 0 */ + writel(0x00000000, WEIM_BASE_ADDR + 0x78 + CSRCR2); + /* WAL=0, WBED=1, WWSC=50, WADVA=2, WADVN=6, WEA=0, WEN=0, + * WCSA=0, WCSN=0 + */ + writel(0x72080F00, WEIM_BASE_ADDR + 0x78 + CSWCR1); + if ((readw(CS5_BASE_ADDR + PBC_ID_AAAA) == 0xAAAA) && + (readw(CS5_BASE_ADDR + PBC_ID_5555) == 0x5555)) { + if (is_soc_rev(CHIP_REV_2_0) < 0) { + reg = readl(CCM_BASE_ADDR + CLKCTL_CBCDR); + reg = (reg & (~0x70000)) | 0x30000; + writel(reg, CCM_BASE_ADDR + CLKCTL_CBCDR); + /* make sure divider effective */ + while (readl(CCM_BASE_ADDR + CLKCTL_CDHIPR) != 0) + ; + writel(0x0, CCM_BASE_ADDR + CLKCTL_CCDR); + } + mx51_io_base_addr = CS5_BASE_ADDR; + } else { + /* CS1 */ + writel(0x00410089, WEIM_BASE_ADDR + 0x18 + CSGCR1); + writel(0x00000002, WEIM_BASE_ADDR + 0x18 + CSGCR2); + /* RWSC=50, RADVA=2, RADVN=6, OEA=0, OEN=0, RCSA=0, RCSN=0 */ + writel(0x32260000, WEIM_BASE_ADDR + 0x18 + CSRCR1); + /* APR=0 */ + writel(0x00000000, WEIM_BASE_ADDR + 0x18 + CSRCR2); + /* WAL=0, WBED=1, WWSC=50, WADVA=2, WADVN=6, WEA=0, + * WEN=0, WCSA=0, WCSN=0 + */ + writel(0x72080F00, WEIM_BASE_ADDR + 0x18 + CSWCR1); + mx51_io_base_addr = CS1_BASE_ADDR; + } + + /* Reset interrupt status reg */ + writew(0x1F, mx51_io_base_addr + PBC_INT_REST); + writew(0x00, mx51_io_base_addr + PBC_INT_REST); + writew(0xFFFF, mx51_io_base_addr + PBC_INT_MASK); + + /* Reset the XUART and Ethernet controllers */ + reg = readw(mx51_io_base_addr + PBC_SW_RESET); + reg |= 0x9; + writew(reg, mx51_io_base_addr + PBC_SW_RESET); + reg &= ~0x9; + writew(reg, mx51_io_base_addr + PBC_SW_RESET); +} + +#if defined(CONFIG_MXC_ATA) +int setup_ata(void) +{ + u32 pad; + + pad = (PAD_CTL_DRV_HIGH | PAD_CTL_DRV_VOT_HIGH); + + /* Need to disable nand iomux first */ + mxc_request_iomux(MX51_PIN_NANDF_ALE, IOMUX_CONFIG_ALT1); + mxc_iomux_set_pad(MX51_PIN_NANDF_ALE, pad); + + mxc_request_iomux(MX51_PIN_NANDF_CS2, IOMUX_CONFIG_ALT1); + mxc_iomux_set_pad(MX51_PIN_NANDF_CS2, pad); + + mxc_request_iomux(MX51_PIN_NANDF_CS3, IOMUX_CONFIG_ALT1); + mxc_iomux_set_pad(MX51_PIN_NANDF_CS3, pad); + + mxc_request_iomux(MX51_PIN_NANDF_CS4, IOMUX_CONFIG_ALT1); + mxc_iomux_set_pad(MX51_PIN_NANDF_CS4, pad); + + mxc_request_iomux(MX51_PIN_NANDF_CS5, IOMUX_CONFIG_ALT1); + mxc_iomux_set_pad(MX51_PIN_NANDF_CS5, pad); + + mxc_request_iomux(MX51_PIN_NANDF_CS6, IOMUX_CONFIG_ALT1); + mxc_iomux_set_pad(MX51_PIN_NANDF_CS6, pad); + + mxc_request_iomux(MX51_PIN_NANDF_RE_B, IOMUX_CONFIG_ALT1); + mxc_iomux_set_pad(MX51_PIN_NANDF_RE_B, pad); + + mxc_request_iomux(MX51_PIN_NANDF_WE_B, IOMUX_CONFIG_ALT1); + mxc_iomux_set_pad(MX51_PIN_NANDF_WE_B, pad); + + mxc_request_iomux(MX51_PIN_NANDF_CLE, IOMUX_CONFIG_ALT1); + mxc_iomux_set_pad(MX51_PIN_NANDF_CLE, pad); + + mxc_request_iomux(MX51_PIN_NANDF_RB0, IOMUX_CONFIG_ALT1); + mxc_iomux_set_pad(MX51_PIN_NANDF_RB0, pad); + + mxc_request_iomux(MX51_PIN_NANDF_WP_B, IOMUX_CONFIG_ALT1); + mxc_iomux_set_pad(MX51_PIN_NANDF_WP_B, pad); + + /* TO 2.0 */ + mxc_request_iomux(MX51_PIN_GPIO_NAND, IOMUX_CONFIG_ALT1); + mxc_iomux_set_pad(MX51_PIN_GPIO_NAND, pad); + + /* TO 1.0 */ + mxc_request_iomux(MX51_PIN_NANDF_RB5, IOMUX_CONFIG_ALT1); + mxc_iomux_set_pad(MX51_PIN_NANDF_RB5, pad); + + mxc_request_iomux(MX51_PIN_NANDF_RB1, IOMUX_CONFIG_ALT1); + mxc_iomux_set_pad(MX51_PIN_NANDF_RB1, pad); + + mxc_request_iomux(MX51_PIN_NANDF_D0, IOMUX_CONFIG_ALT1); + mxc_iomux_set_pad(MX51_PIN_NANDF_D0, pad); + + mxc_request_iomux(MX51_PIN_NANDF_D1, IOMUX_CONFIG_ALT1); + mxc_iomux_set_pad(MX51_PIN_NANDF_D1, pad); + + mxc_request_iomux(MX51_PIN_NANDF_D2, IOMUX_CONFIG_ALT1); + mxc_iomux_set_pad(MX51_PIN_NANDF_D2, pad); + + mxc_request_iomux(MX51_PIN_NANDF_D3, IOMUX_CONFIG_ALT1); + mxc_iomux_set_pad(MX51_PIN_NANDF_D3, pad); + + mxc_request_iomux(MX51_PIN_NANDF_D4, IOMUX_CONFIG_ALT1); + mxc_iomux_set_pad(MX51_PIN_NANDF_D4, pad); + + mxc_request_iomux(MX51_PIN_NANDF_D5, IOMUX_CONFIG_ALT1); + mxc_iomux_set_pad(MX51_PIN_NANDF_D5, pad); + + mxc_request_iomux(MX51_PIN_NANDF_D6, IOMUX_CONFIG_ALT1); + mxc_iomux_set_pad(MX51_PIN_NANDF_D6, pad); + + mxc_request_iomux(MX51_PIN_NANDF_D7, IOMUX_CONFIG_ALT1); + mxc_iomux_set_pad(MX51_PIN_NANDF_D7, pad); + + mxc_request_iomux(MX51_PIN_NANDF_D8, IOMUX_CONFIG_ALT1); + mxc_iomux_set_pad(MX51_PIN_NANDF_D8, pad); + + mxc_request_iomux(MX51_PIN_NANDF_D9, IOMUX_CONFIG_ALT1); + mxc_iomux_set_pad(MX51_PIN_NANDF_D9, pad); + + mxc_request_iomux(MX51_PIN_NANDF_D10, IOMUX_CONFIG_ALT1); + mxc_iomux_set_pad(MX51_PIN_NANDF_D10, pad); + + mxc_request_iomux(MX51_PIN_NANDF_D11, IOMUX_CONFIG_ALT1); + mxc_iomux_set_pad(MX51_PIN_NANDF_D11, pad); + + mxc_request_iomux(MX51_PIN_NANDF_D12, IOMUX_CONFIG_ALT1); + mxc_iomux_set_pad(MX51_PIN_NANDF_D12, pad); + + mxc_request_iomux(MX51_PIN_NANDF_D13, IOMUX_CONFIG_ALT1); + mxc_iomux_set_pad(MX51_PIN_NANDF_D13, pad); + + mxc_request_iomux(MX51_PIN_NANDF_D14, IOMUX_CONFIG_ALT1); + mxc_iomux_set_pad(MX51_PIN_NANDF_D14, pad); + + mxc_request_iomux(MX51_PIN_NANDF_D15, IOMUX_CONFIG_ALT1); + mxc_iomux_set_pad(MX51_PIN_NANDF_D15, pad); + + return 0; +} +#endif + +#ifdef CONFIG_I2C_MXC +static setup_i2c(unsigned int module_base) +{ + unsigned int reg; + + switch (module_base) { + case I2C1_BASE_ADDR: + reg = IOMUXC_BASE_ADDR + 0x210; /* i2c SDA */ + writel(0x11, reg); + reg = IOMUXC_BASE_ADDR + 0x600; + writel(0x1ad, reg); + reg = IOMUXC_BASE_ADDR + 0x9B4; + writel(0x1, reg); + + reg = IOMUXC_BASE_ADDR + 0x224; /* i2c SCL */ + writel(0x11, reg); + reg = IOMUXC_BASE_ADDR + 0x614; + writel(0x1ad, reg); + reg = IOMUXC_BASE_ADDR + 0x9B0; + writel(0x1, reg); + break; + case I2C2_BASE_ADDR: + /* Workaround for Atlas Lite */ + writel(0x0, IOMUXC_BASE_ADDR + 0x3CC); /* i2c SCL */ + writel(0x0, IOMUXC_BASE_ADDR + 0x3D0); /* i2c SDA */ + reg = readl(GPIO1_BASE_ADDR + 0x0); + reg |= 0xC; /* write a 1 on the SCL and SDA lines */ + writel(reg, GPIO1_BASE_ADDR + 0x0); + reg = readl(GPIO1_BASE_ADDR + 0x4); + reg |= 0xC; /* configure GPIO lines as output */ + writel(reg, GPIO1_BASE_ADDR + 0x4); + reg = readl(GPIO1_BASE_ADDR + 0x0); + reg &= ~0x4 ; /* set SCL low for a few milliseconds */ + writel(reg, GPIO1_BASE_ADDR + 0x0); + udelay(20000); + reg |= 0x4; + writel(reg, GPIO1_BASE_ADDR + 0x0); + udelay(10); + reg = readl(GPIO1_BASE_ADDR + 0x4); + reg &= ~0xC; /* configure GPIO lines back as input */ + writel(reg, GPIO1_BASE_ADDR + 0x4); + + writel(0x12, IOMUXC_BASE_ADDR + 0x3CC); /* i2c SCL */ + writel(0x3, IOMUXC_BASE_ADDR + 0x9B8); + writel(0x1ed, IOMUXC_BASE_ADDR + 0x7D4); + + writel(0x12, IOMUXC_BASE_ADDR + 0x3D0); /* i2c SDA */ + writel(0x3, IOMUXC_BASE_ADDR + 0x9BC); + writel(0x1ed, IOMUXC_BASE_ADDR + 0x7D8); + break; + default: + printf("Invalid I2C base: 0x%x\n", module_base); + break; + } +} + +#define REV_ATLAS_LITE_1_0 0x8 +#define REV_ATLAS_LITE_1_1 0x9 +#define REV_ATLAS_LITE_2_0 0x10 +#define REV_ATLAS_LITE_2_1 0x11 + +void setup_core_voltages(void) +{ + unsigned char buf[4] = { 0 }; + + i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); + + if (is_soc_rev(CHIP_REV_2_0) <= 0) { + /* Set core voltage to 1.1V */ + if (i2c_read(0x8, 24, 1, buf, 3)) { + puts("setup_core_voltages: read PMIC@0x08:0x18 fail\n"); + return; + } + buf[2] = (buf[2] & (~0x1F)) | 0x14; + if (i2c_write(0x8, 24, 1, buf, 3)) { + puts("setup_core_voltages: write PMIC@0x08:0x18 fail\n"); + return; + } + + /* Setup VCC (SW2) to 1.25 */ + if (i2c_read(0x8, 25, 1, buf, 3)) { + puts("setup_core_voltages: read PMIC@0x08:0x19 fail\n"); + return; + } + buf[2] = (buf[2] & (~0x1F)) | 0x1A; + if (i2c_write(0x8, 25, 1, buf, 3)) { + puts("setup_core_voltages: write PMIC@0x08:0x19 fail\n"); + return; + } + + /* Setup 1V2_DIG1 (SW3) to 1.25 */ + if (i2c_read(0x8, 26, 1, buf, 3)) { + puts("setup_core_voltages: read PMIC@0x08:0x1A fail\n"); + return; + } + buf[2] = (buf[2] & (~0x1F)) | 0x1A; + if (i2c_write(0x8, 26, 1, buf, 3)) { + puts("setup_core_voltages: write PMIC@0x08:0x1A fail\n"); + return; + } + + udelay(50); + + /* Raise the core frequency to 800MHz */ + writel(0x0, CCM_BASE_ADDR + CLKCTL_CACRR); + } else { + /* TO 3.0 */ + /* Setup VCC (SW2) to 1.225 */ + if (i2c_read(0x8, 25, 1, buf, 3)) { + puts("setup_core_voltages: read PMIC@0x08:0x19 fail\n"); + return; + } + buf[2] = (buf[2] & (~0x1F)) | 0x19; + if (i2c_write(0x8, 25, 1, buf, 3)) { + puts("setup_core_voltages: write PMIC@0x08:0x19 fail\n"); + return; + } + + /* Setup 1V2_DIG1 (SW3) to 1.2 */ + if (i2c_read(0x8, 26, 1, buf, 3)) { + puts("setup_core_voltages: read PMIC@0x08:0x1A fail\n"); + return; + } + buf[2] = (buf[2] & (~0x1F)) | 0x18; + if (i2c_write(0x8, 26, 1, buf, 3)) { + puts("setup_core_voltages: write PMIC@0x08:0x1A fail\n"); + return; + } + } + + if (i2c_read(0x8, 7, 1, buf, 3)) { + puts("setup_core_voltages: read PMIC@0x08:0x07 fail\n"); + return; + } + + if (((buf[2] & 0x1F) < REV_ATLAS_LITE_2_0) || (((buf[1] >> 1) & 0x3) == 0)) { + /* Set switchers in PWM mode for Atlas 2.0 and lower */ + /* Setup the switcher mode for SW1 & SW2*/ + if (i2c_read(0x8, 28, 1, buf, 3)) { + puts("setup_core_voltages: read PMIC@0x08:0x1C fail\n"); + return; + } + buf[2] = (buf[2] & (~0xF)) | 0x5; + buf[1] = (buf[1] & (~0x3C)) | 0x14; + if (i2c_write(0x8, 28, 1, buf, 3)) { + puts("setup_core_voltages: write PMIC@0x08:0x1C fail\n"); + return; + } + + /* Setup the switcher mode for SW3 & SW4*/ + if (i2c_read(0x8, 29, 1, buf, 3)) { + puts("setup_core_voltages: read PMIC@0x08:0x1D fail\n"); + return; + } + buf[2] = (buf[2] & (~0xF)) | 0x5; + buf[1] = (buf[1] & (~0xF)) | 0x5; + if (i2c_write(0x8, 29, 1, buf, 3)) { + puts("setup_core_voltages: write PMIC@0x08:0x1D fail\n"); + return; + } + } else { + /* Set switchers in Auto in NORMAL mode & STANDBY mode for Atlas 2.0a */ + /* Setup the switcher mode for SW1 & SW2*/ + if (i2c_read(0x8, 28, 1, buf, 3)) { + puts("setup_core_voltages: read PMIC@0x08:0x1C fail\n"); + return; + } + buf[2] = (buf[2] & (~0xF)) | 0x8; + buf[1] = (buf[1] & (~0x3C)) | 0x20; + if (i2c_write(0x8, 28, 1, buf, 3)) { + puts("setup_core_voltages: write PMIC@0x08:0x1C fail\n"); + return; + } + + /* Setup the switcher mode for SW3 & SW4*/ + if (i2c_read(0x8, 29, 1, buf, 3)) { + puts("setup_core_voltages: read PMIC@0x08:0x1D fail\n"); + return; + } + buf[2] = (buf[2] & (~0xF)) | 0x8; + buf[1] = (buf[1] & (~0xF)) | 0x8; + if (i2c_write(0x8, 29, 1, buf, 3)) { + puts("setup_core_voltages: write PMIC@0x08:0x1D fail\n"); + return; + } + } +} + +#endif + +int board_init(void) +{ + setup_boot_device(); + setup_soc_rev(); + + gd->bd->bi_arch_number = MACH_TYPE_MX51_3DS; /* board id for linux */ + /* address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; + + setup_uart(); + setup_nfc(); + setup_expio(); +#ifdef CONFIG_I2C_MXC + setup_i2c(I2C2_BASE_ADDR); + setup_core_voltages(); +#endif + return 0; +} + +#ifdef BOARD_LATE_INIT + +#if defined(CONFIG_FSL_ANDROID) && defined(CONFIG_MXC_KPD) +static int waiting_for_func_key_pressing(void) +{ + struct kpp_key_info key_info = {0, 0}; + int switch_delay = CONFIG_ANDROID_BOOTMOD_DELAY; + int state = 0, boot_mode_switch = 0; + + mxc_kpp_init(); + + puts("Press home + power to enter recovery mode ...\n"); + + while ((switch_delay > 0) && (!boot_mode_switch)) { + int i; + + --switch_delay; + /* delay 100 * 10ms */ + for (i = 0; !boot_mode_switch && i < 100; ++i) { + /* A state machine to scan home + power key */ + /* Check for home + power */ + if (mxc_kpp_getc(&key_info)) { + switch (state) { + case 0: + /* First press */ + if (TEST_HOME_KEY_DEPRESS(key_info.val, key_info.evt)) { + /* Press Home */ + state = 1; + } else if (TEST_POWER_KEY_DEPRESS(key_info.val, key_info.evt)) { + state = 2; + } else { + state = 0; + } + break; + case 1: + /* Home is already pressed, try to detect Power */ + if (TEST_POWER_KEY_DEPRESS(key_info.val, + key_info.evt)) { + boot_mode_switch = 1; + } else { + if (TEST_HOME_KEY_DEPRESS(key_info.val, + key_info.evt)) + state = 2; + else + state = 0; + } + break; + case 2: + /* Power is already pressed, try to detect Home */ + if (TEST_HOME_KEY_DEPRESS(key_info.val, + key_info.evt)) { + boot_mode_switch = 1; + } else { + if (TEST_POWER_KEY_DEPRESS(key_info.val, + key_info.evt)) + state = 1; + else + state = 0; + } + break; + default: + break; + } + + if (1 == boot_mode_switch) + return 1; + } + } + for (i = 0; i < 100; ++i) + udelay(10000); + } + + return 0; +} + +static int switch_to_recovery_mode(void) +{ + char *env = NULL; + char *boot_args = NULL; + char *boot_cmd = NULL; + + printf("Boot mode switched to recovery mode!\n"); + + switch (get_boot_device()) { + case MMC_BOOT: + boot_args = CONFIG_ANDROID_RECOVERY_BOOTARGS_MMC; + boot_cmd = CONFIG_ANDROID_RECOVERY_BOOTCMD_MMC; + break; + case NAND_BOOT: + boot_args = CONFIG_ANDROID_RECOVERY_BOOTARGS_NAND; + boot_cmd = CONFIG_ANDROID_RECOVERY_BOOTCMD_NAND; + break; + case SPI_NOR_BOOT: + printf("Recovery mode not supported in SPI NOR boot\n"); + return -1; + break; + case UNKNOWN_BOOT: + default: + printf("Unknown boot device!\n"); + return -1; + break; + } + + env = getenv("bootargs_android_recovery"); + /* Set env to recovery mode */ + if (!env) + setenv("bootargs_android", boot_args); + else + setenv("bootargs_android", env); + + env = getenv("bootcmd_android_recovery"); + if (!env) + setenv("bootcmd_android", boot_cmd); + else + setenv("bootcmd_android", env); + setenv("bootcmd", "run bootcmd_android"); + + return 0; +} + +static int check_mmc_recovery_cmd_file(int dev_num, int part_num, char *path) +{ + block_dev_desc_t *dev_desc = NULL; + struct mmc *mmc = find_mmc_device(dev_num); + disk_partition_t info; + ulong part_length = 0; + int filelen = 0; + + memset(&info, 0, sizeof(disk_partition_t)); + + dev_desc = get_dev("mmc", dev_num); + + if (NULL == dev_desc) { + printf("** Block device MMC %d not supported\n", + dev_num); + return 0; + } + + mmc_init(mmc); + + if (get_partition_info(dev_desc, + part_num, + &info)) { + printf("** Bad partition %d **\n", + part_num); + return 0; + } + + part_length = ext2fs_set_blk_dev(dev_desc, + part_num); + if (part_length == 0) { + printf("** Bad partition - mmc 0:%d **\n", + part_num); + ext2fs_close(); + return 0; + } + + if (!ext2fs_mount(part_length)) { + printf("** Bad ext2 partition or disk - mmc 0:%d **\n", + part_num); + ext2fs_close(); + return 0; + } + + filelen = ext2fs_open(path); + + ext2fs_close(); + + return (filelen > 0) ? 1 : 0; +} + +extern int ubifs_init(void); +extern int ubifs_mount(char *vol_name); +extern int ubifs_load(char *filename, u32 addr, u32 size); + +static int check_nand_recovery_cmd_file(char *mtd_part_name, + char *ubi_part_name, + char *path) +{ + struct mtd_device *dev_desc = NULL; + struct part_info *part = NULL; + struct mtd_partition mtd_part; + struct mtd_info *mtd_info = NULL; + char mtd_dev[16] = { 0 }; + char mtd_buffer[80] = { 0 }; + u8 pnum = 0, + read_test = 0; + int err = 0, + filelen = 0; + + memset(&mtd_part, 0, sizeof(struct mtd_partition)); + + /* ========== ubi and mtd operations ========== */ + if (mtdparts_init() != 0) { + printf("Error initializing mtdparts!\n"); + return 0; + } + + if (find_dev_and_part(mtd_part_name, &dev_desc, &pnum, &part)) { + printf("Partition %s not found!\n", mtd_part_name); + return 0; + } + sprintf(mtd_dev, "%s%d", + MTD_DEV_TYPE(dev_desc->id->type), + dev_desc->id->num); + mtd_info = get_mtd_device_nm(mtd_dev); + if (IS_ERR(mtd_info)) { + printf("Partition %s not found on device %s!\n", + "nand", mtd_dev); + return 0; + } + + sprintf(mtd_buffer, "mtd=%d", pnum); + memset(&mtd_part, 0, sizeof(mtd_part)); + mtd_part.name = mtd_buffer; + mtd_part.size = part->size; + mtd_part.offset = part->offset; + add_mtd_partitions(mtd_info, &mtd_part, 1); + + err = ubi_mtd_param_parse(mtd_buffer, NULL); + if (err) { + del_mtd_partitions(mtd_info); + return 0; + } + + err = ubi_init(); + if (err) { + del_mtd_partitions(mtd_info); + return 0; + } + + /* ========== ubifs operations ========== */ + /* Init ubifs */ + ubifs_init(); + + if (ubifs_mount(ubi_part_name)) { + printf("Mount ubifs volume %s fail!\n", + ubi_part_name); + return 0; + } + + /* Try to read one byte for a read test. */ + if (ubifs_load(path, (u32)&read_test, 1)) { + /* File not found */ + filelen = 0; + } else + filelen = 1; + + return filelen; +} + +static int check_recovery_cmd_file(void) +{ + int if_exist = 0; + char *env = NULL; + + switch (get_boot_device()) { + case MMC_BOOT: + if_exist = check_mmc_recovery_cmd_file(0, + CONFIG_ANDROID_CACHE_PARTITION_MMC, + CONFIG_ANDROID_RECOVERY_CMD_FILE); + break; + case NAND_BOOT: + env = getenv("mtdparts"); + if (!env) + setenv("mtdparts", MTDPARTS_DEFAULT); + + env = getenv("mtdids"); + if (!env) + setenv("mtdids", MTDIDS_DEFAULT); + + env = getenv("partition"); + if (!env) + setenv("partition", MTD_ACTIVE_PART); + + /* + if_exist = check_nand_recovery_cmd_file(CONFIG_ANDROID_UBIFS_PARTITION_NM, + CONFIG_ANDROID_CACHE_PARTITION_NAND, + CONFIG_ANDROID_RECOVERY_CMD_FILE); + */ + break; + case SPI_NOR_BOOT: + return 0; + break; + case UNKNOWN_BOOT: + default: + return 0; + break; + } + + return if_exist; +} +#endif + +int board_late_init(void) +{ +#if defined(CONFIG_FSL_ANDROID) && defined(CONFIG_MXC_KPD) + if (waiting_for_func_key_pressing()) + switch_to_recovery_mode(); + else { + if (check_recovery_cmd_file()) { + puts("Recovery command file detected!\n"); + switch_to_recovery_mode(); + } + } +#endif + + return 0; +} +#endif + +int checkboard(void) +{ + printf("Board: MX51 3STACK "); + + if (system_rev & CHIP_REV_2_0) { + printf("2.0 ["); + } else if (system_rev & CHIP_REV_1_1) { + printf("1.1 ["); + } else { + printf("1.0 ["); + } + + switch (__REG(SRC_BASE_ADDR + 0x8)) { + case 0x0001: + printf("POR"); + break; + case 0x0009: + printf("RST"); + break; + case 0x0010: + case 0x0011: + printf("WDOG"); + break; + default: + printf("unknown"); + } + printf("]\n"); + + printf("Boot Device: "); + switch (get_boot_device()) { + case NAND_BOOT: + printf("NAND\n"); + break; + case SPI_NOR_BOOT: + printf("SPI NOR\n"); + break; + case MMC_BOOT: + printf("MMC\n"); + break; + case UNKNOWN_BOOT: + default: + printf("UNKNOWN\n"); + break; + } + + return 0; +} + +#if defined(CONFIG_SMC911X) +extern int smc911x_initialize(u8 dev_num, int base_addr); +#endif + +#ifdef CONFIG_NET_MULTI +int board_eth_init(bd_t *bis) +{ + int rc = -ENODEV; +#if defined(CONFIG_SMC911X) + rc = smc911x_initialize(0, CONFIG_SMC911X_BASE); +#endif + + cpu_eth_init(bis); + + return rc; +} +#endif + +#ifdef CONFIG_CMD_MMC + +struct fsl_esdhc_cfg esdhc_cfg[2] = { + {MMC_SDHC1_BASE_ADDR, 1, 1}, +}; + +#ifdef CONFIG_DYNAMIC_MMC_DEVNO +int get_mmc_env_devno() +{ + uint soc_sbmr = readl(SRC_BASE_ADDR + 0x4); + return (soc_sbmr & 0x00180000) ? 1 : 0; +} +#endif + +int esdhc_gpio_init(bd_t *bis) +{ + u32 index = 0; + s32 status = 0; + + for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; + ++index) { + switch (index) { + case 0: + mxc_request_iomux(MX51_PIN_SD1_CMD, + IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); + mxc_request_iomux(MX51_PIN_SD1_CLK, + IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); + + mxc_request_iomux(MX51_PIN_SD1_DATA0, + IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); + mxc_request_iomux(MX51_PIN_SD1_DATA1, + IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); + mxc_request_iomux(MX51_PIN_SD1_DATA2, + IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); + mxc_request_iomux(MX51_PIN_SD1_DATA3, + IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); + mxc_iomux_set_pad(MX51_PIN_SD1_CMD, + PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH | + PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU | + PAD_CTL_PUE_PULL | + PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST); + mxc_iomux_set_pad(MX51_PIN_SD1_CLK, + PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH | + PAD_CTL_HYS_NONE | PAD_CTL_47K_PU | + PAD_CTL_PUE_PULL | + PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST); + mxc_iomux_set_pad(MX51_PIN_SD1_DATA0, + PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH | + PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU | + PAD_CTL_PUE_PULL | + PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST); + mxc_iomux_set_pad(MX51_PIN_SD1_DATA1, + PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH | + PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU | + PAD_CTL_PUE_PULL | + PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST); + mxc_iomux_set_pad(MX51_PIN_SD1_DATA2, + PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH | + PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU | + PAD_CTL_PUE_PULL | + PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST); + mxc_iomux_set_pad(MX51_PIN_SD1_DATA3, + PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH | + PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PD | + PAD_CTL_PUE_PULL | + PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST); + break; + case 1: + status = 1; + break; + case 2: + status = 1; + break; + case 3: + status = 1; + break; + default: + status = 1; + break; + } + status |= fsl_esdhc_initialize(bis, &esdhc_cfg[index]); + } + + return status; +} + +int board_mmc_init(bd_t *bis) +{ + if (!esdhc_gpio_init(bis)) + return fsl_esdhc_mmc_init(gd->bd); + else + return -1; +} +#endif + +#if defined(CONFIG_MXC_KPD) +int setup_mxc_kpd(void) +{ + mxc_request_iomux(MX51_PIN_KEY_COL0, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX51_PIN_KEY_COL1, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX51_PIN_KEY_COL2, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX51_PIN_KEY_COL3, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX51_PIN_KEY_COL4, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX51_PIN_KEY_COL5, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX51_PIN_KEY_ROW0, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX51_PIN_KEY_ROW1, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX51_PIN_KEY_ROW2, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX51_PIN_KEY_ROW3, IOMUX_CONFIG_ALT0); + + return 0; +} +#endif diff --git a/board/freescale/mx51_3stack/u-boot.lds b/board/freescale/mx51_3stack/u-boot.lds new file mode 100644 index 0000000000..8671fff3b2 --- /dev/null +++ b/board/freescale/mx51_3stack/u-boot.lds @@ -0,0 +1,73 @@ +/* + * January 2004 - Changed to support H4 device + * Copyright (c) 2004 Texas Instruments + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * (C) Copyright 2009 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + board/freescale/mx51_3stack/flash_header.o (.text.flasheader) + cpu/arm_cortexa8/start.o + board/freescale/mx51_3stack/libmx51_3stack.a (.text) + lib_arm/libarm.a (.text) + net/libnet.a (.text) + drivers/mtd/libmtd.a (.text) + drivers/mmc/libmmc.a (.text) + + . = DEFINED(env_offset) ? env_offset : .; + common/env_embedded.o(.text) + + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} diff --git a/board/freescale/mx51_bbg/Makefile b/board/freescale/mx51_bbg/Makefile new file mode 100644 index 0000000000..109ca7bd58 --- /dev/null +++ b/board/freescale/mx51_bbg/Makefile @@ -0,0 +1,49 @@ +# +# Copyright (C) 2007, Guennadi Liakhovetski +# +# (C) Copyright 2009 Freescale Semiconductor, Inc. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := mx51_bbg.o +SOBJS := lowlevel_init.o flash_header.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/freescale/mx51_bbg/board-imx51.h b/board/freescale/mx51_bbg/board-imx51.h new file mode 100644 index 0000000000..7a2cae0632 --- /dev/null +++ b/board/freescale/mx51_bbg/board-imx51.h @@ -0,0 +1,64 @@ +/* + * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#ifndef __BOARD_FREESCALE_BOARD_IMX51_H__ +#define __BOARD_FREESCALE_BOARD_IMX51_H__ + +/*! + * @defgroup BRDCFG_MX51 Board Configuration Options + * @ingroup MSL_MX51 + */ + +/*! + * @file mx51_3stack/board-imx51.h + * + * @brief This file contains all the board level configuration options. + * + * It currently hold the options defined for MX51 3Stack Platform. + * + * @ingroup BRDCFG_IMX51 + */ + +/* CPLD offsets */ +#define PBC_LED_CTRL (0x20000) +#define PBC_SB_STAT (0x20008) +#define PBC_ID_AAAA (0x20040) +#define PBC_ID_5555 (0x20048) +#define PBC_VERSION (0x20050) +#define PBC_ID_CAFE (0x20058) +#define PBC_INT_STAT (0x20010) +#define PBC_INT_MASK (0x20038) +#define PBC_INT_REST (0x20020) +#define PBC_SW_RESET (0x20060) + +/* LED switchs */ +#define LED_SWITCH_REG 0x00 +/* buttons */ +#define SWITCH_BUTTONS_REG 0x08 +/* status, interrupt */ +#define INTR_STATUS_REG 0x10 +#define INTR_MASK_REG 0x38 +#define INTR_RESET_REG 0x20 +/* magic word for debug CPLD */ +#define MAGIC_NUMBER1_REG 0x40 +#define MAGIC_NUMBER2_REG 0x48 +/* CPLD code version */ +#define CPLD_CODE_VER_REG 0x50 +/* magic word for debug CPLD */ +#define MAGIC_NUMBER3_REG 0x58 +/* module reset register*/ +#define MODULE_RESET_REG 0x60 +/* CPU ID and Personality ID */ +#define MCU_BOARD_ID_REG 0x68 + +#endif /* __BOARD_FREESCALE_BOARD_IMX51_H__ */ diff --git a/board/freescale/mx51_bbg/config.mk b/board/freescale/mx51_bbg/config.mk new file mode 100644 index 0000000000..97e8856a3e --- /dev/null +++ b/board/freescale/mx51_bbg/config.mk @@ -0,0 +1,7 @@ +LDSCRIPT := $(SRCTREE)/board/$(VENDOR)/$(BOARD)/u-boot.lds + +sinclude $(OBJTREE)/board/$(VENDOR)/$(BOARD)/config.tmp + +ifndef TEXT_BASE + TEXT_BASE = 0x97800000 +endif diff --git a/board/freescale/mx51_bbg/flash_header.S b/board/freescale/mx51_bbg/flash_header.S new file mode 100644 index 0000000000..72d0e81fc9 --- /dev/null +++ b/board/freescale/mx51_bbg/flash_header.S @@ -0,0 +1,112 @@ +/* + * (C) Copyright 2009-2010 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include "board-imx51.h" + +#ifdef CONFIG_FLASH_HEADER +#ifndef CONFIG_FLASH_HEADER_OFFSET +# error "Must define the offset of flash header" +#endif +#define MXC_DCD_ITEM(i, type, addr, val) \ +dcd_node_##i: \ + .word type ; \ + .word addr ; \ + .word val ; \ + +.section ".text.flasheader", "x" + b _start + .org CONFIG_FLASH_HEADER_OFFSET +app_code_jump_v: .word _start +app_code_code_barker: .word CONFIG_FLASH_HEADER_BARKER +app_code_csf: .word 0 +dcd_ptr_ptr: .word dcd_ptr +super_root_key: .word 0 +dcd_ptr: .word dcd_array_start +app_dest_ptr: .word TEXT_BASE +dcd_array_start: +magic: .word 0xB17219E9 +dcd_array_size: .word dcd_data_end - dcd_array_start - 8 +/* DCD */ +/* DDR2 IOMUX configuration */ +MXC_DCD_ITEM(1, 4, IOMUXC_BASE_ADDR + 0x8a0, 0x200) +MXC_DCD_ITEM(2, 4, IOMUXC_BASE_ADDR + 0x50c, 0x20c5) +MXC_DCD_ITEM(3, 4, IOMUXC_BASE_ADDR + 0x510, 0x20c5) +MXC_DCD_ITEM(4, 4, IOMUXC_BASE_ADDR + 0x83c, 0x2) +MXC_DCD_ITEM(5, 4, IOMUXC_BASE_ADDR + 0x848, 0x2) +MXC_DCD_ITEM(6, 4, IOMUXC_BASE_ADDR + 0x4b8, 0xe7) +MXC_DCD_ITEM(7, 4, IOMUXC_BASE_ADDR + 0x4bc, 0x45) +MXC_DCD_ITEM(8, 4, IOMUXC_BASE_ADDR + 0x4c0, 0x45) +MXC_DCD_ITEM(9, 4, IOMUXC_BASE_ADDR + 0x4c4, 0x45) +MXC_DCD_ITEM(10, 4, IOMUXC_BASE_ADDR + 0x4c8, 0x45) +MXC_DCD_ITEM(11, 4, IOMUXC_BASE_ADDR + 0x820, 0x0) +MXC_DCD_ITEM(12, 4, IOMUXC_BASE_ADDR + 0x4a4, 0x3) +MXC_DCD_ITEM(13, 4, IOMUXC_BASE_ADDR + 0x4a8, 0x3) +MXC_DCD_ITEM(14, 4, IOMUXC_BASE_ADDR + 0x4ac, 0xe3) +MXC_DCD_ITEM(15, 4, IOMUXC_BASE_ADDR + 0x4b0, 0xe3) +MXC_DCD_ITEM(16, 4, IOMUXC_BASE_ADDR + 0x4b4, 0xe3) +MXC_DCD_ITEM(17, 4, IOMUXC_BASE_ADDR + 0x4cc, 0xe3) +MXC_DCD_ITEM(18, 4, IOMUXC_BASE_ADDR + 0x4d0, 0xe2) +/* Set drive strength to MAX */ +MXC_DCD_ITEM(19, 4, IOMUXC_BASE_ADDR + 0x82c, 0x4) +MXC_DCD_ITEM(20, 4, IOMUXC_BASE_ADDR + 0x8a4, 0x4) +MXC_DCD_ITEM(21, 4, IOMUXC_BASE_ADDR + 0x8ac, 0x4) +MXC_DCD_ITEM(22, 4, IOMUXC_BASE_ADDR + 0x8b8, 0x4) +/* 13 ROW, 10 COL, 32Bit, SREF=4 Micron Model */ +/* CAS=3, BL=4 */ +MXC_DCD_ITEM(23, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCTL0, 0x82a20000) +MXC_DCD_ITEM(24, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCTL1, 0x82a20000) +MXC_DCD_ITEM(25, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDMISC, 0x000ad0d0) +MXC_DCD_ITEM(26, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCFG0, 0x333584ab) +MXC_DCD_ITEM(27, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCFG1, 0x333584ab) +/* Init DRAM on CS0 */ +MXC_DCD_ITEM(28, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x04008008) +MXC_DCD_ITEM(29, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0000801a) +MXC_DCD_ITEM(30, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0000801b) +MXC_DCD_ITEM(31, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00448019) +MXC_DCD_ITEM(32, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x07328018) +MXC_DCD_ITEM(33, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x04008008) +MXC_DCD_ITEM(34, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008010) +MXC_DCD_ITEM(35, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008010) +MXC_DCD_ITEM(36, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x06328018) +MXC_DCD_ITEM(37, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x03808019) +MXC_DCD_ITEM(38, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00408019) +MXC_DCD_ITEM(39, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008000) +/* Init DRAM on CS1 */ +MXC_DCD_ITEM(40, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0400800c) +MXC_DCD_ITEM(41, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0000801e) +MXC_DCD_ITEM(42, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0000801f) +MXC_DCD_ITEM(43, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0000801d) +MXC_DCD_ITEM(44, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0732801c) +MXC_DCD_ITEM(45, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0400800c) +MXC_DCD_ITEM(46, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008014) +MXC_DCD_ITEM(47, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008014) +MXC_DCD_ITEM(48, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0632801c) +MXC_DCD_ITEM(49, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0380801d) +MXC_DCD_ITEM(50, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0040801d) +MXC_DCD_ITEM(51, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008004) +MXC_DCD_ITEM(52, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCTL0, 0xb2a20000) +MXC_DCD_ITEM(53, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCTL1, 0xb2a20000) +MXC_DCD_ITEM(54, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDMISC, 0x000ad6d0) +MXC_DCD_ITEM(55, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCDLYGD, 0x90000000) +MXC_DCD_ITEM(56, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00000000) +dcd_data_end: +image_len: .word _end - TEXT_BASE +#endif diff --git a/board/freescale/mx51_bbg/lowlevel_init.S b/board/freescale/mx51_bbg/lowlevel_init.S new file mode 100644 index 0000000000..f7f780a097 --- /dev/null +++ b/board/freescale/mx51_bbg/lowlevel_init.S @@ -0,0 +1,326 @@ +/* + * Copyright (C) 2007, Guennadi Liakhovetski + * + * (C) Copyright 2009-2010 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include "board-imx51.h" + +/* + * return soc version + * 0x10: TO1 + * 0x20: TO2 + * 0x30: TO3 + */ +.macro check_soc_version ret, tmp +.endm + +/* + * L2CC Cache setup/invalidation/disable + */ +.macro init_l2cc + /* explicitly disable L2 cache */ + mrc 15, 0, r0, c1, c0, 1 + bic r0, r0, #0x2 + mcr 15, 0, r0, c1, c0, 1 + + /* reconfigure L2 cache aux control reg */ + mov r0, #0xC0 /* tag RAM */ + add r0, r0, #0x4 /* data RAM */ + orr r0, r0, #(1 << 24) /* disable write allocate delay */ + orr r0, r0, #(1 << 23) /* disable write allocate combine */ + orr r0, r0, #(1 << 22) /* disable write allocate */ + + ldr r1, =0x00000000 + ldr r3, [r1, #ROM_SI_REV] + cmp r3, #0x10 /* r3 contains the silicon rev */ + orrls r0, r0, #(1 << 25) /* disable write combine for TO 2 and lower revs */ + + mcr 15, 1, r0, c9, c0, 2 +.endm /* init_l2cc */ + +/* AIPS setup - Only setup MPROTx registers. + * The PACR default values are good.*/ +.macro init_aips + /* + * Set all MPROTx to be non-bufferable, trusted for R/W, + * not forced to user-mode. + */ + ldr r0, =AIPS1_BASE_ADDR + ldr r1, =0x77777777 + str r1, [r0, #0x0] + str r1, [r0, #0x4] + ldr r0, =AIPS2_BASE_ADDR + str r1, [r0, #0x0] + str r1, [r0, #0x4] + /* + * Clear the on and off peripheral modules Supervisor Protect bit + * for SDMA to access them. Did not change the AIPS control registers + * (offset 0x20) access type + */ +.endm /* init_aips */ + +/* MAX (Multi-Layer AHB Crossbar Switch) setup */ +.macro init_max +.endm /* init_max */ + +/* M4IF setup */ +.macro init_m4if + /* VPU and IPU given higher priority (0x4) + * IPU accesses with ID=0x1 given highest priority (=0xA) + */ + ldr r0, =M4IF_BASE_ADDR + + ldr r1, =0x00000203 + str r1, [r0, #0x40] + + ldr r1, =0x0 + str r1, [r0, #0x44] + + ldr r1, =0x00120125 + str r1, [r0, #0x9C] + + ldr r1, =0x001901A3 + str r1, [r0, #0x48] + +/* + ldr r1, =0x00000a01 + str r1, [r0, #0x48] + ldr r1, =0x00000404 + str r1, [r0, #0x40] +*/ +.endm /* init_m4if */ + +/* To support 133MHz DDR */ +.macro init_drive_strength +.endm /* init_drive_strength */ + +/* CPLD on CS5 setup */ +.macro init_debug_board +.endm /* init_debug_board */ + +.macro setup_pll pll, freq + ldr r2, =\pll + ldr r1, =0x00001232 + str r1, [r2, #PLL_DP_CTL] /* Set DPLL ON (set UPEN bit): BRMO=1 */ + mov r1, #0x2 + str r1, [r2, #PLL_DP_CONFIG] /* Enable auto-restart AREN bit */ + + str r3, [r2, #PLL_DP_OP] + str r3, [r2, #PLL_DP_HFS_OP] + + str r4, [r2, #PLL_DP_MFD] + str r4, [r2, #PLL_DP_HFS_MFD] + + str r5, [r2, #PLL_DP_MFN] + str r5, [r2, #PLL_DP_HFS_MFN] + + ldr r1, =0x00001232 + str r1, [r2, #PLL_DP_CTL] +1: ldr r1, [r2, #PLL_DP_CTL] + ands r1, r1, #0x1 + beq 1b +.endm + +.macro init_clock + ldr r0, =CCM_BASE_ADDR + + /* Gate of clocks to the peripherals first */ + ldr r1, =0x3FFFFFFF + str r1, [r0, #CLKCTL_CCGR0] + ldr r1, =0x0 + str r1, [r0, #CLKCTL_CCGR1] + str r1, [r0, #CLKCTL_CCGR2] + str r1, [r0, #CLKCTL_CCGR3] + + ldr r1, =0x00030000 + str r1, [r0, #CLKCTL_CCGR4] + ldr r1, =0x00FFF030 + str r1, [r0, #CLKCTL_CCGR5] + ldr r1, =0x00000300 + str r1, [r0, #CLKCTL_CCGR6] + + /* Disable IPU and HSC dividers */ + mov r1, #0x60000 + str r1, [r0, #CLKCTL_CCDR] + + /* Make sure to switch the DDR away from PLL 1 */ + ldr r1, =0x19239145 + str r1, [r0, #CLKCTL_CBCDR] + /* make sure divider effective */ +1: ldr r1, [r0, #CLKCTL_CDHIPR] + cmp r1, #0x0 + bne 1b + + /* Switch ARM to step clock */ + mov r1, #0x4 + str r1, [r0, #CLKCTL_CCSR] + mov r3, #DP_OP_800 + mov r4, #DP_MFD_800 + mov r5, #DP_MFN_800 + setup_pll PLL1_BASE_ADDR + + mov r3, #DP_OP_665 + mov r4, #DP_MFD_665 + mov r5, #DP_MFN_665 + setup_pll PLL3_BASE_ADDR + + /* Switch peripheral to PLL 3 */ + ldr r0, =CCM_BASE_ADDR + ldr r1, =0x000010C0 + str r1, [r0, #CLKCTL_CBCMR] + ldr r1, =0x13239145 + str r1, [r0, #CLKCTL_CBCDR] + mov r3, #DP_OP_665 + mov r4, #DP_MFD_665 + mov r5, #DP_MFN_665 + setup_pll PLL2_BASE_ADDR + + /* Switch peripheral to PLL2 */ + ldr r0, =CCM_BASE_ADDR + ldr r1, =0x19239145 + str r1, [r0, #CLKCTL_CBCDR] + ldr r1, =0x000020C0 + str r1, [r0, #CLKCTL_CBCMR] + + mov r3, #DP_OP_216 + mov r4, #DP_MFD_216 + mov r5, #DP_MFN_216 + setup_pll PLL3_BASE_ADDR + + + /* Set the platform clock dividers */ + ldr r0, =ARM_BASE_ADDR + ldr r1, =0x00000725 + str r1, [r0, #0x14] + + ldr r0, =CCM_BASE_ADDR + /* Run TO 3.0 at Full speed, for other TO's wait till we increase VDDGP */ + ldr r1, =0x0 + ldr r3, [r1, #ROM_SI_REV] + cmp r3, #0x10 + movls r1, #0x1 + movhi r1, #0 + str r1, [r0, #CLKCTL_CACRR] + + /* Switch ARM back to PLL 1 */ + mov r1, #0 + str r1, [r0, #CLKCTL_CCSR] + + /* setup the rest */ + /* Use lp_apm (24MHz) source for perclk */ + ldr r1, =0x000020C2 + str r1, [r0, #CLKCTL_CBCMR] + /* ddr clock from PLL 1, all perclk dividers are 1 since using 24MHz */ + ldr r1, =0x59E35100 + str r1, [r0, #CLKCTL_CBCDR] + + /* Restore the default values in the Gate registers */ + ldr r1, =0xFFFFFFFF + str r1, [r0, #CLKCTL_CCGR0] + str r1, [r0, #CLKCTL_CCGR1] + str r1, [r0, #CLKCTL_CCGR2] + str r1, [r0, #CLKCTL_CCGR3] + str r1, [r0, #CLKCTL_CCGR4] + str r1, [r0, #CLKCTL_CCGR5] + str r1, [r0, #CLKCTL_CCGR6] + + /* Use PLL 2 for UART's, get 66.5MHz from it */ + ldr r1, =0xA5A2A020 + str r1, [r0, #CLKCTL_CSCMR1] + ldr r1, =0x00C30321 + str r1, [r0, #CLKCTL_CSCDR1] + + /* make sure divider effective */ +1: ldr r1, [r0, #CLKCTL_CDHIPR] + cmp r1, #0x0 + bne 1b + + mov r1, #0x0 + str r1, [r0, #CLKCTL_CCDR] + + /* for cko - for ARM div by 8 */ + mov r1, #0x000A0000 + add r1, r1, #0x00000F0 + str r1, [r0, #CLKCTL_CCOSR] +.endm + +.macro setup_wdog + ldr r0, =WDOG1_BASE_ADDR + mov r1, #0x30 + strh r1, [r0] +.endm + +.section ".text.init", "x" + +.globl lowlevel_init +lowlevel_init: + ldr r0, =GPIO1_BASE_ADDR + ldr r1, [r0, #0x0] + orr r1, r1, #(1 << 23) + str r1, [r0, #0x0] + ldr r1, [r0, #0x4] + orr r1, r1, #(1 << 23) + str r1, [r0, #0x4] + +#ifdef ENABLE_IMPRECISE_ABORT + mrs r1, spsr /* save old spsr */ + mrs r0, cpsr /* read out the cpsr */ + bic r0, r0, #0x100 /* clear the A bit */ + msr spsr, r0 /* update spsr */ + add lr, pc, #0x8 /* update lr */ + movs pc, lr /* update cpsr */ + nop + nop + nop + nop + msr spsr, r1 /* restore old spsr */ +#endif + + /* ARM errata ID #468414 */ + mrc 15, 0, r1, c1, c0, 1 + orr r1, r1, #(1 << 5) /* enable L1NEON bit */ + mcr 15, 0, r1, c1, c0, 1 + + init_l2cc + + init_aips + + init_max + + init_m4if + + init_drive_strength + + init_clock + + init_debug_board + + /* return from mxc_nand_load */ + /* r12 saved upper lr*/ + b mxc_nand_load + +/* Board level setting value */ +DDR_PERCHARGE_CMD: .word 0x04008008 +DDR_REFRESH_CMD: .word 0x00008010 +DDR_LMR1_W: .word 0x00338018 +DDR_LMR_CMD: .word 0xB2220000 +DDR_TIMING_W: .word 0xB02567A9 +DDR_MISC_W: .word 0x000A0104 diff --git a/board/freescale/mx51_bbg/mx51_bbg.c b/board/freescale/mx51_bbg/mx51_bbg.c new file mode 100644 index 0000000000..1f49c0e7a0 --- /dev/null +++ b/board/freescale/mx51_bbg/mx51_bbg.c @@ -0,0 +1,1145 @@ +/* + * Copyright (C) 2007, Guennadi Liakhovetski + * + * (C) Copyright 2009-2010 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include "board-imx51.h" +#ifdef CONFIG_IMX_ECSPI +#include +#include +#endif + +#include + +#ifdef CONFIG_CMD_MMC +#include +#include +#endif + +#ifdef CONFIG_ARCH_MMU +#include +#include +#endif + +#ifdef CONFIG_GET_FEC_MAC_ADDR_FROM_IIM +#include +#endif + +#ifdef CONFIG_FSL_ANDROID +#include +#include +#include +#include +#include +#include +#include +#endif + +DECLARE_GLOBAL_DATA_PTR; + +static u32 system_rev; +static enum boot_device boot_dev; +u32 mx51_io_base_addr; + +static inline void setup_boot_device(void) +{ + uint *fis_addr = (uint *)IRAM_BASE_ADDR; + + switch (*fis_addr) { + case NAND_FLASH_BOOT: + boot_dev = NAND_BOOT; + break; + case SPI_NOR_FLASH_BOOT: + boot_dev = SPI_NOR_BOOT; + break; + case MMC_FLASH_BOOT: + boot_dev = MMC_BOOT; + break; + default: + { + uint soc_sbmr = readl(SRC_BASE_ADDR + 0x4); + uint bt_mem_ctl = soc_sbmr & 0x00000003; + uint bt_mem_type = (soc_sbmr & 0x00000180) >> 7; + + switch (bt_mem_ctl) { + case 0x3: + if (bt_mem_type == 0) + boot_dev = MMC_BOOT; + else if (bt_mem_type == 3) + boot_dev = SPI_NOR_BOOT; + else + boot_dev = UNKNOWN_BOOT; + break; + case 0x1: + boot_dev = NAND_BOOT; + break; + default: + boot_dev = UNKNOWN_BOOT; + } + } + break; + } +} + +enum boot_device get_boot_device(void) +{ + return boot_dev; +} + +u32 get_board_rev(void) +{ + return system_rev; +} + +static inline void setup_soc_rev(void) +{ + int reg; +#ifdef CONFIG_ARCH_MMU + reg = __REG(0x20000000 + ROM_SI_REV); /* Virtual address */ +#else + reg = __REG(ROM_SI_REV); +#endif + + switch (reg) { + case 0x02: + system_rev = 0x51000 | CHIP_REV_1_1; + break; + case 0x10: + system_rev = 0x51000 | CHIP_REV_2_0; + break; + case 0x20: + system_rev = 0x51000 | CHIP_REV_3_0; + break; + default: + system_rev = 0x51000 | CHIP_REV_1_0; + } +} + +static inline void set_board_rev(void) +{ + if ((__REG(GPIO1_BASE_ADDR + 0x0) & (0x1 << 22)) == 0) + system_rev |= BOARD_REV_2_0 << BOARD_VER_OFFSET; + +} + +inline int is_soc_rev(int rev) +{ + return (system_rev & 0xFF) - rev; +} + +#ifdef CONFIG_ARCH_MMU +void board_mmu_init(void) +{ + unsigned long ttb_base = PHYS_SDRAM_1 + 0x4000; + unsigned long i; + + /* + * Set the TTB register + */ + asm volatile ("mcr p15, 0, %0, c2, c0, 0" : : "r"(ttb_base) /*:*/); + + /* + * Set the Domain Access Control Register + */ + i = ARM_ACCESS_DACR_DEFAULT; + asm volatile ("mcr p15, 0, %0, c3, c0, 0" : : "r"(i) /*:*/); + + /* + * First clear all TT entries - ie Set them to Faulting + */ + memset((void *)ttb_base, 0, ARM_FIRST_LEVEL_PAGE_TABLE_SIZE); + /* Actual Virtual Size Attributes Function */ + /* Base Base MB cached? buffered? access permissions */ + /* xxx00000 xxx00000 */ + X_ARM_MMU_SECTION(0x000, 0x200, 0x1, + ARM_UNCACHEABLE, ARM_UNBUFFERABLE, + ARM_ACCESS_PERM_RW_RW); /* ROM */ + X_ARM_MMU_SECTION(0x1FF, 0x1FF, 0x001, + ARM_UNCACHEABLE, ARM_UNBUFFERABLE, + ARM_ACCESS_PERM_RW_RW); /* IRAM */ + X_ARM_MMU_SECTION(0x300, 0x300, 0x100, + ARM_UNCACHEABLE, ARM_UNBUFFERABLE, + ARM_ACCESS_PERM_RW_RW); /* GPU */ + X_ARM_MMU_SECTION(0x400, 0x400, 0x200, + ARM_UNCACHEABLE, ARM_UNBUFFERABLE, + ARM_ACCESS_PERM_RW_RW); /* IPUv3D */ + X_ARM_MMU_SECTION(0x600, 0x600, 0x300, + ARM_UNCACHEABLE, ARM_UNBUFFERABLE, + ARM_ACCESS_PERM_RW_RW); /* periperals */ + X_ARM_MMU_SECTION(0x900, 0x000, 0x1FF, + ARM_CACHEABLE, ARM_BUFFERABLE, + ARM_ACCESS_PERM_RW_RW); /* SDRAM */ + X_ARM_MMU_SECTION(0x900, 0x900, 0x200, + ARM_CACHEABLE, ARM_BUFFERABLE, + ARM_ACCESS_PERM_RW_RW); /* SDRAM */ + X_ARM_MMU_SECTION(0x900, 0xE00, 0x200, + ARM_UNCACHEABLE, ARM_UNBUFFERABLE, + ARM_ACCESS_PERM_RW_RW); /* SDRAM 0:128M*/ + X_ARM_MMU_SECTION(0xB80, 0xB80, 0x10, + ARM_UNCACHEABLE, ARM_UNBUFFERABLE, + ARM_ACCESS_PERM_RW_RW); /* CS1 EIM control*/ + X_ARM_MMU_SECTION(0xCC0, 0xCC0, 0x040, + ARM_UNCACHEABLE, ARM_UNBUFFERABLE, + ARM_ACCESS_PERM_RW_RW); /* CS4/5/NAND Flash buffer */ + + /* Workaround for arm errata #709718 */ + /* Setup PRRR so device is always mapped to non-shared */ + asm volatile ("mrc p15, 0, %0, c10, c2, 0" : "=r"(i) : /*:*/); + i &= (~(3 << 0x10)); + asm volatile ("mcr p15, 0, %0, c10, c2, 0" : : "r"(i) /*:*/); + + /* Enable MMU */ + MMU_ON(); +} +#endif + +int dram_init(void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + return 0; +} + +static void setup_uart(void) +{ + unsigned int pad = PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE | + PAD_CTL_PUE_PULL | PAD_CTL_DRV_HIGH; + mxc_request_iomux(MX51_PIN_UART1_RXD, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX51_PIN_UART1_RXD, pad | PAD_CTL_SRE_FAST); + mxc_request_iomux(MX51_PIN_UART1_TXD, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX51_PIN_UART1_TXD, pad | PAD_CTL_SRE_FAST); + mxc_request_iomux(MX51_PIN_UART1_RTS, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX51_PIN_UART1_RTS, pad); + mxc_request_iomux(MX51_PIN_UART1_CTS, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX51_PIN_UART1_CTS, pad); + /* enable GPIO1_9 for CLK0 and GPIO1_8 for CLK02 */ + writel(0x00000004, 0x73fa83e8); + writel(0x00000004, 0x73fa83ec); +} + +void setup_nfc(void) +{ + /* Enable NFC IOMUX */ + mxc_request_iomux(MX51_PIN_NANDF_CS0, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX51_PIN_NANDF_CS1, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX51_PIN_NANDF_CS2, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX51_PIN_NANDF_CS3, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX51_PIN_NANDF_CS4, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX51_PIN_NANDF_CS5, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX51_PIN_NANDF_CS6, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX51_PIN_NANDF_CS7, IOMUX_CONFIG_ALT0); +} + +static void setup_expio(void) +{ + u32 reg; + /* CS5 setup */ + mxc_request_iomux(MX51_PIN_EIM_CS5, IOMUX_CONFIG_ALT0); + writel(0x00410089, WEIM_BASE_ADDR + 0x78 + CSGCR1); + writel(0x00000002, WEIM_BASE_ADDR + 0x78 + CSGCR2); + /* RWSC=50, RADVA=2, RADVN=6, OEA=0, OEN=0, RCSA=0, RCSN=0 */ + writel(0x32260000, WEIM_BASE_ADDR + 0x78 + CSRCR1); + /* APR = 0 */ + writel(0x00000000, WEIM_BASE_ADDR + 0x78 + CSRCR2); + /* WAL=0, WBED=1, WWSC=50, WADVA=2, WADVN=6, WEA=0, WEN=0, + * WCSA=0, WCSN=0 + */ + writel(0x72080F00, WEIM_BASE_ADDR + 0x78 + CSWCR1); + if ((readw(CS5_BASE_ADDR + PBC_ID_AAAA) == 0xAAAA) && + (readw(CS5_BASE_ADDR + PBC_ID_5555) == 0x5555)) { + if (is_soc_rev(CHIP_REV_2_0) < 0) { + reg = readl(CCM_BASE_ADDR + CLKCTL_CBCDR); + reg = (reg & (~0x70000)) | 0x30000; + writel(reg, CCM_BASE_ADDR + CLKCTL_CBCDR); + /* make sure divider effective */ + while (readl(CCM_BASE_ADDR + CLKCTL_CDHIPR) != 0) + ; + writel(0x0, CCM_BASE_ADDR + CLKCTL_CCDR); + } + mx51_io_base_addr = CS5_BASE_ADDR; + } else { + /* CS1 */ + writel(0x00410089, WEIM_BASE_ADDR + 0x18 + CSGCR1); + writel(0x00000002, WEIM_BASE_ADDR + 0x18 + CSGCR2); + /* RWSC=50, RADVA=2, RADVN=6, OEA=0, OEN=0, RCSA=0, RCSN=0 */ + writel(0x32260000, WEIM_BASE_ADDR + 0x18 + CSRCR1); + /* APR=0 */ + writel(0x00000000, WEIM_BASE_ADDR + 0x18 + CSRCR2); + /* WAL=0, WBED=1, WWSC=50, WADVA=2, WADVN=6, WEA=0, + * WEN=0, WCSA=0, WCSN=0 + */ + writel(0x72080F00, WEIM_BASE_ADDR + 0x18 + CSWCR1); + mx51_io_base_addr = CS1_BASE_ADDR; + } + + /* Reset interrupt status reg */ + writew(0x1F, mx51_io_base_addr + PBC_INT_REST); + writew(0x00, mx51_io_base_addr + PBC_INT_REST); + writew(0xFFFF, mx51_io_base_addr + PBC_INT_MASK); + + /* Reset the XUART and Ethernet controllers */ + reg = readw(mx51_io_base_addr + PBC_SW_RESET); + reg |= 0x9; + writew(reg, mx51_io_base_addr + PBC_SW_RESET); + reg &= ~0x9; + writew(reg, mx51_io_base_addr + PBC_SW_RESET); +} + +#ifdef CONFIG_IMX_ECSPI +s32 spi_get_cfg(struct imx_spi_dev_t *dev) +{ + switch (dev->slave.cs) { + case 0: + /* pmic */ + dev->base = CSPI1_BASE_ADDR; + dev->freq = 2500000; + dev->ss_pol = IMX_SPI_ACTIVE_HIGH; + dev->ss = 0; + dev->fifo_sz = 64 * 4; + dev->us_delay = 0; + break; + case 1: + /* spi_nor */ + dev->base = CSPI1_BASE_ADDR; + dev->freq = 2500000; + dev->ss_pol = IMX_SPI_ACTIVE_LOW; + dev->ss = 1; + dev->fifo_sz = 64 * 4; + dev->us_delay = 0; + break; + default: + printf("Invalid Bus ID! \n"); + break; + } + + return 0; +} + +void spi_io_init(struct imx_spi_dev_t *dev) +{ + switch (dev->base) { + case CSPI1_BASE_ADDR: + /* 000: Select mux mode: ALT0 mux port: MOSI of instance: ecspi1 */ + mxc_request_iomux(MX51_PIN_CSPI1_MOSI, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX51_PIN_CSPI1_MOSI, 0x105); + + /* 000: Select mux mode: ALT0 mux port: MISO of instance: ecspi1. */ + mxc_request_iomux(MX51_PIN_CSPI1_MISO, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX51_PIN_CSPI1_MISO, 0x105); + + if (dev->ss == 0) { + /* de-select SS1 of instance: ecspi1. */ + mxc_request_iomux(MX51_PIN_CSPI1_SS1, IOMUX_CONFIG_ALT3); + mxc_iomux_set_pad(MX51_PIN_CSPI1_SS1, 0x85); + /* 000: Select mux mode: ALT0 mux port: SS0 of instance: ecspi1. */ + mxc_request_iomux(MX51_PIN_CSPI1_SS0, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX51_PIN_CSPI1_SS0, 0x185); + } else if (dev->ss == 1) { + /* de-select SS0 of instance: ecspi1. */ + mxc_request_iomux(MX51_PIN_CSPI1_SS0, IOMUX_CONFIG_ALT3); + mxc_iomux_set_pad(MX51_PIN_CSPI1_SS0, 0x85); + /* 000: Select mux mode: ALT0 mux port: SS1 of instance: ecspi1. */ + mxc_request_iomux(MX51_PIN_CSPI1_SS1, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX51_PIN_CSPI1_SS1, 0x105); + } + + /* 000: Select mux mode: ALT0 mux port: RDY of instance: ecspi1. */ + mxc_request_iomux(MX51_PIN_CSPI1_RDY, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX51_PIN_CSPI1_RDY, 0x180); + + /* 000: Select mux mode: ALT0 mux port: SCLK of instance: ecspi1. */ + mxc_request_iomux(MX51_PIN_CSPI1_SCLK, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX51_PIN_CSPI1_SCLK, 0x105); + break; + case CSPI2_BASE_ADDR: + default: + break; + } +} +#endif + +#ifdef CONFIG_MXC_FEC + +#ifdef CONFIG_GET_FEC_MAC_ADDR_FROM_IIM + +int fec_get_mac_addr(unsigned char *mac) +{ + u32 *iim1_mac_base = + (u32 *)(IIM_BASE_ADDR + IIM_BANK_AREA_1_OFFSET + + CONFIG_IIM_MAC_ADDR_OFFSET); + int i; + + for (i = 0; i < 6; ++i, ++iim1_mac_base) + mac[i] = (u8)readl(iim1_mac_base); + + return 0; +} +#endif + +static void setup_fec(void) +{ + /*FEC_MDIO*/ + writel(0x3, IOMUXC_BASE_ADDR + 0x0D4); + writel(0x1FD, IOMUXC_BASE_ADDR + 0x0468); + writel(0x0, IOMUXC_BASE_ADDR + 0x0954); + + /*FEC_MDC*/ + writel(0x2, IOMUXC_BASE_ADDR + 0x13C); + writel(0x2004, IOMUXC_BASE_ADDR + 0x0524); + + /* FEC RDATA[3] */ + writel(0x3, IOMUXC_BASE_ADDR + 0x0EC); + writel(0x180, IOMUXC_BASE_ADDR + 0x0480); + writel(0x0, IOMUXC_BASE_ADDR + 0x0964); + + /* FEC RDATA[2] */ + writel(0x3, IOMUXC_BASE_ADDR + 0x0E8); + writel(0x180, IOMUXC_BASE_ADDR + 0x047C); + writel(0x0, IOMUXC_BASE_ADDR + 0x0960); + + /* FEC RDATA[1] */ + writel(0x3, IOMUXC_BASE_ADDR + 0x0d8); + writel(0x180, IOMUXC_BASE_ADDR + 0x046C); + writel(0x0, IOMUXC_BASE_ADDR + 0x095C); + + /* FEC RDATA[0] */ + writel(0x2, IOMUXC_BASE_ADDR + 0x016C); + writel(0x2180, IOMUXC_BASE_ADDR + 0x0554); + writel(0x0, IOMUXC_BASE_ADDR + 0x0958); + + /* FEC TDATA[3] */ + writel(0x2, IOMUXC_BASE_ADDR + 0x148); + writel(0x2004, IOMUXC_BASE_ADDR + 0x0530); + + /* FEC TDATA[2] */ + writel(0x2, IOMUXC_BASE_ADDR + 0x144); + writel(0x2004, IOMUXC_BASE_ADDR + 0x052C); + + /* FEC TDATA[1] */ + writel(0x2, IOMUXC_BASE_ADDR + 0x140); + writel(0x2004, IOMUXC_BASE_ADDR + 0x0528); + + /* FEC TDATA[0] */ + writel(0x2, IOMUXC_BASE_ADDR + 0x0170); + writel(0x2004, IOMUXC_BASE_ADDR + 0x0558); + + /* FEC TX_EN */ + writel(0x1, IOMUXC_BASE_ADDR + 0x014C); + writel(0x2004, IOMUXC_BASE_ADDR + 0x0534); + + /* FEC TX_ER */ + writel(0x2, IOMUXC_BASE_ADDR + 0x0138); + writel(0x2004, IOMUXC_BASE_ADDR + 0x0520); + + /* FEC TX_CLK */ + writel(0x1, IOMUXC_BASE_ADDR + 0x0150); + writel(0x2180, IOMUXC_BASE_ADDR + 0x0538); + writel(0x0, IOMUXC_BASE_ADDR + 0x0974); + + /* FEC COL */ + writel(0x1, IOMUXC_BASE_ADDR + 0x0124); + writel(0x2180, IOMUXC_BASE_ADDR + 0x0500); + writel(0x0, IOMUXC_BASE_ADDR + 0x094c); + + /* FEC RX_CLK */ + writel(0x1, IOMUXC_BASE_ADDR + 0x0128); + writel(0x2180, IOMUXC_BASE_ADDR + 0x0504); + writel(0x0, IOMUXC_BASE_ADDR + 0x0968); + + /* FEC CRS */ + writel(0x3, IOMUXC_BASE_ADDR + 0x0f4); + writel(0x180, IOMUXC_BASE_ADDR + 0x0488); + writel(0x0, IOMUXC_BASE_ADDR + 0x0950); + + /* FEC RX_ER */ + writel(0x3, IOMUXC_BASE_ADDR + 0x0f0); + writel(0x180, IOMUXC_BASE_ADDR + 0x0484); + writel(0x0, IOMUXC_BASE_ADDR + 0x0970); + + /* FEC RX_DV */ + writel(0x2, IOMUXC_BASE_ADDR + 0x164); + writel(0x2180, IOMUXC_BASE_ADDR + 0x054C); + writel(0x0, IOMUXC_BASE_ADDR + 0x096C); +} +#endif + +#ifdef CONFIG_I2C_MXC +static void setup_i2c(unsigned int module_base) +{ + unsigned int reg; + + switch (module_base) { + case I2C1_BASE_ADDR: + reg = IOMUXC_BASE_ADDR + 0x5c; /* i2c1 SDA */ + writel(0x14, reg); + reg = IOMUXC_BASE_ADDR + 0x3f0; + writel(0x10d, reg); + reg = IOMUXC_BASE_ADDR + 0x9B4; + writel(0x0, reg); + + reg = IOMUXC_BASE_ADDR + 0x68; /* i2c2 SCL */ + writel(0x14, reg); + reg = IOMUXC_BASE_ADDR + 0x3fc; + writel(0x10d, reg); + reg = IOMUXC_BASE_ADDR + 0x9B0; + writel(0x0, reg); + break; + case I2C2_BASE_ADDR: + /* dummy here*/ + break; + default: + printf("Invalid I2C base: 0x%x\n", module_base); + break; + } +} + +static void setup_core_voltage_i2c(void) +{ + unsigned int reg; + unsigned char buf[1] = { 0 }; + + puts("PMIC Mode: linear\n"); + + writel(0x0, CCM_BASE_ADDR + CLKCTL_CACRR); + reg = readl(GPIO2_BASE_ADDR + 0x0); + reg &= ~0x4000; /* Lower reset line */ + writel(reg, GPIO2_BASE_ADDR + 0x0); + + reg = readl(GPIO2_BASE_ADDR + 0x4); + reg |= 0x4000; /* configure GPIO lines as output */ + writel(reg, GPIO2_BASE_ADDR + 0x4); + + /* Reset the ethernet controller over GPIO */ + writel(0x1, IOMUXC_BASE_ADDR + 0x0AC); + + /*Configure LDO4*/ + i2c_read(0x34, 0x12, 1, buf, 1); + buf[0] = buf[0] | 0x40; + if (i2c_write(0x34, 0x12, 1, buf, 1)) { + puts("write to PMIC 0x12 failed!\n"); + return; + } + i2c_read(0x34, 0x12, 1, buf, 1); + printf("PMIC 0x12: 0x%x \n", buf[0]); + + i2c_read(0x34, 0x10, 1, buf, 1); + buf[0] = buf[0] | 0x40; + if (i2c_write(0x34, 0x10, 1, buf, 1)) { + puts("write to PMIC 0x10 failed!\n"); + return; + } + i2c_read(0x34, 0x10, 1, buf, 1); + printf("PMIC 0x10: 0x%x \n", buf[0]); + + udelay(500); + + reg = readl(GPIO2_BASE_ADDR + 0x0); + reg |= 0x4000; + writel(reg, GPIO2_BASE_ADDR + 0x0); +} +#endif + +#ifdef CONFIG_IMX_ECSPI +static void setup_core_voltage_spi(void) +{ + struct spi_slave *slave; + unsigned int val; + unsigned int reg; + + puts("PMIC Mode: SPI\n"); + +#define REV_ATLAS_LITE_1_0 0x8 +#define REV_ATLAS_LITE_1_1 0x9 +#define REV_ATLAS_LITE_2_0 0x10 +#define REV_ATLAS_LITE_2_1 0x11 + + slave = spi_pmic_probe(); + + /* Write needed to Power Gate 2 register */ + val = pmic_reg(slave, 34, 0, 0); + val &= ~0x10000; + pmic_reg(slave, 34, val, 1); + + /* Write needed to update Charger 0 */ + pmic_reg(slave, 48, 0x0023807F, 1); + + /* power up the system first */ + pmic_reg(slave, 34, 0x00200000, 1); + + if (is_soc_rev(CHIP_REV_2_0) >= 0) { + /* Set core voltage to 1.1V */ + val = pmic_reg(slave, 24, 0, 0); + val = (val & (~0x1F)) | 0x14; + pmic_reg(slave, 24, val, 1); + + /* Setup VCC (SW2) to 1.25 */ + val = pmic_reg(slave, 25, 0, 0); + val = (val & (~0x1F)) | 0x1A; + pmic_reg(slave, 25, val, 1); + + /* Setup 1V2_DIG1 (SW3) to 1.25 */ + val = pmic_reg(slave, 26, 0, 0); + val = (val & (~0x1F)) | 0x1A; + pmic_reg(slave, 26, val, 1); + udelay(50); + /* Raise the core frequency to 800MHz */ + writel(0x0, CCM_BASE_ADDR + CLKCTL_CACRR); + } else { + /* TO 3.0 */ + /* Setup VCC (SW2) to 1.225 */ + val = pmic_reg(slave, 25, 0, 0); + val = (val & (~0x1F)) | 0x19; + pmic_reg(slave, 25, val, 1); + + /* Setup 1V2_DIG1 (SW3) to 1.2 */ + val = pmic_reg(slave, 26, 0, 0); + val = (val & (~0x1F)) | 0x18; + pmic_reg(slave, 26, val, 1); + } + + if (((pmic_reg(slave, 7, 0, 0) & 0x1F) < REV_ATLAS_LITE_2_0) || + (((pmic_reg(slave, 7, 0, 0) >> 9) & 0x3) == 0)) { + /* Set switchers in PWM mode for Atlas 2.0 and lower */ + /* Setup the switcher mode for SW1 & SW2*/ + val = pmic_reg(slave, 28, 0, 0); + val = (val & (~0x3C0F)) | 0x1405; + pmic_reg(slave, 28, val, 1); + + /* Setup the switcher mode for SW3 & SW4 */ + val = pmic_reg(slave, 29, 0, 0); + val = (val & (~0xF0F)) | 0x505; + pmic_reg(slave, 29, val, 1); + } else { + /* Set switchers in Auto in NORMAL mode & STANDBY mode for Atlas 2.0a */ + /* Setup the switcher mode for SW1 & SW2*/ + val = pmic_reg(slave, 28, 0, 0); + val = (val & (~0x3C0F)) | 0x2008; + pmic_reg(slave, 28, val, 1); + + /* Setup the switcher mode for SW3 & SW4 */ + val = pmic_reg(slave, 29, 0, 0); + val = (val & (~0xF0F)) | 0x808; + pmic_reg(slave, 29, val, 1); + } + + /* Set VDIG to 1.65V, VGEN3 to 1.8V, VCAM to 2.5V */ + val = pmic_reg(slave, 30, 0, 0); + val &= ~0x34030; + val |= 0x10020; + pmic_reg(slave, 30, val, 1); + + /* Set VVIDEO to 2.775V, VAUDIO to 3V, VSD to 3.15V */ + val = pmic_reg(slave, 31, 0, 0); + val &= ~0x1FC; + val |= 0x1F4; + pmic_reg(slave, 31, val, 1); + + /* Configure VGEN3 and VCAM regulators to use external PNP */ + val = 0x208; + pmic_reg(slave, 33, val, 1); + udelay(200); + + reg = readl(GPIO2_BASE_ADDR + 0x0); + reg &= ~0x4000; /* Lower reset line */ + writel(reg, GPIO2_BASE_ADDR + 0x0); + + reg = readl(GPIO2_BASE_ADDR + 0x4); + reg |= 0x4000; /* configure GPIO lines as output */ + writel(reg, GPIO2_BASE_ADDR + 0x4); + + /* Reset the ethernet controller over GPIO */ + writel(0x1, IOMUXC_BASE_ADDR + 0x0AC); + + /* Enable VGEN3, VCAM, VAUDIO, VVIDEO, VSD regulators */ + val = 0x49249; + pmic_reg(slave, 33, val, 1); + + udelay(500); + + reg = readl(GPIO2_BASE_ADDR + 0x0); + reg |= 0x4000; + writel(reg, GPIO2_BASE_ADDR + 0x0); + + spi_pmic_free(slave); +} +#endif + +#ifdef CONFIG_NET_MULTI + +int board_eth_init(bd_t *bis) +{ + int rc = -ENODEV; + + return rc; +} +#endif + +#ifdef CONFIG_CMD_MMC + +struct fsl_esdhc_cfg esdhc_cfg[2] = { + {MMC_SDHC1_BASE_ADDR, 1, 1}, + {MMC_SDHC2_BASE_ADDR, 1, 1}, +}; + +#ifdef CONFIG_DYNAMIC_MMC_DEVNO +int get_mmc_env_devno() +{ + uint soc_sbmr = readl(SRC_BASE_ADDR + 0x4); + return (soc_sbmr & 0x00180000) ? 1 : 0; +} +#endif + +int esdhc_gpio_init(bd_t *bis) +{ + s32 status = 0; + u32 index = 0; + + for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; + ++index) { + switch (index) { + case 0: + mxc_request_iomux(MX51_PIN_SD1_CMD, + IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); + mxc_request_iomux(MX51_PIN_SD1_CLK, + IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); + + mxc_request_iomux(MX51_PIN_SD1_DATA0, + IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); + mxc_request_iomux(MX51_PIN_SD1_DATA1, + IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); + mxc_request_iomux(MX51_PIN_SD1_DATA2, + IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); + mxc_request_iomux(MX51_PIN_SD1_DATA3, + IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); + mxc_iomux_set_pad(MX51_PIN_SD1_CMD, + PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH | + PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU | + PAD_CTL_PUE_PULL | + PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST); + mxc_iomux_set_pad(MX51_PIN_SD1_CLK, + PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH | + PAD_CTL_HYS_NONE | PAD_CTL_47K_PU | + PAD_CTL_PUE_PULL | + PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST); + mxc_iomux_set_pad(MX51_PIN_SD1_DATA0, + PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH | + PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU | + PAD_CTL_PUE_PULL | + PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST); + mxc_iomux_set_pad(MX51_PIN_SD1_DATA1, + PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH | + PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU | + PAD_CTL_PUE_PULL | + PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST); + mxc_iomux_set_pad(MX51_PIN_SD1_DATA2, + PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH | + PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU | + PAD_CTL_PUE_PULL | + PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST); + mxc_iomux_set_pad(MX51_PIN_SD1_DATA3, + PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH | + PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PD | + PAD_CTL_PUE_PULL | + PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST); + break; + case 1: + mxc_request_iomux(MX51_PIN_SD2_CMD, + IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); + mxc_request_iomux(MX51_PIN_SD2_CLK, + IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); + + mxc_request_iomux(MX51_PIN_SD2_DATA0, + IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); + mxc_request_iomux(MX51_PIN_SD2_DATA1, + IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); + mxc_request_iomux(MX51_PIN_SD2_DATA2, + IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); + mxc_request_iomux(MX51_PIN_SD2_DATA3, + IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); + mxc_iomux_set_pad(MX51_PIN_SD2_CMD, + PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | + PAD_CTL_SRE_FAST); + mxc_iomux_set_pad(MX51_PIN_SD2_CLK, + PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | + PAD_CTL_SRE_FAST); + mxc_iomux_set_pad(MX51_PIN_SD2_DATA0, + PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | + PAD_CTL_SRE_FAST); + mxc_iomux_set_pad(MX51_PIN_SD2_DATA1, + PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | + PAD_CTL_SRE_FAST); + mxc_iomux_set_pad(MX51_PIN_SD2_DATA2, + PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | + PAD_CTL_SRE_FAST); + mxc_iomux_set_pad(MX51_PIN_SD2_DATA3, + PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | + PAD_CTL_SRE_FAST); + break; + default: + printf("Warning: you configured more ESDHC controller" + "(%d) as supported by the board(2)\n", + CONFIG_SYS_FSL_ESDHC_NUM); + return status; + break; + } + status |= fsl_esdhc_initialize(bis, &esdhc_cfg[index]); + } + + return status; +} + +int board_mmc_init(bd_t *bis) +{ + if (!esdhc_gpio_init(bis)) + return 0; + else + return -1; +} + +#endif + +#if defined(CONFIG_MXC_KPD) +int setup_mxc_kpd(void) +{ + mxc_request_iomux(MX51_PIN_KEY_COL0, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX51_PIN_KEY_COL1, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX51_PIN_KEY_COL2, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX51_PIN_KEY_COL3, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX51_PIN_KEY_COL4, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX51_PIN_KEY_COL5, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX51_PIN_KEY_ROW0, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX51_PIN_KEY_ROW1, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX51_PIN_KEY_ROW2, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX51_PIN_KEY_ROW3, IOMUX_CONFIG_ALT0); + + return 0; +} +#endif + +int board_init(void) +{ +#ifdef CONFIG_MFG +/* MFG firmware need reset usb to avoid host crash firstly */ +#define USBCMD 0x140 + int val = readl(OTG_BASE_ADDR + USBCMD); + val &= ~0x1; /*RS bit*/ + writel(val, OTG_BASE_ADDR + USBCMD); +#endif + setup_boot_device(); + setup_soc_rev(); + set_board_rev(); + + gd->bd->bi_arch_number = MACH_TYPE_MX51_BABBAGE; /* board id for linux */ + /* address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; + + setup_uart(); + setup_nfc(); + setup_expio(); +#ifdef CONFIG_MXC_FEC + setup_fec(); +#endif +#ifdef CONFIG_I2C_MXC + setup_i2c(I2C1_BASE_ADDR); +#endif + + return 0; +} + +#ifdef BOARD_LATE_INIT +#if defined(CONFIG_FSL_ANDROID) && defined(CONFIG_MXC_KPD) +inline int waiting_for_func_key_pressing(void) +{ + struct kpp_key_info key_info = {0, 0}; + int switch_delay = CONFIG_ANDROID_BOOTMOD_DELAY; + int state = 0, boot_mode_switch = 0; + + mxc_kpp_init(); + + puts("Press home + power to enter recovery mode ...\n"); + + while ((switch_delay > 0) && (!boot_mode_switch)) { + int i; + + --switch_delay; + /* delay 100 * 10ms */ + for (i = 0; !boot_mode_switch && i < 100; ++i) { + /* A state machine to scan home + power key */ + /* Check for home + power */ + if (mxc_kpp_getc(&key_info)) { + switch (state) { + case 0: + /* First press */ + if (TEST_HOME_KEY_DEPRESS(key_info.val, key_info.evt)) { + /* Press Home */ + state = 1; + } else if (TEST_POWER_KEY_DEPRESS(key_info.val, key_info.evt)) { + /* Press Power */ + state = 2; + } else { + state = 0; + } + break; + case 1: + /* Home is already pressed, try to detect Power */ + if (TEST_POWER_KEY_DEPRESS(key_info.val, + key_info.evt)) { + /* Switch */ + boot_mode_switch = 1; + } else { + if (TEST_HOME_KEY_DEPRESS(key_info.val, + key_info.evt)) { + /* Not switch */ + state = 2; + } else + state = 0; + } + break; + case 2: + /* Power is already pressed, try to detect Home */ + if (TEST_HOME_KEY_DEPRESS(key_info.val, + key_info.evt)) { + /* Switch */ + boot_mode_switch = 1; + } else { + if (TEST_POWER_KEY_DEPRESS(key_info.val, + key_info.evt)) { + /* Not switch */ + state = 1; + } else + state = 0; + } + break; + default: + break; + } + + if (1 == boot_mode_switch) + return 1; + } + } + for (i = 0; i < 100; ++i) + udelay(10000); + } + + return 0; +} + +inline int switch_to_recovery_mode(void) +{ + char *env = NULL; + char *boot_args = NULL; + char *boot_cmd = NULL; + + printf("Boot mode switched to recovery mode!\n"); + + switch (get_boot_device()) { + case MMC_BOOT: + boot_args = CONFIG_ANDROID_RECOVERY_BOOTARGS_MMC; + boot_cmd = CONFIG_ANDROID_RECOVERY_BOOTCMD_MMC; + break; + case NAND_BOOT: + printf("Recovery mode not supported in NAND boot\n"); + return -1; + break; + case SPI_NOR_BOOT: + printf("Recovery mode not supported in SPI NOR boot\n"); + return -1; + break; + case UNKNOWN_BOOT: + default: + printf("Unknown boot device!\n"); + return -1; + break; + } + + env = getenv("bootargs_android_recovery"); + /* Set env to recovery mode */ + if (!env) + setenv("bootargs_android", boot_args); + else + setenv("bootargs_android", env); + + env = getenv("bootcmd_android_recovery"); + if (!env) + setenv("bootcmd_android", boot_cmd); + else + setenv("bootcmd_android", env); + setenv("bootcmd", "run bootcmd_android"); + + return 0; +} + +inline int check_recovery_cmd_file(void) +{ + disk_partition_t info; + ulong part_length; + int filelen; + + switch (get_boot_device()) { + case MMC_BOOT: + { + block_dev_desc_t *dev_desc = NULL; + struct mmc *mmc = find_mmc_device(0); + + dev_desc = get_dev("mmc", 0); + + if (NULL == dev_desc) { + puts("** Block device MMC 0 not supported\n"); + return 0; + } + + mmc_init(mmc); + + if (get_partition_info(dev_desc, + CONFIG_ANDROID_CACHE_PARTITION_MMC, + &info)) { + printf("** Bad partition %d **\n", + CONFIG_ANDROID_CACHE_PARTITION_MMC); + return 0; + } + + part_length = ext2fs_set_blk_dev(dev_desc, + CONFIG_ANDROID_CACHE_PARTITION_MMC); + if (part_length == 0) { + printf("** Bad partition - mmc 0:%d **\n", + CONFIG_ANDROID_CACHE_PARTITION_MMC); + ext2fs_close(); + return 0; + } + + if (!ext2fs_mount(part_length)) { + printf("** Bad ext2 partition or disk - mmc 0:%d **\n", + CONFIG_ANDROID_CACHE_PARTITION_MMC); + ext2fs_close(); + return 0; + } + + filelen = ext2fs_open(CONFIG_ANDROID_RECOVERY_CMD_FILE); + + ext2fs_close(); + } + break; + case NAND_BOOT: + return 0; + break; + case SPI_NOR_BOOT: + return 0; + break; + case UNKNOWN_BOOT: + default: + return 0; + break; + } + + return (filelen > 0) ? 1 : 0; + +} +#endif + +int board_late_init(void) +{ +#ifdef CONFIG_I2C_MXC + i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); + if (!i2c_probe(0x34)) + setup_core_voltage_i2c(); + else +#endif +#ifdef CONFIG_IMX_ECSPI + setup_core_voltage_spi(); +#endif + +#if defined(CONFIG_FSL_ANDROID) && defined(CONFIG_MXC_KPD) + if (waiting_for_func_key_pressing()) + switch_to_recovery_mode(); + else { + if (check_recovery_cmd_file()) { + puts("Recovery command file founded!\n"); + switch_to_recovery_mode(); + } + } +#endif + + return 0; +} +#endif + +int checkboard(void) +{ + printf("Board: MX51 BABBAGE "); + + if (is_soc_rev(CHIP_REV_3_0) == 0) { + printf("3.0 ["); + } else if ((is_soc_rev(CHIP_REV_2_0) == 0) + && (system_rev & (BOARD_REV_2_0 << BOARD_VER_OFFSET))) { + printf("2.5 ["); + } else if (is_soc_rev(CHIP_REV_2_0) == 0) { + printf("2.0 ["); + } else if (is_soc_rev(CHIP_REV_1_1) == 0) { + printf("1.1 ["); + } else { + printf("1.0 ["); + } + + switch (__REG(SRC_BASE_ADDR + 0x8)) { + case 0x0001: + printf("POR"); + break; + case 0x0009: + printf("RST"); + break; + case 0x0010: + case 0x0011: + printf("WDOG"); + break; + default: + printf("unknown"); + } + printf("]\n"); + + printf("Boot Device: "); + switch (get_boot_device()) { + case NAND_BOOT: + printf("NAND\n"); + break; + case SPI_NOR_BOOT: + printf("SPI NOR\n"); + break; + case MMC_BOOT: + printf("MMC\n"); + break; + case UNKNOWN_BOOT: + default: + printf("UNKNOWN\n"); + break; + } + return 0; +} + diff --git a/board/freescale/mx51_bbg/u-boot.lds b/board/freescale/mx51_bbg/u-boot.lds new file mode 100644 index 0000000000..9ece8afacd --- /dev/null +++ b/board/freescale/mx51_bbg/u-boot.lds @@ -0,0 +1,73 @@ +/* + * January 2004 - Changed to support H4 device + * Copyright (c) 2004 Texas Instruments + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * (C) Copyright 2009 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + board/freescale/mx51_bbg/flash_header.o (.text.flasheader) + cpu/arm_cortexa8/start.o + board/freescale/mx51_bbg/libmx51_bbg.a (.text) + lib_arm/libarm.a (.text) + net/libnet.a (.text) + drivers/mtd/libmtd.a (.text) + drivers/mmc/libmmc.a (.text) + + . = DEFINED(env_offset) ? env_offset : .; + common/env_embedded.o(.text) + + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} diff --git a/board/freescale/mx53_evk/Makefile b/board/freescale/mx53_evk/Makefile new file mode 100644 index 0000000000..9e20903126 --- /dev/null +++ b/board/freescale/mx53_evk/Makefile @@ -0,0 +1,49 @@ +# +# Copyright (C) 2007, Guennadi Liakhovetski +# +# (C) Copyright 2010 Freescale Semiconductor, Inc. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := mx53_evk.o +SOBJS := lowlevel_init.o flash_header.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/freescale/mx53_evk/config.mk b/board/freescale/mx53_evk/config.mk new file mode 100644 index 0000000000..34f830a630 --- /dev/null +++ b/board/freescale/mx53_evk/config.mk @@ -0,0 +1,3 @@ +LDSCRIPT := $(SRCTREE)/board/$(VENDOR)/$(BOARD)/u-boot.lds + +TEXT_BASE = 0x77800000 diff --git a/board/freescale/mx53_evk/flash_header.S b/board/freescale/mx53_evk/flash_header.S new file mode 100644 index 0000000000..014333db1e --- /dev/null +++ b/board/freescale/mx53_evk/flash_header.S @@ -0,0 +1,250 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +#ifdef CONFIG_FLASH_HEADER +#ifndef CONFIG_FLASH_HEADER_OFFSET +# error "Must define the offset of flash header" +#endif + +#define CPU_2_BE_32(l) \ + ((((l) & 0x000000FF) << 24) | \ + (((l) & 0x0000FF00) << 8) | \ + (((l) & 0x00FF0000) >> 8) | \ + (((l) & 0xFF000000) >> 24)) + +#define MXC_DCD_ITEM(i, addr, val) \ +dcd_node_##i: \ + .word CPU_2_BE_32(addr) ; \ + .word CPU_2_BE_32(val) ; \ + +.section ".text.flasheader", "x" + b _start + .org CONFIG_FLASH_HEADER_OFFSET +ivt_header: .word 0x402000D1 /* Tag=0xD1, Len=0x0020, Ver=0x40 */ +app_code_jump_v: .word _start +reserv1: .word 0x0 +dcd_ptr: .word dcd_hdr +boot_data_ptr: .word boot_data +self_ptr: .word ivt_header +app_code_csf: .word 0x0 +reserv2: .word 0x0 + +boot_data: .word 0x77800000 +image_len: .word _end - TEXT_BASE +plugin: .word 0x0 + +#if defined(CONFIG_MX53_EVK) +dcd_hdr: .word 0x400802D2 /* Tag=0xD2, Len=64*8 + 4 + 4, Ver=0x40 */ +write_dcd_cmd: .word 0x040402CC /* Tag=0xCC, Len=64*8 + 4, Param=4 */ + +/* DCD */ +MXC_DCD_ITEM(1, IOMUXC_BASE_ADDR + 0x554, 0x00380000) +MXC_DCD_ITEM(2, IOMUXC_BASE_ADDR + 0x558, 0x00380040) +MXC_DCD_ITEM(3, IOMUXC_BASE_ADDR + 0x560, 0x00380000) +MXC_DCD_ITEM(4, IOMUXC_BASE_ADDR + 0x564, 0x00380040) +MXC_DCD_ITEM(5, IOMUXC_BASE_ADDR + 0x568, 0x00380040) +MXC_DCD_ITEM(6, IOMUXC_BASE_ADDR + 0x570, 0x00200000) +MXC_DCD_ITEM(7, IOMUXC_BASE_ADDR + 0x574, 0x00380000) +MXC_DCD_ITEM(8, IOMUXC_BASE_ADDR + 0x578, 0x00200000) +MXC_DCD_ITEM(9, IOMUXC_BASE_ADDR + 0x57c, 0x00380040) +MXC_DCD_ITEM(10, IOMUXC_BASE_ADDR + 0x580, 0x00380040) +MXC_DCD_ITEM(11, IOMUXC_BASE_ADDR + 0x584, 0x00380000) +MXC_DCD_ITEM(12, IOMUXC_BASE_ADDR + 0x588, 0x00380000) +MXC_DCD_ITEM(13, IOMUXC_BASE_ADDR + 0x590, 0x00380040) +MXC_DCD_ITEM(14, IOMUXC_BASE_ADDR + 0x594, 0x00380000) +MXC_DCD_ITEM(15, IOMUXC_BASE_ADDR + 0x6f0, 0x00380000) +MXC_DCD_ITEM(16, IOMUXC_BASE_ADDR + 0x6f4, 0x00000200) +MXC_DCD_ITEM(17, IOMUXC_BASE_ADDR + 0x6fc, 0x00000000) +MXC_DCD_ITEM(18, IOMUXC_BASE_ADDR + 0x714, 0x00000000) +MXC_DCD_ITEM(19, IOMUXC_BASE_ADDR + 0x718, 0x00380000) +MXC_DCD_ITEM(20, IOMUXC_BASE_ADDR + 0x71c, 0x00380000) +MXC_DCD_ITEM(21, IOMUXC_BASE_ADDR + 0x720, 0x00380000) +MXC_DCD_ITEM(22, IOMUXC_BASE_ADDR + 0x724, 0x06000000) +MXC_DCD_ITEM(23, IOMUXC_BASE_ADDR + 0x728, 0x00380000) +MXC_DCD_ITEM(24, IOMUXC_BASE_ADDR + 0x72c, 0x00380000) +MXC_DCD_ITEM(25, ESDCTL_BASE_ADDR + 0x088, 0x2b2f3031) +MXC_DCD_ITEM(26, ESDCTL_BASE_ADDR + 0x090, 0x40363333) +MXC_DCD_ITEM(27, ESDCTL_BASE_ADDR + 0x098, 0x00000f00) +MXC_DCD_ITEM(28, ESDCTL_BASE_ADDR + 0x0f8, 0x00000800) +MXC_DCD_ITEM(29, ESDCTL_BASE_ADDR + 0x07c, 0x01310132) +MXC_DCD_ITEM(30, ESDCTL_BASE_ADDR + 0x080, 0x0133014b) +MXC_DCD_ITEM(31, ESDCTL_BASE_ADDR + 0x018, 0x000016d0) +MXC_DCD_ITEM(32, ESDCTL_BASE_ADDR + 0x000, 0xc4110000) +MXC_DCD_ITEM(33, ESDCTL_BASE_ADDR + 0x00c, 0x4d5122d2) +MXC_DCD_ITEM(34, ESDCTL_BASE_ADDR + 0x010, 0x92d18a22) +MXC_DCD_ITEM(35, ESDCTL_BASE_ADDR + 0x014, 0x00c70092) +MXC_DCD_ITEM(36, ESDCTL_BASE_ADDR + 0x02c, 0x000026d2) +MXC_DCD_ITEM(37, ESDCTL_BASE_ADDR + 0x030, 0x009f000e) +MXC_DCD_ITEM(38, ESDCTL_BASE_ADDR + 0x008, 0x12272000) +MXC_DCD_ITEM(39, ESDCTL_BASE_ADDR + 0x004, 0x00030012) +MXC_DCD_ITEM(40, ESDCTL_BASE_ADDR + 0x01c, 0x04008010) +MXC_DCD_ITEM(41, ESDCTL_BASE_ADDR + 0x01c, 0x00008032) +MXC_DCD_ITEM(42, ESDCTL_BASE_ADDR + 0x01c, 0x00008033) +MXC_DCD_ITEM(43, ESDCTL_BASE_ADDR + 0x01c, 0x00008031) +MXC_DCD_ITEM(44, ESDCTL_BASE_ADDR + 0x01c, 0x0b5280b0) +MXC_DCD_ITEM(45, ESDCTL_BASE_ADDR + 0x01c, 0x04008010) +MXC_DCD_ITEM(46, ESDCTL_BASE_ADDR + 0x01c, 0x00008020) +MXC_DCD_ITEM(47, ESDCTL_BASE_ADDR + 0x01c, 0x00008020) +MXC_DCD_ITEM(48, ESDCTL_BASE_ADDR + 0x01c, 0x0a528030) +MXC_DCD_ITEM(49, ESDCTL_BASE_ADDR + 0x01c, 0x03c68031) +MXC_DCD_ITEM(50, ESDCTL_BASE_ADDR + 0x01c, 0x00468031) +MXC_DCD_ITEM(51, ESDCTL_BASE_ADDR + 0x01c, 0x04008018) +MXC_DCD_ITEM(52, ESDCTL_BASE_ADDR + 0x01c, 0x0000803a) +MXC_DCD_ITEM(53, ESDCTL_BASE_ADDR + 0x01c, 0x0000803b) +MXC_DCD_ITEM(54, ESDCTL_BASE_ADDR + 0x01c, 0x00008039) +MXC_DCD_ITEM(55, ESDCTL_BASE_ADDR + 0x01c, 0x0b528138) +MXC_DCD_ITEM(56, ESDCTL_BASE_ADDR + 0x01c, 0x04008018) +MXC_DCD_ITEM(57, ESDCTL_BASE_ADDR + 0x01c, 0x00008028) +MXC_DCD_ITEM(58, ESDCTL_BASE_ADDR + 0x01c, 0x00008028) +MXC_DCD_ITEM(59, ESDCTL_BASE_ADDR + 0x01c, 0x0a528038) +MXC_DCD_ITEM(60, ESDCTL_BASE_ADDR + 0x01c, 0x03c68039) +MXC_DCD_ITEM(61, ESDCTL_BASE_ADDR + 0x01c, 0x00468039) +MXC_DCD_ITEM(62, ESDCTL_BASE_ADDR + 0x020, 0x00005800) +MXC_DCD_ITEM(63, ESDCTL_BASE_ADDR + 0x058, 0x00033337) +MXC_DCD_ITEM(64, ESDCTL_BASE_ADDR + 0x01c, 0x00000000) + +#elif defined(CONFIG_MX53_ARM2) /*ARM2 board*/ +dcd_hdr: .word 0x400002D2 /* Tag=0xD2, Len=63*8 + 4 + 4, Ver=0x40 */ +write_dcd_cmd: .word 0x04FC01CC /* Tag=0xCC, Len=63*8 + 4, Param=4 */ + +/* DCD */ +MXC_DCD_ITEM(1, IOMUXC_BASE_ADDR + 0x554, 0x00380000) +MXC_DCD_ITEM(2, IOMUXC_BASE_ADDR + 0x558, 0x00380040) +MXC_DCD_ITEM(3, IOMUXC_BASE_ADDR + 0x560, 0x00380000) +MXC_DCD_ITEM(4, IOMUXC_BASE_ADDR + 0x564, 0x00380040) +MXC_DCD_ITEM(5, IOMUXC_BASE_ADDR + 0x568, 0x00380040) +MXC_DCD_ITEM(6, IOMUXC_BASE_ADDR + 0x570, 0x00380000) +MXC_DCD_ITEM(7, IOMUXC_BASE_ADDR + 0x574, 0x00380000) +MXC_DCD_ITEM(8, IOMUXC_BASE_ADDR + 0x578, 0x00380000) +MXC_DCD_ITEM(9, IOMUXC_BASE_ADDR + 0x57c, 0x00380040) +MXC_DCD_ITEM(10, IOMUXC_BASE_ADDR + 0x580, 0x00380040) +MXC_DCD_ITEM(11, IOMUXC_BASE_ADDR + 0x584, 0x00380000) +MXC_DCD_ITEM(12, IOMUXC_BASE_ADDR + 0x588, 0x00380000) +MXC_DCD_ITEM(13, IOMUXC_BASE_ADDR + 0x590, 0x00380040) +MXC_DCD_ITEM(14, IOMUXC_BASE_ADDR + 0x594, 0x00380000) +MXC_DCD_ITEM(15, IOMUXC_BASE_ADDR + 0x6f0, 0x00380000) +MXC_DCD_ITEM(16, IOMUXC_BASE_ADDR + 0x6f4, 0x00000200) +MXC_DCD_ITEM(17, IOMUXC_BASE_ADDR + 0x6fc, 0x00000000) +MXC_DCD_ITEM(18, IOMUXC_BASE_ADDR + 0x714, 0x00000000) +MXC_DCD_ITEM(19, IOMUXC_BASE_ADDR + 0x718, 0x00380000) +MXC_DCD_ITEM(20, IOMUXC_BASE_ADDR + 0x71c, 0x00380000) +MXC_DCD_ITEM(21, IOMUXC_BASE_ADDR + 0x720, 0x00380000) +MXC_DCD_ITEM(22, IOMUXC_BASE_ADDR + 0x724, 0x02000000) +MXC_DCD_ITEM(23, IOMUXC_BASE_ADDR + 0x728, 0x00380000) +MXC_DCD_ITEM(24, IOMUXC_BASE_ADDR + 0x72c, 0x00380000) +MXC_DCD_ITEM(25, ESDCTL_BASE_ADDR + 0x088, 0x2d313331) +MXC_DCD_ITEM(26, ESDCTL_BASE_ADDR + 0x090, 0x40363333) +MXC_DCD_ITEM(27, ESDCTL_BASE_ADDR + 0x0f8, 0x00000800) +MXC_DCD_ITEM(28, ESDCTL_BASE_ADDR + 0x07c, 0x020c0211) +MXC_DCD_ITEM(29, ESDCTL_BASE_ADDR + 0x080, 0x014c0155) +MXC_DCD_ITEM(30, ESDCTL_BASE_ADDR + 0x018, 0x00001710) +MXC_DCD_ITEM(31, ESDCTL_BASE_ADDR + 0x000, 0xc4110000) +MXC_DCD_ITEM(32, ESDCTL_BASE_ADDR + 0x00c, 0x4d5122d2) +MXC_DCD_ITEM(33, ESDCTL_BASE_ADDR + 0x010, 0x92d18a22) +MXC_DCD_ITEM(34, ESDCTL_BASE_ADDR + 0x014, 0x00c70092) +MXC_DCD_ITEM(35, ESDCTL_BASE_ADDR + 0x02c, 0x000026d2) +MXC_DCD_ITEM(36, ESDCTL_BASE_ADDR + 0x030, 0x009f000e) +MXC_DCD_ITEM(37, ESDCTL_BASE_ADDR + 0x008, 0x12272000) +MXC_DCD_ITEM(38, ESDCTL_BASE_ADDR + 0x004, 0x00030012) +MXC_DCD_ITEM(39, ESDCTL_BASE_ADDR + 0x01c, 0x04008010) +MXC_DCD_ITEM(40, ESDCTL_BASE_ADDR + 0x01c, 0x00008032) +MXC_DCD_ITEM(41, ESDCTL_BASE_ADDR + 0x01c, 0x00008033) +MXC_DCD_ITEM(42, ESDCTL_BASE_ADDR + 0x01c, 0x00008031) +MXC_DCD_ITEM(43, ESDCTL_BASE_ADDR + 0x01c, 0x0b5280b0) +MXC_DCD_ITEM(44, ESDCTL_BASE_ADDR + 0x01c, 0x04008010) +MXC_DCD_ITEM(45, ESDCTL_BASE_ADDR + 0x01c, 0x00008020) +MXC_DCD_ITEM(46, ESDCTL_BASE_ADDR + 0x01c, 0x00008020) +MXC_DCD_ITEM(47, ESDCTL_BASE_ADDR + 0x01c, 0x0a528030) +MXC_DCD_ITEM(48, ESDCTL_BASE_ADDR + 0x01c, 0x03c68031) +MXC_DCD_ITEM(49, ESDCTL_BASE_ADDR + 0x01c, 0x00468031) +MXC_DCD_ITEM(50, ESDCTL_BASE_ADDR + 0x01c, 0x04008018) +MXC_DCD_ITEM(51, ESDCTL_BASE_ADDR + 0x01c, 0x0000803a) +MXC_DCD_ITEM(52, ESDCTL_BASE_ADDR + 0x01c, 0x0000803b) +MXC_DCD_ITEM(53, ESDCTL_BASE_ADDR + 0x01c, 0x00008039) +MXC_DCD_ITEM(54, ESDCTL_BASE_ADDR + 0x01c, 0x0b528138) +MXC_DCD_ITEM(55, ESDCTL_BASE_ADDR + 0x01c, 0x04008018) +MXC_DCD_ITEM(56, ESDCTL_BASE_ADDR + 0x01c, 0x00008028) +MXC_DCD_ITEM(57, ESDCTL_BASE_ADDR + 0x01c, 0x00008028) +MXC_DCD_ITEM(58, ESDCTL_BASE_ADDR + 0x01c, 0x0a528038) +MXC_DCD_ITEM(59, ESDCTL_BASE_ADDR + 0x01c, 0x03c68039) +MXC_DCD_ITEM(60, ESDCTL_BASE_ADDR + 0x01c, 0x00468039) +MXC_DCD_ITEM(61, ESDCTL_BASE_ADDR + 0x020, 0x00005800) +MXC_DCD_ITEM(62, ESDCTL_BASE_ADDR + 0x058, 0x00033337) +MXC_DCD_ITEM(63, ESDCTL_BASE_ADDR + 0x01c, 0x00000000) +#elif defined(CONFIG_MX53_ARM2_DDR3) +dcd_hdr: .word 0x40A001D2 /* Tag=0xD2, Len=51*8 + 4 + 4, Ver=0x40 */ +write_dcd_cmd: .word 0x049C01CC /* Tag=0xCC, Len=51*8 + 4, Param=4 */ + +/* DCD */ +MXC_DCD_ITEM(1, IOMUXC_BASE_ADDR + 0x554, 0x00300000) +MXC_DCD_ITEM(2, IOMUXC_BASE_ADDR + 0x558, 0x00300040) +MXC_DCD_ITEM(3, IOMUXC_BASE_ADDR + 0x560, 0x00300000) +MXC_DCD_ITEM(4, IOMUXC_BASE_ADDR + 0x564, 0x00300040) +MXC_DCD_ITEM(5, IOMUXC_BASE_ADDR + 0x568, 0x00300040) +MXC_DCD_ITEM(6, IOMUXC_BASE_ADDR + 0x570, 0x00300000) +MXC_DCD_ITEM(7, IOMUXC_BASE_ADDR + 0x574, 0x00300000) +MXC_DCD_ITEM(8, IOMUXC_BASE_ADDR + 0x578, 0x00300000) +MXC_DCD_ITEM(9, IOMUXC_BASE_ADDR + 0x57c, 0x00300040) +MXC_DCD_ITEM(10, IOMUXC_BASE_ADDR + 0x580, 0x00300040) +MXC_DCD_ITEM(11, IOMUXC_BASE_ADDR + 0x584, 0x00300000) +MXC_DCD_ITEM(12, IOMUXC_BASE_ADDR + 0x588, 0x00300000) +MXC_DCD_ITEM(13, IOMUXC_BASE_ADDR + 0x590, 0x00300040) +MXC_DCD_ITEM(14, IOMUXC_BASE_ADDR + 0x594, 0x00300000) +MXC_DCD_ITEM(15, IOMUXC_BASE_ADDR + 0x6f0, 0x00300000) +MXC_DCD_ITEM(16, IOMUXC_BASE_ADDR + 0x6f4, 0x00000000) +MXC_DCD_ITEM(17, IOMUXC_BASE_ADDR + 0x6fc, 0x00000000) +MXC_DCD_ITEM(18, IOMUXC_BASE_ADDR + 0x714, 0x00000000) +MXC_DCD_ITEM(19, IOMUXC_BASE_ADDR + 0x718, 0x00300000) +MXC_DCD_ITEM(20, IOMUXC_BASE_ADDR + 0x71c, 0x00300000) +MXC_DCD_ITEM(21, IOMUXC_BASE_ADDR + 0x720, 0x00300000) +MXC_DCD_ITEM(22, IOMUXC_BASE_ADDR + 0x724, 0x04000000) +MXC_DCD_ITEM(23, IOMUXC_BASE_ADDR + 0x728, 0x00300000) +MXC_DCD_ITEM(24, IOMUXC_BASE_ADDR + 0x72c, 0x00300000) +MXC_DCD_ITEM(25, ESDCTL_BASE_ADDR + 0x088, 0x32383535) +MXC_DCD_ITEM(26, ESDCTL_BASE_ADDR + 0x090, 0x40383538) +MXC_DCD_ITEM(27, ESDCTL_BASE_ADDR + 0x07c, 0x0136014d) +MXC_DCD_ITEM(28, ESDCTL_BASE_ADDR + 0x080, 0x01510141) +MXC_DCD_ITEM(29, ESDCTL_BASE_ADDR + 0x018, 0x00091740) +MXC_DCD_ITEM(30, ESDCTL_BASE_ADDR + 0x000, 0xc4190000) +MXC_DCD_ITEM(31, ESDCTL_BASE_ADDR + 0x00c, 0x565a7543) +MXC_DCD_ITEM(32, ESDCTL_BASE_ADDR + 0x010, 0xb6ae8aa3) +MXC_DCD_ITEM(33, ESDCTL_BASE_ADDR + 0x014, 0x01ff00db) +MXC_DCD_ITEM(34, ESDCTL_BASE_ADDR + 0x02c, 0x000026d2) +MXC_DCD_ITEM(35, ESDCTL_BASE_ADDR + 0x030, 0x009f0e21) +MXC_DCD_ITEM(36, ESDCTL_BASE_ADDR + 0x008, 0x12272000) +MXC_DCD_ITEM(37, ESDCTL_BASE_ADDR + 0x004, 0x00030012) +MXC_DCD_ITEM(38, ESDCTL_BASE_ADDR + 0x01c, 0x00008032) +MXC_DCD_ITEM(39, ESDCTL_BASE_ADDR + 0x01c, 0x00008033) +MXC_DCD_ITEM(40, ESDCTL_BASE_ADDR + 0x01c, 0x00028031) +MXC_DCD_ITEM(41, ESDCTL_BASE_ADDR + 0x01c, 0x092080b0) +MXC_DCD_ITEM(42, ESDCTL_BASE_ADDR + 0x01c, 0x04008040) +MXC_DCD_ITEM(43, ESDCTL_BASE_ADDR + 0x01c, 0x0000803a) +MXC_DCD_ITEM(44, ESDCTL_BASE_ADDR + 0x01c, 0x0000803b) +MXC_DCD_ITEM(45, ESDCTL_BASE_ADDR + 0x01c, 0x00028039) +MXC_DCD_ITEM(46, ESDCTL_BASE_ADDR + 0x01c, 0x09208138) +MXC_DCD_ITEM(47, ESDCTL_BASE_ADDR + 0x01c, 0x04008048) +MXC_DCD_ITEM(48, ESDCTL_BASE_ADDR + 0x020, 0x00001800) +MXC_DCD_ITEM(49, ESDCTL_BASE_ADDR + 0x040, 0x04b80003) +MXC_DCD_ITEM(50, ESDCTL_BASE_ADDR + 0x058, 0x00022227) +MXC_DCD_ITEM(51, ESDCTL_BASE_ADDR + 0x01c, 0x00000000) +#endif +#endif diff --git a/board/freescale/mx53_evk/lowlevel_init.S b/board/freescale/mx53_evk/lowlevel_init.S new file mode 100644 index 0000000000..d5e9f66ba4 --- /dev/null +++ b/board/freescale/mx53_evk/lowlevel_init.S @@ -0,0 +1,219 @@ +/* + * Copyright (C) 2007, Guennadi Liakhovetski + * + * Copyright (C) 2010 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +/* + * L2CC Cache setup/invalidation/disable + */ +.macro init_l2cc + /* explicitly disable L2 cache */ + mrc 15, 0, r0, c1, c0, 1 + bic r0, r0, #0x2 + mcr 15, 0, r0, c1, c0, 1 + + /* reconfigure L2 cache aux control reg */ + mov r0, #0xC0 /* tag RAM */ + add r0, r0, #0x4 /* data RAM */ + orr r0, r0, #(1 << 24) /* disable write allocate delay */ + orr r0, r0, #(1 << 23) /* disable write allocate combine */ + orr r0, r0, #(1 << 22) /* disable write allocate */ + + mcr 15, 1, r0, c9, c0, 2 +.endm /* init_l2cc */ + +/* AIPS setup - Only setup MPROTx registers. + * The PACR default values are good.*/ +.macro init_aips + /* + * Set all MPROTx to be non-bufferable, trusted for R/W, + * not forced to user-mode. + */ + ldr r0, =AIPS1_BASE_ADDR + ldr r1, =0x77777777 + str r1, [r0, #0x0] + str r1, [r0, #0x4] + ldr r0, =AIPS2_BASE_ADDR + str r1, [r0, #0x0] + str r1, [r0, #0x4] +.endm /* init_aips */ + +.macro setup_pll pll, freq + ldr r0, =\pll + ldr r1, =0x00001232 + str r1, [r0, #PLL_DP_CTL] + mov r1, #0x2 + str r1, [r0, #PLL_DP_CONFIG] + + ldr r1, W_DP_OP_\freq + str r1, [r0, #PLL_DP_OP] + str r1, [r0, #PLL_DP_HFS_OP] + + ldr r1, W_DP_MFD_\freq + str r1, [r0, #PLL_DP_MFD] + str r1, [r0, #PLL_DP_HFS_MFD] + + ldr r1, W_DP_MFN_\freq + str r1, [r0, #PLL_DP_MFN] + str r1, [r0, #PLL_DP_HFS_MFN] + + ldr r1, =0x00001232 + str r1, [r0, #PLL_DP_CTL] +1: ldr r1, [r0, #PLL_DP_CTL] + ands r1, r1, #0x1 + beq 1b +.endm + +.macro init_clock + ldr r0, CCM_BASE_ADDR_W + + /* Switch ARM to step clock */ + mov r1, #0x4 + str r1, [r0, #CLKCTL_CCSR] + + setup_pll PLL1_BASE_ADDR, 800 + + setup_pll PLL3_BASE_ADDR, 400 + + /* Switch peripheral to PLL3 */ + ldr r0, CCM_BASE_ADDR_W + ldr r1, CCM_VAL_0x00015154 + str r1, [r0, #CLKCTL_CBCMR] + ldr r1, CCM_VAL_0x02888945 + orr r1, r1, #(1 << 16) + str r1, [r0, #CLKCTL_CBCDR] + /* make sure change is effective */ +1: ldr r1, [r0, #CLKCTL_CDHIPR] + cmp r1, #0x0 + bne 1b + + setup_pll PLL2_BASE_ADDR, CONFIG_SYS_PLL2_FREQ + + /* Switch peripheral to PLL2 */ + ldr r0, CCM_BASE_ADDR_W + ldr r1, CCM_VAL_0x00808145 + orr r1, r1, #(CONFIG_SYS_AHB_PODF << 10) + orr r1, r1, #(CONFIG_SYS_AXIA_PODF << 16) + orr r1, r1, #(CONFIG_SYS_AXIB_PODF << 19) + str r1, [r0, #CLKCTL_CBCDR] + + ldr r1, CCM_VAL_0x00016154 + str r1, [r0, #CLKCTL_CBCMR] + + /* make sure change is effective */ +1: ldr r1, [r0, #CLKCTL_CDHIPR] + cmp r1, #0x0 + bne 1b + + setup_pll PLL3_BASE_ADDR, 216 + + /* Set the platform clock dividers */ + ldr r0, PLATFORM_BASE_ADDR_W + ldr r1, PLATFORM_CLOCK_DIV_W + str r1, [r0, #PLATFORM_ICGC] + + ldr r0, CCM_BASE_ADDR_W + mov r1, #1 + str r1, [r0, #CLKCTL_CACRR] + + /* Switch ARM back to PLL 1. */ + mov r1, #0x0 + str r1, [r0, #CLKCTL_CCSR] + + ldr r1, [r0, #CLKCTL_CSCDR1] + orr r1, r1, #0x3f + eor r1, r1, #0x3f + orr r1, r1, #0x21 + str r1, [r0, #CLKCTL_CSCDR1] + + /* Restore the default values in the Gate registers */ + ldr r1, =0xFFFFFFFF + str r1, [r0, #CLKCTL_CCGR0] + str r1, [r0, #CLKCTL_CCGR1] + str r1, [r0, #CLKCTL_CCGR2] + str r1, [r0, #CLKCTL_CCGR3] + str r1, [r0, #CLKCTL_CCGR4] + str r1, [r0, #CLKCTL_CCGR5] + str r1, [r0, #CLKCTL_CCGR6] + str r1, [r0, #CLKCTL_CCGR7] + + mov r1, #0x00000 + str r1, [r0, #CLKCTL_CCDR] + + /* for cko - for ARM div by 8 */ + mov r1, #0x000A0000 + add r1, r1, #0x00000F0 + str r1, [r0, #CLKCTL_CCOSR] +.endm + +.section ".text.init", "x" + +.globl lowlevel_init +lowlevel_init: + +#ifdef ENABLE_IMPRECISE_ABORT + mrs r1, spsr /* save old spsr */ + mrs r0, cpsr /* read out the cpsr */ + bic r0, r0, #0x100 /* clear the A bit */ + msr spsr, r0 /* update spsr */ + add lr, pc, #0x8 /* update lr */ + movs pc, lr /* update cpsr */ + nop + nop + nop + nop + msr spsr, r1 /* restore old spsr */ +#endif + + /* ARM errata ID #468414 */ + mrc 15, 0, r1, c1, c0, 1 + orr r1, r1, #(1 << 5) /* enable L1NEON bit */ + mcr 15, 0, r1, c1, c0, 1 + + init_l2cc + + init_aips + + init_clock + + mov pc, lr + +/* Board level setting value */ +CCM_BASE_ADDR_W: .word CCM_BASE_ADDR +CCM_VAL_0x00016154: .word 0x00016154 +CCM_VAL_0x00808145: .word 0x00808145 +CCM_VAL_0x00015154: .word 0x00015154 +CCM_VAL_0x02888945: .word 0x02888945 +W_DP_OP_800: .word DP_OP_800 +W_DP_MFD_800: .word DP_MFD_800 +W_DP_MFN_800: .word DP_MFN_800 +W_DP_OP_600: .word DP_OP_600 +W_DP_MFD_600: .word DP_MFD_600 +W_DP_MFN_600: .word DP_MFN_600 +W_DP_OP_400: .word DP_OP_400 +W_DP_MFD_400: .word DP_MFD_400 +W_DP_MFN_400: .word DP_MFN_400 +W_DP_OP_216: .word DP_OP_216 +W_DP_MFD_216: .word DP_MFD_216 +W_DP_MFN_216: .word DP_MFN_216 +PLATFORM_BASE_ADDR_W: .word ARM_BASE_ADDR +PLATFORM_CLOCK_DIV_W: .word 0x00000124 diff --git a/board/freescale/mx53_evk/mx53_evk.c b/board/freescale/mx53_evk/mx53_evk.c new file mode 100644 index 0000000000..2f5c4b1857 --- /dev/null +++ b/board/freescale/mx53_evk/mx53_evk.c @@ -0,0 +1,850 @@ +/* + * Copyright (C) 2007, Guennadi Liakhovetski + * + * (C) Copyright 2009-2010 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include + +#if CONFIG_I2C_MXC +#include +#endif + +#ifdef CONFIG_CMD_MMC +#include +#include +#endif + +#ifdef CONFIG_ARCH_MMU +#include +#include +#endif + +#ifdef CONFIG_GET_FEC_MAC_ADDR_FROM_IIM +#include +#endif + +#ifdef CONFIG_CMD_CLOCK +#include +#endif + +DECLARE_GLOBAL_DATA_PTR; + +static u32 system_rev; +static enum boot_device boot_dev; + +static inline void setup_boot_device(void) +{ + uint soc_sbmr = readl(SRC_BASE_ADDR + 0x4); + uint bt_mem_ctl = (soc_sbmr & 0x000000FF) >> 4 ; + uint bt_mem_type = (soc_sbmr & 0x00000008) >> 3; + + switch (bt_mem_ctl) { + case 0x0: + if (bt_mem_type) + boot_dev = ONE_NAND_BOOT; + else + boot_dev = WEIM_NOR_BOOT; + break; + case 0x2: + if (bt_mem_type) + boot_dev = SATA_BOOT; + else + boot_dev = PATA_BOOT; + break; + case 0x3: + if (bt_mem_type) + boot_dev = SPI_NOR_BOOT; + else + boot_dev = I2C_BOOT; + break; + case 0x4: + case 0x5: + boot_dev = SD_BOOT; + break; + case 0x6: + case 0x7: + boot_dev = MMC_BOOT; + break; + case 0x8 ... 0xf: + boot_dev = NAND_BOOT; + break; + default: + boot_dev = UNKNOWN_BOOT; + break; + } +} + +enum boot_device get_boot_device(void) +{ + return boot_dev; +} + +u32 get_board_rev(void) +{ + return system_rev; +} + +static inline void setup_soc_rev(void) +{ + system_rev = 0x53000 | CHIP_REV_1_0; +} + +static inline void setup_board_rev(int rev) +{ + system_rev |= (rev & 0xF) << 8; +} + +inline int is_soc_rev(int rev) +{ + return (system_rev & 0xFF) - rev; +} + +#ifdef CONFIG_ARCH_MMU +void board_mmu_init(void) +{ + unsigned long ttb_base = PHYS_SDRAM_1 + 0x4000; + unsigned long i; + + /* + * Set the TTB register + */ + asm volatile ("mcr p15,0,%0,c2,c0,0" : : "r"(ttb_base) /*:*/); + + /* + * Set the Domain Access Control Register + */ + i = ARM_ACCESS_DACR_DEFAULT; + asm volatile ("mcr p15,0,%0,c3,c0,0" : : "r"(i) /*:*/); + + /* + * First clear all TT entries - ie Set them to Faulting + */ + memset((void *)ttb_base, 0, ARM_FIRST_LEVEL_PAGE_TABLE_SIZE); + /* Actual Virtual Size Attributes Function */ + /* Base Base MB cached? buffered? access permissions */ + /* xxx00000 xxx00000 */ + X_ARM_MMU_SECTION(0x000, 0x000, 0x10, + ARM_UNCACHEABLE, ARM_UNBUFFERABLE, + ARM_ACCESS_PERM_RW_RW); /* ROM, 16M */ + X_ARM_MMU_SECTION(0x070, 0x070, 0x010, + ARM_UNCACHEABLE, ARM_UNBUFFERABLE, + ARM_ACCESS_PERM_RW_RW); /* IRAM */ + X_ARM_MMU_SECTION(0x100, 0x100, 0x040, + ARM_UNCACHEABLE, ARM_UNBUFFERABLE, + ARM_ACCESS_PERM_RW_RW); /* SATA */ + X_ARM_MMU_SECTION(0x180, 0x180, 0x100, + ARM_UNCACHEABLE, ARM_UNBUFFERABLE, + ARM_ACCESS_PERM_RW_RW); /* IPUv3M */ + X_ARM_MMU_SECTION(0x200, 0x200, 0x200, + ARM_UNCACHEABLE, ARM_UNBUFFERABLE, + ARM_ACCESS_PERM_RW_RW); /* GPU */ + X_ARM_MMU_SECTION(0x400, 0x400, 0x300, + ARM_UNCACHEABLE, ARM_UNBUFFERABLE, + ARM_ACCESS_PERM_RW_RW); /* periperals */ + X_ARM_MMU_SECTION(0x700, 0x700, 0x400, + ARM_CACHEABLE, ARM_BUFFERABLE, + ARM_ACCESS_PERM_RW_RW); /* CSD0 1G */ + X_ARM_MMU_SECTION(0x700, 0xB00, 0x400, + ARM_UNCACHEABLE, ARM_UNBUFFERABLE, + ARM_ACCESS_PERM_RW_RW); /* CSD0 1G */ + X_ARM_MMU_SECTION(0xF00, 0xF00, 0x100, + ARM_UNCACHEABLE, ARM_UNBUFFERABLE, + ARM_ACCESS_PERM_RW_RW); /* CS1 EIM control*/ + X_ARM_MMU_SECTION(0xF7F, 0xF7F, 0x040, + ARM_UNCACHEABLE, ARM_UNBUFFERABLE, + ARM_ACCESS_PERM_RW_RW); /* NAND Flash buffer */ + X_ARM_MMU_SECTION(0xF80, 0xF80, 0x001, + ARM_UNCACHEABLE, ARM_UNBUFFERABLE, + ARM_ACCESS_PERM_RW_RW); /* iRam */ + + /* Workaround for arm errata #709718 */ + /* Setup PRRR so device is always mapped to non-shared */ + asm volatile ("mrc p15, 0, %0, c10, c2, 0" : "=r"(i) : /*:*/); + i &= (~(3 << 0x10)); + asm volatile ("mcr p15, 0, %0, c10, c2, 0" : : "r"(i) /*:*/); + + /* Enable MMU */ + MMU_ON(); +} +#endif + +int dram_init(void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + return 0; +} + +static void setup_uart(void) +{ + + /* UART1 RXD */ + mxc_request_iomux(MX53_PIN_CSI0_D11, IOMUX_CONFIG_ALT2); + mxc_iomux_set_pad(MX53_PIN_CSI0_D11, 0x1E4); + mxc_iomux_set_input(MUX_IN_UART1_IPP_UART_RXD_MUX_SELECT_INPUT, 0x1); + + /* UART1 TXD */ + mxc_request_iomux(MX53_PIN_CSI0_D10, IOMUX_CONFIG_ALT2); + mxc_iomux_set_pad(MX53_PIN_CSI0_D10, 0x1E4); +} + +#ifdef CONFIG_I2C_MXC +static void setup_i2c(unsigned int module_base) +{ + switch (module_base) { + case I2C1_BASE_ADDR: + /* i2c1 SDA */ + mxc_request_iomux(MX53_PIN_CSI0_D8, + IOMUX_CONFIG_ALT5 | IOMUX_CONFIG_SION); + mxc_iomux_set_input(MUX_IN_I2C1_IPP_SDA_IN_SELECT_INPUT, + INPUT_CTL_PATH0); + mxc_iomux_set_pad(MX53_PIN_CSI0_D8, PAD_CTL_SRE_FAST | + PAD_CTL_ODE_OPENDRAIN_ENABLE | + PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU | + PAD_CTL_HYS_ENABLE); + /* i2c1 SCL */ + mxc_request_iomux(MX53_PIN_CSI0_D9, + IOMUX_CONFIG_ALT5 | IOMUX_CONFIG_SION); + mxc_iomux_set_input(MUX_IN_I2C1_IPP_SCL_IN_SELECT_INPUT, + INPUT_CTL_PATH0); + mxc_iomux_set_pad(MX53_PIN_CSI0_D9, PAD_CTL_SRE_FAST | + PAD_CTL_ODE_OPENDRAIN_ENABLE | + PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU | + PAD_CTL_HYS_ENABLE); + break; + case I2C2_BASE_ADDR: + /* i2c2 SDA */ + mxc_request_iomux(MX53_PIN_KEY_ROW3, + IOMUX_CONFIG_ALT4 | IOMUX_CONFIG_SION); + mxc_iomux_set_input(MUX_IN_I2C2_IPP_SDA_IN_SELECT_INPUT, + INPUT_CTL_PATH0); + mxc_iomux_set_pad(MX53_PIN_KEY_ROW3, + PAD_CTL_SRE_FAST | + PAD_CTL_ODE_OPENDRAIN_ENABLE | + PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU | + PAD_CTL_HYS_ENABLE); + + /* i2c2 SCL */ + mxc_request_iomux(MX53_PIN_KEY_COL3, + IOMUX_CONFIG_ALT4 | IOMUX_CONFIG_SION); + mxc_iomux_set_input(MUX_IN_I2C2_IPP_SCL_IN_SELECT_INPUT, + INPUT_CTL_PATH0); + mxc_iomux_set_pad(MX53_PIN_KEY_COL3, + PAD_CTL_SRE_FAST | + PAD_CTL_ODE_OPENDRAIN_ENABLE | + PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU | + PAD_CTL_HYS_ENABLE); + break; + default: + printf("Invalid I2C base: 0x%x\n", module_base); + break; + } +} + +void setup_core_voltages(void) +{ + unsigned char buf[4] = { 0 }; + + i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); + + /* Set core voltage VDDGP to 1.05V for 800MHZ */ + buf[0] = 0x45; + buf[1] = 0x4a; + buf[2] = 0x52; + if (i2c_write(0x8, 24, 1, buf, 3)) + return; + + /* Set DDR voltage VDDA to 1.25V */ + buf[0] = 0; + buf[1] = 0x63; + buf[2] = 0x1a; + if (i2c_write(0x8, 26, 1, buf, 3)) + return; + + /* Raise the core frequency to 800MHz */ + writel(0x0, CCM_BASE_ADDR + CLKCTL_CACRR); +} + +#ifndef CONFIG_MX53_ARM2 +static int __read_adc_channel(unsigned int chan) +{ + unsigned char buf[4] = { 0 }; + + buf[0] = (0xb0 | ((chan & 0x1) << 3) | ((chan >> 1) & 0x7)); + + /* LTC2495 need 410ms delay */ + udelay(410000); + + if (i2c_write(0x14, chan, 0, &buf[0], 1)) { + printf("%s:i2c_write:error\n", __func__); + return -1; + } + + /* LTC2495 need 410ms delay*/ + udelay(410000); + + if (i2c_read(0x14, chan, 0, &buf[0], 3)) { + printf("%s:i2c_read:error\n", __func__); + return -1; + } + + return buf[0] << 16 | buf[1] << 8 | buf[2]; +} + +static int __lookup_board_id(int adc_val) +{ + int id; + + if (adc_val < 0x3FFFC0) + id = 0; + else if (adc_val < 0x461863) + id = 1; + else if (adc_val < 0x4C30C4) + id = 2; + else if (adc_val < 0x524926) + id = 3; + else if (adc_val < 0x586187) + id = 4; + else if (adc_val < 0x5E79E9) + id = 5; + else if (adc_val < 0x64924A) + id = 6; + else if (adc_val < 0x6AAAAC) + id = 7; + else if (adc_val < 0x70C30D) + id = 8; + else if (adc_val < 0x76DB6F) + id = 9; + else if (adc_val < 0x7CF3D0) + id = 10; + else if (adc_val < 0x830C32) + id = 11; + else if (adc_val < 0x892493) + id = 12; + else if (adc_val < 0x8F3CF5) + id = 13; + else if (adc_val < 0x955556) + id = 14; + else if (adc_val < 0x9B6DB8) + id = 15; + else if (adc_val < 0xA18619) + id = 16; + else if (adc_val < 0xA79E7B) + id = 17; + else if (adc_val < 0xADB6DC) + id = 18; + else if (adc_val < 0xB3CF3E) + id = 19; + else if (adc_val < 0xB9E79F) + id = 20; + else if (adc_val <= 0xC00000) + id = 21; + else + return -1; + + return id; +} + +static int __print_board_info(int id0, int id1) +{ + int ret = 0; + + switch (id0) { + case 21: + switch (id1) { + case 15: + printf("MX53-EVK with DDR2 1GByte RevB\n"); + + break; + case 18: + printf("MX53-EVK with DDR2 2GByte RevA1\n"); + + break; + case 19: + printf("MX53-EVK with DDR2 2GByte RevA2\n"); + break; + default: + printf("Unkown board id1:%d\n", id1); + ret = -1; + + break; + } + + break; + case 11: + switch (id1) { + case 1: + printf("MX53 1.5V DDR3 x8 CPU Card, Rev. A\n"); + + break; + case 11: + printf("MX53 1.8V DDR2 x8 CPU Card, Rev. A\n"); + + break; + default: + printf("Unkown board id1:%d\n", id1); + ret = -1; + + break; + } + + break; + default: + printf("Unkown board id0:%d\n", id0); + + break; + } + + return ret; +} + +static int _identify_board_fix_up(int id0, int id1) +{ + int ret = 0; + +#ifdef CONFIG_CMD_CLOCK + /* For EVK RevB, set DDR to 400MHz */ + if (id0 == 21 && id1 == 15) { + ret = clk_config(CONFIG_REF_CLK_FREQ, 400, PERIPH_CLK); + if (ret < 0) + return ret; + + ret = clk_config(CONFIG_REF_CLK_FREQ, 400, DDR_CLK); + if (ret < 0) + return ret; + + /* set up rev #2 for EVK RevB board */ + setup_board_rev(2); + } +#endif + return ret; +} + +int identify_board_id(void) +{ + int ret = 0; + int bd_id0, bd_id1; + +#define CPU_CHANNEL_ID0 0xc +#define CPU_CHANNEL_ID1 0xd + + ret = bd_id0 = __read_adc_channel(CPU_CHANNEL_ID0); + if (ret < 0) + return ret; + + ret = bd_id1 = __read_adc_channel(CPU_CHANNEL_ID1); + if (ret < 0) + return ret; + + ret = bd_id0 = __lookup_board_id(bd_id0); + if (ret < 0) + return ret; + + ret = bd_id1 = __lookup_board_id(bd_id1); + if (ret < 0) + return ret; + + ret = __print_board_info(bd_id0, bd_id1); + if (ret < 0) + return ret; + + ret = _identify_board_fix_up(bd_id0, bd_id1); + + return ret; + +} +#endif +#endif + +#ifdef CONFIG_IMX_ECSPI +s32 spi_get_cfg(struct imx_spi_dev_t *dev) +{ + switch (dev->slave.cs) { + case 0: + /* pmic */ + dev->base = CSPI1_BASE_ADDR; + dev->freq = 2500000; + dev->ss_pol = IMX_SPI_ACTIVE_HIGH; + dev->ss = 0; + dev->fifo_sz = 64 * 4; + dev->us_delay = 0; + break; + case 1: + /* spi_nor */ + dev->base = CSPI1_BASE_ADDR; + dev->freq = 2500000; + dev->ss_pol = IMX_SPI_ACTIVE_LOW; + dev->ss = 1; + dev->fifo_sz = 64 * 4; + dev->us_delay = 0; + break; + default: + printf("Invalid Bus ID! \n"); + break; + } + + return 0; +} + +void spi_io_init(struct imx_spi_dev_t *dev) +{ + switch (dev->base) { + case CSPI1_BASE_ADDR: + /* Select mux mode: ALT4 mux port: MOSI of instance: ecspi1 */ + mxc_request_iomux(MX53_PIN_EIM_D18, IOMUX_CONFIG_ALT4); + mxc_iomux_set_pad(MX53_PIN_EIM_D18, 0x104); + mxc_iomux_set_input( + MUX_IN_ECSPI1_IPP_IND_MOSI_SELECT_INPUT, 0x3); + + /* Select mux mode: ALT4 mux port: MISO of instance: ecspi1. */ + mxc_request_iomux(MX53_PIN_EIM_D17, IOMUX_CONFIG_ALT4); + mxc_iomux_set_pad(MX53_PIN_EIM_D17, 0x104); + mxc_iomux_set_input( + MUX_IN_ECSPI1_IPP_IND_MISO_SELECT_INPUT, 0x3); + + if (dev->ss == 0) { + /* de-select SS1 of instance: ecspi1. */ + mxc_request_iomux(MX53_PIN_EIM_D19, IOMUX_CONFIG_ALT1); + mxc_iomux_set_pad(MX53_PIN_EIM_D19, 0x1E4); + + /* mux mode: ALT4 mux port: SS0 of instance: ecspi1. */ + mxc_request_iomux(MX53_PIN_EIM_EB2, IOMUX_CONFIG_ALT4); + mxc_iomux_set_pad(MX53_PIN_EIM_EB2, 0x104); + mxc_iomux_set_input( + MUX_IN_ECSPI1_IPP_IND_SS_B_1_SELECT_INPUT, 0x3); + } else if (dev->ss == 1) { + /* de-select SS0 of instance: ecspi1. */ + mxc_request_iomux(MX53_PIN_EIM_EB2, IOMUX_CONFIG_ALT1); + mxc_iomux_set_pad(MX53_PIN_EIM_EB2, 0x1E4); + + /* mux mode: ALT0 mux port: SS1 of instance: ecspi1. */ + mxc_request_iomux(MX53_PIN_EIM_D19, IOMUX_CONFIG_ALT4); + mxc_iomux_set_pad(MX53_PIN_EIM_D19, 0x104); + mxc_iomux_set_input( + MUX_IN_ECSPI1_IPP_IND_SS_B_2_SELECT_INPUT, 0x2); + } + + /* Select mux mode: ALT0 mux port: SCLK of instance: ecspi1. */ + mxc_request_iomux(MX53_PIN_EIM_D16, IOMUX_CONFIG_ALT4); + mxc_iomux_set_pad(MX53_PIN_EIM_D16, 0x104); + mxc_iomux_set_input( + MUX_IN_CSPI_IPP_CSPI_CLK_IN_SELECT_INPUT, 0x3); + + break; + case CSPI2_BASE_ADDR: + default: + + break; + } +} +#endif + +#ifdef CONFIG_MXC_FEC + +#ifdef CONFIG_GET_FEC_MAC_ADDR_FROM_IIM + +int fec_get_mac_addr(unsigned char *mac) +{ + u32 *iim1_mac_base = + (u32 *)(IIM_BASE_ADDR + IIM_BANK_AREA_1_OFFSET + + CONFIG_IIM_MAC_ADDR_OFFSET); + int i; + + for (i = 0; i < 6; ++i, ++iim1_mac_base) + mac[i] = (u8)readl(iim1_mac_base); + + return 0; +} +#endif + +static void setup_fec(void) +{ + volatile unsigned int reg; + + /*FEC_MDIO*/ + mxc_request_iomux(MX53_PIN_FEC_MDIO, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX53_PIN_FEC_MDIO, 0x1FC); + mxc_iomux_set_input(MUX_IN_FEC_FEC_MDI_SELECT_INPUT, 0x1); + + /*FEC_MDC*/ + mxc_request_iomux(MX53_PIN_FEC_MDC, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX53_PIN_FEC_MDC, 0x004); + + /* FEC RXD1 */ + mxc_request_iomux(MX53_PIN_FEC_RXD1, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX53_PIN_FEC_RXD1, 0x180); + + /* FEC RXD0 */ + mxc_request_iomux(MX53_PIN_FEC_RXD0, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX53_PIN_FEC_RXD0, 0x180); + + /* FEC TXD1 */ + mxc_request_iomux(MX53_PIN_FEC_TXD1, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX53_PIN_FEC_TXD1, 0x004); + + /* FEC TXD0 */ + mxc_request_iomux(MX53_PIN_FEC_TXD0, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX53_PIN_FEC_TXD0, 0x004); + + /* FEC TX_EN */ + mxc_request_iomux(MX53_PIN_FEC_TX_EN, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX53_PIN_FEC_TX_EN, 0x004); + + /* FEC TX_CLK */ + mxc_request_iomux(MX53_PIN_FEC_REF_CLK, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX53_PIN_FEC_REF_CLK, 0x180); + + /* FEC RX_ER */ + mxc_request_iomux(MX53_PIN_FEC_RX_ER, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX53_PIN_FEC_RX_ER, 0x180); + + /* FEC CRS */ + mxc_request_iomux(MX53_PIN_FEC_CRS_DV, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX53_PIN_FEC_CRS_DV, 0x180); + + /* phy reset: gpio7-6 */ + mxc_request_iomux(MX53_PIN_ATA_DA_0, IOMUX_CONFIG_ALT1); + + reg = readl(GPIO7_BASE_ADDR + 0x0); + reg &= ~0x40; + writel(reg, GPIO7_BASE_ADDR + 0x0); + + reg = readl(GPIO7_BASE_ADDR + 0x4); + reg |= 0x40; + writel(reg, GPIO7_BASE_ADDR + 0x4); + + udelay(500); + + reg = readl(GPIO7_BASE_ADDR + 0x0); + reg |= 0x40; + writel(reg, GPIO7_BASE_ADDR + 0x0); + +} +#endif + +#ifdef CONFIG_CMD_MMC + +struct fsl_esdhc_cfg esdhc_cfg[2] = { + {MMC_SDHC1_BASE_ADDR, 1, 1}, + {MMC_SDHC3_BASE_ADDR, 1, 1}, +}; + +#ifdef CONFIG_DYNAMIC_MMC_DEVNO +int get_mmc_env_devno() +{ + uint soc_sbmr = readl(SRC_BASE_ADDR + 0x4); + return (soc_sbmr & 0x00300000) ? 1 : 0; +} +#endif + + +int esdhc_gpio_init(bd_t *bis) +{ + s32 status = 0; + u32 index = 0; + + for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; + ++index) { + switch (index) { + case 0: + mxc_request_iomux(MX53_PIN_SD1_CMD, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX53_PIN_SD1_CLK, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX53_PIN_SD1_DATA0, + IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX53_PIN_SD1_DATA1, + IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX53_PIN_SD1_DATA2, + IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX53_PIN_SD1_DATA3, + IOMUX_CONFIG_ALT0); + + mxc_iomux_set_pad(MX53_PIN_SD1_CMD, 0x1E4); + mxc_iomux_set_pad(MX53_PIN_SD1_CLK, 0xD4); + mxc_iomux_set_pad(MX53_PIN_SD1_DATA0, 0x1D4); + mxc_iomux_set_pad(MX53_PIN_SD1_DATA1, 0x1D4); + mxc_iomux_set_pad(MX53_PIN_SD1_DATA2, 0x1D4); + mxc_iomux_set_pad(MX53_PIN_SD1_DATA3, 0x1D4); + break; + case 1: + mxc_request_iomux(MX53_PIN_ATA_RESET_B, + IOMUX_CONFIG_ALT2); + mxc_request_iomux(MX53_PIN_ATA_IORDY, + IOMUX_CONFIG_ALT2); + mxc_request_iomux(MX53_PIN_ATA_DATA8, + IOMUX_CONFIG_ALT4); + mxc_request_iomux(MX53_PIN_ATA_DATA9, + IOMUX_CONFIG_ALT4); + mxc_request_iomux(MX53_PIN_ATA_DATA10, + IOMUX_CONFIG_ALT4); + mxc_request_iomux(MX53_PIN_ATA_DATA11, + IOMUX_CONFIG_ALT4); + mxc_request_iomux(MX53_PIN_ATA_DATA0, + IOMUX_CONFIG_ALT4); + mxc_request_iomux(MX53_PIN_ATA_DATA1, + IOMUX_CONFIG_ALT4); + mxc_request_iomux(MX53_PIN_ATA_DATA2, + IOMUX_CONFIG_ALT4); + mxc_request_iomux(MX53_PIN_ATA_DATA3, + IOMUX_CONFIG_ALT4); + + mxc_iomux_set_pad(MX53_PIN_ATA_RESET_B, 0x1E4); + mxc_iomux_set_pad(MX53_PIN_ATA_IORDY, 0xD4); + mxc_iomux_set_pad(MX53_PIN_ATA_DATA8, 0x1D4); + mxc_iomux_set_pad(MX53_PIN_ATA_DATA9, 0x1D4); + mxc_iomux_set_pad(MX53_PIN_ATA_DATA10, 0x1D4); + mxc_iomux_set_pad(MX53_PIN_ATA_DATA11, 0x1D4); + mxc_iomux_set_pad(MX53_PIN_ATA_DATA0, 0x1D4); + mxc_iomux_set_pad(MX53_PIN_ATA_DATA1, 0x1D4); + mxc_iomux_set_pad(MX53_PIN_ATA_DATA2, 0x1D4); + mxc_iomux_set_pad(MX53_PIN_ATA_DATA3, 0x1D4); + + break; + default: + printf("Warning: you configured more ESDHC controller" + "(%d) as supported by the board(2)\n", + CONFIG_SYS_FSL_ESDHC_NUM); + return status; + break; + } + status |= fsl_esdhc_initialize(bis, &esdhc_cfg[index]); + } + + return status; +} + +int board_mmc_init(bd_t *bis) +{ + if (!esdhc_gpio_init(bis)) + return 0; + else + return -1; +} + +#endif + +int board_init(void) +{ +#ifdef CONFIG_MFG +/* MFG firmware need reset usb to avoid host crash firstly */ +#define USBCMD 0x140 + int val = readl(OTG_BASE_ADDR + USBCMD); + val &= ~0x1; /*RS bit*/ + writel(val, OTG_BASE_ADDR + USBCMD); +#endif + setup_boot_device(); + setup_soc_rev(); +#if defined(CONFIG_MX53_ARM2) || defined(CONFIG_MX53_ARM2_DDR3) + setup_board_rev(1); +#endif + gd->bd->bi_arch_number = MACH_TYPE_MX53_EVK; /* board id for linux */ + /* address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; + + setup_uart(); + setup_fec(); + +#ifdef CONFIG_I2C_MXC + setup_i2c(CONFIG_SYS_I2C_PORT); + setup_core_voltages(); +#endif + + return 0; +} + +int board_late_init(void) +{ + return 0; +} + +int checkboard(void) +{ + printf("Board: "); + +#ifdef CONFIG_MX53_ARM2 + printf("Board: MX53 ARMADILLO2 "); + printf("1.0 ["); +#else +#ifdef CONFIG_I2C_MXC + identify_board_id(); + + printf("Boot Reason: ["); +#endif +#endif + + switch (__REG(SRC_BASE_ADDR + 0x8)) { + case 0x0001: + printf("POR"); + break; + case 0x0009: + printf("RST"); + break; + case 0x0010: + case 0x0011: + printf("WDOG"); + break; + default: + printf("unknown"); + } + printf("]\n"); + + printf("Boot Device: "); + switch (get_boot_device()) { + case WEIM_NOR_BOOT: + printf("NOR\n"); + break; + case ONE_NAND_BOOT: + printf("ONE NAND\n"); + break; + case PATA_BOOT: + printf("PATA\n"); + break; + case SATA_BOOT: + printf("SATA\n"); + break; + case I2C_BOOT: + printf("I2C\n"); + break; + case SPI_NOR_BOOT: + printf("SPI NOR\n"); + break; + case SD_BOOT: + printf("SD\n"); + break; + case MMC_BOOT: + printf("MMC\n"); + break; + case NAND_BOOT: + printf("NAND\n"); + break; + case UNKNOWN_BOOT: + default: + printf("UNKNOWN\n"); + break; + } + return 0; +} diff --git a/board/freescale/mx53_evk/u-boot.lds b/board/freescale/mx53_evk/u-boot.lds new file mode 100644 index 0000000000..fe5f4ebbc4 --- /dev/null +++ b/board/freescale/mx53_evk/u-boot.lds @@ -0,0 +1,73 @@ +/* + * January 2004 - Changed to support H4 device + * Copyright (c) 2004 Texas Instruments + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * (C) Copyright 2010 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + board/freescale/mx53_evk/flash_header.o (.text.flasheader) + cpu/arm_cortexa8/start.o + board/freescale/mx53_evk/libmx53_evk.a (.text) + lib_arm/libarm.a (.text) + net/libnet.a (.text) + drivers/mtd/libmtd.a (.text) + drivers/mmc/libmmc.a (.text) + + . = DEFINED(env_offset) ? env_offset : .; + common/env_embedded.o(.text) + + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} diff --git a/board/karo/tx28/Makefile b/board/karo/tx28/Makefile new file mode 100644 index 0000000000..e20fde3a31 --- /dev/null +++ b/board/karo/tx28/Makefile @@ -0,0 +1,55 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := tx28.o +ifeq ($(CONFIG_CMD_ROMUPDATE),y) + COBJS += flash.o +endif +SOBJS := lowlevel_init.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### + diff --git a/board/karo/tx28/config.mk b/board/karo/tx28/config.mk new file mode 100644 index 0000000000..6d50b56cfd --- /dev/null +++ b/board/karo/tx28/config.mk @@ -0,0 +1,3 @@ +LDSCRIPT := $(SRCTREE)/board/$(VENDOR)/$(BOARD)/u-boot.lds + +TEXT_BASE = 0x47f80000 diff --git a/board/karo/tx28/flash.c b/board/karo/tx28/flash.c new file mode 100644 index 0000000000..b1c49499e6 --- /dev/null +++ b/board/karo/tx28/flash.c @@ -0,0 +1,583 @@ +#include +#include +#include + +#include + +#include +#include +#include +#include +#include + +#define FCB_START_BLOCK 0 +#define NUM_FCB_BLOCKS 1 +#define MAX_FCB_BLOCKS 32768 + +struct mx28_nand_timing { + u8 data_setup; + u8 data_hold; + u8 address_setup; + u8 dsample_time; + u8 nand_timing_state; + u8 tREA; + u8 tRLOH; + u8 tRHOH; +}; + +struct mx28_fcb { + u32 checksum; + u32 fingerprint; + u32 version; + struct mx28_nand_timing timing; + u32 page_data_size; + u32 total_page_size; + u32 sectors_per_block; + u32 number_of_nands; /* not used by ROM code */ + u32 total_internal_die; /* not used by ROM code */ + u32 cell_type; /* not used by ROM code */ + u32 ecc_blockn_type; + u32 ecc_block0_size; + u32 ecc_blockn_size; + u32 ecc_block0_type; + u32 metadata_size; + u32 ecc_blocks_per_page; + u32 rsrvd[6]; /* not used by ROM code */ + u32 bch_mode; + u32 boot_patch; + u32 patch_sectors; + u32 fw1_start_page; + u32 fw2_start_page; + u32 fw1_sectors; + u32 fw2_sectors; + u32 dbbt_search_area; + u32 bb_mark_byte; + u32 bb_mark_startbit; + u32 bb_mark_phys_offset; +}; + +struct mx28_dbbt_header { + u32 checksum; + u32 fingerprint; + u32 version; + u32 number_bb; + u32 number_pages; + u8 spare[492]; +}; + +struct mx28_dbbt { + u32 nand_number; + u32 number_bb; + u32 bb_num[2040 / 4]; +}; + +#define BF_VAL(v, bf) (((v) & BM_##bf) >> BP_##bf) + +static nand_info_t *mtd = &nand_info[0]; + +extern void *_start; + +#define BIT(v,n) (((v) >> (n)) & 0x1) + +static u8 calculate_parity_13_8(u8 d) +{ + u8 p = 0; + + p |= (BIT(d, 6) ^ BIT(d, 5) ^ BIT(d, 3) ^ BIT(d, 2)) << 0; + p |= (BIT(d, 7) ^ BIT(d, 5) ^ BIT(d, 4) ^ BIT(d, 2) ^ BIT(d, 1)) << 1; + p |= (BIT(d, 7) ^ BIT(d, 6) ^ BIT(d, 5) ^ BIT(d, 1) ^ BIT(d, 0)) << 2; + p |= (BIT(d, 7) ^ BIT(d, 4) ^ BIT(d, 3) ^ BIT(d, 0)) << 3; + p |= (BIT(d, 6) ^ BIT(d, 4) ^ BIT(d, 3) ^ BIT(d, 2) ^ BIT(d, 1) ^ BIT(d, 0)) << 4; + return p; +} + +static void encode_hamming_13_8(void *_src, void *_ecc, size_t size) +{ + int i; + u8 *src = _src; + u8 *ecc = _ecc; + + for (i = 0; i < size; i++) + ecc[i] = calculate_parity_13_8(src[i]); +} + +static u32 calc_chksum(void *buf, size_t size) +{ + u32 chksum; + u8 *bp = buf; + size_t i; + + for (i = 0; i < size; i++) { + chksum += bp[i]; + } + return ~chksum; +} + +/* + Physical organisation of data in NAND flash: + metadata + payload chunk 0 (may be empty) + ecc for metadata + payload chunk 0 + payload chunk 1 + ecc for payload chunk 1 +... + payload chunk n + ecc for payload chunk n + */ + +static int calc_bb_offset(nand_info_t *mtd, struct mx28_fcb *fcb) +{ + int bb_mark_offset; + int chunk_data_size = fcb->ecc_blockn_size * 8; + int chunk_ecc_size = (fcb->ecc_blockn_type << 1) * 13; + int chunk_total_size = chunk_data_size + chunk_ecc_size; + int bb_mark_chunk, bb_mark_chunk_offs; + + bb_mark_offset = (mtd->writesize - fcb->metadata_size) * 8; + if (fcb->ecc_block0_size == 0) + bb_mark_offset -= (fcb->ecc_block0_type << 1) * 13; + + bb_mark_chunk = bb_mark_offset / chunk_total_size; + bb_mark_chunk_offs = bb_mark_offset - (bb_mark_chunk * chunk_total_size); + if (bb_mark_chunk_offs > chunk_data_size) { + printf("Unsupported ECC layout; BB mark resides in ECC data: %u\n", + bb_mark_chunk_offs); + return -EINVAL; + } + bb_mark_offset -= bb_mark_chunk * chunk_ecc_size; + return bb_mark_offset; +} + +static struct mx28_fcb *create_fcb(void *buf, int fw1_start_block, int fw2_start_block, + size_t fw_size) +{ + volatile void *gpmi_base = __ioremap(GPMI_BASE_ADDR, SZ_4K, 1); + volatile void *bch_base = __ioremap(BCH_BASE_ADDR, SZ_4K, 1); + u32 fl0, fl1; + u32 t0, t1; + int metadata_size; + int bb_mark_bit_offs; + struct mx28_fcb *fcb; + int fcb_offs; + + if (gpmi_base == NULL || bch_base == NULL) { + return ERR_PTR(-ENOMEM); + } + + fl0 = readl(bch_base + HW_BCH_FLASH0LAYOUT0); + fl1 = readl(bch_base + HW_BCH_FLASH0LAYOUT1); + t0 = readl(gpmi_base + HW_GPMI_TIMING0); + t1 = readl(gpmi_base + HW_GPMI_TIMING1); + + metadata_size = BF_VAL(fl0, BCH_FLASH0LAYOUT0_META_SIZE); + + fcb = buf + ALIGN(metadata_size, 4); + fcb_offs = (void *)fcb - buf; + + memset(buf, 0xff, fcb_offs); + memset(fcb, 0x00, sizeof(*fcb)); + memset(fcb + 1, 0xff, mtd->erasesize - fcb_offs - sizeof(*fcb)); + + strncpy((char *)&fcb->fingerprint, "FCB ", 4); + fcb->version = cpu_to_be32(1); + + fcb->timing.data_setup = BF_VAL(t0, GPMI_TIMING0_DATA_SETUP); + fcb->timing.data_hold = BF_VAL(t0, GPMI_TIMING0_DATA_HOLD); + fcb->timing.address_setup = BF_VAL(t0, GPMI_TIMING0_ADDRESS_SETUP); + + fcb->page_data_size = mtd->writesize; + fcb->total_page_size = mtd->writesize + mtd->oobsize; + fcb->sectors_per_block = mtd->erasesize / mtd->writesize; + + fcb->ecc_block0_type = BF_VAL(fl0, BCH_FLASH0LAYOUT0_ECC0); + fcb->ecc_block0_size = BF_VAL(fl0, BCH_FLASH0LAYOUT0_DATA0_SIZE); + fcb->ecc_blockn_type = BF_VAL(fl1, BCH_FLASH0LAYOUT1_ECCN); + fcb->ecc_blockn_size = BF_VAL(fl1, BCH_FLASH0LAYOUT1_DATAN_SIZE); + + fcb->metadata_size = BF_VAL(fl0, BCH_FLASH0LAYOUT0_META_SIZE); + fcb->ecc_blocks_per_page = BF_VAL(fl0, BCH_FLASH0LAYOUT0_NBLOCKS); + fcb->bch_mode = readl(bch_base + HW_BCH_MODE); +/* + fcb->boot_patch = 0; + fcb->patch_sectors = 0; +*/ + fcb->fw1_start_page = fw1_start_block * mtd->erasesize / mtd->writesize; + fcb->fw1_sectors = DIV_ROUND_UP(fw_size, mtd->writesize); + + if (fw2_start_block != 0 && fw2_start_block < mtd->size / mtd->erasesize) { + fcb->fw2_start_page = fw2_start_block * mtd->erasesize / mtd->writesize; + fcb->fw2_sectors = fcb->fw1_sectors; + } + + fcb->dbbt_search_area = 1; + + bb_mark_bit_offs = calc_bb_offset(mtd, fcb); + if (bb_mark_bit_offs < 0) + return ERR_PTR(bb_mark_bit_offs); + fcb->bb_mark_byte = bb_mark_bit_offs / 8; + fcb->bb_mark_startbit = bb_mark_bit_offs % 8; + fcb->bb_mark_phys_offset = mtd->writesize; + + fcb->checksum = calc_chksum(&fcb->fingerprint, 512 - 4); + return fcb; +} + +static int find_fcb(void *ref, int page) +{ + int ret = 0; + struct nand_chip *chip = mtd->priv; + void *buf = malloc(mtd->erasesize); + + if (buf == NULL) { + return -ENOMEM; + } + chip->select_chip(mtd, 0); + chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page); + ret = chip->ecc.read_page_raw(mtd, chip, buf); + if (ret) { + printf("Failed to read FCB from page %u: %d\n", page, ret); + return ret; + } + chip->select_chip(mtd, -1); + if (memcmp(buf, ref, mtd->writesize) == 0) { + printf("%s: Found FCB in page %u (%08x)\n", __func__, + page, page * mtd->writesize); + ret = 1; + } + free(buf); + return ret; +} + +static int write_fcb(void *buf, int block) +{ + int ret; + struct nand_chip *chip = mtd->priv; + int page = block * mtd->erasesize / mtd->writesize; + + ret = find_fcb(buf, page); + if (ret > 0) { + printf("FCB at block %d is up to date\n", block); + return 0; + } + + ret = nand_erase(mtd, block * mtd->erasesize, mtd->erasesize); + if (ret) { + printf("Failed to erase FCB block %u\n", block); + return ret; + } + + printf("Writing FCB to block %d @ %08x\n", block, + block * mtd->erasesize); + chip->select_chip(mtd, 0); + ret = chip->write_page(mtd, chip, buf, page, 0, 1); + if (ret) { + printf("Failed to write FCB to block %u: %d\n", block, ret); + } + chip->select_chip(mtd, -1); + return ret; +} + +#define chk_overlap(a,b) \ + ((a##_start_block <= b##_end_block && \ + a##_end_block >= b##_start_block) || \ + (b##_start_block <= a##_end_block && \ + b##_end_block >= a##_start_block)) + +#define fail_if_overlap(a,b,m1,m2) do { \ + if (chk_overlap(a, b)) { \ + printf("%s blocks %lu..%lu overlap %s in blocks %lu..%lu!\n", \ + m1, a##_start_block, a##_end_block, \ + m2, b##_start_block, b##_end_block); \ + return -EINVAL; \ + } \ +} while (0) + +int do_update(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + int ret; + int block; + int erase_size = mtd->erasesize; + int page_size = mtd->writesize; + void *buf; + char *load_addr; + char *file_size; + size_t size = 0; + void *addr = NULL; + struct mx28_fcb *fcb; + unsigned long fcb_start_block = FCB_START_BLOCK; + unsigned long num_fcb_blocks = NUM_FCB_BLOCKS; + unsigned long fcb_end_block; + unsigned long mtd_num_blocks = mtd->size / mtd->erasesize; + unsigned long env_start_block = CONFIG_ENV_OFFSET / mtd->erasesize; + unsigned long env_end_block = env_start_block + + DIV_ROUND_UP(CONFIG_ENV_SIZE, mtd->erasesize) - 1; + int optind; + int fw1_set = 0; + int fw2_set = 0; + unsigned long fw1_start_block = 0, fw1_end_block; + unsigned long fw2_start_block = 0, fw2_end_block; + unsigned long fw_num_blocks; + unsigned long extra_blocks = 2; + nand_erase_options_t erase_opts = { 0, }; + int fcb_written = 0; + + load_addr = getenv("fileaddr"); + file_size = getenv("filesize"); + + if (argc < 2 && load_addr == NULL) { + printf("Load address not specified\n"); + return -EINVAL; + } + if (argc < 3 && file_size == NULL) { + printf("Image size not specified\n"); + return -EINVAL; + } + + for (optind = 1; optind < argc; optind++) { + if (strcmp(argv[optind], "-b") == 0) { + if (optind >= argc - 1) { + printf("Option %s requires an argument\n", argv[optind]); + return -EINVAL; + } + optind++; + fcb_start_block = simple_strtoul(argv[optind], NULL, 0); + if (fcb_start_block >= mtd_num_blocks) { + printf("Block number %lu is out of range: 0..%lu\n", + fcb_start_block, mtd_num_blocks - 1); + return -EINVAL; + } + } else if (strcmp(argv[optind], "-n") == 0) { + if (optind >= argc - 1) { + printf("Option %s requires an argument\n", argv[optind]); + return -EINVAL; + } + optind++; + num_fcb_blocks = simple_strtoul(argv[optind], NULL, 0); + if (num_fcb_blocks > MAX_FCB_BLOCKS) { + printf("Extraneous number of FCB blocks; max. allowed: %u\n", + MAX_FCB_BLOCKS); + return -EINVAL; + } + } else if (strcmp(argv[optind], "-f") == 0) { + if (optind >= argc - 1) { + printf("Option %s requires an argument\n", argv[optind]); + return -EINVAL; + } + optind++; + fw1_start_block = simple_strtoul(argv[optind], NULL, 0); + if (fw1_start_block >= mtd_num_blocks) { + printf("Block number %lu is out of range: 0..%lu\n", + fw1_start_block, + mtd_num_blocks - 1); + return -EINVAL; + } + fw1_set = 1; + } else if (strcmp(argv[optind], "-r") == 0) { + if (optind < argc - 1 && argv[optind + 1][0] != '-') { + optind++; + fw2_start_block = simple_strtoul(argv[optind], NULL, 0); + if (fw2_start_block >= mtd_num_blocks) { + printf("Block number %lu is out of range: 0..%lu\n", + fw2_start_block, + mtd_num_blocks - 1); + return -EINVAL; + } + } + fw2_set = 1; + } else if (strcmp(argv[optind], "-e") == 0) { + if (optind >= argc - 1) { + printf("Option %s requires an argument\n", argv[optind]); + return -EINVAL; + } + optind++; + extra_blocks = simple_strtoul(argv[optind], NULL, 0); + if (extra_blocks >= mtd_num_blocks) { + printf("Extra block count %lu is out of range: 0..%lu\n", + extra_blocks, + mtd_num_blocks - 1); + return -EINVAL; + } + } else if (argv[optind][0] == '-') { + printf("Unrecognized option %s\n", argv[optind]); + return -EINVAL; + } + } + if (argc > optind) { + load_addr = NULL; + addr = (void *)simple_strtoul(argv[optind], NULL, 0); + optind++; + } + if (argc > optind) { + file_size = NULL; + size = simple_strtoul(argv[optind], NULL, 0); + optind++; + } + if (load_addr != NULL) { + addr = (void *)simple_strtoul(load_addr, NULL, 16); + printf("Using default load address %p\n", addr); + } + if (file_size != NULL) { + size = simple_strtoul(file_size, NULL, 16); + printf("Using default file size %08x\n", size); + } + fcb_end_block = fcb_start_block + num_fcb_blocks - 1; + fw_num_blocks = DIV_ROUND_UP(size, mtd->erasesize); + + if (!fw1_set) { + fw1_start_block = fcb_end_block + 1; + fw1_end_block = fw1_start_block + fw_num_blocks + extra_blocks - 1; + if (chk_overlap(fw1, env)) { + fw1_start_block = env_end_block + 1; + fw1_end_block = fw1_start_block + fw_num_blocks + extra_blocks - 1; + } + } else { + fw1_end_block = fw1_start_block + fw_num_blocks + extra_blocks - 1; + } + + if (fw2_set && fw2_start_block == 0) { + fw2_start_block = fw1_end_block + 1; + fw2_end_block = fw2_start_block + fw_num_blocks + extra_blocks - 1; + if (chk_overlap(fw2, env)) { + fw2_start_block = env_end_block + 1; + fw2_end_block = fw2_start_block + fw_num_blocks + extra_blocks - 1; + } + } else { + fw2_end_block = fw2_start_block + fw_num_blocks + extra_blocks - 1; + } + + fail_if_overlap(fcb, env, "FCB", "Environment"); + fail_if_overlap(fcb, fw1, "FCB", "FW1"); + fail_if_overlap(fw1, env, "FW1", "Environment"); + if (fw2_set) { + fail_if_overlap(fcb, fw2, "FCB", "FW2"); + fail_if_overlap(fw2, env, "FW2", "Environment"); + fail_if_overlap(fw1, fw2, "FW1", "FW2"); + } + + buf = malloc(erase_size); + if (buf == NULL) { + printf("Failed to allocate buffer\n"); + return -ENOMEM; + } + /* search for first non-bad block in FW1 block range */ + while (fw1_start_block <= fw1_end_block) { + if (!nand_block_isbad(mtd, fw1_start_block * mtd->erasesize)) + break; + fw1_start_block++; + } + if (fw1_end_block - fw1_start_block + 1 < fw_num_blocks) { + printf("Too many bad blocks in FW1 block range: %lu..%lu\n", + fw1_end_block + 1 - fw_num_blocks - extra_blocks, + fw1_end_block); + return -EINVAL; + } + + /* search for first non-bad block in FW2 block range */ + while (fw2_set && fw2_start_block <= fw2_end_block) { + if (!nand_block_isbad(mtd, fw2_start_block * mtd->erasesize)) + break; + fw2_start_block++; + } + if (fw2_end_block - fw2_start_block + 1 < fw_num_blocks) { + printf("Too many bad blocks in FW2 area %08lx..%08lx\n", + fw2_end_block + 1 - fw_num_blocks - extra_blocks, + fw2_end_block); + return -EINVAL; + } + + fcb = create_fcb(buf, fw1_start_block, fw2_start_block, + (fw_num_blocks + extra_blocks) * mtd->erasesize); + if (IS_ERR(fcb)) { + printf("Failed to initialize FCB: %ld\n", PTR_ERR(fcb)); + return PTR_ERR(fcb); + } + encode_hamming_13_8(fcb, (void *)fcb + 512, 512); + + for (block = fcb_start_block; block < fcb_start_block + num_fcb_blocks; + block++) { + if (nand_block_isbad(mtd, block * mtd->erasesize)) { + if (block == fcb_start_block) + fcb_start_block++; + continue; + } + ret = write_fcb(buf, block); + if (ret) { + printf("Failed to write FCB to block %u\n", block); + return ret; + } + fcb_written = 1; + } + + if (!fcb_written) { + printf("Could not write FCB to flash\n"); + return -EIO; + } + + printf("Programming U-Boot image from %p to block %lu\n", + addr, fw1_start_block); + if (size & (page_size - 1)) { + memset(addr + size, 0xff, size & (page_size - 1)); + size = ALIGN(size, page_size); + } + + erase_opts.offset = fcb->fw1_start_page * page_size; + erase_opts.length = ALIGN(size, erase_size) + + extra_blocks * mtd->erasesize; + erase_opts.quiet = 1; + + printf("Erasing flash @ %08lx..%08lx\n", erase_opts.offset, + erase_opts.offset + erase_opts.length - 1); + + ret = nand_erase_opts(mtd, &erase_opts); + if (ret) { + printf("Failed to erase flash: %d\n", ret); + return ret; + } + printf("Programming flash @ %08x..%08x from %p\n", + fcb->fw1_start_page * page_size, + fcb->fw1_start_page * page_size + size, addr); + ret = nand_write_skip_bad(mtd, fcb->fw1_start_page * page_size, + &size, addr); + if (ret) { + printf("Failed to program flash: %d\n", ret); + return ret; + } + if (fw2_start_block == 0) { + return ret; + } + + printf("Programming redundant U-Boot image to block %lu\n", + fw2_start_block); + erase_opts.offset = fcb->fw2_start_page * page_size; + printf("Erasing flash @ %08lx..%08lx\n", erase_opts.offset, + erase_opts.offset + erase_opts.length - 1); + + ret = nand_erase_opts(mtd, &erase_opts); + if (ret) { + printf("Failed to erase flash: %d\n", ret); + return ret; + } + printf("Programming flash @ %08x..%08x from %p\n", + fcb->fw2_start_page * page_size, + fcb->fw2_start_page * page_size + size, addr); + ret = nand_write_skip_bad(mtd, fcb->fw2_start_page * page_size, + &size, addr); + if (ret) { + printf("Failed to program flash: %d\n", ret); + return ret; + } + return ret; +} + +U_BOOT_CMD(romupdate, 11, 0, do_update, + "Creates an FCB data structure and writes an U-Boot image to flash\n", + "[-b #] [-n #] [-f #] [-r [#]] [
] []\n" + "\t-b #\tfirst FCB block number (default 0)\n" + "\t-n #\ttotal number of FCB blocks (default 1)\n" + "\t-f #\twrite bootloader image at block #\n" + "\t-r\twrite redundant bootloader image at next free block after first image\n" + "\t-r #\twrite redundant bootloader image at block #\n" + "\t-e #\tspecify number of redundant blocks per boot loader image\n" + "\t
\tRAM address of bootloader image (default: ${fileaddr}\n" + "\t\tlength of bootloader image in RAM (default: ${filesize}" + ); diff --git a/board/karo/tx28/lowlevel_init.S b/board/karo/tx28/lowlevel_init.S new file mode 100644 index 0000000000..d191640531 --- /dev/null +++ b/board/karo/tx28/lowlevel_init.S @@ -0,0 +1,36 @@ +/* + * Board specific setup info + * + * Copyright (C) 2010 Freescale Semiconductor, Inc. + * + * (C) Copyright 2003, ARM Ltd. + * Philippe Robin, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +/* Set up the platform, once the cpu has been initialized */ + .globl lowlevel_init +lowlevel_init: + + /* All SDRAM settings are done by sdram_prep */ + mov pc, lr diff --git a/board/karo/tx28/tx28.c b/board/karo/tx28/tx28.c new file mode 100644 index 0000000000..6b00aeb128 --- /dev/null +++ b/board/karo/tx28/tx28.c @@ -0,0 +1,268 @@ +/* + * Copyright (C) 2011 Lothar Waßmann + * based on: board/freesclae/mx28_evk.c (C) 2010 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include + +#include +#include + +/* This should be removed after it's added into mach-types.h */ + +static const int mach_type = MACH_TYPE_TX28; + +DECLARE_GLOBAL_DATA_PTR; + +#ifdef CONFIG_IMX_SSP_MMC + +/* MMC pins */ +static struct pin_desc mmc0_pins_desc[] = { + { PINID_SSP0_DATA0, PIN_FUN1, PAD_8MA, PAD_3V3, 1 }, + { PINID_SSP0_DATA1, PIN_FUN1, PAD_8MA, PAD_3V3, 1 }, + { PINID_SSP0_DATA2, PIN_FUN1, PAD_8MA, PAD_3V3, 1 }, + { PINID_SSP0_DATA3, PIN_FUN1, PAD_8MA, PAD_3V3, 1 }, + { PINID_SSP0_DATA4, PIN_FUN1, PAD_8MA, PAD_3V3, 1 }, + { PINID_SSP0_DATA5, PIN_FUN1, PAD_8MA, PAD_3V3, 1 }, + { PINID_SSP0_DATA6, PIN_FUN1, PAD_8MA, PAD_3V3, 1 }, + { PINID_SSP0_DATA7, PIN_FUN1, PAD_8MA, PAD_3V3, 1 }, + { PINID_SSP0_CMD, PIN_FUN1, PAD_8MA, PAD_3V3, 1 }, + { PINID_SSP0_DETECT, PIN_FUN1, PAD_8MA, PAD_3V3, 1 }, + { PINID_SSP0_SCK, PIN_FUN1, PAD_8MA, PAD_3V3, 1 }, +}; + +static struct pin_group mmc0_pins = { + .pins = mmc0_pins_desc, + .nr_pins = ARRAY_SIZE(mmc0_pins_desc) +}; + +struct imx_ssp_mmc_cfg ssp_mmc_cfg[2] = { + {REGS_SSP0_BASE, HW_CLKCTRL_SSP0, BM_CLKCTRL_CLKSEQ_BYPASS_SSP0}, + {REGS_SSP1_BASE, HW_CLKCTRL_SSP1, BM_CLKCTRL_CLKSEQ_BYPASS_SSP1}, +}; +#endif + +/* ENET pins */ +static struct pin_desc enet_pins_desc[] = { + { PINID_ENET0_MDC, PIN_FUN1, PAD_8MA, PAD_3V3, 1 }, + { PINID_ENET0_MDIO, PIN_FUN1, PAD_8MA, PAD_3V3, 1 }, + { PINID_ENET0_RX_EN, PIN_FUN1, PAD_8MA, PAD_3V3, 1 }, + { PINID_ENET0_RXD0, PIN_FUN1, PAD_8MA, PAD_3V3, 1 }, + { PINID_ENET0_RXD1, PIN_FUN1, PAD_8MA, PAD_3V3, 1 }, + { PINID_ENET0_TX_EN, PIN_FUN1, PAD_8MA, PAD_3V3, 1 }, + { PINID_ENET0_TXD0, PIN_FUN1, PAD_8MA, PAD_3V3, 1 }, + { PINID_ENET0_TXD1, PIN_FUN1, PAD_8MA, PAD_3V3, 1 }, + { PINID_ENET_CLK, PIN_FUN1, PAD_8MA, PAD_3V3, 1 } +}; + +static struct pin_group enet_pins = { + .pins = enet_pins_desc, + .nr_pins = ARRAY_SIZE(enet_pins_desc), +}; + +static struct pin_desc duart_pins_desc[] = { + { PINID_PWM0, PIN_GPIO, PAD_8MA, PAD_3V3, 1 }, + { PINID_PWM1, PIN_GPIO, PAD_8MA, PAD_3V3, 1 }, + { PINID_I2C0_SCL, PIN_GPIO, PAD_8MA, PAD_3V3, 1 }, + { PINID_I2C0_SDA, PIN_GPIO, PAD_8MA, PAD_3V3, 1 }, + + { PINID_AUART0_RTS, PIN_FUN3, PAD_8MA, PAD_3V3, 1 }, + { PINID_AUART0_CTS, PIN_FUN3, PAD_8MA, PAD_3V3, 1 }, + { PINID_AUART0_TX, PIN_FUN3, PAD_8MA, PAD_3V3, 1 }, + { PINID_AUART0_RX, PIN_FUN3, PAD_8MA, PAD_3V3, 1 }, +}; + +static struct pin_group duart_pins = { + .pins = duart_pins_desc, + .nr_pins = ARRAY_SIZE(duart_pins_desc), +}; + +static struct pin_desc gpmi_pins_desc[] = { + { PINID_GPMI_D00, PIN_FUN1, }, + { PINID_GPMI_D01, PIN_FUN1, }, + { PINID_GPMI_D02, PIN_FUN1, }, + { PINID_GPMI_D03, PIN_FUN1, }, + { PINID_GPMI_D04, PIN_FUN1, }, + { PINID_GPMI_D05, PIN_FUN1, }, + { PINID_GPMI_D06, PIN_FUN1, }, + { PINID_GPMI_D07, PIN_FUN1, }, + { PINID_GPMI_CE0N, PIN_FUN1, }, + { PINID_GPMI_RDY0, PIN_FUN1, }, + { PINID_GPMI_RDN, PIN_FUN1, }, + { PINID_GPMI_WRN, PIN_FUN1, }, + { PINID_GPMI_ALE, PIN_FUN1, }, + { PINID_GPMI_CLE, PIN_FUN1, }, + { PINID_GPMI_RESETN, PIN_FUN1, }, +}; + +static struct pin_group gpmi_pins = { + .pins = gpmi_pins_desc, + .nr_pins = ARRAY_SIZE(gpmi_pins_desc), +}; + +/* + * Functions + */ +static void duart_init(void) +{ + pin_set_group(&duart_pins); +} + +int board_init(void) +{ + gd->bd->bi_arch_number = mach_type; + + /* Address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x1000; + + duart_init(); + return 0; +} + +int dram_init(void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + + return 0; +} + +#ifdef CONFIG_IMX_SSP_MMC + +#ifdef CONFIG_DYNAMIC_MMC_DEVNO +int get_mmc_env_devno(void) +{ + unsigned long global_boot_mode; + + global_boot_mode = REG_RD_ADDR(GLOBAL_BOOT_MODE_ADDR); + return ((global_boot_mode & 0xf) == BOOT_MODE_SD1) ? 1 : 0; +} +#endif + + +u32 ssp_mmc_is_wp(struct mmc *mmc) +{ + return 0; +} + +int ssp_mmc_gpio_init(bd_t *bis) +{ + s32 status = 0; + u32 index = 0; + + for (index = 0; index < CONFIG_SYS_SSP_MMC_NUM; index++) { + switch (index) { + case 0: + /* Set up MMC pins */ + pin_set_group(&mmc0_pins); + break; + + default: + printf("Warning: more ssp mmc controllers configured(%d) than supported by the board(2)\n", + CONFIG_SYS_SSP_MMC_NUM); + return status; + } + status |= imx_ssp_mmc_initialize(bis, &ssp_mmc_cfg[index]); + } + + return status; +} + +int board_mmc_init(bd_t *bis) +{ + if (!ssp_mmc_gpio_init(bis)) + return 0; + else + return -1; +} + +#endif + +#if defined(CONFIG_MXC_FEC) && defined(CONFIG_GET_FEC_MAC_ADDR_FROM_IIM) +int fec_get_mac_addr(unsigned char *mac) +{ + u32 val; + int timeout = 1000; + + /* set this bit to open the OTP banks for reading */ + REG_WR(REGS_OCOTP_BASE, HW_OCOTP_CTRL_SET, + BM_OCOTP_CTRL_RD_BANK_OPEN); + + /* wait until OTP contents are readable */ + while (BM_OCOTP_CTRL_BUSY & REG_RD(REGS_OCOTP_BASE, HW_OCOTP_CTRL)) { + if (timeout-- < 0) + return -ETIMEDOUT; + udelay(100); + } + + val = REG_RD(REGS_OCOTP_BASE, HW_OCOTP_CUSTn(0)); + mac[0] = (val >> 24) & 0xFF; + mac[1] = (val >> 16) & 0xFF; + mac[2] = (val >> 8) & 0xFF; + mac[3] = (val >> 0) & 0xFF; + val = REG_RD(REGS_OCOTP_BASE, HW_OCOTP_CUSTn(1)); + mac[4] = (val >> 24) & 0xFF; + mac[5] = (val >> 16) & 0xFF; + + return 0; +} +#endif + +void enet_board_init(void) +{ + /* Set up ENET pins */ + pin_set_group(&enet_pins); + + /* Power on the external phy */ + pin_gpio_set(PINID_PWM4, 1); + pin_gpio_direction(PINID_PWM4, 1); + pin_set_type(PINID_PWM4, PIN_GPIO); + + /* Reset the external phy */ + pin_gpio_set(PINID_ENET0_RX_CLK, 0); + pin_gpio_direction(PINID_ENET0_RX_CLK, 1); + pin_set_type(PINID_ENET0_RX_CLK, PIN_GPIO); + udelay(200); + pin_gpio_set(PINID_ENET0_RX_CLK, 1); +} + +#ifdef CONFIG_MXS_NAND +#include +extern int mxs_gpmi_nand_init(struct mtd_info *mtd, struct nand_chip *chip); + +int board_nand_init(struct mtd_info *mtd, struct nand_chip *chip) +{ + pin_set_group(&gpmi_pins); + return mxs_gpmi_nand_init(mtd, chip); +} +#endif + +int checkboard(void) +{ + printf("Board: Ka-Ro TX28\n"); + + return 0; +} diff --git a/board/karo/tx28/u-boot.lds b/board/karo/tx28/u-boot.lds new file mode 100644 index 0000000000..b7efe6d72c --- /dev/null +++ b/board/karo/tx28/u-boot.lds @@ -0,0 +1,51 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + . = ALIGN(4); + .text : + { + cpu/arm926ejs/start.o (.text) + *(.text) + } + .rodata : { *(.rodata) } + . = ALIGN(4); + .data : { *(.data) } + . = ALIGN(4); + .got : { *(.got) } + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss (NOLOAD) : { *(.bss) } + _end = .; +} diff --git a/common/Makefile b/common/Makefile index 3781738e19..ad7cb4f36e 100644 --- a/common/Makefile +++ b/common/Makefile @@ -55,12 +55,16 @@ COBJS-$(CONFIG_ENV_IS_EMBEDDED) += env_embedded.o COBJS-$(CONFIG_ENV_IS_IN_EEPROM) += env_embedded.o COBJS-$(CONFIG_ENV_IS_IN_FLASH) += env_embedded.o COBJS-$(CONFIG_ENV_IS_IN_NVRAM) += env_embedded.o +COBJS-$(CONFIG_ENV_IS_IN_MMC) += env_embedded.o +COBJS-$(CONFIG_ENV_IS_IN_NAND) += env_embedded.o +COBJS-$(CONFIG_ENV_IS_IN_SPI_FLASH) += env_embedded.o COBJS-$(CONFIG_ENV_IS_IN_FLASH) += env_flash.o COBJS-$(CONFIG_ENV_IS_IN_MG_DISK) += env_mgdisk.o COBJS-$(CONFIG_ENV_IS_IN_NAND) += env_nand.o COBJS-$(CONFIG_ENV_IS_IN_NVRAM) += env_nvram.o COBJS-$(CONFIG_ENV_IS_IN_ONENAND) += env_onenand.o COBJS-$(CONFIG_ENV_IS_IN_SPI_FLASH) += env_sf.o +COBJS-$(CONFIG_ENV_IS_IN_MMC) += env_mmc.o COBJS-$(CONFIG_ENV_IS_NOWHERE) += env_nowhere.o # command @@ -72,6 +76,7 @@ COBJS-$(CONFIG_CMD_BEDBUG) += bedbug.o cmd_bedbug.o COBJS-$(CONFIG_CMD_BMP) += cmd_bmp.o COBJS-$(CONFIG_CMD_BOOTLDR) += cmd_bootldr.o COBJS-$(CONFIG_CMD_CACHE) += cmd_cache.o +COBJS-$(CONFIG_CMD_CLOCK) += cmd_clk.o COBJS-$(CONFIG_CMD_CONSOLE) += cmd_console.o COBJS-$(CONFIG_CMD_CPLBINFO) += cmd_cplbinfo.o COBJS-$(CONFIG_DATAFLASH_MMC_SELECT) += cmd_dataflash_mmc_mux.o @@ -96,6 +101,7 @@ COBJS-$(CONFIG_CMD_FLASH) += cmd_flash.o ifdef CONFIG_FPGA COBJS-$(CONFIG_CMD_FPGA) += cmd_fpga.o endif +COBJS-$(CONFIG_CMD_IIM) += cmd_iim.o COBJS-$(CONFIG_CMD_I2C) += cmd_i2c.o COBJS-$(CONFIG_CMD_IDE) += cmd_ide.o COBJS-$(CONFIG_CMD_IMMAP) += cmd_immap.o @@ -120,6 +126,7 @@ COBJS-y += cmd_nand.o COBJS-$(CONFIG_CMD_NET) += cmd_net.o COBJS-$(CONFIG_CMD_ONENAND) += cmd_onenand.o COBJS-$(CONFIG_CMD_OTP) += cmd_otp.o +COBJS-$(CONFIG_CMD_PATA) += cmd_pata.o ifdef CONFIG_PCI COBJS-$(CONFIG_CMD_PCI) += cmd_pci.o endif diff --git a/common/cmd_bootce.c b/common/cmd_bootce.c new file mode 100644 index 0000000000..594df392d6 --- /dev/null +++ b/common/cmd_bootce.c @@ -0,0 +1,1305 @@ +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; /* defines global data structure pointer */ + + +/*/////////////////////////////////////////////////////////////////////////////////////////////*/ +/* Local macro */ + +/* Memory macro */ + +/* #define CE_RAM_BASE 0x80100000 */ +/* #define CE_WINCE_VRAM_BASE 0x80000000 */ +/* #define CE_FIX_ADDRESS(a) (((a) - CE_WINCE_VRAM_BASE) + CE_RAM_BASE) */ +#define CE_FIX_ADDRESS(a) (a) + +/* Bin image parse states */ + +#define CE_PS_RTI_ADDR 0 +#define CE_PS_RTI_LEN 1 +#define CE_PS_E_ADDR 2 +#define CE_PS_E_LEN 3 +#define CE_PS_E_CHKSUM 4 +#define CE_PS_E_DATA 5 + +/* Min/max */ + +#define CE_MIN(a, b) (((a) < (b)) ? (a) : (b)) +#define CE_MAX(a, b) (((a) > (b)) ? (a) : (b)) + +// Macro string + +#define _STRMAC(s) #s +#define STRMAC(s) _STRMAC(s) + + + + + + + +/////////////////////////////////////////////////////////////////////////////////////////////// +// Global data + +static ce_bin __attribute__ ((aligned (32))) g_bin; +static ce_net __attribute__ ((aligned (32))) g_net; + + +/////////////////////////////////////////////////////////////////////////////////////////////// +// Local proto + + + + +/////////////////////////////////////////////////////////////////////////////////////////////// +// Implementation + +int ce_bin_load(void* image, int imglen) +{ + ce_init_bin(&g_bin, image); + + g_bin.dataLen = imglen; + + if (ce_parse_bin(&g_bin) == CE_PR_EOF) + { + ce_prepare_run_bin(&g_bin); + return 1; + } + + return 0; +} + +int ce_is_bin_image(void* image, int imglen) +{ + if (imglen < CE_BIN_SIGN_LEN) + { + return 0; + } + + return (memcmp(image, CE_BIN_SIGN, CE_BIN_SIGN_LEN) == 0); +} + +void ce_bin_init_parser(void) +{ + // No buffer address by now, will be specified + // latter by the ce_bin_parse_next routine + + ce_init_bin(&g_bin, NULL); +} + +int ce_bin_parse_next(void* parseBuffer, int len) +{ + int rc; + + g_bin.data = (unsigned char*)parseBuffer; + g_bin.dataLen = len; + rc = ce_parse_bin(&g_bin); + + if (rc == CE_PR_EOF) + { + ce_prepare_run_bin(&g_bin); + } + + return rc; +} + +void ce_init_bin(ce_bin* bin, unsigned char* dataBuffer) +{ + memset(bin, 0, sizeof(ce_bin)); + + bin->data = dataBuffer; + bin->parseState = CE_PS_RTI_ADDR; + bin->parsePtr = (unsigned char*)&bin->rtiPhysAddr; +} + +int ce_parse_bin(ce_bin* bin) +{ + unsigned char* pbData = bin->data; + int pbLen = bin->dataLen; + int copyLen; + + #ifdef DEBUG + printf("starting ce image parsing:\n\tbin->binLen: 0x%08X\n", bin->binLen); + printf("\tpbData: 0x%08X pbLEN: 0x%08X\n", pbData, pbLen); + #endif + + if (pbLen) + { + if (bin->binLen == 0) + { + // Check for the .BIN signature first + + if (!ce_is_bin_image(pbData, pbLen)) + { + printf("Error: Invalid or corrupted .BIN image!\n"); + + return CE_PR_ERROR; + } + + printf("Loading Windows CE .BIN image ...\n"); + + // Skip signature + + pbLen -= CE_BIN_SIGN_LEN; + pbData += CE_BIN_SIGN_LEN; + } + + while (pbLen) + { + switch (bin->parseState) + { + case CE_PS_RTI_ADDR: + case CE_PS_RTI_LEN: + case CE_PS_E_ADDR: + case CE_PS_E_LEN: + case CE_PS_E_CHKSUM: + + copyLen = CE_MIN(sizeof(unsigned int) - bin->parseLen, pbLen); + + memcpy(&bin->parsePtr[ bin->parseLen ], pbData, copyLen); + + bin->parseLen += copyLen; + pbLen -= copyLen; + pbData += copyLen; + + if (bin->parseLen == sizeof(unsigned int)) + { + if (bin->parseState == CE_PS_RTI_ADDR) + { + bin->rtiPhysAddr = CE_FIX_ADDRESS(bin->rtiPhysAddr); + } + else if (bin->parseState == CE_PS_E_ADDR) + { + if (bin->ePhysAddr) + { + bin->ePhysAddr = CE_FIX_ADDRESS(bin->ePhysAddr); + } + } + + bin->parseState ++; + bin->parseLen = 0; + bin->parsePtr += sizeof(unsigned int); + + if (bin->parseState == CE_PS_E_DATA) + { + if (bin->ePhysAddr) + { + bin->parsePtr = (unsigned char*)(bin->ePhysAddr); + bin->parseChkSum = 0; + } + else + { + // EOF + + pbLen = 0; + bin->endOfBin = 1; + } + } + } + + break; + + case CE_PS_E_DATA: + + if (bin->ePhysAddr) + { + copyLen = CE_MIN(bin->ePhysLen - bin->parseLen, pbLen); + bin->parseLen += copyLen; + pbLen -= copyLen; + + #ifdef DEBUG + printf("copy %d bytes from: 0x%08X to: 0x%08X\n", copyLen, pbData, bin->parsePtr); + #endif + while (copyLen --) + { + bin->parseChkSum += *pbData; + *bin->parsePtr ++ = *pbData ++; + } + + if (bin->parseLen == bin->ePhysLen) + { + printf("Section [%02d]: address 0x%08X, size 0x%08X, checksum %s\n", + bin->secion, + bin->ePhysAddr, + bin->ePhysLen, + (bin->eChkSum == bin->parseChkSum) ? "ok" : "fail"); + + if (bin->eChkSum != bin->parseChkSum) + { + // Checksum error! + + printf("Error: Checksum error, corrupted .BIN file!\n"); + + bin->binLen = 0; + + return CE_PR_ERROR; + } + + bin->secion ++; + bin->parseState = CE_PS_E_ADDR; + bin->parseLen = 0; + bin->parsePtr = (unsigned char*)(&bin->ePhysAddr); + } + } + else + { + bin->parseLen = 0; + bin->endOfBin = 1; + pbLen = 0; + } + + break; + } + } + } + + if (bin->endOfBin) + { + // Find entry point + + if (!ce_lookup_ep_bin(bin)) + { + printf("Error: entry point not found!\n"); + + bin->binLen = 0; + + return CE_PR_ERROR; + } + + printf("Entry point: 0x%08X, address range: 0x%08X-0x%08X\n", + bin->eEntryPoint, + bin->rtiPhysAddr, + bin->rtiPhysAddr + bin->rtiPhysLen); + + return CE_PR_EOF; + } + + // Need more data + + bin->binLen += bin->dataLen; + + return CE_PR_MORE; +} + + + + + + + +void ce_prepare_run_bin(ce_bin* bin) +{ + ce_driver_globals* drv_glb; + char *e, *s; + char tmp[64]; + int i; + + + // Clear os RAM area (if needed) + + //if (bin->edbgConfig.flags & EDBG_FL_CLEANBOOT) + { + #ifdef DEBUG + printf("cleaning memory from 0x%08X to 0x%08X\n", bin->eRamStart, bin->eRamStart + bin->eRamLen); + #endif + printf("Preparing clean boot ... "); + memset((void*)bin->eRamStart, 0, bin->eRamLen); + printf("ok\n"); + } + + // Prepare driver globals (if needed) + + if (bin->eDrvGlb) + { + drv_glb = (ce_driver_globals*)bin->eDrvGlb; + + // Fill out driver globals + + memset(drv_glb, 0, sizeof(ce_driver_globals)); + + // Signature + + drv_glb->signature = DRV_GLB_SIGNATURE; + + // No flags by now + + drv_glb->flags = 0; + + /* Local ethernet MAC address */ + i = getenv_r ("ethaddr", tmp, sizeof (tmp)); + s = (i > 0) ? tmp : 0; + + for (i = 0; i < 6; ++i) { + drv_glb->macAddr[i] = s ? simple_strtoul (s, &e, 16) : 0; + if (s) + s = (*e) ? e + 1 : e; + } + + + #ifdef DEBUG + printf("got MAC address %02X:%02X:%02X:%02X:%02X:%02X from environment\n", drv_glb->macAddr[0],drv_glb->macAddr[1],drv_glb->macAddr[2],drv_glb->macAddr[3],drv_glb->macAddr[4],drv_glb->macAddr[5]); + #endif + + /* Local IP address */ + drv_glb->ipAddr=(unsigned int)getenv_IPaddr("ipaddr"); + #ifdef DEBUG + printf("got IP address "); + print_IPaddr((IPaddr_t)drv_glb->ipAddr); + printf(" from environment\n"); + #endif + + /* Subnet mask */ + drv_glb->ipMask=(unsigned long)getenv_IPaddr("netmask"); + #ifdef DEBUG + printf("got IP mask "); + print_IPaddr((IPaddr_t)drv_glb->ipMask); + printf(" from environment\n"); + #endif + + /* Gateway config */ + drv_glb->ipGate=(unsigned long)getenv_IPaddr("gatewayip"); + #ifdef DEBUG + printf("got gateway address "); + print_IPaddr((IPaddr_t)drv_glb->ipGate); + printf(" from environment\n"); + #endif + + + + + + // EDBG services config + + memcpy(&drv_glb->edbgConfig, &bin->edbgConfig, sizeof(bin->edbgConfig)); + + + + + } + +} + + +int ce_lookup_ep_bin(ce_bin* bin) +{ + ce_rom_hdr* header; + ce_toc_entry* tentry; + e32_rom* e32; + unsigned int i; + + // Check image Table Of Contents (TOC) signature + + if (*(unsigned int*)(bin->rtiPhysAddr + ROM_SIGNATURE_OFFSET) != ROM_SIGNATURE) + { + // Error: Did not find image TOC signature! + + return 0; + } + + + // Lookup entry point + + header = (ce_rom_hdr*)CE_FIX_ADDRESS(*(unsigned int*)(bin->rtiPhysAddr + ROM_SIGNATURE_OFFSET + sizeof(unsigned int))); + tentry = (ce_toc_entry*)(header + 1); + + for (i = 0; i < header->nummods; i ++) + { + // Look for 'nk.exe' module + + if (strcmp((char*)CE_FIX_ADDRESS(tentry[ i ].fileName), "nk.exe") == 0) + { + // Save entry point and RAM addresses + + e32 = (e32_rom*)CE_FIX_ADDRESS(tentry[ i ].e32Offset); + + bin->eEntryPoint = CE_FIX_ADDRESS(tentry[ i ].loadOffset) + e32->e32_entryrva; + bin->eRamStart = CE_FIX_ADDRESS(header->ramStart); + bin->eRamLen = header->ramEnd - header->ramStart; + + // Save driver_globals address + // Must follow RAM section in CE config.bib file + // + // eg. + // + // RAM 80900000 03200000 RAM + // DRV_GLB 83B00000 00001000 RESERVED + // + + bin->eDrvGlb = CE_FIX_ADDRESS(header->ramEnd); + + return 1; + } + } + + // Error: Did not find 'nk.exe' module + + return 0; +} + + + + +typedef void (*CeEntryPointPtr)(void); + + + +void ce_run_bin(ce_bin* bin) +{ + CeEntryPointPtr EnrtryPoint; + + printf("Launching Windows CE ...\n"); + + + EnrtryPoint = (CeEntryPointPtr)bin->eEntryPoint; + + EnrtryPoint(); + +} + +int ce_boot (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + unsigned long addr; + unsigned long image_size; + unsigned char *s; + + + if (argc < 2) { + printf ("myUsage:\n%s\n", cmdtp->usage); + return 1; + } + + addr = simple_strtoul(argv[1], NULL, 16); + image_size = 0x7fffffff; /* actually we do not know the image size */ + + printf ("## Booting Windows CE Image from address 0x%08lX ...\n", addr); + + + /* check if there is a valid windows CE image */ + if (ce_is_bin_image((void *)addr, image_size)) + { + if (!ce_bin_load((void*)addr, image_size)) + { + /* Ops! Corrupted .BIN image! */ + /* Handle error here ... */ + printf("corrupted .BIN image !!!\n"); + return 1; + + } + if ((s = getenv("autostart")) != NULL) { + if (*s == 'n') { + /* + * just use bootce to load the image to SDRAM; + * Do not start it automatically. + */ + return 0; + } + } + ce_run_bin(&g_bin); /* start the image */ + + } else { + printf("Image seems to be no valid Windows CE image !\n"); + return 1; + + } + return 1; /* never reached - just to keep compiler happy */ + + +} + + + +U_BOOT_CMD( + bootce, 2, 0, ce_boot, + "bootce\t- Boot a Windows CE image from memory \n", + "[args..]\n" + "\taddr\t\t-boot image from address addr\n" +); + + + +#if 1 +static void wince_handler (uchar * pkt, unsigned dest, unsigned src, unsigned len) +{ + + + NetState = NETLOOP_SUCCESS; /* got input - quit net loop */ + if(!memcmp(g_net.data + g_net.align_offset, gd->bd->bi_enetaddr, 6)) { + g_net.got_packet_4me=1; + g_net.dataLen=len; + } else { + g_net.got_packet_4me=0; + return; + } + + if(1) { + g_net.srvAddrRecv.sin_port = ntohs(*((unsigned short *)(g_net.data + ETHER_HDR_SIZE + IP_HDR_SIZE_NO_UDP + g_net.align_offset))); + NetCopyIP(&g_net.srvAddrRecv.sin_addr, g_net.data + ETHER_HDR_SIZE + g_net.align_offset + 12); + memcpy(NetServerEther, g_net.data + g_net.align_offset +6, 6); + + #if 0 + printf("received packet: buffer 0x%08X Laenge %d \n", (unsigned long) pkt, len); + printf("from "); + print_IPaddr(g_net.srvAddrRecv.sin_addr); + printf(", port: %d\n", g_net.srvAddrRecv.sin_port); + + + + ce_dump_block(pkt, len); + + printf("Headers:\n"); + ce_dump_block(pkt - ETHER_HDR_SIZE - IP_HDR_SIZE, ETHER_HDR_SIZE + IP_HDR_SIZE); + printf("\n\nmy port should be: %d\n", ntohs(*((unsigned short *)(g_net.data + ETHER_HDR_SIZE + IP_HDR_SIZE_NO_UDP + g_net.align_offset +2)))); + #endif + } + +} + + + +/* returns packet lengt if successfull */ +int ce_recv_packet(char *buf, int len, struct sockaddr_in *from, struct sockaddr_in *local, struct timeval *timeout){ + + int rxlength; + ulong time_started; + + + + g_net.got_packet_4me=0; + time_started = get_timer(0); + + + NetRxPackets[0] = (uchar *)buf; + NetSetHandler(wince_handler); + + while(1) { + rxlength=eth_rx(); + if(g_net.got_packet_4me) + return g_net.dataLen; + /* check for timeout */ + if (get_timer(time_started) > timeout->tv_sec * CFG_HZ) { + return -1; + } + } +} + + + +int ce_recv_frame(ce_net* net, int timeout) +{ + struct timeval timeo; + + // Setup timeout + + timeo.tv_sec = timeout; + timeo.tv_usec = 0; + + /* Receive UDP packet */ + + net->dataLen = ce_recv_packet(net->data+net->align_offset, sizeof(net->data)-net->align_offset, &net->srvAddrRecv, &net->locAddr, &timeo); + + if (net->dataLen < 0) + { + /* Error! No data available */ + + net->dataLen = 0; + } + + return net->dataLen; +} + +int ce_process_download(ce_net* net, ce_bin* bin) +{ + int ret = CE_PR_MORE; + + if (net->dataLen >= 2) + { + unsigned short command; + + command = ntohs(*(unsigned short*)(net->data+CE_DOFFSET)); + + #ifdef DEBUG + printf("command found: 0x%04X\n", command); + #endif + + switch (command) + { + case EDBG_CMD_WRITE_REQ: + + if (!net->link) + { + // Check file name for WRITE request + // CE EShell uses "boot.bin" file name + + /*printf(">>>>>>>> First Frame, IP: %s, port: %d\n", + inet_ntoa((in_addr_t *)&net->srvAddrRecv), + net->srvAddrRecv.sin_port);*/ + + if (strncmp((char*)(net->data +CE_DOFFSET + 2), "boot.bin", 8) == 0) + { + // Some diag output + + if (net->verbose) + { + printf("Locked Down download link, IP: "); + print_IPaddr(net->srvAddrRecv.sin_addr); + printf(", port: %d\n", net->srvAddrRecv.sin_port); + } + + + + + if (net->verbose) + { + printf("Sending BOOTME request [%d] to ", (int)net->secNum); + print_IPaddr(net->srvAddrSend.sin_addr); + printf("\n"); + } + + + + + // Lock down EShell download link + + net->locAddr.sin_port = (EDBG_DOWNLOAD_PORT + 1); + net->srvAddrSend.sin_port = net->srvAddrRecv.sin_port; + net->srvAddrSend.sin_addr = net->srvAddrRecv.sin_addr; + net->link = 1; + } + else + { + // Unknown link + + net->srvAddrRecv.sin_port = 0; + } + + // Return write ack + + if (net->link) + { + ce_send_write_ack(net); + } + + break; + } + + case EDBG_CMD_WRITE: + + /* Fix data len */ + bin->dataLen = net->dataLen - 4; + + // Parse next block of .bin file + + ret = ce_parse_bin(bin); + + // Request next block + + if (ret != CE_PR_ERROR) + { + net->blockNum ++; + + ce_send_write_ack(net); + } + + break; + + case EDBG_CMD_READ_REQ: + + // Read requests are not supported + // Do nothing ... + + break; + + case EDBG_CMD_ERROR: + + // Error condition on the host side + + printf("Error: unknown error on the host side\n"); + + bin->binLen = 0; + ret = CE_PR_ERROR; + + break; + default: + printf("unknown command 0x%04X ????\n", command); + while(1); + } + + + } + + return ret; +} + + + +void ce_init_edbg_link(ce_net* net) +{ + /* Initialize EDBG link for commands */ + + net->locAddr.sin_port = EDBG_DOWNLOAD_PORT; + net->srvAddrSend.sin_port = EDBG_DOWNLOAD_PORT; + net->srvAddrRecv.sin_port = 0; + net->link = 0; +} + +void ce_process_edbg(ce_net* net, ce_bin* bin) +{ + eth_dbg_hdr* header; + + + + if (net->dataLen < sizeof(eth_dbg_hdr)) + { + /* Bad packet */ + + net->srvAddrRecv.sin_port = 0; + return; + } + + header = (eth_dbg_hdr*)(net->data + net->align_offset + ETHER_HDR_SIZE + IP_HDR_SIZE); + + if (header->id != EDBG_ID) + { + /* Bad packet */ + + net->srvAddrRecv.sin_port = 0; + return; + } + + if (header->service != EDBG_SVC_ADMIN) + { + /* Unknown service */ + + return; + } + + if (!net->link) + { + /* Some diag output */ + + if (net->verbose) + { + printf("Locked Down EDBG service link, IP: "); + print_IPaddr(net->srvAddrRecv.sin_addr); + printf(", port: %d\n", net->srvAddrRecv.sin_port); + } + + /* Lock down EDBG link */ + + net->srvAddrSend.sin_port = net->srvAddrRecv.sin_port; + net->link = 1; + } + + switch (header->cmd) + { + case EDBG_CMD_JUMPIMG: + + net->gotJumpingRequest = 1; + + if (net->verbose) + { + printf("Received JUMPING command\n"); + } + + /* Just pass through and copy CONFIG structure */ + + case EDBG_CMD_OS_CONFIG: + + /* Copy config structure */ + + memcpy(&bin->edbgConfig, header->data, sizeof(edbg_os_config_data)); + + if (net->verbose) + { + printf("Received CONFIG command\n"); + + if (bin->edbgConfig.flags & EDBG_FL_DBGMSG) + { + printf("--> Enabling DBGMSG service, IP: %d.%d.%d.%d, port: %d\n", + (bin->edbgConfig.dbgMsgIPAddr >> 0) & 0xFF, + (bin->edbgConfig.dbgMsgIPAddr >> 8) & 0xFF, + (bin->edbgConfig.dbgMsgIPAddr >> 16) & 0xFF, + (bin->edbgConfig.dbgMsgIPAddr >> 24) & 0xFF, + (int)bin->edbgConfig.dbgMsgPort); + } + + if (bin->edbgConfig.flags & EDBG_FL_PPSH) + { + printf("--> Enabling PPSH service, IP: %d.%d.%d.%d, port: %d\n", + (bin->edbgConfig.ppshIPAddr >> 0) & 0xFF, + (bin->edbgConfig.ppshIPAddr >> 8) & 0xFF, + (bin->edbgConfig.ppshIPAddr >> 16) & 0xFF, + (bin->edbgConfig.ppshIPAddr >> 24) & 0xFF, + (int)bin->edbgConfig.ppshPort); + } + + if (bin->edbgConfig.flags & EDBG_FL_KDBG) + { + printf("--> Enabling KDBG service, IP: %d.%d.%d.%d, port: %d\n", + (bin->edbgConfig.kdbgIPAddr >> 0) & 0xFF, + (bin->edbgConfig.kdbgIPAddr >> 8) & 0xFF, + (bin->edbgConfig.kdbgIPAddr >> 16) & 0xFF, + (bin->edbgConfig.kdbgIPAddr >> 24) & 0xFF, + (int)bin->edbgConfig.kdbgPort); + } + + if (bin->edbgConfig.flags & EDBG_FL_CLEANBOOT) + { + printf("--> Force clean boot\n"); + } + } + + break; + + default: + if (net->verbose) { + printf("Received unknown command: %08X\n", header->cmd); + } + return; + } + + /* Respond with ack */ + header->flags = EDBG_FL_FROM_DEV | EDBG_FL_ACK; + net->dataLen = EDBG_DATA_OFFSET; + ce_send_frame(net); +} + +int ce_send_write_ack(ce_net* net) +{ + unsigned short* wdata; + unsigned long aligned_address; + + aligned_address=(unsigned long)net->data+ETHER_HDR_SIZE+IP_HDR_SIZE+net->align_offset; + + wdata = (unsigned short*)aligned_address; + wdata[ 0 ] = htons(EDBG_CMD_WRITE_ACK); + wdata[ 1 ] = htons(net->blockNum); + + net->dataLen = 4; + + return ce_send_frame(net); +} + + + +int ce_send_frame(ce_net* net) +{ + /* Send UDP packet */ + NetTxPacket = (uchar *)net->data + net->align_offset; + return NetSendUDPPacket(NetServerEther, net->srvAddrSend.sin_addr, (int)net->srvAddrSend.sin_port, (int)net->locAddr.sin_port, net->dataLen); +} + + + + + + + +int ce_send_bootme(ce_net* net) +{ + eth_dbg_hdr* header; + edbg_bootme_data* data; + + char *e, *s; + int i; + unsigned char tmp[64]; + unsigned char *macp; + + #ifdef DEBUG + char *pkt; + #endif + + + /* Fill out BOOTME packet */ + memset(net->data, 0, PKTSIZE); + header = (eth_dbg_hdr*)(net->data +CE_DOFFSET); + data = (edbg_bootme_data*)header->data; + + header->id=EDBG_ID; + header->service = EDBG_SVC_ADMIN; + header->flags = EDBG_FL_FROM_DEV; + header->seqNum = net->secNum ++; + header->cmd = EDBG_CMD_BOOTME; + + data->versionMajor = 0; + data->versionMinor = 0; + data->cpuId = EDBG_CPU_TYPE_ARM; + data->bootmeVer = EDBG_CURRENT_BOOTME_VERSION; + data->bootFlags = 0; + data->downloadPort = 0; + data->svcPort = 0; + + macp=(unsigned char *)data->macAddr; + /* MAC address from environment*/ + i = getenv_r ("ethaddr", tmp, sizeof (tmp)); + s = (i > 0) ? tmp : 0; + for (i = 0; i < 6; ++i) { + macp[i] = s ? simple_strtoul (s, &e, 16) : 0; + if (s) + s = (*e) ? e + 1 : e; + } + + /* IP address from environment */ + data->ipAddr = (unsigned int)getenv_IPaddr("ipaddr"); + + // Device name string (NULL terminated). Should include + // platform and number based on Ether address (e.g. Odo42, CEPCLS2346, etc) + + // We will use lower MAC address segment to create device name + // eg. MAC '00-0C-C6-69-09-05', device name 'Triton05' + + strcpy(data->platformId, "Triton"); + sprintf(data->deviceName, "%s%02X", data->platformId, macp[5]); + + +#ifdef DEBUG + + printf("header->id: %08X\r\n", header->id); + printf("header->service: %08X\r\n", header->service); + printf("header->flags: %08X\r\n", header->flags); + printf("header->seqNum: %08X\r\n", header->seqNum); + printf("header->cmd: %08X\r\n\r\n", header->cmd); + + printf("data->versionMajor: %08X\r\n", data->versionMajor); + printf("data->versionMinor: %08X\r\n", data->versionMinor); + printf("data->cpuId: %08X\r\n", data->cpuId); + printf("data->bootmeVer: %08X\r\n", data->bootmeVer); + printf("data->bootFlags: %08X\r\n", data->bootFlags); + printf("data->svcPort: %08X\r\n\r\n", data->svcPort); + + printf("data->macAddr: %02X-%02X-%02X-%02X-%02X-%02X\r\n", + (data->macAddr[0] >> 0) & 0xFF, + (data->macAddr[0] >> 8) & 0xFF, + (data->macAddr[1] >> 0) & 0xFF, + (data->macAddr[1] >> 8) & 0xFF, + (data->macAddr[2] >> 0) & 0xFF, + (data->macAddr[2] >> 8) & 0xFF); + + printf("data->ipAddr: %d.%d.%d.%d\r\n", + (data->ipAddr >> 0) & 0xFF, + (data->ipAddr >> 8) & 0xFF, + (data->ipAddr >> 16) & 0xFF, + (data->ipAddr >> 24) & 0xFF); + + printf("data->platformId: %s\r\n", data->platformId); + + printf("data->deviceName: %s\r\n", data->deviceName); + +#endif + + + // Some diag output ... + + if (net->verbose) + { + printf("Sending BOOTME request [%d] to ", (int)net->secNum); + print_IPaddr(net->srvAddrSend.sin_addr); + printf("\n"); + } + + // Send packet + + net->dataLen = BOOTME_PKT_SIZE; + + + #ifdef DEBUG + printf("\n\n\nStart of buffer: 0x%08X\n", (unsigned long)net->data); + printf("Start of ethernet buffer: 0x%08X\n", (unsigned long)net->data+net->align_offset); + printf("Start of CE header: 0x%08X\n", (unsigned long)header); + printf("Start of CE data: 0x%08X\n", (unsigned long)data); + + pkt = (uchar *)net->data+net->align_offset; + printf("\n\npacket to send (ceconnect): \n"); + for(i=0; i<(net->dataLen+ETHER_HDR_SIZE+IP_HDR_SIZE); i++) { + printf("0x%02X ", pkt[i]); + if(!((i+1)%16)) + printf("\n"); + } + printf("\n\n"); + #endif + + memcpy(NetServerEther, NetBcastAddr, 6); + + return ce_send_frame(net); +} + + + +void ce_dump_block(unsigned char *ptr, int length) { + + int i; + int j; + + for(i=0; i0x1f) && (ptr[j]<0x7f)) { + printf("%c", ptr[j]); + } else { + printf("."); + } + } + } + + } + + printf("\n\n"); +} + + + + + + + + + + +void ce_init_download_link(ce_net* net, ce_bin* bin, struct sockaddr_in* host_addr, int verbose) +{ + unsigned long aligned_address; + /* Initialize EDBG link for download */ + + + memset(net, 0, sizeof(ce_net)); + + /* our buffer contains space for ethernet- ip- and udp- headers */ + /* calucalate an offset that our ce field is aligned to 4 bytes */ + aligned_address=(unsigned long)net->data; /* this is the start of our physical buffer */ + aligned_address += (ETHER_HDR_SIZE+IP_HDR_SIZE); /* we need 42 bytes room for headers (14 Ethernet , 20 IPv4, 8 UDP) */ + net->align_offset = 4-(aligned_address%4); /* want CE header aligned to 4 Byte boundary */ + if(net->align_offset == 4) { + net->align_offset=0; + } + + net->locAddr.sin_family = AF_INET; + net->locAddr.sin_addr = getenv_IPaddr("ipaddr"); + net->locAddr.sin_port = EDBG_DOWNLOAD_PORT; + + net->srvAddrSend.sin_family = AF_INET; + net->srvAddrSend.sin_port = EDBG_DOWNLOAD_PORT; + + net->srvAddrRecv.sin_family = AF_INET; + net->srvAddrRecv.sin_port = 0; + + if (host_addr->sin_addr) + { + /* Use specified host address ... */ + + net->srvAddrSend.sin_addr = host_addr->sin_addr; + net->srvAddrRecv.sin_addr = host_addr->sin_addr; + } + else + { + /* ... or use default server address */ + + net->srvAddrSend.sin_addr = getenv_IPaddr("serverip"); + net->srvAddrRecv.sin_addr = getenv_IPaddr("serverip"); + } + + net->verbose = verbose; + /* Initialize .BIN parser */ + ce_init_bin(bin, net->data + CE_DOFFSET + 4); + + + + eth_halt(); + +#ifdef CONFIG_NET_MULTI + eth_set_current(); +#endif + if (eth_init(gd->bd) < 0) { + #ifdef ET_DEBUG + puts("ceconnect: failed to init ethernet !\n"); + #endif + eth_halt(); + return; + } + #ifdef ET_DEBUG + puts("ceconnect: init ethernet done!\n"); + #endif + + + memcpy (NetOurEther, gd->bd->bi_enetaddr, 6); + NetCopyIP(&NetOurIP, &gd->bd->bi_ip_addr); + NetOurGatewayIP = getenv_IPaddr ("gatewayip"); + NetOurSubnetMask= getenv_IPaddr ("netmask"); + NetServerIP = getenv_IPaddr ("serverip"); + +} + + +int ce_load(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + int i; + int verbose, use_timeout; + int timeout, recv_timeout, ret; + struct sockaddr_in host_ip_addr; + + // -v verbose + + verbose = 0; + use_timeout = 0; + timeout = 0; + + + for(i=0;i]\n" + " -v verbose operation\n" + " -t - max wait time (#sec) for the connection\n" +); + +#endif + +/* CFG_CMD_WINCE */ diff --git a/common/cmd_bootm.c b/common/cmd_bootm.c index 86c81220d2..f43b472a4c 100644 --- a/common/cmd_bootm.c +++ b/common/cmd_bootm.c @@ -713,6 +713,13 @@ static image_header_t *image_get_kernel (ulong img_addr, int verify) return NULL; } +#if defined(CONFIG_MX51_BBG) || defined(CONFIG_MX51_3DS) + if (image_get_load(hdr) < 0x90000000) + image_set_load(hdr, image_get_load(hdr)+0x20000000); + if (image_get_ep(hdr) < 0x90000000) + image_set_ep(hdr, image_get_ep(hdr)+0x20000000); +#endif + show_boot_progress (3); image_print_contents (hdr); diff --git a/common/cmd_clk.c b/common/cmd_clk.c new file mode 100644 index 0000000000..76cd6e283a --- /dev/null +++ b/common/cmd_clk.c @@ -0,0 +1,90 @@ +/* + * (C) Copyright 2008-2010 Freescale Semiconductor, Inc. + * Terry Lv + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include + +int do_clkops(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + int rc = 0; + int freq = 0; + + switch (argc) { + case 1: + clk_info(ALL_CLK); + break; + case 2: + if ((strcmp(argv[1], "core") == 0) || + (strcmp(argv[1], "cpu") == 0)) + clk_info(CPU_CLK); + else if (strcmp(argv[1], "periph") == 0) + clk_info(PERIPH_CLK); + else if (strcmp(argv[1], "ddr") == 0) + clk_info(DDR_CLK); + else if (strcmp(argv[1], "nfc") == 0) + clk_info(NFC_CLK); + else + printf("Unsupported clock type!\n"); + break; + case 3: + freq = simple_strtoul(argv[2], NULL, 10); + if ((strcmp(argv[1], "core") == 0) || + (strcmp(argv[1], "cpu") == 0)) + clk_config(CONFIG_REF_CLK_FREQ, freq, CPU_CLK); + else if (strcmp(argv[1], "periph") == 0) + clk_config(CONFIG_REF_CLK_FREQ, freq, PERIPH_CLK); + else if (strcmp(argv[1], "ddr") == 0) + clk_config(CONFIG_REF_CLK_FREQ, freq, DDR_CLK); + else if (strcmp(argv[1], "nfc") == 0) + clk_config(CONFIG_REF_CLK_FREQ, freq, NFC_CLK); + else + printf("Unsupported clock type!\n"); + break; + default: + rc = 1; + printf("Too many parameters.\n"); + printf("Usage:\n%s\n", cmdtp->usage); + break; + } + + return rc; +} + +U_BOOT_CMD( + clk, 3, 1, do_clkops, + "Clock sub system", + "Setup/Display clock\n" + "clk - Display all clocks\n" + "clk core - Setup/Display core clock\n" + "clk periph -" + "Setup/Display peripheral clock\n" + "clk ddr - Setup/Display DDR clock\n" + "clk nfc - Setup/Display NFC clock\n" + "Example:\n" + "clk - Show various clocks\n" + "clk core 665 - Set core clock to 665MHz\n" + "clk periph 600 - Set peripheral clock to 600MHz\n" + "clk ddr 166 - Set DDR clock to 166MHz"); + diff --git a/common/cmd_iim.c b/common/cmd_iim.c new file mode 100644 index 0000000000..56e38048a9 --- /dev/null +++ b/common/cmd_iim.c @@ -0,0 +1,95 @@ +/* + * (C) Copyright 2008-2010 Freescale Semiconductor, Inc. + * + * Copyright 2007, Freescale Semiconductor, Inc + * Andy Fleming + * + * Based vaguely on the pxa mmc code: + * (C) Copyright 2003 + * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include + +int do_iimops(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + int bank = 0, + row = 0, + val = 0; + + if (argc < 3 || argc > 5) + goto err_rtn; + + if (strcmp(argv[1], "read") == 0) { + if (strcmp(argv[2], "fecmac") == 0) { + if (3 == argc) + iim_blow_func(argv[2], NULL); + else + goto err_rtn; + } else { + if (4 == argc) { + bank = simple_strtoul(argv[2], NULL, 16); + row = simple_strtoul(argv[3], NULL, 16); + + iim_read(bank, row); + } else + goto err_rtn; + } + } else if (strcmp(argv[1], "blow") == 0) { + if (strcmp(argv[2], "fecmac") == 0) { + if (4 == argc) + iim_blow_func(argv[2], argv[3]); + else + goto err_rtn; + } else { + if (5 == argc) { + bank = simple_strtoul(argv[2], NULL, 16); + row = simple_strtoul(argv[3], NULL, 16); + val = simple_strtoul(argv[4], NULL, 16); + + iim_blow(bank, row, val); + } else + goto err_rtn; + } + } else + goto err_rtn; + + return 0; +err_rtn: + printf("Invalid parameters!\n"); + printf("It is too dangeous for you to use iim command.\n"); + return 1; +} + +U_BOOT_CMD( + iim, 5, 1, do_iimops, + "IIM sub system", + "Warning: all numbers in parameter are in hex format!\n" + "iim read - Read some fuses\n" + "iim read fecmac - Read FEC Mac address\n" + "iim blow - Blow some fuses\n" + "iim blow fecmac <0x##:0x##:0x##:0x##:0x##:0x##>" + "- Blow FEC Mac address"); + diff --git a/common/cmd_mmc.c b/common/cmd_mmc.c index 0e3393b5f4..139b1e8220 100644 --- a/common/cmd_mmc.c +++ b/common/cmd_mmc.c @@ -93,6 +93,33 @@ U_BOOT_CMD( ); #else /* !CONFIG_GENERIC_MMC */ +#ifdef CONFIG_BOOT_PARTITION_ACCESS +#define MMC_PARTITION_SWITCH(mmc, part, enable_boot) \ + do { \ + if (IS_SD(mmc)) { \ + if (part > 1) {\ + printf( \ + "\nError: SD partition can only be 0 or 1\n");\ + return 1; \ + } \ + if (sd_switch_partition(mmc, part) < 0) { \ + if (part > 0) { \ + printf("\nError: Unable to switch SD "\ + "partition\n");\ + return 1; \ + } \ + } \ + } else { \ + if (mmc_switch_partition(mmc, part, enable_boot) \ + < 0) { \ + printf("Error: Fail to switch " \ + "partition to %d\n", part); \ + return 1; \ + } \ + } \ + } while (0) +#endif + static void print_mmcinfo(struct mmc *mmc) { printf("Device: %s\n", mmc->name); @@ -111,7 +138,39 @@ static void print_mmcinfo(struct mmc *mmc) printf("High Capacity: %s\n", mmc->high_capacity ? "Yes" : "No"); printf("Capacity: %lld\n", mmc->capacity); +#ifdef CONFIG_EMMC_DDR_MODE + if (mmc->bus_width == EMMC_MODE_4BIT_DDR || + mmc->bus_width == EMMC_MODE_8BIT_DDR) + printf("Bus Width: %d-bit DDR\n", (mmc->bus_width >> 8)); + else +#endif printf("Bus Width: %d-bit\n", mmc->bus_width); +#ifdef CONFIG_BOOT_PARTITION_ACCESS + if (mmc->boot_size_mult == 0) { + printf("Boot Partition Size: %s\n", "No boot partition available"); + } else { + printf("Boot Partition Size: %5dKB\n", mmc->boot_size_mult * 128); + + printf("Current Partition for boot: "); + switch (mmc->boot_config & EXT_CSD_BOOT_PARTITION_ENABLE_MASK) { + case EXT_CSD_BOOT_PARTITION_DISABLE: + printf("Not bootable\n"); + break; + case EXT_CSD_BOOT_PARTITION_PART1: + printf("Boot partition 1\n"); + break; + case EXT_CSD_BOOT_PARTITION_PART2: + printf("Boot partition 2\n"); + break; + case EXT_CSD_BOOT_PARTITION_USER: + printf("User area\n"); + break; + default: + printf("Unknown\n"); + break; + } + } +#endif } int do_mmcinfo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) @@ -127,22 +186,26 @@ int do_mmcinfo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) mmc = find_mmc_device(dev_num); if (mmc) { - mmc_init(mmc); - - print_mmcinfo(mmc); + if (mmc_init(mmc)) + puts("MMC card init failed!\n"); + else + print_mmcinfo(mmc); } return 0; } U_BOOT_CMD(mmcinfo, 2, 0, do_mmcinfo, - "mmcinfo -- display MMC info\n", + "mmcinfo -- display MMC info", "" ); int do_mmcops(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { int rc = 0; +#ifdef CONFIG_BOOT_PARTITION_ACCESS + u32 part = 0; +#endif switch (argc) { case 3: @@ -170,6 +233,10 @@ int do_mmcops(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) return 0; } return 1; +#ifdef CONFIG_BOOT_PARTITION_ACCESS + case 7: /* Fall through */ + part = simple_strtoul(argv[6], NULL, 10); +#endif default: /* at least 5 args */ if (strcmp(argv[1], "read") == 0) { int dev = simple_strtoul(argv[2], NULL, 10); @@ -177,16 +244,36 @@ int do_mmcops(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) u32 cnt = simple_strtoul(argv[5], NULL, 16); u32 n; u32 blk = simple_strtoul(argv[4], NULL, 16); + struct mmc *mmc = find_mmc_device(dev); if (!mmc) return 1; - printf("\nMMC read: dev # %d, block # %d, count %d ... ", - dev, blk, cnt); +#ifdef CONFIG_BOOT_PARTITION_ACCESS + printf("\nMMC read: dev # %d, block # %d, " + "count %d partition # %d ... \n", + dev, blk, cnt, part); +#else + printf("\nMMC read: dev # %d, block # %d," + "count %d ... \n", dev, blk, cnt); +#endif mmc_init(mmc); +#ifdef CONFIG_BOOT_PARTITION_ACCESS + if (((mmc->boot_config & + EXT_CSD_BOOT_PARTITION_ACCESS_MASK) != part) + || IS_SD(mmc)) { + /* + * After mmc_init, we now know whether + * this is a eSD/eMMC which support boot + * partition + */ + MMC_PARTITION_SWITCH(mmc, part, 0); + } +#endif + n = mmc->block_dev.block_read(dev, blk, cnt, addr); /* flush cache after read */ @@ -200,6 +287,7 @@ int do_mmcops(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) void *addr = (void *)simple_strtoul(argv[3], NULL, 16); u32 cnt = simple_strtoul(argv[5], NULL, 16); u32 n; + struct mmc *mmc = find_mmc_device(dev); int blk = simple_strtoul(argv[4], NULL, 16); @@ -207,11 +295,30 @@ int do_mmcops(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) if (!mmc) return 1; - printf("\nMMC write: dev # %d, block # %d, count %d ... ", +#ifdef CONFIG_BOOT_PARTITION_ACCESS + printf("\nMMC write: dev # %d, block # %d, " + "count %d, partition # %d ... \n", + dev, blk, cnt, part); +#else + printf("\nMMC write: dev # %d, block # %d, " + "count %d ... \n", dev, blk, cnt); +#endif mmc_init(mmc); +#ifdef CONFIG_BOOT_PARTITION_ACCESS + if (((mmc->boot_config & + EXT_CSD_BOOT_PARTITION_ACCESS_MASK) != part) + || IS_SD(mmc)) { + /* + * After mmc_init, we now know whether this is a + * eSD/eMMC which support boot partition + */ + MMC_PARTITION_SWITCH(mmc, part, 1); + } +#endif + n = mmc->block_dev.block_write(dev, blk, cnt, addr); printf("%d blocks written: %s\n", @@ -226,11 +333,22 @@ int do_mmcops(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) } } +#ifndef CONFIG_BOOT_PARTITION_ACCESS U_BOOT_CMD( mmc, 6, 1, do_mmcops, "MMC sub system", - "read addr blk# cnt\n" + "mmc read addr blk# cnt\n" "mmc write addr blk# cnt\n" "mmc rescan \n" "mmc list - lists available devices"); +#else +U_BOOT_CMD( + mmc, 7, 1, do_mmcops, + "MMC sub system", + "mmc read addr blk# cnt [partition]\n" + "mmc write addr blk# cnt [partition]\n" + "mmc rescan \n" + "mmc list - lists available devices"); +#endif #endif + diff --git a/common/cmd_nvedit.c b/common/cmd_nvedit.c index 2186205a1a..e0ccd56c33 100644 --- a/common/cmd_nvedit.c +++ b/common/cmd_nvedit.c @@ -60,9 +60,9 @@ DECLARE_GLOBAL_DATA_PTR; !defined(CONFIG_ENV_IS_IN_NVRAM) && \ !defined(CONFIG_ENV_IS_IN_ONENAND) && \ !defined(CONFIG_ENV_IS_IN_SPI_FLASH) && \ + !defined(CONFIG_ENV_IS_IN_MMC) && \ !defined(CONFIG_ENV_IS_NOWHERE) -# error Define one of CONFIG_ENV_IS_IN_{EEPROM|FLASH|DATAFLASH|ONENAND|\ -SPI_FLASH|MG_DISK|NVRAM|NOWHERE} +# error Define one of CONFIG_ENV_IS_IN_{NVRAM|EEPROM|FLASH|DATAFLASH|ONENAND|SPI_FLASH|MMC|MG_DISK|NOWHERE} #endif #define XMK_STR(x) #x @@ -556,7 +556,6 @@ int getenv_r (char *name, char *buf, unsigned len) } #if defined(CONFIG_CMD_SAVEENV) && !defined(CONFIG_ENV_IS_NOWHERE) - int do_saveenv (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { extern char * env_name_spec; diff --git a/common/cmd_pata.c b/common/cmd_pata.c new file mode 100644 index 0000000000..d326c1e35f --- /dev/null +++ b/common/cmd_pata.c @@ -0,0 +1,203 @@ +/* + * Copyright (C) 2000-2005, DENX Software Engineering + * Wolfgang Denk + * Copyright (C) Procsys. All rights reserved. + * Mushtaq Khan + * + * (C) Copyright 2008-2009 Freescale Semiconductor, Inc. + * Terry Lv + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include + +int pata_curr_device = -1; +block_dev_desc_t pata_dev_desc[CONFIG_SYS_ATA_MAX_DEVICE]; + +int pata_initialize(void) +{ + int rc; + int i; + + for (i = 0; i < CONFIG_SYS_ATA_MAX_DEVICE; i++) { + memset(&pata_dev_desc[i], 0, sizeof(struct block_dev_desc)); + pata_dev_desc[i].if_type = IF_TYPE_ATAPI; + pata_dev_desc[i].dev = i; + pata_dev_desc[i].part_type = PART_TYPE_UNKNOWN; + pata_dev_desc[i].type = DEV_TYPE_HARDDISK; + pata_dev_desc[i].lba = 0; + pata_dev_desc[i].blksz = 512; + pata_dev_desc[i].block_read = pata_read; + pata_dev_desc[i].block_write = pata_write; + + rc = init_pata(i); + rc = scan_pata(i); + if ((pata_dev_desc[i].lba > 0) && (pata_dev_desc[i].blksz > 0)) + init_part(&pata_dev_desc[i]); + } + pata_curr_device = 0; + return rc; +} + +block_dev_desc_t *pata_get_dev(int dev) +{ + return (dev < CONFIG_SYS_ATA_MAX_DEVICE) ? &pata_dev_desc[dev] : NULL; +} + +int do_pata(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + int rc = 0; + + if (argc == 2 && strcmp(argv[1], "init") == 0) + return pata_initialize(); + + /* If the user has not yet run `pata init`, do it now */ + if (pata_curr_device == -1) + if (pata_initialize()) + return 1; + + switch (argc) { + case 0: + case 1: + printf("Usage:\n%s\n", cmdtp->usage); + return 1; + case 2: + if (strncmp(argv[1], "inf", 3) == 0) { + int i; + putc('\n'); + for (i = 0; i < CONFIG_SYS_ATA_MAX_DEVICE; ++i) { + if (pata_dev_desc[i].type == DEV_TYPE_UNKNOWN) + continue; + printf("PATA device %d: ", i); + dev_print(&pata_dev_desc[i]); + } + return 0; + } else if (strncmp(argv[1], "dev", 3) == 0) { + if ((pata_curr_device < 0) || \ + (pata_curr_device >= CONFIG_SYS_ATA_MAX_DEVICE)) { + puts("\nno PATA devices available\n"); + return 1; + } + printf("\nPATA device %d: ", pata_curr_device); + dev_print(&pata_dev_desc[pata_curr_device]); + return 0; + } else if (strncmp(argv[1], "part", 4) == 0) { + int dev, ok; + + for (ok = 0, dev = 0; dev < CONFIG_SYS_ATA_MAX_DEVICE; ++dev) { + if (pata_dev_desc[dev].part_type != PART_TYPE_UNKNOWN) { + ++ok; + if (dev) + putc('\n'); + print_part(&pata_dev_desc[dev]); + } + } + if (!ok) { + puts("\nno PATA devices available\n"); + rc++; + } + return rc; + } + printf("Usage:\n%s\n", cmdtp->usage); + return 1; + case 3: + if (strncmp(argv[1], "dev", 3) == 0) { + int dev = (int)simple_strtoul(argv[2], NULL, 10); + + printf("\nPATA device %d: ", dev); + if (dev >= CONFIG_SYS_ATA_MAX_DEVICE) { + puts("unknown device\n"); + return 1; + } + dev_print(&pata_dev_desc[dev]); + + if (pata_dev_desc[dev].type == DEV_TYPE_UNKNOWN) + return 1; + + pata_curr_device = dev; + + puts("... is now current device\n"); + + return 0; + } else if (strncmp(argv[1], "part", 4) == 0) { + int dev = (int)simple_strtoul(argv[2], NULL, 10); + + if (pata_dev_desc[dev].part_type != PART_TYPE_UNKNOWN) { + print_part(&pata_dev_desc[dev]); + } else { + printf("\nPATA device %d not available\n", dev); + rc = 1; + } + return rc; + } + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + + default: /* at least 4 args */ + if (strcmp(argv[1], "read") == 0) { + ulong addr = simple_strtoul(argv[2], NULL, 16); + ulong cnt = simple_strtoul(argv[4], NULL, 16); + ulong n; + lbaint_t blk = simple_strtoul(argv[3], NULL, 16); + + printf("\nPATA read: device %d block # %ld, count %ld ... ", + pata_curr_device, blk, cnt); + + n = pata_read(pata_curr_device, blk, cnt, (u32 *)addr); + + /* flush cache after read */ + flush_cache(addr, cnt * pata_dev_desc[pata_curr_device].blksz); + + printf("%ld blocks read: %s\n", + n, (n == cnt) ? "OK" : "ERROR"); + return (n == cnt) ? 0 : 1; + } else if (strcmp(argv[1], "write") == 0) { + ulong addr = simple_strtoul(argv[2], NULL, 16); + ulong cnt = simple_strtoul(argv[4], NULL, 16); + ulong n; + + lbaint_t blk = simple_strtoul(argv[3], NULL, 16); + + printf("\nPATA write: device %d block # %ld, count %ld ... ", + pata_curr_device, blk, cnt); + + n = pata_write(pata_curr_device, blk, cnt, (u32 *)addr); + + printf("%ld blocks written: %s\n", + n, (n == cnt) ? "OK" : "ERROR"); + return (n == cnt) ? 0 : 1; + } else { + printf("Usage:\n%s\n", cmdtp->usage); + rc = 1; + } + + return rc; + } +} + +U_BOOT_CMD( + pata, 5, 1, do_pata, + "pata - PATA sub system\n", + "pata info - show available PATA devices\n" + "pata device [dev] - show or set current device\n" + "pata part [dev] - print partition table\n" + "pata read addr blk# cnt\n" + "pata write addr blk# cnt\n"); diff --git a/common/cmd_sata.c b/common/cmd_sata.c index 1693a7e312..cd21f2a990 100644 --- a/common/cmd_sata.c +++ b/common/cmd_sata.c @@ -1,4 +1,7 @@ /* + * (C) Copyright 2008-2010 Freescale Semiconductor, Inc. + * Terry Lv + * * Copyright (C) 2000-2005, DENX Software Engineering * Wolfgang Denk * Copyright (C) Procsys. All rights reserved. @@ -48,9 +51,12 @@ int __sata_initialize(void) sata_dev_desc[i].block_write = sata_write; rc = init_sata(i); - rc = scan_sata(i); - if ((sata_dev_desc[i].lba > 0) && (sata_dev_desc[i].blksz > 0)) - init_part(&sata_dev_desc[i]); + if (!rc) { + rc = scan_sata(i); + if ((sata_dev_desc[i].lba > 0) && + (sata_dev_desc[i].blksz > 0)) + init_part(&sata_dev_desc[i]); + } } sata_curr_device = 0; return rc; diff --git a/common/env_common.c b/common/env_common.c index be64d1307b..eb0b37446e 100644 --- a/common/env_common.c +++ b/common/env_common.c @@ -139,6 +139,12 @@ uchar default_environment[] = { "\0" }; +#if defined(CONFIG_ENV_IS_IN_NAND) /* Environment is in Nand Flash */ \ + || defined(CONFIG_ENV_IS_IN_SPI_FLASH) \ + || defined(CONFIG_ENV_IS_IN_MMC) +int default_environment_size = sizeof(default_environment); +#endif + void env_crc_update (void) { env_ptr->crc = crc32(0, env_ptr->data, ENV_SIZE); diff --git a/common/env_mmc.c b/common/env_mmc.c new file mode 100644 index 0000000000..9ee90625ba --- /dev/null +++ b/common/env_mmc.c @@ -0,0 +1,162 @@ +/* + * (C) Copyright 2008-2010 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* #define DEBUG */ + +#include + +#include +#include +#include +#include +#include + +/* references to names in env_common.c */ +extern uchar default_environment[]; + +char *env_name_spec = "MMC"; + +#ifdef ENV_IS_EMBEDDED +extern uchar environment[]; +env_t *env_ptr = (env_t *)(&environment[0]); +#else /* ! ENV_IS_EMBEDDED */ +env_t *env_ptr; +#endif /* ENV_IS_EMBEDDED */ + +static int mmc_env_devno; + +/* local functions */ +#if !defined(ENV_IS_EMBEDDED) +static void use_default(void); +#endif + +DECLARE_GLOBAL_DATA_PTR; + +uchar env_get_char_spec(int index) +{ + return *((uchar *)(gd->env_addr + index)); +} + +int env_init(void) +{ + /* use default */ + gd->env_addr = (ulong)&default_environment[0]; + gd->env_valid = 1; + +#ifdef CONFIG_DYNAMIC_MMC_DEVNO + mmc_env_devno = get_mmc_env_devno(); +#else + mmc_env_devno = CONFIG_SYS_MMC_ENV_DEV; +#endif + + return 0; +} + +int init_mmc_for_env(struct mmc *mmc) +{ + if (!mmc) { + puts("No MMC card found\n"); + return -1; + } + + if (mmc_init(mmc)) { + puts("MMC init failed\n"); + return -1; + } + + return 0; +} + +#ifdef CONFIG_CMD_SAVEENV + +inline int write_env(struct mmc *mmc, unsigned long size, + unsigned long offset, const void *buffer) +{ + uint blk_start, blk_cnt, n; + + blk_start = ALIGN(offset, mmc->write_bl_len) / mmc->write_bl_len; + blk_cnt = ALIGN(size, mmc->write_bl_len) / mmc->write_bl_len; + + n = mmc->block_dev.block_write(mmc_env_devno, blk_start, + blk_cnt, (u_char *)buffer); + + return (n == blk_cnt) ? 0 : -1; +} + +int saveenv(void) +{ + struct mmc *mmc = find_mmc_device(mmc_env_devno); + + if (init_mmc_for_env(mmc)) + return 1; + + printf("Writing to MMC(%d)... ", mmc_env_devno); + if (write_env(mmc, CONFIG_ENV_SIZE, CONFIG_ENV_OFFSET, env_ptr)) { + puts("failed\n"); + return 1; + } + + puts("done\n"); + return 0; +} +#endif /* CONFIG_CMD_SAVEENV */ + +inline int read_env(struct mmc *mmc, unsigned long size, + unsigned long offset, const void *buffer) +{ + uint blk_start, blk_cnt, n; + + blk_start = ALIGN(offset, mmc->read_bl_len) / mmc->read_bl_len; + blk_cnt = ALIGN(size, mmc->read_bl_len) / mmc->read_bl_len; + + n = mmc->block_dev.block_read(mmc_env_devno, blk_start, + blk_cnt, (uchar *)buffer); + + return (n == blk_cnt) ? 0 : -1; +} + +void env_relocate_spec(void) +{ +#if !defined(ENV_IS_EMBEDDED) + struct mmc *mmc = find_mmc_device(mmc_env_devno); + + if (init_mmc_for_env(mmc)) + return; + + if (read_env(mmc, CONFIG_ENV_SIZE, CONFIG_ENV_OFFSET, env_ptr)) + return use_default(); + + if (crc32(0, env_ptr->data, ENV_SIZE) != env_ptr->crc) + return use_default(); + + gd->env_valid = 1; +#endif +} + +#if !defined(ENV_IS_EMBEDDED) +static void use_default() +{ + puts ("*** Warning - bad CRC or MMC, using default environment\n\n"); + set_default_env(); +} +#endif + diff --git a/common/lcd.c b/common/lcd.c index dc8fea6694..85969ff568 100644 --- a/common/lcd.c +++ b/common/lcd.c @@ -477,7 +477,7 @@ ulong lcd_setmem (ulong addr) static void lcd_setfgcolor (int color) { -#ifdef CONFIG_ATMEL_LCD +#if defined(CONFIG_ATMEL_LCD) || defined(CONFIG_MXC2_LCD) lcd_color_fg = color; #else lcd_color_fg = color & 0x0F; @@ -488,7 +488,7 @@ static void lcd_setfgcolor (int color) static void lcd_setbgcolor (int color) { -#ifdef CONFIG_ATMEL_LCD +#if defined(CONFIG_ATMEL_LCD) || defined(CONFIG_MXC2_LCD) lcd_color_bg = color; #else lcd_color_bg = color & 0x0F; @@ -649,14 +649,20 @@ int lcd_display_bitmap(ulong bmp_image, int x, int y) bpix = NBITS(panel_info.vl_bpix); - if ((bpix != 1) && (bpix != 8) && (bpix != 16)) { + if ((bpix != 1) && (bpix != 8) && (bpix != 16) && (bpix != 24)) { printf ("Error: %d bit/pixel mode, but BMP has %d bit/pixel\n", bpix, bmp_bpix); return 1; } +#if defined(CONFIG_BMP_24BPP) + /* We support displaying 24bpp BMPs on 16bpp LCDs */ + if (bpix != bmp_bpix && (bmp_bpix != 24 || bpix != 16) && + (bmp_bpix != 8 || bpix != 16)) { +#else /* We support displaying 8bpp BMPs on 16bpp LCDs */ if (bpix != bmp_bpix && (bmp_bpix != 8 || bpix != 16)) { +#endif printf ("Error: %d bit/pixel mode, but BMP has %d bit/pixel\n", bpix, le16_to_cpu(bmp->header.bit_count)); @@ -676,7 +682,6 @@ int lcd_display_bitmap(ulong bmp_image, int x, int y) #elif !defined(CONFIG_ATMEL_LCD) cmap = panel_info.cmap; #endif - cmap_base = cmap; /* Set color map */ @@ -705,12 +710,12 @@ int lcd_display_bitmap(ulong bmp_image, int x, int y) #endif /* - * BMP format for Monochrome assumes that the state of a + * BMP format for Monochrome assumes that the state of a * pixel is described on a per Bit basis, not per Byte. - * So, in case of Monochrome BMP we should align widths + * So, in case of Monochrome BMP we should align widths * on a byte boundary and convert them from Bit to Byte * units. - * Probably, PXA250 and MPC823 process 1bpp BMP images in + * Probably, PXA250 and MPC823 process 1bpp BMP images in * their own ways, so make the converting to be MCC200 * specific. */ @@ -722,9 +727,7 @@ int lcd_display_bitmap(ulong bmp_image, int x, int y) pwidth= ((pwidth + 7) & ~7) >> 3; } #endif - padded_line = (width&0x3) ? ((width&~0x3)+4) : (width); - #ifdef CONFIG_SPLASH_SCREEN_ALIGN if (x == BMP_ALIGN_CENTER) x = max(0, (pwidth - width) / 2); @@ -743,8 +746,7 @@ int lcd_display_bitmap(ulong bmp_image, int x, int y) height = panel_info.vl_row - y; bmap = (uchar *)bmp + le32_to_cpu (bmp->header.data_offset); - fb = (uchar *) (lcd_base + - (y + height - 1) * lcd_line_length + x); + fb = (uchar *) (lcd_base + (y + height - 1) * lcd_line_length + x); switch (bmp_bpix) { case 1: /* pass through */ @@ -794,7 +796,28 @@ int lcd_display_bitmap(ulong bmp_image, int x, int y) } break; #endif /* CONFIG_BMP_16BPP */ - +#if defined(CONFIG_BMP_24BPP) + case 24: + if (bpix != 16) { + printf("Error: %d bit/pixel mode," + "but BMP has %d bit/pixel\n", + bpix, bmp_bpix); + break; + } + for (i = 0; i < height; ++i) { + WATCHDOG_RESET(); + for (j = 0; j < width; j++) { + *(uint16_t *)fb = ((*(bmap + 2) << 8) & 0xf800) + | ((*(bmap + 1) << 3) & 0x07e0) + | ((*(bmap) >> 3) & 0x001f); + bmap += 3; + fb += sizeof(uint16_t) / sizeof(*fb); + } + bmap += (width - padded_line); + fb -= ((2*width) + lcd_line_length); + } + break; +#endif /* CONFIG_BMP_24BPP */ default: break; }; @@ -815,6 +838,7 @@ static void *lcd_logo (void) do_splash = 0; addr = simple_strtoul (s, NULL, 16); + #ifdef CONFIG_SPLASH_SCREEN_ALIGN if ((s = getenv ("splashpos")) != NULL) { if (s[0] == 'm') diff --git a/common/main.c b/common/main.c index 026edd1db2..d479660aa6 100644 --- a/common/main.c +++ b/common/main.c @@ -596,7 +596,7 @@ static char* hist_prev(void) } else ret = hist_list[hist_cur]; - return (ret); + return ret; } static char* hist_next(void) @@ -617,7 +617,7 @@ static char* hist_next(void) } else ret = hist_list[hist_cur]; - return (ret); + return ret; } #ifndef CONFIG_CMDLINE_EDITING @@ -728,9 +728,10 @@ static int cread_line(const char *const prompt, char *buf, unsigned int *len) #ifdef CONFIG_BOOT_RETRY_TIME while (!tstc()) { /* while no incoming data */ if (retry_time >= 0 && get_ticks() > endtime) - return (-2); /* timed out */ + return -2; /* timed out */ } #endif + WATCHDOG_RESET(); /* Trigger watchdog, if needed */ ichar = getcmd_getch(); @@ -802,7 +803,7 @@ static int cread_line(const char *const prompt, char *buf, unsigned int *len) break; case CTL_CH('c'): /* ^C - break */ *buf = '\0'; /* discard input */ - return (-1); + return -1; case CTL_CH('f'): if (num < eol_num) { getcmd_putch(buf[num]); @@ -923,7 +924,7 @@ static int cread_line(const char *const prompt, char *buf, unsigned int *len) cread_add_to_hist(buf); hist_cur = hist_add_idx; - return (rc); + return rc; } #endif /* CONFIG_CMDLINE_EDITING */ @@ -988,7 +989,7 @@ int readline_into_buffer (const char *const prompt, char * buffer) #ifdef CONFIG_BOOT_RETRY_TIME while (!tstc()) { /* while no incoming data */ if (retry_time >= 0 && get_ticks() > endtime) - return (-2); /* timed out */ + return -2; /* timed out */ } #endif WATCHDOG_RESET(); /* Trigger watchdog, if needed */ @@ -1009,14 +1010,14 @@ int readline_into_buffer (const char *const prompt, char * buffer) case '\n': *p = '\0'; puts ("\r\n"); - return (p - p_buf); + return p - p_buf; case '\0': /* nul */ continue; case 0x03: /* ^C - break */ p_buf[0] = '\0'; /* discard input */ - return (-1); + return -1; case 0x15: /* ^U - erase line */ while (col > plen) { @@ -1078,7 +1079,7 @@ static char * delete_char (char *buffer, char *p, int *colp, int *np, int plen) char *s; if (*np == 0) { - return (p); + return p; } if (*(--p) == '\t') { /* will retype the whole line */ @@ -1088,8 +1089,8 @@ static char * delete_char (char *buffer, char *p, int *colp, int *np, int plen) } for (s=buffer; s * + * (C) Copyright 2008-2010 Freescale Semiconductor, Inc. + * * See file CREDITS for list of people who contributed to this * project. * @@ -34,8 +36,65 @@ #include #include #include +#include +#include -static void cache_flush(void); +#define dcache_invalidate_all_l1() \ +{ \ + int i = 0; \ + /* Clean and Invalidate Entire Data Cache */ \ + asm volatile ("mcr p15, 0, %0, c7, c14, 0;" \ + : \ + : "r"(i) \ + : "memory"); \ + asm volatile ("mcr p15, 0, %0, c8, c7, 0;" \ + : \ + : "r"(i) \ + : "memory"); /* Invalidate i+d-TLBs */ \ +} + +#define dcache_disable_l1() \ +{ \ + int i = 0; \ + asm volatile ("mcr p15, 0, %0, c7, c6, 0;" \ + : \ + : "r"(i)); /* clear data cache */ \ + asm volatile ("mrc p15, 0, %0, c1, c0, 0;" \ + : "=r"(i)); \ + i &= (~0x0004); /* disable DCache */ \ + /* but not MMU and alignment faults */ \ + asm volatile ("mcr p15, 0, %0, c1, c0, 0;" \ + : \ + : "r"(i)); \ +} + +#define icache_invalidate_all_l1() \ +{ \ + /* this macro can discard dirty cache lines (N/A for ICache) */ \ + int i = 0; \ + asm volatile ("mcr p15, 0, %0, c7, c5, 0;" \ + : \ + : "r"(i)); /* flush ICache */ \ + asm volatile ("mcr p15, 0, %0, c8, c5, 0;" \ + : \ + : "r"(i)); /* flush ITLB only */ \ + asm volatile ("mcr p15, 0, %0, c7, c5, 4;" \ + : \ + : "r"(i)); /* flush prefetch buffer */ \ + asm ( \ + "nop;" /* next few instructions may be via cache */ \ + "nop;" \ + "nop;" \ + "nop;" \ + "nop;" \ + "nop;"); \ +} + +#define cache_flush() \ +{ \ + dcache_invalidate_all_l1(); \ + icache_invalidate_all_l1(); \ +} int cleanup_before_linux (void) { @@ -57,20 +116,20 @@ int cleanup_before_linux (void) lcd_panel_disable(); } #endif + /* flush I/D-cache */ + cache_flush(); /* turn off I/D-cache */ icache_disable(); dcache_disable(); - /* flush I/D-cache */ - cache_flush(); + /* MMU Off */ + MMU_OFF(); + +/*Workaround to enable L2CC during kernel decompressing*/ +#ifdef fixup_before_linux + fixup_before_linux; +#endif return 0; } -static void cache_flush(void) -{ - unsigned long i = 0; - - asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (i)); /* invalidate both caches and flush btb */ - asm ("mcr p15, 0, %0, c7, c10, 4": :"r" (i)); /* mem barrier to sync things */ -} diff --git a/cpu/arm1136/mx31/Makefile b/cpu/arm1136/mx31/Makefile index c8e18f7f02..41eb2d497e 100644 --- a/cpu/arm1136/mx31/Makefile +++ b/cpu/arm1136/mx31/Makefile @@ -29,6 +29,8 @@ COBJS += generic.o COBJS += timer.o COBJS += devices.o +SOBJS = nand_load.o + SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) diff --git a/cpu/arm1136/mx31/generic.c b/cpu/arm1136/mx31/generic.c index 1415d6c2ae..67c0cc64c3 100644 --- a/cpu/arm1136/mx31/generic.c +++ b/cpu/arm1136/mx31/generic.c @@ -95,6 +95,7 @@ int print_cpuinfo (void) { printf("CPU: Freescale i.MX31 at %d MHz\n", mx31_get_mcu_main_clk() / 1000000); + mx31_dump_clocks(); return 0; } #endif diff --git a/cpu/arm1136/mx31/nand_load.S b/cpu/arm1136/mx31/nand_load.S new file mode 100644 index 0000000000..c0d099a8b2 --- /dev/null +++ b/cpu/arm1136/mx31/nand_load.S @@ -0,0 +1,160 @@ +/* + * Copyright (C) 2008 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +.section ".text.load", "x" + +.macro wait_op_done +1: ldrh r3, [r12, #NAND_FLASH_CONFIG2_REG_OFF] + ands r3, r3, #NAND_FLASH_CONFIG2_INT_DONE + beq 1b +.endm + +data_output: + strh r8, [r12, #RAM_BUFFER_ADDRESS_REG_OFF] + mov r3, #FDO_PAGE_SPARE_VAL + strh r3, [r12, #NAND_FLASH_CONFIG2_REG_OFF] + wait_op_done + bx lr + +send_addr: + strh r3, [r12, #NAND_FLASH_ADD_REG_OFF] + mov r3, #NAND_FLASH_CONFIG2_FADD_EN + strh r3, [r12, #NAND_FLASH_CONFIG2_REG_OFF] + wait_op_done + bx lr + +send_cmd: + strh r3, [r12, #NAND_FLASH_CMD_REG_OFF] + mov r3, #NAND_FLASH_CONFIG2_FCMD_EN + strh r3, [r12, #NAND_FLASH_CONFIG2_REG_OFF] + wait_op_done + bx lr + + +nand_read_page: + + mov r7, lr + + mov r3, #0x0 + /* send command */ + bl send_cmd + /* 5 cycles address input */ + mov r3, #0x0 + bl send_addr + mov r3, #0x0 + bl send_addr + mov r3, r0 + bl send_addr + mov r3, #0x0 + bl send_addr + mov r3, #0x0 + bl send_addr + /* confirm read */ + mov r3, #0x30 + bl send_cmd + /* data output */ + mov r8, #0x0 + mov r4, #0x4 +1: + bl data_output + add r8, r8, #0x01 + cmp r8, r4 + bne 1b + ldrh r3, [r12, #ECC_STATUS_RESULT_REG_OFF] + tst r3, #0x0a + bne . + mov pc, r7 + +.global mxc_nand_load +mxc_nand_load: + + /* Copy image from flash to SDRAM first */ + mov r0, #NFC_BASE_ADDR + add r12, r0, #0xE00 /* register */ + add r2, r0, #0x800 /* 2K */ + ldr r1, __TEXT_BASE + +1: ldmia r0!, {r3-r10} + stmia r1!, {r3-r10} + cmp r0, r2 + blo 1b + /* Jump to SDRAM */ + ldr r1, =0x0FFF + and r0, pc, r1 /* offset of pc */ + ldr r1, __TEXT_BASE + add r1, r1, #0x10 + add pc, r0, r1 + nop + nop + nop + nop + +nand_copy_block: + + /* wait for boot complete */ +4: + ldrh r3, [r12, #NAND_FLASH_CONFIG2_REG_OFF] + tst r3, #0x8000 + beq 4b + + /* unlock buffer and blocks */ + mov r3, #0x02 + strh r3, [r12, #NFC_CONFIGURATION_REG_OFF] + mov r3, #0x0 + strh r3, [r12, #UNLOCK_START_BLK_ADD_REG_OFF] + mov r3, #0x800 + strh r3, [r12, #UNLOCK_END_BLK_ADD_REG_OFF] + mov r3, #0x04 + strh r3, [r12, #NF_WR_PROT_REG_OFF] + mov r3, #0x10 + strh r3, [r12, #NAND_FLASH_CONFIG1_REG_OFF] + + /* read 1 block, 256K */ + mov r0, #0x01 /* page offset */ + ldr r11, __TEXT_BASE + add r11, r11, #0x800 + + mov r1, #NFC_BASE_ADDR + add r2, r1, #0x800 +2: + bl nand_read_page /* r0, r1, r2, r11 has been used */ + /* copy data from internal buffer */ +3: ldmia r1!, {r3-r10} + stmia r11!, {r3-r10} + cmp r1, r2 + blo 3b + + add r0, r0, #0x01 + cmp r0, #0x80 + mov r1, #NFC_BASE_ADDR + bne 2b + + /* set pc to _set_env */ + ldr r11, __TEXT_BASE + ldr r1, =0x7FF + /* correct the lr */ + and r13, r13, r1 + add r13, r13, r11 + mov pc, r13 + +__TEXT_BASE: + .word TEXT_BASE diff --git a/cpu/arm1136/mx35/Makefile b/cpu/arm1136/mx35/Makefile new file mode 100644 index 0000000000..996360f3ab --- /dev/null +++ b/cpu/arm1136/mx35/Makefile @@ -0,0 +1,48 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# (C) Copyright 2008-2009 Freescale Semiconductor, Inc. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(SOC).a + +COBJS = timer.o serial.o generic.o iomux.o +SOBJS = mxc_nand_load.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) + +all: $(obj).depend $(LIB) + +$(LIB): $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/cpu/arm1136/mx35/crm_regs.h b/cpu/arm1136/mx35/crm_regs.h new file mode 100644 index 0000000000..082fdc6641 --- /dev/null +++ b/cpu/arm1136/mx35/crm_regs.h @@ -0,0 +1,258 @@ +/* + * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#ifndef __CPU_ARM1136_MX35_CRM_REGS_H__ +#define __CPU_ARM1136_MX35_CRM_REGS_H__ + +/* Register bit definitions */ +#define MXC_CCM_CCMR_WFI (1 << 30) +#define MXC_CCM_CCMR_STBY_EXIT_SRC (1 << 29) +#define MXC_CCM_CCMR_VSTBY (1 << 28) +#define MXC_CCM_CCMR_WBEN (1 << 27) +#define MXC_CCM_CCMR_VOL_RDY_CNT_OFFSET 20 +#define MXC_CCM_CCMR_VOL_RDY_CNT_MASK (0xF << 20) +#define MXC_CCM_CCMR_ROMW_OFFSET 18 +#define MXC_CCM_CCMR_ROMW_MASK (0x3 << 18) +#define MXC_CCM_CCMR_RAMW_OFFSET 21 +#define MXC_CCM_CCMR_RAMW_MASK (0x3 << 21) +#define MXC_CCM_CCMR_LPM_OFFSET 14 +#define MXC_CCM_CCMR_LPM_MASK (0x3 << 14) +#define MXC_CCM_CCMR_UPE (1 << 9) +#define MXC_CCM_CCMR_MPE (1 << 3) + +#define MXC_CCM_PDR0_PER_SEL (1 << 26) +#define MXC_CCM_PDR0_IPU_HND_BYP (1 << 23) +#define MXC_CCM_PDR0_HSP_PODF_OFFSET 20 +#define MXC_CCM_PDR0_HSP_PODF_MASK (0x3 << 20) +#define MXC_CCM_PDR0_CON_MUX_DIV_OFFSET 16 +#define MXC_CCM_PDR0_CON_MUX_DIV_MASK (0xF << 16) +#define MXC_CCM_PDR0_CKIL_SEL (1 << 15) +#define MXC_CCM_PDR0_PER_PODF_OFFSET 12 +#define MXC_CCM_PDR0_PER_PODF_MASK (0xF << 12) +#define MXC_CCM_PDR0_AUTO_MUX_DIV_OFFSET 9 +#define MXC_CCM_PDR0_AUTO_MUX_DIV_MASK (0x7 << 9) +#define MXC_CCM_PDR0_AUTO_CON 0x1 + +#define MXC_CCM_PDR1_MSHC_PRDF_OFFSET 28 +#define MXC_CCM_PDR1_MSHC_PRDF_MASK (0x7 << 28) +#define MXC_CCM_PDR1_MSHC_PODF_OFFSET 22 +#define MXC_CCM_PDR1_MSHC_PODF_MASK (0x3F << 22) +#define MXC_CCM_PDR1_MSHC_M_U (1 << 7) + +#define MXC_CCM_PDR2_SSI2_PRDF_OFFSET 27 +#define MXC_CCM_PDR2_SSI2_PRDF_MASK (0x7 << 27) +#define MXC_CCM_PDR2_SSI1_PRDF_OFFSET 24 +#define MXC_CCM_PDR2_SSI1_PRDF_MASK (0x7 << 24) +#define MXC_CCM_PDR2_CSI_PRDF_OFFSET 19 +#define MXC_CCM_PDR2_CSI_PRDF_MASK (0x7 << 19) +#define MXC_CCM_PDR2_CSI_PODF_OFFSET 16 +#define MXC_CCM_PDR2_CSI_PODF_MASK (0x7 << 16) +#define MXC_CCM_PDR2_SSI2_PODF_OFFSET 8 +#define MXC_CCM_PDR2_SSI2_PODF_MASK (0x3F << 8) +#define MXC_CCM_PDR2_CSI_M_U (1 << 7) +#define MXC_CCM_PDR2_SSI_M_U (1 << 6) +#define MXC_CCM_PDR2_SSI1_PODF_OFFSET 0 +#define MXC_CCM_PDR2_SSI1_PODF_MASK (0x3F) + +#define MXC_CCM_PDR3_SPDIF_PRDF_OFFSET 29 +#define MXC_CCM_PDR3_SPDIF_PRDF_MASK (0x7 << 29) +#define MXC_CCM_PDR3_SPDIF_PODF_OFFSET 23 +#define MXC_CCM_PDR3_SPDIF_PODF_MASK (0x3F << 23) +#define MXC_CCM_PDR3_SPDIF_M_U (1 << 22) +#define MXC_CCM_PDR3_ESDHC3_PRDF_OFFSET 19 +#define MXC_CCM_PDR3_ESDHC3_PRDF_MASK (0x7 << 19) +#define MXC_CCM_PDR3_ESDHC3_PODF_OFFSET 16 +#define MXC_CCM_PDR3_ESDHC3_PODF_MASK (0x7 << 16) +#define MXC_CCM_PDR3_UART_M_U (1 << 15) +#define MXC_CCM_PDR3_ESDHC2_PRDF_OFFSET 11 +#define MXC_CCM_PDR3_ESDHC2_PRDF_MASK (0x7 << 11) +#define MXC_CCM_PDR3_ESDHC2_PODF_OFFSET 8 +#define MXC_CCM_PDR3_ESDHC2_PODF_MASK (0x7 << 8) +#define MXC_CCM_PDR3_ESDHC_M_U (1 << 6) +#define MXC_CCM_PDR3_ESDHC1_PRDF_OFFSET 3 +#define MXC_CCM_PDR3_ESDHC1_PRDF_MASK (0x7 << 3) +#define MXC_CCM_PDR3_ESDHC1_PODF_OFFSET 0 +#define MXC_CCM_PDR3_ESDHC1_PODF_MASK (0x7) + +#define MXC_CCM_PDR4_NFC_PODF_OFFSET 28 +#define MXC_CCM_PDR4_NFC_PODF_MASK (0xF << 28) +#define MXC_CCM_PDR4_USB_PRDF_OFFSET 25 +#define MXC_CCM_PDR4_USB_PRDF_MASK (0x7 << 25) +#define MXC_CCM_PDR4_USB_PODF_OFFSET 22 +#define MXC_CCM_PDR4_USB_PODF_MASK (0x7 << 22) +#define MXC_CCM_PDR4_PER0_PRDF_OFFSET 19 +#define MXC_CCM_PDR4_PER0_PRDF_MASK (0x7 << 19) +#define MXC_CCM_PDR4_PER0_PODF_OFFSET 16 +#define MXC_CCM_PDR4_PER0_PODF_MASK (0x7 << 16) +#define MXC_CCM_PDR4_UART_PRDF_OFFSET 13 +#define MXC_CCM_PDR4_UART_PRDF_MASK (0x7 << 13) +#define MXC_CCM_PDR4_UART_PODF_OFFSET 10 +#define MXC_CCM_PDR4_UART_PODF_MASK (0x7 << 10) +#define MXC_CCM_PDR4_USB_M_U (1 << 9) + +/* Bit definitions for RCSR */ +#define MXC_CCM_RCSR_BUS_WIDTH (1 << 29) +#define MXC_CCM_RCSR_BUS_16BIT (1 << 29) +#define MXC_CCM_RCSR_PAGE_SIZE (3 << 27) +#define MXC_CCM_RCSR_PAGE_512 (0 << 27) +#define MXC_CCM_RCSR_PAGE_2K (1 << 27) +#define MXC_CCM_RCSR_PAGE_4K1 (2 << 27) +#define MXC_CCM_RCSR_PAGE_4K2 (3 << 27) +#define MXC_CCM_RCSR_SOFT_RESET (1 << 15) +#define MXC_CCM_RCSR_NF16B (1 << 14) +#define MXC_CCM_RCSR_NFC_4K (1 << 9) +#define MXC_CCM_RCSR_NFC_FMS (1 << 8) + +/* Bit definitions for both MCU, PERIPHERAL PLL control registers */ +#define MXC_CCM_PCTL_BRM 0x80000000 +#define MXC_CCM_PCTL_PD_OFFSET 26 +#define MXC_CCM_PCTL_PD_MASK (0xF << 26) +#define MXC_CCM_PCTL_MFD_OFFSET 16 +#define MXC_CCM_PCTL_MFD_MASK (0x3FF << 16) +#define MXC_CCM_PCTL_MFI_OFFSET 10 +#define MXC_CCM_PCTL_MFI_MASK (0xF << 10) +#define MXC_CCM_PCTL_MFN_OFFSET 0 +#define MXC_CCM_PCTL_MFN_MASK 0x3FF + +/* Bit definitions for Audio clock mux register*/ +#define MXC_CCM_ACMR_ESAI_CLK_SEL_OFFSET 12 +#define MXC_CCM_ACMR_ESAI_CLK_SEL_MASK (0xF << 12) +#define MXC_CCM_ACMR_SPDIF_CLK_SEL_OFFSET 8 +#define MXC_CCM_ACMR_SPDIF_CLK_SEL_MASK (0xF << 8) +#define MXC_CCM_ACMR_SSI1_CLK_SEL_OFFSET 4 +#define MXC_CCM_ACMR_SSI1_CLK_SEL_MASK (0xF << 4) +#define MXC_CCM_ACMR_SSI2_CLK_SEL_OFFSET 0 +#define MXC_CCM_ACMR_SSI2_CLK_SEL_MASK (0xF << 0) + +/* Bit definitions for Clock gating Register*/ +#define MXC_CCM_CGR0_ASRC_OFFSET 0 +#define MXC_CCM_CGR0_ASRC_MASK (0x3 << 0) +#define MXC_CCM_CGR0_ATA_OFFSET 2 +#define MXC_CCM_CGR0_ATA_MASK (0x3 << 2) +#define MXC_CCM_CGR0_CAN1_OFFSET 6 +#define MXC_CCM_CGR0_CAN1_MASK (0x3 << 6) +#define MXC_CCM_CGR0_CAN2_OFFSET 8 +#define MXC_CCM_CGR0_CAN2_MASK (0x3 << 8) +#define MXC_CCM_CGR0_CSPI1_OFFSET 10 +#define MXC_CCM_CGR0_CSPI1_MASK (0x3 << 10) +#define MXC_CCM_CGR0_CSPI2_OFFSET 12 +#define MXC_CCM_CGR0_CSPI2_MASK (0x3 << 12) +#define MXC_CCM_CGR0_ECT_OFFSET 14 +#define MXC_CCM_CGR0_ECT_MASK (0x3 << 14) +#define MXC_CCM_CGR0_EMI_OFFSET 18 +#define MXC_CCM_CGR0_EMI_MASK (0x3 << 18) +#define MXC_CCM_CGR0_EPIT1_OFFSET 20 +#define MXC_CCM_CGR0_EPIT1_MASK (0x3 << 20) +#define MXC_CCM_CGR0_EPIT2_OFFSET 22 +#define MXC_CCM_CGR0_EPIT2_MASK (0x3 << 22) +#define MXC_CCM_CGR0_ESAI_OFFSET 24 +#define MXC_CCM_CGR0_ESAI_MASK (0x3 << 24) +#define MXC_CCM_CGR0_ESDHC1_OFFSET 26 +#define MXC_CCM_CGR0_ESDHC1_MASK (0x3 << 26) +#define MXC_CCM_CGR0_ESDHC2_OFFSET 28 +#define MXC_CCM_CGR0_ESDHC2_MASK (0x3 << 28) +#define MXC_CCM_CGR0_ESDHC3_OFFSET 30 +#define MXC_CCM_CGR0_ESDHC3_MASK (0x3 << 30) + +#define MXC_CCM_CGR1_FEC_OFFSET 0 +#define MXC_CCM_CGR1_FEC_MASK (0x3 << 0) +#define MXC_CCM_CGR1_GPIO1_OFFSET 2 +#define MXC_CCM_CGR1_GPIO1_MASK (0x3 << 2) +#define MXC_CCM_CGR1_GPIO2_OFFSET 4 +#define MXC_CCM_CGR1_GPIO2_MASK (0x3 << 4) +#define MXC_CCM_CGR1_GPIO3_OFFSET 6 +#define MXC_CCM_CGR1_GPIO3_MASK (0x3 << 6) +#define MXC_CCM_CGR1_GPT_OFFSET 8 +#define MXC_CCM_CGR1_GPT_MASK (0x3 << 8) +#define MXC_CCM_CGR1_I2C1_OFFSET 10 +#define MXC_CCM_CGR1_I2C1_MASK (0x3 << 10) +#define MXC_CCM_CGR1_I2C2_OFFSET 12 +#define MXC_CCM_CGR1_I2C2_MASK (0x3 << 12) +#define MXC_CCM_CGR1_I2C3_OFFSET 14 +#define MXC_CCM_CGR1_I2C3_MASK (0x3 << 14) +#define MXC_CCM_CGR1_IOMUXC_OFFSET 16 +#define MXC_CCM_CGR1_IOMUXC_MASK (0x3 << 16) +#define MXC_CCM_CGR1_IPU_OFFSET 18 +#define MXC_CCM_CGR1_IPU_MASK (0x3 << 18) +#define MXC_CCM_CGR1_KPP_OFFSET 20 +#define MXC_CCM_CGR1_KPP_MASK (0x3 << 20) +#define MXC_CCM_CGR1_MLB_OFFSET 22 +#define MXC_CCM_CGR1_MLB_MASK (0x3 << 22) +#define MXC_CCM_CGR1_MSHC_OFFSET 24 +#define MXC_CCM_CGR1_MSHC_MASK (0x3 << 24) +#define MXC_CCM_CGR1_OWIRE_OFFSET 26 +#define MXC_CCM_CGR1_OWIRE_MASK (0x3 << 26) +#define MXC_CCM_CGR1_PWM_OFFSET 28 +#define MXC_CCM_CGR1_PWM_MASK (0x3 << 28) +#define MXC_CCM_CGR1_RNGC_OFFSET 30 +#define MXC_CCM_CGR1_RNGC_MASK (0x3 << 30) + +#define MXC_CCM_CGR2_RTC_OFFSET 0 +#define MXC_CCM_CGR2_RTC_MASK (0x3 << 0) +#define MXC_CCM_CGR2_RTIC_OFFSET 2 +#define MXC_CCM_CGR2_RTIC_MASK (0x3 << 2) +#define MXC_CCM_CGR2_SCC_OFFSET 4 +#define MXC_CCM_CGR2_SCC_MASK (0x3 << 4) +#define MXC_CCM_CGR2_SDMA_OFFSET 6 +#define MXC_CCM_CGR2_SDMA_MASK (0x3 << 6) +#define MXC_CCM_CGR2_SPBA_OFFSET 8 +#define MXC_CCM_CGR2_SPBA_MASK (0x3 << 8) +#define MXC_CCM_CGR2_SPDIF_OFFSET 10 +#define MXC_CCM_CGR2_SPDIF_MASK (0x3 << 10) +#define MXC_CCM_CGR2_SSI1_OFFSET 12 +#define MXC_CCM_CGR2_SSI1_MASK (0x3 << 12) +#define MXC_CCM_CGR2_SSI2_OFFSET 14 +#define MXC_CCM_CGR2_SSI2_MASK (0x3 << 14) +#define MXC_CCM_CGR2_UART1_OFFSET 16 +#define MXC_CCM_CGR2_UART1_MASK (0x3 << 16) +#define MXC_CCM_CGR2_UART2_OFFSET 18 +#define MXC_CCM_CGR2_UART2_MASK (0x3 << 18) +#define MXC_CCM_CGR2_UART3_OFFSET 20 +#define MXC_CCM_CGR2_UART3_MASK (0x3 << 20) +#define MXC_CCM_CGR2_USBOTG_OFFSET 22 +#define MXC_CCM_CGR2_USBOTG_MASK (0x3 << 22) +#define MXC_CCM_CGR2_WDOG_OFFSET 24 +#define MXC_CCM_CGR2_WDOG_MASK (0x3 << 24) +#define MXC_CCM_CGR2_MAX_OFFSET 26 +#define MXC_CCM_CGR2_MAX_MASK (0x3 << 26) +#define MXC_CCM_CGR2_MAX_ENABLE (0x2 << 26) +#define MXC_CCM_CGR2_AUDMUX_OFFSET 30 +#define MXC_CCM_CGR2_AUDMUX_MASK (0x3 << 30) + +#define MXC_CCM_CGR3_CSI_OFFSET 0 +#define MXC_CCM_CGR3_CSI_MASK (0x3 << 0) +#define MXC_CCM_CGR3_IIM_OFFSET 2 +#define MXC_CCM_CGR3_IIM_MASK (0x3 << 2) +#define MXC_CCM_CGR3_GPU2D_OFFSET 4 +#define MXC_CCM_CGR3_GPU2D_MASK (0x3 << 4) + +#define MXC_CCM_COSR_CLKOSEL_MASK 0x1F +#define MXC_CCM_COSR_CLKOSEL_OFFSET 0 +#define MXC_CCM_COSR_CLKOEN (1 << 5) +#define MXC_CCM_COSR_CLKOUTDIV_1 (1 << 6) +#define MXC_CCM_COSR_CLKOUT_PREDIV_MASK (0x7 << 10) +#define MXC_CCM_COSR_CLKOUT_PREDIV_OFFSET 10 +#define MXC_CCM_COSR_CLKOUT_PRODIV_MASK (0x7 << 13) +#define MXC_CCM_COSR_CLKOUT_PRODIV_OFFSET 13 +#define MXC_CCM_COSR_SSI1_RX_SRC_SEL_MASK (0x3 << 16) +#define MXC_CCM_COSR_SSI1_RX_SRC_SEL_OFFSET 16 +#define MXC_CCM_COSR_SSI1_TX_SRC_SEL_MASK (0x3 << 18) +#define MXC_CCM_COSR_SSI1_TX_SRC_SEL_OFFSET 18 +#define MXC_CCM_COSR_SSI2_RX_SRC_SEL_MASK (0x3 << 20) +#define MXC_CCM_COSR_SSI2_RX_SRC_SEL_OFFSET 20 +#define MXC_CCM_COSR_SSI2_TX_SRC_SEL_MASK (0x3 << 22) +#define MXC_CCM_COSR_SSI2_TX_SRC_SEL_OFFSET 22 +#define MXC_CCM_COSR_ASRC_AUDIO_EN (1 << 24) +#define MXC_CCM_COSR_ASRC_AUDIO_PODF_MASK (0x3F << 26) +#define MXC_CCM_COSR_ASRC_AUDIO_PODF_OFFSET 26 + +#endif /* __CPU_ARM1136_MX35_CRM_REGS_H__ */ diff --git a/cpu/arm1136/mx35/generic.c b/cpu/arm1136/mx35/generic.c new file mode 100644 index 0000000000..1b4825a264 --- /dev/null +++ b/cpu/arm1136/mx35/generic.c @@ -0,0 +1,388 @@ +/* + * (C) Copyright 2007 + * Sascha Hauer, Pengutronix + * + * (C) Copyright 2008-2010 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include "crm_regs.h" + +#define CLK_CODE(arm, ahb, sel) (((arm) << 16) + ((ahb) << 8) + (sel)) +#define CLK_CODE_ARM(c) (((c) >> 16) & 0xFF) +#define CLK_CODE_AHB(c) (((c) >> 8) & 0xFF) +#define CLK_CODE_PATH(c) ((c) & 0xFF) + +#define CCM_GET_DIVIDER(x, m, o) (((x) & (m)) >> (o)) + +static int g_clk_mux_auto[8] = { + CLK_CODE(1, 3, 0), CLK_CODE(1, 2, 1), CLK_CODE(2, 1, 1), -1, + CLK_CODE(1, 6, 0), CLK_CODE(1, 4, 1), CLK_CODE(2, 2, 1), -1, +}; + +static int g_clk_mux_consumer[16] = { + CLK_CODE(1, 4, 0), CLK_CODE(1, 3, 1), CLK_CODE(1, 3, 1), -1, + -1, -1, CLK_CODE(4, 1, 0), CLK_CODE(1, 5, 0), + CLK_CODE(1, 8, 1), CLK_CODE(1, 6, 1), CLK_CODE(2, 4, 0), -1, + -1, -1, CLK_CODE(4, 2, 0), -1, +}; + +static int hsp_div_table[3][16] = { + {4, 3, 2, -1, -1, -1, 1, 5, 4, 3, 2, -1, -1, -1, 1, -1}, + {-1, -1, -1, -1, -1, -1, -1, -1, 8, 6, 4, -1, -1, -1, 2, -1}, + {3, -1, -1, -1, -1, -1, -1, -1, 3, -1, -1, -1, -1, -1, -1, -1}, +}; + +static u32 __get_arm_div(u32 pdr0, u32 *fi, u32 *fd) +{ + int *pclk_mux; + if (pdr0 & MXC_CCM_PDR0_AUTO_CON) { + pclk_mux = g_clk_mux_consumer + + ((pdr0 & MXC_CCM_PDR0_CON_MUX_DIV_MASK) >> + MXC_CCM_PDR0_CON_MUX_DIV_OFFSET); + } else { + pclk_mux = g_clk_mux_auto + + ((pdr0 & MXC_CCM_PDR0_AUTO_MUX_DIV_MASK) >> + MXC_CCM_PDR0_AUTO_MUX_DIV_OFFSET); + } + + if ((*pclk_mux) == -1) + return -1; + + if (fi && fd) { + if (!CLK_CODE_PATH(*pclk_mux)) { + *fi = *fd = 1; + return CLK_CODE_ARM(*pclk_mux); + } + if (pdr0 & MXC_CCM_PDR0_AUTO_CON) { + *fi = 3; + *fd = 4; + } else { + *fi = 2; + *fd = 3; + } + } + return CLK_CODE_ARM(*pclk_mux); +} + +static int __get_ahb_div(u32 pdr0) +{ + int *pclk_mux; + + pclk_mux = g_clk_mux_consumer + + ((pdr0 & MXC_CCM_PDR0_CON_MUX_DIV_MASK) >> + MXC_CCM_PDR0_CON_MUX_DIV_OFFSET); + + if ((*pclk_mux) == -1) + return -1; + + return CLK_CODE_AHB(*pclk_mux); +} + +static u32 __decode_pll(u32 reg, u32 infreq) +{ + u32 mfi = (reg >> 10) & 0xf; + u32 mfn = reg & 0x3f; + u32 mfd = (reg >> 16) & 0x3f; + u32 pd = (reg >> 26) & 0xf; + + mfi = mfi <= 5 ? 5 : mfi; + mfd += 1; + pd += 1; + + return ((2 * (infreq / 1000) * (mfi * mfd + mfn)) / (mfd * pd)) * 1000; +} + +static u32 __get_mcu_main_clk(void) +{ + u32 arm_div = 0, fi = 0, fd = 0; + arm_div = __get_arm_div(__REG(CCM_BASE_ADDR + CLKCTL_PDR0), &fi, &fd); + fi *= + __decode_pll(__REG(MCU_PLL), + CONFIG_MX35_HCLK_FREQ); + return fi / (arm_div * fd); +} + +static u32 __get_ipg_clk(void) +{ + u32 freq = __get_mcu_main_clk(); + u32 pdr0 = __REG(CCM_BASE_ADDR + CLKCTL_PDR0); + + return freq / (__get_ahb_div(pdr0) * 2); +} + +static u32 __get_ipg_per_clk(void) +{ + u32 freq = __get_mcu_main_clk(); + u32 pdr0 = __REG(CCM_BASE_ADDR + CLKCTL_PDR0); + u32 pdr4 = __REG(CCM_BASE_ADDR + CLKCTL_PDR4); + u32 div; + if (pdr0 & MXC_CCM_PDR0_PER_SEL) { + div = (CCM_GET_DIVIDER(pdr4, + MXC_CCM_PDR4_PER0_PRDF_MASK, + MXC_CCM_PDR4_PER0_PODF_OFFSET) + 1) * + (CCM_GET_DIVIDER(pdr4, + MXC_CCM_PDR4_PER0_PODF_MASK, + MXC_CCM_PDR4_PER0_PODF_OFFSET) + 1); + } else { + div = CCM_GET_DIVIDER(pdr0, + MXC_CCM_PDR0_PER_PODF_MASK, + MXC_CCM_PDR0_PER_PODF_OFFSET) + 1; + freq /= __get_ahb_div(pdr0); + } + return freq / div; +} + +static u32 __get_uart_clk(void) +{ + u32 freq; + u32 pdr4 = __REG(CCM_BASE_ADDR + CLKCTL_PDR4); + + if (__REG(CCM_BASE_ADDR + CLKCTL_PDR3) & MXC_CCM_PDR3_UART_M_U) + freq = __get_mcu_main_clk(); + else + freq = __decode_pll(__REG(PER_PLL), + CONFIG_MX35_HCLK_FREQ); + freq /= ((CCM_GET_DIVIDER(pdr4, + MXC_CCM_PDR4_UART_PRDF_MASK, + MXC_CCM_PDR4_UART_PRDF_OFFSET) + 1) * + (CCM_GET_DIVIDER(pdr4, + MXC_CCM_PDR4_UART_PODF_MASK, + MXC_CCM_PDR4_UART_PODF_OFFSET) + 1)); + return freq; +} + +unsigned int mxc_get_main_clock(enum mxc_main_clocks clk) +{ + u32 nfc_pdf, hsp_podf; + u32 pll, ret_val = 0, usb_prdf, usb_podf; + + u32 reg = readl(CCM_BASE_ADDR + CLKCTL_PDR0); + u32 reg4 = readl(CCM_BASE_ADDR + CLKCTL_PDR4); + + reg |= 0x1; + + switch (clk) { + case CPU_CLK: + ret_val = __get_mcu_main_clk(); + break; + case AHB_CLK: + ret_val = __get_mcu_main_clk(); + break; + case HSP_CLK: + if (reg & CLKMODE_CONSUMER) { + hsp_podf = (reg >> 20) & 0x3; + pll = __get_mcu_main_clk(); + hsp_podf = hsp_div_table[hsp_podf][(reg>>16)&0xF]; + if(hsp_podf > 0 ) { + ret_val = pll / hsp_podf; + } else { + puts("mismatch HSP with ARM clock setting\n"); + ret_val = 0; + } + } else { + ret_val = __get_mcu_main_clk(); + } + break; + case IPG_CLK: + ret_val = __get_ipg_clk();; + break; + case IPG_PER_CLK: + ret_val = __get_ipg_per_clk(); + break; + case NFC_CLK: + nfc_pdf = (reg4 >> 28) & 0xF; + pll = __get_mcu_main_clk(); + /* AHB/nfc_pdf */ + ret_val = pll / (nfc_pdf + 1); + break; + case USB_CLK: + usb_prdf = (reg4 >> 25) & 0x7; + usb_podf = (reg4 >> 22) & 0x7; + if (reg4 & 0x200) + pll = __get_mcu_main_clk(); + else + pll = __decode_pll(__REG(PER_PLL), CONFIG_MX35_HCLK_FREQ); + + ret_val = pll / ((usb_prdf + 1) * (usb_podf + 1)); + break; + default: + printf("Unknown clock: %d\n", clk); + break; + } + + return ret_val; +} +unsigned int mxc_get_peri_clock(enum mxc_peri_clocks clk) +{ + u32 ret_val = 0, pdf, pre_pdf, clk_sel; + u32 mpdr2 = readl(CCM_BASE_ADDR + CLKCTL_PDR2); + u32 mpdr3 = readl(CCM_BASE_ADDR + CLKCTL_PDR3); + u32 mpdr4 = readl(CCM_BASE_ADDR + CLKCTL_PDR4); + + switch (clk) { + case UART1_BAUD: + case UART2_BAUD: + case UART3_BAUD: + clk_sel = mpdr3 & (1 << 14); + pre_pdf = (mpdr4 >> 13) & 0x7; + pdf = (mpdr4 >> 10) & 0x7; + ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) : + __decode_pll(__REG(PER_PLL), CONFIG_MX35_HCLK_FREQ)) / ((pre_pdf + 1) * (pdf + 1)); + break; + case SSI1_BAUD: + pre_pdf = (mpdr2 >> 24) & 0x7; + pdf = mpdr2 & 0x3F; + clk_sel = mpdr2 & ( 1 << 6); + ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) : + __decode_pll(__REG(PER_PLL), CONFIG_MX35_HCLK_FREQ)) / ((pre_pdf + 1) * (pdf + 1)); + break; + case SSI2_BAUD: + pre_pdf = (mpdr2 >> 27) & 0x7; + pdf = (mpdr2 >> 8)& 0x3F; + clk_sel = mpdr2 & ( 1 << 6); + ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) : + __decode_pll(__REG(PER_PLL), CONFIG_MX35_HCLK_FREQ)) / ((pre_pdf + 1) * (pdf + 1)); + break; + case CSI_BAUD: + clk_sel = mpdr2 & (1 << 7); + pre_pdf = (mpdr2 >> 16) & 0x7; + pdf = (mpdr2 >> 19) & 0x7; + ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) : + __decode_pll(__REG(PER_PLL), CONFIG_MX35_HCLK_FREQ)) / ((pre_pdf + 1) * (pdf + 1)); + break; + case MSHC_CLK: + pre_pdf = readl(CCM_BASE_ADDR + CLKCTL_PDR1); + clk_sel = (pre_pdf & 0x80); + pdf = (pre_pdf >> 22) & 0x3F; + pre_pdf = (pre_pdf >> 28) & 0x7; + ret_val = ((clk_sel != 0)? mxc_get_main_clock(CPU_CLK) : + __decode_pll(__REG(PER_PLL), CONFIG_MX35_HCLK_FREQ)) / ((pre_pdf + 1) * (pdf + 1)); + break; + case ESDHC1_CLK: + clk_sel = mpdr3 & 0x40; + pre_pdf = mpdr3&0x7; + pdf = (mpdr3>>3)&0x7; + ret_val = ((clk_sel != 0)? mxc_get_main_clock(CPU_CLK) : + __decode_pll(__REG(PER_PLL), CONFIG_MX35_HCLK_FREQ)) / ((pre_pdf + 1) * (pdf + 1)); + break; + case ESDHC2_CLK: + clk_sel = mpdr3 & 0x40; + pre_pdf = (mpdr3 >> 8)&0x7; + pdf = (mpdr3 >> 11)&0x7; + ret_val = ((clk_sel != 0)? mxc_get_main_clock(CPU_CLK) : + __decode_pll(__REG(PER_PLL), CONFIG_MX35_HCLK_FREQ)) / ((pre_pdf + 1) * (pdf + 1)); + break; + case ESDHC3_CLK: + clk_sel = mpdr3 & 0x40; + pre_pdf = (mpdr3 >> 16)&0x7; + pdf = (mpdr3 >> 19)&0x7; + ret_val = ((clk_sel != 0)? mxc_get_main_clock(CPU_CLK) : + __decode_pll(__REG(PER_PLL), CONFIG_MX35_HCLK_FREQ)) / ((pre_pdf + 1) * (pdf + 1)); + break; + case SPDIF_CLK: + clk_sel = mpdr3 & 0x400000; + pre_pdf = (mpdr3 >> 29)&0x7; + pdf = (mpdr3 >> 23)&0x3F; + ret_val = ((clk_sel != 0)? mxc_get_main_clock(CPU_CLK) : + __decode_pll(__REG(PER_PLL), CONFIG_MX35_HCLK_FREQ)) / ((pre_pdf + 1) * (pdf + 1)); + break; + default: + printf("%s(): This clock: %d not supported yet \n", + __FUNCTION__, clk); + break; + } + + return ret_val; +} + +unsigned int mxc_get_clock(enum mxc_clock clk) +{ + switch (clk) { + case MXC_ARM_CLK: + return __get_mcu_main_clk(); + case MXC_AHB_CLK: + break; + case MXC_IPG_CLK: + return __get_ipg_clk(); + case MXC_IPG_PERCLK: + return __get_ipg_per_clk(); + case MXC_UART_CLK: + return __get_uart_clk(); + case MXC_ESDHC_CLK: + return mxc_get_peri_clock(ESDHC1_CLK); + case MXC_USB_CLK: + return mxc_get_main_clock(USB_CLK); + } + return -1; +} + +void mxc_dump_clocks(void) +{ + u32 cpufreq = __get_mcu_main_clk(); + printf("mx35 cpu clock: %dMHz\n", cpufreq / 1000000); + printf("ipg clock : %dHz\n", __get_ipg_clk()); + printf("ipg per clock : %dHz\n", __get_ipg_per_clk()); + printf("uart clock : %dHz\n", mxc_get_clock(MXC_UART_CLK)); +} + +#if defined(CONFIG_DISPLAY_CPUINFO) +int print_cpuinfo(void) +{ + printf("CPU: Freescale i.MX35 at %d MHz\n", + __get_mcu_main_clk() / 1000000); + /* mxc_dump_clocks(); */ + return 0; +} +#endif + +#if defined(CONFIG_MXC_FEC) +extern int mxc_fec_initialize(bd_t *bis); +extern void mxc_fec_set_mac_from_env(char *mac_addr); +#endif + +/* + * Initializes on-chip ethernet controllers. + * to override, implement board_eth_init() + */ +int cpu_eth_init(bd_t *bis) +{ + int rc = -ENODEV; + +#if defined(CONFIG_MXC_FEC) + rc = mxc_fec_initialize(bis); +#endif + + return rc; +} + +#if defined(CONFIG_ARCH_CPU_INIT) +int arch_cpu_init(void) +{ + icache_enable(); + dcache_enable(); + return 0; +} +#endif diff --git a/cpu/arm1136/mx35/iomux.c b/cpu/arm1136/mx35/iomux.c new file mode 100644 index 0000000000..e66332c5d8 --- /dev/null +++ b/cpu/arm1136/mx35/iomux.c @@ -0,0 +1,149 @@ +/* + * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @defgroup GPIO_MX35 Board GPIO and Muxing Setup + * @ingroup MSL_MX35 + */ +/*! + * @file mach-mx35/iomux.c + * + * @brief I/O Muxing control functions + * + * @ingroup GPIO_MX35 + */ +#include +#include +#include +#include + +/*! + * IOMUX register (base) addresses + */ +enum iomux_reg_addr { + IOMUXGPR = IOMUXC_BASE_ADDR, + /*!< General purpose */ + IOMUXSW_MUX_CTL = IOMUXC_BASE_ADDR + 4, + /*!< MUX control */ + IOMUXSW_MUX_END = IOMUXC_BASE_ADDR + 0x324, + /*!< last MUX control register */ + IOMUXSW_PAD_CTL = IOMUXC_BASE_ADDR + 0x328, + /*!< Pad control */ + IOMUXSW_PAD_END = IOMUXC_BASE_ADDR + 0x794, + /*!< last Pad control register */ + IOMUXSW_INPUT_CTL = IOMUXC_BASE_ADDR + 0x7AC, + /*!< input select register */ + IOMUXSW_INPUT_END = IOMUXC_BASE_ADDR + 0x9F4, + /*!< last input select register */ +}; + +#define MUX_PIN_NUM_MAX \ + (((IOMUXSW_PAD_END - IOMUXSW_PAD_CTL) >> 2) + 1) +#define MUX_INPUT_NUM_MUX \ + (((IOMUXSW_INPUT_END - IOMUXSW_INPUT_CTL) >> 2) + 1) + +#define PIN_TO_IOMUX_INDEX(pin) ((PIN_TO_IOMUX_PAD(pin) - 0x328) >> 2) + +/*! + * This function is used to configure a pin through the IOMUX module. + * FIXED ME: for backward compatible. Will be static function! + * @param pin a pin number as defined in \b #iomux_pin_name_t + * @param cfg an output function as defined in \b #iomux_pin_cfg_t + * + * @return 0 if successful; Non-zero otherwise + */ +static int iomux_config_mux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg) +{ + u32 mux_reg = PIN_TO_IOMUX_MUX(pin); + + if (mux_reg != NON_MUX_I) { + mux_reg += IOMUXGPR; + __REG(mux_reg) = cfg; + } + + return 0; +} + +/*! + * Request ownership for an IO pin. This function has to be the first one + * being called before that pin is used. The caller has to check the + * return value to make sure it returns 0. + * + * @param pin a name defined by \b iomux_pin_name_t + * @param cfg an input function as defined in \b #iomux_pin_cfg_t + * + * @return 0 if successful; Non-zero otherwise + */ +int mxc_request_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg) +{ + int ret = iomux_config_mux(pin, cfg); + return ret; +} + +/*! + * Release ownership for an IO pin + * + * @param pin a name defined by \b iomux_pin_name_t + * @param cfg an input function as defined in \b #iomux_pin_cfg_t + */ +void mxc_free_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg) +{ +} + +/*! + * This function configures the pad value for a IOMUX pin. + * + * @param pin a pin number as defined in \b #iomux_pin_name_t + * @param config the ORed value of elements defined in \b #iomux_pad_config_t + */ +void mxc_iomux_set_pad(iomux_pin_name_t pin, u32 config) +{ + u32 pad_reg = IOMUXGPR + PIN_TO_IOMUX_PAD(pin); + + __REG(pad_reg) = config; +} + +/*! + * This function enables/disables the general purpose function for a particular + * signal. + * + * @param gp one signal as defined in \b #iomux_gp_func_t + * @param en \b #true to enable; \b #false to disable + */ +void mxc_iomux_set_gpr(iomux_gp_func_t gp, int en) +{ + u32 l; + + l = __REG(IOMUXGPR); + if (en) + l |= gp; + else + l &= ~gp; + + __REG(IOMUXGPR) = l; +} + +/*! + * This function configures input path. + * + * @param input index of input select register as defined in \b + * #iomux_input_select_t + * @param config the binary value of elements defined in \b + * #iomux_input_config_t + */ +void mxc_iomux_set_input(iomux_input_select_t input, u32 config) +{ + u32 reg = IOMUXSW_INPUT_CTL + (input << 2); + + __REG(reg) = config; +} diff --git a/cpu/arm1136/mx35/mxc_nand_load.S b/cpu/arm1136/mx35/mxc_nand_load.S new file mode 100644 index 0000000000..2ff223def8 --- /dev/null +++ b/cpu/arm1136/mx35/mxc_nand_load.S @@ -0,0 +1,261 @@ +/* + * (C) Copyright 2008 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +.macro nfc_cmd_input + strh r3, [r12, #NAND_FLASH_CMD_REG_OFF] + mov r3, #NAND_FLASH_CONFIG2_FCMD_EN; + strh r3, [r12, #NAND_FLASH_CONFIG2_REG_OFF] + bl do_wait_op_done +.endm // nfc_cmd_input + +.macro do_addr_input + and r3, r3, #0xFF + strh r3, [r12, #NAND_FLASH_ADD_REG_OFF] + mov r3, #NAND_FLASH_CONFIG2_FADD_EN + strh r3, [r12, #NAND_FLASH_CONFIG2_REG_OFF] + bl do_wait_op_done +.endm // do_addr_input + +.section ".text.load", "x" +.globl mxc_nand_load +mxc_nand_load: + ldr r2, U_BOOT_NAND_START +1: ldmia r0!, {r3-r10} + stmia r2!, {r3-r10} + cmp r0, r1 + blo 1b + + ldr r1, CONST_0X0FFF + ldr r2, U_BOOT_NAND_START + and lr, lr, r1 + add lr, lr, r2 + and r12, r12, r1 + add r12, r12, r2 + add r2, r2, #0x8 + and r0, pc, r1 + add pc, r0, r2 + nop + nop + nop + nop + nop + adr r0, SAVE_REGS + str r12, [r0] + str lr, [r0, #4] +Copy_Main: + mov r0, #NFC_BASE_ADDR + add r12, r0, #0x1E00 + ldrh r3, [r12, #NAND_FLASH_CONFIG1_REG_OFF] + orr r3, r3, #1 + + /* Setting NFC */ + ldr r7, =CCM_BASE_ADDR + ldr r1, [r7, #CLKCTL_RCSR] + /*BUS WIDTH setting*/ + tst r1, #0x20000000 + orrne r1, r1, #0x4000 + biceq r1, r1, #0x4000 + + /*4K PAGE*/ + tst r1, #0x10000000 + orrne r1, r1, #0x200 + bne 1f + /*2K PAGE*/ + bic r1, r1, #0x200 + tst r1, #0x08000000 + orrne r1, r1, #0x100 /*2KB page size*/ + biceq r1, r1, #0x100 /*512B page size*/ + movne r2, #32 /*64 bytes*/ + moveq r2, #8 /*16 bytes*/ + b NAND_setup +1: + tst r1, #0x08000000 + bicne r3, r3, #1 /*Enable 8bit ECC mode*/ + movne r2, #109 /*218 bytes*/ + moveq r2, #64 /*128 bytes*/ +NAND_setup: + str r1, [r7, #CLKCTL_RCSR] + strh r2, [r12, #ECC_RSLT_SPARE_AREA_REG_OFF] + strh r3, [r12, #NAND_FLASH_CONFIG1_REG_OFF] + + //unlock internal buffer + mov r3, #0x2 + strh r3, [r12, #NFC_CONFIGURATION_REG_OFF] + //unlock nand device + mov r3, #0 + strh r3, [r12, #UNLOCK_START_BLK_ADD_REG_OFF] + sub r3, r3, #1 + strh r3, [r12, #UNLOCK_END_BLK_ADD_REG_OFF] + mov r3, #4 + strh r3, [r12, #NF_WR_PROT_REG_OFF] + + /* r0: NFC base address. RAM buffer base address. [constantly] + * r1: starting flash address to be copied. [constantly] + * r2: page size. [Doesn't change] + * r3: used as argument. + * r11: starting SDRAM address for copying. [Updated constantly]. + * r12: NFC register base address. [constantly]. + * r13: end of SDRAM address for copying. [Doesn't change]. + */ + + mov r1, #0x1000 + ldr r3, [r7, #CLKCTL_RCSR] + tst r3, #0x200 + movne r2, #0x1000 + bne 1f + tst r3, #0x100 + mov r1, #0x800 /*Strange Why is not 4K offset*/ + movne r2, #0x800 + moveq r2, #0x200 +1: /*Update the indicator of copy area */ + ldr r11, U_BOOT_NAND_START + add r13, r11, #0x00088000; /*512K + 32K*/ + add r11, r11, r1 + +Nfc_Read_Page: + mov r3, #0x0 + nfc_cmd_input + + cmp r2, #0x800 + bhi nfc_addr_ops_4kb + beq nfc_addr_ops_2kb + + mov r3, r1 + do_addr_input //1st addr cycle + mov r3, r1, lsr #9 + do_addr_input //2nd addr cycle + mov r3, r1, lsr #17 + do_addr_input //3rd addr cycle + mov r3, r1, lsr #25 + do_addr_input //4th addr cycle + b end_of_nfc_addr_ops + +nfc_addr_ops_2kb: + mov r3, #0 + do_addr_input //1st addr cycle + mov r3, #0 + do_addr_input //2nd addr cycle + mov r3, r1, lsr #11 + do_addr_input //3rd addr cycle + mov r3, r1, lsr #19 + do_addr_input //4th addr cycle + mov r3, r1, lsr #27 + do_addr_input //5th addr cycle + + mov r3, #0x30 + nfc_cmd_input + b end_of_nfc_addr_ops + +nfc_addr_ops_4kb: + mov r3, #0 + do_addr_input //1st addr cycle + mov r3, #0 + do_addr_input //2nd addr cycle + mov r3, r1, lsr #12 + do_addr_input //3rd addr cycle + mov r3, r1, lsr #20 + do_addr_input //4th addr cycle + mov r3, r1, lsr #27 + do_addr_input //5th addr cycle + + mov r3, #0x30 + nfc_cmd_input + +end_of_nfc_addr_ops: + mov r8, #0 + bl nfc_data_output + bl do_wait_op_done + // Check if x16/2kb page + cmp r2, #0x800 + bhi nfc_addr_data_output_done_4k + beq nfc_addr_data_output_done_2k + beq nfc_addr_data_output_done_512 + + // check for bad block + // mov r3, r1, lsl #(32-17) // get rid of block number + // cmp r3, #(0x800 << (32-17)) // check if not page 0 or 1 + b nfc_addr_data_output_done + +nfc_addr_data_output_done_4k: +//TODO + b nfc_addr_data_output_done + +nfc_addr_data_output_done_2k: + // end of 4th + // check for bad block + //TODO mov r3, r1, lsl #(32-17) // get rid of block number + // cmp r3, #(0x800 << (32-17)) // check if not page 0 or 1 + b nfc_addr_data_output_done + +nfc_addr_data_output_done_512: + // check for bad block + // TODO mov r3, r1, lsl #(32-5-9) // get rid of block number + // TODO cmp r3, #(512 << (32-5-9)) // check if not page 0 or 1 + +nfc_addr_data_output_done: +Copy_Good_Blk: + //copying page + add r2, r2, #NFC_BASE_ADDR +1: ldmia r0!, {r3-r10} + stmia r11!, {r3-r10} + cmp r0, r2 + blo 1b + sub r2, r2, #NFC_BASE_ADDR + + cmp r11, r13 + bge NAND_Copy_Main_done + // Check if x16/2kb page + add r1, r1, r2 + mov r0, #NFC_BASE_ADDR + b Nfc_Read_Page + +NAND_Copy_Main_done: + adr r0, SAVE_REGS + ldr r12, [r0] + ldr lr, [r0, #4] + mov pc, lr + +do_wait_op_done: +1: + ldrh r3, [r12, #NAND_FLASH_CONFIG2_REG_OFF] + ands r3, r3, #NAND_FLASH_CONFIG2_INT_DONE + beq 1b + bx lr // do + +nfc_data_output: + ldrh r3, [r12, #NAND_FLASH_CONFIG1_REG_OFF] + orr r3, r3, #(NAND_FLASH_CONFIG1_INT_MSK | NAND_FLASH_CONFIG1_ECC_EN) + strh r3, [r12, #NAND_FLASH_CONFIG1_REG_OFF] + + strh r8, [r12, #RAM_BUFFER_ADDRESS_REG_OFF] + + mov r3, #FDO_PAGE_SPARE_VAL + strh r3, [r12, #NAND_FLASH_CONFIG2_REG_OFF] + bx lr + +U_BOOT_NAND_START: .word TEXT_BASE +CONST_0X0FFF: .word 0x0FFF +SAVE_REGS: .word 0x0 + .word 0x0 diff --git a/cpu/arm1136/mx35/serial.c b/cpu/arm1136/mx35/serial.c new file mode 100644 index 0000000000..f4f674aeda --- /dev/null +++ b/cpu/arm1136/mx35/serial.c @@ -0,0 +1,220 @@ +/* + * (c) 2007 Sascha Hauer + * + * (C) Copyright 2008-2009 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#include + +#if defined CONFIG_MX35_UART + +#include + +#define __REG(x) (*((volatile u32 *)(x))) + +#define UART_PHYS CONFIG_MX35_UART + +/* Register definitions */ +#define URXD 0x0 /* Receiver Register */ +#define UTXD 0x40 /* Transmitter Register */ +#define UCR1 0x80 /* Control Register 1 */ +#define UCR2 0x84 /* Control Register 2 */ +#define UCR3 0x88 /* Control Register 3 */ +#define UCR4 0x8c /* Control Register 4 */ +#define UFCR 0x90 /* FIFO Control Register */ +#define USR1 0x94 /* Status Register 1 */ +#define USR2 0x98 /* Status Register 2 */ +#define UESC 0x9c /* Escape Character Register */ +#define UTIM 0xa0 /* Escape Timer Register */ +#define UBIR 0xa4 /* BRM Incremental Register */ +#define UBMR 0xa8 /* BRM Modulator Register */ +#define UBRC 0xac /* Baud Rate Count Register */ +#define UTS 0xb4 /* UART Test Register (mx31) */ + +/* UART Control Register Bit Fields.*/ +#define URXD_CHARRDY (1<<15) +#define URXD_ERR (1<<14) +#define URXD_OVRRUN (1<<13) +#define URXD_FRMERR (1<<12) +#define URXD_BRK (1<<11) +#define URXD_PRERR (1<<10) +#define UCR1_ADEN (1<<15) /* Auto dectect interrupt */ +#define UCR1_ADBR (1<<14) /* Auto detect baud rate */ +#define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */ +#define UCR1_IDEN (1<<12) /* Idle condition interrupt */ +#define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */ +#define UCR1_RDMAEN (1<<8) /* Recv ready DMA enable */ +#define UCR1_IREN (1<<7) /* Infrared interface enable */ +#define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */ +#define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */ +#define UCR1_SNDBRK (1<<4) /* Send break */ +#define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */ +#define UCR1_UARTCLKEN (1<<2) /* UART clock enabled */ +#define UCR1_DOZE (1<<1) /* Doze */ +#define UCR1_UARTEN (1<<0) /* UART enabled */ +#define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */ +#define UCR2_IRTS (1<<14) /* Ignore RTS pin */ +#define UCR2_CTSC (1<<13) /* CTS pin control */ +#define UCR2_CTS (1<<12) /* Clear to send */ +#define UCR2_ESCEN (1<<11) /* Escape enable */ +#define UCR2_PREN (1<<8) /* Parity enable */ +#define UCR2_PROE (1<<7) /* Parity odd/even */ +#define UCR2_STPB (1<<6) /* Stop */ +#define UCR2_WS (1<<5) /* Word size */ +#define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */ +#define UCR2_TXEN (1<<2) /* Transmitter enabled */ +#define UCR2_RXEN (1<<1) /* Receiver enabled */ +#define UCR2_SRST (1<<0) /* SW reset */ +#define UCR3_DTREN (1<<13) /* DTR interrupt enable */ +#define UCR3_PARERREN (1<<12) /* Parity enable */ +#define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */ +#define UCR3_DSR (1<<10) /* Data set ready */ +#define UCR3_DCD (1<<9) /* Data carrier detect */ +#define UCR3_RI (1<<8) /* Ring indicator */ +#define UCR3_TIMEOUTEN (1<<7) /* Timeout interrupt enable */ +#define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */ +#define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */ +#define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */ +#define UCR3_REF25 (1<<3) /* Ref freq 25 MHz */ +#define UCR3_REF30 (1<<2) /* Ref Freq 30 MHz */ +#define UCR3_INVT (1<<1) /* Inverted Infrared transmission */ +#define UCR3_BPEN (1<<0) /* Preset registers enable */ +#define UCR4_CTSTL_32 (32<<10) /* CTS trigger level (32 chars) */ +#define UCR4_INVR (1<<9) /* Inverted infrared reception */ +#define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */ +#define UCR4_WKEN (1<<7) /* Wake interrupt enable */ +#define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */ +#define UCR4_IRSC (1<<5) /* IR special case */ +#define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */ +#define UCR4_BKEN (1<<2) /* Break condition interrupt enable */ +#define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */ +#define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */ +#define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */ +#define UFCR_RFDIV (7<<7) /* Reference freq divider mask */ +#define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */ +#define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */ +#define USR1_RTSS (1<<14) /* RTS pin status */ +#define USR1_TRDY (1<<13)/* Transmitter ready interrupt/dma flag */ +#define USR1_RTSD (1<<12) /* RTS delta */ +#define USR1_ESCF (1<<11) /* Escape seq interrupt flag */ +#define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */ +#define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */ +#define USR1_TIMEOUT (1<<7) /* Receive timeout interrupt status */ +#define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */ +#define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */ +#define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */ +#define USR2_ADET (1<<15) /* Auto baud rate detect complete */ +#define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */ +#define USR2_DTRF (1<<13) /* DTR edge interrupt flag */ +#define USR2_IDLE (1<<12) /* Idle condition */ +#define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */ +#define USR2_WAKE (1<<7) /* Wake */ +#define USR2_RTSF (1<<4) /* RTS edge interrupt flag */ +#define USR2_TXDC (1<<3) /* Transmitter complete */ +#define USR2_BRCD (1<<2) /* Break condition */ +#define USR2_ORE (1<<1) /* Overrun error */ +#define USR2_RDR (1<<0) /* Recv data ready */ +#define UTS_FRCPERR (1<<13) /* Force parity error */ +#define UTS_LOOP (1<<12) /* Loop tx and rx */ +#define UTS_TXEMPTY (1<<6) /* TxFIFO empty */ +#define UTS_RXEMPTY (1<<5) /* RxFIFO empty */ +#define UTS_TXFULL (1<<4) /* TxFIFO full */ +#define UTS_RXFULL (1<<3) /* RxFIFO full */ +#define UTS_SOFTRST (1<<0) /* Software reset */ + +DECLARE_GLOBAL_DATA_PTR; + +void serial_setbrg(void) +{ + u32 clk = mxc_get_clock(MXC_UART_CLK); + + if (!gd->baudrate) + gd->baudrate = CONFIG_BAUDRATE; + __REG(UART_PHYS + UFCR) = 0x4 << 7; /* divide input clock by 2 */ + __REG(UART_PHYS + UBIR) = 0xf; + __REG(UART_PHYS + UBMR) = clk / (2 * gd->baudrate); +} + +int serial_getc(void) +{ + while (__REG(UART_PHYS + UTS) & UTS_RXEMPTY) + ; + return __REG(UART_PHYS + URXD); +} + +void serial_putc(const char c) +{ + __REG(UART_PHYS + UTXD) = c; + + /* wait for transmitter to be ready */ + while (!(__REG(UART_PHYS + UTS) & UTS_TXEMPTY)) + ; + + /* If \n, also do \r */ + if (c == '\n') + serial_putc('\r'); +} + +/* + * Test whether a character is in the RX buffer + */ +int serial_tstc(void) +{ + /* If receive fifo is empty, return false */ + if (__REG(UART_PHYS + UTS) & UTS_RXEMPTY) + return 0; + return 1; +} + +void serial_puts(const char *s) +{ + while (*s) + serial_putc(*s++); +} + +/* + * Initialise the serial port with the given baudrate. The settings + * are always 8 data bits, no parity, 1 stop bit, no start bits. + * + */ +int serial_init(void) +{ + __REG(UART_PHYS + UCR1) = 0x0; + __REG(UART_PHYS + UCR2) = 0x0; + + while (!(__REG(UART_PHYS + UCR2) & UCR2_SRST)) + ; + + __REG(UART_PHYS + UCR3) = 0x0704; + __REG(UART_PHYS + UCR4) = 0x8000; + __REG(UART_PHYS + UESC) = 0x002b; + __REG(UART_PHYS + UTIM) = 0x0; + + __REG(UART_PHYS + UTS) = 0x0; + + serial_setbrg(); + + __REG(UART_PHYS + UCR2) = + UCR2_WS | UCR2_IRTS | UCR2_RXEN | UCR2_TXEN | UCR2_SRST; + + __REG(UART_PHYS + UCR1) = UCR1_UARTEN; + + return 0; +} + +#endif /* CONFIG_MX35 */ diff --git a/cpu/arm1136/mx35/timer.c b/cpu/arm1136/mx35/timer.c new file mode 100644 index 0000000000..f18be9ccf5 --- /dev/null +++ b/cpu/arm1136/mx35/timer.c @@ -0,0 +1,132 @@ +/* + * (C) Copyright 2007 + * Sascha Hauer, Pengutronix + * + * (C) Copyright 2008-2009 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +/* General purpose timers registers */ +#define GPTCR __REG(GPT1_BASE_ADDR) /* Control register */ +#define GPTPR __REG(GPT1_BASE_ADDR + 0x4) /* Prescaler register */ +#define GPTSR __REG(GPT1_BASE_ADDR + 0x8) /* Status register */ +#define GPTCNT __REG(GPT1_BASE_ADDR + 0x24) /* Counter register */ + +/* General purpose timers bitfields */ +#define GPTCR_SWR (1<<15) /* Software reset */ +#define GPTCR_FRR (1<<9) /* Freerun / restart */ +#define GPTCR_CLKSOURCE_32 (0x100<<6) /* Clock source */ +#define GPTCR_CLKSOURCE_IPG (0x001<<6) /* Clock source */ +#define GPTCR_TEN (1) /* Timer enable */ +#define GPTPR_VAL (66) + +static inline void setup_gpt() +{ + int i; + static int init_done; + + if (init_done) + return; + + init_done = 1; + + /* setup GP Timer 1 */ + GPTCR = GPTCR_SWR; + for (i = 0; i < 100; i++) + GPTCR = 0; /* We have no udelay by now */ + GPTPR = GPTPR_VAL; /* 66Mhz / 66 */ + /* Freerun Mode, PERCLK1 input */ + GPTCR |= GPTCR_CLKSOURCE_IPG | GPTCR_TEN; +} + +int timer_init(void) +{ + setup_gpt(); + + return 0; +} + +void reset_timer_masked(void) +{ + GPTCR = 0; + /* Freerun Mode, PERCLK1 input */ + GPTCR = GPTCR_CLKSOURCE_IPG | GPTCR_TEN; +} + +inline ulong get_timer_masked(void) +{ + ulong val = GPTCNT; + + return val; +} + +void reset_timer(void) +{ + reset_timer_masked(); +} + +ulong get_timer(ulong base) +{ + ulong tmp; + + tmp = get_timer_masked(); + + if (tmp <= (base * 1000)) { + /* Overflow */ + tmp += (0xffffffff - base); + } + + return (tmp / 1000) - base; +} + +void set_timer(ulong t) +{ +} + +/* delay x useconds AND perserve advance timstamp value */ +/* GPTCNT is now supposed to tick 1 by 1 us. */ +void udelay(unsigned long usec) +{ + ulong tmp; + + setup_gpt(); + + tmp = get_timer_masked(); /* get current timestamp */ + + /* if setting this forward will roll time stamp */ + if ((usec + tmp + 1) < tmp) { + /* reset "advancing" timestamp to 0, set lastinc value */ + reset_timer_masked(); + } else { + /* else, set advancing stamp wake up time */ + tmp += usec; + } + + while (get_timer_masked() < tmp) /* loop till event */ + /*NOP*/; +} + +void reset_cpu(ulong addr) +{ + __REG16(WDOG_BASE_ADDR) = 4; +} diff --git a/cpu/arm1136/start.S b/cpu/arm1136/start.S index 957f4389b2..03128567b3 100644 --- a/cpu/arm1136/start.S +++ b/cpu/arm1136/start.S @@ -30,9 +30,15 @@ #include #include + +.section ".text.head", "ax" .globl _start -_start: b reset +_start: +.section ".text.vect", "ax" +.global _start_vect +_start_vect: #ifdef CONFIG_PRELOADER + b reset ldr pc, _hang ldr pc, _hang ldr pc, _hang @@ -85,40 +91,12 @@ _end_vect: ************************************************************************* */ -_TEXT_BASE: - .word TEXT_BASE - -.globl _armboot_start -_armboot_start: - .word _start - -/* - * These are defined in the board-specific linker script. - */ -.globl _bss_start -_bss_start: - .word __bss_start - -.globl _bss_end -_bss_end: - .word _end - -#ifdef CONFIG_USE_IRQ -/* IRQ stack memory (calculated at run-time) */ -.globl IRQ_STACK_START -IRQ_STACK_START: - .word 0x0badc0de - -/* IRQ stack memory (calculated at run-time) */ -.globl FIQ_STACK_START -FIQ_STACK_START: - .word 0x0badc0de -#endif - /* * the actual reset code */ +.section ".text.head", "ax" +.globl reset reset: /* * set the cpu to SVC32 mode @@ -131,7 +109,7 @@ reset: #ifdef CONFIG_OMAP2420H4 /* Copy vectors to mask ROM indirect addr */ adr r0, _start /* r0 <- current position of code */ - add r0, r0, #4 /* skip reset vector */ + add r0, r0, #4 /* skip reset vector */ mov r2, #64 /* r2 <- size to copy */ add r2, r0, r2 /* r2 <- source end address */ mov r1, #SRAM_OFFSET0 /* build vect addr */ @@ -150,16 +128,92 @@ next: #ifndef CONFIG_SKIP_LOWLEVEL_INIT bl cpu_init_crit #endif + b setup_env + +#ifndef CONFIG_SKIP_LOWLEVEL_INIT +/* + ************************************************************************* + * + * CPU_init_critical registers + * + * setup important registers + * setup memory timing + * + ************************************************************************* + */ +cpu_init_crit: + /* + * flush v4 I/D caches + */ + mov r0, #0 + mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */ + mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */ + + /* + * disable MMU stuff and caches + */ + mrc p15, 0, r0, c1, c0, 0 + bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS) + bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM) + orr r0, r0, #0x00000002 @ set bit 2 (A) Align + orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache + mcr p15, 0, r0, c1, c0, 0 + + /* + * Jump to board specific initialization... The Mask ROM will have already initialized + * basic memory. Go here to bump up clock rate and handle wake up conditions. + */ + mov ip, lr /* persevere link reg across call */ + bl lowlevel_init /* go setup pll,mux,memory */ + mov lr, ip /* restore link */ + mov pc, lr /* back to my caller */ +#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ + +.section ".text.setup", "ax" + +.globl _TEXT_BASE +_TEXT_BASE: + .word TEXT_BASE + +.globl _armboot_start +_armboot_start: + .word _start + +/* + * These are defined in the board-specific linker script. + */ +.globl _bss_start +_bss_start: + .word __bss_start + +.globl _bss_end +_bss_end: + .word _end + +#ifdef CONFIG_USE_IRQ +/* IRQ stack memory (calculated at run-time) */ +.globl IRQ_STACK_START +IRQ_STACK_START: + .word 0x0badc0de + +/* IRQ stack memory (calculated at run-time) */ +.globl FIQ_STACK_START +FIQ_STACK_START: + .word 0x0badc0de +#endif + +setup_env: #ifndef CONFIG_SKIP_RELOCATE_UBOOT relocate: /* relocate U-Boot to RAM */ - adr r0, _start /* r0 <- current position of code */ - ldr r1, _TEXT_BASE /* test if we run from flash or RAM */ + adr r0, _armboot_start + ldr r1, =_armboot_start cmp r0, r1 /* don't reloc during debug */ -#ifndef CONFIG_PRELOADER beq stack_setup -#endif /* CONFIG_PRELOADER */ - + ldr r2, _armboot_start + sub r0, r1, r0 + sub r0, r2, r0 + mov r1, r2 ldr r2, _armboot_start ldr r3, _bss_start sub r2, r3, r2 /* r2 <- size of armboot */ @@ -197,7 +251,9 @@ clbss_l:str r2, [r0] /* clear loop... */ cmp r0, r1 bne clbss_l #endif - +#ifdef CONFIG_ARCH_MMU + bl board_mmu_init +#endif ldr pc, _start_armboot #ifdef CONFIG_NAND_SPL @@ -210,45 +266,6 @@ _start_armboot: .word start_armboot #endif /* CONFIG_ONENAND_IPL */ #endif /* CONFIG_NAND_SPL */ -/* - ************************************************************************* - * - * CPU_init_critical registers - * - * setup important registers - * setup memory timing - * - ************************************************************************* - */ -#ifndef CONFIG_SKIP_LOWLEVEL_INIT -cpu_init_crit: - /* - * flush v4 I/D caches - */ - mov r0, #0 - mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */ - mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */ - - /* - * disable MMU stuff and caches - */ - mrc p15, 0, r0, c1, c0, 0 - bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS) - bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM) - orr r0, r0, #0x00000002 @ set bit 2 (A) Align - orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache - mcr p15, 0, r0, c1, c0, 0 - - /* - * Jump to board specific initialization... The Mask ROM will have already initialized - * basic memory. Go here to bump up clock rate and handle wake up conditions. - */ - mov ip, lr /* persevere link reg across call */ - bl lowlevel_init /* go setup pll,mux,memory */ - mov lr, ip /* restore link */ - mov pc, lr /* back to my caller */ -#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ - #ifndef CONFIG_PRELOADER /* ************************************************************************* diff --git a/cpu/arm926ejs/cpu.c b/cpu/arm926ejs/cpu.c index 5c902dfc13..7f2dbd439b 100644 --- a/cpu/arm926ejs/cpu.c +++ b/cpu/arm926ejs/cpu.c @@ -32,6 +32,7 @@ #include #include #include +#include static void cache_flush(void); diff --git a/cpu/arm926ejs/mx23/Makefile b/cpu/arm926ejs/mx23/Makefile new file mode 100644 index 0000000000..3b23886396 --- /dev/null +++ b/cpu/arm926ejs/mx23/Makefile @@ -0,0 +1,47 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(SOC).a + +COBJS = timer.o spi.o +SOBJS = reset.o + +SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) +START := $(addprefix $(obj),$(START)) + +all: $(obj).depend $(LIB) + +$(LIB): $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/cpu/arm926ejs/mx23/config.mk b/cpu/arm926ejs/mx23/config.mk new file mode 100644 index 0000000000..b524ad1482 --- /dev/null +++ b/cpu/arm926ejs/mx23/config.mk @@ -0,0 +1,2 @@ +PLATFORM_CPPFLAGS += -march=armv5te +PLATFORM_CPPFLAGS += $(call cc-option,-mtune=arm926ejs,) \ No newline at end of file diff --git a/cpu/arm926ejs/mx23/reset.S b/cpu/arm926ejs/mx23/reset.S new file mode 100644 index 0000000000..a53ca577ba --- /dev/null +++ b/cpu/arm926ejs/mx23/reset.S @@ -0,0 +1,45 @@ +/* + * Processor reset for Freescale MX23 SoC. + * + * (C) Copyright 2009-2010 Freescale Semiconductor, Inc. + * + * Copyright (C) 2007 Sergey Kubushyn + * + * ----------------------------------------------------- + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +.globl reset_cpu +reset_cpu: + ldr r0, POWER_CHARGE + mov r1, #0x0 + str r1, [r0] + ldr r0, POWER_MINPWR + str r1, [r0] + ldr r0, CLKCTRL_RESET + mov r1, #0x1 + str r1, [r0] +_loop_forever: + b _loop_forever + +POWER_MINPWR: + .word 0x80044020 +POWER_CHARGE: + .word 0x80044030 +CLKCTRL_RESET: + .word 0x80040120 + diff --git a/cpu/arm926ejs/mx23/spi.c b/cpu/arm926ejs/mx23/spi.c new file mode 100644 index 0000000000..b78591803f --- /dev/null +++ b/cpu/arm926ejs/mx23/spi.c @@ -0,0 +1,255 @@ +/* + * Copyright (C) 2008 Embedded Alley Solutions Inc. + * + * (C) Copyright 2009-2010 Freescale Semiconductor, Inc. + * + * Freescale MX23 SSP/SPI driver + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include + +#define SPI_NUM_BUSES 2 +#define SPI_NUM_SLAVES 3 + +/* Initalized in spi_init() depending on SSP port configuration */ +static unsigned long ssp_bases[SPI_NUM_BUSES]; + +/* Set in spi_set_cfg() depending on which SSP port is being used */ +static unsigned long ssp_base = SSP1_BASE; + +/* + * Init SSP port: SSP1 (@bus = 0) or SSP2 (@bus == 1) + */ +static void ssp_spi_init(unsigned int bus) +{ + u32 spi_div; + u32 val = 0; + + if (bus >= SPI_NUM_BUSES) { + printf("SPI bus %d doesn't exist\n", bus); + return; + } + + ssp_base = ssp_bases[bus]; + + /* Reset block */ + + /* Clear SFTRST */ + REG_CLR(ssp_base + SSP_CTRL0, CTRL0_SFTRST); + while (REG_RD(ssp_base + SSP_CTRL0) & CTRL0_SFTRST) + ; + + /* Clear CLKGATE */ + REG_CLR(ssp_base + SSP_CTRL0, CTRL0_CLKGATE); + + /* Set SFTRST and wait until CLKGATE is set */ + REG_SET(ssp_base + SSP_CTRL0, CTRL0_SFTRST); + while (!(REG_RD(ssp_base + SSP_CTRL0) & CTRL0_CLKGATE)) + ; + + /* Clear SFTRST and CLKGATE */ + REG_CLR(ssp_base + SSP_CTRL0, CTRL0_SFTRST); + REG_CLR(ssp_base + SSP_CTRL0, CTRL0_CLKGATE); + + /* + * Set CLK to desired value + */ + + spi_div = ((CONFIG_SSP_CLK>>1) + CONFIG_SPI_CLK - 1) / CONFIG_SPI_CLK; + val = (2 << TIMING_CLOCK_DIVIDE) | ((spi_div - 1) << TIMING_CLOCK_RATE); + REG_WR(ssp_base + SSP_TIMING, val); + + /* Set transfer parameters */ + + /* Set SSP SPI Master mode and word length to 8 bit */ + REG_WR(ssp_base + SSP_CTRL1, WORD_LENGTH8 | SSP_MODE_SPI); + + /* Set BUS_WIDTH to 1 bit and XFER_COUNT to 1 byte */ + REG_WR(ssp_base + SSP_CTRL0, + BUS_WIDTH_SPI1 | (0x1 << CTRL0_XFER_COUNT)); + + /* + * Set BLOCK_SIZE and BLOCK_COUNT to 0, so that XFER_COUNT + * reflects number of bytes to send. Disalbe other bits as + * well + */ + REG_WR(ssp_base + SSP_CMD0, 0x0); +} + +/* + * Init SSP ports, must be called first and only once + */ +void spi_init(void) +{ +#ifdef CONFIG_SPI_SSP1 + ssp_bases[0] = SSP1_BASE; + ssp_spi_init(0); +#endif + +#ifdef CONFIG_SPI_SSP2 + ssp_bases[1] = SSP2_BASE; + ssp_spi_init(1); +#endif +} + +void spi_set_cfg(unsigned int bus, unsigned int cs, unsigned long mode) +{ + u32 clr_mask = 0; + u32 set_mask = 0; + + if (bus >= SPI_NUM_BUSES || cs >= SPI_NUM_SLAVES) { + printf("SPI device %d:%d doesn't exist", bus, cs); + return; + } + + if (ssp_bases[bus] == 0) { + printf("SSP port %d isn't in SPI mode\n", bus + 1); + return; + } + + /* Set SSP port to use */ + ssp_base = ssp_bases[bus]; + + /* Set phase and polarity: HW_SSP_CTRL1 */ + if (mode & SPI_PHASE) + set_mask |= CTRL1_PHASE; + else + clr_mask |= CTRL1_PHASE; + + if (mode & SPI_POLARITY) + set_mask |= CTRL1_POLARITY; + else + clr_mask |= CTRL1_POLARITY; + + REG_SET(ssp_base + SSP_CTRL1, set_mask); + REG_CLR(ssp_base + SSP_CTRL1, clr_mask); + + /* Set SSn number: HW_SSP_CTRL0 */ + REG_CLR(ssp_base + SSP_CTRL0, SPI_CS_CLR_MASK); + + switch (cs) { + case 0: + set_mask = SPI_CS0; + break; + case 1: + set_mask = SPI_CS1; + break; + case 2: + set_mask = SPI_CS2; + break; + } + + REG_SET(ssp_base + SSP_CTRL0, set_mask); +} + +/* Read single data byte */ +static unsigned char spi_read(void) +{ + unsigned char b = 0; + + /* Set XFER_LENGTH to 1 */ + REG_CLR(ssp_base + SSP_CTRL0, 0xffff); + REG_SET(ssp_base + SSP_CTRL0, 1); + + /* Enable READ mode */ + REG_SET(ssp_base + SSP_CTRL0, CTRL0_READ); + + /* Set RUN bit */ + REG_SET(ssp_base + SSP_CTRL0, CTRL0_RUN); + + + /* Set transfer */ + REG_SET(ssp_base + SSP_CTRL0, CTRL0_DATA_XFER); + + while (REG_RD(ssp_base + SSP_STATUS) & STATUS_FIFO_EMPTY) + ; + + /* Read data byte */ + b = REG_RD(ssp_base + SSP_DATA) & 0xff; + + /* Wait until RUN bit is cleared */ + while (REG_RD(ssp_base + SSP_CTRL0) & CTRL0_RUN) + ; + + return b; +} + +/* Write single data byte */ +static void spi_write(unsigned char b) +{ + /* Set XFER_LENGTH to 1 */ + REG_CLR(ssp_base + SSP_CTRL0, 0xffff); + REG_SET(ssp_base + SSP_CTRL0, 1); + + /* Enable WRITE mode */ + REG_CLR(ssp_base + SSP_CTRL0, CTRL0_READ); + + /* Set RUN bit */ + REG_SET(ssp_base + SSP_CTRL0, CTRL0_RUN); + + /* Write data byte */ + REG_WR(ssp_base + SSP_DATA, b); + + /* Set transfer */ + REG_SET(ssp_base + SSP_CTRL0, CTRL0_DATA_XFER); + + /* Wait until RUN bit is cleared */ + while (REG_RD(ssp_base + SSP_CTRL0) & CTRL0_RUN) + ; +} + +static void spi_lock_cs(void) +{ + REG_CLR(ssp_base + SSP_CTRL0, CTRL0_IGNORE_CRC); + REG_SET(ssp_base + SSP_CTRL0, CTRL0_LOCK_CS); +} + +static void spi_unlock_cs(void) +{ + REG_CLR(ssp_base + SSP_CTRL0, CTRL0_LOCK_CS); + REG_SET(ssp_base + SSP_CTRL0, CTRL0_IGNORE_CRC); +} + +void spi_txrx(const char *dout, unsigned int tx_len, char *din, + unsigned int rx_len, unsigned long flags) +{ + int i; + + if (tx_len == 0 && rx_len == 0) + return; + + if (flags & SPI_START) + spi_lock_cs(); + + for (i = 0; i < tx_len; i++) { + + /* Check if it is last data byte to transfer */ + if (flags & SPI_STOP && rx_len == 0 && i == tx_len - 1) + spi_unlock_cs(); + + spi_write(dout[i]); + } + + for (i = 0; i < rx_len; i++) { + + /* Check if it is last data byte to transfer */ + if (flags & SPI_STOP && i == rx_len - 1) + spi_unlock_cs(); + + din[i] = spi_read(); + } +} diff --git a/cpu/arm926ejs/mx23/timer.c b/cpu/arm926ejs/mx23/timer.c new file mode 100644 index 0000000000..2edfa98100 --- /dev/null +++ b/cpu/arm926ejs/mx23/timer.c @@ -0,0 +1,245 @@ +/* + * (C) Copyright 2003 + * Texas Instruments + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Alex Zuepke + * + * (C) Copyright 2002-2004 + * Gary Jennejohn, DENX Software Engineering, + * + * (C) Copyright 2004 + * Philippe Robin, ARM Ltd. + * + * (C) Copyright 2009-2010 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +#define CONFIG_USE_TIMER0 + +#if defined(CONFIG_USE_TIMER0) +#define TIMCTRL TIMCTRL0 +#define TIMCOUNT TIMCOUNT0 +#elif defined(CONFIG_USE_TIMER1) +#define TIMCTRL TIMCTRL1 +#define TIMCOUNT TIMCOUNT1 +#elif defined(CONFIG_USE_TIMER2) +#define TIMCTRL TIMCTRL2 +#define TIMCOUNT TIMCOUNT2 +#elif defined(CONFIG_USE_TIMER3) +#define TIMCTRL TIMCTRL3 +#define TIMCOUNT TIMCOUNT3 +#else +#error "Define which MX23 timer to use" +#endif + +#define TIMER_LOAD_VAL 0x0000ffff + +/* macro to read the 16 bit timer */ +#define READ_TIMER ((REG_RD(TIMROT_BASE + TIMCOUNT) & 0xffff0000) >> 16) + +static ulong timestamp; +static ulong lastdec; + +int timer_init(void) +{ + u32 val; + + /* + * Reset Timers and Rotary Encoder module + */ + + /* Clear SFTRST */ + REG_CLR(TIMROT_BASE + ROTCTRL, 1 << 31); + while (REG_RD(TIMROT_BASE + ROTCTRL) & (1 << 31)) + ; + + /* Clear CLKGATE */ + REG_CLR(TIMROT_BASE + ROTCTRL, 1 << 30); + + /* Set SFTRST and wait until CLKGATE is set */ + REG_SET(TIMROT_BASE + ROTCTRL, 1 << 31); + while (!(REG_RD(TIMROT_BASE + ROTCTRL) & (1 << 30))) + ; + + /* Clear SFTRST and CLKGATE */ + REG_CLR(TIMROT_BASE + ROTCTRL, 1 << 31); + REG_CLR(TIMROT_BASE + ROTCTRL, 1 << 30); + + /* + * Now initialize timer + */ + + /* Set fixed_count to 0 */ + REG_WR(TIMROT_BASE + TIMCOUNT, 0); + + /* set UPDATE bit and 1Khz frequency */ + REG_WR(TIMROT_BASE + TIMCTRL, + TIMCTRL_RELOAD | TIMCTRL_UPDATE | TIMCTRL_SELECT_1KHZ); + + /* Set fixed_count to maximal value */ + REG_WR(TIMROT_BASE + TIMCOUNT, TIMER_LOAD_VAL); + + /* init the timestamp and lastdec value */ + reset_timer_masked(); + + return 0; +} + +/* + * timer without interrupts + */ + +void reset_timer(void) +{ + reset_timer_masked(); +} + +ulong get_timer(ulong base) +{ + return get_timer_masked() - base; +} + +void set_timer(ulong t) +{ + timestamp = t; +} + +/* delay x useconds AND perserve advance timstamp value */ +void udelay(unsigned long usec) +{ + ulong tmo, tmp; + + if (usec >= 1000) { + /* if "big" number, spread normalization to seconds */ + tmo = usec / 1000; + /* start to normalize for usec to ticks per sec */ + tmo *= CONFIG_SYS_HZ; + /* find number of "ticks" to wait to achieve target */ + tmo /= 1000; + /* finish normalize. */ + } else { + /* else small number, don't kill it prior to HZ multiply */ + tmo = usec * CONFIG_SYS_HZ; + tmo /= (1000*1000); + } + + tmp = get_timer(0); + /* get current timestamp */ + if ((tmo + tmp + 1) < tmp) + /* if setting this fordward will roll time stamp */ + reset_timer_masked(); + /* reset "advancing" timestamp to 0, set lastdec value */ + else + tmo += tmp; + /* else, set advancing stamp wake up time */ + + while (get_timer_masked() < tmo)/* loop till event */ + /*NOP*/; +} + +void reset_timer_masked(void) +{ + /* reset time */ + lastdec = READ_TIMER; /* capure current decrementer value time */ + timestamp = 0; /* start "advancing" time stamp from 0 */ +} + +ulong get_timer_masked(void) +{ + ulong now = READ_TIMER; /* current tick value */ + + if (lastdec >= now) { /* normal mode (non roll) */ + /* normal mode */ + timestamp += lastdec - now; + /* move stamp fordward with absoulte diff ticks */ + } else { + /* we have overflow of the count down timer */ + /* nts = ts + ld + (TLV - now) + * ts=old stamp, ld=time that passed before passing through -1 + * (TLV-now) amount of time after passing though -1 + * nts = new "advancing time stamp"...it could also roll + * and cause problems. + */ + timestamp += lastdec + TIMER_LOAD_VAL - now + 1; + } + lastdec = now; + + return timestamp; +} + +/* waits specified delay value and resets timestamp */ +void udelay_masked(unsigned long usec) +{ + ulong tmo; + ulong endtime; + signed long diff; + + if (usec >= 1000) { + /* if "big" number, spread normalization to seconds */ + tmo = usec / 1000; + /* start to normalize for usec to ticks per sec */ + tmo *= CONFIG_SYS_HZ; + /* find number of "ticks" to wait to achieve target */ + tmo /= 1000; + /* finish normalize. */ + } else { + /* else small number, don't kill it prior to HZ multiply */ + tmo = usec * CONFIG_SYS_HZ; + tmo /= (1000*1000); + } + + endtime = get_timer_masked() + tmo; + + do { + ulong now = get_timer_masked(); + diff = endtime - now; + } while (diff >= 0); +} + +/* + * This function is derived from PowerPC code (read timebase as long long). + * On ARM it just returns the timer value. + */ +unsigned long long get_ticks(void) +{ + return get_timer(0); +} + +/* + * This function is derived from PowerPC code (timebase clock frequency). + * On ARM it returns the number of timer ticks per second. + */ +ulong get_tbclk(void) +{ + ulong tbclk; + + tbclk = CONFIG_SYS_HZ; + return tbclk; +} diff --git a/cpu/arm926ejs/mx25/Makefile b/cpu/arm926ejs/mx25/Makefile new file mode 100644 index 0000000000..48b4e7d46b --- /dev/null +++ b/cpu/arm926ejs/mx25/Makefile @@ -0,0 +1,45 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(SOC).a + +COBJS = timer.o serial.o generic.o iomux.o gpio.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) + +all: $(obj).depend $(LIB) + +$(LIB): $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/cpu/arm926ejs/mx25/generic.c b/cpu/arm926ejs/mx25/generic.c new file mode 100644 index 0000000000..4b8775db88 --- /dev/null +++ b/cpu/arm926ejs/mx25/generic.c @@ -0,0 +1,136 @@ +/* + * (C) Copyright 2007 + * Sascha Hauer, Pengutronix + * + * (C) Copyright 2009-2010 Freescale Semiconductor + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +static u32 mx25_decode_pll(u32 reg) +{ + u32 mfi = (reg >> 10) & 0xf; + u32 mfn = reg & 0x3ff; + u32 mfd = (reg >> 16) & 0x3ff; + u32 pd = (reg >> 26) & 0xf; + + u32 ref_clk = PLL_REF_CLK; + + mfi = mfi <= 5 ? 5 : mfi; + mfd += 1; + pd += 1; + + return ((2 * (ref_clk >> 10) * (mfi * mfd + mfn)) / + (mfd * pd)) << 10; +} + +static u32 mx25_get_mcu_main_clk(void) +{ + u32 cctl = __REG(CCM_CCTL); + u32 ret_val = mx25_decode_pll(__REG(CCM_MPCTL)); + + if (cctl & CRM_CCTL_ARM_SRC) { + ret_val *= 3; + ret_val /= 4; + } + + return ret_val; +} + +static u32 mx25_get_ahb_clk(void) +{ + u32 cctl = __REG(CCM_CCTL); + u32 ahb_div = ((cctl >> CRM_CCTL_AHB_OFFSET) & 3) + 1; + + return mx25_get_mcu_main_clk()/ahb_div; +} + +unsigned int mx25_get_ipg_clk(void) +{ + return mx25_get_ahb_clk()/2; +} + +unsigned int mx25_get_cspi_clk(void) +{ + return mx25_get_ipg_clk(); +} + +void mx25_dump_clocks(void) +{ + u32 cpufreq = mx25_get_mcu_main_clk(); + printf("mx25 cpu clock: %dMHz\n", cpufreq / 1000000); + printf("ipg clock : %dHz\n", mx25_get_ipg_clk()); +} + +unsigned int mxc_get_clock(enum mxc_clock clk) +{ + switch (clk) { + case MXC_ARM_CLK: + return mx25_get_mcu_main_clk(); + case MXC_AHB_CLK: + return mx25_get_ahb_clk(); + break; + case MXC_IPG_PERCLK: + case MXC_IPG_CLK: + return mx25_get_ipg_clk(); + case MXC_CSPI_CLK: + return mx25_get_cspi_clk(); + case MXC_UART_CLK: + break; + case MXC_ESDHC_CLK: + return mx25_get_ipg_clk(); + break; + } + return -1; +} + +#if defined(CONFIG_DISPLAY_CPUINFO) +int print_cpuinfo(void) +{ + printf("CPU: Freescale i.MX25 at %d MHz\n", + mx25_get_mcu_main_clk() / 1000000); + mx25_dump_clocks(); + return 0; +} +#endif + +#if defined(CONFIG_MXC_FEC) +extern int mxc_fec_initialize(bd_t *bis); +extern void mxc_fec_set_mac_from_env(char *mac_addr); +#endif + +/* + * Initializes on-chip ethernet controllers. + * to override, implement board_eth_init() + */ +int cpu_eth_init(bd_t *bis) +{ + int rc = -ENODEV; + +#if defined(CONFIG_MXC_FEC) + rc = mxc_fec_initialize(bis); +#endif + + return rc; +} + diff --git a/cpu/arm926ejs/mx25/gpio.c b/cpu/arm926ejs/mx25/gpio.c new file mode 100644 index 0000000000..560b3a43e5 --- /dev/null +++ b/cpu/arm926ejs/mx25/gpio.c @@ -0,0 +1,113 @@ +/* + * (c) Copyright 2009 Freescale Semiconductors + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include + +enum gpio_reg { + DR = 0x00, + GDIR = 0x04, + PSR = 0x08, + ICR1 = 0x0C, + ICR2 = 0x10, + IMR = 0x14, + ISR = 0x18, +}; + +struct gpio_port_addr { + int num; + int base; +}; + +struct gpio_port_addr gpio_port[4] = { + {0, GPIO1_BASE}, + {1, GPIO2_BASE}, + {2, GPIO3_BASE}, + {3, GPIO4_BASE} + }; + +/* + * Set a GPIO pin's direction + * @param port pointer to a gpio_port + * @param index gpio pin index value (0~31) + * @param is_input 0 for output; non-zero for input + */ +static void _set_gpio_direction(u32 port, u32 index, int is_input) +{ + u32 reg = gpio_port[port].base + GDIR; + u32 l; + + l = __REG(reg); + if (is_input) + l &= ~(1 << index); + else + l |= 1 << index; + __REG(reg) = l; +} + + +/*! + * Exported function to set a GPIO pin's direction + * @param pin a name defined by \b iomux_pin_name_t + * @param is_input 1 (or non-zero) for input; 0 for output + */ +void mxc_set_gpio_direction(iomux_pin_name_t pin, int is_input) +{ + u32 port; + u32 gpio = IOMUX_TO_GPIO(pin); + + port = GPIO_TO_PORT(gpio); + _set_gpio_direction(port, GPIO_TO_INDEX(gpio), is_input); +} + +/* + * Set a GPIO pin's data output + * @param port number of gpio port + * @param index gpio pin index value (0~31) + * @param data value to be set (only 0 or 1 is valid) + */ +static void _set_gpio_dataout(u32 port, u32 index, u32 data) +{ + u32 reg = gpio_port[port].base + DR; + u32 l = 0; + + l = (__REG(reg) & (~(1 << index))) | (data << index); + __REG(reg) = l; +} + +/*! + * Exported function to set a GPIO pin's data output + * @param pin a name defined by \b iomux_pin_name_t + * @param data value to be set (only 0 or 1 is valid) + */ + +void mxc_set_gpio_dataout(iomux_pin_name_t pin, u32 data) +{ + u32 port; + u32 gpio = IOMUX_TO_GPIO(pin); + + port = GPIO_TO_PORT(gpio); + _set_gpio_dataout(port, GPIO_TO_INDEX(gpio), (data == 0) ? 0 : 1); +} + diff --git a/cpu/arm926ejs/mx25/iomux.c b/cpu/arm926ejs/mx25/iomux.c new file mode 100644 index 0000000000..c0805d35c7 --- /dev/null +++ b/cpu/arm926ejs/mx25/iomux.c @@ -0,0 +1,153 @@ +/* + * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @defgroup GPIO_MX25 Board GPIO and Muxing Setup + * @ingroup MSL_MX25 + */ +/*! + * @file mach-mx25/iomux.c + * + * @brief I/O Muxing control functions + * + * @ingroup GPIO_MX25 + */ + +#include +#include +#include +#include + +/*! + * IOMUX register (base) addresses + */ +enum iomux_reg_addr { + IOMUXGPR = IOMUXC_BASE, + /*!< General purpose */ + IOMUXSW_MUX_CTL = IOMUXC_BASE + 0x008, + /*!< MUX control */ + IOMUXSW_MUX_END = IOMUXC_BASE + 0x228, + /*!< last MUX control register */ + IOMUXSW_PAD_CTL = IOMUXC_BASE + 0x22C, + /*!< Pad control */ + IOMUXSW_PAD_END = IOMUXC_BASE + 0x414, + /*!< last Pad control register */ + IOMUXSW_INPUT_CTL = IOMUXC_BASE + 0x460, + /*!< input select register */ + IOMUXSW_INPUT_END = IOMUXC_BASE + 0x580, + /*!< last input select register */ +}; + +#define MUX_PIN_NUM_MAX \ + (((IOMUXSW_MUX_END - IOMUXSW_MUX_CTL) >> 2) + 1) +#define MUX_INPUT_NUM_MUX \ + (((IOMUXSW_INPUT_END - IOMUXSW_INPUT_CTL) >> 2) + 1) + +#define PIN_TO_IOMUX_INDEX(pin) (PIN_TO_IOMUX_MUX(pin) >> 2) + +#define MUX_USED 0x80 + +/*! + * This function is used to configure a pin through the IOMUX module. + * FIXED ME: for backward compatible. Will be static function! + * @param pin a pin number as defined in \b #iomux_pin_name_t + * @param cfg an output function as defined in \b #iomux_pin_cfg_t + * + * @return 0 if successful; Non-zero otherwise + */ +static int iomux_config_mux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg) +{ + u32 mux_reg = PIN_TO_IOMUX_MUX(pin); + + if (mux_reg != NON_MUX_I) { + mux_reg += IOMUXGPR; + __REG(mux_reg) = cfg; + } + + return 0; +} + +/*! + * Request ownership for an IO pin. This function has to be the first one + * being called before that pin is used. The caller has to check the + * return value to make sure it returns 0. + * + * @param pin a name defined by \b iomux_pin_name_t + * @param cfg an input function as defined in \b #iomux_pin_cfg_t + * + * @return 0 if successful; Non-zero otherwise + */ +int mxc_request_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg) +{ + int ret = iomux_config_mux(pin, cfg); + return ret; +} + +/*! + * Release ownership for an IO pin + * + * @param pin a name defined by \b iomux_pin_name_t + * @param cfg an input function as defined in \b #iomux_pin_cfg_t + */ +void mxc_free_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg) +{ +} + +/*! + * This function configures the pad value for a IOMUX pin. + * + * @param pin a pin number as defined in \b #iomux_pin_name_t + * @param config the ORed value of elements defined in \b #iomux_pad_config_t + */ +void mxc_iomux_set_pad(iomux_pin_name_t pin, u32 config) +{ + u32 pad_reg = IOMUXGPR + PIN_TO_IOMUX_PAD(pin); + + __REG(pad_reg) = config; +} + +/*! + * This function enables/disables the general purpose function for a particular + * signal. + * + * @param gp one signal as defined in \b #iomux_gp_func_t + * @param en \b #true to enable; \b #false to disable + */ +void mxc_iomux_set_gpr(iomux_gp_func_t gp, int en) +{ + u32 l; + + l = __REG(IOMUXGPR); + if (en) + l |= gp; + else + l &= ~gp; + + __REG(IOMUXGPR) = l; +} + +/*! + * This function configures input path. + * + * @param input index of input select register as defined in \b + * #iomux_input_select_t + * @param config the binary value of elements defined in \b + * #iomux_input_config_t + */ +void mxc_iomux_set_input(iomux_input_select_t input, u32 config) +{ + u32 reg = IOMUXSW_INPUT_CTL + (input << 2); + + __REG(reg) = config; +} + diff --git a/cpu/arm926ejs/mx25/serial.c b/cpu/arm926ejs/mx25/serial.c new file mode 100644 index 0000000000..17a08c3037 --- /dev/null +++ b/cpu/arm926ejs/mx25/serial.c @@ -0,0 +1,231 @@ +/* + * (c) 2007 Sascha Hauer + * + * (C) Copyright 2009 Freescale Semiconductor + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#include + +#if defined CONFIG_MX25_UART + +#include + +#define __REG(x) (*((volatile u32 *)(x))) + +#ifdef CONFIG_MX25_UART1 +#define UART_PHYS 0x43f90000 +#else +#error "define CONFIG_MX25_UARTx to use the mx25 UART driver" +#endif + +/* Register definitions */ +#define URXD 0x0 /* Receiver Register */ +#define UTXD 0x40 /* Transmitter Register */ +#define UCR1 0x80 /* Control Register 1 */ +#define UCR2 0x84 /* Control Register 2 */ +#define UCR3 0x88 /* Control Register 3 */ +#define UCR4 0x8c /* Control Register 4 */ +#define UFCR 0x90 /* FIFO Control Register */ +#define USR1 0x94 /* Status Register 1 */ +#define USR2 0x98 /* Status Register 2 */ +#define UESC 0x9c /* Escape Character Register */ +#define UTIM 0xa0 /* Escape Timer Register */ +#define UBIR 0xa4 /* BRM Incremental Register */ +#define UBMR 0xa8 /* BRM Modulator Register */ +#define UBRC 0xac /* Baud Rate Count Register */ +#define UTS 0xb4 /* UART Test Register (mx25) */ + +/* UART Control Register Bit Fields.*/ +#define URXD_CHARRDY (1<<15) +#define URXD_ERR (1<<14) +#define URXD_OVRRUN (1<<13) +#define URXD_FRMERR (1<<12) +#define URXD_BRK (1<<11) +#define URXD_PRERR (1<<10) +#define URXD_RX_DATA (0xFF) +#define UCR1_ADEN (1<<15) /* Auto dectect interrupt */ +#define UCR1_ADBR (1<<14) /* Auto detect baud rate */ +#define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */ +#define UCR1_IDEN (1<<12) /* Idle condition interrupt */ +#define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */ +#define UCR1_RDMAEN (1<<8) /* Recv ready DMA enable */ +#define UCR1_IREN (1<<7) /* Infrared interface enable */ +#define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */ +#define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */ +#define UCR1_SNDBRK (1<<4) /* Send break */ +#define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */ +#define UCR1_UARTCLKEN (1<<2) /* UART clock enabled */ +#define UCR1_DOZE (1<<1) /* Doze */ +#define UCR1_UARTEN (1<<0) /* UART enabled */ +#define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */ +#define UCR2_IRTS (1<<14) /* Ignore RTS pin */ +#define UCR2_CTSC (1<<13) /* CTS pin control */ +#define UCR2_CTS (1<<12) /* Clear to send */ +#define UCR2_ESCEN (1<<11) /* Escape enable */ +#define UCR2_PREN (1<<8) /* Parity enable */ +#define UCR2_PROE (1<<7) /* Parity odd/even */ +#define UCR2_STPB (1<<6) /* Stop */ +#define UCR2_WS (1<<5) /* Word size */ +#define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */ +#define UCR2_TXEN (1<<2) /* Transmitter enabled */ +#define UCR2_RXEN (1<<1) /* Receiver enabled */ +#define UCR2_SRST (1<<0) /* SW reset */ +#define UCR3_DTREN (1<<13) /* DTR interrupt enable */ +#define UCR3_PARERREN (1<<12) /* Parity enable */ +#define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */ +#define UCR3_DSR (1<<10) /* Data set ready */ +#define UCR3_DCD (1<<9) /* Data carrier detect */ +#define UCR3_RI (1<<8) /* Ring indicator */ +#define UCR3_TIMEOUTEN (1<<7) /* Timeout interrupt enable */ +#define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */ +#define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */ +#define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */ +#define UCR3_REF25 (1<<3) /* Ref freq 25 MHz */ +#define UCR3_REF30 (1<<2) /* Ref Freq 30 MHz */ +#define UCR3_INVT (1<<1) /* Inverted Infrared transmission */ +#define UCR3_BPEN (1<<0) /* Preset registers enable */ +#define UCR4_CTSTL_32 (32<<10)/* CTS trigger level (32 chars) */ +#define UCR4_INVR (1<<9) /* Inverted infrared reception */ +#define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */ +#define UCR4_WKEN (1<<7) /* Wake interrupt enable */ +#define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */ +#define UCR4_IRSC (1<<5) /* IR special case */ +#define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */ +#define UCR4_BKEN (1<<2) /* Break condition interrupt enable */ +#define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */ +#define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */ +#define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */ +#define UFCR_RFDIV (7<<7) /* Reference freq divider mask */ +#define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */ +#define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */ +#define USR1_RTSS (1<<14) /* RTS pin status */ +#define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */ +#define USR1_RTSD (1<<12) /* RTS delta */ +#define USR1_ESCF (1<<11) /* Escape seq interrupt flag */ +#define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */ +#define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */ +#define USR1_TIMEOUT (1<<7) /* Receive timeout interrupt status */ +#define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */ +#define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */ +#define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */ +#define USR2_ADET (1<<15) /* Auto baud rate detect complete */ +#define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */ +#define USR2_DTRF (1<<13) /* DTR edge interrupt flag */ +#define USR2_IDLE (1<<12) /* Idle condition */ +#define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */ +#define USR2_WAKE (1<<7) /* Wake */ +#define USR2_RTSF (1<<4) /* RTS edge interrupt flag */ +#define USR2_TXDC (1<<3) /* Transmitter complete */ +#define USR2_BRCD (1<<2) /* Break condition */ +#define USR2_ORE (1<<1) /* Overrun error */ +#define USR2_RDR (1<<0) /* Recv data ready */ +#define UTS_FRCPERR (1<<13) /* Force parity error */ +#define UTS_LOOP (1<<12) /* Loop tx and rx */ +#define UTS_TXEMPTY (1<<6) /* TxFIFO empty */ +#define UTS_RXEMPTY (1<<5) /* RxFIFO empty */ +#define UTS_TXFULL (1<<4) /* TxFIFO full */ +#define UTS_RXFULL (1<<3) /* RxFIFO full */ +#define UTS_SOFTRST (1<<0) /* Software reset */ + +DECLARE_GLOBAL_DATA_PTR; + +void serial_setbrg(void) +{ + u32 clk = mx25_get_ipg_clk(); + + if (!gd->baudrate) + gd->baudrate = CONFIG_BAUDRATE; + + __REG(UART_PHYS + UFCR) = 4 << 7; /* divide input clock by 2 */ + __REG(UART_PHYS + UBIR) = 0xf; + __REG(UART_PHYS + UBMR) = clk / (2 * gd->baudrate); + +} + +int serial_getc(void) +{ + while (__REG(UART_PHYS + UTS) & UTS_RXEMPTY) + ; + + /* mask out status from upper word */ + return (__REG(UART_PHYS + URXD) & URXD_RX_DATA) + ; +} + +void serial_putc(const char c) +{ + __REG(UART_PHYS + UTXD) = c; + + /* wait for transmitter to be ready */ + while (!(__REG(UART_PHYS + UTS) & UTS_TXEMPTY)) + ; + + /* If \n, also do \r */ + if (c == '\n') + serial_putc('\r'); +} + +/* + * Test whether a character is in the RX buffer + */ +int serial_tstc(void) +{ + /* If receive fifo is empty, return false */ + if (__REG(UART_PHYS + UTS) & UTS_RXEMPTY) + return 0; + return 1; +} + +void serial_puts(const char *s) +{ + while (*s) + serial_putc(*s++); +} + +/* + * Initialise the serial port with the given baudrate. The settings + * are always 8 data bits, no parity, 1 stop bit, no start bits. + * + */ +int serial_init(void) +{ + __REG(UART_PHYS + UCR1) = 0x0; + __REG(UART_PHYS + UCR2) = 0x0; + + while (!(__REG(UART_PHYS + UCR2) & UCR2_SRST)) + ; + + __REG(UART_PHYS + UCR3) = 0x0704; + __REG(UART_PHYS + UCR4) = 0x8000; + __REG(UART_PHYS + UESC) = 0x002b; + __REG(UART_PHYS + UTIM) = 0x0; + + __REG(UART_PHYS + UTS) = 0x0; + + serial_setbrg(); + + __REG(UART_PHYS + UCR2) = UCR2_WS | UCR2_IRTS | UCR2_RXEN | + UCR2_TXEN | UCR2_SRST; + + __REG(UART_PHYS + UCR1) = UCR1_UARTEN; + + return 0; +} + + +#endif /* CONFIG_MX25 */ diff --git a/cpu/arm926ejs/mx25/timer.c b/cpu/arm926ejs/mx25/timer.c new file mode 100644 index 0000000000..34c28e15b6 --- /dev/null +++ b/cpu/arm926ejs/mx25/timer.c @@ -0,0 +1,132 @@ +/* + * (C) Copyright 2007 + * Sascha Hauer, Pengutronix + * + * (C) Copyright 2009 Freescale Semiconductor + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +/* General purpose timers registers */ +#define GPTCR __REG(GPT1_BASE) /* Control register */ +#define GPTPR __REG(GPT1_BASE + 0x4) /* Prescaler register */ +#define GPTSR __REG(GPT1_BASE + 0x8) /* Status register */ +#define GPTCNT __REG(GPT1_BASE + 0x24) /* Counter register */ + +/* General purpose timers bitfields */ +#define GPTCR_SWR (1<<15) /* Software reset */ +#define GPTCR_FRR (1<<9) /* Freerun / restart */ +#define GPTCR_CLKSOURCE_32 (0x100<<6) /* Clock source */ +#define GPTCR_CLKSOURCE_IPG (0x001<<6) /* Clock source */ +#define GPTCR_TEN (1) /* Timer enable */ +#define GPTPR_VAL (66) + +static inline void setup_gpt() +{ + int i; + static int init_done; + + if (init_done) + return; + + init_done = 1; + + /* setup GP Timer 1 */ + GPTCR = GPTCR_SWR; + for (i = 0; i < 100; i++) + GPTCR = 0; /* We have no udelay by now */ + GPTPR = GPTPR_VAL; /* 66Mhz / 66 */ + /* Freerun Mode, PERCLK1 input */ + GPTCR |= GPTCR_CLKSOURCE_IPG | GPTCR_TEN; +} + +int timer_init(void) +{ + setup_gpt(); + + return 0; +} + +void reset_timer_masked(void) +{ + GPTCR = 0; + /* Freerun Mode, PERCLK1 input */ + GPTCR = GPTCR_CLKSOURCE_IPG | GPTCR_TEN; +} + +inline ulong get_timer_masked(void) +{ + ulong val = GPTCNT; + + return val; +} + +void reset_timer(void) +{ + reset_timer_masked(); +} + +ulong get_timer(ulong base) +{ + ulong tmp; + + tmp = get_timer_masked(); + + if (tmp <= (base * 1000)) { + /* Overflow */ + tmp += (0xffffffff - base); + } + + return (tmp / 1000) - base; +} + +void set_timer(ulong t) +{ +} + +/* delay x useconds AND perserve advance timstamp value */ +/* GPTCNT is now supposed to tick 1 by 1 us. */ +void udelay(unsigned long usec) +{ + ulong tmp; + + setup_gpt(); + + tmp = get_timer_masked(); /* get current timestamp */ + + /* if setting this forward will roll time stamp */ + if ((usec + tmp + 1) < tmp) { + /* reset "advancing" timestamp to 0, set lastinc value */ + reset_timer_masked(); + } else { + /* else, set advancing stamp wake up time */ + tmp += usec; + } + + while (get_timer_masked() < tmp) /* loop till event */ + /*NOP*/; +} + +void reset_cpu(ulong addr) +{ + __REG16(WDOG_BASE) = 4; +} diff --git a/cpu/arm926ejs/mx28/Makefile b/cpu/arm926ejs/mx28/Makefile new file mode 100644 index 0000000000..9f2d5e5909 --- /dev/null +++ b/cpu/arm926ejs/mx28/Makefile @@ -0,0 +1,47 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(SOC).a + +COBJS = timer.o serial.o generic.o pinctrl.o mmcops.o +SOBJS = reset.o + +SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) +START := $(addprefix $(obj),$(START)) + +all: $(obj).depend $(LIB) + +$(LIB): $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/cpu/arm926ejs/mx28/config.mk b/cpu/arm926ejs/mx28/config.mk new file mode 100644 index 0000000000..ca2cae181b --- /dev/null +++ b/cpu/arm926ejs/mx28/config.mk @@ -0,0 +1,2 @@ +PLATFORM_CPPFLAGS += -march=armv5te +PLATFORM_CPPFLAGS += $(call cc-option,-mtune=arm926ejs,) diff --git a/cpu/arm926ejs/mx28/generic.c b/cpu/arm926ejs/mx28/generic.c new file mode 100644 index 0000000000..e857452753 --- /dev/null +++ b/cpu/arm926ejs/mx28/generic.c @@ -0,0 +1,298 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include + +#define MXS_MODULE_SFTRST (1 << 31) +#define MXS_MODULE_CLKGATE (1 << 30) + +static inline void __mxs_clrl(u32 mask, volatile void *addr) +{ + __raw_writel(mask, addr + MXS_CLR_ADDR); +} + +static inline void __mxs_setl(u32 mask, volatile void *addr) +{ + __raw_writel(mask, addr + MXS_SET_ADDR); +} + +/* + * Clear the bit and poll it cleared. This is usually called with + * a reset address and mask being either SFTRST(bit 31) or CLKGATE + * (bit 30). + */ +static int clear_poll_bit(volatile void *addr, u32 mask) +{ + int timeout = 0x400; + + /* clear the bit */ + __mxs_clrl(mask, addr); + + /* + * SFTRST needs 3 GPMI clocks to settle, the reference manual + * recommends to wait 1us. + */ + udelay(1); + + /* poll the bit becoming clear */ + while ((__raw_readl(addr) & mask) && --timeout) + udelay(1); + + return !timeout; +} + +int mxs_reset_block(volatile void *reset_addr) +{ + int ret; + int timeout = 0x400000; + + /* clear and poll SFTRST */ + ret = clear_poll_bit(reset_addr, MXS_MODULE_SFTRST); + if (ret) + goto error; + + /* clear CLKGATE */ + __mxs_clrl(MXS_MODULE_CLKGATE, reset_addr); + + /* set SFTRST to reset the block */ + __mxs_setl(MXS_MODULE_SFTRST, reset_addr); + udelay(1); + + /* poll CLKGATE becoming set */ + while ((!(__raw_readl(reset_addr) & MXS_MODULE_CLKGATE)) && --timeout) + udelay(1); + + if (!timeout) + goto error; + + /* clear and poll SFTRST */ + ret = clear_poll_bit(reset_addr, MXS_MODULE_SFTRST); + if (ret) + goto error; + + /* clear and poll CLKGATE */ + ret = clear_poll_bit(reset_addr, MXS_MODULE_CLKGATE); + if (ret) + goto error; + + return 0; + +error: + printf("%s(%p): module reset timeout\n", __func__, reset_addr); + return -ETIMEDOUT; +} + +static u32 mx28_get_pclk(void) +{ + const u32 xtal = 24, ref = 480; + u32 clkfrac, clkseq, clkctrl; + u32 frac, div; + u32 pclk; + + clkfrac = REG_RD(REGS_CLKCTRL_BASE, HW_CLKCTRL_FRAC0); + clkseq = REG_RD(REGS_CLKCTRL_BASE, HW_CLKCTRL_CLKSEQ); + clkctrl = REG_RD(REGS_CLKCTRL_BASE, HW_CLKCTRL_CPU); + + if (clkctrl & (BM_CLKCTRL_CPU_DIV_XTAL_FRAC_EN | + BM_CLKCTRL_CPU_DIV_CPU_FRAC_EN)) { + /* No support of fractional divider calculation */ + pclk = 0; + } else { + if (clkseq & BM_CLKCTRL_CLKSEQ_BYPASS_CPU) { + /* xtal path */ + div = (clkctrl & BM_CLKCTRL_CPU_DIV_XTAL) >> + BP_CLKCTRL_CPU_DIV_XTAL; + pclk = xtal / div; + } else { + /* ref path */ + frac = (clkfrac & BM_CLKCTRL_FRAC0_CPUFRAC) >> + BP_CLKCTRL_FRAC0_CPUFRAC; + div = (clkctrl & BM_CLKCTRL_CPU_DIV_CPU) >> + BP_CLKCTRL_CPU_DIV_CPU; + pclk = (ref * 18 / frac) / div; + } + } + + return pclk; +} + +static u32 mx28_get_hclk(void) +{ + u32 clkctrl, div, hclk; + + clkctrl = REG_RD(REGS_CLKCTRL_BASE, HW_CLKCTRL_HBUS); + + if (clkctrl & BM_CLKCTRL_HBUS_DIV_FRAC_EN) { + /* No support of fractional divider calculation */ + hclk = 0; + } else { + div = (clkctrl & BM_CLKCTRL_HBUS_DIV) >> + BP_CLKCTRL_HBUS_DIV; + hclk = mx28_get_pclk() / div; + } + + return hclk; +} + +static u32 mx28_get_emiclk(void) +{ + const u32 xtal = 24, ref = 480; + u32 clkfrac, clkseq, clkctrl; + u32 frac, div; + u32 emiclk; + + clkfrac = REG_RD(REGS_CLKCTRL_BASE, HW_CLKCTRL_FRAC0); + clkseq = REG_RD(REGS_CLKCTRL_BASE, HW_CLKCTRL_CLKSEQ); + clkctrl = REG_RD(REGS_CLKCTRL_BASE, HW_CLKCTRL_EMI); + + if (clkseq & BM_CLKCTRL_CLKSEQ_BYPASS_EMI) { + /* xtal path */ + div = (clkctrl & BM_CLKCTRL_EMI_DIV_XTAL) >> + BP_CLKCTRL_EMI_DIV_XTAL; + emiclk = xtal / div; + } else { + /* ref path */ + frac = (clkfrac & BM_CLKCTRL_FRAC0_EMIFRAC) >> + BP_CLKCTRL_FRAC0_EMIFRAC; + div = (clkctrl & BM_CLKCTRL_EMI_DIV_EMI) >> + BP_CLKCTRL_EMI_DIV_EMI; + emiclk = (ref * 18 / frac) / div; + } + + return emiclk; +} + +static inline void __enable_gpmi_clk(void) +{ + /* Clear bypass bit*/ + REG_SET(REGS_CLKCTRL_BASE, HW_CLKCTRL_CLKSEQ, + BM_CLKCTRL_CLKSEQ_BYPASS_GPMI); + /* Set gpmi clock to ref_gpmi/12 */ + REG_WR(REGS_CLKCTRL_BASE, HW_CLKCTRL_GPMI, + (REG_RD(REGS_CLKCTRL_BASE, HW_CLKCTRL_GPMI) & + (~(BM_CLKCTRL_GPMI_DIV | + ~BM_CLKCTRL_GPMI_CLKGATE))) | + 1); +} + +static u32 mx28_get_gpmiclk(void) +{ + const u32 xtal = 24, ref = 480; + u32 clkfrac, clkseq, clkctrl; + u32 frac, div; + u32 gpmiclk; + /* Enable gpmi clock */ + __enable_gpmi_clk(); + + clkfrac = REG_RD(REGS_CLKCTRL_BASE, HW_CLKCTRL_FRAC1); + clkseq = REG_RD(REGS_CLKCTRL_BASE, HW_CLKCTRL_CLKSEQ); + clkctrl = REG_RD(REGS_CLKCTRL_BASE, HW_CLKCTRL_GPMI); + + if (clkseq & BM_CLKCTRL_CLKSEQ_BYPASS_GPMI) { + /* xtal path */ + div = (clkctrl & BM_CLKCTRL_GPMI_DIV) >> + BP_CLKCTRL_GPMI_DIV; + gpmiclk = xtal / div; + } else { + /* ref path */ + frac = (clkfrac & BM_CLKCTRL_FRAC1_GPMIFRAC) >> + BP_CLKCTRL_FRAC1_GPMIFRAC; + div = (clkctrl & BM_CLKCTRL_GPMI_DIV) >> + BP_CLKCTRL_GPMI_DIV; + gpmiclk = (ref * 18 / frac) / div; + } + + return gpmiclk; +} + +u32 mxc_get_clock(enum mxc_clock clk) +{ + switch (clk) { + case MXC_ARM_CLK: + return mx28_get_pclk() * 1000000; + case MXC_GPMI_CLK: + return mx28_get_gpmiclk() * 1000000; + case MXC_AHB_CLK: + case MXC_IPG_CLK: + return mx28_get_hclk() * 1000000; + } + + return 0; +} + +#if defined(CONFIG_ARCH_CPU_INIT) +int arch_cpu_init(void) +{ + icache_enable(); + dcache_enable(); + + return 0; +} +#endif + +#if defined(CONFIG_DISPLAY_CPUINFO) +int print_cpuinfo(void) +{ + printf("Freescale i.MX28 family\n"); + printf("CPU: %d MHz\n", mx28_get_pclk()); + printf("BUS: %d MHz\n", mx28_get_hclk()); + printf("EMI: %d MHz\n", mx28_get_emiclk()); + printf("GPMI: %d MHz\n", mx28_get_gpmiclk()); + return 0; +} +#endif + +/* + * Initializes on-chip ethernet controllers. + */ +int cpu_eth_init(bd_t *bis) +{ + int rc = ENODEV; +#if defined(CONFIG_MXC_FEC) + rc = mxc_fec_initialize(bis); + + /* Turn on ENET clocks */ + REG_WR(REGS_CLKCTRL_BASE, HW_CLKCTRL_ENET, + REG_RD(REGS_CLKCTRL_BASE, HW_CLKCTRL_ENET) & + ~(BM_CLKCTRL_ENET_SLEEP | BM_CLKCTRL_ENET_DISABLE)); + + /* Set up ENET PLL for 50 MHz */ + REG_SET(REGS_CLKCTRL_BASE, HW_CLKCTRL_PLL2CTRL0, + BM_CLKCTRL_PLL2CTRL0_POWER); /* Power on ENET PLL */ + udelay(10); /* Wait 10 us */ + REG_CLR(REGS_CLKCTRL_BASE, HW_CLKCTRL_PLL2CTRL0, + BM_CLKCTRL_PLL2CTRL0_CLKGATE); /* Gate on ENET PLL */ + REG_WR(REGS_CLKCTRL_BASE, HW_CLKCTRL_ENET, + REG_RD(REGS_CLKCTRL_BASE, HW_CLKCTRL_ENET) | + BM_CLKCTRL_ENET_CLK_OUT_EN); /* Enable pad output */ + + /* Board level init */ + enet_board_init(); +#endif + return rc; +} + diff --git a/cpu/arm926ejs/mx28/mmcops.c b/cpu/arm926ejs/mx28/mmcops.c new file mode 100644 index 0000000000..e1d211b651 --- /dev/null +++ b/cpu/arm926ejs/mx28/mmcops.c @@ -0,0 +1,555 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include +#include +#include +#include + +#ifdef CONFIG_GENERIC_MMC +#define MMCOPS_DEBUG + +#define MBR_SIGNATURE 0xaa55 +#define MBR_SECTOR_COUNT (CONFIG_ENV_OFFSET >> 9) +/* 1. RSV partition (env and uImage) */ +#define RSVPART_SECTOR_OFFSET (MBR_SECTOR_COUNT) +#define RSVPART_SECTOR_COUNT 0x3ffe /* 8 MB */ +/* 2. FAT partition */ +#define FATPART_FILESYS 0xb +#define FATPART_SECTOR_OFFSET (RSVPART_SECTOR_OFFSET + RSVPART_SECTOR_COUNT) +#define FATPART_SECTOR_COUNT 0x10000 /* 32 MB (minimal) */ +/* 3. EXT partition */ +#define EXTPART_FILESYS 0x83 +#define EXTPART_SECTOR_COUNT 0xc0000 /* 384 MB */ +/* 4. SB partition (uboot.sb or linux.sb) */ +#define SBPART_FILESYS 'S' +#define SBPART_SECTOR_COUNT 0x4000 /* 8 MB */ +#define CB_SIGNATURE 0x00112233 +#define CB_SECTOR_COUNT 2 + +#define MAX_CYLINDERS 1024 +#define MAX_HEADS 256 +#define MAX_SECTORS 63 + +struct partition { + u8 boot_flag; + u8 start_head; + u8 start_sector; + u8 start_cylinder; + u8 file_system; + u8 end_head; + u8 end_sector; + u8 end_cylinder; + u32 sector_offset; + u32 sector_count; +} __attribute__ ((__packed__)); + +struct partition_table { + u8 reserved[446]; + struct partition partitions[4]; + u16 signature; +}; + +struct drive_info { + u32 chip_num; + u32 drive_type; + u32 drive_tag; + u32 sector_offset; + u32 sector_count; +}; + +struct config_block { + u32 signature; + u32 primary_tag; + u32 secondary_tag; + u32 num_copies; + struct drive_info drive_info[2]; +}; + +static int mmc_format(int dev) +{ + int rc = 0; + u8 *buf = 0; + u32 i, cnt, total_sectors; + u32 offset[4]; + struct config_block *cb; + struct partition_table *mbr; + struct mmc *mmc = find_mmc_device(dev); + + /* Warning */ + printf("WARN: Data on card will get lost with format.\n" + "Continue? (y/n)"); + char ch = getc(); + printf("\n"); + if (ch != 'y') { + rc = -1; + goto out; + } + + /* Allocate sector buffer */ + buf = malloc(mmc->read_bl_len); + if (!buf) { + printf("%s[%d]: malloc error\n", __func__, __LINE__); + rc = -1; + goto out; + } + memset(buf, 0, mmc->read_bl_len); + + /* Erase the first sector of each partition */ + cnt = mmc->block_dev.block_read(dev, 0, 1, buf); + if (cnt != 1) { + printf("%s[%d]: read mmc error\n", __func__, __LINE__); + rc = -1; + goto out; + } + mbr = (struct partition_table *)buf; + if (mbr->signature == MBR_SIGNATURE) { + /* Get sector offset of each partition */ + for (i = 0; i < 4; i++) + offset[i] = mbr->partitions[i].sector_offset; + /* Erase */ + memset(buf, 0, mmc->read_bl_len); + for (i = 0; i < 4; i++) { + if (offset[i] > 0) { + cnt = mmc->block_dev.block_write(dev, + offset[i], 1, buf); + if (cnt != 1) { + printf("%s[%d]: write mmc error\n", + __func__, __LINE__); + rc = -1; + goto out; + } + } + } + } + + /* Get total sectors */ + total_sectors = mmc->capacity >> 9; + if (RSVPART_SECTOR_COUNT + SBPART_SECTOR_COUNT > total_sectors) { + printf("Card capacity is too low to format\n"); + rc = -1; + goto out; + } + + /* Write config block */ + cb = (struct config_block *)buf; + cb->signature = CB_SIGNATURE; + cb->num_copies = 2; + cb->primary_tag = 0x1; + cb->secondary_tag = 0x2; + cb->drive_info[0].chip_num = 0; + cb->drive_info[0].drive_type = 0; + cb->drive_info[0].drive_tag = 0x1; + cb->drive_info[0].sector_count = SBPART_SECTOR_COUNT - CB_SECTOR_COUNT; + cb->drive_info[0].sector_offset = + total_sectors - cb->drive_info[0].sector_count; + cb->drive_info[1].chip_num = 0; + cb->drive_info[1].drive_type = 0; + cb->drive_info[1].drive_tag = 0x2; + cb->drive_info[1].sector_count = SBPART_SECTOR_COUNT - CB_SECTOR_COUNT; + cb->drive_info[1].sector_offset = + total_sectors - cb->drive_info[1].sector_count; + + cnt = mmc->block_dev.block_write(dev, + total_sectors - SBPART_SECTOR_COUNT, 1, (void *)cb); + if (cnt != 1) { + printf("%s[%d]: write mmc error\n", __func__, __LINE__); + rc = -1; + goto out; + } + + /* Prepare for MBR */ + memset(buf, 0, mmc->read_bl_len); + mbr = (struct partition_table *)buf; + + /* RSV partition */ + mbr->partitions[0].sector_offset = RSVPART_SECTOR_OFFSET; + mbr->partitions[0].sector_count = RSVPART_SECTOR_COUNT; + + /* SB partition */ + mbr->partitions[3].file_system = SBPART_FILESYS; + mbr->partitions[3].sector_offset = total_sectors - SBPART_SECTOR_COUNT; + mbr->partitions[3].sector_count = SBPART_SECTOR_COUNT; + + /* EXT partition */ + if (EXTPART_SECTOR_COUNT + SBPART_SECTOR_COUNT + + RSVPART_SECTOR_COUNT > total_sectors) { +#ifdef MMCOPS_DEBUG + printf("No room for EXT partition\n"); +#endif + } else { + mbr->partitions[2].file_system = EXTPART_FILESYS; + mbr->partitions[2].sector_offset = total_sectors - + SBPART_SECTOR_COUNT - EXTPART_SECTOR_COUNT; + mbr->partitions[2].sector_count = EXTPART_SECTOR_COUNT; + } + + /* FAT partition */ + if (FATPART_SECTOR_COUNT + MBR_SECTOR_COUNT + + mbr->partitions[0].sector_count + + mbr->partitions[2].sector_count + + mbr->partitions[3].sector_count > total_sectors) { +#ifdef MMCOPS_DEBUG + printf("No room for FAT partition\n"); +#endif + goto out; + } + mbr->partitions[1].file_system = FATPART_FILESYS; + mbr->partitions[1].sector_offset = FATPART_SECTOR_OFFSET; + mbr->partitions[1].sector_count = total_sectors - MBR_SECTOR_COUNT - + mbr->partitions[0].sector_count - + mbr->partitions[2].sector_count - + mbr->partitions[3].sector_count; + +out: + if (rc == 0) { + /* Write MBR */ + mbr->signature = MBR_SIGNATURE; + cnt = mmc->block_dev.block_write(dev, 0, 1, (void *)mbr); + if (cnt != 1) { + printf("%s[%d]: write mmc error\n", __func__, __LINE__); + rc = -1; + } else + printf("Done.\n"); + } + + if (!buf) + free(buf); + return rc; +} + +static int install_sbimage(int dev, void *addr, u32 size) +{ + int rc = 0; + u8 *buf = 0; + u32 cnt, offset, cb_offset, sectors, not_format = 0; + struct config_block *cb; + struct partition_table *mbr; + struct mmc *mmc = find_mmc_device(dev); + + /* Allocate sector buffer */ + buf = malloc(mmc->read_bl_len); + if (!buf) { + printf("%s[%d]: malloc error\n", __func__, __LINE__); + rc = -1; + goto out; + } + + /* Check partition */ + offset = 0; + cnt = mmc->block_dev.block_read(dev, offset, 1, buf); + if (cnt != 1) { + printf("%s[%d]: read mmc error\n", __func__, __LINE__); + rc = -1; + goto out; + } + mbr = (struct partition_table *)buf; + if ((mbr->signature != MBR_SIGNATURE) || + (mbr->partitions[3].file_system != SBPART_FILESYS)) + not_format = 1; + + /* Check config block */ + offset = mbr->partitions[3].sector_offset; + cb_offset = offset; /* Save for later use */ + cnt = mmc->block_dev.block_read(dev, offset, 1, buf); + if (cnt != 1) { + printf("%s[%d]: read mmc error\n", __func__, __LINE__); + rc = -1; + goto out; + } + cb = (struct config_block *)buf; + if (cb->signature != CB_SIGNATURE) + not_format = 1; + + /* Not formatted */ + if (not_format) { + printf("Card is not formatted yet\n"); + rc = -1; + goto out; + } + + /* Calculate sectors of image */ + sectors = size / mmc->read_bl_len; + if (size % mmc->read_bl_len) + sectors++; + + /* Write image */ + offset = cb->drive_info[0].sector_offset; + cnt = mmc->block_dev.block_write(dev, offset, sectors, addr); + if (cnt != sectors) { + printf("%s[%d]: write mmc error\n", __func__, __LINE__); + rc = -1; + goto out; + } + /* Verify */ + cnt = mmc->block_dev.block_read(dev, offset, sectors, + addr + sectors * mmc->read_bl_len); + if (cnt != sectors) { + printf("%s[%d]: read mmc error\n", __func__, __LINE__); + rc = -1; + goto out; + } + if (memcmp(addr, addr + sectors * mmc->read_bl_len, + sectors * mmc->read_bl_len)) { + printf("Verifying sbImage write fails\n"); + rc = -1; + goto out; + } + + /* Redundant one */ + offset += sectors; + cnt = mmc->block_dev.block_write(dev, offset, sectors, addr); + if (cnt != sectors) { + printf("%s[%d]: write mmc error\n", __func__, __LINE__); + rc = -1; + goto out; + } + /* Verify */ + cnt = mmc->block_dev.block_read(dev, offset, sectors, + addr + sectors * mmc->read_bl_len); + if (cnt != sectors) { + printf("%s[%d]: read mmc error\n", __func__, __LINE__); + rc = -1; + goto out; + } + if (memcmp(addr, addr + sectors * mmc->read_bl_len, + sectors * mmc->read_bl_len)) { + printf("Verifying redundant sbImage write fails"); + rc = -1; + goto out; + } + + /* Update config block */ + cb->drive_info[0].sector_count = sectors; + cb->drive_info[1].sector_count = sectors; + cb->drive_info[1].sector_offset = offset; + cnt = mmc->block_dev.block_write(dev, cb_offset, 1, (void *)cb); + if (cnt != 1) { + printf("%s[%d]: write mmc error\n", __func__, __LINE__); + rc = -1; + goto out; + } + + /* Done */ + printf("Done: %d (%x hex) sectors written at %d (%x hex)\n", + sectors, sectors, offset - sectors, offset - sectors); + +out: + if (!buf) + free(buf); + return rc; +} + +static int install_uimage(int dev, void *addr, u32 size) +{ + int rc = 0; + u8 *buf = 0; + u32 cnt, offset, sectors; + struct partition_table *mbr; + struct mmc *mmc = find_mmc_device(dev); + + /* Calculate sectors of uImage */ + sectors = size / mmc->read_bl_len; + if (size % mmc->read_bl_len) + sectors++; + + /* Allocate sector buffer */ + buf = malloc(mmc->read_bl_len); + if (!buf) { + printf("%s[%d]: malloc error\n", __func__, __LINE__); + rc = -1; + goto out; + } + + /* Check partition */ + offset = 0; + cnt = mmc->block_dev.block_read(dev, offset, 1, buf); + if (cnt != 1) { + printf("%s[%d]: read mmc error\n", __func__, __LINE__); + rc = -1; + goto out; + } + mbr = (struct partition_table *)buf; + if (mbr->signature != MBR_SIGNATURE) { + printf("No valid partition table\n"); + rc = -1; + goto out; + } + if (mbr->partitions[0].sector_count < sectors) { + printf("No enough uImage partition room\n"); + rc = -1; + goto out; + } + + /* Write uImage */ + offset = mbr->partitions[0].sector_offset + (CONFIG_ENV_SIZE >> 9); + cnt = mmc->block_dev.block_write(dev, offset, sectors, addr); + if (cnt != sectors) { + printf("%s[%d]: write mmc error\n", __func__, __LINE__); + rc = -1; + goto out; + } + /* Verify */ + cnt = mmc->block_dev.block_read(dev, offset, sectors, + addr + sectors * mmc->read_bl_len); + if (cnt != sectors) { + printf("%s[%d]: read mmc error\n", __func__, __LINE__); + rc = -1; + goto out; + } + if (memcmp(addr, addr + sectors * mmc->read_bl_len, + sectors * mmc->read_bl_len)) { + printf("Verifying uImage write fails"); + rc = -1; + goto out; + } + + /* Done */ + printf("Done: %d (%x hex) sectors written at %d (%x hex)\n", + sectors, sectors, offset, offset); + +out: + if (!buf) + free(buf); + return rc; +} + +static int install_rootfs(int dev, void *addr, u32 size) +{ + int rc = 0; + u8 *buf = 0; + u32 cnt, offset, sectors; + struct partition_table *mbr; + struct mmc *mmc = find_mmc_device(dev); + + /* Calculate sectors of rootfs */ + sectors = size / mmc->read_bl_len; + if (size % mmc->read_bl_len) + sectors++; + + /* Allocate sector buffer */ + buf = malloc(mmc->read_bl_len); + if (!buf) { + printf("%s[%d]: malloc error\n", __func__, __LINE__); + rc = -1; + goto out; + } + + /* Check partition */ + offset = 0; + cnt = mmc->block_dev.block_read(dev, offset, 1, buf); + if (cnt != 1) { + printf("%s[%d]: read mmc error\n", __func__, __LINE__); + rc = -1; + goto out; + } + mbr = (struct partition_table *)buf; + if ((mbr->signature != MBR_SIGNATURE) || + (mbr->partitions[2].file_system != EXTPART_FILESYS)) { + printf("No rootfs partition\n"); + rc = -1; + goto out; + } + if (mbr->partitions[2].sector_count < sectors) { + printf("No enough rootfs partition room\n"); + rc = -1; + goto out; + } + + /* Write rootfs */ + offset = mbr->partitions[2].sector_offset; + cnt = mmc->block_dev.block_write(dev, offset, sectors, addr); + if (cnt != sectors) { + printf("%s[%d]: write mmc error\n", __func__, __LINE__); + rc = -1; + goto out; + } + + /* Done */ + printf("Done: %d (%x hex) sectors written at %d (%x hex)\n", + sectors, sectors, offset, offset); + +out: + if (!buf) + free(buf); + return rc; +} + +int do_mxs_mmcops(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + int dev = 0; + struct mmc *mmc; + + if (argc < 2) + goto err_out; + + if (strcmp(argv[1], "format") && + strcmp(argv[1], "install")) + goto err_out; + + if (argc == 2) { /* list */ + print_mmc_devices('\n'); + return 0; + } + + /* Find and init mmc */ + dev = simple_strtoul(argv[2], NULL, 10); + mmc = find_mmc_device(dev); + if (!mmc) { + printf("%s[%d]: find mmc error\n", __func__, __LINE__); + return -1; + } + if (mmc_init(mmc)) { + printf("%s[%d]: init mmc error\n", __func__, __LINE__); + return -1; + } + + if (!strcmp(argv[1], "format")) + mmc_format(dev); + if (argc == 3) /* rescan (mmc_init) */ + return 0; + + if (argc != 6) + goto err_out; + + if (!strcmp(argv[1], "install")) { + void *addr = (void *)simple_strtoul(argv[3], NULL, 16); + u32 size = simple_strtoul(argv[4], NULL, 16); + + if (!strcmp(argv[5], "sbImage")) + return install_sbimage(dev, addr, size); + else if (!strcmp(argv[5], "uImage")) + return install_uimage(dev, addr, size); + else if (!strcmp(argv[5], "rootfs")) + return install_rootfs(dev, addr, size); + } + +err_out: + printf("Usage:\n%s\n", cmdtp->usage); + return -1; +} + +U_BOOT_CMD( + mxs_mmc, 6, 1, do_mxs_mmcops, + "MXS specific MMC sub system", + "mxs_mmc format \n" + "mxs_mmc install addr size sbImage/uImage/rootfs\n"); +#endif /* CONFIG_GENERIC_MMC */ diff --git a/cpu/arm926ejs/mx28/pinctrl.c b/cpu/arm926ejs/mx28/pinctrl.c new file mode 100644 index 0000000000..cca7d462ca --- /dev/null +++ b/cpu/arm926ejs/mx28/pinctrl.c @@ -0,0 +1,141 @@ +/* + * + * (C) Copyright 2009-2010 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#include +#include +#include + +void pin_gpio_direction(u32 id, u32 output) +{ + u32 addr; + u32 bank = PINID_2_BANK(id); + u32 pin = PINID_2_PIN(id); + + addr = REGS_PINCTRL_BASE + HW_PINCTRL_DOE0; + addr += 0x10 * bank; + if (output) + REG_SET_ADDR(addr, 1 << pin); + else + REG_CLR_ADDR(addr, 1 << pin); +} + +u32 pin_gpio_get(u32 id) +{ + u32 addr, val; + u32 bank = PINID_2_BANK(id); + u32 pin = PINID_2_PIN(id); + + addr = REGS_PINCTRL_BASE + HW_PINCTRL_DIN0; + addr += 0x10 * bank; + val = REG_RD_ADDR(addr); + + return !!(val & (1 << pin)); +} + +void pin_gpio_set(u32 id, u32 val) +{ + u32 addr; + u32 bank = PINID_2_BANK(id); + u32 pin = PINID_2_PIN(id); + + addr = REGS_PINCTRL_BASE + HW_PINCTRL_DOUT0; + addr += 0x10 * bank; + if (val) + REG_SET_ADDR(addr, 1 << pin); + else + REG_CLR_ADDR(addr, 1 << pin); +} + +void pin_set_strength(u32 id, enum pad_strength strength) +{ + u32 addr; + u32 bank = PINID_2_BANK(id); + u32 pin = PINID_2_PIN(id); + u32 val; + + addr = REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE0; + addr += 0x40 * bank + 0x10 * (pin >> 3); + pin &= 0x7; + + /* Don't use REG_CLR_ADDR/REG_SET_ADDR to prevent unwanted pin state transitions */ + val = REG_RD_ADDR(addr); + val &= ~(0x7 << (pin * 4)); + val |= (strength & 0x7) << (pin * 4); + REG_WR_ADDR(addr, val); +} + +void pin_set_voltage(u32 id, enum pad_voltage volt) +{ + u32 addr; + u32 bank = PINID_2_BANK(id); + u32 pin = PINID_2_PIN(id); + + addr = REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE0; + addr += 0x40 * bank + 0x10 * (pin >> 3); + pin &= 0x7; + if (volt == PAD_1V8) + REG_CLR_ADDR(addr, 1 << (pin * 4 + 2)); + else + REG_SET_ADDR(addr, 1 << (pin * 4 + 2)); +} + +void pin_set_pullup(u32 id, u32 pullup) +{ + u32 addr; + u32 bank = PINID_2_BANK(id); + u32 pin = PINID_2_PIN(id); + + addr = REGS_PINCTRL_BASE + HW_PINCTRL_PULL0; + addr += 0x10 * bank; + if (pullup) + REG_SET_ADDR(addr, 1 << pin); + else + REG_CLR_ADDR(addr, 1 << pin); +} + +void pin_set_type(u32 id, enum pin_fun cfg) +{ + u32 addr; + u32 bank = PINID_2_BANK(id); + u32 pin = PINID_2_PIN(id); + u32 val; + + addr = REGS_PINCTRL_BASE + HW_PINCTRL_MUXSEL0; + addr += 0x20 * bank + 0x10 * (pin >> 4); + pin &= 0xf; + + /* Don't use _CLR/_SET to prevent unwanted pin state transitions */ + val = REG_RD_ADDR(addr); + val &= ~(0x3 << (pin * 2)); + val |= (cfg & 0x3) << (pin * 2); + REG_WR_ADDR(addr, val); +} + +void pin_set_group(struct pin_group *pin_group) +{ + u32 p; + struct pin_desc *pin; + + for (p = 0; p < pin_group->nr_pins; p++) { + pin = &pin_group->pins[p]; + pin_set_type(pin->id, pin->fun); + pin_set_strength(pin->id, pin->strength); + pin_set_voltage(pin->id, pin->voltage); + pin_set_pullup(pin->id, pin->pullup); + } +} diff --git a/cpu/arm926ejs/mx28/reset.S b/cpu/arm926ejs/mx28/reset.S new file mode 100644 index 0000000000..c8596e5457 --- /dev/null +++ b/cpu/arm926ejs/mx28/reset.S @@ -0,0 +1,44 @@ +/* + * Processor reset for Freescale i.MX28 SoC. + * + * Copyright (C) 2007 Sergey Kubushyn + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * ----------------------------------------------------- + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +.globl reset_cpu +reset_cpu: + ldr r0, POWER_CHARGE + mov r1, #0x0 + str r1, [r0] + ldr r0, POWER_MINPWR + str r1, [r0] + ldr r0, CLKCTRL_RESET + mov r1, #0x1 + str r1, [r0] +_loop_forever: + b _loop_forever + +POWER_MINPWR: + .word 0x80044020 +POWER_CHARGE: + .word 0x80044030 +CLKCTRL_RESET: + .word 0x800401e0 + diff --git a/cpu/arm926ejs/mx28/serial.c b/cpu/arm926ejs/mx28/serial.c new file mode 100644 index 0000000000..c39da1b020 --- /dev/null +++ b/cpu/arm926ejs/mx28/serial.c @@ -0,0 +1,107 @@ +/* + * (c) 2007 Sascha Hauer + * + * (C) Copyright 2009-2010 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +/* + * Set baud rate. The settings are always 8n1: + * 8 data bits, no parity, 1 stop bit + */ +void serial_setbrg(void) +{ + u32 cr; + u32 quot; + + /* Disable everything */ + cr = REG_RD(REGS_UARTDBG_BASE, HW_UARTDBGCR); + REG_WR(REGS_UARTDBG_BASE, HW_UARTDBGCR, 0); + + /* Calculate and set baudrate */ + quot = (CONFIG_UARTDBG_CLK * 4) / gd->baudrate; + REG_WR(REGS_UARTDBG_BASE, HW_UARTDBGFBRD, quot & 0x3f); + REG_WR(REGS_UARTDBG_BASE, HW_UARTDBGIBRD, quot >> 6); + + /* Set 8n1 mode, enable FIFOs */ + REG_WR(REGS_UARTDBG_BASE, HW_UARTDBGLCR_H, + BM_UARTDBGLCR_H_WLEN | BM_UARTDBGLCR_H_FEN); + + /* Enable Debug UART */ + REG_WR(REGS_UARTDBG_BASE, HW_UARTDBGCR, cr); +} + +int serial_init(void) +{ + /* Disable UART */ + REG_WR(REGS_UARTDBG_BASE, HW_UARTDBGCR, 0); + + /* Mask interrupts */ + REG_WR(REGS_UARTDBG_BASE, HW_UARTDBGIMSC, 0); + + /* Set default baudrate */ + serial_setbrg(); + + /* Enable UART */ + REG_WR(REGS_UARTDBG_BASE, HW_UARTDBGCR, + BM_UARTDBGCR_TXE | BM_UARTDBGCR_RXE | BM_UARTDBGCR_UARTEN); + + return 0; +} + +/* Send a character */ +void serial_putc(const char c) +{ + /* Wait for room in TX FIFO */ + while (REG_RD(REGS_UARTDBG_BASE, HW_UARTDBGFR) & BM_UARTDBGFR_TXFF) + ; + + /* Write the data byte */ + REG_WR(REGS_UARTDBG_BASE, HW_UARTDBGDR, c); + + if (c == '\n') + serial_putc('\r'); +} + +void serial_puts(const char *s) +{ + while (*s) + serial_putc(*s++); +} + +/* Test whether a character is in TX buffer */ +int serial_tstc(void) +{ + /* Check if RX FIFO is not empty */ + return !(REG_RD(REGS_UARTDBG_BASE, HW_UARTDBGFR) & BM_UARTDBGFR_RXFE); +} + +/* Receive character */ +int serial_getc(void) +{ + /* Wait while TX FIFO is empty */ + while (REG_RD(REGS_UARTDBG_BASE, HW_UARTDBGFR) & BM_UARTDBGFR_RXFE) + ; + + /* Read data byte */ + return REG_RD(REGS_UARTDBG_BASE, HW_UARTDBGDR) & 0xff; +} + diff --git a/cpu/arm926ejs/mx28/timer.c b/cpu/arm926ejs/mx28/timer.c new file mode 100644 index 0000000000..fef5e7a108 --- /dev/null +++ b/cpu/arm926ejs/mx28/timer.c @@ -0,0 +1,234 @@ +/* + * (C) Copyright 2003 + * Texas Instruments + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Alex Zuepke + * + * (C) Copyright 2002-2004 + * Gary Jennejohn, DENX Software Engineering, + * + * (C) Copyright 2004 + * Philippe Robin, ARM Ltd. + * + * (C) Copyright 2009-2010 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +/* + * TIMROT gets 4 timer instances + * Define N as 0..3 to specify + */ +#define N 0 + +/* Ticks per second */ +#define CONFIG_SYS_HZ 1000 + +/* Maximum fixed count */ +#define TIMER_LOAD_VAL 0xffffffff + +static ulong timestamp; +static ulong lastdec; + +int timer_init(void) +{ + /* + * Reset Timers and Rotary Encoder module + */ + + /* Clear SFTRST */ + REG_CLR(REGS_TIMROT_BASE, HW_TIMROT_ROTCTRL, 1 << 31); + while (REG_RD(REGS_TIMROT_BASE, HW_TIMROT_ROTCTRL) & (1 << 31)) + ; + + /* Clear CLKGATE */ + REG_CLR(REGS_TIMROT_BASE, HW_TIMROT_ROTCTRL, 1 << 30); + + /* Set SFTRST and wait until CLKGATE is set */ + REG_SET(REGS_TIMROT_BASE, HW_TIMROT_ROTCTRL, 1 << 31); + while (!(REG_RD(REGS_TIMROT_BASE, HW_TIMROT_ROTCTRL) & (1 << 30))) + ; + + /* Clear SFTRST and CLKGATE */ + REG_CLR(REGS_TIMROT_BASE, HW_TIMROT_ROTCTRL, 1 << 31); + REG_CLR(REGS_TIMROT_BASE, HW_TIMROT_ROTCTRL, 1 << 30); + + /* + * Now initialize timer + */ + + /* Set fixed_count to 0 */ + REG_WR(REGS_TIMROT_BASE, HW_TIMROT_FIXED_COUNTn(N), 0); + + /* set UPDATE bit and 1Khz frequency */ + REG_WR(REGS_TIMROT_BASE, HW_TIMROT_TIMCTRLn(N), + BM_TIMROT_TIMCTRLn_RELOAD | BM_TIMROT_TIMCTRLn_UPDATE | + BV_TIMROT_TIMCTRLn_SELECT__1KHZ_XTAL); + + /* Set fixed_count to maximal value */ + REG_WR(REGS_TIMROT_BASE, HW_TIMROT_FIXED_COUNTn(N), TIMER_LOAD_VAL); + + /* init the timestamp and lastdec value */ + reset_timer_masked(); + + return 0; +} + +/* + * timer without interrupts + */ + +void reset_timer(void) +{ + reset_timer_masked(); +} + +ulong get_timer(ulong base) +{ + return get_timer_masked() - base; +} + +void set_timer(ulong t) +{ + timestamp = t; +} + +/* delay x useconds AND perserve advance timstamp value */ +void udelay(unsigned long usec) +{ + ulong tmo, tmp; + + if (usec >= 1000) { + /* if "big" number, spread normalization to seconds */ + tmo = usec / 1000; + /* start to normalize for usec to ticks per sec */ + tmo *= CONFIG_SYS_HZ; + /* find number of "ticks" to wait to achieve target */ + tmo /= 1000; + /* finish normalize. */ + } else { + /* else small number, don't kill it prior to HZ multiply */ + tmo = usec * CONFIG_SYS_HZ; + tmo /= (1000*1000); + } + + tmp = get_timer(0); + /* get current timestamp */ + if ((tmo + tmp + 1) < tmp) + /* if setting this fordward will roll time stamp */ + reset_timer_masked(); + /* reset "advancing" timestamp to 0, set lastdec value */ + else + tmo += tmp; + /* else, set advancing stamp wake up time */ + + while (get_timer_masked() < tmo)/* loop till event */ + /*NOP*/; +} + +void reset_timer_masked(void) +{ + /* capure current decrementer value time */ + lastdec = REG_RD(REGS_TIMROT_BASE, HW_TIMROT_RUNNING_COUNTn(N)); + /* start "advancing" time stamp from 0 */ + timestamp = 0; +} + +ulong get_timer_masked(void) +{ + /* current tick value */ + ulong now = REG_RD(REGS_TIMROT_BASE, HW_TIMROT_RUNNING_COUNTn(N)); + + if (lastdec >= now) { /* normal mode (non roll) */ + /* normal mode */ + timestamp += lastdec - now; + /* move stamp fordward with absoulte diff ticks */ + } else { + /* we have overflow of the count down timer */ + /* nts = ts + ld + (TLV - now) + * ts=old stamp, ld=time that passed before passing through -1 + * (TLV-now) amount of time after passing though -1 + * nts = new "advancing time stamp"...it could also roll + * and cause problems. + */ + timestamp += lastdec + TIMER_LOAD_VAL - now + 1; + } + lastdec = now; + + return timestamp; +} + +/* waits specified delay value and resets timestamp */ +void udelay_masked(unsigned long usec) +{ + ulong tmo; + ulong endtime; + signed long diff; + + if (usec >= 1000) { + /* if "big" number, spread normalization to seconds */ + tmo = usec / 1000; + /* start to normalize for usec to ticks per sec */ + tmo *= CONFIG_SYS_HZ; + /* find number of "ticks" to wait to achieve target */ + tmo /= 1000; + /* finish normalize. */ + } else { + /* else small number, don't kill it prior to HZ multiply */ + tmo = usec * CONFIG_SYS_HZ; + tmo /= (1000*1000); + } + + endtime = get_timer_masked() + tmo; + + do { + ulong now = get_timer_masked(); + diff = endtime - now; + } while (diff >= 0); +} + +/* + * This function is derived from PowerPC code (read timebase as long long). + * On ARM it just returns the timer value. + */ +unsigned long long get_ticks(void) +{ + return get_timer(0); +} + +/* + * This function is derived from PowerPC code (timebase clock frequency). + * On ARM it returns the number of timer ticks per second. + */ +ulong get_tbclk(void) +{ + ulong tbclk; + + tbclk = CONFIG_SYS_HZ; + return tbclk; +} diff --git a/cpu/arm926ejs/start.S b/cpu/arm926ejs/start.S index 8043322583..31bdcf0fbf 100644 --- a/cpu/arm926ejs/start.S +++ b/cpu/arm926ejs/start.S @@ -126,7 +126,7 @@ FIQ_STACK_START: /* * the actual reset code */ - +.globl reset reset: /* * set the cpu to SVC32 mode diff --git a/cpu/arm_cortexa8/Makefile b/cpu/arm_cortexa8/Makefile index ae20299db7..b8efc4e6cb 100644 --- a/cpu/arm_cortexa8/Makefile +++ b/cpu/arm_cortexa8/Makefile @@ -44,4 +44,4 @@ include $(SRCTREE)/rules.mk sinclude $(obj).depend -######################################################################### \ No newline at end of file +######################################################################### diff --git a/cpu/arm_cortexa8/config.mk b/cpu/arm_cortexa8/config.mk index da5ee162c5..079bd5fd74 100644 --- a/cpu/arm_cortexa8/config.mk +++ b/cpu/arm_cortexa8/config.mk @@ -30,5 +30,14 @@ PLATFORM_CPPFLAGS += -march=armv5 # Supply options according to compiler version # # ========================================================================= -PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,\ +#ifdef CONFIG_SYS_APCS_GNU +#PLATFORM_CPPFLAGS +=$(call cc-option,-mapcs-32,-mabi=apcs-gnu) +#else +#PLATFORM_CPPFLAGS +=$(call cc-option) +#endif +#PLATFORM_CPPFLAGS +=$(call cc-option,-mno-thumb-interwork,\ +# $(call cc-option,-mshort-load-bytes,\ +# $(call cc-option,-malignment-traps,))) + +PLATFORM_CPPFLAGS +=$(call cc-option,-mshort-load-bytes,\ $(call cc-option,-malignment-traps,)) diff --git a/cpu/arm_cortexa8/cpu.c b/cpu/arm_cortexa8/cpu.c index 5a5981e405..e4bd7cfb09 100644 --- a/cpu/arm_cortexa8/cpu.c +++ b/cpu/arm_cortexa8/cpu.c @@ -35,11 +35,97 @@ #include #include #include +#include +#include + #ifndef CONFIG_L2_OFF +#ifndef CONFIG_MXC #include #endif +#endif -static void cache_flush(void); +#define cache_flush(void) \ +{ \ + asm volatile ( \ + "stmfd sp!, {r0-r5, r7, r9-r11};" \ + "mrc p15, 1, r0, c0, c0, 1;" /*@ read clidr*/ \ + /* @ extract loc from clidr */ \ + "ands r3, r0, #0x7000000;" \ + /* @ left align loc bit field*/ \ + "mov r3, r3, lsr #23;" \ + /* @ if loc is 0, then no need to clean*/ \ + "beq 555f;" /* finished;" */ \ + /* @ start clean at cache level 0*/ \ + "mov r10, #0;" \ + "111:" /*"loop1: */ \ + /* @ work out 3x current cache level */ \ + "add r2, r10, r10, lsr #1;" \ + /* @ extract cache type bits from clidr */ \ + "mov r1, r0, lsr r2;" \ + /* @ mask of the bits for current cache only */ \ + "and r1, r1, #7;" \ + /* @ see what cache we have at this level*/ \ + "cmp r1, #2;" \ + /* @ skip if no cache, or just i-cache*/ \ + "blt 444f;" /* skip;" */ \ + /* @ select current cache level in cssr*/ \ + "mcr p15, 2, r10, c0, c0, 0;" \ + /* @ isb to sych the new cssr&csidr */ \ + "mcr p15, 0, r10, c7, c5, 4;" \ + /* @ read the new csidr */ \ + "mrc p15, 1, r1, c0, c0, 0;" \ + /* @ extract the length of the cache lines */ \ + "and r2, r1, #7;" \ + /* @ add 4 (line length offset) */ \ + "add r2, r2, #4;" \ + "ldr r4, =0x3ff;" \ + /* @ find maximum number on the way size*/ \ + "ands r4, r4, r1, lsr #3;" \ + /*"clz r5, r4;" @ find bit position of way size increment*/ \ + ".word 0xE16F5F14;" \ + "ldr r7, =0x7fff;" \ + /* @ extract max number of the index size*/ \ + "ands r7, r7, r1, lsr #13;" \ + "222:" /* loop2:" */ \ + /* @ create working copy of max way size*/ \ + "mov r9, r4;" \ + "333:" /* loop3:" */ \ + /* @ factor way and cache number into r11*/ \ + "orr r11, r10, r9, lsl r5;" \ + /* @ factor index number into r11*/ \ + "orr r11, r11, r7, lsl r2;" \ + /* @ clean & invalidate by set/way */ \ + "mcr p15, 0, r11, c7, c14, 2;" \ + /* @ decrement the way */ \ + "subs r9, r9, #1;" \ + "bge 333b;" /* loop3;" */ \ + /* @ decrement the index */ \ + "subs r7, r7, #1;" \ + "bge 222b;" /* loop2;" */ \ + "444:" /* skip: */ \ + /*@ increment cache number */ \ + "add r10, r10, #2;" \ + "cmp r3, r10;" \ + "bgt 111b;" /* loop1; */ \ + "555:" /* "finished:" */ \ + /* @ swith back to cache level 0 */ \ + "mov r10, #0;" \ + /* @ select current cache level in cssr */ \ + "mcr p15, 2, r10, c0, c0, 0;" \ + /* @ isb to sych the new cssr&csidr */ \ + "mcr p15, 0, r10, c7, c5, 4;" \ + "ldmfd sp!, {r0-r5, r7, r9-r11};" \ + "666:" /* iflush:" */ \ + "mov r0, #0x0;" \ + /* @ invalidate I+BTB */ \ + "mcr p15, 0, r0, c7, c5, 0;" \ + /* @ drain WB */ \ + "mcr p15, 0, r0, c7, c10, 4;" \ + : \ + : \ + : "r0" /* Clobber list */ \ + ); \ +} int cleanup_before_linux(void) { @@ -53,13 +139,14 @@ int cleanup_before_linux(void) */ disable_interrupts(); + /* flush cache */ + cache_flush(); + /* turn off I/D-cache */ icache_disable(); + /* invalidate D-cache */ dcache_disable(); - /* invalidate I-cache */ - cache_flush(); - #ifndef CONFIG_L2_OFF /* turn off L2 cache */ l2_cache_disable(); @@ -70,6 +157,9 @@ int cleanup_before_linux(void) /* mem barrier to sync up things */ asm("mcr p15, 0, %0, c7, c10, 4": :"r"(i)); + /* turn off MMU */ + MMU_OFF(); + #ifndef CONFIG_L2_OFF l2_cache_enable(); #endif @@ -77,7 +167,3 @@ int cleanup_before_linux(void) return 0; } -static void cache_flush(void) -{ - asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (0)); -} diff --git a/cpu/arm_cortexa8/mx50/Makefile b/cpu/arm_cortexa8/mx50/Makefile new file mode 100644 index 0000000000..460bdd9aea --- /dev/null +++ b/cpu/arm_cortexa8/mx50/Makefile @@ -0,0 +1,48 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# (C) Copyright 2010 Freescale Semiconductor, Inc. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(SOC).a + +COBJS = interrupts.o serial.o generic.o iomux.o timer.o cache.o +COBJS += $(COBJS-y) + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) + +all: $(obj).depend $(LIB) + +$(LIB): $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/cpu/arm_cortexa8/mx50/cache.c b/cpu/arm_cortexa8/mx50/cache.c new file mode 100644 index 0000000000..60df92f862 --- /dev/null +++ b/cpu/arm_cortexa8/mx50/cache.c @@ -0,0 +1,44 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +void l2_cache_enable(void) +{ + asm("mrc 15, 0, r0, c1, c0, 1"); + asm("orr r0, r0, #0x2"); + asm("mcr 15, 0, r0, c1, c0, 1"); +} + +void l2_cache_disable(void) +{ + asm("mrc 15, 0, r0, c1, c0, 1"); + asm("bic r0, r0, #0x2"); + asm("mcr 15, 0, r0, c1, c0, 1"); +} + +/*dummy function for L2 ON*/ +u32 get_device_type(void) +{ + return 0; +} diff --git a/cpu/arm_cortexa8/mx50/crm_regs.h b/cpu/arm_cortexa8/mx50/crm_regs.h new file mode 100644 index 0000000000..eb94bbe457 --- /dev/null +++ b/cpu/arm_cortexa8/mx50/crm_regs.h @@ -0,0 +1,646 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef __ARCH_ARM_MACH_MX50_CRM_REGS_H__ +#define __ARCH_ARM_MACH_MX50_CRM_REGS_H__ + +#define MXC_CCM_BASE CCM_BASE_ADDR +#define MXC_DPLL1_BASE PLL1_BASE_ADDR +#define MXC_DPLL2_BASE PLL2_BASE_ADDR +#define MXC_DPLL3_BASE PLL3_BASE_ADDR + +/* PLL Register Offsets */ +#define MXC_PLL_DP_CTL 0x00 +#define MXC_PLL_DP_CONFIG 0x04 +#define MXC_PLL_DP_OP 0x08 +#define MXC_PLL_DP_MFD 0x0C +#define MXC_PLL_DP_MFN 0x10 +#define MXC_PLL_DP_MFNMINUS 0x14 +#define MXC_PLL_DP_MFNPLUS 0x18 +#define MXC_PLL_DP_HFS_OP 0x1C +#define MXC_PLL_DP_HFS_MFD 0x20 +#define MXC_PLL_DP_HFS_MFN 0x24 +#define MXC_PLL_DP_MFN_TOGC 0x28 +#define MXC_PLL_DP_DESTAT 0x2c + +/* PLL Register Bit definitions */ +#define MXC_PLL_DP_CTL_MUL_CTRL 0x2000 +#define MXC_PLL_DP_CTL_DPDCK0_2_EN 0x1000 +#define MXC_PLL_DP_CTL_DPDCK0_2_OFFSET 12 +#define MXC_PLL_DP_CTL_ADE 0x800 +#define MXC_PLL_DP_CTL_REF_CLK_DIV 0x400 +#define MXC_PLL_DP_CTL_REF_CLK_SEL_MASK (3 << 8) +#define MXC_PLL_DP_CTL_REF_CLK_SEL_OFFSET 8 +#define MXC_PLL_DP_CTL_HFSM 0x80 +#define MXC_PLL_DP_CTL_PRE 0x40 +#define MXC_PLL_DP_CTL_UPEN 0x20 +#define MXC_PLL_DP_CTL_RST 0x10 +#define MXC_PLL_DP_CTL_RCP 0x8 +#define MXC_PLL_DP_CTL_PLM 0x4 +#define MXC_PLL_DP_CTL_BRM0 0x2 +#define MXC_PLL_DP_CTL_LRF 0x1 + +#define MXC_PLL_DP_CONFIG_BIST 0x8 +#define MXC_PLL_DP_CONFIG_SJC_CE 0x4 +#define MXC_PLL_DP_CONFIG_AREN 0x2 +#define MXC_PLL_DP_CONFIG_LDREQ 0x1 + +#define MXC_PLL_DP_OP_MFI_OFFSET 4 +#define MXC_PLL_DP_OP_MFI_MASK (0xF << 4) +#define MXC_PLL_DP_OP_PDF_OFFSET 0 +#define MXC_PLL_DP_OP_PDF_MASK 0xF + +#define MXC_PLL_DP_MFD_OFFSET 0 +#define MXC_PLL_DP_MFD_MASK 0x07FFFFFF + +#define MXC_PLL_DP_MFN_OFFSET 0x0 +#define MXC_PLL_DP_MFN_MASK 0x07FFFFFF + +#define MXC_PLL_DP_MFN_TOGC_TOG_DIS (1 << 17) +#define MXC_PLL_DP_MFN_TOGC_TOG_EN (1 << 16) +#define MXC_PLL_DP_MFN_TOGC_CNT_OFFSET 0x0 +#define MXC_PLL_DP_MFN_TOGC_CNT_MASK 0xFFFF + +#define MXC_PLL_DP_DESTAT_TOG_SEL (1 << 31) +#define MXC_PLL_DP_DESTAT_MFN 0x07FFFFFF + +/* Register addresses of CCM*/ +#define MXC_CCM_CCR (MXC_CCM_BASE + 0x00) +#define MXC_CCM_CCDR (MXC_CCM_BASE + 0x04) /* Reserved */ +#define MXC_CCM_CSR (MXC_CCM_BASE + 0x08) +#define MXC_CCM_CCSR (MXC_CCM_BASE + 0x0C) +#define MXC_CCM_CACRR (MXC_CCM_BASE + 0x10) +#define MXC_CCM_CBCDR (MXC_CCM_BASE + 0x14) +#define MXC_CCM_CBCMR (MXC_CCM_BASE + 0x18) +#define MXC_CCM_CSCMR1 (MXC_CCM_BASE + 0x1C) +#define MXC_CCM_CSCMR2 (MXC_CCM_BASE + 0x20) /* Reserved */ +#define MXC_CCM_CSCDR1 (MXC_CCM_BASE + 0x24) +#define MXC_CCM_CS1CDR (MXC_CCM_BASE + 0x28) +#define MXC_CCM_CS2CDR (MXC_CCM_BASE + 0x2C) +#define MXC_CCM_CDCDR (MXC_CCM_BASE + 0x30) /* Reserved */ +#define MXC_CCM_CHSCDR (MXC_CCM_BASE + 0x34) /* Reserved */ +#define MXC_CCM_CSCDR2 (MXC_CCM_BASE + 0x38) +#define MXC_CCM_CSCDR3 (MXC_CCM_BASE + 0x3C) /* Reserved */ +#define MXC_CCM_CSCDR4 (MXC_CCM_BASE + 0x40) /* Reserved */ +#define MXC_CCM_CWDR (MXC_CCM_BASE + 0x44) /* Reserved */ +#define MXC_CCM_CDHIPR (MXC_CCM_BASE + 0x48) +#define MXC_CCM_CDCR (MXC_CCM_BASE + 0x4C) +#define MXC_CCM_CTOR (MXC_CCM_BASE + 0x50) +#define MXC_CCM_CLPCR (MXC_CCM_BASE + 0x54) +#define MXC_CCM_CISR (MXC_CCM_BASE + 0x58) +#define MXC_CCM_CIMR (MXC_CCM_BASE + 0x5C) +#define MXC_CCM_CCOSR (MXC_CCM_BASE + 0x60) +#define MXC_CCM_CGPR (MXC_CCM_BASE + 0x64) /* Reserved */ +#define MXC_CCM_CCGR0 (MXC_CCM_BASE + 0x68) +#define MXC_CCM_CCGR1 (MXC_CCM_BASE + 0x6C) +#define MXC_CCM_CCGR2 (MXC_CCM_BASE + 0x70) +#define MXC_CCM_CCGR3 (MXC_CCM_BASE + 0x74) +#define MXC_CCM_CCGR4 (MXC_CCM_BASE + 0x78) +#define MXC_CCM_CCGR5 (MXC_CCM_BASE + 0x7C) +#define MXC_CCM_CCGR6 (MXC_CCM_BASE + 0x80) +#define MXC_CCM_CCGR7 (MXC_CCM_BASE + 0x84) +#define MXC_CCM_CMEOR (MXC_CCM_BASE + 0x88) +#define MXC_CCM_CSR2 (MXC_CCM_BASE + 0x8C) +#define MXC_CCM_CLKSEQ_BYPASS (MXC_CCM_BASE + 0x90) +#define MXC_CCM_CLK_SYS (MXC_CCM_BASE + 0x94) +#define MXC_CCM_CLK_DDR (MXC_CCM_BASE + 0x98) + +/* Define the bits in register CCR */ +#define MXC_CCM_CCR_COSC_EN (1 << 12) +#define MXC_CCM_CCR_CAMP1_EN (1 << 9) +#define MXC_CCM_CCR_OSCNT_OFFSET (0) +#define MXC_CCM_CCR_OSCNT_MASK (0xFF) + +/* Define the bits in register CSR */ +#define MXC_CCM_CSR_COSR_READY (1 << 5) +#define MXC_CCM_CSR_LVS_VALUE (1 << 4) +#define MXC_CCM_CSR_CAMP1_READY (1 << 2) +#define MXC_CCM_CSR_TEMP_MON_ALARM (1 << 1) +#define MXC_CCM_CSR_REF_EN_B (1 << 0) + +/* Define the bits in register CCSR */ +#define MXC_CCM_CCSR_PLL3_PFD_EN (0x1 << 13) +#define MXC_CCM_CCSR_PLL2_PFD_EN (0x1 << 12) +#define MXC_CCM_CCSR_PLL1_PFD_EN (0x1 << 11) +#define MXC_CCM_CCSR_LP_APM_SEL (0x1 << 10) +#define MXC_CCM_CCSR_LP_APM_SEL_OFFSET (1) +#define MXC_CCM_CCSR_STEP_SEL_OFFSET (7) +#define MXC_CCM_CCSR_STEP_SEL_MASK (0x3 << 7) +#define MXC_CCM_CCSR_PLL2_PODF_OFFSET (5) +#define MXC_CCM_CCSR_PLL2_PODF_MASK (0x3 << 5) +#define MXC_CCM_CCSR_PLL3_PODF_OFFSET (3) +#define MXC_CCM_CCSR_PLL3_PODF_MASK (0x3 << 3) +#define MXC_CCM_CCSR_PLL1_SW_CLK_SEL (1 << 2) +#define MXC_CCM_CCSR_PLL2_SW_CLK_SEL (1 << 1) +#define MXC_CCM_CCSR_PLL3_SW_CLK_SEL (1 << 0) + +/* Define the bits in register CACRR */ +#define MXC_CCM_CACRR_ARM_PODF_OFFSET (0) +#define MXC_CCM_CACRR_ARM_PODF_MASK (0x7) + +/* Define the bits in register CBCDR */ +#define MXC_CCM_CBCDR_WEIM_CLK_SEL (0x1 << 27) +#define MXC_CCM_CBCDR_PERIPH_CLK_SEL_OFFSET (25) +#define MXC_CCM_CBCDR_PERIPH_CLK_SEL_MASK (0x3 << 25) +#define MXC_CCM_CBCDR_WEIM_PODF_OFFSET (22) +#define MXC_CCM_CBCDR_WEIM_PODF_MASK (7 << 22) +#define MXC_CCM_CBCDR_AXI_B_PODF_OFFSET (19) +#define MXC_CCM_CBCDR_AXI_B_PODF_MASK (0x7 << 19) +#define MXC_CCM_CBCDR_AXI_A_PODF_OFFSET (16) +#define MXC_CCM_CBCDR_AXI_A_PODF_MASK (0x7 << 16) +#define MXC_CCM_CBCDR_AHB_PODF_OFFSET (10) +#define MXC_CCM_CBCDR_AHB_PODF_MASK (0x7 << 10) +#define MXC_CCM_CBCDR_IPG_PODF_OFFSET (8) +#define MXC_CCM_CBCDR_IPG_PODF_MASK (0x3 << 8) +#define MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET (6) +#define MXC_CCM_CBCDR_PERCLK_PRED1_MASK (0x3 << 6) +#define MXC_CCM_CBCDR_PERCLK_PRED2_OFFSET (3) +#define MXC_CCM_CBCDR_PERCLK_PRED2_MASK (0x7 << 3) +#define MXC_CCM_CBCDR_PERCLK_PODF_OFFSET (0) +#define MXC_CCM_CBCDR_PERCLK_PODF_MASK (0x7) + +/* Define the bits in register CBCMR */ +#define MXC_CCM_CBCMR_GPU2D_CLK_SEL_OFFSET (16) +#define MXC_CCM_CBCMR_GPU2D_CLK_SEL_MASK (0x3 << 16) +#define MXC_CCM_CBCMR_DBG_APB_CLK_SEL_OFFSET (2) +#define MXC_CCM_CBCMR_DBG_APB_CLK_SEL_MASK (0x3 << 2) +#define MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL (0x1 << 1) +#define MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL (0x1 << 0) +#define MXC_CCM_CBCMR_LP_APM_SEL_OFFSET (0x1) + +/* Define the bits in register CSCMR1 */ +#define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_OFFSET (30) +#define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_MASK (0x3 << 30) +#define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_OFFSET (28) +#define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_MASK (0x3 << 28) +#define MXC_CCM_CSCMR1_UART_CLK_SEL_OFFSET (24) +#define MXC_CCM_CSCMR1_UART_CLK_SEL_MASK (0x3 << 24) +#define MXC_CCM_CSCMR1_ESDHC1_CLK_SEL_OFFSET (21) +#define MXC_CCM_CSCMR1_ESDHC1_CLK_SEL_MASK (0x3 << 21) +#define MXC_CCM_CSCMR1_ESDHC2_CLK_SEL (0x1 << 20) +#define MXC_CCM_CSCMR1_ESDHC4_CLK_SEL (0x1 << 19) +#define MXC_CCM_CSCMR1_ESDHC3_CLK_SEL_OFFSET (16) +#define MXC_CCM_CSCMR1_ESDHC3_CLK_SEL_MASK (0x7 << 16) +#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET (14) +#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK (0x3 << 14) +#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET (12) +#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_MASK (0x3 << 12) +#define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_OFFSET (8) +#define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_MASK (0x3 << 8) +#define MXC_CCM_CSCMR1_CSPI_CLK_SEL_OFFSET (4) +#define MXC_CCM_CSCMR1_CSPI_CLK_SEL_MASK (0x3 << 4) +#define MXC_CCM_CSCMR1_SSI_EXT2_COM_CLK_SEL (0x1 << 1) +#define MXC_CCM_CSCMR1_SSI_EXT1_COM_CLK_SEL (0x1) + +/* Define the bits in register CSCDR1 */ +#define MXC_CCM_CSCDR1_ESDHC3_CLK_PRED_OFFSET (22) +#define MXC_CCM_CSCDR1_ESDHC3_CLK_PRED_MASK (0x7 << 22) +#define MXC_CCM_CSCDR1_ESDHC3_CLK_PODF_OFFSET (19) +#define MXC_CCM_CSCDR1_ESDHC3_CLK_PODF_MASK (0x7 << 19) +#define MXC_CCM_CSCDR1_ESDHC1_CLK_PRED_OFFSET (16) +#define MXC_CCM_CSCDR1_ESDHC1_CLK_PRED_MASK (0x7 << 16) +#define MXC_CCM_CSCDR1_PGC_CLK_PODF_OFFSET (14) +#define MXC_CCM_CSCDR1_PGC_CLK_PODF_MASK (0x3 << 14) +#define MXC_CCM_CSCDR1_ESDHC1_CLK_PODF_OFFSET (11) +#define MXC_CCM_CSCDR1_ESDHC1_CLK_PODF_MASK (0x7 << 11) +#define MXC_CCM_CSCDR1_UART_CLK_PRED_OFFSET (3) +#define MXC_CCM_CSCDR1_UART_CLK_PRED_MASK (0x7 << 3) +#define MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET (0) +#define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK (0x7) + +/* Define the bits in register CS1CDR and CS2CDR */ +#define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PRED_OFFSET (22) +#define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PRED_MASK (0x7 << 22) +#define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PODF_OFFSET (16) +#define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PODF_MASK (0x3F << 16) +#define MXC_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET (6) +#define MXC_CCM_CS1CDR_SSI1_CLK_PRED_MASK (0x7 << 6) +#define MXC_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET (0) +#define MXC_CCM_CS1CDR_SSI1_CLK_PODF_MASK (0x3F) + +#define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PRED_OFFSET (22) +#define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PRED_MASK (0x7 << 22) +#define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PODF_OFFSET (16) +#define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PODF_MASK (0x3F << 16) +#define MXC_CCM_CS2CDR_SSI2_CLK_PRED_OFFSET (6) +#define MXC_CCM_CS2CDR_SSI2_CLK_PRED_MASK (0x7 << 6) +#define MXC_CCM_CS2CDR_SSI2_CLK_PODF_OFFSET (0) +#define MXC_CCM_CS2CDR_SSI2_CLK_PODF_MASK (0x3F) + +/* Define the bits in register CSCDR2 */ +#define MXC_CCM_CSCDR2_CSPI_CLK_PRED_OFFSET (25) +#define MXC_CCM_CSCDR2_CSPI_CLK_PRED_MASK (0x7 << 25) +#define MXC_CCM_CSCDR2_CSPI_CLK_PODF_OFFSET (19) +#define MXC_CCM_CSCDR2_CSPI_CLK_PODF_MASK (0x3F << 19) + +/* Define the bits in register CDHIPR */ +#define MXC_CCM_CDHIPR_ARM_PODF_BUSY (1 << 16) +#define MXC_CCM_CDHIPR_WEIM_CLK_SEL_BUSY (1 << 6) +#define MXC_CCM_CDHIPR_PERIPH_CLK_SEL_BUSY (1 << 5) +#define MXC_CCM_CDHIPR_AHB_PODF_BUSY (1 << 3) +#define MXC_CCM_CDHIPR_WEIM_PODF_BUSY (1 << 2) +#define MXC_CCM_CDHIPR_AXI_B_PODF_BUSY (1 << 1) +#define MXC_CCM_CDHIPR_AXI_A_PODF_BUSY (1 << 0) + +/* Define the bits in register CDCR */ + +#define MXC_CCM_CDCR_SW_PERIPH_CLK_DIV_REQ_STATUS (0x1 << 7) +#define MXC_CCM_CDCR_SW_PERIPH_CLK_DIV_REQ (0x1 << 6) +#define MXC_CCM_CDCR_SW_DVFS_EN (0x1 << 5) +#define MXC_CCM_CDCR_ARM_FREQ_SHIFT_DIVIDER (0x1 << 2) +#define MXC_CCM_CDCR_PERIPH_CLK_DVFS_PODF_OFFSET (0) +#define MXC_CCM_CDCR_PERIPH_CLK_DVFS_PODF_MASK (0x3) + +/* Define the bits in register CLPCR */ +#define MXC_CCM_CLPCR_BYPASS_MAX_LPM_HS (0x1 << 25) +#define MXC_CCM_CLPCR_BYPASS_SDMA_LPM_HS (0x1 << 24) +#define MXC_CCM_CLPCR_BYPASS_RNGB_LPM_HS (0x1 << 23) +#define MXC_CCM_CLPCR_BYPASS_WEIM_LPM_HS (0x1 << 19) +#define MXC_CCM_CLPCR_COSC_PWRDOWN (0x1 << 11) +#define MXC_CCM_CLPCR_STBY_COUNT_OFFSET (9) +#define MXC_CCM_CLPCR_STBY_COUNT_MASK (0x3 << 9) +#define MXC_CCM_CLPCR_VSTBY (0x1 << 8) +#define MXC_CCM_CLPCR_DIS_REF_OSC (0x1 << 7) +#define MXC_CCM_CLPCR_SBYOS (0x1 << 6) +#define MXC_CCM_CLPCR_ARM_CLK_DIS_ON_LPM (0x1 << 5) +#define MXC_CCM_CLPCR_BYPASS_PMIC_VFUNC_READY (0x1 << 2) +#define MXC_CCM_CLPCR_LPM_OFFSET (0) +#define MXC_CCM_CLPCR_LPM_MASK (0x3) + +/* Define the bits in register CISR */ +#define MXC_CCM_CISR_ARM_PODF_LOADED (0x1 << 26) +#define MXC_CCM_CISR_TEMP_MON_ALARM (0x1 << 25) +#define MXC_CCM_CISR_WEIM_CLK_SEL_LOADED (0x1 << 23) +#define MXC_CCM_CISR_PER_CLK_SEL_LOADED (0x1 << 22) +#define MXC_CCM_CISR_AHB_PODF_LOADED (0x1 << 20) +#define MXC_CCM_CISR_WEIM_PODF_LOADED (0x1 << 19) +#define MXC_CCM_CISR_AXI_B_PODF_LOADED (0x1 << 18) +#define MXC_CCM_CISR_AXI_A_PODF_LOADED (0x1 << 17) +#define MXC_CCM_CISR_DIVIDER_LOADED (0x1 << 16) +#define MXC_CCM_CISR_COSC_READY (0x1 << 6) +#define MXC_CCM_CISR_CAMP1_READY (0x1 << 4) +#define MXC_CCM_CISR_LRF_PLL3 (0x1 << 2) +#define MXC_CCM_CISR_LRF_PLL2 (0x1 << 1) +#define MXC_CCM_CISR_LRF_PLL1 (0x1) + +/* Define the bits in register CIMR */ +#define MXC_CCM_CIMR_MASK_ARM_PODF_LOADED (0x1 << 26) +#define MXC_CCM_CIMR_MASK_TEMP_MON_ALARM (0x1 << 25) +#define MXC_CCM_CIMR_MASK_WEIM_CLK_SEL_LOADED (0x1 << 23) +#define MXC_CCM_CIMR_MASK_PER_CLK_SEL_LOADED (0x1 << 22) +#define MXC_CCM_CIMR_MASK_AHB_PODF_LOADED (0x1 << 20) +#define MXC_CCM_CIMR_MASK_WEIM_PODF_LOADED (0x1 << 19) +#define MXC_CCM_CIMR_MASK_AXI_B_PODF_LOADED (0x1 << 18) +#define MXC_CCM_CIMR_MASK_AXI_A_PODF_LOADED (0x1 << 17) +#define MXC_CCM_CIMR_MASK_DIVIDER_LOADED (0x1 << 16) +#define MXC_CCM_CIMR_MASK_COSC_READY (0x1 << 6) +#define MXC_CCM_CIMR_MASK_CAMP1_READY (0x1 << 4) +#define MXC_CCM_CIMR_MASK_LRF_PLL3 (0x1 << 2) +#define MXC_CCM_CIMR_MASK_LRF_PLL2 (0x1 << 1) +#define MXC_CCM_CIMR_MASK_LRF_PLL1 (0x1) + +/* Define the bits in register CCOSR */ +#define MXC_CCM_CCOSR_CKO2_EN_OFFSET (0x1 << 24) +#define MXC_CCM_CCOSR_CKO2_DIV_OFFSET (21) +#define MXC_CCM_CCOSR_CKO2_DIV_MASK (0x7 << 21) +#define MXC_CCM_CCOSR_CKO2_SEL_OFFSET (16) +#define MXC_CCM_CCOSR_CKO2_SEL_MASK (0x1F << 16) +#define MXC_CCM_CCOSR_CKO1_SLOW_SEL (0x1 << 8) +#define MXC_CCM_CCOSR_CKO1_EN (0x1 << 7) +#define MXC_CCM_CCOSR_CKO1_DIV_OFFSET (4) +#define MXC_CCM_CCOSR_CKO1_DIV_MASK (0x7 << 4) +#define MXC_CCM_CCOSR_CKO1_SEL_OFFSET (0) +#define MXC_CCM_CCOSR_CKO1_SEL_MASK (0xF) + +/* Define the bits in registers CCGRx */ +#define MXC_CCM_CCGR_CG_MASK 0x3 + +#define MXC_CCM_CCGR0_CG15_OFFSET 30 +#define MXC_CCM_CCGR0_CG15_MASK (0x3 << 30) +#define MXC_CCM_CCGR0_CG14_OFFSET 28 +#define MXC_CCM_CCGR0_CG14_MASK (0x3 << 28) +#define MXC_CCM_CCGR0_CG13_OFFSET 26 +#define MXC_CCM_CCGR0_CG13_MASK (0x3 << 26) +#define MXC_CCM_CCGR0_CG12_OFFSET 24 +#define MXC_CCM_CCGR0_CG12_MASK (0x3 << 24) +#define MXC_CCM_CCGR0_CG11_OFFSET 22 +#define MXC_CCM_CCGR0_CG11_MASK (0x3 << 22) +#define MXC_CCM_CCGR0_CG10_OFFSET 20 +#define MXC_CCM_CCGR0_CG10_MASK (0x3 << 20) +#define MXC_CCM_CCGR0_CG9_OFFSET 18 +#define MXC_CCM_CCGR0_CG9_MASK (0x3 << 18) +#define MXC_CCM_CCGR0_CG8_OFFSET 16 +#define MXC_CCM_CCGR0_CG8_MASK (0x3 << 16) +#define MXC_CCM_CCGR0_CG7_OFFSET 14 +#define MXC_CCM_CCGR0_CG6_OFFSET 12 +#define MXC_CCM_CCGR0_CG5_OFFSET 10 +#define MXC_CCM_CCGR0_CG5_MASK (0x3 << 10) +#define MXC_CCM_CCGR0_CG4_OFFSET 8 +#define MXC_CCM_CCGR0_CG4_MASK (0x3 << 8) +#define MXC_CCM_CCGR0_CG3_OFFSET 6 +#define MXC_CCM_CCGR0_CG3_MASK (0x3 << 6) +#define MXC_CCM_CCGR0_CG2_OFFSET 4 +#define MXC_CCM_CCGR0_CG2_MASK (0x3 << 4) +#define MXC_CCM_CCGR0_CG1_OFFSET 2 +#define MXC_CCM_CCGR0_CG1_MASK (0x3 << 2) +#define MXC_CCM_CCGR0_CG0_OFFSET 0 +#define MXC_CCM_CCGR0_CG0_MASK 0x3 + +#define MXC_CCM_CCGR1_CG15_OFFSET 30 +#define MXC_CCM_CCGR1_CG14_OFFSET 28 +#define MXC_CCM_CCGR1_CG13_OFFSET 26 +#define MXC_CCM_CCGR1_CG12_OFFSET 24 +#define MXC_CCM_CCGR1_CG11_OFFSET 22 +#define MXC_CCM_CCGR1_CG10_OFFSET 20 +#define MXC_CCM_CCGR1_CG9_OFFSET 18 +#define MXC_CCM_CCGR1_CG8_OFFSET 16 +#define MXC_CCM_CCGR1_CG7_OFFSET 14 +#define MXC_CCM_CCGR1_CG6_OFFSET 12 +#define MXC_CCM_CCGR1_CG5_OFFSET 10 +#define MXC_CCM_CCGR1_CG4_OFFSET 8 +#define MXC_CCM_CCGR1_CG3_OFFSET 6 +#define MXC_CCM_CCGR1_CG2_OFFSET 4 +#define MXC_CCM_CCGR1_CG1_OFFSET 2 +#define MXC_CCM_CCGR1_CG0_OFFSET 0 + +#define MXC_CCM_CCGR2_CG15_OFFSET 30 +#define MXC_CCM_CCGR2_CG14_OFFSET 28 +#define MXC_CCM_CCGR2_CG13_OFFSET 26 +#define MXC_CCM_CCGR2_CG12_OFFSET 24 +#define MXC_CCM_CCGR2_CG11_OFFSET 22 +#define MXC_CCM_CCGR2_CG10_OFFSET 20 +#define MXC_CCM_CCGR2_CG9_OFFSET 18 +#define MXC_CCM_CCGR2_CG8_OFFSET 16 +#define MXC_CCM_CCGR2_CG7_OFFSET 14 +#define MXC_CCM_CCGR2_CG6_OFFSET 12 +#define MXC_CCM_CCGR2_CG5_OFFSET 10 +#define MXC_CCM_CCGR2_CG4_OFFSET 8 +#define MXC_CCM_CCGR2_CG3_OFFSET 6 +#define MXC_CCM_CCGR2_CG2_OFFSET 4 +#define MXC_CCM_CCGR2_CG1_OFFSET 2 +#define MXC_CCM_CCGR2_CG0_OFFSET 0 + +#define MXC_CCM_CCGR3_CG15_OFFSET 30 +#define MXC_CCM_CCGR3_CG14_OFFSET 28 +#define MXC_CCM_CCGR3_CG13_OFFSET 26 +#define MXC_CCM_CCGR3_CG12_OFFSET 24 +#define MXC_CCM_CCGR3_CG11_OFFSET 22 +#define MXC_CCM_CCGR3_CG10_OFFSET 20 +#define MXC_CCM_CCGR3_CG9_OFFSET 18 +#define MXC_CCM_CCGR3_CG8_OFFSET 16 +#define MXC_CCM_CCGR3_CG7_OFFSET 14 +#define MXC_CCM_CCGR3_CG6_OFFSET 12 +#define MXC_CCM_CCGR3_CG5_OFFSET 10 +#define MXC_CCM_CCGR3_CG4_OFFSET 8 +#define MXC_CCM_CCGR3_CG3_OFFSET 6 +#define MXC_CCM_CCGR3_CG2_OFFSET 4 +#define MXC_CCM_CCGR3_CG1_OFFSET 2 +#define MXC_CCM_CCGR3_CG0_OFFSET 0 + +#define MXC_CCM_CCGR4_CG15_OFFSET 30 +#define MXC_CCM_CCGR4_CG14_OFFSET 28 +#define MXC_CCM_CCGR4_CG13_OFFSET 26 +#define MXC_CCM_CCGR4_CG12_OFFSET 24 +#define MXC_CCM_CCGR4_CG11_OFFSET 22 +#define MXC_CCM_CCGR4_CG10_OFFSET 20 +#define MXC_CCM_CCGR4_CG9_OFFSET 18 +#define MXC_CCM_CCGR4_CG8_OFFSET 16 +#define MXC_CCM_CCGR4_CG7_OFFSET 14 +#define MXC_CCM_CCGR4_CG6_OFFSET 12 +#define MXC_CCM_CCGR4_CG5_OFFSET 10 +#define MXC_CCM_CCGR4_CG4_OFFSET 8 +#define MXC_CCM_CCGR4_CG3_OFFSET 6 +#define MXC_CCM_CCGR4_CG2_OFFSET 4 +#define MXC_CCM_CCGR4_CG1_OFFSET 2 +#define MXC_CCM_CCGR4_CG0_OFFSET 0 + +#define MXC_CCM_CCGR5_CG15_OFFSET 30 +#define MXC_CCM_CCGR5_CG14_OFFSET 28 +#define MXC_CCM_CCGR5_CG14_MASK (0x3 << 28) +#define MXC_CCM_CCGR5_CG13_OFFSET 26 +#define MXC_CCM_CCGR5_CG13_MASK (0x3 << 26) +#define MXC_CCM_CCGR5_CG12_OFFSET 24 +#define MXC_CCM_CCGR5_CG12_MASK (0x3 << 24) +#define MXC_CCM_CCGR5_CG11_OFFSET 22 +#define MXC_CCM_CCGR5_CG11_MASK (0x3 << 22) +#define MXC_CCM_CCGR5_CG10_OFFSET 20 +#define MXC_CCM_CCGR5_CG10_MASK (0x3 << 20) +#define MXC_CCM_CCGR5_CG9_OFFSET 18 +#define MXC_CCM_CCGR5_CG9_MASK (0x3 << 18) +#define MXC_CCM_CCGR5_CG8_OFFSET 16 +#define MXC_CCM_CCGR5_CG8_MASK (0x3 << 16) +#define MXC_CCM_CCGR5_CG7_OFFSET 14 +#define MXC_CCM_CCGR5_CG7_MASK (0x3 << 14) +#define MXC_CCM_CCGR5_CG6_1_OFFSET 12 +#define MXC_CCM_CCGR5_CG6_2_OFFSET 13 +#define MXC_CCM_CCGR5_CG6_OFFSET 12 +#define MXC_CCM_CCGR5_CG6_MASK (0x3 << 12) +#define MXC_CCM_CCGR5_CG5_OFFSET 10 +#define MXC_CCM_CCGR5_CG4_OFFSET 8 +#define MXC_CCM_CCGR5_CG3_OFFSET 6 +#define MXC_CCM_CCGR5_CG2_OFFSET 4 +#define MXC_CCM_CCGR5_CG2_MASK (0x3 << 4) +#define MXC_CCM_CCGR5_CG1_OFFSET 2 +#define MXC_CCM_CCGR5_CG0_OFFSET 0 + +#define MXC_CCM_CCGR6_CG15_OFFSET 30 +#define MXC_CCM_CCGR6_CG14_OFFSET 28 +#define MXC_CCM_CCGR6_CG14_MASK (0x3 << 28) +#define MXC_CCM_CCGR6_CG13_OFFSET 26 +#define MXC_CCM_CCGR6_CG13_MASK (0x3 << 26) +#define MXC_CCM_CCGR6_CG12_OFFSET 24 +#define MXC_CCM_CCGR6_CG12_MASK (0x3 << 24) +#define MXC_CCM_CCGR6_CG11_OFFSET 22 +#define MXC_CCM_CCGR6_CG11_MASK (0x3 << 22) +#define MXC_CCM_CCGR6_CG10_OFFSET 20 +#define MXC_CCM_CCGR6_CG10_MASK (0x3 << 20) +#define MXC_CCM_CCGR6_CG9_OFFSET 18 +#define MXC_CCM_CCGR6_CG9_MASK (0x3 << 18) +#define MXC_CCM_CCGR6_CG8_OFFSET 16 +#define MXC_CCM_CCGR6_CG8_MASK (0x3 << 16) +#define MXC_CCM_CCGR6_CG7_OFFSET 14 +#define MXC_CCM_CCGR6_CG7_MASK (0x3 << 14) +#define MXC_CCM_CCGR6_CG6_OFFSET 12 +#define MXC_CCM_CCGR6_CG6_MASK (0x3 << 12) +#define MXC_CCM_CCGR6_CG5_OFFSET 10 +#define MXC_CCM_CCGR6_CG5_MASK (0x3 << 10) +#define MXC_CCM_CCGR6_CG4_OFFSET 8 +#define MXC_CCM_CCGR6_CG4_MASK (0x3 << 8) +#define MXC_CCM_CCGR6_CG3_OFFSET 6 +#define MXC_CCM_CCGR6_CG2_OFFSET 4 +#define MXC_CCM_CCGR6_CG2_MASK (0x3 << 4) +#define MXC_CCM_CCGR6_CG1_OFFSET 2 +#define MXC_CCM_CCGR6_CG0_OFFSET 0 + +#define MXC_CCM_CCGR7_CG15_OFFSET 30 +#define MXC_CCM_CCGR7_CG14_OFFSET 28 +#define MXC_CCM_CCGR7_CG14_MASK (0x3 << 28) +#define MXC_CCM_CCGR7_CG13_OFFSET 26 +#define MXC_CCM_CCGR7_CG13_MASK (0x3 << 26) +#define MXC_CCM_CCGR7_CG12_OFFSET 24 +#define MXC_CCM_CCGR7_CG12_MASK (0x3 << 24) +#define MXC_CCM_CCGR7_CG11_OFFSET 22 +#define MXC_CCM_CCGR7_CG11_MASK (0x3 << 22) +#define MXC_CCM_CCGR7_CG10_OFFSET 20 +#define MXC_CCM_CCGR7_CG10_MASK (0x3 << 20) +#define MXC_CCM_CCGR7_CG9_OFFSET 18 +#define MXC_CCM_CCGR7_CG9_MASK (0x3 << 18) +#define MXC_CCM_CCGR7_CG8_OFFSET 16 +#define MXC_CCM_CCGR7_CG8_MASK (0x3 << 16) +#define MXC_CCM_CCGR7_CG7_OFFSET 14 +#define MXC_CCM_CCGR7_CG7_MASK (0x3 << 14) +#define MXC_CCM_CCGR7_CG6_OFFSET 12 +#define MXC_CCM_CCGR7_CG6_MASK (0x3 << 12) +#define MXC_CCM_CCGR7_CG5_OFFSET 10 +#define MXC_CCM_CCGR7_CG4_OFFSET 8 +#define MXC_CCM_CCGR7_CG3_OFFSET 6 +#define MXC_CCM_CCGR7_CG2_OFFSET 4 +#define MXC_CCM_CCGR7_CG2_MASK (0x3 << 4) +#define MXC_CCM_CCGR7_CG1_OFFSET 2 +#define MXC_CCM_CCGR7_CG0_OFFSET 0 + +/* Define the bits in registers CLKSEQ_BYPASS */ +#define MXC_CCM_CLKSEQ_BYPASS_ELCDIF_PIX_OFFSET 14 +#define MXC_CCM_CLKSEQ_BYPASS_ELCDIF_PIX_MASK (0x3 << 14) +#define MXC_CCM_CLKSEQ_BYPASS_EPDC_PIX_OFFSET 12 +#define MXC_CCM_CLKSEQ_BYPASS_EPDC_PIX_MASK (0x3 << 12) +#define MXC_CCM_CLKSEQ_BYPASS_MSHCX_OFFSET 10 +#define MXC_CCM_CLKSEQ_BYPASS_MSHCX_MASK (0x3 << 10) +#define MXC_CCM_CLKSEQ_BYPASS_BCH_OFFSET 8 +#define MXC_CCM_CLKSEQ_BYPASS_BCH_MASK (0x3 << 8) +#define MXC_CCM_CLKSEQ_BYPASS_GPMI_OFFSET 6 +#define MXC_CCM_CLKSEQ_BYPASS_GPMI_MASK (0x3 << 6) +#define MXC_CCM_CLKSEQ_BYPASS_EPDC_OFFSET 4 +#define MXC_CCM_CLKSEQ_BYPASS_EPDC_MASK (0x3 << 4) +#define MXC_CCM_CLKSEQ_BYPASS_DISPLY_AXI_OFFSET 2 +#define MXC_CCM_CLKSEQ_BYPASS_DISPLY_AXI_MASK (0x3 << 2) +#define MXC_CCM_CLKSEQ_BYPASS_SYS_CLK_1 (0x1 << 1) +#define MXC_CCM_CLKSEQ_BYPASS_SYS_CLK_0 (0x1 << 0) + +/* Define the bits in registers CLK_SYS */ +#define MXC_CCM_CLK_SYS_XTAL_CLKGATE_OFFSET 30 +#define MXC_CCM_CLK_SYS_XTAL_CLKGATE_MASK (0x3 << 30) +#define MXC_CCM_CLK_SYS_PLL_CLKGATE_OFFSET 28 +#define MXC_CCM_CLK_SYS_PLL_CLKGATE_MASK (0x3 << 28) +#define MXC_CCM_CLK_SYS_DIV_XTAL_OFFSET 6 +#define MXC_CCM_CLK_SYS_DIV_XTAL_MASK (0xf << 6) +#define MXC_CCM_CLK_SYS_DIV_PLL_OFFSET 0 +#define MXC_CCM_CLK_SYS_DIV_PLL_MASK (0x3f << 0) + +/* Define the bits in registers CLK_DDR */ +#define MXC_CCM_CLK_DDR_DDR_CLKGATE_OFFSET (30) +#define MXC_CCM_CLK_DDR_DDR_CLKGATE_MASK (0x3 << 30) +#define MXC_CCM_CLK_DDR_DDR_PFD_SEL (1 << 6) +#define MXC_CCM_CLK_DDR_DDR_DIV_PLL_OFFSET (0) +#define MXC_CCM_CLK_DDR_DDR_DIV_PLL_MASK (0x3F) + + +#define MXC_GPC_BASE (IO_ADDRESS(GPC_BASE_ADDR)) +#define MXC_DPTC_LP_BASE (MXC_GPC_BASE + 0x80) +#define MXC_DPTC_GP_BASE (MXC_GPC_BASE + 0x100) +#define MXC_DVFS_CORE_BASE (MXC_GPC_BASE + 0x180) +#define MXC_DVFS_PER_BASE (MXC_GPC_BASE + 0x1C4) +#define MXC_PGC_IPU_BASE (MXC_GPC_BASE + 0x220) +#define MXC_PGC_VPU_BASE (MXC_GPC_BASE + 0x240) +#define MXC_PGC_GPU_BASE (MXC_GPC_BASE + 0x260) +#define MXC_SRPG_NEON_BASE (MXC_GPC_BASE + 0x280) +#define MXC_SRPG_ARM_BASE (MXC_GPC_BASE + 0x2A0) +#define MXC_SRPG_EMPGC0_BASE (MXC_GPC_BASE + 0x2C0) +#define MXC_SRPG_EMPGC1_BASE (MXC_GPC_BASE + 0x2D0) +#define MXC_SRPG_MEGAMIX_BASE (MXC_GPC_BASE + 0x2E0) +#define MXC_SRPG_EMI_BASE (MXC_GPC_BASE + 0x300) + +/* DVFS CORE */ +#define MXC_DVFSTHRS (MXC_DVFS_CORE_BASE + 0x00) +#define MXC_DVFSCOUN (MXC_DVFS_CORE_BASE + 0x04) +#define MXC_DVFSSIG1 (MXC_DVFS_CORE_BASE + 0x08) +#define MXC_DVFSSIG0 (MXC_DVFS_CORE_BASE + 0x0C) +#define MXC_DVFSGPC0 (MXC_DVFS_CORE_BASE + 0x10) +#define MXC_DVFSGPC1 (MXC_DVFS_CORE_BASE + 0x14) +#define MXC_DVFSGPBT (MXC_DVFS_CORE_BASE + 0x18) +#define MXC_DVFSEMAC (MXC_DVFS_CORE_BASE + 0x1C) +#define MXC_DVFSCNTR (MXC_DVFS_CORE_BASE + 0x20) +#define MXC_DVFSLTR0_0 (MXC_DVFS_CORE_BASE + 0x24) +#define MXC_DVFSLTR0_1 (MXC_DVFS_CORE_BASE + 0x28) +#define MXC_DVFSLTR1_0 (MXC_DVFS_CORE_BASE + 0x2C) +#define MXC_DVFSLTR1_1 (MXC_DVFS_CORE_BASE + 0x30) +#define MXC_DVFSPT0 (MXC_DVFS_CORE_BASE + 0x34) +#define MXC_DVFSPT1 (MXC_DVFS_CORE_BASE + 0x38) +#define MXC_DVFSPT2 (MXC_DVFS_CORE_BASE + 0x3C) +#define MXC_DVFSPT3 (MXC_DVFS_CORE_BASE + 0x40) + +/* DVFS PER */ +#define MXC_DVFSPER_LTR0 (MXC_DVFS_PER_BASE) +#define MXC_DVFSPER_LTR1 (MXC_DVFS_PER_BASE + 0x04) +#define MXC_DVFSPER_LTR2 (MXC_DVFS_PER_BASE + 0x08) +#define MXC_DVFSPER_LTR3 (MXC_DVFS_PER_BASE + 0x0C) +#define MXC_DVFSPER_LTBR0 (MXC_DVFS_PER_BASE + 0x10) +#define MXC_DVFSPER_LTBR1 (MXC_DVFS_PER_BASE + 0x14) +#define MXC_DVFSPER_PMCR0 (MXC_DVFS_PER_BASE + 0x18) +#define MXC_DVFSPER_PMCR1 (MXC_DVFS_PER_BASE + 0x1C) + +/* GPC */ +#define MXC_GPC_CNTR (MXC_GPC_BASE + 0x0) +#define MXC_GPC_PGR (MXC_GPC_BASE + 0x4) +#define MXC_GPC_VCR (MXC_GPC_BASE + 0x8) +#define MXC_GPC_ALL_PU (MXC_GPC_BASE + 0xC) +#define MXC_GPC_NEON (MXC_GPC_BASE + 0x10) + +/* PGC */ +#define MXC_PGC_IPU_PGCR (MXC_PGC_IPU_BASE + 0x0) +#define MXC_PGC_IPU_PGSR (MXC_PGC_IPU_BASE + 0xC) +#define MXC_PGC_VPU_PGCR (MXC_PGC_VPU_BASE + 0x0) +#define MXC_PGC_VPU_PGSR (MXC_PGC_VPU_BASE + 0xC) +#define MXC_PGC_GPU_PGCR (MXC_PGC_GPU_BASE + 0x0) +#define MXC_PGC_GPU_PGSR (MXC_PGC_GPU_BASE + 0xC) + +#define MXC_PGCR_PCR 1 +#define MXC_SRPGCR_PCR 1 +#define MXC_EMPGCR_PCR 1 +#define MXC_PGSR_PSR 1 + + +#define MXC_CORTEXA8_PLAT_LPC_DSM (1 << 0) +#define MXC_CORTEXA8_PLAT_LPC_DBG_DSM (1 << 1) + +/* SRPG */ +#define MXC_SRPG_NEON_SRPGCR (MXC_SRPG_NEON_BASE + 0x0) +#define MXC_SRPG_NEON_PUPSCR (MXC_SRPG_NEON_BASE + 0x4) +#define MXC_SRPG_NEON_PDNSCR (MXC_SRPG_NEON_BASE + 0x8) + +#define MXC_SRPG_ARM_SRPGCR (MXC_SRPG_ARM_BASE + 0x0) +#define MXC_SRPG_ARM_PUPSCR (MXC_SRPG_ARM_BASE + 0x4) +#define MXC_SRPG_ARM_PDNSCR (MXC_SRPG_ARM_BASE + 0x8) + +#define MXC_SRPG_EMPGC0_SRPGCR (MXC_SRPG_EMPGC0_BASE + 0x0) +#define MXC_SRPG_EMPGC0_PUPSCR (MXC_SRPG_EMPGC0_BASE + 0x4) +#define MXC_SRPG_EMPGC0_PDNSCR (MXC_SRPG_EMPGC0_BASE + 0x8) + +#define MXC_SRPG_EMPGC1_SRPGCR (MXC_SRPG_EMPGC1_BASE + 0x0) +#define MXC_SRPG_EMPGC1_PUPSCR (MXC_SRPG_EMPGC1_BASE + 0x4) +#define MXC_SRPG_EMPGC1_PDNSCR (MXC_SRPG_EMPGC1_BASE + 0x8) + +#define MXC_SRPG_MEGAMIX_SRPGCR (MXC_SRPG_MEGAMIX_BASE + 0x0) +#define MXC_SRPG_MEGAMIX_PUPSCR (MXC_SRPG_MEGAMIX_BASE + 0x4) +#define MXC_SRPG_MEGAMIX_PDNSCR (MXC_SRPG_MEGAMIX_BASE + 0x8) + +#define MXC_SRPGC_EMI_SRPGCR (MXC_SRPGC_EMI_BASE + 0x0) +#define MXC_SRPGC_EMI_PUPSCR (MXC_SRPGC_EMI_BASE + 0x4) +#define MXC_SRPGC_EMI_PDNSCR (MXC_SRPGC_EMI_BASE + 0x8) + +#endif /* __ARCH_ARM_MACH_MX50_CRM_REGS_H__ */ diff --git a/cpu/arm_cortexa8/mx50/generic.c b/cpu/arm_cortexa8/mx50/generic.c new file mode 100644 index 0000000000..d1562d1e8a --- /dev/null +++ b/cpu/arm_cortexa8/mx50/generic.c @@ -0,0 +1,1013 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include "crm_regs.h" +#ifdef CONFIG_CMD_CLOCK +#include +#endif +#include +#ifdef CONFIG_ARCH_CPU_INIT +#include +#endif + +enum pll_clocks { + PLL1_CLK = MXC_DPLL1_BASE, + PLL2_CLK = MXC_DPLL2_BASE, + PLL3_CLK = MXC_DPLL3_BASE, +}; + +enum pll_sw_clocks { + PLL1_SW_CLK, + PLL2_SW_CLK, + PLL3_SW_CLK, +}; + +#define AHB_CLK_ROOT 133333333 +#define IPG_CLK_ROOT 66666666 +#define IPG_PER_CLK_ROOT 40000000 + +#ifdef CONFIG_CMD_CLOCK +#define SZ_DEC_1M 1000000 +#define PLL_PD_MAX 16 /* Actual pd+1 */ +#define PLL_MFI_MAX 15 +#define PLL_MFI_MIN 5 +#define ARM_DIV_MAX 8 +#define IPG_DIV_MAX 4 +#define AHB_DIV_MAX 8 +#define EMI_DIV_MAX 8 +#define NFC_DIV_MAX 8 + +struct fixed_pll_mfd { + u32 ref_clk_hz; + u32 mfd; +}; + +const struct fixed_pll_mfd fixed_mfd[4] = { + {0, 0}, /* reserved */ + {0, 0}, /* reserved */ + {CONFIG_MX50_HCLK_FREQ, 24 * 16}, /* 384 */ + {0, 0}, /* reserved */ +}; + +struct pll_param { + u32 pd; + u32 mfi; + u32 mfn; + u32 mfd; +}; + +#define PLL_FREQ_MAX(_ref_clk_) \ + (4 * _ref_clk_ * PLL_MFI_MAX) +#define PLL_FREQ_MIN(_ref_clk_) \ + ((2 * _ref_clk_ * (PLL_MFI_MIN - 1)) / PLL_PD_MAX) +#define MAX_DDR_CLK 420000000 +#define AHB_CLK_MAX 133333333 +#define IPG_CLK_MAX (AHB_CLK_MAX / 2) +#define NFC_CLK_MAX 25000000 +#define HSP_CLK_MAX 133333333 +#endif + +static u32 __decode_pll(enum pll_clocks pll, u32 infreq) +{ + long mfi, mfn, mfd, pdf, ref_clk, mfn_abs; + unsigned long dp_op, dp_mfd, dp_mfn, dp_ctl, pll_hfsm, dbl; + s64 temp; + + dp_ctl = __REG(pll + MXC_PLL_DP_CTL); + pll_hfsm = dp_ctl & MXC_PLL_DP_CTL_HFSM; + dbl = dp_ctl & MXC_PLL_DP_CTL_DPDCK0_2_EN; + + if (pll_hfsm == 0) { + dp_op = __REG(pll + MXC_PLL_DP_OP); + dp_mfd = __REG(pll + MXC_PLL_DP_MFD); + dp_mfn = __REG(pll + MXC_PLL_DP_MFN); + } else { + dp_op = __REG(pll + MXC_PLL_DP_HFS_OP); + dp_mfd = __REG(pll + MXC_PLL_DP_HFS_MFD); + dp_mfn = __REG(pll + MXC_PLL_DP_HFS_MFN); + } + pdf = dp_op & MXC_PLL_DP_OP_PDF_MASK; + mfi = (dp_op & MXC_PLL_DP_OP_MFI_MASK) >> MXC_PLL_DP_OP_MFI_OFFSET; + mfi = (mfi <= 5) ? 5 : mfi; + mfd = dp_mfd & MXC_PLL_DP_MFD_MASK; + mfn = mfn_abs = dp_mfn & MXC_PLL_DP_MFN_MASK; + /* Sign extend to 32-bits */ + if (mfn >= 0x04000000) { + mfn |= 0xFC000000; + mfn_abs = -mfn; + } + + ref_clk = 2 * infreq; + if (dbl != 0) + ref_clk *= 2; + + ref_clk /= (pdf + 1); + temp = (u64) ref_clk * mfn_abs; + do_div(temp, mfd + 1); + if (mfn < 0) + temp = -temp; + temp = (ref_clk * mfi) + temp; + + return temp; +} + +static u32 __get_mcu_main_clk(void) +{ + u32 reg, freq; + reg = (__REG(MXC_CCM_CACRR) & MXC_CCM_CACRR_ARM_PODF_MASK) >> + MXC_CCM_CACRR_ARM_PODF_OFFSET; + freq = __decode_pll(PLL1_CLK, CONFIG_MX50_HCLK_FREQ); + return freq / (reg + 1); +} + +/* + * This function returns the low power audio clock. + */ +u32 __get_lp_apm(void) +{ + u32 ret_val = 0; + u32 cbcmr = __REG(MXC_CCM_CBCMR); + + if (((cbcmr >> MXC_CCM_CBCMR_LP_APM_SEL_OFFSET) & 0x1) == 0) + ret_val = CONFIG_MX50_HCLK_FREQ; + else + ret_val = ((32768 * 1024)); + + return ret_val; +} + +static u32 __get_periph_clk(void) +{ + u32 reg; + reg = __REG(MXC_CCM_CBCDR); + + switch ((reg & MXC_CCM_CBCDR_PERIPH_CLK_SEL_MASK) >> + MXC_CCM_CBCDR_PERIPH_CLK_SEL_OFFSET) { + case 0: + return __decode_pll(PLL1_CLK, CONFIG_MX50_HCLK_FREQ); + case 1: + return __decode_pll(PLL2_CLK, CONFIG_MX50_HCLK_FREQ); + case 2: + return __decode_pll(PLL3_CLK, CONFIG_MX50_HCLK_FREQ); + default: + return __get_lp_apm(); + } +} + +static u32 __get_ipg_clk(void) +{ + u32 ahb_podf, ipg_podf; + + ahb_podf = __REG(MXC_CCM_CBCDR); + ipg_podf = (ahb_podf & MXC_CCM_CBCDR_IPG_PODF_MASK) >> + MXC_CCM_CBCDR_IPG_PODF_OFFSET; + ahb_podf = (ahb_podf & MXC_CCM_CBCDR_AHB_PODF_MASK) >> + MXC_CCM_CBCDR_AHB_PODF_OFFSET; + return __get_periph_clk() / ((ahb_podf + 1) * (ipg_podf + 1)); +} + +static u32 __get_ipg_per_clk(void) +{ + u32 pred1, pred2, podf, clk; + if (__REG(MXC_CCM_CBCMR) & MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL) + return __get_ipg_clk(); + + clk = __REG(MXC_CCM_CBCMR) & MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL ? + __get_lp_apm() : __get_periph_clk(); + + podf = __REG(MXC_CCM_CBCDR); + pred1 = (podf & MXC_CCM_CBCDR_PERCLK_PRED1_MASK) >> + MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET; + pred2 = (podf & MXC_CCM_CBCDR_PERCLK_PRED2_MASK) >> + MXC_CCM_CBCDR_PERCLK_PRED2_OFFSET; + podf = (podf & MXC_CCM_CBCDR_PERCLK_PODF_MASK) >> + MXC_CCM_CBCDR_PERCLK_PODF_OFFSET; + + return clk / ((pred1 + 1) * (pred2 + 1) * (podf + 1)); +} + +static u32 __get_uart_clk(void) +{ + u32 freq = 0, reg, pred, podf; + reg = __REG(MXC_CCM_CSCMR1); + switch ((reg & MXC_CCM_CSCMR1_UART_CLK_SEL_MASK) >> + MXC_CCM_CSCMR1_UART_CLK_SEL_OFFSET) { + case 0x0: + freq = __decode_pll(PLL1_CLK, CONFIG_MX50_HCLK_FREQ); + break; + case 0x1: + freq = __decode_pll(PLL2_CLK, CONFIG_MX50_HCLK_FREQ); + break; + case 0x2: + freq = __decode_pll(PLL3_CLK, CONFIG_MX50_HCLK_FREQ); + break; + case 0x3: + freq = __get_lp_apm(); + break; + default: + break; + } + + reg = __REG(MXC_CCM_CSCDR1); + + pred = (reg & MXC_CCM_CSCDR1_UART_CLK_PRED_MASK) >> + MXC_CCM_CSCDR1_UART_CLK_PRED_OFFSET; + + podf = (reg & MXC_CCM_CSCDR1_UART_CLK_PODF_MASK) >> + MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET; + freq /= (pred + 1) * (podf + 1); + + return freq; +} + + +static u32 __get_cspi_clk(void) +{ + u32 ret_val = 0, pdf, pre_pdf, clk_sel, div; + u32 cscmr1 = __REG(MXC_CCM_CSCMR1); + u32 cscdr2 = __REG(MXC_CCM_CSCDR2); + + pre_pdf = (cscdr2 & MXC_CCM_CSCDR2_CSPI_CLK_PRED_MASK) \ + >> MXC_CCM_CSCDR2_CSPI_CLK_PRED_OFFSET; + pdf = (cscdr2 & MXC_CCM_CSCDR2_CSPI_CLK_PODF_MASK) \ + >> MXC_CCM_CSCDR2_CSPI_CLK_PODF_OFFSET; + clk_sel = (cscmr1 & MXC_CCM_CSCMR1_CSPI_CLK_SEL_MASK) \ + >> MXC_CCM_CSCMR1_CSPI_CLK_SEL_OFFSET; + + div = (pre_pdf + 1) * (pdf + 1); + + switch (clk_sel) { + case 0: + ret_val = __decode_pll(PLL1_CLK, CONFIG_MX50_HCLK_FREQ) / div; + break; + case 1: + ret_val = __decode_pll(PLL2_CLK, CONFIG_MX50_HCLK_FREQ) / div; + break; + case 2: + ret_val = __decode_pll(PLL3_CLK, CONFIG_MX50_HCLK_FREQ) / div; + break; + default: + ret_val = __get_lp_apm() / div; + break; + } + + return ret_val; +} + +static u32 __get_axi_a_clk(void) +{ + u32 cbcdr = __REG(MXC_CCM_CBCDR); + u32 pdf = (cbcdr & MXC_CCM_CBCDR_AXI_A_PODF_MASK) \ + >> MXC_CCM_CBCDR_AXI_A_PODF_OFFSET; + + return __get_periph_clk() / (pdf + 1); +} + +static u32 __get_axi_b_clk(void) +{ + u32 cbcdr = __REG(MXC_CCM_CBCDR); + u32 pdf = (cbcdr & MXC_CCM_CBCDR_AXI_B_PODF_MASK) \ + >> MXC_CCM_CBCDR_AXI_B_PODF_OFFSET; + + return __get_periph_clk() / (pdf + 1); +} + +static u32 __get_ahb_clk(void) +{ + u32 cbcdr = __REG(MXC_CCM_CBCDR); + u32 pdf = (cbcdr & MXC_CCM_CBCDR_AHB_PODF_MASK) \ + >> MXC_CCM_CBCDR_AHB_PODF_OFFSET; + + return __get_periph_clk() / (pdf + 1); +} + + +static u32 __get_emi_slow_clk(void) +{ + u32 cbcdr = __REG(MXC_CCM_CBCDR); + u32 emi_clk_sel = cbcdr & MXC_CCM_CBCDR_WEIM_CLK_SEL; + u32 pdf = (cbcdr & MXC_CCM_CBCDR_WEIM_PODF_MASK) \ + >> MXC_CCM_CBCDR_WEIM_PODF_OFFSET; + + if (emi_clk_sel) + return __get_ahb_clk() / (pdf + 1); + + return __get_periph_clk() / (pdf + 1); +} + +static u32 __get_sys_clk(void) +{ + u32 ret_val = 0, clk, sys_pll_div; + u32 clkseq_bypass = __REG(MXC_CCM_CLKSEQ_BYPASS); + + /* Fixme Not handle OSC and PFD1 mux */ + if ((clkseq_bypass & MXC_CCM_CLKSEQ_BYPASS_SYS_CLK_1) && + clkseq_bypass & MXC_CCM_CLKSEQ_BYPASS_SYS_CLK_0) { + sys_pll_div = __REG(MXC_CCM_CLK_SYS) \ + & MXC_CCM_CLK_SYS_DIV_PLL_MASK; + clk = __decode_pll(PLL1_CLK, CONFIG_MX50_HCLK_FREQ); + if (sys_pll_div) + clk /= sys_pll_div; + ret_val = clk; + } else if ((clkseq_bypass & MXC_CCM_CLKSEQ_BYPASS_SYS_CLK_0) == 0) { + ret_val = CONFIG_MX50_HCLK_FREQ; /* OSC */ + } else { + + printf("Warning, Fixme Not handle PFD1 mux\n"); + } + + return ret_val; + +} +static u32 __get_ddr_clk(void) +{ + u32 ret_val = 0, clk, ddr_pll_div; + u32 clk_ddr = __REG(MXC_CCM_CLK_DDR); + u32 ddr_clk_sel = clk_ddr & MXC_CCM_CLK_DDR_DDR_PFD_SEL; + + if (!ddr_clk_sel) { + ddr_pll_div = clk_ddr & \ + MXC_CCM_CLK_DDR_DDR_DIV_PLL_MASK; + clk = __decode_pll(PLL1_CLK, CONFIG_MX50_HCLK_FREQ); + if (ddr_pll_div) + clk /= ddr_pll_div; + ret_val = clk; + } else { + + printf("Warning, Fixme Not handle PFD1 mux\n"); + } + + return ret_val; +} + +#ifdef CONFIG_CMD_MMC +static u32 __get_esdhc1_clk(void) +{ + u32 ret_val = 0, div, pre_pdf, pdf; + u32 cscmr1 = __REG(MXC_CCM_CSCMR1); + u32 cscdr1 = __REG(MXC_CCM_CSCDR1); + u32 esdh1_clk_sel; + + esdh1_clk_sel = (cscmr1 & MXC_CCM_CSCMR1_ESDHC1_CLK_SEL_MASK) \ + >> MXC_CCM_CSCMR1_ESDHC1_CLK_SEL_OFFSET; + pre_pdf = (cscdr1 & MXC_CCM_CSCDR1_ESDHC1_CLK_PRED_MASK) \ + >> MXC_CCM_CSCDR1_ESDHC1_CLK_PRED_OFFSET; + pdf = (cscdr1 & MXC_CCM_CSCDR1_ESDHC1_CLK_PODF_MASK) \ + >> MXC_CCM_CSCDR1_ESDHC1_CLK_PODF_OFFSET ; + + div = (pre_pdf + 1) * (pdf + 1); + + switch (esdh1_clk_sel) { + case 0: + ret_val = __decode_pll(PLL1_CLK, CONFIG_MX50_HCLK_FREQ); + break; + case 1: + ret_val = __decode_pll(PLL2_CLK, CONFIG_MX50_HCLK_FREQ); + break; + case 2: + ret_val = __decode_pll(PLL3_CLK, CONFIG_MX50_HCLK_FREQ); + break; + case 3: + ret_val = __get_lp_apm(); + break; + default: + break; + } + + ret_val /= div; + + return ret_val; +} + +static u32 __get_esdhc3_clk(void) +{ + u32 ret_val = 0, div, pre_pdf, pdf; + u32 esdh3_clk_sel; + u32 cscmr1 = __REG(MXC_CCM_CSCMR1); + u32 cscdr1 = __REG(MXC_CCM_CSCDR1); + esdh3_clk_sel = (cscmr1 & MXC_CCM_CSCMR1_ESDHC3_CLK_SEL_MASK) \ + >> MXC_CCM_CSCMR1_ESDHC3_CLK_SEL_OFFSET; + pre_pdf = (cscdr1 & MXC_CCM_CSCDR1_ESDHC3_CLK_PRED_MASK) \ + >> MXC_CCM_CSCDR1_ESDHC3_CLK_PRED_OFFSET; + pdf = (cscdr1 & MXC_CCM_CSCDR1_ESDHC3_CLK_PODF_MASK) \ + >> MXC_CCM_CSCDR1_ESDHC3_CLK_PODF_OFFSET ; + + div = (pre_pdf + 1) * (pdf + 1); + + switch (esdh3_clk_sel) { + case 0: + ret_val = __decode_pll(PLL1_CLK, CONFIG_MX50_HCLK_FREQ); + break; + case 1: + ret_val = __decode_pll(PLL2_CLK, CONFIG_MX50_HCLK_FREQ); + break; + case 2: + ret_val = __decode_pll(PLL3_CLK, CONFIG_MX50_HCLK_FREQ); + break; + case 3: + ret_val = __get_lp_apm(); + break; + case 5 ... 8: + puts("Warning, Fixme,not handle PFD mux\n"); + + break; + default: + break; + } + + ret_val /= div; + + return ret_val; +} + +static u32 __get_esdhc2_clk(void) +{ + u32 cscmr1 = __REG(MXC_CCM_CSCMR1); + u32 esdh2_clk_sel = cscmr1 & MXC_CCM_CSCMR1_ESDHC2_CLK_SEL; + if (esdh2_clk_sel) + return __get_esdhc3_clk(); + + return __get_esdhc1_clk(); +} + +static u32 __get_esdhc4_clk(void) +{ + u32 cscmr1 = __REG(MXC_CCM_CSCMR1); + u32 esdh4_clk_sel = cscmr1 & MXC_CCM_CSCMR1_ESDHC4_CLK_SEL; + if (esdh4_clk_sel) + return __get_esdhc3_clk(); + + return __get_esdhc1_clk(); +} +#endif + +unsigned int mxc_get_clock(enum mxc_clock clk) +{ + switch (clk) { + case MXC_ARM_CLK: + return __get_mcu_main_clk(); + case MXC_PER_CLK: + return __get_periph_clk(); + case MXC_AHB_CLK: + return __get_ahb_clk(); + case MXC_IPG_CLK: + return __get_ipg_clk(); + case MXC_IPG_PERCLK: + return __get_ipg_per_clk(); + case MXC_UART_CLK: + return __get_uart_clk(); +#ifdef CONFIG_IMX_CSPI + case MXC_CSPI_CLK: + return __get_cspi_clk(); +#endif + case MXC_AXI_A_CLK: + return __get_axi_a_clk(); + case MXC_AXI_B_CLK: + return __get_axi_b_clk(); + case MXC_EMI_SLOW_CLK: + return __get_emi_slow_clk(); + case MXC_DDR_CLK: + return __get_ddr_clk(); +#ifdef CONFIG_CMD_MMC + case MXC_ESDHC_CLK: + return __get_esdhc1_clk(); + case MXC_ESDHC2_CLK: + return __get_esdhc2_clk(); + case MXC_ESDHC3_CLK: + return __get_esdhc3_clk(); + case MXC_ESDHC4_CLK: + return __get_esdhc4_clk(); +#endif + default: + break; + } + return -1; +} + +void mxc_dump_clocks(void) +{ + u32 freq; + freq = __decode_pll(PLL1_CLK, CONFIG_MX50_HCLK_FREQ); + printf("mx50 pll1: %dMHz\n", freq / 1000000); + freq = __decode_pll(PLL2_CLK, CONFIG_MX50_HCLK_FREQ); + printf("mx50 pll2: %dMHz\n", freq / 1000000); + freq = __decode_pll(PLL3_CLK, CONFIG_MX50_HCLK_FREQ); + printf("mx50 pll3: %dMHz\n", freq / 1000000); + printf("ipg clock : %dHz\n", mxc_get_clock(MXC_IPG_CLK)); + printf("ipg per clock : %dHz\n", mxc_get_clock(MXC_IPG_PERCLK)); + printf("uart clock : %dHz\n", mxc_get_clock(MXC_UART_CLK)); +#ifdef CONFIG_IMX_ECSPI + printf("cspi clock : %dHz\n", mxc_get_clock(MXC_CSPI_CLK)); +#endif + printf("ahb clock : %dHz\n", mxc_get_clock(MXC_AHB_CLK)); + printf("axi_a clock : %dHz\n", mxc_get_clock(MXC_AXI_A_CLK)); + printf("axi_b clock : %dHz\n", mxc_get_clock(MXC_AXI_B_CLK)); + printf("weim_clock : %dHz\n", mxc_get_clock(MXC_EMI_SLOW_CLK)); + printf("ddr clock : %dHz\n", mxc_get_clock(MXC_DDR_CLK)); +#ifdef CONFIG_CMD_MMC + printf("esdhc1 clock : %dHz\n", mxc_get_clock(MXC_ESDHC_CLK)); + printf("esdhc2 clock : %dHz\n", mxc_get_clock(MXC_ESDHC2_CLK)); + printf("esdhc3 clock : %dHz\n", mxc_get_clock(MXC_ESDHC3_CLK)); + printf("esdhc4 clock : %dHz\n", mxc_get_clock(MXC_ESDHC4_CLK)); +#endif +} + +#ifdef CONFIG_CMD_CLOCK +/* precondition: m>0 and n>0. Let g=gcd(m,n). */ +static int gcd(int m, int n) +{ + int t; + while (m > 0) { + if (n > m) { + t = m; + m = n; + n = t; + } /* swap */ + m -= n; + } + return n; +} + +/*! + * This is to calculate various parameters based on reference clock and + * targeted clock based on the equation: + * t_clk = 2*ref_freq*(mfi + mfn/(mfd+1))/(pd+1) + * This calculation is based on a fixed MFD value for simplicity. + * + * @param ref reference clock freq in Hz + * @param target targeted clock in Hz + * @param pll pll_param structure. + * + * @return 0 if successful; non-zero otherwise. + */ +static int calc_pll_params(u32 ref, u32 target, struct pll_param *pll) +{ + u64 pd, mfi = 1, mfn, mfd, t1; + u32 n_target = target; + u32 n_ref = ref, i; + + /* + * Make sure targeted freq is in the valid range. + * Otherwise the following calculation might be wrong!!! + */ + if (n_target < PLL_FREQ_MIN(ref) || + n_target > PLL_FREQ_MAX(ref)) { + printf("Targeted peripheral clock should be" + "within [%d - %d]\n", + PLL_FREQ_MIN(ref) / SZ_DEC_1M, + PLL_FREQ_MAX(ref) / SZ_DEC_1M); + return -1; + } + + for (i = 0; i < ARRAY_SIZE(fixed_mfd); i++) { + if (fixed_mfd[i].ref_clk_hz == ref) { + mfd = fixed_mfd[i].mfd; + break; + } + } + + if (i == ARRAY_SIZE(fixed_mfd)) + return -1; + + /* Use n_target and n_ref to avoid overflow */ + for (pd = 1; pd <= PLL_PD_MAX; pd++) { + t1 = n_target * pd; + do_div(t1, (4 * n_ref)); + mfi = t1; + if (mfi > PLL_MFI_MAX) + return -1; + else if (mfi < 5) + continue; + break; + } + /* Now got pd and mfi already */ + /* + mfn = (((n_target * pd) / 4 - n_ref * mfi) * mfd) / n_ref; + */ + t1 = n_target * pd; + do_div(t1, 4); + t1 -= n_ref * mfi; + t1 *= mfd; + do_div(t1, n_ref); + mfn = t1; +#ifdef CMD_CLOCK_DEBUG + printf("%d: ref=%d, target=%d, pd=%d," + "mfi=%d,mfn=%d, mfd=%d\n", + __LINE__, ref, (u32)n_target, + (u32)pd, (u32)mfi, (u32)mfn, + (u32)mfd); +#endif + i = 1; + if (mfn != 0) + i = gcd(mfd, mfn); + pll->pd = (u32)pd; + pll->mfi = (u32)mfi; + do_div(mfn, i); + pll->mfn = (u32)mfn; + do_div(mfd, i); + pll->mfd = (u32)mfd; + + return 0; +} + +int clk_info(u32 clk_type) +{ + switch (clk_type) { + case CPU_CLK: + printf("CPU Clock: %dHz\n", + mxc_get_clock(MXC_ARM_CLK)); + break; + case PERIPH_CLK: + printf("Peripheral Clock: %dHz\n", + mxc_get_clock(MXC_PER_CLK)); + break; + case AHB_CLK: + printf("AHB Clock: %dHz\n", + mxc_get_clock(MXC_AHB_CLK)); + break; + case IPG_CLK: + printf("IPG Clock: %dHz\n", + mxc_get_clock(MXC_IPG_CLK)); + break; + case IPG_PERCLK: + printf("IPG_PER Clock: %dHz\n", + mxc_get_clock(MXC_IPG_PERCLK)); + break; + case UART_CLK: + printf("UART Clock: %dHz\n", + mxc_get_clock(MXC_UART_CLK)); + break; + case CSPI_CLK: + printf("CSPI Clock: %dHz\n", + mxc_get_clock(MXC_CSPI_CLK)); + break; + case DDR_CLK: + printf("DDR Clock: %dHz\n", + mxc_get_clock(MXC_DDR_CLK)); + break; + case ALL_CLK: + printf("cpu clock: %dMHz\n", + mxc_get_clock(MXC_ARM_CLK) / SZ_DEC_1M); + mxc_dump_clocks(); + break; + default: + printf("Unsupported clock type! :(\n"); + } + + return 0; +} + +#define calc_div(target_clk, src_clk, limit) ({ \ + u32 tmp = 0; \ + if ((src_clk % target_clk) <= 100) \ + tmp = src_clk / target_clk; \ + else \ + tmp = (src_clk / target_clk) + 1; \ + if (tmp > limit) \ + tmp = limit; \ + (tmp - 1); \ + }) + +u32 calc_per_cbcdr_val(u32 per_clk, u32 cbcmr) +{ + u32 cbcdr = __REG(MXC_CCM_CBCDR); + u32 tmp_clk = 0, div = 0, clk_sel = 0; + + cbcdr &= ~MXC_CCM_CBCDR_PERIPH_CLK_SEL; + + /* emi_slow_podf divider */ + tmp_clk = __get_emi_slow_clk(); + clk_sel = cbcdr & MXC_CCM_CBCDR_EMI_CLK_SEL; + if (clk_sel) { + div = calc_div(tmp_clk, per_clk, 8); + cbcdr &= ~MXC_CCM_CBCDR_EMI_PODF_MASK; + cbcdr |= (div << MXC_CCM_CBCDR_EMI_PODF_OFFSET); + } + + /* axi_b_podf divider */ + tmp_clk = __get_axi_b_clk(); + div = calc_div(tmp_clk, per_clk, 8); + cbcdr &= ~MXC_CCM_CBCDR_AXI_B_PODF_MASK; + cbcdr |= (div << MXC_CCM_CBCDR_AXI_B_PODF_OFFSET); + + /* axi_b_podf divider */ + tmp_clk = __get_axi_a_clk(); + div = calc_div(tmp_clk, per_clk, 8); + cbcdr &= ~MXC_CCM_CBCDR_AXI_A_PODF_MASK; + cbcdr |= (div << MXC_CCM_CBCDR_AXI_A_PODF_OFFSET); + + /* ahb podf divider */ + tmp_clk = AHB_CLK_ROOT; + div = calc_div(tmp_clk, per_clk, 8); + cbcdr &= ~MXC_CCM_CBCDR_AHB_PODF_MASK; + cbcdr |= (div << MXC_CCM_CBCDR_AHB_PODF_OFFSET); + + return cbcdr; +} + +#define CHANGE_PLL_SETTINGS(base, pd, mfi, mfn, mfd) \ + { \ + writel(0x1232, base + PLL_DP_CTL); \ + writel(0x2, base + PLL_DP_CONFIG); \ + writel(((pd - 1) << 0) | (mfi << 4), \ + base + PLL_DP_OP); \ + writel(mfn, base + PLL_DP_MFN); \ + writel(mfd - 1, base + PLL_DP_MFD); \ + writel(((pd - 1) << 0) | (mfi << 4), \ + base + PLL_DP_HFS_OP); \ + writel(mfn, base + PLL_DP_HFS_MFN); \ + writel(mfd - 1, base + PLL_DP_HFS_MFD); \ + writel(0x1232, base + PLL_DP_CTL); \ + while (!readl(base + PLL_DP_CTL) & 0x1) \ + ; \ + } + +int config_pll_clk(enum pll_clocks pll, struct pll_param *pll_param) +{ + u32 ccsr = readl(CCM_BASE_ADDR + CLKCTL_CCSR); + u32 pll_base = pll; + + switch (pll) { + case PLL1_CLK: + /* Switch ARM to PLL2 clock */ + writel(ccsr | 0x4, CCM_BASE_ADDR + CLKCTL_CCSR); + CHANGE_PLL_SETTINGS(pll_base, pll_param->pd, + pll_param->mfi, pll_param->mfn, + pll_param->mfd); + /* Switch back */ + writel(ccsr & ~0x4, CCM_BASE_ADDR + CLKCTL_CCSR); + break; + case PLL2_CLK: + /* Switch to pll2 bypass clock */ + writel(ccsr | 0x2, CCM_BASE_ADDR + CLKCTL_CCSR); + CHANGE_PLL_SETTINGS(pll_base, pll_param->pd, + pll_param->mfi, pll_param->mfn, + pll_param->mfd); + /* Switch back */ + writel(ccsr & ~0x2, CCM_BASE_ADDR + CLKCTL_CCSR); + break; + case PLL3_CLK: + /* Switch to pll3 bypass clock */ + writel(ccsr | 0x1, CCM_BASE_ADDR + CLKCTL_CCSR); + CHANGE_PLL_SETTINGS(pll_base, pll_param->pd, + pll_param->mfi, pll_param->mfn, + pll_param->mfd); + /* Switch back */ + writel(ccsr & ~0x1, CCM_BASE_ADDR + CLKCTL_CCSR); + break; + default: + return -1; + } + + return 0; +} + +int config_core_clk(u32 ref, u32 freq) +{ + int ret = 0; + u32 pll = 0; + struct pll_param pll_param; + + memset(&pll_param, 0, sizeof(struct pll_param)); + + /* The case that periph uses PLL1 is not considered here */ + pll = freq; + ret = calc_pll_params(ref, pll, &pll_param); + if (ret != 0) { + printf("Can't find pll parameters: %d\n", + ret); + return ret; + } + + return config_pll_clk(PLL1_CLK, &pll_param); +} + +int config_periph_clk(u32 ref, u32 freq) +{ + int ret = 0; + u32 pll = freq; + struct pll_param pll_param; + + memset(&pll_param, 0, sizeof(struct pll_param)); + + if (__REG(MXC_CCM_CBCDR) & MXC_CCM_CBCDR_PERIPH_CLK_SEL) { + /* Actually this case is not considered here */ + ret = calc_pll_params(ref, pll, &pll_param); + if (ret != 0) { + printf("Can't find pll parameters: %d\n", + ret); + return ret; + } + switch ((__REG(MXC_CCM_CBCMR) & \ + MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK) >> + MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET) { + case 0: + return config_pll_clk(PLL1_CLK, &pll_param); + break; + case 1: + return config_pll_clk(PLL3_CLK, &pll_param); + break; + default: + return -1; + } + } else { + u32 old_cbcmr = readl(CCM_BASE_ADDR + CLKCTL_CBCMR); + u32 new_cbcdr = calc_per_cbcdr_val(pll, old_cbcmr); + + /* Switch peripheral to PLL3 */ + writel(0x00015154, CCM_BASE_ADDR + CLKCTL_CBCMR); + writel(0x02888945, CCM_BASE_ADDR + CLKCTL_CBCDR); + + /* Make sure change is effective */ + while (readl(CCM_BASE_ADDR + CLKCTL_CDHIPR) != 0) + ; + + /* Setup PLL2 */ + ret = calc_pll_params(ref, pll, &pll_param); + if (ret != 0) { + printf("Can't find pll parameters: %d\n", + ret); + return ret; + } + config_pll_clk(PLL2_CLK, &pll_param); + + /* Switch peripheral back */ + writel(new_cbcdr, CCM_BASE_ADDR + CLKCTL_CBCDR); + writel(old_cbcmr, CCM_BASE_ADDR + CLKCTL_CBCMR); + + /* Make sure change is effective */ + while (readl(CCM_BASE_ADDR + CLKCTL_CDHIPR) != 0) + ; + puts("\n"); + } + + return 0; +} + +int config_ddr_clk(u32 emi_clk) +{ + u32 clk_src; + s32 shift = 0, clk_sel, div = 1; + u32 cbcmr = readl(CCM_BASE_ADDR + CLKCTL_CBCMR); + u32 cbcdr = readl(CCM_BASE_ADDR + CLKCTL_CBCDR); + + if (emi_clk > MAX_DDR_CLK) { + printf("DDR clock should be less than" + "%d MHz, assuming max value \n", + (MAX_DDR_CLK / SZ_DEC_1M)); + emi_clk = MAX_DDR_CLK; + } + + clk_src = __get_periph_clk(); + /* Find DDR clock input */ + clk_sel = (cbcmr >> 10) & 0x3; + switch (clk_sel) { + case 0: + shift = 16; + break; + case 1: + shift = 19; + break; + case 2: + shift = 22; + break; + case 3: + shift = 10; + break; + default: + return -1; + } + + if ((clk_src % emi_clk) == 0) + div = clk_src / emi_clk; + else + div = (clk_src / emi_clk) + 1; + if (div > 8) + div = 8; + + cbcdr = cbcdr & ~(0x7 << shift); + cbcdr |= ((div - 1) << shift); + writel(cbcdr, CCM_BASE_ADDR + CLKCTL_CBCDR); + while (readl(CCM_BASE_ADDR + CLKCTL_CDHIPR) != 0) + ; + writel(0x0, CCM_BASE_ADDR + CLKCTL_CCDR); + + return 0; +} + +/*! + * This function assumes the expected core clock has to be changed by + * modifying the PLL. This is NOT true always but for most of the times, + * it is. So it assumes the PLL output freq is the same as the expected + * core clock (presc=1) unless the core clock is less than PLL_FREQ_MIN. + * In the latter case, it will try to increase the presc value until + * (presc*core_clk) is greater than PLL_FREQ_MIN. It then makes call to + * calc_pll_params() and obtains the values of PD, MFI,MFN, MFD based + * on the targeted PLL and reference input clock to the PLL. Lastly, + * it sets the register based on these values along with the dividers. + * Note 1) There is no value checking for the passed-in divider values + * so the caller has to make sure those values are sensible. + * 2) Also adjust the NFC divider such that the NFC clock doesn't + * exceed NFC_CLK_MAX. + * 3) IPU HSP clock is independent of AHB clock. Even it can go up to + * 177MHz for higher voltage, this function fixes the max to 133MHz. + * 4) This function should not have allowed diag_printf() calls since + * the serial driver has been stoped. But leave then here to allow + * easy debugging by NOT calling the cyg_hal_plf_serial_stop(). + * + * @param ref pll input reference clock (24MHz) + * @param freq core clock in Hz + * @param clk_type clock type, e.g CPU_CLK, DDR_CLK, etc. + * @return 0 if successful; non-zero otherwise + */ +int clk_config(u32 ref, u32 freq, u32 clk_type) +{ + freq *= SZ_DEC_1M; + + switch (clk_type) { + case CPU_CLK: + if (config_core_clk(ref, freq)) + return -1; + break; + case PERIPH_CLK: + if (config_periph_clk(ref, freq)) + return -1; + break; + case DDR_CLK: + if (config_ddr_clk(freq)) + return -1; + break; + default: + printf("Unsupported or invalid clock type! :(\n"); + } + + return 0; +} +#endif + +#if defined(CONFIG_DISPLAY_CPUINFO) +int print_cpuinfo(void) +{ + printf("CPU: Freescale i.MX50 family %d.%dV at %d MHz\n", + (get_board_rev() & 0xFF) >> 4, + (get_board_rev() & 0xF), + __get_mcu_main_clk() / 1000000); +#ifndef CONFIG_CMD_CLOCK + mxc_dump_clocks(); +#endif + return 0; +} +#endif + +#if defined(CONFIG_MXC_FEC) +extern int mxc_fec_initialize(bd_t *bis); +extern void mxc_fec_set_mac_from_env(char *mac_addr); +#endif + +int cpu_eth_init(bd_t *bis) +{ + int rc = -ENODEV; +#if defined(CONFIG_MXC_FEC) + rc = mxc_fec_initialize(bis); +#endif + return rc; +} + +#if defined(CONFIG_ARCH_CPU_INIT) +int arch_cpu_init(void) +{ + icache_enable(); + dcache_enable(); + +#ifdef CONFIG_L2_OFF + l2_cache_disable(); +#else + l2_cache_enable(); +#endif + return 0; +} +#endif + diff --git a/cpu/arm_cortexa8/mx50/interrupts.c b/cpu/arm_cortexa8/mx50/interrupts.c new file mode 100644 index 0000000000..45765073b1 --- /dev/null +++ b/cpu/arm_cortexa8/mx50/interrupts.c @@ -0,0 +1,39 @@ +/* + * (C) Copyright 2007 + * Sascha Hauer, Pengutronix + * + * Copyright (C) 2010 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +/* nothing really to do with interrupts, just starts up a counter. */ +int interrupt_init(void) +{ + return 0; +} + +void reset_cpu(ulong addr) +{ + __REG16(WDOG1_BASE_ADDR) = 4; +} diff --git a/cpu/arm_cortexa8/mx50/iomux.c b/cpu/arm_cortexa8/mx50/iomux.c new file mode 100644 index 0000000000..66f1bf742e --- /dev/null +++ b/cpu/arm_cortexa8/mx50/iomux.c @@ -0,0 +1,137 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include + +/*! + * IOMUX register (base) addresses + */ +enum iomux_reg_addr { + IOMUXGPR0 = IOMUXC_BASE_ADDR, + IOMUXGPR1 = IOMUXC_BASE_ADDR + 0x004, + IOMUXGPR2 = IOMUXC_BASE_ADDR + 0x008, + IOMUXSW_MUX_CTL = IOMUXC_BASE_ADDR, + IOMUXSW_MUX_END = IOMUXC_BASE_ADDR + MUX_I_END, + IOMUXSW_PAD_CTL = IOMUXC_BASE_ADDR + PAD_I_START, + IOMUXSW_INPUT_CTL = IOMUXC_BASE_ADDR + INPUT_CTL_START, +}; + +static inline u32 _get_mux_reg(iomux_pin_name_t pin) +{ + u32 mux_reg = PIN_TO_IOMUX_MUX(pin); + + mux_reg += IOMUXSW_MUX_CTL; + + return mux_reg; +} + +static inline u32 _get_pad_reg(iomux_pin_name_t pin) +{ + u32 pad_reg = PIN_TO_IOMUX_PAD(pin); + + pad_reg += IOMUXSW_PAD_CTL; + + return pad_reg; +} + +static inline u32 _get_mux_end(void) +{ + return IOMUXSW_MUX_END; +} + +/*! + * This function is used to configure a pin through the IOMUX module. + * FIXED ME: for backward compatible. Will be static function! + * @param pin a pin number as defined in \b #iomux_pin_name_t + * @param cfg an output function as defined in \b #iomux_pin_cfg_t + * + * @return 0 if successful; Non-zero otherwise + */ +static int iomux_config_mux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg) +{ + u32 mux_reg = _get_mux_reg(pin); + + if ((mux_reg > _get_mux_end()) || (mux_reg < IOMUXSW_MUX_CTL)) + return -1; + if (cfg == IOMUX_CONFIG_GPIO) + writel(PIN_TO_ALT_GPIO(pin), mux_reg); + else + writel(cfg, mux_reg); + + return 0; +} + +/*! + * Request ownership for an IO pin. This function has to be the first one + * being called before that pin is used. The caller has to check the + * return value to make sure it returns 0. + * + * @param pin a name defined by \b iomux_pin_name_t + * @param cfg an input function as defined in \b #iomux_pin_cfg_t + * + * @return 0 if successful; Non-zero otherwise + */ +int mxc_request_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg) +{ + int ret = iomux_config_mux(pin, cfg); + + return ret; +} + +/*! + * Release ownership for an IO pin + * + * @param pin a name defined by \b iomux_pin_name_t + * @param cfg an input function as defined in \b #iomux_pin_cfg_t + */ +void mxc_free_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg) +{ +} + +/*! + * This function configures the pad value for a IOMUX pin. + * + * @param pin a pin number as defined in \b #iomux_pin_name_t + * @param config the ORed value of elements defined in \b #iomux_pad_config_t + */ +void mxc_iomux_set_pad(iomux_pin_name_t pin, u32 config) +{ + u32 pad_reg = _get_pad_reg(pin); + + writel(config, pad_reg); +} + +unsigned int mxc_iomux_get_pad(iomux_pin_name_t pin) +{ + u32 pad_reg = _get_pad_reg(pin); + + return readl(pad_reg); +} +/*! + * This function configures input path. + * + * @param input index of input select register as defined in \b + * #iomux_input_select_t + * @param config the binary value of elements defined in \b + * #iomux_input_config_t + */ +void mxc_iomux_set_input(iomux_input_select_t input, u32 config) +{ + u32 reg = IOMUXSW_INPUT_CTL + (input << 2); + + writel(config, reg); +} diff --git a/cpu/arm_cortexa8/mx50/serial.c b/cpu/arm_cortexa8/mx50/serial.c new file mode 100644 index 0000000000..a0cef257b2 --- /dev/null +++ b/cpu/arm_cortexa8/mx50/serial.c @@ -0,0 +1,226 @@ +/* + * (c) 2007 Sascha Hauer + * + * Copyright (C) 2010 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#include + +#if defined CONFIG_MX50_UART + +#include + +#ifdef CONFIG_MX50_UART1 +#define UART_PHYS UART1_BASE_ADDR +#elif defined(CONFIG_MX50_UART2) +#define UART_PHYS UART2_BASE_ADDR +#elif defined(CONFIG_MX50_UART3) +#define UART_PHYS UART3_BASE_ADDR +#else +#error "define CFG_MX50_UARTx to use the mx50 UART driver" +#endif + +/* Register definitions */ +#define URXD 0x0 /* Receiver Register */ +#define UTXD 0x40 /* Transmitter Register */ +#define UCR1 0x80 /* Control Register 1 */ +#define UCR2 0x84 /* Control Register 2 */ +#define UCR3 0x88 /* Control Register 3 */ +#define UCR4 0x8c /* Control Register 4 */ +#define UFCR 0x90 /* FIFO Control Register */ +#define USR1 0x94 /* Status Register 1 */ +#define USR2 0x98 /* Status Register 2 */ +#define UESC 0x9c /* Escape Character Register */ +#define UTIM 0xa0 /* Escape Timer Register */ +#define UBIR 0xa4 /* BRM Incremental Register */ +#define UBMR 0xa8 /* BRM Modulator Register */ +#define UBRC 0xac /* Baud Rate Count Register */ +#define UTS 0xb4 /* UART Test Register (mx31) */ + +/* UART Control Register Bit Fields.*/ +#define URXD_CHARRDY (1<<15) +#define URXD_ERR (1<<14) +#define URXD_OVRRUN (1<<13) +#define URXD_FRMERR (1<<12) +#define URXD_BRK (1<<11) +#define URXD_PRERR (1<<10) +#define UCR1_ADEN (1<<15) /* Auto dectect interrupt */ +#define UCR1_ADBR (1<<14) /* Auto detect baud rate */ +#define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */ +#define UCR1_IDEN (1<<12) /* Idle condition interrupt */ +#define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */ +#define UCR1_RDMAEN (1<<8) /* Recv ready DMA enable */ +#define UCR1_IREN (1<<7) /* Infrared interface enable */ +#define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */ +#define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */ +#define UCR1_SNDBRK (1<<4) /* Send break */ +#define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */ +#define UCR1_UARTCLKEN (1<<2) /* UART clock enabled */ +#define UCR1_DOZE (1<<1) /* Doze */ +#define UCR1_UARTEN (1<<0) /* UART enabled */ +#define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */ +#define UCR2_IRTS (1<<14) /* Ignore RTS pin */ +#define UCR2_CTSC (1<<13) /* CTS pin control */ +#define UCR2_CTS (1<<12) /* Clear to send */ +#define UCR2_ESCEN (1<<11) /* Escape enable */ +#define UCR2_PREN (1<<8) /* Parity enable */ +#define UCR2_PROE (1<<7) /* Parity odd/even */ +#define UCR2_STPB (1<<6) /* Stop */ +#define UCR2_WS (1<<5) /* Word size */ +#define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */ +#define UCR2_TXEN (1<<2) /* Transmitter enabled */ +#define UCR2_RXEN (1<<1) /* Receiver enabled */ +#define UCR2_SRST (1<<0) /* SW reset */ +#define UCR3_DTREN (1<<13) /* DTR interrupt enable */ +#define UCR3_PARERREN (1<<12) /* Parity enable */ +#define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */ +#define UCR3_DSR (1<<10) /* Data set ready */ +#define UCR3_DCD (1<<9) /* Data carrier detect */ +#define UCR3_RI (1<<8) /* Ring indicator */ +#define UCR3_TIMEOUTEN (1<<7) /* Timeout interrupt enable */ +#define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */ +#define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */ +#define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */ +#define UCR3_REF25 (1<<3) /* Ref freq 25 MHz */ +#define UCR3_REF30 (1<<2) /* Ref Freq 30 MHz */ +#define UCR3_INVT (1<<1) /* Inverted Infrared transmission */ +#define UCR3_BPEN (1<<0) /* Preset registers enable */ +#define UCR4_CTSTL_32 (32<<10) /* CTS trigger level (32 chars) */ +#define UCR4_INVR (1<<9) /* Inverted infrared reception */ +#define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */ +#define UCR4_WKEN (1<<7) /* Wake interrupt enable */ +#define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */ +#define UCR4_IRSC (1<<5) /* IR special case */ +#define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */ +#define UCR4_BKEN (1<<2) /* Break condition interrupt enable */ +#define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */ +#define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */ +#define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */ +#define UFCR_RFDIV (7<<7) /* Reference freq divider mask */ +#define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */ +#define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */ +#define USR1_RTSS (1<<14) /* RTS pin status */ +#define USR1_TRDY (1<<13)/* Transmitter ready interrupt/dma flag */ +#define USR1_RTSD (1<<12) /* RTS delta */ +#define USR1_ESCF (1<<11) /* Escape seq interrupt flag */ +#define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */ +#define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */ +#define USR1_TIMEOUT (1<<7) /* Receive timeout interrupt status */ +#define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */ +#define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */ +#define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */ +#define USR2_ADET (1<<15) /* Auto baud rate detect complete */ +#define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */ +#define USR2_DTRF (1<<13) /* DTR edge interrupt flag */ +#define USR2_IDLE (1<<12) /* Idle condition */ +#define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */ +#define USR2_WAKE (1<<7) /* Wake */ +#define USR2_RTSF (1<<4) /* RTS edge interrupt flag */ +#define USR2_TXDC (1<<3) /* Transmitter complete */ +#define USR2_BRCD (1<<2) /* Break condition */ +#define USR2_ORE (1<<1) /* Overrun error */ +#define USR2_RDR (1<<0) /* Recv data ready */ +#define UTS_FRCPERR (1<<13) /* Force parity error */ +#define UTS_LOOP (1<<12) /* Loop tx and rx */ +#define UTS_TXEMPTY (1<<6) /* TxFIFO empty */ +#define UTS_RXEMPTY (1<<5) /* RxFIFO empty */ +#define UTS_TXFULL (1<<4) /* TxFIFO full */ +#define UTS_RXFULL (1<<3) /* RxFIFO full */ +#define UTS_SOFTRST (1<<0) /* Software reset */ + +DECLARE_GLOBAL_DATA_PTR; + +void serial_setbrg(void) +{ + u32 clk = mxc_get_clock(MXC_UART_CLK); + + if (!gd->baudrate) + gd->baudrate = CONFIG_BAUDRATE; + __REG(UART_PHYS + UFCR) = 0x4 << 7; /* divide input clock by 2 */ + __REG(UART_PHYS + UBIR) = 0xf; + __REG(UART_PHYS + UBMR) = clk / (2 * gd->baudrate); +} + +int serial_getc(void) +{ + while (__REG(UART_PHYS + UTS) & UTS_RXEMPTY) + ; + return __REG(UART_PHYS + URXD); +} + +void serial_putc(const char c) +{ + __REG(UART_PHYS + UTXD) = c; + + /* wait for transmitter to be ready */ + while (!(__REG(UART_PHYS + UTS) & UTS_TXEMPTY)) + ; + + /* If \n, also do \r */ + if (c == '\n') + serial_putc('\r'); +} + +/* + * Test whether a character is in the RX buffer + */ +int serial_tstc(void) +{ + /* If receive fifo is empty, return false */ + if (__REG(UART_PHYS + UTS) & UTS_RXEMPTY) + return 0; + return 1; +} + +void serial_puts(const char *s) +{ + while (*s) + serial_putc(*s++); +} + +/* + * Initialise the serial port with the given baudrate. The settings + * are always 8 data bits, no parity, 1 stop bit, no start bits. + * + */ +int serial_init(void) +{ + __REG(UART_PHYS + UCR1) = 0x0; + __REG(UART_PHYS + UCR2) = 0x0; + + while (!(__REG(UART_PHYS + UCR2) & UCR2_SRST)) + ; + + __REG(UART_PHYS + UCR3) = 0x0704; + __REG(UART_PHYS + UCR4) = 0x8000; + __REG(UART_PHYS + UESC) = 0x002b; + __REG(UART_PHYS + UTIM) = 0x0; + + __REG(UART_PHYS + UTS) = 0x0; + + serial_setbrg(); + + __REG(UART_PHYS + UCR2) = + UCR2_WS | UCR2_IRTS | UCR2_RXEN | UCR2_TXEN | UCR2_SRST; + + __REG(UART_PHYS + UCR1) = UCR1_UARTEN; + + return 0; +} + +#endif /* CONFIG_MX50_UART */ diff --git a/cpu/arm_cortexa8/mx50/timer.c b/cpu/arm_cortexa8/mx50/timer.c new file mode 100644 index 0000000000..00150abdf2 --- /dev/null +++ b/cpu/arm_cortexa8/mx50/timer.c @@ -0,0 +1,127 @@ +/* + * (C) Copyright 2007 + * Sascha Hauer, Pengutronix + * + * Copyright (C) 2010 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +/* General purpose timers registers */ +#define GPTCR __REG(GPT1_BASE_ADDR) /* Control register */ +#define GPTPR __REG(GPT1_BASE_ADDR + 0x4) /* Prescaler register */ +#define GPTSR __REG(GPT1_BASE_ADDR + 0x8) /* Status register */ +#define GPTCNT __REG(GPT1_BASE_ADDR + 0x24) /* Counter register */ + +/* General purpose timers bitfields */ +#define GPTCR_SWR (1<<15) /* Software reset */ +#define GPTCR_FRR (1<<9) /* Freerun / restart */ +#define GPTCR_CLKSOURCE_32 (0x100<<6) /* Clock source */ +#define GPTCR_CLKSOURCE_IPG (0x001<<6) /* Clock source */ +#define GPTCR_TEN (1) /* Timer enable */ +#define GPTPR_VAL (50) + +static inline void setup_gpt(void) +{ + int i; + static int init_done; + + if (init_done) + return; + + init_done = 1; + + /* setup GP Timer 1 */ + GPTCR = GPTCR_SWR; + for (i = 0; i < 100; i++) + GPTCR = 0; /* We have no udelay by now */ + GPTPR = GPTPR_VAL; /* 50Mhz / 50 */ + /* Freerun Mode, PERCLK1 input */ + GPTCR |= GPTCR_CLKSOURCE_IPG | GPTCR_TEN; +} + +int timer_init(void) +{ + setup_gpt(); + + return 0; +} + +void reset_timer_masked(void) +{ + GPTCR = 0; + /* Freerun Mode, PERCLK1 input */ + GPTCR = GPTCR_CLKSOURCE_IPG | GPTCR_TEN; +} + +inline ulong get_timer_masked(void) +{ + ulong val = GPTCNT; + + return val; +} + +void reset_timer(void) +{ + reset_timer_masked(); +} + +ulong get_timer(ulong base) +{ + ulong tmp; + + tmp = get_timer_masked(); + + if (tmp <= (base * 1000)) { + /* Overflow */ + tmp += (0xffffffff - base); + } + + return (tmp / 1000) - base; +} + +void set_timer(ulong t) +{ +} + +/* delay x useconds AND perserve advance timstamp value */ +/* GPTCNT is now supposed to tick 1 by 1 us. */ +void udelay(unsigned long usec) +{ + ulong tmp; + + setup_gpt(); + + tmp = get_timer_masked(); /* get current timestamp */ + + /* if setting this forward will roll time stamp */ + if ((usec + tmp + 1) < tmp) { + /* reset "advancing" timestamp to 0, set lastinc value */ + reset_timer_masked(); + } else { + /* else, set advancing stamp wake up time */ + tmp += usec; + } + + while (get_timer_masked() < tmp) /* loop till event */ + /*NOP*/; +} diff --git a/cpu/arm_cortexa8/mx51/Makefile b/cpu/arm_cortexa8/mx51/Makefile new file mode 100644 index 0000000000..79f697dbf2 --- /dev/null +++ b/cpu/arm_cortexa8/mx51/Makefile @@ -0,0 +1,51 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# (C) Copyright 2009 Freescale Semiconductor, Inc. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(SOC).a + +COBJS = interrupts.o serial.o generic.o iomux.o timer.o cache.o +COBJS-$(CONFIG_CMD_FUSE) += cmd_fuse.o +COBJS-$(CONFIG_IMX_FUSE) += imx_fuse.o +COBJS += $(COBJS-y) +SOBJS = mxc_nand_load.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) + +all: $(obj).depend $(LIB) + +$(LIB): $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/cpu/arm_cortexa8/mx51/cache.c b/cpu/arm_cortexa8/mx51/cache.c new file mode 100644 index 0000000000..7c79f2f251 --- /dev/null +++ b/cpu/arm_cortexa8/mx51/cache.c @@ -0,0 +1,44 @@ +/* + * (C) Copyright 2010 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +void l2_cache_enable(void) +{ + asm("mrc 15, 0, r0, c1, c0, 1"); + asm("orr r0, r0, #0x2"); + asm("mcr 15, 0, r0, c1, c0, 1"); +} + +void l2_cache_disable(void) +{ + asm("mrc 15, 0, r0, c1, c0, 1"); + asm("bic r0, r0, #0x2"); + asm("mcr 15, 0, r0, c1, c0, 1"); +} + +/*dummy function for L2 ON*/ +u32 get_device_type(void) +{ + return 0; +} diff --git a/cpu/arm_cortexa8/mx51/crm_regs.h b/cpu/arm_cortexa8/mx51/crm_regs.h new file mode 100644 index 0000000000..8a2b2dc13e --- /dev/null +++ b/cpu/arm_cortexa8/mx51/crm_regs.h @@ -0,0 +1,669 @@ +/* + * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#ifndef __ARCH_ARM_MACH_MX51_CRM_REGS_H__ +#define __ARCH_ARM_MACH_MX51_CRM_REGS_H__ + +#define MXC_CCM_BASE CCM_BASE_ADDR +#define MXC_DPLL1_BASE PLL1_BASE_ADDR +#define MXC_DPLL2_BASE PLL2_BASE_ADDR +#define MXC_DPLL3_BASE PLL3_BASE_ADDR + +/* PLL Register Offsets */ +#define MXC_PLL_DP_CTL 0x00 +#define MXC_PLL_DP_CONFIG 0x04 +#define MXC_PLL_DP_OP 0x08 +#define MXC_PLL_DP_MFD 0x0C +#define MXC_PLL_DP_MFN 0x10 +#define MXC_PLL_DP_MFNMINUS 0x14 +#define MXC_PLL_DP_MFNPLUS 0x18 +#define MXC_PLL_DP_HFS_OP 0x1C +#define MXC_PLL_DP_HFS_MFD 0x20 +#define MXC_PLL_DP_HFS_MFN 0x24 +#define MXC_PLL_DP_MFN_TOGC 0x28 +#define MXC_PLL_DP_DESTAT 0x2c + +/* PLL Register Bit definitions */ +#define MXC_PLL_DP_CTL_MUL_CTRL 0x2000 +#define MXC_PLL_DP_CTL_DPDCK0_2_EN 0x1000 +#define MXC_PLL_DP_CTL_DPDCK0_2_OFFSET 12 +#define MXC_PLL_DP_CTL_ADE 0x800 +#define MXC_PLL_DP_CTL_REF_CLK_DIV 0x400 +#define MXC_PLL_DP_CTL_REF_CLK_SEL_MASK (3 << 8) +#define MXC_PLL_DP_CTL_REF_CLK_SEL_OFFSET 8 +#define MXC_PLL_DP_CTL_HFSM 0x80 +#define MXC_PLL_DP_CTL_PRE 0x40 +#define MXC_PLL_DP_CTL_UPEN 0x20 +#define MXC_PLL_DP_CTL_RST 0x10 +#define MXC_PLL_DP_CTL_RCP 0x8 +#define MXC_PLL_DP_CTL_PLM 0x4 +#define MXC_PLL_DP_CTL_BRM0 0x2 +#define MXC_PLL_DP_CTL_LRF 0x1 + +#define MXC_PLL_DP_CONFIG_BIST 0x8 +#define MXC_PLL_DP_CONFIG_SJC_CE 0x4 +#define MXC_PLL_DP_CONFIG_AREN 0x2 +#define MXC_PLL_DP_CONFIG_LDREQ 0x1 + +#define MXC_PLL_DP_OP_MFI_OFFSET 4 +#define MXC_PLL_DP_OP_MFI_MASK (0xF << 4) +#define MXC_PLL_DP_OP_PDF_OFFSET 0 +#define MXC_PLL_DP_OP_PDF_MASK 0xF + +#define MXC_PLL_DP_MFD_OFFSET 0 +#define MXC_PLL_DP_MFD_MASK 0x07FFFFFF + +#define MXC_PLL_DP_MFN_OFFSET 0x0 +#define MXC_PLL_DP_MFN_MASK 0x07FFFFFF + +#define MXC_PLL_DP_MFN_TOGC_TOG_DIS (1 << 17) +#define MXC_PLL_DP_MFN_TOGC_TOG_EN (1 << 16) +#define MXC_PLL_DP_MFN_TOGC_CNT_OFFSET 0x0 +#define MXC_PLL_DP_MFN_TOGC_CNT_MASK 0xFFFF + +#define MXC_PLL_DP_DESTAT_TOG_SEL (1 << 31) +#define MXC_PLL_DP_DESTAT_MFN 0x07FFFFFF + +/* Register addresses of CCM*/ +#define MXC_CCM_CCR (MXC_CCM_BASE + 0x00) +#define MXC_CCM_CCDR (MXC_CCM_BASE + 0x04) +#define MXC_CCM_CSR (MXC_CCM_BASE + 0x08) +#define MXC_CCM_CCSR (MXC_CCM_BASE + 0x0C) +#define MXC_CCM_CACRR (MXC_CCM_BASE + 0x10) +#define MXC_CCM_CBCDR (MXC_CCM_BASE + 0x14) +#define MXC_CCM_CBCMR (MXC_CCM_BASE + 0x18) +#define MXC_CCM_CSCMR1 (MXC_CCM_BASE + 0x1C) +#define MXC_CCM_CSCMR2 (MXC_CCM_BASE + 0x20) +#define MXC_CCM_CSCDR1 (MXC_CCM_BASE + 0x24) +#define MXC_CCM_CS1CDR (MXC_CCM_BASE + 0x28) +#define MXC_CCM_CS2CDR (MXC_CCM_BASE + 0x2C) +#define MXC_CCM_CDCDR (MXC_CCM_BASE + 0x30) +#define MXC_CCM_CHSCDR (MXC_CCM_BASE + 0x34) +#define MXC_CCM_CSCDR2 (MXC_CCM_BASE + 0x38) +#define MXC_CCM_CSCDR3 (MXC_CCM_BASE + 0x3C) +#define MXC_CCM_CSCDR4 (MXC_CCM_BASE + 0x40) +#define MXC_CCM_CWDR (MXC_CCM_BASE + 0x44) +#define MXC_CCM_CDHIPR (MXC_CCM_BASE + 0x48) +#define MXC_CCM_CDCR (MXC_CCM_BASE + 0x4C) +#define MXC_CCM_CTOR (MXC_CCM_BASE + 0x50) +#define MXC_CCM_CLPCR (MXC_CCM_BASE + 0x54) +#define MXC_CCM_CISR (MXC_CCM_BASE + 0x58) +#define MXC_CCM_CIMR (MXC_CCM_BASE + 0x5C) +#define MXC_CCM_CCOSR (MXC_CCM_BASE + 0x60) +#define MXC_CCM_CGPR (MXC_CCM_BASE + 0x64) +#define MXC_CCM_CCGR0 (MXC_CCM_BASE + 0x68) +#define MXC_CCM_CCGR1 (MXC_CCM_BASE + 0x6C) +#define MXC_CCM_CCGR2 (MXC_CCM_BASE + 0x70) +#define MXC_CCM_CCGR3 (MXC_CCM_BASE + 0x74) +#define MXC_CCM_CCGR4 (MXC_CCM_BASE + 0x78) +#define MXC_CCM_CCGR5 (MXC_CCM_BASE + 0x7C) +#define MXC_CCM_CCGR6 (MXC_CCM_BASE + 0x80) +#define MXC_CCM_CMEOR (MXC_CCM_BASE + 0x84) + +/* Define the bits in register CCR */ +#define MXC_CCM_CCR_COSC_EN (1 << 12) +#define MXC_CCM_CCR_FPM_MULT_MASK (1 << 11) +#define MXC_CCM_CCR_CAMP2_EN (1 << 10) +#define MXC_CCM_CCR_CAMP1_EN (1 << 9) +#define MXC_CCM_CCR_FPM_EN (1 << 8) +#define MXC_CCM_CCR_OSCNT_OFFSET (0) +#define MXC_CCM_CCR_OSCNT_MASK (0xFF) + +/* Define the bits in register CCDR */ +#define MXC_CCM_CCDR_HSC_HS_MASK (0x1 << 18) +#define MXC_CCM_CCDR_IPU_HS_MASK (0x1 << 17) +#define MXC_CCM_CCDR_EMI_HS_MASK (0x1 << 16) + +/* Define the bits in register CSR */ +#define MXC_CCM_CSR_COSR_READY (1 << 5) +#define MXC_CCM_CSR_LVS_VALUE (1 << 4) +#define MXC_CCM_CSR_CAMP2_READY (1 << 3) +#define MXC_CCM_CSR_CAMP1_READY (1 << 2) +#define MXC_CCM_CSR_FPM_READY (1 << 1) +#define MXC_CCM_CSR_REF_EN_B (1 << 0) + +/* Define the bits in register CCSR */ +#define MXC_CCM_CCSR_LP_APM_SEL (0x1 << 9) +#define MXC_CCM_CCSR_STEP_SEL_OFFSET (7) +#define MXC_CCM_CCSR_STEP_SEL_MASK (0x3 << 7) +#define MXC_CCM_CCSR_PLL2_PODF_OFFSET (5) +#define MXC_CCM_CCSR_PLL2_PODF_MASK (0x3 << 5) +#define MXC_CCM_CCSR_PLL3_PODF_OFFSET (3) +#define MXC_CCM_CCSR_PLL3_PODF_MASK (0x3 << 3) +#define MXC_CCM_CCSR_PLL1_SW_CLK_SEL (1 << 2) +#define MXC_CCM_CCSR_PLL2_SW_CLK_SEL (1 << 1) +#define MXC_CCM_CCSR_PLL3_SW_CLK_SEL (1 << 0) + +/* Define the bits in register CACRR */ +#define MXC_CCM_CACRR_ARM_PODF_OFFSET (0) +#define MXC_CCM_CACRR_ARM_PODF_MASK (0x7) + +/* Define the bits in register CBCDR */ +#define MXC_CCM_CBCDR_EMI_CLK_SEL (0x1 << 26) +#define MXC_CCM_CBCDR_PERIPH_CLK_SEL (0x1 << 25) +#define MXC_CCM_CBCDR_EMI_PODF_OFFSET (22) +#define MXC_CCM_CBCDR_EMI_PODF_MASK (0x7 << 22) +#define MXC_CCM_CBCDR_AXI_B_PODF_OFFSET (19) +#define MXC_CCM_CBCDR_AXI_B_PODF_MASK (0x7 << 19) +#define MXC_CCM_CBCDR_AXI_A_PODF_OFFSET (16) +#define MXC_CCM_CBCDR_AXI_A_PODF_MASK (0x7 << 16) +#define MXC_CCM_CBCDR_NFC_PODF_OFFSET (13) +#define MXC_CCM_CBCDR_NFC_PODF_MASK (0x7 << 13) +#define MXC_CCM_CBCDR_AHB_PODF_OFFSET (10) +#define MXC_CCM_CBCDR_AHB_PODF_MASK (0x7 << 10) +#define MXC_CCM_CBCDR_IPG_PODF_OFFSET (8) +#define MXC_CCM_CBCDR_IPG_PODF_MASK (0x3 << 8) +#define MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET (6) +#define MXC_CCM_CBCDR_PERCLK_PRED1_MASK (0x3 << 6) +#define MXC_CCM_CBCDR_PERCLK_PRED2_OFFSET (3) +#define MXC_CCM_CBCDR_PERCLK_PRED2_MASK (0x7 << 3) +#define MXC_CCM_CBCDR_PERCLK_PODF_OFFSET (0) +#define MXC_CCM_CBCDR_PERCLK_PODF_MASK (0x7) + +/* Define the bits in register CBCMR */ +#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET (14) +#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_MASK (0x3 << 14) +#define MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET (12) +#define MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK (0x3 << 12) +#define MXC_CCM_CBCMR_DDR_CLK_SEL_OFFSET (10) +#define MXC_CCM_CBCMR_DDR_CLK_SEL_MASK (0x3 << 10) +#define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_OFFSET (8) +#define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_MASK (0x3 << 8) +#define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_OFFSET (6) +#define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_MASK (0x3 << 6) +#define MXC_CCM_CBCMR_GPU_CLK_SEL_OFFSET (4) +#define MXC_CCM_CBCMR_GPU_CLK_SEL_MASK (0x3 << 4) +#define MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL (0x1 << 1) +#define MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL (0x1 << 0) + +/* Define the bits in register CSCMR1 */ +#define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_OFFSET (30) +#define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_MASK (0x3 << 30) +#define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_OFFSET (28) +#define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_MASK (0x3 << 28) +#define MXC_CCM_CSCMR1_USB_PHY_CLK_SEL_OFFSET (26) +#define MXC_CCM_CSCMR1_USB_PHY_CLK_SEL (0x1 << 26) +#define MXC_CCM_CSCMR1_UART_CLK_SEL_OFFSET (24) +#define MXC_CCM_CSCMR1_UART_CLK_SEL_MASK (0x3 << 24) +#define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_OFFSET (22) +#define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_MASK (0x3 << 22) +#define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_OFFSET (20) +#define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_MASK (0x3 << 20) +#define MXC_CCM_CSCMR1_ESDHC3_CLK_SEL (0x1 << 19) +#define MXC_CCM_CSCMR1_ESDHC4_CLK_SEL (0x1 << 18) +#define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_OFFSET (16) +#define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_MASK (0x3 << 16) +#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET (14) +#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK (0x3 << 14) +#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET (12) +#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_MASK (0x3 << 12) +#define MXC_CCM_CSCMR1_SSI3_CLK_SEL (0x1 << 11) +#define MXC_CCM_CSCMR1_VPU_RCLK_SEL (0x1 << 10) +#define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_OFFSET (8) +#define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_MASK (0x3 << 8) +#define MXC_CCM_CSCMR1_TVE_CLK_SEL (0x1 << 7) +#define MXC_CCM_CSCMR1_TVE_EXT_CLK_SEL (0x1 << 6) +#define MXC_CCM_CSCMR1_CSPI_CLK_SEL_OFFSET (4) +#define MXC_CCM_CSCMR1_CSPI_CLK_SEL_MASK (0x3 << 4) +#define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_OFFSET (2) +#define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_MASK (0x3 << 2) +#define MXC_CCM_CSCMR1_SSI_EXT2_COM_CLK_SEL (0x1 << 1) +#define MXC_CCM_CSCMR1_SSI_EXT1_COM_CLK_SEL (0x1) + +/* Define the bits in register CSCMR2 */ +#define MXC_CCM_CSCMR2_DI_CLK_SEL_OFFSET (26) +#define MXC_CCM_CSCMR2_DI_CLK_SEL_MASK (0x7 << 26) +#define MXC_CCM_CSCMR2_CSI_MCLK2_CLK_SEL_OFFSET (24) +#define MXC_CCM_CSCMR2_CSI_MCLK2_CLK_SEL_MASK (0x3 << 24) +#define MXC_CCM_CSCMR2_CSI_MCLK1_CLK_SEL_OFFSET (22) +#define MXC_CCM_CSCMR2_CSI_MCLK1_CLK_SEL_MASK (0x3 << 22) +#define MXC_CCM_CSCMR2_ESC_CLK_SEL_OFFSET (20) +#define MXC_CCM_CSCMR2_ESC_CLK_SEL_MASK (0x3 << 20) +#define MXC_CCM_CSCMR2_HSC2_CLK_SEL_OFFSET (18) +#define MXC_CCM_CSCMR2_HSC2_CLK_SEL_MASK (0x3 << 18) +#define MXC_CCM_CSCMR2_HSC1_CLK_SEL_OFFSET (16) +#define MXC_CCM_CSCMR2_HSC1_CLK_SEL_MASK (0x3 << 16) +#define MXC_CCM_CSCMR2_HSI2C_CLK_SEL_OFFSET (14) +#define MXC_CCM_CSCMR2_HSI2C_CLK_SEL_MASK (0x3 << 14) +#define MXC_CCM_CSCMR2_FIRI_CLK_SEL_OFFSET (12) +#define MXC_CCM_CSCMR2_FIRI_CLK_SEL_MASK (0x3 << 12) +#define MXC_CCM_CSCMR2_SIM_CLK_SEL_OFFSET (10) +#define MXC_CCM_CSCMR2_SIM_CLK_SEL_MASK (0x3 << 10) +#define MXC_CCM_CSCMR2_SLIMBUS_COM (0x1 << 9) +#define MXC_CCM_CSCMR2_SLIMBUS_CLK_SEL_OFFSET (6) +#define MXC_CCM_CSCMR2_SLIMBUS_CLK_SEL_MASK (0x7 << 6) +#define MXC_CCM_CSCMR2_SPDIF1_COM (1 << 5) +#define MXC_CCM_CSCMR2_SPDIF0_COM (1 << 4) +#define MXC_CCM_CSCMR2_SPDIF1_CLK_SEL_OFFSET (2) +#define MXC_CCM_CSCMR2_SPDIF1_CLK_SEL_MASK (0x3 << 2) +#define MXC_CCM_CSCMR2_SPDIF0_CLK_SEL_OFFSET (0) +#define MXC_CCM_CSCMR2_SPDIF0_CLK_SEL_MASK (0x3) + +/* Define the bits in register CSCDR1 */ +#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_OFFSET (22) +#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_MASK (0x7 << 22) +#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_OFFSET (19) +#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_MASK (0x7 << 19) +#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_OFFSET (16) +#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_MASK (0x7 << 16) +#define MXC_CCM_CSCDR1_PGC_CLK_PODF_OFFSET (14) +#define MXC_CCM_CSCDR1_PGC_CLK_PODF_MASK (0x3 << 14) +#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_OFFSET (11) +#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_MASK (0x7 << 11) +#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET (8) +#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK (0x7 << 8) +#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET (6) +#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK (0x3 << 6) +#define MXC_CCM_CSCDR1_UART_CLK_PRED_OFFSET (3) +#define MXC_CCM_CSCDR1_UART_CLK_PRED_MASK (0x7 << 3) +#define MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET (0) +#define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK (0x7) + +/* Define the bits in register CS1CDR and CS2CDR */ +#define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PRED_OFFSET (22) +#define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PRED_MASK (0x7 << 22) +#define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PODF_OFFSET (16) +#define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PODF_MASK (0x3F << 16) +#define MXC_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET (6) +#define MXC_CCM_CS1CDR_SSI1_CLK_PRED_MASK (0x7 << 6) +#define MXC_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET (0) +#define MXC_CCM_CS1CDR_SSI1_CLK_PODF_MASK (0x3F) + +#define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PRED_OFFSET (22) +#define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PRED_MASK (0x7 << 22) +#define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PODF_OFFSET (16) +#define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PODF_MASK (0x3F << 16) +#define MXC_CCM_CS2CDR_SSI2_CLK_PRED_OFFSET (6) +#define MXC_CCM_CS2CDR_SSI2_CLK_PRED_MASK (0x7 << 6) +#define MXC_CCM_CS2CDR_SSI2_CLK_PODF_OFFSET (0) +#define MXC_CCM_CS2CDR_SSI2_CLK_PODF_MASK (0x3F) + +/* Define the bits in register CDCDR */ +#define MXC_CCM_CDCDR_TVE_CLK_PRED_OFFSET (28) +#define MXC_CCM_CDCDR_TVE_CLK_PRED_MASK (0x7 << 28) +#define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_OFFSET (25) +#define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_MASK (0x7 << 25) +#define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_OFFSET (19) +#define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_MASK (0x3F << 19) +#define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_OFFSET (16) +#define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_MASK (0x7 << 16) +#define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_OFFSET (9) +#define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_MASK (0x3F << 9) +#define MXC_CCM_CDCDR_DI_CLK_PRED_OFFSET (6) +#define MXC_CCM_CDCDR_DI_CLK_PRED_MASK (0x7 << 6) +#define MXC_CCM_CDCDR_USB_PHY_PRED_OFFSET (3) +#define MXC_CCM_CDCDR_USB_PHY_PRED_MASK (0x7 << 3) +#define MXC_CCM_CDCDR_USB_PHY_PODF_OFFSET (0) +#define MXC_CCM_CDCDR_USB_PHY_PODF_MASK (0x7) + +/* Define the bits in register CHSCCDR */ +#define MXC_CCM_CHSCCDR_ESC_CLK_PRED_OFFSET (12) +#define MXC_CCM_CHSCCDR_ESC_CLK_PRED_MASK (0x7 << 12) +#define MXC_CCM_CHSCCDR_ESC_CLK_PODF_OFFSET (6) +#define MXC_CCM_CHSCCDR_ESC_CLK_PODF_MASK (0x3F << 6) +#define MXC_CCM_CHSCCDR_HSC2_CLK_PODF_OFFSET (3) +#define MXC_CCM_CHSCCDR_HSC2_CLK_PODF_MASK (0x7 << 3) +#define MXC_CCM_CHSCCDR_HSC1_CLK_PODF_OFFSET (0) +#define MXC_CCM_CHSCCDR_HSC1_CLK_PODF_MASK (0x7) + +/* Define the bits in register CSCDR2 */ +#define MXC_CCM_CSCDR2_CSPI_CLK_PRED_OFFSET (25) +#define MXC_CCM_CSCDR2_CSPI_CLK_PRED_MASK (0x7 << 25) +#define MXC_CCM_CSCDR2_CSPI_CLK_PODF_OFFSET (19) +#define MXC_CCM_CSCDR2_CSPI_CLK_PODF_MASK (0x3F << 19) +#define MXC_CCM_CSCDR2_SIM_CLK_PRED_OFFSET (16) +#define MXC_CCM_CSCDR2_SIM_CLK_PRED_MASK (0x7 << 16) +#define MXC_CCM_CSCDR2_SIM_CLK_PODF_OFFSET (9) +#define MXC_CCM_CSCDR2_SIM_CLK_PODF_MASK (0x3F << 9) +#define MXC_CCM_CSCDR2_SLIMBUS_CLK_PRED_OFFSET (6) +#define MXC_CCM_CSCDR2_SLIMBUS_PRED_MASK (0x7 << 6) +#define MXC_CCM_CSCDR2_SLIMBUS_PODF_OFFSET (0) +#define MXC_CCM_CSCDR2_SLIMBUS_PODF_MASK (0x3F) + +/* Define the bits in register CSCDR3 */ +#define MXC_CCM_CSCDR3_HSI2C_CLK_PRED_OFFSET (16) +#define MXC_CCM_CSCDR3_HSI2C_CLK_PRED_MASK (0x7 << 16) +#define MXC_CCM_CSCDR3_HSI2C_CLK_PODF_OFFSET (9) +#define MXC_CCM_CSCDR3_HSI2C_CLK_PODF_MASK (0x3F << 9) +#define MXC_CCM_CSCDR3_FIRI_CLK_PRED_OFFSET (6) +#define MXC_CCM_CSCDR3_FIRI_CLK_PRED_MASK (0x7 << 6) +#define MXC_CCM_CSCDR3_FIRI_CLK_PODF_OFFSET (0) +#define MXC_CCM_CSCDR3_FIRI_CLK_PODF_MASK (0x3F) + +/* Define the bits in register CSCDR4 */ +#define MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PRED_OFFSET (16) +#define MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PRED_MASK (0x7 << 16) +#define MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PODF_OFFSET (9) +#define MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PODF_MASK (0x3F << 9) +#define MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PRED_OFFSET (6) +#define MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PRED_MASK (0x7 << 6) +#define MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PODF_OFFSET (0) +#define MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PODF_MASK (0x3F) + +/* Define the bits in register CDHIPR */ +#define MXC_CCM_CDHIPR_ARM_PODF_BUSY (1 << 16) +#define MXC_CCM_CDHIPR_EMI_CLK_SEL_BUSY (1 << 6) +#define MXC_CCM_CDHIPR_PERIPH_CLK_SEL_BUSY (1 << 5) +#define MXC_CCM_CDHIPR_NFC_IPG_INT_MEM_PODF_BUSY (1 << 4) +#define MXC_CCM_CDHIPR_AHB_PODF_BUSY (1 << 3) +#define MXC_CCM_CDHIPR_EMI_PODF_BUSY (1 << 2) +#define MXC_CCM_CDHIPR_AXI_B_PODF_BUSY (1 << 1) +#define MXC_CCM_CDHIPR_AXI_A_PODF_BUSY (1 << 0) + +/* Define the bits in register CDCR */ +#define MXC_CCM_CDCR_ARM_FREQ_SHIFT_DIVIDER (0x1 << 2) +#define MXC_CCM_CDCR_PERIPH_CLK_DVFS_PODF_OFFSET (0) +#define MXC_CCM_CDCR_PERIPH_CLK_DVFS_PODF_MASK (0x3) + +/* Define the bits in register CLPCR */ +#define MXC_CCM_CLPCR_BYPASS_HSC_LPM_HS (0x1 << 23) +#define MXC_CCM_CLPCR_BYPASS_SCC_LPM_HS (0x1 << 22) +#define MXC_CCM_CLPCR_BYPASS_MAX_LPM_HS (0x1 << 21) +#define MXC_CCM_CLPCR_BYPASS_SDMA_LPM_HS (0x1 << 20) +#define MXC_CCM_CLPCR_BYPASS_EMI_LPM_HS (0x1 << 19) +#define MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS (0x1 << 18) +#define MXC_CCM_CLPCR_BYPASS_RTIC_LPM_HS (0x1 << 17) +#define MXC_CCM_CLPCR_BYPASS_RNGC_LPM_HS (0x1 << 16) +#define MXC_CCM_CLPCR_COSC_PWRDOWN (0x1 << 11) +#define MXC_CCM_CLPCR_STBY_COUNT_OFFSET (9) +#define MXC_CCM_CLPCR_STBY_COUNT_MASK (0x3 << 9) +#define MXC_CCM_CLPCR_VSTBY (0x1 << 8) +#define MXC_CCM_CLPCR_DIS_REF_OSC (0x1 << 7) +#define MXC_CCM_CLPCR_SBYOS (0x1 << 6) +#define MXC_CCM_CLPCR_ARM_CLK_DIS_ON_LPM (0x1 << 5) +#define MXC_CCM_CLPCR_LPSR_CLK_SEL_OFFSET (3) +#define MXC_CCM_CLPCR_LPSR_CLK_SEL_MASK (0x3 << 3) +#define MXC_CCM_CLPCR_LPM_OFFSET (0) +#define MXC_CCM_CLPCR_LPM_MASK (0x3) + +/* Define the bits in register CISR */ +#define MXC_CCM_CISR_ARM_PODF_LOADED (0x1 << 25) +#define MXC_CCM_CISR_NFC_IPG_INT_MEM_PODF_LOADED (0x1 << 21) +#define MXC_CCM_CISR_AHB_PODF_LOADED (0x1 << 20) +#define MXC_CCM_CISR_EMI_PODF_LOADED (0x1 << 19) +#define MXC_CCM_CISR_AXI_B_PODF_LOADED (0x1 << 18) +#define MXC_CCM_CISR_AXI_A_PODF_LOADED (0x1 << 17) +#define MXC_CCM_CISR_DIVIDER_LOADED (0x1 << 16) +#define MXC_CCM_CISR_COSC_READY (0x1 << 6) +#define MXC_CCM_CISR_CKIH2_READY (0x1 << 5) +#define MXC_CCM_CISR_CKIH_READY (0x1 << 4) +#define MXC_CCM_CISR_FPM_READY (0x1 << 3) +#define MXC_CCM_CISR_LRF_PLL3 (0x1 << 2) +#define MXC_CCM_CISR_LRF_PLL2 (0x1 << 1) +#define MXC_CCM_CISR_LRF_PLL1 (0x1) + +/* Define the bits in register CIMR */ +#define MXC_CCM_CIMR_MASK_ARM_PODF_LOADED (0x1 << 25) +#define MXC_CCM_CIMR_MASK_NFC_IPG_INT_MEM_PODF_LOADED (0x1 << 21) +#define MXC_CCM_CIMR_MASK_EMI_PODF_LOADED (0x1 << 20) +#define MXC_CCM_CIMR_MASK_AXI_C_PODF_LOADED (0x1 << 19) +#define MXC_CCM_CIMR_MASK_AXI_B_PODF_LOADED (0x1 << 18) +#define MXC_CCM_CIMR_MASK_AXI_A_PODF_LOADED (0x1 << 17) +#define MXC_CCM_CIMR_MASK_DIVIDER_LOADED (0x1 << 16) +#define MXC_CCM_CIMR_MASK_COSC_READY (0x1 << 5) +#define MXC_CCM_CIMR_MASK_CKIH_READY (0x1 << 4) +#define MXC_CCM_CIMR_MASK_FPM_READY (0x1 << 3) +#define MXC_CCM_CIMR_MASK_LRF_PLL3 (0x1 << 2) +#define MXC_CCM_CIMR_MASK_LRF_PLL2 (0x1 << 1) +#define MXC_CCM_CIMR_MASK_LRF_PLL1 (0x1) + +/* Define the bits in register CCOSR */ +#define MXC_CCM_CCOSR_CKO2_EN_OFFSET (0x1 << 24) +#define MXC_CCM_CCOSR_CKO2_DIV_OFFSET (21) +#define MXC_CCM_CCOSR_CKO2_DIV_MASK (0x7 << 21) +#define MXC_CCM_CCOSR_CKO2_SEL_OFFSET (16) +#define MXC_CCM_CCOSR_CKO2_SEL_MASK (0x1F << 16) +#define MXC_CCM_CCOSR_CKOL_EN (0x1 << 7) +#define MXC_CCM_CCOSR_CKOL_DIV_OFFSET (4) +#define MXC_CCM_CCOSR_CKOL_DIV_MASK (0x7 << 4) +#define MXC_CCM_CCOSR_CKOL_SEL_OFFSET (0) +#define MXC_CCM_CCOSR_CKOL_SEL_MASK (0xF) + +/* Define the bits in registers CGPR */ +#define MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE (0x1 << 4) +#define MXC_CCM_CGPR_FPM_SEL (0x1 << 3) +#define MXC_CCM_CGPR_VL_L2BIST_CLKDIV_OFFSET (0) +#define MXC_CCM_CGPR_VL_L2BIST_CLKDIV_MASK (0x7) + +/* Define the bits in registers CCGRx */ +#define MXC_CCM_CCGR_CG_MASK 0x3 + +#define MXC_CCM_CCGR0_CG15_OFFSET 30 +#define MXC_CCM_CCGR0_CG15_MASK (0x3 << 30) +#define MXC_CCM_CCGR0_CG14_OFFSET 28 +#define MXC_CCM_CCGR0_CG14_MASK (0x3 << 28) +#define MXC_CCM_CCGR0_CG13_OFFSET 26 +#define MXC_CCM_CCGR0_CG13_MASK (0x3 << 26) +#define MXC_CCM_CCGR0_CG12_OFFSET 24 +#define MXC_CCM_CCGR0_CG12_MASK (0x3 << 24) +#define MXC_CCM_CCGR0_CG11_OFFSET 22 +#define MXC_CCM_CCGR0_CG11_MASK (0x3 << 22) +#define MXC_CCM_CCGR0_CG10_OFFSET 20 +#define MXC_CCM_CCGR0_CG10_MASK (0x3 << 20) +#define MXC_CCM_CCGR0_CG9_OFFSET 18 +#define MXC_CCM_CCGR0_CG9_MASK (0x3 << 18) +#define MXC_CCM_CCGR0_CG8_OFFSET 16 +#define MXC_CCM_CCGR0_CG8_MASK (0x3 << 16) +#define MXC_CCM_CCGR0_CG7_OFFSET 14 +#define MXC_CCM_CCGR0_CG6_OFFSET 12 +#define MXC_CCM_CCGR0_CG5_OFFSET 10 +#define MXC_CCM_CCGR0_CG5_MASK (0x3 << 10) +#define MXC_CCM_CCGR0_CG4_OFFSET 8 +#define MXC_CCM_CCGR0_CG4_MASK (0x3 << 8) +#define MXC_CCM_CCGR0_CG3_OFFSET 6 +#define MXC_CCM_CCGR0_CG3_MASK (0x3 << 6) +#define MXC_CCM_CCGR0_CG2_OFFSET 4 +#define MXC_CCM_CCGR0_CG2_MASK (0x3 << 4) +#define MXC_CCM_CCGR0_CG1_OFFSET 2 +#define MXC_CCM_CCGR0_CG1_MASK (0x3 << 2) +#define MXC_CCM_CCGR0_CG0_OFFSET 0 +#define MXC_CCM_CCGR0_CG0_MASK 0x3 + +#define MXC_CCM_CCGR1_CG15_OFFSET 30 +#define MXC_CCM_CCGR1_CG14_OFFSET 28 +#define MXC_CCM_CCGR1_CG13_OFFSET 26 +#define MXC_CCM_CCGR1_CG12_OFFSET 24 +#define MXC_CCM_CCGR1_CG11_OFFSET 22 +#define MXC_CCM_CCGR1_CG10_OFFSET 20 +#define MXC_CCM_CCGR1_CG9_OFFSET 18 +#define MXC_CCM_CCGR1_CG8_OFFSET 16 +#define MXC_CCM_CCGR1_CG7_OFFSET 14 +#define MXC_CCM_CCGR1_CG6_OFFSET 12 +#define MXC_CCM_CCGR1_CG5_OFFSET 10 +#define MXC_CCM_CCGR1_CG4_OFFSET 8 +#define MXC_CCM_CCGR1_CG3_OFFSET 6 +#define MXC_CCM_CCGR1_CG2_OFFSET 4 +#define MXC_CCM_CCGR1_CG1_OFFSET 2 +#define MXC_CCM_CCGR1_CG0_OFFSET 0 + +#define MXC_CCM_CCGR2_CG15_OFFSET 30 +#define MXC_CCM_CCGR2_CG14_OFFSET 28 +#define MXC_CCM_CCGR2_CG13_OFFSET 26 +#define MXC_CCM_CCGR2_CG12_OFFSET 24 +#define MXC_CCM_CCGR2_CG11_OFFSET 22 +#define MXC_CCM_CCGR2_CG10_OFFSET 20 +#define MXC_CCM_CCGR2_CG9_OFFSET 18 +#define MXC_CCM_CCGR2_CG8_OFFSET 16 +#define MXC_CCM_CCGR2_CG7_OFFSET 14 +#define MXC_CCM_CCGR2_CG6_OFFSET 12 +#define MXC_CCM_CCGR2_CG5_OFFSET 10 +#define MXC_CCM_CCGR2_CG4_OFFSET 8 +#define MXC_CCM_CCGR2_CG3_OFFSET 6 +#define MXC_CCM_CCGR2_CG2_OFFSET 4 +#define MXC_CCM_CCGR2_CG1_OFFSET 2 +#define MXC_CCM_CCGR2_CG0_OFFSET 0 + +#define MXC_CCM_CCGR3_CG15_OFFSET 30 +#define MXC_CCM_CCGR3_CG14_OFFSET 28 +#define MXC_CCM_CCGR3_CG13_OFFSET 26 +#define MXC_CCM_CCGR3_CG12_OFFSET 24 +#define MXC_CCM_CCGR3_CG11_OFFSET 22 +#define MXC_CCM_CCGR3_CG10_OFFSET 20 +#define MXC_CCM_CCGR3_CG9_OFFSET 18 +#define MXC_CCM_CCGR3_CG8_OFFSET 16 +#define MXC_CCM_CCGR3_CG7_OFFSET 14 +#define MXC_CCM_CCGR3_CG6_OFFSET 12 +#define MXC_CCM_CCGR3_CG5_OFFSET 10 +#define MXC_CCM_CCGR3_CG4_OFFSET 8 +#define MXC_CCM_CCGR3_CG3_OFFSET 6 +#define MXC_CCM_CCGR3_CG2_OFFSET 4 +#define MXC_CCM_CCGR3_CG1_OFFSET 2 +#define MXC_CCM_CCGR3_CG0_OFFSET 0 + +#define MXC_CCM_CCGR4_CG15_OFFSET 30 +#define MXC_CCM_CCGR4_CG14_OFFSET 28 +#define MXC_CCM_CCGR4_CG13_OFFSET 26 +#define MXC_CCM_CCGR4_CG12_OFFSET 24 +#define MXC_CCM_CCGR4_CG11_OFFSET 22 +#define MXC_CCM_CCGR4_CG10_OFFSET 20 +#define MXC_CCM_CCGR4_CG9_OFFSET 18 +#define MXC_CCM_CCGR4_CG8_OFFSET 16 +#define MXC_CCM_CCGR4_CG7_OFFSET 14 +#define MXC_CCM_CCGR4_CG6_OFFSET 12 +#define MXC_CCM_CCGR4_CG5_OFFSET 10 +#define MXC_CCM_CCGR4_CG4_OFFSET 8 +#define MXC_CCM_CCGR4_CG3_OFFSET 6 +#define MXC_CCM_CCGR4_CG2_OFFSET 4 +#define MXC_CCM_CCGR4_CG1_OFFSET 2 +#define MXC_CCM_CCGR4_CG0_OFFSET 0 + +#define MXC_CCM_CCGR5_CG15_OFFSET 30 +#define MXC_CCM_CCGR5_CG14_OFFSET 28 +#define MXC_CCM_CCGR5_CG14_MASK (0x3 << 28) +#define MXC_CCM_CCGR5_CG13_OFFSET 26 +#define MXC_CCM_CCGR5_CG13_MASK (0x3 << 26) +#define MXC_CCM_CCGR5_CG12_OFFSET 24 +#define MXC_CCM_CCGR5_CG12_MASK (0x3 << 24) +#define MXC_CCM_CCGR5_CG11_OFFSET 22 +#define MXC_CCM_CCGR5_CG11_MASK (0x3 << 22) +#define MXC_CCM_CCGR5_CG10_OFFSET 20 +#define MXC_CCM_CCGR5_CG10_MASK (0x3 << 20) +#define MXC_CCM_CCGR5_CG9_OFFSET 18 +#define MXC_CCM_CCGR5_CG9_MASK (0x3 << 18) +#define MXC_CCM_CCGR5_CG8_OFFSET 16 +#define MXC_CCM_CCGR5_CG8_MASK (0x3 << 16) +#define MXC_CCM_CCGR5_CG7_OFFSET 14 +#define MXC_CCM_CCGR5_CG7_MASK (0x3 << 14) +#define MXC_CCM_CCGR5_CG6_OFFSET 12 +#define MXC_CCM_CCGR5_CG5_OFFSET 10 +#define MXC_CCM_CCGR5_CG4_OFFSET 8 +#define MXC_CCM_CCGR5_CG3_OFFSET 6 +#define MXC_CCM_CCGR5_CG2_OFFSET 4 +#define MXC_CCM_CCGR5_CG2_MASK (0x3 << 4) +#define MXC_CCM_CCGR5_CG1_OFFSET 2 +#define MXC_CCM_CCGR5_CG0_OFFSET 0 + +#define MXC_CCM_CCGR6_CG4_OFFSET 8 +#define MXC_CCM_CCGR6_CG4_MASK (0x3 << 8) +#define MXC_CCM_CCGR6_CG3_OFFSET 6 +#define MXC_CCM_CCGR6_CG2_OFFSET 4 +#define MXC_CCM_CCGR6_CG1_OFFSET 2 +#define MXC_CCM_CCGR6_CG0_OFFSET 0 + +#define MXC_CORTEXA8_BASE ARM_BASE_ADDR +#define MXC_GPC_BASE GPC_BASE_ADDR +#define MXC_DPTC_LP_BASE (GPC_BASE_ADDR + 0x80) +#define MXC_DPTC_GP_BASE (GPC_BASE_ADDR + 0x100) +#define MXC_DVFS_CORE_BASE (GPC_BASE_ADDR + 0x180) +#define MXC_DPTC_PER_BASE (GPC_BASE_ADDR + 0x1C0) +#define MXC_PGC_IPU_BASE (GPC_BASE_ADDR + 0x220) +#define MXC_PGC_VPU_BASE (GPC_BASE_ADDR + 0x240) +#define MXC_PGC_GPU_BASE (GPC_BASE_ADDR + 0x260) +#define MXC_SRPG_NEON_BASE (GPC_BASE_ADDR + 0x280) +#define MXC_SRPG_ARM_BASE (GPC_BASE_ADDR + 0x2A0) +#define MXC_SRPG_EMPGC0_BASE (GPC_BASE_ADDR + 0x2C0) +#define MXC_SRPG_EMPGC1_BASE (GPC_BASE_ADDR + 0x2D0) +#define MXC_SRPG_MEGAMIX_BASE (GPC_BASE_ADDR + 0x2E0) +#define MXC_SRPG_EMI_BASE (GPC_BASE_ADDR + 0x300) + +/* CORTEXA8 platform */ +#define MXC_CORTEXA8_PLAT_PVID (MXC_CORTEXA8_BASE + 0x0) +#define MXC_CORTEXA8_PLAT_GPC (MXC_CORTEXA8_BASE + 0x4) +#define MXC_CORTEXA8_PLAT_PIC (MXC_CORTEXA8_BASE + 0x8) +#define MXC_CORTEXA8_PLAT_LPC (MXC_CORTEXA8_BASE + 0xC) +#define MXC_CORTEXA8_PLAT_NEON_LPC (MXC_CORTEXA8_BASE + 0x10) +#define MXC_CORTEXA8_PLAT_ICGC (MXC_CORTEXA8_BASE + 0x14) +#define MXC_CORTEXA8_PLAT_AMC (MXC_CORTEXA8_BASE + 0x18) +#define MXC_CORTEXA8_PLAT_NMC (MXC_CORTEXA8_BASE + 0x20) +#define MXC_CORTEXA8_PLAT_NMS (MXC_CORTEXA8_BASE + 0x24) + +/* DVFS CORE */ +#define MXC_DVFSTHRS (MXC_DVFS_CORE_BASE + 0x00) +#define MXC_DVFSCOUN (MXC_DVFS_CORE_BASE + 0x04) +#define MXC_DVFSSIG1 (MXC_DVFS_CORE_BASE + 0x08) +#define MXC_DVFSSIG0 (MXC_DVFS_CORE_BASE + 0x0C) +#define MXC_DVFSGPC0 (MXC_DVFS_CORE_BASE + 0x10) +#define MXC_DVFSGPC1 (MXC_DVFS_CORE_BASE + 0x14) +#define MXC_DVFSGPBT (MXC_DVFS_CORE_BASE + 0x18) +#define MXC_DVFSEMAC (MXC_DVFS_CORE_BASE + 0x1C) +#define MXC_DVFSCNTR (MXC_DVFS_CORE_BASE + 0x20) +#define MXC_DVFSLTR0_0 (MXC_DVFS_CORE_BASE + 0x24) +#define MXC_DVFSLTR0_1 (MXC_DVFS_CORE_BASE + 0x28) +#define MXC_DVFSLTR1_0 (MXC_DVFS_CORE_BASE + 0x2C) +#define MXC_DVFSLTR1_1 (MXC_DVFS_CORE_BASE + 0x30) +#define MXC_DVFSPT0 (MXC_DVFS_CORE_BASE + 0x34) +#define MXC_DVFSPT1 (MXC_DVFS_CORE_BASE + 0x38) +#define MXC_DVFSPT2 (MXC_DVFS_CORE_BASE + 0x3C) +#define MXC_DVFSPT3 (MXC_DVFS_CORE_BASE + 0x40) + +/* GPC */ +#define MXC_GPC_CNTR (MXC_GPC_BASE + 0x0) +#define MXC_GPC_PGR (MXC_GPC_BASE + 0x4) +#define MXC_GPC_VCR (MXC_GPC_BASE + 0x8) +#define MXC_GPC_ALL_PU (MXC_GPC_BASE + 0xC) +#define MXC_GPC_NEON (MXC_GPC_BASE + 0x10) +#define MXC_GPC_PGR_ARMPG_OFFSET 8 +#define MXC_GPC_PGR_ARMPG_MASK (3 << 8) + +/* PGC */ +#define MXC_PGC_IPU_PGCR (MXC_PGC_IPU_BASE + 0x0) +#define MXC_PGC_IPU_PGSR (MXC_PGC_IPU_BASE + 0xC) +#define MXC_PGC_VPU_PGCR (MXC_PGC_VPU_BASE + 0x0) +#define MXC_PGC_VPU_PGSR (MXC_PGC_VPU_BASE + 0xC) +#define MXC_PGC_GPU_PGCR (MXC_PGC_GPU_BASE + 0x0) +#define MXC_PGC_GPU_PGSR (MXC_PGC_GPU_BASE + 0xC) + +#define MXC_PGCR_PCR 1 +#define MXC_SRPGCR_PCR 1 +#define MXC_EMPGCR_PCR 1 +#define MXC_PGSR_PSR 1 + + +#define MXC_CORTEXA8_PLAT_LPC_DSM (1 << 0) +#define MXC_CORTEXA8_PLAT_LPC_DBG_DSM (1 << 1) + +/* SRPG */ +#define MXC_SRPG_NEON_SRPGCR (MXC_SRPG_NEON_BASE + 0x0) +#define MXC_SRPG_NEON_PUPSCR (MXC_SRPG_NEON_BASE + 0x4) +#define MXC_SRPG_NEON_PDNSCR (MXC_SRPG_NEON_BASE + 0x8) + +#define MXC_SRPG_ARM_SRPGCR (MXC_SRPG_ARM_BASE + 0x0) +#define MXC_SRPG_ARM_PUPSCR (MXC_SRPG_ARM_BASE + 0x4) +#define MXC_SRPG_ARM_PDNSCR (MXC_SRPG_ARM_BASE + 0x8) + +#define MXC_SRPG_EMPGC0_SRPGCR (MXC_SRPG_EMPGC0_BASE + 0x0) +#define MXC_SRPG_EMPGC0_PUPSCR (MXC_SRPG_EMPGC0_BASE + 0x4) +#define MXC_SRPG_EMPGC0_PDNSCR (MXC_SRPG_EMPGC0_BASE + 0x8) + +#define MXC_SRPG_EMPGC1_SRPGCR (MXC_SRPG_EMPGC1_BASE + 0x0) +#define MXC_SRPG_EMPGC1_PUPSCR (MXC_SRPG_EMPGC1_BASE + 0x4) +#define MXC_SRPG_EMPGC1_PDNSCR (MXC_SRPG_EMPGC1_BASE + 0x8) + +#define MXC_SRPG_MEGAMIX_SRPGCR (MXC_SRPG_MEGAMIX_BASE + 0x0) +#define MXC_SRPG_MEGAMIX_PUPSCR (MXC_SRPG_MEGAMIX_BASE + 0x4) +#define MXC_SRPG_MEGAMIX_PDNSCR (MXC_SRPG_MEGAMIX_BASE + 0x8) + +#define MXC_SRPGC_EMI_SRPGCR (MXC_SRPGC_EMI_BASE + 0x0) +#define MXC_SRPGC_EMI_PUPSCR (MXC_SRPGC_EMI_BASE + 0x4) +#define MXC_SRPGC_EMI_PDNSCR (MXC_SRPGC_EMI_BASE + 0x8) + +#endif /* __ARCH_ARM_MACH_MX51_CRM_REGS_H__ */ diff --git a/cpu/arm_cortexa8/mx51/generic.c b/cpu/arm_cortexa8/mx51/generic.c new file mode 100644 index 0000000000..4706a0067b --- /dev/null +++ b/cpu/arm_cortexa8/mx51/generic.c @@ -0,0 +1,279 @@ +/* + * (C) Copyright 2007 + * Sascha Hauer, Pengutronix + * + * (C) Copyright 2009-2010 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#ifdef CONFIG_ARCH_CPU_INIT +#include +#endif +#include "crm_regs.h" + +enum pll_clocks { +PLL1_CLK = MXC_DPLL1_BASE, +PLL2_CLK = MXC_DPLL2_BASE, +PLL3_CLK = MXC_DPLL3_BASE, +}; + +enum pll_sw_clocks { +PLL1_SW_CLK, +PLL2_SW_CLK, +PLL3_SW_CLK, +}; + +static u32 __decode_pll(enum pll_clocks pll, u32 infreq) +{ + u32 mfi, mfn, mfd, pd; + + mfn = __REG(pll + MXC_PLL_DP_MFN); + mfd = __REG(pll + MXC_PLL_DP_MFD) + 1; + mfi = __REG(pll + MXC_PLL_DP_OP); + pd = (mfi & 0xF) + 1; + mfi = (mfi >> 4) & 0xF; + mfi = (mfi >= 5) ? mfi : 5; + + return ((4 * (infreq / 1000) * (mfi * mfd + mfn)) / (mfd * pd)) * 1000; +} + +static u32 __get_mcu_main_clk(void) +{ + u32 reg, freq; + reg = (__REG(MXC_CCM_CACRR) & MXC_CCM_CACRR_ARM_PODF_MASK) >> + MXC_CCM_CACRR_ARM_PODF_OFFSET; + freq = __decode_pll(PLL1_CLK, CONFIG_MX51_HCLK_FREQ); + return freq / (reg + 1); +} + +static u32 __get_periph_clk(void) +{ + u32 reg; + reg = __REG(MXC_CCM_CBCDR); + if (reg & MXC_CCM_CBCDR_PERIPH_CLK_SEL) { + reg = __REG(MXC_CCM_CBCMR); + switch ((reg & MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK) >> + MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET) { + case 0: + return __decode_pll(PLL1_CLK, CONFIG_MX51_HCLK_FREQ); + case 1: + return __decode_pll(PLL3_CLK, CONFIG_MX51_HCLK_FREQ); + default: + return 0; + } + } + return __decode_pll(PLL2_CLK, CONFIG_MX51_HCLK_FREQ); +} + +static u32 __get_ipg_clk(void) +{ + u32 ahb_podf, ipg_podf; + + ahb_podf = __REG(MXC_CCM_CBCDR); + ipg_podf = (ahb_podf & MXC_CCM_CBCDR_IPG_PODF_MASK) >> + MXC_CCM_CBCDR_IPG_PODF_OFFSET; + ahb_podf = (ahb_podf & MXC_CCM_CBCDR_AHB_PODF_MASK) >> + MXC_CCM_CBCDR_AHB_PODF_OFFSET; + return __get_periph_clk() / ((ahb_podf + 1) * (ipg_podf + 1)); +} + +static u32 __get_ipg_per_clk(void) +{ + u32 pred1, pred2, podf; + if (__REG(MXC_CCM_CBCMR) & MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL) + return __get_ipg_clk(); + /* Fixme: not handle what about lpm*/ + podf = __REG(MXC_CCM_CBCDR); + pred1 = (podf & MXC_CCM_CBCDR_PERCLK_PRED1_MASK) >> + MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET; + pred2 = (podf & MXC_CCM_CBCDR_PERCLK_PRED2_MASK) >> + MXC_CCM_CBCDR_PERCLK_PRED2_OFFSET; + podf = (podf & MXC_CCM_CBCDR_PERCLK_PODF_MASK) >> + MXC_CCM_CBCDR_PERCLK_PODF_OFFSET; + + return __get_periph_clk() / ((pred1 + 1) * (pred2 + 1) * (podf + 1)); +} + +static u32 __get_uart_clk(void) +{ + unsigned int freq, reg, pred, podf; + reg = __REG(MXC_CCM_CSCMR1); + switch ((reg & MXC_CCM_CSCMR1_UART_CLK_SEL_MASK) >> + MXC_CCM_CSCMR1_UART_CLK_SEL_OFFSET) { + case 0x0: + freq = __decode_pll(PLL1_CLK, CONFIG_MX51_HCLK_FREQ); + break; + case 0x1: + freq = __decode_pll(PLL2_CLK, CONFIG_MX51_HCLK_FREQ); + break; + case 0x2: + freq = __decode_pll(PLL3_CLK, CONFIG_MX51_HCLK_FREQ); + break; + default: + return 66500000; + } + + reg = __REG(MXC_CCM_CSCDR1); + + pred = (reg & MXC_CCM_CSCDR1_UART_CLK_PRED_MASK) >> + MXC_CCM_CSCDR1_UART_CLK_PRED_OFFSET; + + podf = (reg & MXC_CCM_CSCDR1_UART_CLK_PODF_MASK) >> + MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET; + freq /= (pred + 1) * (podf + 1); + + return freq; +} + +/*! ++ * This function returns the low power audio clock. ++ */ +u32 get_lp_apm(void) +{ + u32 ret_val = 0; + u32 ccsr = __REG(MXC_CCM_CCSR); + + if (((ccsr >> 9) & 1) == 0) + ret_val = CONFIG_MX51_HCLK_FREQ; + else + ret_val = ((32768 * 1024)); + + return ret_val; +} + +static u32 __get_cspi_clk(void) +{ + u32 ret_val = 0, pdf, pre_pdf, clk_sel; + u32 cscmr1 = __REG(MXC_CCM_CSCMR1); + u32 cscdr2 = __REG(MXC_CCM_CSCDR2); + + pre_pdf = (cscdr2 & MXC_CCM_CSCDR2_CSPI_CLK_PRED_MASK) \ + >> MXC_CCM_CSCDR2_CSPI_CLK_PRED_OFFSET; + pdf = (cscdr2 & MXC_CCM_CSCDR2_CSPI_CLK_PODF_MASK) \ + >> MXC_CCM_CSCDR2_CSPI_CLK_PODF_OFFSET; + clk_sel = (cscmr1 & MXC_CCM_CSCMR1_CSPI_CLK_SEL_MASK) \ + >> MXC_CCM_CSCMR1_CSPI_CLK_SEL_OFFSET; + + switch (clk_sel) { + case 0: + ret_val = __decode_pll(PLL1_CLK, CONFIG_MX51_HCLK_FREQ) / ((pre_pdf + 1) * (pdf + 1)); + break; + case 1: + ret_val = __decode_pll(PLL2_CLK, CONFIG_MX51_HCLK_FREQ) / ((pre_pdf + 1) * (pdf + 1)); + break; + case 2: + ret_val = __decode_pll(PLL3_CLK, CONFIG_MX51_HCLK_FREQ) / ((pre_pdf + 1) * (pdf + 1)); + break; + default: + ret_val = get_lp_apm() / ((pre_pdf + 1) * (pdf + 1)); + break; + } + + return ret_val; +} + +unsigned int mxc_get_clock(enum mxc_clock clk) +{ + switch (clk) { + case MXC_ARM_CLK: + return __get_mcu_main_clk(); + case MXC_AHB_CLK: + break; + case MXC_IPG_CLK: + return __get_ipg_clk(); + case MXC_IPG_PERCLK: + return __get_ipg_per_clk(); + case MXC_UART_CLK: + return __get_uart_clk(); + case MXC_CSPI_CLK: + return __get_cspi_clk(); + case MXC_FEC_CLK: + return __decode_pll(PLL1_CLK, CONFIG_MX51_HCLK_FREQ); + case MXC_ESDHC_CLK: + return __decode_pll(PLL3_CLK, CONFIG_MX51_HCLK_FREQ); + default: + break; + } + return -1; +} + +void mxc_dump_clocks(void) +{ + u32 freq; + freq = __decode_pll(PLL1_CLK, CONFIG_MX51_HCLK_FREQ); + printf("mx51 pll1: %dMHz\n", freq / 1000000); + freq = __decode_pll(PLL2_CLK, CONFIG_MX51_HCLK_FREQ); + printf("mx51 pll2: %dMHz\n", freq / 1000000); + freq = __decode_pll(PLL3_CLK, CONFIG_MX51_HCLK_FREQ); + printf("mx51 pll3: %dMHz\n", freq / 1000000); + printf("ipg clock : %dHz\n", mxc_get_clock(MXC_IPG_CLK)); + printf("ipg per clock : %dHz\n", mxc_get_clock(MXC_IPG_PERCLK)); + printf("uart clock : %dHz\n", mxc_get_clock(MXC_UART_CLK)); + printf("cspi clock : %dHz\n", mxc_get_clock(MXC_CSPI_CLK)); +} + +#if defined(CONFIG_DISPLAY_CPUINFO) +int print_cpuinfo(void) +{ + printf("CPU: Freescale i.MX51 family %d.%dV at %d MHz\n", + (get_board_rev() & 0xFF) >> 4, + (get_board_rev() & 0xF), + __get_mcu_main_clk() / 1000000); + mxc_dump_clocks(); + return 0; +} +#endif + +/* + * Initializes on-chip ethernet controllers. + * to override, implement board_eth_init() + */ +#if defined(CONFIG_MXC_FEC) +extern int mxc_fec_initialize(bd_t *bis); +extern void mxc_fec_set_mac_from_env(char *mac_addr); +#endif + +int cpu_eth_init(bd_t *bis) +{ + int rc = -ENODEV; + +#if defined(CONFIG_MXC_FEC) + rc = mxc_fec_initialize(bis); +#endif + + return rc; +} + +#if defined(CONFIG_ARCH_CPU_INIT) +int arch_cpu_init(void) +{ + icache_enable(); + dcache_enable(); +#ifdef CONFIG_L2_OFF + l2_cache_disable(); +#else + l2_cache_enable(); +#endif + return 0; +} +#endif diff --git a/cpu/arm_cortexa8/mx51/interrupts.c b/cpu/arm_cortexa8/mx51/interrupts.c new file mode 100644 index 0000000000..5212a4248e --- /dev/null +++ b/cpu/arm_cortexa8/mx51/interrupts.c @@ -0,0 +1,47 @@ +/* + * (C) Copyright 2007 + * Sascha Hauer, Pengutronix + * + * (C) Copyright 2009 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +/* nothing really to do with interrupts, just starts up a counter. */ +int interrupt_init(void) +{ + return 0; +} + +void reset_cpu(ulong addr) +{ + /* workaround for ENGcm09397 - Fix SPI NOR reset issue*/ + /* de-select SS0 of instance: eCSPI1 */ + writel(0x3, IOMUXC_BASE_ADDR + 0x218); + writel(0x85, IOMUXC_BASE_ADDR + 0x608); + /* de-select SS1 of instance: ecspi1 */ + writel(0x3, IOMUXC_BASE_ADDR + 0x21C); + writel(0x85, IOMUXC_BASE_ADDR + 0x60C); + + __REG16(WDOG1_BASE_ADDR) = 4; +} diff --git a/cpu/arm_cortexa8/mx51/iomux.c b/cpu/arm_cortexa8/mx51/iomux.c new file mode 100644 index 0000000000..294708531e --- /dev/null +++ b/cpu/arm_cortexa8/mx51/iomux.c @@ -0,0 +1,199 @@ +/* + * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @defgroup GPIO_MX51 Board GPIO and Muxing Setup + * @ingroup MSL_MX51 + */ +/*! + * @file mach-mx51/iomux.c + * + * @brief I/O Muxing control functions + * + * @ingroup GPIO_MX51 + */ +#include +#include +#include +#include +#include + +/*! + * IOMUX register (base) addresses + */ +enum iomux_reg_addr { + IOMUXGPR0 = IOMUXC_BASE_ADDR, + IOMUXGPR1 = IOMUXC_BASE_ADDR + 0x004, + IOMUXSW_MUX_CTL = IOMUXC_BASE_ADDR, + IOMUXSW_MUX_END = IOMUXC_BASE_ADDR + MUX_I_END, + IOMUXSW_PAD_CTL = IOMUXC_BASE_ADDR + PAD_I_START, + IOMUXSW_INPUT_CTL = IOMUXC_BASE_ADDR, +}; + +#define MUX_PIN_NUM_MAX (((MUX_I_END - MUX_I_START) >> 2) + 1) + +static inline u32 _get_mux_reg(iomux_pin_name_t pin) +{ + u32 mux_reg = PIN_TO_IOMUX_MUX(pin); + + if (is_soc_rev(CHIP_REV_2_0) < 0) { + if ((pin == MX51_PIN_NANDF_RB5) || + (pin == MX51_PIN_NANDF_RB6) || + (pin == MX51_PIN_NANDF_RB7)) + ; /* Do nothing */ + else if (mux_reg >= 0x2FC) + mux_reg += 8; + else if (mux_reg >= 0x130) + mux_reg += 0xC; + } + mux_reg += IOMUXSW_MUX_CTL; + return mux_reg; +} + +static inline u32 _get_pad_reg(iomux_pin_name_t pin) +{ + u32 pad_reg = PIN_TO_IOMUX_PAD(pin); + + if (is_soc_rev(CHIP_REV_2_0) < 0) { + if ((pin == MX51_PIN_NANDF_RB5) || + (pin == MX51_PIN_NANDF_RB6) || + (pin == MX51_PIN_NANDF_RB7)) + ; /* Do nothing */ + else if (pad_reg == 0x4D0 - PAD_I_START) + pad_reg += 0x4C; + else if (pad_reg == 0x860 - PAD_I_START) + pad_reg += 0x9C; + else if (pad_reg >= 0x804 - PAD_I_START) + pad_reg += 0xB0; + else if (pad_reg >= 0x7FC - PAD_I_START) + pad_reg += 0xB4; + else if (pad_reg >= 0x4E4 - PAD_I_START) + pad_reg += 0xCC; + else + pad_reg += 8; + } + pad_reg += IOMUXSW_PAD_CTL; + return pad_reg; +} + +static inline u32 _get_mux_end() +{ + if (is_soc_rev(CHIP_REV_2_0) < 0) + return IOMUXC_BASE_ADDR + (0x3F8 - 4); + else + return IOMUXC_BASE_ADDR + (0x3F0 - 4); +} + +/*! + * This function is used to configure a pin through the IOMUX module. + * FIXED ME: for backward compatible. Will be static function! + * @param pin a pin number as defined in \b #iomux_pin_name_t + * @param cfg an output function as defined in \b #iomux_pin_cfg_t + * + * @return 0 if successful; Non-zero otherwise + */ +static int iomux_config_mux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg) +{ + u32 mux_reg = _get_mux_reg(pin); + + if ((mux_reg > _get_mux_end()) || (mux_reg < IOMUXSW_MUX_CTL)) + return -1; + if (cfg == IOMUX_CONFIG_GPIO) + writel(PIN_TO_ALT_GPIO(pin), mux_reg); + else + writel(cfg, mux_reg); + + return 0; +} + +/*! + * Request ownership for an IO pin. This function has to be the first one + * being called before that pin is used. The caller has to check the + * return value to make sure it returns 0. + * + * @param pin a name defined by \b iomux_pin_name_t + * @param cfg an input function as defined in \b #iomux_pin_cfg_t + * + * @return 0 if successful; Non-zero otherwise + */ +int mxc_request_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg) +{ + int ret = iomux_config_mux(pin, cfg); + return ret; +} + +/*! + * Release ownership for an IO pin + * + * @param pin a name defined by \b iomux_pin_name_t + * @param cfg an input function as defined in \b #iomux_pin_cfg_t + */ +void mxc_free_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg) +{ +} + +/*! + * This function configures the pad value for a IOMUX pin. + * + * @param pin a pin number as defined in \b #iomux_pin_name_t + * @param config the ORed value of elements defined in \b #iomux_pad_config_t + */ +void mxc_iomux_set_pad(iomux_pin_name_t pin, u32 config) +{ + u32 pad_reg = _get_pad_reg(pin); + writel(config, pad_reg); +} + +unsigned int mxc_iomux_get_pad(iomux_pin_name_t pin) +{ + u32 pad_reg = _get_pad_reg(pin); + return readl(pad_reg); +} +/*! + * This function configures input path. + * + * @param input index of input select register as defined in \b + * #iomux_input_select_t + * @param config the binary value of elements defined in \b + * #iomux_input_config_t + */ +void mxc_iomux_set_input(iomux_input_select_t input, u32 config) +{ + u32 reg = IOMUXSW_INPUT_CTL + (input << 2); + + if (is_soc_rev(CHIP_REV_2_0) < 0) { + if (input == MUX_IN_IPU_IPP_DI_0_IND_DISPB_SD_D_SELECT_INPUT) + input -= 4; + else if (input == + MUX_IN_IPU_IPP_DI_1_IND_DISPB_SD_D_SELECT_INPUT) + input -= 3; + else if (input >= MUX_IN_KPP_IPP_IND_COL_6_SELECT_INPUT) + input -= 2; + else if (input >= + MUX_IN_HSC_MIPI_MIX_PAR_SISG_TRIG_SELECT_INPUT) + input -= 5; + else if (input >= + MUX_IN_HSC_MIPI_MIX_IPP_IND_SENS1_DATA_EN_SELECT_INPUT) + input -= 3; + else if (input >= MUX_IN_ECSPI2_IPP_IND_SS_B_3_SELECT_INPUT) + input -= 2; + else if (input >= MUX_IN_CCM_PLL1_BYPASS_CLK_SELECT_INPUT) + input -= 1; + + reg += INPUT_CTL_START_TO1; + } else { + reg += INPUT_CTL_START; + } + + writel(config, reg); +} diff --git a/cpu/arm_cortexa8/mx51/mxc_nand_load.S b/cpu/arm_cortexa8/mx51/mxc_nand_load.S new file mode 100644 index 0000000000..ca1f07b374 --- /dev/null +++ b/cpu/arm_cortexa8/mx51/mxc_nand_load.S @@ -0,0 +1,167 @@ +/* + * (C) Copyright 2009 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +.macro do_wait_op_done +1: ldr r7, [r3, #0x2C] + ands r7, r7, #0x80000000 + beq 1b + mov r7, #0x0 + str r7, [r3, #0x2C] +.endm // do_wait_op_done + +.section ".text.load", "x" +.globl mxc_nand_load +/* + * R0: NFC BUF base address + * R1: NFC BUF data end address + * R2: RAM destination offset address + * R3: NFC IP control register base + * R4: NAND block address + * R5: RAM destination end address + * R6: NFC DATA register base + * R7 - r14: 8 working buffer registers + */ +mxc_nand_load: + ldr r0, =NFC_BASE_ADDR_AXI + add r1, r0, #NFC_BUF_SIZE + + /* For non-nand-boot, directly quit */ + cmp pc, r0 + movlo pc, lr + cmp pc, r1 + movhi pc, lr + + mov r4, #NFC_BUF_SIZE + /* Get NAND page size */ + ldr r3, =NFC_BASE_ADDR + ldr r2, [r3, #0x24] + and r2, r2, #0x3 + cmp r2, #1 + moveq r2, #0x800 + movlt r2, #0x200 + adrls r5, NFC_PAGE_MODE + strls r2, [r5] + /* Get actually pre-loading size*/ + subls r1, r1, #0x800 + subls r4, r4, #0x800 + + /* r1 ~ r3, r12, lr(r14) must not change in relocated operation */ + ldr r2, U_BOOT_NAND_START +1: ldmia r0!, {r5-r11, r13} + stmia r2!, {r5-r11, r13} + cmp r0, r1 + blo 1b + + ldr r0, CONST_0X0FFF + ldr r5, U_BOOT_NAND_START + and lr, lr, r0 + add lr, lr, r5 + and r12, r12, r0 + add r12, r12, r5 + add r5, r5, #0x8 + and r0, pc, r0 + add pc, r5, r0 + nop + nop + nop + nop + nop + adr r0, SAVE_REGS /* Save r12 & R14(lr) */ + str r12, [r0] + str lr, [r0, #4] +Copy_Main: + ldr r0, =NFC_BASE_ADDR_AXI + + add r6, r0, #0x1E00 + ldr r5, =_end /* Try get right image size */ + add r5, r2, #0x00040000 /* Fixme to get actual image size */ + + mov r7, #0xFF000000 + add r7, r7, #0x00FF0000 + str r7, [r3, #0x4] + str r7, [r3, #0x8] + str r7, [r3, #0xC] + str r7, [r3, #0x10] + str r7, [r3, #0x14] + str r7, [r3, #0x18] + str r7, [r3, #0x1C] + str r7, [r3, #0x20] + mov r8, #0x7 + mov r7, #0x84 +1: add r9, r7, r8, lsr #3 + str r9, [r3, #0x0] + subs r8, r8, #0x01 + bne 1b + + mov r7, #0 + str r7, [r3, #0x2C] + + ldr r7, NFC_PAGE_MODE +Read_Page: + /* start_nfc_addr_ops1(pg_no, pg_off) */ + cmp r7, #0x800 + movgt r7, r4, lsr #12 /* Get the page number for 4K page */ + moveq r7, r4, lsr #11 /* Get the page number for 2K page */ + mov r7, r7, lsl #16 + str r7, [r6, #0x04] /* Set the address */ + + /* writel((FLASH_Read_Mode1_LG << 8) | FLASH_Read_Mode1, NAND_CMD_REG)*/ + mov r7, #0x3000 + str r7, [r6,#0x0] + + /* writel(0x00000000, NAND_CONFIGURATION1_REG) */ + mov r7, #0x0 + str r7, [r6, #0x34] + + /* start auto-read + * writel(NAND_LAUNCH_AUTO_READ, NAND_LAUNCH_REG); + */ + mov r7, #0x80 + str r7, [r6, #0x40] + + do_wait_op_done + +Copy_Good_Blk: +1: ldmia r0!, {r7-r14} + stmia r2!, {r7-r14} + cmp r0, r1 + blo 1b + cmp r2, r5 + bge Copy_Main_done + ldr r7, NFC_PAGE_MODE + add r4, r4, r7 + ldr r0, =NFC_BASE_ADDR_AXI + b Read_Page + +Copy_Main_done: + adr r0, SAVE_REGS + ldr r12, [r0] + ldr lr, [r0, #4] + mov pc, lr + +U_BOOT_NAND_START: .word TEXT_BASE +CONST_0X0FFF: .word 0x0FFF +NFC_PAGE_MODE: .word 0x1000 +SAVE_REGS: .word 0x0 + .word 0x0 diff --git a/cpu/arm_cortexa8/mx51/serial.c b/cpu/arm_cortexa8/mx51/serial.c new file mode 100644 index 0000000000..7fe74e56af --- /dev/null +++ b/cpu/arm_cortexa8/mx51/serial.c @@ -0,0 +1,226 @@ +/* + * (c) 2007 Sascha Hauer + * + * (C) Copyright 2009 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#include + +#if defined CONFIG_MX51_UART + +#include + +#ifdef CONFIG_MX51_UART1 +#define UART_PHYS UART1_BASE_ADDR +#elif defined(CONFIG_MX51_UART2) +#define UART_PHYS UART2_BASE_ADDR +#elif defined(CONFIG_MX51_UART3) +#define UART_PHYS UART3_BASE_ADDR +#else +#error "define CFG_MX51_UARTx to use the mx51 UART driver" +#endif + +/* Register definitions */ +#define URXD 0x0 /* Receiver Register */ +#define UTXD 0x40 /* Transmitter Register */ +#define UCR1 0x80 /* Control Register 1 */ +#define UCR2 0x84 /* Control Register 2 */ +#define UCR3 0x88 /* Control Register 3 */ +#define UCR4 0x8c /* Control Register 4 */ +#define UFCR 0x90 /* FIFO Control Register */ +#define USR1 0x94 /* Status Register 1 */ +#define USR2 0x98 /* Status Register 2 */ +#define UESC 0x9c /* Escape Character Register */ +#define UTIM 0xa0 /* Escape Timer Register */ +#define UBIR 0xa4 /* BRM Incremental Register */ +#define UBMR 0xa8 /* BRM Modulator Register */ +#define UBRC 0xac /* Baud Rate Count Register */ +#define UTS 0xb4 /* UART Test Register (mx31) */ + +/* UART Control Register Bit Fields.*/ +#define URXD_CHARRDY (1<<15) +#define URXD_ERR (1<<14) +#define URXD_OVRRUN (1<<13) +#define URXD_FRMERR (1<<12) +#define URXD_BRK (1<<11) +#define URXD_PRERR (1<<10) +#define UCR1_ADEN (1<<15) /* Auto dectect interrupt */ +#define UCR1_ADBR (1<<14) /* Auto detect baud rate */ +#define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */ +#define UCR1_IDEN (1<<12) /* Idle condition interrupt */ +#define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */ +#define UCR1_RDMAEN (1<<8) /* Recv ready DMA enable */ +#define UCR1_IREN (1<<7) /* Infrared interface enable */ +#define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */ +#define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */ +#define UCR1_SNDBRK (1<<4) /* Send break */ +#define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */ +#define UCR1_UARTCLKEN (1<<2) /* UART clock enabled */ +#define UCR1_DOZE (1<<1) /* Doze */ +#define UCR1_UARTEN (1<<0) /* UART enabled */ +#define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */ +#define UCR2_IRTS (1<<14) /* Ignore RTS pin */ +#define UCR2_CTSC (1<<13) /* CTS pin control */ +#define UCR2_CTS (1<<12) /* Clear to send */ +#define UCR2_ESCEN (1<<11) /* Escape enable */ +#define UCR2_PREN (1<<8) /* Parity enable */ +#define UCR2_PROE (1<<7) /* Parity odd/even */ +#define UCR2_STPB (1<<6) /* Stop */ +#define UCR2_WS (1<<5) /* Word size */ +#define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */ +#define UCR2_TXEN (1<<2) /* Transmitter enabled */ +#define UCR2_RXEN (1<<1) /* Receiver enabled */ +#define UCR2_SRST (1<<0) /* SW reset */ +#define UCR3_DTREN (1<<13) /* DTR interrupt enable */ +#define UCR3_PARERREN (1<<12) /* Parity enable */ +#define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */ +#define UCR3_DSR (1<<10) /* Data set ready */ +#define UCR3_DCD (1<<9) /* Data carrier detect */ +#define UCR3_RI (1<<8) /* Ring indicator */ +#define UCR3_TIMEOUTEN (1<<7) /* Timeout interrupt enable */ +#define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */ +#define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */ +#define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */ +#define UCR3_REF25 (1<<3) /* Ref freq 25 MHz */ +#define UCR3_REF30 (1<<2) /* Ref Freq 30 MHz */ +#define UCR3_INVT (1<<1) /* Inverted Infrared transmission */ +#define UCR3_BPEN (1<<0) /* Preset registers enable */ +#define UCR4_CTSTL_32 (32<<10) /* CTS trigger level (32 chars) */ +#define UCR4_INVR (1<<9) /* Inverted infrared reception */ +#define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */ +#define UCR4_WKEN (1<<7) /* Wake interrupt enable */ +#define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */ +#define UCR4_IRSC (1<<5) /* IR special case */ +#define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */ +#define UCR4_BKEN (1<<2) /* Break condition interrupt enable */ +#define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */ +#define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */ +#define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */ +#define UFCR_RFDIV (7<<7) /* Reference freq divider mask */ +#define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */ +#define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */ +#define USR1_RTSS (1<<14) /* RTS pin status */ +#define USR1_TRDY (1<<13)/* Transmitter ready interrupt/dma flag */ +#define USR1_RTSD (1<<12) /* RTS delta */ +#define USR1_ESCF (1<<11) /* Escape seq interrupt flag */ +#define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */ +#define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */ +#define USR1_TIMEOUT (1<<7) /* Receive timeout interrupt status */ +#define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */ +#define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */ +#define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */ +#define USR2_ADET (1<<15) /* Auto baud rate detect complete */ +#define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */ +#define USR2_DTRF (1<<13) /* DTR edge interrupt flag */ +#define USR2_IDLE (1<<12) /* Idle condition */ +#define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */ +#define USR2_WAKE (1<<7) /* Wake */ +#define USR2_RTSF (1<<4) /* RTS edge interrupt flag */ +#define USR2_TXDC (1<<3) /* Transmitter complete */ +#define USR2_BRCD (1<<2) /* Break condition */ +#define USR2_ORE (1<<1) /* Overrun error */ +#define USR2_RDR (1<<0) /* Recv data ready */ +#define UTS_FRCPERR (1<<13) /* Force parity error */ +#define UTS_LOOP (1<<12) /* Loop tx and rx */ +#define UTS_TXEMPTY (1<<6) /* TxFIFO empty */ +#define UTS_RXEMPTY (1<<5) /* RxFIFO empty */ +#define UTS_TXFULL (1<<4) /* TxFIFO full */ +#define UTS_RXFULL (1<<3) /* RxFIFO full */ +#define UTS_SOFTRST (1<<0) /* Software reset */ + +DECLARE_GLOBAL_DATA_PTR; + +void serial_setbrg(void) +{ + u32 clk = mxc_get_clock(MXC_UART_CLK); + + if (!gd->baudrate) + gd->baudrate = CONFIG_BAUDRATE; + __REG(UART_PHYS + UFCR) = 0x4 << 7; /* divide input clock by 2 */ + __REG(UART_PHYS + UBIR) = 0xf; + __REG(UART_PHYS + UBMR) = clk / (2 * gd->baudrate); +} + +int serial_getc(void) +{ + while (__REG(UART_PHYS + UTS) & UTS_RXEMPTY) + ; + return __REG(UART_PHYS + URXD); +} + +void serial_putc(const char c) +{ + __REG(UART_PHYS + UTXD) = c; + + /* wait for transmitter to be ready */ + while (!(__REG(UART_PHYS + UTS) & UTS_TXEMPTY)) + ; + + /* If \n, also do \r */ + if (c == '\n') + serial_putc('\r'); +} + +/* + * Test whether a character is in the RX buffer + */ +int serial_tstc(void) +{ + /* If receive fifo is empty, return false */ + if (__REG(UART_PHYS + UTS) & UTS_RXEMPTY) + return 0; + return 1; +} + +void serial_puts(const char *s) +{ + while (*s) + serial_putc(*s++); +} + +/* + * Initialise the serial port with the given baudrate. The settings + * are always 8 data bits, no parity, 1 stop bit, no start bits. + * + */ +int serial_init(void) +{ + __REG(UART_PHYS + UCR1) = 0x0; + __REG(UART_PHYS + UCR2) = 0x0; + + while (!(__REG(UART_PHYS + UCR2) & UCR2_SRST)) + ; + + __REG(UART_PHYS + UCR3) = 0x0704; + __REG(UART_PHYS + UCR4) = 0x8000; + __REG(UART_PHYS + UESC) = 0x002b; + __REG(UART_PHYS + UTIM) = 0x0; + + __REG(UART_PHYS + UTS) = 0x0; + + serial_setbrg(); + + __REG(UART_PHYS + UCR2) = + UCR2_WS | UCR2_IRTS | UCR2_RXEN | UCR2_TXEN | UCR2_SRST; + + __REG(UART_PHYS + UCR1) = UCR1_UARTEN; + + return 0; +} + +#endif /* CONFIG_MX51_UART */ diff --git a/cpu/arm_cortexa8/mx51/timer.c b/cpu/arm_cortexa8/mx51/timer.c new file mode 100644 index 0000000000..2fa04d6b49 --- /dev/null +++ b/cpu/arm_cortexa8/mx51/timer.c @@ -0,0 +1,127 @@ +/* + * (C) Copyright 2007 + * Sascha Hauer, Pengutronix + * + * (C) Copyright 2008-2009 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +/* General purpose timers registers */ +#define GPTCR __REG(GPT1_BASE_ADDR) /* Control register */ +#define GPTPR __REG(GPT1_BASE_ADDR + 0x4) /* Prescaler register */ +#define GPTSR __REG(GPT1_BASE_ADDR + 0x8) /* Status register */ +#define GPTCNT __REG(GPT1_BASE_ADDR + 0x24) /* Counter register */ + +/* General purpose timers bitfields */ +#define GPTCR_SWR (1<<15) /* Software reset */ +#define GPTCR_FRR (1<<9) /* Freerun / restart */ +#define GPTCR_CLKSOURCE_32 (0x100<<6) /* Clock source */ +#define GPTCR_CLKSOURCE_IPG (0x001<<6) /* Clock source */ +#define GPTCR_TEN (1) /* Timer enable */ +#define GPTPR_VAL (66) + +static inline void setup_gpt() +{ + int i; + static int init_done; + + if (init_done) + return; + + init_done = 1; + + /* setup GP Timer 1 */ + GPTCR = GPTCR_SWR; + for (i = 0; i < 100; i++) + GPTCR = 0; /* We have no udelay by now */ + GPTPR = GPTPR_VAL; /* 66Mhz / 66 */ + /* Freerun Mode, PERCLK1 input */ + GPTCR |= GPTCR_CLKSOURCE_IPG | GPTCR_TEN; +} + +int timer_init(void) +{ + setup_gpt(); + + return 0; +} + +void reset_timer_masked(void) +{ + GPTCR = 0; + /* Freerun Mode, PERCLK1 input */ + GPTCR = GPTCR_CLKSOURCE_IPG | GPTCR_TEN; +} + +inline ulong get_timer_masked(void) +{ + ulong val = GPTCNT; + + return val; +} + +void reset_timer(void) +{ + reset_timer_masked(); +} + +ulong get_timer(ulong base) +{ + ulong tmp; + + tmp = get_timer_masked(); + + if (tmp <= (base * 1000)) { + /* Overflow */ + tmp += (0xffffffff - base); + } + + return (tmp / 1000) - base; +} + +void set_timer(ulong t) +{ +} + +/* delay x useconds AND perserve advance timstamp value */ +/* GPTCNT is now supposed to tick 1 by 1 us. */ +void udelay(unsigned long usec) +{ + ulong tmp; + + setup_gpt(); + + tmp = get_timer_masked(); /* get current timestamp */ + + /* if setting this forward will roll time stamp */ + if ((usec + tmp + 1) < tmp) { + /* reset "advancing" timestamp to 0, set lastinc value */ + reset_timer_masked(); + } else { + /* else, set advancing stamp wake up time */ + tmp += usec; + } + + while (get_timer_masked() < tmp) /* loop till event */ + /*NOP*/; +} diff --git a/cpu/arm_cortexa8/mx53/Makefile b/cpu/arm_cortexa8/mx53/Makefile new file mode 100644 index 0000000000..460bdd9aea --- /dev/null +++ b/cpu/arm_cortexa8/mx53/Makefile @@ -0,0 +1,48 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# (C) Copyright 2010 Freescale Semiconductor, Inc. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(SOC).a + +COBJS = interrupts.o serial.o generic.o iomux.o timer.o cache.o +COBJS += $(COBJS-y) + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) + +all: $(obj).depend $(LIB) + +$(LIB): $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/cpu/arm_cortexa8/mx53/cache.c b/cpu/arm_cortexa8/mx53/cache.c new file mode 100644 index 0000000000..60df92f862 --- /dev/null +++ b/cpu/arm_cortexa8/mx53/cache.c @@ -0,0 +1,44 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +void l2_cache_enable(void) +{ + asm("mrc 15, 0, r0, c1, c0, 1"); + asm("orr r0, r0, #0x2"); + asm("mcr 15, 0, r0, c1, c0, 1"); +} + +void l2_cache_disable(void) +{ + asm("mrc 15, 0, r0, c1, c0, 1"); + asm("bic r0, r0, #0x2"); + asm("mcr 15, 0, r0, c1, c0, 1"); +} + +/*dummy function for L2 ON*/ +u32 get_device_type(void) +{ + return 0; +} diff --git a/cpu/arm_cortexa8/mx53/crm_regs.h b/cpu/arm_cortexa8/mx53/crm_regs.h new file mode 100644 index 0000000000..aadca1fe4a --- /dev/null +++ b/cpu/arm_cortexa8/mx53/crm_regs.h @@ -0,0 +1,752 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef __ARCH_ARM_MACH_MX53_CRM_REGS_H__ +#define __ARCH_ARM_MACH_MX53_CRM_REGS_H__ + +#define MXC_CCM_BASE CCM_BASE_ADDR +#define MXC_DPLL1_BASE PLL1_BASE_ADDR +#define MXC_DPLL2_BASE PLL2_BASE_ADDR +#define MXC_DPLL3_BASE PLL3_BASE_ADDR +#define MXC_DPLL4_BASE PLL4_BASE_ADDR + +/* PLL Register Offsets */ +#define MXC_PLL_DP_CTL 0x00 +#define MXC_PLL_DP_CONFIG 0x04 +#define MXC_PLL_DP_OP 0x08 +#define MXC_PLL_DP_MFD 0x0C +#define MXC_PLL_DP_MFN 0x10 +#define MXC_PLL_DP_MFNMINUS 0x14 +#define MXC_PLL_DP_MFNPLUS 0x18 +#define MXC_PLL_DP_HFS_OP 0x1C +#define MXC_PLL_DP_HFS_MFD 0x20 +#define MXC_PLL_DP_HFS_MFN 0x24 +#define MXC_PLL_DP_MFN_TOGC 0x28 +#define MXC_PLL_DP_DESTAT 0x2c + +/* PLL Register Bit definitions */ +#define MXC_PLL_DP_CTL_MUL_CTRL 0x2000 +#define MXC_PLL_DP_CTL_DPDCK0_2_EN 0x1000 +#define MXC_PLL_DP_CTL_DPDCK0_2_OFFSET 12 +#define MXC_PLL_DP_CTL_ADE 0x800 +#define MXC_PLL_DP_CTL_REF_CLK_DIV 0x400 +#define MXC_PLL_DP_CTL_REF_CLK_SEL_MASK (3 << 8) +#define MXC_PLL_DP_CTL_REF_CLK_SEL_OFFSET 8 +#define MXC_PLL_DP_CTL_HFSM 0x80 +#define MXC_PLL_DP_CTL_PRE 0x40 +#define MXC_PLL_DP_CTL_UPEN 0x20 +#define MXC_PLL_DP_CTL_RST 0x10 +#define MXC_PLL_DP_CTL_RCP 0x8 +#define MXC_PLL_DP_CTL_PLM 0x4 +#define MXC_PLL_DP_CTL_BRM0 0x2 +#define MXC_PLL_DP_CTL_LRF 0x1 + +#define MXC_PLL_DP_CONFIG_BIST 0x8 +#define MXC_PLL_DP_CONFIG_SJC_CE 0x4 +#define MXC_PLL_DP_CONFIG_AREN 0x2 +#define MXC_PLL_DP_CONFIG_LDREQ 0x1 + +#define MXC_PLL_DP_OP_MFI_OFFSET 4 +#define MXC_PLL_DP_OP_MFI_MASK (0xF << 4) +#define MXC_PLL_DP_OP_PDF_OFFSET 0 +#define MXC_PLL_DP_OP_PDF_MASK 0xF + +#define MXC_PLL_DP_MFD_OFFSET 0 +#define MXC_PLL_DP_MFD_MASK 0x07FFFFFF + +#define MXC_PLL_DP_MFN_OFFSET 0x0 +#define MXC_PLL_DP_MFN_MASK 0x07FFFFFF + +#define MXC_PLL_DP_MFN_TOGC_TOG_DIS (1 << 17) +#define MXC_PLL_DP_MFN_TOGC_TOG_EN (1 << 16) +#define MXC_PLL_DP_MFN_TOGC_CNT_OFFSET 0x0 +#define MXC_PLL_DP_MFN_TOGC_CNT_MASK 0xFFFF + +#define MXC_PLL_DP_DESTAT_TOG_SEL (1 << 31) +#define MXC_PLL_DP_DESTAT_MFN 0x07FFFFFF + +/* Register addresses of CCM*/ +#define MXC_CCM_CCR (MXC_CCM_BASE + 0x00) +#define MXC_CCM_CCDR (MXC_CCM_BASE + 0x04) +#define MXC_CCM_CSR (MXC_CCM_BASE + 0x08) +#define MXC_CCM_CCSR (MXC_CCM_BASE + 0x0C) +#define MXC_CCM_CACRR (MXC_CCM_BASE + 0x10) +#define MXC_CCM_CBCDR (MXC_CCM_BASE + 0x14) +#define MXC_CCM_CBCMR (MXC_CCM_BASE + 0x18) +#define MXC_CCM_CSCMR1 (MXC_CCM_BASE + 0x1C) +#define MXC_CCM_CSCMR2 (MXC_CCM_BASE + 0x20) +#define MXC_CCM_CSCDR1 (MXC_CCM_BASE + 0x24) +#define MXC_CCM_CS1CDR (MXC_CCM_BASE + 0x28) +#define MXC_CCM_CS2CDR (MXC_CCM_BASE + 0x2C) +#define MXC_CCM_CDCDR (MXC_CCM_BASE + 0x30) +#define MXC_CCM_CHSCDR (MXC_CCM_BASE + 0x34) +#define MXC_CCM_CSCDR2 (MXC_CCM_BASE + 0x38) +#define MXC_CCM_CSCDR3 (MXC_CCM_BASE + 0x3C) +#define MXC_CCM_CSCDR4 (MXC_CCM_BASE + 0x40) +#define MXC_CCM_CWDR (MXC_CCM_BASE + 0x44) +#define MXC_CCM_CDHIPR (MXC_CCM_BASE + 0x48) +#define MXC_CCM_CDCR (MXC_CCM_BASE + 0x4C) +#define MXC_CCM_CTOR (MXC_CCM_BASE + 0x50) +#define MXC_CCM_CLPCR (MXC_CCM_BASE + 0x54) +#define MXC_CCM_CISR (MXC_CCM_BASE + 0x58) +#define MXC_CCM_CIMR (MXC_CCM_BASE + 0x5C) +#define MXC_CCM_CCOSR (MXC_CCM_BASE + 0x60) +#define MXC_CCM_CGPR (MXC_CCM_BASE + 0x64) +#define MXC_CCM_CCGR0 (MXC_CCM_BASE + 0x68) +#define MXC_CCM_CCGR1 (MXC_CCM_BASE + 0x6C) +#define MXC_CCM_CCGR2 (MXC_CCM_BASE + 0x70) +#define MXC_CCM_CCGR3 (MXC_CCM_BASE + 0x74) +#define MXC_CCM_CCGR4 (MXC_CCM_BASE + 0x78) +#define MXC_CCM_CCGR5 (MXC_CCM_BASE + 0x7C) +#define MXC_CCM_CCGR6 (MXC_CCM_BASE + 0x80) +#define MXC_CCM_CCGR7 (MXC_CCM_BASE + 0x80) +#define MXC_CCM_CMEOR (MXC_CCM_BASE + 0x88) + +/* Define the bits in register CCR */ +#define MXC_CCM_CCR_COSC_EN (1 << 12) +#define MXC_CCM_CCR_CAMP2_EN (1 << 10) +#define MXC_CCM_CCR_CAMP1_EN (1 << 9) +#define MXC_CCM_CCR_FPM_EN (1 << 8) +#define MXC_CCM_CCR_OSCNT_OFFSET (0) +#define MXC_CCM_CCR_OSCNT_MASK (0xFF) + +/* Define the bits in register CCDR */ +#define MXC_CCM_CCDR_IPU_HS_MASK (0x1 << 21) +#define MXC_CCM_CCDR_EMI_HS_INT2_MASK (0x1 << 20) +#define MXC_CCM_CCDR_EMI_HS_INT1_MASK (0x1 << 19) +#define MXC_CCM_CCDR_EMI_HS_SLOW_MASK (0x1 << 18) +#define MXC_CCM_CCDR_EMI_HS_FAST_MASK (0x1 << 17) +#define MXC_CCM_CCDR_EMI_HS_MASK (0x1 << 16) + +/* Define the bits in register CSR */ +#define MXC_CCM_CSR_COSR_READY (1 << 5) +#define MXC_CCM_CSR_LVS_VALUE (1 << 4) +#define MXC_CCM_CSR_CAMP2_READY (1 << 3) +#define MXC_CCM_CSR_CAMP1_READY (1 << 2) +#define MXC_CCM_CSR_TEMP_MON_ALARM (1 << 1) +#define MXC_CCM_CSR_REF_EN_B (1 << 0) + +/* Define the bits in register CCSR */ +#define MXC_CCM_CCSR_LP_APM_SEL (0x1 << 10) +#define MXC_CCM_CCSR_LP_APM_SEL_OFFSET 10 +#define MXC_CCM_CCSR_PLL4_SW_CLK_SEL (1 << 9) +#define MXC_CCM_CCSR_STEP_SEL_OFFSET (7) +#define MXC_CCM_CCSR_STEP_SEL_MASK (0x3 << 7) +#define MXC_CCM_CCSR_PLL2_PODF_OFFSET (5) +#define MXC_CCM_CCSR_PLL2_PODF_MASK (0x3 << 5) +#define MXC_CCM_CCSR_PLL3_PODF_OFFSET (3) +#define MXC_CCM_CCSR_PLL3_PODF_MASK (0x3 << 3) +#define MXC_CCM_CCSR_PLL1_SW_CLK_SEL (1 << 2) +#define MXC_CCM_CCSR_PLL2_SW_CLK_SEL (1 << 1) +#define MXC_CCM_CCSR_PLL3_SW_CLK_SEL (1 << 0) + +/* Define the bits in register CACRR */ +#define MXC_CCM_CACRR_ARM_PODF_OFFSET (0) +#define MXC_CCM_CACRR_ARM_PODF_MASK (0x7) + +/* Define the bits in register CBCDR */ +#define MXC_CCM_CBCDR_EMI_CLK_SEL (0x1 << 26) +#define MXC_CCM_CBCDR_PERIPH_CLK_SEL (0x1 << 25) +#define MXC_CCM_CBCDR_DDR_HF_SEL_OFFSET (30) +#define MXC_CCM_CBCDR_DDR_HF_SEL (0x1 << 30) +#define MXC_CCM_CBCDR_DDR_PODF_OFFSET (27) +#define MXC_CCM_CBCDR_DDR_PODF_MASK (0x7 << 27) +#define MXC_CCM_CBCDR_EMI_PODF_OFFSET (22) +#define MXC_CCM_CBCDR_EMI_PODF_MASK (0x7 << 22) +#define MXC_CCM_CBCDR_AXI_B_PODF_OFFSET (19) +#define MXC_CCM_CBCDR_AXI_B_PODF_MASK (0x7 << 19) +#define MXC_CCM_CBCDR_AXI_A_PODF_OFFSET (16) +#define MXC_CCM_CBCDR_AXI_A_PODF_MASK (0x7 << 16) +#define MXC_CCM_CBCDR_NFC_PODF_OFFSET (13) +#define MXC_CCM_CBCDR_NFC_PODF_MASK (0x7 << 13) +#define MXC_CCM_CBCDR_AHB_PODF_OFFSET (10) +#define MXC_CCM_CBCDR_AHB_PODF_MASK (0x7 << 10) +#define MXC_CCM_CBCDR_IPG_PODF_OFFSET (8) +#define MXC_CCM_CBCDR_IPG_PODF_MASK (0x3 << 8) +#define MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET (6) +#define MXC_CCM_CBCDR_PERCLK_PRED1_MASK (0x3 << 6) +#define MXC_CCM_CBCDR_PERCLK_PRED2_OFFSET (3) +#define MXC_CCM_CBCDR_PERCLK_PRED2_MASK (0x7 << 3) +#define MXC_CCM_CBCDR_PERCLK_PODF_OFFSET (0) +#define MXC_CCM_CBCDR_PERCLK_PODF_MASK (0x7) + +/* Define the bits in register CBCMR */ +#define MXC_CCM_CBCMR_GPU2D_CLK_SEL_OFFSET (16) +#define MXC_CCM_CBCMR_GPU2D_CLK_SEL_MASK (0x3 << 16) +#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET (14) +#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_MASK (0x3 << 14) +#define MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET (12) +#define MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK (0x3 << 12) +#define MXC_CCM_CBCMR_DDR_CLK_SEL_OFFSET (10) +#define MXC_CCM_CBCMR_DDR_CLK_SEL_MASK (0x3 << 10) +#define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_OFFSET (8) +#define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_MASK (0x3 << 8) +#define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_OFFSET (6) +#define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_MASK (0x3 << 6) +#define MXC_CCM_CBCMR_GPU_CLK_SEL_OFFSET (4) +#define MXC_CCM_CBCMR_GPU_CLK_SEL_MASK (0x3 << 4) +#define MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL (0x1 << 1) +#define MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL_OFFSET (1) +#define MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL (0x1 << 0) +#define MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL_OFFSET (0) + +/* Define the bits in register CSCMR1 */ +#define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_OFFSET (30) +#define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_MASK (0x3 << 30) +#define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_OFFSET (28) +#define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_MASK (0x3 << 28) +#define MXC_CCM_CSCMR1_USB_PHY_CLK_SEL_OFFSET (26) +#define MXC_CCM_CSCMR1_USB_PHY_CLK_SEL (0x1 << 26) +#define MXC_CCM_CSCMR1_UART_CLK_SEL_OFFSET (24) +#define MXC_CCM_CSCMR1_UART_CLK_SEL_MASK (0x3 << 24) +#define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_OFFSET (22) +#define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_MASK (0x3 << 22) +#define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_OFFSET (20) +#define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_MASK (0x3 << 20) +#define MXC_CCM_CSCMR1_ESDHC2_CLK_SEL (0x1 << 19) +#define MXC_CCM_CSCMR1_ESDHC4_CLK_SEL (0x1 << 18) +#define MXC_CCM_CSCMR1_ESDHC3_MSHC2_CLK_SEL_OFFSET (16) +#define MXC_CCM_CSCMR1_ESDHC3_MSHC2_CLK_SEL_MASK (0x3 << 16) +#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET (14) +#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK (0x3 << 14) +#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET (12) +#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_MASK (0x3 << 12) +#define MXC_CCM_CSCMR1_SSI3_CLK_SEL (0x1 << 11) +#define MXC_CCM_CSCMR1_VPU_RCLK_SEL (0x1 << 10) +#define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_OFFSET (8) +#define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_MASK (0x3 << 8) +#define MXC_CCM_CSCMR1_TVE_EXT_CLK_SEL (0x1 << 6) +#define MXC_CCM_CSCMR1_CSPI_CLK_SEL_OFFSET (4) +#define MXC_CCM_CSCMR1_CSPI_CLK_SEL_MASK (0x3 << 4) +#define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_OFFSET (2) +#define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_MASK (0x3 << 2) +#define MXC_CCM_CSCMR1_SSI_EXT2_COM_CLK_SEL (0x1 << 1) +#define MXC_CCM_CSCMR1_SSI_EXT1_COM_CLK_SEL (0x1) + +/* Define the bits in register CSCMR2 */ +#define MXC_CCM_CSCMR2_DI_CLK_SEL_OFFSET(n) (26+n*3) +#define MXC_CCM_CSCMR2_DI_CLK_SEL_MASK(n) (0x7 << (26+n*3)) +#define MXC_CCM_CSCMR2_CSI_MCLK2_CLK_SEL_OFFSET (24) +#define MXC_CCM_CSCMR2_CSI_MCLK2_CLK_SEL_MASK (0x3 << 24) +#define MXC_CCM_CSCMR2_CSI_MCLK1_CLK_SEL_OFFSET (22) +#define MXC_CCM_CSCMR2_CSI_MCLK1_CLK_SEL_MASK (0x3 << 22) +#define MXC_CCM_CSCMR2_ASRC_CLK_SEL (1<<21) +#define MXC_CCM_CSCMR2_ESAI_PRE_SEL_OFFSET (19) +#define MXC_CCM_CSCMR2_ESAI_PRE_SEL_MASK (0x3 << 19) +#define MXC_CCM_CSCMR2_ESAI_POST_SEL_OFFSET (16) +#define MXC_CCM_CSCMR2_ESAI_POST_SEL_MASK (0x7 << 16) +#define MXC_CCM_CSCMR2_IEEE_CLK_SEL_OFFSET (14) +#define MXC_CCM_CSCMR2_IEEE_CLK_SEL_MASK (0x3 << 14) +#define MXC_CCM_CSCMR2_FIRI_CLK_SEL_OFFSET (12) +#define MXC_CCM_CSCMR2_FIRI_CLK_SEL_MASK (0x3 << 12) +#define MXC_CCM_CSCMR2_LBD_DI1_IPU_DIV (0x1 << 11) +#define MXC_CCM_CSCMR2_LBD_DI0_IPU_DIV (0x1 << 10) +#define MXC_CCM_CSCMR2_LBD_DI1_CLK_SEL (0x1 << 9) +#define MXC_CCM_CSCMR2_LBD_DI0_CLK_SEL (0x1 << 8) +#define MXC_CCM_CSCMR2_CAN_CLK_SEL_OFFSET (6) +#define MXC_CCM_CSCMR2_CAN_CLK_SEL_MASK (0x3 << 6) +#define MXC_CCM_CSCMR2_SPDIF1_COM (1 << 5) +#define MXC_CCM_CSCMR2_SPDIF0_COM (1 << 4) +#define MXC_CCM_CSCMR2_SPDIF1_CLK_SEL_OFFSET (2) +#define MXC_CCM_CSCMR2_SPDIF1_CLK_SEL_MASK (0x3 << 2) +#define MXC_CCM_CSCMR2_SPDIF0_CLK_SEL_OFFSET (0) +#define MXC_CCM_CSCMR2_SPDIF0_CLK_SEL_MASK (0x3) + +/* Define the bits in register CSCDR1 */ +#define MXC_CCM_CSCDR1_ESDHC3_MSHC2_CLK_PRED_OFFSET (22) +#define MXC_CCM_CSCDR1_ESDHC3_MSHC2_CLK_PRED_MASK (0x7 << 22) +#define MXC_CCM_CSCDR1_ESDHC3_MSHC2_CLK_PODF_OFFSET (19) +#define MXC_CCM_CSCDR1_ESDHC3_MSHC2_CLK_PODF_MASK (0x7 << 19) +#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_OFFSET (16) +#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_MASK (0x7 << 16) +#define MXC_CCM_CSCDR1_PGC_CLK_PODF_OFFSET (14) +#define MXC_CCM_CSCDR1_PGC_CLK_PODF_MASK (0x3 << 14) +#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_OFFSET (11) +#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_MASK (0x7 << 11) +#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET (8) +#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK (0x7 << 8) +#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET (6) +#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK (0x3 << 6) +#define MXC_CCM_CSCDR1_UART_CLK_PRED_OFFSET (3) +#define MXC_CCM_CSCDR1_UART_CLK_PRED_MASK (0x7 << 3) +#define MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET (0) +#define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK (0x7) + +/* Define the bits in register CS1CDR and CS2CDR */ +#define MXC_CCM_CS1CDR_ESAI_CLK_PODF_OFFSET (25) +#define MXC_CCM_CS1CDR_ESAI_CLK_PODF_MASK (0x3F << 25) +#define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PRED_OFFSET (22) +#define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PRED_MASK (0x7 << 22) +#define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PODF_OFFSET (16) +#define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PODF_MASK (0x3F << 16) +#define MXC_CCM_CS1CDR_ESAI_CLK_PRED_OFFSET (9) +#define MXC_CCM_CS1CDR_ESAI_CLK_PRED_MASK (0x7 << 9) +#define MXC_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET (6) +#define MXC_CCM_CS1CDR_SSI1_CLK_PRED_MASK (0x7 << 6) +#define MXC_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET (0) +#define MXC_CCM_CS1CDR_SSI1_CLK_PODF_MASK (0x3F) + +#define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PRED_OFFSET (22) +#define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PRED_MASK (0x7 << 22) +#define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PODF_OFFSET (16) +#define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PODF_MASK (0x3F << 16) +#define MXC_CCM_CS2CDR_SSI2_CLK_PRED_OFFSET (6) +#define MXC_CCM_CS2CDR_SSI2_CLK_PRED_MASK (0x7 << 6) +#define MXC_CCM_CS2CDR_SSI2_CLK_PODF_OFFSET (0) +#define MXC_CCM_CS2CDR_SSI2_CLK_PODF_MASK (0x3F) + +/* Define the bits in register CDCDR */ +#define MXC_CCM_CDCDR_TVE_CLK_PRED_OFFSET (28) +#define MXC_CCM_CDCDR_TVE_CLK_PRED_MASK (0x7 << 28) +#define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_OFFSET (25) +#define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_MASK (0x7 << 25) +#define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_OFFSET (19) +#define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_MASK (0x3F << 19) +#define MXC_CCM_CDCDR_DI_PLL4_PODF_OFFSET (16) +#define MXC_CCM_CDCDR_DI_PLL4_PODF_MASK (0x7 << 16) +#define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_OFFSET (9) +#define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_MASK (0x3F << 9) +#define MXC_CCM_CDCDR_DI1_CLK_PRED_OFFSET (6) +#define MXC_CCM_CDCDR_DI1_CLK_PRED_MASK (0x7 << 6) +#define MXC_CCM_CDCDR_USB_PHY_PRED_OFFSET (3) +#define MXC_CCM_CDCDR_USB_PHY_PRED_MASK (0x7 << 3) +#define MXC_CCM_CDCDR_USB_PHY_PODF_OFFSET (0) +#define MXC_CCM_CDCDR_USB_PHY_PODF_MASK (0x7) + +/* Define the bits in register CHSCCDR */ +#define MXC_CCM_CHSCCDR_ESAI_HCKT_SEL_OFFSET (6) +#define MXC_CCM_CHSCCDR_ESAI_HCKT_SEL_MASK (0x3 << 6) +#define MXC_CCM_CHSCCDR_ESAI_HCKR_SEL_OFFSET (4) +#define MXC_CCM_CHSCCDR_ESAI_HCKR_SEL_MASK (0x3 << 4) +#define MXC_CCM_CHSCCDR_SSI2_MLB_SPDIF_SRC_OFFSET (2) +#define MXC_CCM_CHSCCDR_SSI2_MLB_SPDIF_SRC_MASK (0x3 << 2) +#define MXC_CCM_CHSCCDR_SSI1_MLB_SPDIF_SRC_OFFSET (0) +#define MXC_CCM_CHSCCDR_SSI1_MLB_SPDIF_SRC_MASK (0x3) + +/* Define the bits in register CSCDR2 */ +#define MXC_CCM_CSCDR2_ASRC_CLK_PRED_OFFSET (28) +#define MXC_CCM_CSCDR2_ASRC_CLK_PRED_MASK (0x7 << 28) +#define MXC_CCM_CSCDR2_CSPI_CLK_PRED_OFFSET (25) +#define MXC_CCM_CSCDR2_CSPI_CLK_PRED_MASK (0x7 << 25) +#define MXC_CCM_CSCDR2_CSPI_CLK_PODF_OFFSET (19) +#define MXC_CCM_CSCDR2_CSPI_CLK_PODF_MASK (0x3F << 19) +#define MXC_CCM_CSCDR2_ASRC_CLK_PODF_OFFSET (9) +#define MXC_CCM_CSCDR2_ASRC_CLK_PODF_MASK (0x3F << 9) +#define MXC_CCM_CSCDR2_IEEE_CLK_PRED_OFFSET (6) +#define MXC_CCM_CSCDR2_IEEE_CLK_PRED_MASK (0x7 << 6) +#define MXC_CCM_CSCDR2_IEEE_CLK_PODF_OFFSET (0) +#define MXC_CCM_CSCDR2_IEEE_CLK_PODF_MASK (0x3F) + +/* Define the bits in register CSCDR3 */ +#define MXC_CCM_CSCDR3_HSI2C_CLK_PRED_OFFSET (16) +#define MXC_CCM_CSCDR3_HSI2C_CLK_PRED_MASK (0x7 << 16) +#define MXC_CCM_CSCDR3_HSI2C_CLK_PODF_OFFSET (9) +#define MXC_CCM_CSCDR3_HSI2C_CLK_PODF_MASK (0x3F << 9) +#define MXC_CCM_CSCDR3_FIRI_CLK_PRED_OFFSET (6) +#define MXC_CCM_CSCDR3_FIRI_CLK_PRED_MASK (0x7 << 6) +#define MXC_CCM_CSCDR3_FIRI_CLK_PODF_OFFSET (0) +#define MXC_CCM_CSCDR3_FIRI_CLK_PODF_MASK (0x3F) + +/* Define the bits in register CSCDR4 */ +#define MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PRED_OFFSET (16) +#define MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PRED_MASK (0x7 << 16) +#define MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PODF_OFFSET (9) +#define MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PODF_MASK (0x3F << 9) +#define MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PRED_OFFSET (6) +#define MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PRED_MASK (0x7 << 6) +#define MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PODF_OFFSET (0) +#define MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PODF_MASK (0x3F) + +/* Define the bits in register CDHIPR */ +#define MXC_CCM_CDHIPR_ARM_PODF_BUSY (1 << 16) +#define MXC_CCM_CDHIPR_DDR_HF_CLK_SEL_BUSY (1 << 8) +#define MXC_CCM_CDHIPR_DDR_PODF_BUSY (1 << 7) +#define MXC_CCM_CDHIPR_EMI_CLK_SEL_BUSY (1 << 6) +#define MXC_CCM_CDHIPR_PERIPH_CLK_SEL_BUSY (1 << 5) +#define MXC_CCM_CDHIPR_NFC_IPG_INT_MEM_PODF_BUSY (1 << 4) +#define MXC_CCM_CDHIPR_AHB_PODF_BUSY (1 << 3) +#define MXC_CCM_CDHIPR_EMI_PODF_BUSY (1 << 2) +#define MXC_CCM_CDHIPR_AXI_B_PODF_BUSY (1 << 1) +#define MXC_CCM_CDHIPR_AXI_A_PODF_BUSY (1 << 0) + +/* Define the bits in register CDCR */ +#define MXC_CCM_CDCR_ARM_FREQ_SHIFT_DIVIDER (0x1 << 2) +#define MXC_CCM_CDCR_PERIPH_CLK_DVFS_PODF_OFFSET (0) +#define MXC_CCM_CDCR_PERIPH_CLK_DVFS_PODF_MASK (0x3) + +/* Define the bits in register CLPCR */ +#define MXC_CCM_CLPCR_BYPASS_CAN2_LPM_HS (0x1 << 27) +#define MXC_CCM_CLPCR_BYPASS_CAN1_LPM_HS (0x1 << 27) +#define MXC_CCM_CLPCR_BYPASS_SCC_LPM_HS (0x1 << 26) +#define MXC_CCM_CLPCR_BYPASS_MAX_LPM_HS (0x1 << 25) +#define MXC_CCM_CLPCR_BYPASS_SDMA_LPM_HS (0x1 << 24) +#define MXC_CCM_CLPCR_BYPASS_EMI_INT2_LPM_HS (0x1 << 23) +#define MXC_CCM_CLPCR_BYPASS_EMI_INT1_LPM_HS (0x1 << 22) +#define MXC_CCM_CLPCR_BYPASS_EMI_SLOW_LPM_HS (0x1 << 21) +#define MXC_CCM_CLPCR_BYPASS_EMI_FAST_LPM_HS (0x1 << 20) +#define MXC_CCM_CLPCR_BYPASS_EMI_LPM_HS (0x1 << 19) +#define MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS (0x1 << 18) +#define MXC_CCM_CLPCR_BYPASS_RTIC_LPM_HS (0x1 << 17) +#define MXC_CCM_CLPCR_BYPASS_RNGC_LPM_HS (0x1 << 16) +#define MXC_CCM_CLPCR_COSC_PWRDOWN (0x1 << 11) +#define MXC_CCM_CLPCR_STBY_COUNT_OFFSET (9) +#define MXC_CCM_CLPCR_STBY_COUNT_MASK (0x3 << 9) +#define MXC_CCM_CLPCR_VSTBY (0x1 << 8) +#define MXC_CCM_CLPCR_DIS_REF_OSC (0x1 << 7) +#define MXC_CCM_CLPCR_SBYOS (0x1 << 6) +#define MXC_CCM_CLPCR_ARM_CLK_DIS_ON_LPM (0x1 << 5) +#define MXC_CCM_CLPCR_LPSR_CLK_SEL_OFFSET (3) +#define MXC_CCM_CLPCR_LPSR_CLK_SEL_MASK (0x3 << 3) +#define MXC_CCM_CLPCR_LPM_OFFSET (0) +#define MXC_CCM_CLPCR_LPM_MASK (0x3) + +/* Define the bits in register CISR */ +#define MXC_CCM_CISR_ARM_PODF_LOADED (0x1 << 26) +#define MXC_CCM_CISR_TEMP_MON_ALARM (0x1 << 25) +#define MXC_CCM_CISR_EMI_CLK_SEL_LOADED (0x1 << 23) +#define MXC_CCM_CISR_PER_CLK_SEL_LOADED (0x1 << 22) +#define MXC_CCM_CISR_NFC_IPG_INT_MEM_PODF_LOADED (0x1 << 21) +#define MXC_CCM_CISR_AHB_PODF_LOADED (0x1 << 20) +#define MXC_CCM_CISR_EMI_PODF_LOADED (0x1 << 19) +#define MXC_CCM_CISR_AXI_B_PODF_LOADED (0x1 << 18) +#define MXC_CCM_CISR_AXI_A_PODF_LOADED (0x1 << 17) +#define MXC_CCM_CISR_DIVIDER_LOADED (0x1 << 16) +#define MXC_CCM_CISR_COSC_READY (0x1 << 6) +#define MXC_CCM_CISR_CKIH2_READY (0x1 << 5) +#define MXC_CCM_CISR_CKIH_READY (0x1 << 4) +#define MXC_CCM_CISR_FPM_READY (0x1 << 3) +#define MXC_CCM_CISR_LRF_PLL3 (0x1 << 2) +#define MXC_CCM_CISR_LRF_PLL2 (0x1 << 1) +#define MXC_CCM_CISR_LRF_PLL1 (0x1) + +/* Define the bits in register CIMR */ +#define MXC_CCM_CIMR_MASK_ARM_PODF_LOADED (0x1 << 26) +#define MXC_CCM_CIMR_MASK_TEMP_MON_ALARM (0x1 << 25) +#define MXC_CCM_CIMR_MASK_EMI_CLK_SEL_LOADED (0x1 << 23) +#define MXC_CCM_CIMR_MASK_PER_CLK_SEL_LOADED (0x1 << 22) +#define MXC_CCM_CIMR_MASK_NFC_IPG_INT_MEM_PODF_LOADED (0x1 << 21) +#define MXC_CCM_CIMR_MASK_AHB_PODF_LOADED (0x1 << 20) +#define MXC_CCM_CIMR_MASK_EMI_SLOW_PODF_LOADED (0x1 << 19) +#define MXC_CCM_CIMR_MASK_AXI_B_PODF_LOADED (0x1 << 18) +#define MXC_CCM_CIMR_MASK_AXI_A_PODF_LOADED (0x1 << 17) +#define MXC_CCM_CIMR_MASK_DIVIDER_LOADED (0x1 << 16) +#define MXC_CCM_CIMR_MASK_COSC_READY (0x1 << 6) +#define MXC_CCM_CIMR_MASK_CAMP2_READY (0x1 << 5) +#define MXC_CCM_CIMR_MASK_CAMP1_READY (0x1 << 4) +#define MXC_CCM_CIMR_MASK_LRF_PLL4 (0x1 << 3) +#define MXC_CCM_CIMR_MASK_LRF_PLL3 (0x1 << 2) +#define MXC_CCM_CIMR_MASK_LRF_PLL2 (0x1 << 1) +#define MXC_CCM_CIMR_MASK_LRF_PLL1 (0x1) + +/* Define the bits in register CCOSR */ +#define MXC_CCM_CCOSR_CKO2_EN_OFFSET (0x1 << 24) +#define MXC_CCM_CCOSR_CKO2_DIV_OFFSET (21) +#define MXC_CCM_CCOSR_CKO2_DIV_MASK (0x7 << 21) +#define MXC_CCM_CCOSR_CKO2_SEL_OFFSET (16) +#define MXC_CCM_CCOSR_CKO2_SEL_MASK (0x1F << 16) +#define MXC_CCM_CCOSR_CKOL_EN (0x1 << 7) +#define MXC_CCM_CCOSR_CKOL_DIV_OFFSET (4) +#define MXC_CCM_CCOSR_CKOL_DIV_MASK (0x7 << 4) +#define MXC_CCM_CCOSR_CKOL_SEL_OFFSET (0) +#define MXC_CCM_CCOSR_CKOL_SEL_MASK (0xF) + +/* Define the bits in registers CGPR */ +#define MXC_CCM_CGPR_ARM_CLK_INPUT_SEL (0x1 << 24) +#define MXC_CCM_CGPR_ARM_ASYNC_REF_EN (0x1 << 23) +#define MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE (0x1 << 4) +#define MXC_CCM_CGPR_FPM_SEL (0x1 << 3) +#define MXC_CCM_CGPR_VL_L2BIST_CLKDIV_OFFSET (0) +#define MXC_CCM_CGPR_VL_L2BIST_CLKDIV_MASK (0x7) + +/* Define the bits in registers CCGRx */ +#define MXC_CCM_CCGR_CG_MASK 0x3 + +#define MXC_CCM_CCGR0_CG15_OFFSET 30 +#define MXC_CCM_CCGR0_CG15_MASK (0x3 << 30) +#define MXC_CCM_CCGR0_CG14_OFFSET 28 +#define MXC_CCM_CCGR0_CG14_MASK (0x3 << 28) +#define MXC_CCM_CCGR0_CG13_OFFSET 26 +#define MXC_CCM_CCGR0_CG13_MASK (0x3 << 26) +#define MXC_CCM_CCGR0_CG12_OFFSET 24 +#define MXC_CCM_CCGR0_CG12_MASK (0x3 << 24) +#define MXC_CCM_CCGR0_CG11_OFFSET 22 +#define MXC_CCM_CCGR0_CG11_MASK (0x3 << 22) +#define MXC_CCM_CCGR0_CG10_OFFSET 20 +#define MXC_CCM_CCGR0_CG10_MASK (0x3 << 20) +#define MXC_CCM_CCGR0_CG9_OFFSET 18 +#define MXC_CCM_CCGR0_CG9_MASK (0x3 << 18) +#define MXC_CCM_CCGR0_CG8_OFFSET 16 +#define MXC_CCM_CCGR0_CG8_MASK (0x3 << 16) +#define MXC_CCM_CCGR0_CG7_OFFSET 14 +#define MXC_CCM_CCGR0_CG6_OFFSET 12 +#define MXC_CCM_CCGR0_CG5_OFFSET 10 +#define MXC_CCM_CCGR0_CG5_MASK (0x3 << 10) +#define MXC_CCM_CCGR0_CG4_OFFSET 8 +#define MXC_CCM_CCGR0_CG4_MASK (0x3 << 8) +#define MXC_CCM_CCGR0_CG3_OFFSET 6 +#define MXC_CCM_CCGR0_CG3_MASK (0x3 << 6) +#define MXC_CCM_CCGR0_CG2_OFFSET 4 +#define MXC_CCM_CCGR0_CG2_MASK (0x3 << 4) +#define MXC_CCM_CCGR0_CG1_OFFSET 2 +#define MXC_CCM_CCGR0_CG1_MASK (0x3 << 2) +#define MXC_CCM_CCGR0_CG0_OFFSET 0 +#define MXC_CCM_CCGR0_CG0_MASK 0x3 + +#define MXC_CCM_CCGR1_CG15_OFFSET 30 +#define MXC_CCM_CCGR1_CG14_OFFSET 28 +#define MXC_CCM_CCGR1_CG13_OFFSET 26 +#define MXC_CCM_CCGR1_CG12_OFFSET 24 +#define MXC_CCM_CCGR1_CG11_OFFSET 22 +#define MXC_CCM_CCGR1_CG10_OFFSET 20 +#define MXC_CCM_CCGR1_CG9_OFFSET 18 +#define MXC_CCM_CCGR1_CG8_OFFSET 16 +#define MXC_CCM_CCGR1_CG7_OFFSET 14 +#define MXC_CCM_CCGR1_CG6_OFFSET 12 +#define MXC_CCM_CCGR1_CG5_OFFSET 10 +#define MXC_CCM_CCGR1_CG4_OFFSET 8 +#define MXC_CCM_CCGR1_CG3_OFFSET 6 +#define MXC_CCM_CCGR1_CG2_OFFSET 4 +#define MXC_CCM_CCGR1_CG1_OFFSET 2 +#define MXC_CCM_CCGR1_CG0_OFFSET 0 + +#define MXC_CCM_CCGR2_CG15_OFFSET 30 +#define MXC_CCM_CCGR2_CG14_OFFSET 28 +#define MXC_CCM_CCGR2_CG13_OFFSET 26 +#define MXC_CCM_CCGR2_CG12_OFFSET 24 +#define MXC_CCM_CCGR2_CG11_OFFSET 22 +#define MXC_CCM_CCGR2_CG10_OFFSET 20 +#define MXC_CCM_CCGR2_CG9_OFFSET 18 +#define MXC_CCM_CCGR2_CG8_OFFSET 16 +#define MXC_CCM_CCGR2_CG7_OFFSET 14 +#define MXC_CCM_CCGR2_CG6_OFFSET 12 +#define MXC_CCM_CCGR2_CG5_OFFSET 10 +#define MXC_CCM_CCGR2_CG4_OFFSET 8 +#define MXC_CCM_CCGR2_CG3_OFFSET 6 +#define MXC_CCM_CCGR2_CG2_OFFSET 4 +#define MXC_CCM_CCGR2_CG1_OFFSET 2 +#define MXC_CCM_CCGR2_CG0_OFFSET 0 + +#define MXC_CCM_CCGR3_CG15_OFFSET 30 +#define MXC_CCM_CCGR3_CG14_OFFSET 28 +#define MXC_CCM_CCGR3_CG13_OFFSET 26 +#define MXC_CCM_CCGR3_CG12_OFFSET 24 +#define MXC_CCM_CCGR3_CG11_OFFSET 22 +#define MXC_CCM_CCGR3_CG10_OFFSET 20 +#define MXC_CCM_CCGR3_CG9_OFFSET 18 +#define MXC_CCM_CCGR3_CG8_OFFSET 16 +#define MXC_CCM_CCGR3_CG7_OFFSET 14 +#define MXC_CCM_CCGR3_CG6_OFFSET 12 +#define MXC_CCM_CCGR3_CG5_OFFSET 10 +#define MXC_CCM_CCGR3_CG4_OFFSET 8 +#define MXC_CCM_CCGR3_CG3_OFFSET 6 +#define MXC_CCM_CCGR3_CG2_OFFSET 4 +#define MXC_CCM_CCGR3_CG1_OFFSET 2 +#define MXC_CCM_CCGR3_CG0_OFFSET 0 + +#define MXC_CCM_CCGR4_CG15_OFFSET 30 +#define MXC_CCM_CCGR4_CG14_OFFSET 28 +#define MXC_CCM_CCGR4_CG13_OFFSET 26 +#define MXC_CCM_CCGR4_CG12_OFFSET 24 +#define MXC_CCM_CCGR4_CG11_OFFSET 22 +#define MXC_CCM_CCGR4_CG10_OFFSET 20 +#define MXC_CCM_CCGR4_CG9_OFFSET 18 +#define MXC_CCM_CCGR4_CG8_OFFSET 16 +#define MXC_CCM_CCGR4_CG7_OFFSET 14 +#define MXC_CCM_CCGR4_CG6_OFFSET 12 +#define MXC_CCM_CCGR4_CG5_OFFSET 10 +#define MXC_CCM_CCGR4_CG4_OFFSET 8 +#define MXC_CCM_CCGR4_CG3_OFFSET 6 +#define MXC_CCM_CCGR4_CG2_OFFSET 4 +#define MXC_CCM_CCGR4_CG1_OFFSET 2 +#define MXC_CCM_CCGR4_CG0_OFFSET 0 + +#define MXC_CCM_CCGR5_CG15_OFFSET 30 +#define MXC_CCM_CCGR5_CG14_OFFSET 28 +#define MXC_CCM_CCGR5_CG14_MASK (0x3 << 28) +#define MXC_CCM_CCGR5_CG13_OFFSET 26 +#define MXC_CCM_CCGR5_CG13_MASK (0x3 << 26) +#define MXC_CCM_CCGR5_CG12_OFFSET 24 +#define MXC_CCM_CCGR5_CG12_MASK (0x3 << 24) +#define MXC_CCM_CCGR5_CG11_OFFSET 22 +#define MXC_CCM_CCGR5_CG11_MASK (0x3 << 22) +#define MXC_CCM_CCGR5_CG10_OFFSET 20 +#define MXC_CCM_CCGR5_CG10_MASK (0x3 << 20) +#define MXC_CCM_CCGR5_CG9_OFFSET 18 +#define MXC_CCM_CCGR5_CG9_MASK (0x3 << 18) +#define MXC_CCM_CCGR5_CG8_OFFSET 16 +#define MXC_CCM_CCGR5_CG8_MASK (0x3 << 16) +#define MXC_CCM_CCGR5_CG7_OFFSET 14 +#define MXC_CCM_CCGR5_CG7_MASK (0x3 << 14) +#define MXC_CCM_CCGR5_CG6_OFFSET 12 +#define MXC_CCM_CCGR5_CG6_MASK (0x3 << 12) +#define MXC_CCM_CCGR5_CG5_OFFSET 10 +#define MXC_CCM_CCGR5_CG4_OFFSET 8 +#define MXC_CCM_CCGR5_CG3_OFFSET 6 +#define MXC_CCM_CCGR5_CG2_OFFSET 4 +#define MXC_CCM_CCGR5_CG2_MASK (0x3 << 4) +#define MXC_CCM_CCGR5_CG1_OFFSET 2 +#define MXC_CCM_CCGR5_CG0_OFFSET 0 + +#define MXC_CCM_CCGR6_CG15_OFFSET 30 +#define MXC_CCM_CCGR6_CG14_OFFSET 28 +#define MXC_CCM_CCGR6_CG14_MASK (0x3 << 28) +#define MXC_CCM_CCGR6_CG13_OFFSET 26 +#define MXC_CCM_CCGR6_CG13_MASK (0x3 << 26) +#define MXC_CCM_CCGR6_CG12_OFFSET 24 +#define MXC_CCM_CCGR6_CG12_MASK (0x3 << 24) +#define MXC_CCM_CCGR6_CG11_OFFSET 22 +#define MXC_CCM_CCGR6_CG11_MASK (0x3 << 22) +#define MXC_CCM_CCGR6_CG10_OFFSET 20 +#define MXC_CCM_CCGR6_CG10_MASK (0x3 << 20) +#define MXC_CCM_CCGR6_CG9_OFFSET 18 +#define MXC_CCM_CCGR6_CG9_MASK (0x3 << 18) +#define MXC_CCM_CCGR6_CG8_OFFSET 16 +#define MXC_CCM_CCGR6_CG8_MASK (0x3 << 16) +#define MXC_CCM_CCGR6_CG7_OFFSET 14 +#define MXC_CCM_CCGR6_CG7_MASK (0x3 << 14) +#define MXC_CCM_CCGR6_CG6_OFFSET 12 +#define MXC_CCM_CCGR6_CG6_MASK (0x3 << 12) +#define MXC_CCM_CCGR6_CG5_OFFSET 10 +#define MXC_CCM_CCGR6_CG4_OFFSET 8 +#define MXC_CCM_CCGR6_CG3_OFFSET 6 +#define MXC_CCM_CCGR6_CG2_OFFSET 4 +#define MXC_CCM_CCGR6_CG2_MASK (0x3 << 4) +#define MXC_CCM_CCGR6_CG1_OFFSET 2 +#define MXC_CCM_CCGR6_CG0_OFFSET 0 + +#define MXC_CCM_CCGR7_CG15_OFFSET 30 +#define MXC_CCM_CCGR7_CG14_OFFSET 28 +#define MXC_CCM_CCGR7_CG14_MASK (0x3 << 28) +#define MXC_CCM_CCGR7_CG13_OFFSET 26 +#define MXC_CCM_CCGR7_CG13_MASK (0x3 << 26) +#define MXC_CCM_CCGR7_CG12_OFFSET 24 +#define MXC_CCM_CCGR7_CG12_MASK (0x3 << 24) +#define MXC_CCM_CCGR7_CG11_OFFSET 22 +#define MXC_CCM_CCGR7_CG11_MASK (0x3 << 22) +#define MXC_CCM_CCGR7_CG10_OFFSET 20 +#define MXC_CCM_CCGR7_CG10_MASK (0x3 << 20) +#define MXC_CCM_CCGR7_CG9_OFFSET 18 +#define MXC_CCM_CCGR7_CG9_MASK (0x3 << 18) +#define MXC_CCM_CCGR7_CG8_OFFSET 16 +#define MXC_CCM_CCGR7_CG8_MASK (0x3 << 16) +#define MXC_CCM_CCGR7_CG7_OFFSET 14 +#define MXC_CCM_CCGR7_CG7_MASK (0x3 << 14) +#define MXC_CCM_CCGR7_CG6_OFFSET 12 +#define MXC_CCM_CCGR7_CG6_MASK (0x3 << 12) +#define MXC_CCM_CCGR7_CG5_OFFSET 10 +#define MXC_CCM_CCGR7_CG4_OFFSET 8 +#define MXC_CCM_CCGR7_CG3_OFFSET 6 +#define MXC_CCM_CCGR7_CG2_OFFSET 4 +#define MXC_CCM_CCGR7_CG2_MASK (0x3 << 4) +#define MXC_CCM_CCGR7_CG1_OFFSET 2 +#define MXC_CCM_CCGR7_CG0_OFFSET 0 + +#define MXC_GPC_BASE (IO_ADDRESS(GPC_BASE_ADDR)) +#define MXC_DPTC_LP_BASE (MXC_GPC_BASE + 0x80) +#define MXC_DPTC_GP_BASE (MXC_GPC_BASE + 0x100) +#define MXC_DVFS_CORE_BASE (MXC_GPC_BASE + 0x180) +#define MXC_DVFS_PER_BASE (MXC_GPC_BASE + 0x1C4) +#define MXC_PGC_IPU_BASE (MXC_GPC_BASE + 0x220) +#define MXC_PGC_VPU_BASE (MXC_GPC_BASE + 0x240) +#define MXC_PGC_GPU_BASE (MXC_GPC_BASE + 0x260) +#define MXC_SRPG_NEON_BASE (MXC_GPC_BASE + 0x280) +#define MXC_SRPG_ARM_BASE (MXC_GPC_BASE + 0x2A0) +#define MXC_SRPG_EMPGC0_BASE (MXC_GPC_BASE + 0x2C0) +#define MXC_SRPG_EMPGC1_BASE (MXC_GPC_BASE + 0x2D0) +#define MXC_SRPG_MEGAMIX_BASE (MXC_GPC_BASE + 0x2E0) +#define MXC_SRPG_EMI_BASE (MXC_GPC_BASE + 0x300) + +/* DVFS CORE */ +#define MXC_DVFSTHRS (MXC_DVFS_CORE_BASE + 0x00) +#define MXC_DVFSCOUN (MXC_DVFS_CORE_BASE + 0x04) +#define MXC_DVFSSIG1 (MXC_DVFS_CORE_BASE + 0x08) +#define MXC_DVFSSIG0 (MXC_DVFS_CORE_BASE + 0x0C) +#define MXC_DVFSGPC0 (MXC_DVFS_CORE_BASE + 0x10) +#define MXC_DVFSGPC1 (MXC_DVFS_CORE_BASE + 0x14) +#define MXC_DVFSGPBT (MXC_DVFS_CORE_BASE + 0x18) +#define MXC_DVFSEMAC (MXC_DVFS_CORE_BASE + 0x1C) +#define MXC_DVFSCNTR (MXC_DVFS_CORE_BASE + 0x20) +#define MXC_DVFSLTR0_0 (MXC_DVFS_CORE_BASE + 0x24) +#define MXC_DVFSLTR0_1 (MXC_DVFS_CORE_BASE + 0x28) +#define MXC_DVFSLTR1_0 (MXC_DVFS_CORE_BASE + 0x2C) +#define MXC_DVFSLTR1_1 (MXC_DVFS_CORE_BASE + 0x30) +#define MXC_DVFSPT0 (MXC_DVFS_CORE_BASE + 0x34) +#define MXC_DVFSPT1 (MXC_DVFS_CORE_BASE + 0x38) +#define MXC_DVFSPT2 (MXC_DVFS_CORE_BASE + 0x3C) +#define MXC_DVFSPT3 (MXC_DVFS_CORE_BASE + 0x40) + +/* DVFS PER */ +#define MXC_DVFSPER_LTR0 (MXC_DVFS_PER_BASE) +#define MXC_DVFSPER_LTR1 (MXC_DVFS_PER_BASE + 0x04) +#define MXC_DVFSPER_LTR2 (MXC_DVFS_PER_BASE + 0x08) +#define MXC_DVFSPER_LTR3 (MXC_DVFS_PER_BASE + 0x0C) +#define MXC_DVFSPER_LTBR0 (MXC_DVFS_PER_BASE + 0x10) +#define MXC_DVFSPER_LTBR1 (MXC_DVFS_PER_BASE + 0x14) +#define MXC_DVFSPER_PMCR0 (MXC_DVFS_PER_BASE + 0x18) +#define MXC_DVFSPER_PMCR1 (MXC_DVFS_PER_BASE + 0x1C) + +/* GPC */ +#define MXC_GPC_CNTR (MXC_GPC_BASE + 0x0) +#define MXC_GPC_PGR (MXC_GPC_BASE + 0x4) +#define MXC_GPC_VCR (MXC_GPC_BASE + 0x8) +#define MXC_GPC_ALL_PU (MXC_GPC_BASE + 0xC) +#define MXC_GPC_NEON (MXC_GPC_BASE + 0x10) + +/* PGC */ +#define MXC_PGC_IPU_PGCR (MXC_PGC_IPU_BASE + 0x0) +#define MXC_PGC_IPU_PGSR (MXC_PGC_IPU_BASE + 0xC) +#define MXC_PGC_VPU_PGCR (MXC_PGC_VPU_BASE + 0x0) +#define MXC_PGC_VPU_PGSR (MXC_PGC_VPU_BASE + 0xC) +#define MXC_PGC_GPU_PGCR (MXC_PGC_GPU_BASE + 0x0) +#define MXC_PGC_GPU_PGSR (MXC_PGC_GPU_BASE + 0xC) + +#define MXC_PGCR_PCR 1 +#define MXC_SRPGCR_PCR 1 +#define MXC_EMPGCR_PCR 1 +#define MXC_PGSR_PSR 1 + + +#define MXC_CORTEXA8_PLAT_LPC_DSM (1 << 0) +#define MXC_CORTEXA8_PLAT_LPC_DBG_DSM (1 << 1) + +/* SRPG */ +#define MXC_SRPG_NEON_SRPGCR (MXC_SRPG_NEON_BASE + 0x0) +#define MXC_SRPG_NEON_PUPSCR (MXC_SRPG_NEON_BASE + 0x4) +#define MXC_SRPG_NEON_PDNSCR (MXC_SRPG_NEON_BASE + 0x8) + +#define MXC_SRPG_ARM_SRPGCR (MXC_SRPG_ARM_BASE + 0x0) +#define MXC_SRPG_ARM_PUPSCR (MXC_SRPG_ARM_BASE + 0x4) +#define MXC_SRPG_ARM_PDNSCR (MXC_SRPG_ARM_BASE + 0x8) + +#define MXC_SRPG_EMPGC0_SRPGCR (MXC_SRPG_EMPGC0_BASE + 0x0) +#define MXC_SRPG_EMPGC0_PUPSCR (MXC_SRPG_EMPGC0_BASE + 0x4) +#define MXC_SRPG_EMPGC0_PDNSCR (MXC_SRPG_EMPGC0_BASE + 0x8) + +#define MXC_SRPG_EMPGC1_SRPGCR (MXC_SRPG_EMPGC1_BASE + 0x0) +#define MXC_SRPG_EMPGC1_PUPSCR (MXC_SRPG_EMPGC1_BASE + 0x4) +#define MXC_SRPG_EMPGC1_PDNSCR (MXC_SRPG_EMPGC1_BASE + 0x8) + +#define MXC_SRPG_MEGAMIX_SRPGCR (MXC_SRPG_MEGAMIX_BASE + 0x0) +#define MXC_SRPG_MEGAMIX_PUPSCR (MXC_SRPG_MEGAMIX_BASE + 0x4) +#define MXC_SRPG_MEGAMIX_PDNSCR (MXC_SRPG_MEGAMIX_BASE + 0x8) + +#define MXC_SRPGC_EMI_SRPGCR (MXC_SRPGC_EMI_BASE + 0x0) +#define MXC_SRPGC_EMI_PUPSCR (MXC_SRPGC_EMI_BASE + 0x4) +#define MXC_SRPGC_EMI_PDNSCR (MXC_SRPGC_EMI_BASE + 0x8) + +#endif /* __ARCH_ARM_MACH_MX53_CRM_REGS_H__ */ diff --git a/cpu/arm_cortexa8/mx53/generic.c b/cpu/arm_cortexa8/mx53/generic.c new file mode 100644 index 0000000000..664412ca0b --- /dev/null +++ b/cpu/arm_cortexa8/mx53/generic.c @@ -0,0 +1,993 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include "crm_regs.h" +#ifdef CONFIG_CMD_CLOCK +#include +#endif +#include +#ifdef CONFIG_ARCH_CPU_INIT +#include +#endif + +enum pll_clocks { + PLL1_CLK = MXC_DPLL1_BASE, + PLL2_CLK = MXC_DPLL2_BASE, + PLL3_CLK = MXC_DPLL3_BASE, + PLL4_CLK = MXC_DPLL4_BASE, +}; + +enum pll_sw_clocks { + PLL1_SW_CLK, + PLL2_SW_CLK, + PLL3_SW_CLK, + PLL4_SW_CLK, +}; + +#define AHB_CLK_ROOT 133333333 +#define IPG_CLK_ROOT 66666666 +#define IPG_PER_CLK_ROOT 40000000 + +#ifdef CONFIG_CMD_CLOCK +#define SZ_DEC_1M 1000000 +#define PLL_PD_MAX 16 /* Actual pd+1 */ +#define PLL_MFI_MAX 15 +#define PLL_MFI_MIN 5 +#define ARM_DIV_MAX 8 +#define IPG_DIV_MAX 4 +#define AHB_DIV_MAX 8 +#define EMI_DIV_MAX 8 +#define NFC_DIV_MAX 8 + +struct fixed_pll_mfd { + u32 ref_clk_hz; + u32 mfd; +}; + +const struct fixed_pll_mfd fixed_mfd[4] = { + {0, 0}, /* reserved */ + {0, 0}, /* reserved */ + {CONFIG_MX53_HCLK_FREQ, 24 * 16}, /* 384 */ + {0, 0}, /* reserved */ +}; + +struct pll_param { + u32 pd; + u32 mfi; + u32 mfn; + u32 mfd; +}; + +#define PLL_FREQ_MAX(_ref_clk_) \ + (4 * _ref_clk_ * PLL_MFI_MAX) +#define PLL_FREQ_MIN(_ref_clk_) \ + ((2 * _ref_clk_ * (PLL_MFI_MIN - 1)) / PLL_PD_MAX) +#define MAX_DDR_CLK 420000000 +#define AHB_CLK_MAX 133333333 +#define IPG_CLK_MAX (AHB_CLK_MAX / 2) +#define NFC_CLK_MAX 25000000 +#define HSP_CLK_MAX 133333333 +#endif + +static u32 __decode_pll(enum pll_clocks pll, u32 infreq) +{ + u32 mfi, mfn, mfd, pd; + + mfn = __REG(pll + MXC_PLL_DP_MFN); + mfd = __REG(pll + MXC_PLL_DP_MFD) + 1; + mfi = __REG(pll + MXC_PLL_DP_OP); + pd = (mfi & 0xF) + 1; + mfi = (mfi >> 4) & 0xF; + mfi = (mfi >= 5) ? mfi : 5; + + return ((4 * (infreq / 1000) * (mfi * mfd + mfn)) / (mfd * pd)) * 1000; +} + +static u32 __get_mcu_main_clk(void) +{ + u32 reg, freq; + reg = (__REG(MXC_CCM_CACRR) & MXC_CCM_CACRR_ARM_PODF_MASK) >> + MXC_CCM_CACRR_ARM_PODF_OFFSET; + freq = __decode_pll(PLL1_CLK, CONFIG_MX53_HCLK_FREQ); + return freq / (reg + 1); +} + +static u32 __get_periph_clk(void) +{ + u32 reg; + reg = __REG(MXC_CCM_CBCDR); + if (reg & MXC_CCM_CBCDR_PERIPH_CLK_SEL) { + reg = __REG(MXC_CCM_CBCMR); + switch ((reg & MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK) >> + MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET) { + case 0: + return __decode_pll(PLL1_CLK, CONFIG_MX53_HCLK_FREQ); + case 1: + return __decode_pll(PLL3_CLK, CONFIG_MX53_HCLK_FREQ); + default: + return 0; + } + } + return __decode_pll(PLL2_CLK, CONFIG_MX53_HCLK_FREQ); +} + +static u32 __get_ipg_clk(void) +{ + u32 ahb_podf, ipg_podf; + + ahb_podf = __REG(MXC_CCM_CBCDR); + ipg_podf = (ahb_podf & MXC_CCM_CBCDR_IPG_PODF_MASK) >> + MXC_CCM_CBCDR_IPG_PODF_OFFSET; + ahb_podf = (ahb_podf & MXC_CCM_CBCDR_AHB_PODF_MASK) >> + MXC_CCM_CBCDR_AHB_PODF_OFFSET; + return __get_periph_clk() / ((ahb_podf + 1) * (ipg_podf + 1)); +} + +static u32 __get_ipg_per_clk(void) +{ + u32 pred1, pred2, podf; + if (__REG(MXC_CCM_CBCMR) & MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL) + return __get_ipg_clk(); + /* Fixme: not handle what about lpm */ + podf = __REG(MXC_CCM_CBCDR); + pred1 = (podf & MXC_CCM_CBCDR_PERCLK_PRED1_MASK) >> + MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET; + pred2 = (podf & MXC_CCM_CBCDR_PERCLK_PRED2_MASK) >> + MXC_CCM_CBCDR_PERCLK_PRED2_OFFSET; + podf = (podf & MXC_CCM_CBCDR_PERCLK_PODF_MASK) >> + MXC_CCM_CBCDR_PERCLK_PODF_OFFSET; + + return __get_periph_clk() / ((pred1 + 1) * (pred2 + 1) * (podf + 1)); +} + +/*! + * This function returns the low power audio clock. + */ +static u32 __get_lp_apm(void) +{ + u32 ret_val = 0; + u32 ccsr = __REG(MXC_CCM_CCSR); + + if (((ccsr >> MXC_CCM_CCSR_LP_APM_SEL_OFFSET) & 1) == 0) + ret_val = CONFIG_MX53_HCLK_FREQ; + else + ret_val = ((32768 * 1024)); + + return ret_val; +} + +/* +static u32 __get_perclk_lp_apm(void) +{ + u32 ret_val = 0; + u32 cbcmr = __REG(MXC_CCM_CBCMR); + u32 clk_sel = (cbcmr & MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL) \ + >> MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL_OFFSET; + + switch (clk_sel) { + case 0: + ret_val = __get_periph_clk(); + break; + case 1: + ret_val = __get_lp_apm(); + break; + default: + break; + } + + return ret_val; +} +*/ + +static u32 __get_uart_clk(void) +{ + u32 freq = 0, reg, pred, podf; + reg = __REG(MXC_CCM_CSCMR1); + switch ((reg & MXC_CCM_CSCMR1_UART_CLK_SEL_MASK) >> + MXC_CCM_CSCMR1_UART_CLK_SEL_OFFSET) { + case 0x0: + freq = __decode_pll(PLL1_CLK, CONFIG_MX53_HCLK_FREQ); + break; + case 0x1: + freq = __decode_pll(PLL2_CLK, CONFIG_MX53_HCLK_FREQ); + break; + case 0x2: + freq = __decode_pll(PLL3_CLK, CONFIG_MX53_HCLK_FREQ); + break; + case 0x4: + freq = __get_lp_apm(); + break; + default: + break; + } + + reg = __REG(MXC_CCM_CSCDR1); + + pred = (reg & MXC_CCM_CSCDR1_UART_CLK_PRED_MASK) >> + MXC_CCM_CSCDR1_UART_CLK_PRED_OFFSET; + + podf = (reg & MXC_CCM_CSCDR1_UART_CLK_PODF_MASK) >> + MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET; + freq /= (pred + 1) * (podf + 1); + + return freq; +} + + +static u32 __get_cspi_clk(void) +{ + u32 ret_val = 0, pdf, pre_pdf, clk_sel, div; + u32 cscmr1 = __REG(MXC_CCM_CSCMR1); + u32 cscdr2 = __REG(MXC_CCM_CSCDR2); + + pre_pdf = (cscdr2 & MXC_CCM_CSCDR2_CSPI_CLK_PRED_MASK) \ + >> MXC_CCM_CSCDR2_CSPI_CLK_PRED_OFFSET; + pdf = (cscdr2 & MXC_CCM_CSCDR2_CSPI_CLK_PODF_MASK) \ + >> MXC_CCM_CSCDR2_CSPI_CLK_PODF_OFFSET; + clk_sel = (cscmr1 & MXC_CCM_CSCMR1_CSPI_CLK_SEL_MASK) \ + >> MXC_CCM_CSCMR1_CSPI_CLK_SEL_OFFSET; + + div = (pre_pdf + 1) * (pdf + 1); + + switch (clk_sel) { + case 0: + ret_val = __decode_pll(PLL1_CLK, CONFIG_MX53_HCLK_FREQ) / div; + break; + case 1: + ret_val = __decode_pll(PLL2_CLK, CONFIG_MX53_HCLK_FREQ) / div; + break; + case 2: + ret_val = __decode_pll(PLL3_CLK, CONFIG_MX53_HCLK_FREQ) / div; + break; + default: + ret_val = __get_lp_apm() / div; + break; + } + + return ret_val; +} + +static u32 __get_axi_a_clk(void) +{ + u32 cbcdr = __REG(MXC_CCM_CBCDR); + u32 pdf = (cbcdr & MXC_CCM_CBCDR_AXI_A_PODF_MASK) \ + >> MXC_CCM_CBCDR_AXI_A_PODF_OFFSET; + + return __get_periph_clk() / (pdf + 1); +} + +static u32 __get_axi_b_clk(void) +{ + u32 cbcdr = __REG(MXC_CCM_CBCDR); + u32 pdf = (cbcdr & MXC_CCM_CBCDR_AXI_B_PODF_MASK) \ + >> MXC_CCM_CBCDR_AXI_B_PODF_OFFSET; + + return __get_periph_clk() / (pdf + 1); +} + +static u32 __get_ahb_clk(void) +{ + u32 cbcdr = __REG(MXC_CCM_CBCDR); + u32 pdf = (cbcdr & MXC_CCM_CBCDR_AHB_PODF_MASK) \ + >> MXC_CCM_CBCDR_AHB_PODF_OFFSET; + + return __get_periph_clk() / (pdf + 1); +} + + +static u32 __get_emi_slow_clk(void) +{ + u32 cbcdr = __REG(MXC_CCM_CBCDR); + u32 emi_clk_sel = cbcdr & MXC_CCM_CBCDR_EMI_CLK_SEL; + u32 pdf = (cbcdr & MXC_CCM_CBCDR_EMI_PODF_MASK) \ + >> MXC_CCM_CBCDR_EMI_PODF_OFFSET; + + if (emi_clk_sel) + return __get_ahb_clk() / (pdf + 1); + + return __get_periph_clk() / (pdf + 1); +} + +/* +static u32 __get_nfc_clk(void) +{ + u32 cbcdr = __REG(MXC_CCM_CBCDR); + u32 pdf = (cbcdr & MXC_CCM_CBCDR_NFC_PODF_MASK) \ + >> MXC_CCM_CBCDR_NFC_PODF_OFFSET; + + return __get_emi_slow_clk() / (pdf + 1); +} +*/ + +static u32 __get_ddr_clk(void) +{ + u32 ret_val = 0; + u32 cbcmr = __REG(MXC_CCM_CBCMR); + u32 ddr_clk_sel = (cbcmr & MXC_CCM_CBCMR_DDR_CLK_SEL_MASK) \ + >> MXC_CCM_CBCMR_DDR_CLK_SEL_OFFSET; + + switch (ddr_clk_sel) { + case 0: + ret_val = __get_axi_a_clk(); + break; + case 1: + ret_val = __get_axi_b_clk(); + break; + case 2: + ret_val = __get_emi_slow_clk(); + break; + case 3: + ret_val = __get_ahb_clk(); + break; + default: + break; + } + + return ret_val; +} + +static u32 __get_esdhc1_clk(void) +{ + u32 ret_val = 0, div, pre_pdf, pdf; + u32 cscmr1 = __REG(MXC_CCM_CSCMR1); + u32 cscdr1 = __REG(MXC_CCM_CSCDR1); + u32 esdh1_clk_sel; + + esdh1_clk_sel = (cscmr1 & MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_MASK) \ + >> MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_OFFSET; + pre_pdf = (cscdr1 & MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_MASK) \ + >> MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_OFFSET; + pdf = (cscdr1 & MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_MASK) \ + >> MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_OFFSET ; + + div = (pre_pdf + 1) * (pdf + 1); + + switch (esdh1_clk_sel) { + case 0: + ret_val = __decode_pll(PLL1_CLK, CONFIG_MX53_HCLK_FREQ); + break; + case 1: + ret_val = __decode_pll(PLL2_CLK, CONFIG_MX53_HCLK_FREQ); + break; + case 2: + ret_val = __decode_pll(PLL3_CLK, CONFIG_MX53_HCLK_FREQ); + break; + case 3: + ret_val = __get_lp_apm(); + break; + default: + break; + } + + ret_val /= div; + + return ret_val; +} + +static u32 __get_esdhc3_clk(void) +{ + u32 ret_val = 0, div, pre_pdf, pdf; + u32 esdh3_clk_sel; + u32 cscmr1 = __REG(MXC_CCM_CSCMR1); + u32 cscdr1 = __REG(MXC_CCM_CSCDR1); + esdh3_clk_sel = (cscmr1 & MXC_CCM_CSCMR1_ESDHC3_MSHC2_CLK_SEL_MASK) \ + >> MXC_CCM_CSCMR1_ESDHC3_MSHC2_CLK_SEL_OFFSET; + pre_pdf = (cscdr1 & MXC_CCM_CSCDR1_ESDHC3_MSHC2_CLK_PRED_MASK) \ + >> MXC_CCM_CSCDR1_ESDHC3_MSHC2_CLK_PRED_OFFSET; + pdf = (cscdr1 & MXC_CCM_CSCDR1_ESDHC3_MSHC2_CLK_PODF_MASK) \ + >> MXC_CCM_CSCDR1_ESDHC3_MSHC2_CLK_PODF_OFFSET ; + + div = (pre_pdf + 1) * (pdf + 1); + + switch (esdh3_clk_sel) { + case 0: + ret_val = __decode_pll(PLL1_CLK, CONFIG_MX53_HCLK_FREQ); + break; + case 1: + ret_val = __decode_pll(PLL2_CLK, CONFIG_MX53_HCLK_FREQ); + break; + case 2: + ret_val = __decode_pll(PLL3_CLK, CONFIG_MX53_HCLK_FREQ); + break; + case 3: + ret_val = __get_lp_apm(); + break; + default: + break; + } + + ret_val /= div; + + return ret_val; +} + +static u32 __get_esdhc2_clk(void) +{ + u32 cscmr1 = __REG(MXC_CCM_CSCMR1); + u32 esdh2_clk_sel = cscmr1 & MXC_CCM_CSCMR1_ESDHC2_CLK_SEL; + if (esdh2_clk_sel) + return __get_esdhc3_clk(); + + return __get_esdhc1_clk(); +} + +static u32 __get_esdhc4_clk(void) +{ + u32 cscmr1 = __REG(MXC_CCM_CSCMR1); + u32 esdh4_clk_sel = cscmr1 & MXC_CCM_CSCMR1_ESDHC4_CLK_SEL; + if (esdh4_clk_sel) + return __get_esdhc3_clk(); + + return __get_esdhc1_clk(); +} + +unsigned int mxc_get_clock(enum mxc_clock clk) +{ + switch (clk) { + case MXC_ARM_CLK: + return __get_mcu_main_clk(); + case MXC_PER_CLK: + return __get_periph_clk(); + case MXC_AHB_CLK: + return __get_ahb_clk(); + case MXC_IPG_CLK: + return __get_ipg_clk(); + case MXC_IPG_PERCLK: + return __get_ipg_per_clk(); + case MXC_UART_CLK: + return __get_uart_clk(); + case MXC_CSPI_CLK: + return __get_cspi_clk(); + case MXC_AXI_A_CLK: + return __get_axi_a_clk(); + case MXC_AXI_B_CLK: + return __get_axi_b_clk(); + case MXC_EMI_SLOW_CLK: + return __get_emi_slow_clk(); + case MXC_DDR_CLK: + return __get_ddr_clk(); + case MXC_ESDHC_CLK: + return __get_esdhc1_clk(); + case MXC_ESDHC2_CLK: + return __get_esdhc2_clk(); + case MXC_ESDHC3_CLK: + return __get_esdhc3_clk(); + case MXC_ESDHC4_CLK: + return __get_esdhc4_clk(); + case MXC_SATA_CLK: + return __get_ahb_clk(); + default: + break; + } + return -1; +} + +void mxc_dump_clocks(void) +{ + u32 freq; + freq = __decode_pll(PLL1_CLK, CONFIG_MX53_HCLK_FREQ); + printf("mx53 pll1: %dMHz\n", freq / 1000000); + freq = __decode_pll(PLL2_CLK, CONFIG_MX53_HCLK_FREQ); + printf("mx53 pll2: %dMHz\n", freq / 1000000); + freq = __decode_pll(PLL3_CLK, CONFIG_MX53_HCLK_FREQ); + printf("mx53 pll3: %dMHz\n", freq / 1000000); + printf("ipg clock : %dHz\n", mxc_get_clock(MXC_IPG_CLK)); + printf("ipg per clock : %dHz\n", mxc_get_clock(MXC_IPG_PERCLK)); + printf("uart clock : %dHz\n", mxc_get_clock(MXC_UART_CLK)); + printf("cspi clock : %dHz\n", mxc_get_clock(MXC_CSPI_CLK)); + printf("ahb clock : %dHz\n", mxc_get_clock(MXC_AHB_CLK)); + printf("axi_a clock : %dHz\n", mxc_get_clock(MXC_AXI_A_CLK)); + printf("axi_b clock : %dHz\n", mxc_get_clock(MXC_AXI_B_CLK)); + printf("emi_slow clock: %dHz\n", mxc_get_clock(MXC_EMI_SLOW_CLK)); + printf("ddr clock : %dHz\n", mxc_get_clock(MXC_DDR_CLK)); + printf("esdhc1 clock : %dHz\n", mxc_get_clock(MXC_ESDHC_CLK)); + printf("esdhc2 clock : %dHz\n", mxc_get_clock(MXC_ESDHC2_CLK)); + printf("esdhc3 clock : %dHz\n", mxc_get_clock(MXC_ESDHC3_CLK)); + printf("esdhc4 clock : %dHz\n", mxc_get_clock(MXC_ESDHC4_CLK)); +} + +#ifdef CONFIG_CMD_CLOCK +/* precondition: m>0 and n>0. Let g=gcd(m,n). */ +static int gcd(int m, int n) +{ + int t; + while (m > 0) { + if (n > m) { + t = m; + m = n; + n = t; + } /* swap */ + m -= n; + } + return n; +} + +/*! + * This is to calculate various parameters based on reference clock and + * targeted clock based on the equation: + * t_clk = 2*ref_freq*(mfi + mfn/(mfd+1))/(pd+1) + * This calculation is based on a fixed MFD value for simplicity. + * + * @param ref reference clock freq in Hz + * @param target targeted clock in Hz + * @param pll pll_param structure. + * + * @return 0 if successful; non-zero otherwise. + */ +static int calc_pll_params(u32 ref, u32 target, struct pll_param *pll) +{ + u64 pd, mfi = 1, mfn, mfd, t1; + u32 n_target = target; + u32 n_ref = ref, i; + + /* + * Make sure targeted freq is in the valid range. + * Otherwise the following calculation might be wrong!!! + */ + if (n_target < PLL_FREQ_MIN(ref) || + n_target > PLL_FREQ_MAX(ref)) { + printf("Targeted peripheral clock should be" + "within [%d - %d]\n", + PLL_FREQ_MIN(ref) / SZ_DEC_1M, + PLL_FREQ_MAX(ref) / SZ_DEC_1M); + return -1; + } + + for (i = 0; i < ARRAY_SIZE(fixed_mfd); i++) { + if (fixed_mfd[i].ref_clk_hz == ref) { + mfd = fixed_mfd[i].mfd; + break; + } + } + + if (i == ARRAY_SIZE(fixed_mfd)) + return -1; + + /* Use n_target and n_ref to avoid overflow */ + for (pd = 1; pd <= PLL_PD_MAX; pd++) { + t1 = n_target * pd; + do_div(t1, (4 * n_ref)); + mfi = t1; + if (mfi > PLL_MFI_MAX) + return -1; + else if (mfi < 5) + continue; + break; + } + /* Now got pd and mfi already */ + /* + mfn = (((n_target * pd) / 4 - n_ref * mfi) * mfd) / n_ref; + */ + t1 = n_target * pd; + do_div(t1, 4); + t1 -= n_ref * mfi; + t1 *= mfd; + do_div(t1, n_ref); + mfn = t1; +#ifdef CMD_CLOCK_DEBUG + printf("%d: ref=%d, target=%d, pd=%d," + "mfi=%d,mfn=%d, mfd=%d\n", + __LINE__, ref, (u32)n_target, + (u32)pd, (u32)mfi, (u32)mfn, + (u32)mfd); +#endif + i = 1; + if (mfn != 0) + i = gcd(mfd, mfn); + pll->pd = (u32)pd; + pll->mfi = (u32)mfi; + do_div(mfn, i); + pll->mfn = (u32)mfn; + do_div(mfd, i); + pll->mfd = (u32)mfd; + + return 0; +} + +int clk_info(u32 clk_type) +{ + switch (clk_type) { + case CPU_CLK: + printf("CPU Clock: %dHz\n", + mxc_get_clock(MXC_ARM_CLK)); + break; + case PERIPH_CLK: + printf("Peripheral Clock: %dHz\n", + mxc_get_clock(MXC_PER_CLK)); + break; + case AHB_CLK: + printf("AHB Clock: %dHz\n", + mxc_get_clock(MXC_AHB_CLK)); + break; + case IPG_CLK: + printf("IPG Clock: %dHz\n", + mxc_get_clock(MXC_IPG_CLK)); + break; + case IPG_PERCLK: + printf("IPG_PER Clock: %dHz\n", + mxc_get_clock(MXC_IPG_PERCLK)); + break; + case UART_CLK: + printf("UART Clock: %dHz\n", + mxc_get_clock(MXC_UART_CLK)); + break; + case CSPI_CLK: + printf("CSPI Clock: %dHz\n", + mxc_get_clock(MXC_CSPI_CLK)); + break; + case DDR_CLK: + printf("DDR Clock: %dHz\n", + mxc_get_clock(MXC_DDR_CLK)); + break; + case ALL_CLK: + printf("cpu clock: %dMHz\n", + mxc_get_clock(MXC_ARM_CLK) / SZ_DEC_1M); + mxc_dump_clocks(); + break; + default: + printf("Unsupported clock type! :(\n"); + } + + return 0; +} + +#define calc_div(target_clk, src_clk, limit) ({ \ + u32 tmp = 0; \ + if ((src_clk % target_clk) <= 100) \ + tmp = src_clk / target_clk; \ + else \ + tmp = (src_clk / target_clk) + 1; \ + if (tmp > limit) \ + tmp = limit; \ + (tmp - 1); \ + }) + +u32 calc_per_cbcdr_val(u32 per_clk, u32 cbcmr) +{ + u32 cbcdr = __REG(MXC_CCM_CBCDR); + u32 tmp_clk = 0, div = 0, clk_sel = 0; + + cbcdr &= ~MXC_CCM_CBCDR_PERIPH_CLK_SEL; + + /* emi_slow_podf divider */ + tmp_clk = __get_emi_slow_clk(); + clk_sel = cbcdr & MXC_CCM_CBCDR_EMI_CLK_SEL; + if (clk_sel) { + div = calc_div(tmp_clk, per_clk, 8); + cbcdr &= ~MXC_CCM_CBCDR_EMI_PODF_MASK; + cbcdr |= (div << MXC_CCM_CBCDR_EMI_PODF_OFFSET); + } + + /* axi_b_podf divider */ + tmp_clk = __get_axi_b_clk(); + div = calc_div(tmp_clk, per_clk, 8); + cbcdr &= ~MXC_CCM_CBCDR_AXI_B_PODF_MASK; + cbcdr |= (div << MXC_CCM_CBCDR_AXI_B_PODF_OFFSET); + + /* axi_b_podf divider */ + tmp_clk = __get_axi_a_clk(); + div = calc_div(tmp_clk, per_clk, 8); + cbcdr &= ~MXC_CCM_CBCDR_AXI_A_PODF_MASK; + cbcdr |= (div << MXC_CCM_CBCDR_AXI_A_PODF_OFFSET); + + /* ahb podf divider */ + tmp_clk = AHB_CLK_ROOT; + div = calc_div(tmp_clk, per_clk, 8); + cbcdr &= ~MXC_CCM_CBCDR_AHB_PODF_MASK; + cbcdr |= (div << MXC_CCM_CBCDR_AHB_PODF_OFFSET); + + return cbcdr; +} + +#define CHANGE_PLL_SETTINGS(base, pd, mfi, mfn, mfd) \ + { \ + writel(0x1232, base + PLL_DP_CTL); \ + writel(0x2, base + PLL_DP_CONFIG); \ + writel(((pd - 1) << 0) | (mfi << 4), \ + base + PLL_DP_OP); \ + writel(mfn, base + PLL_DP_MFN); \ + writel(mfd - 1, base + PLL_DP_MFD); \ + writel(((pd - 1) << 0) | (mfi << 4), \ + base + PLL_DP_HFS_OP); \ + writel(mfn, base + PLL_DP_HFS_MFN); \ + writel(mfd - 1, base + PLL_DP_HFS_MFD); \ + writel(0x1232, base + PLL_DP_CTL); \ + while (!readl(base + PLL_DP_CTL) & 0x1) \ + ; \ + } + +int config_pll_clk(enum pll_clocks pll, struct pll_param *pll_param) +{ + u32 ccsr = readl(CCM_BASE_ADDR + CLKCTL_CCSR); + u32 pll_base = pll; + + switch (pll) { + case PLL1_CLK: + /* Switch ARM to PLL2 clock */ + writel(ccsr | 0x4, CCM_BASE_ADDR + CLKCTL_CCSR); + CHANGE_PLL_SETTINGS(pll_base, pll_param->pd, + pll_param->mfi, pll_param->mfn, + pll_param->mfd); + /* Switch back */ + writel(ccsr & ~0x4, CCM_BASE_ADDR + CLKCTL_CCSR); + break; + case PLL2_CLK: + /* Switch to pll2 bypass clock */ + writel(ccsr | 0x2, CCM_BASE_ADDR + CLKCTL_CCSR); + CHANGE_PLL_SETTINGS(pll_base, pll_param->pd, + pll_param->mfi, pll_param->mfn, + pll_param->mfd); + /* Switch back */ + writel(ccsr & ~0x2, CCM_BASE_ADDR + CLKCTL_CCSR); + break; + case PLL3_CLK: + /* Switch to pll3 bypass clock */ + writel(ccsr | 0x1, CCM_BASE_ADDR + CLKCTL_CCSR); + CHANGE_PLL_SETTINGS(pll_base, pll_param->pd, + pll_param->mfi, pll_param->mfn, + pll_param->mfd); + /* Switch back */ + writel(ccsr & ~0x1, CCM_BASE_ADDR + CLKCTL_CCSR); + break; + case PLL4_CLK: + /* Switch to pll4 bypass clock */ + writel(ccsr | 0x20, CCM_BASE_ADDR + CLKCTL_CCSR); + CHANGE_PLL_SETTINGS(pll_base, pll_param->pd, + pll_param->mfi, pll_param->mfn, + pll_param->mfd); + /* Switch back */ + writel(ccsr & ~0x20, CCM_BASE_ADDR + CLKCTL_CCSR); + break; + default: + return -1; + } + + return 0; +} + +int config_core_clk(u32 ref, u32 freq) +{ + int ret = 0; + u32 pll = 0; + struct pll_param pll_param; + + memset(&pll_param, 0, sizeof(struct pll_param)); + + /* The case that periph uses PLL1 is not considered here */ + pll = freq; + ret = calc_pll_params(ref, pll, &pll_param); + if (ret != 0) { + printf("Can't find pll parameters: %d\n", + ret); + return ret; + } + + return config_pll_clk(PLL1_CLK, &pll_param); +} + +int config_periph_clk(u32 ref, u32 freq) +{ + int ret = 0; + u32 pll = freq; + struct pll_param pll_param; + + memset(&pll_param, 0, sizeof(struct pll_param)); + + if (__REG(MXC_CCM_CBCDR) & MXC_CCM_CBCDR_PERIPH_CLK_SEL) { + /* Actually this case is not considered here */ + ret = calc_pll_params(ref, pll, &pll_param); + if (ret != 0) { + printf("Can't find pll parameters: %d\n", + ret); + return ret; + } + switch ((__REG(MXC_CCM_CBCMR) & \ + MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK) >> + MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET) { + case 0: + return config_pll_clk(PLL1_CLK, &pll_param); + break; + case 1: + return config_pll_clk(PLL3_CLK, &pll_param); + break; + default: + return -1; + } + } else { + u32 old_cbcmr = readl(CCM_BASE_ADDR + CLKCTL_CBCMR); + u32 new_cbcdr = calc_per_cbcdr_val(pll, old_cbcmr); + + /* Switch peripheral to PLL3 */ + writel(0x00015154, CCM_BASE_ADDR + CLKCTL_CBCMR); + writel(0x02888945, CCM_BASE_ADDR + CLKCTL_CBCDR); + + /* Make sure change is effective */ + while (readl(CCM_BASE_ADDR + CLKCTL_CDHIPR) != 0) + ; + + /* Setup PLL2 */ + ret = calc_pll_params(ref, pll, &pll_param); + if (ret != 0) { + printf("Can't find pll parameters: %d\n", + ret); + return ret; + } + config_pll_clk(PLL2_CLK, &pll_param); + + /* Switch peripheral back */ + writel(new_cbcdr, CCM_BASE_ADDR + CLKCTL_CBCDR); + writel(old_cbcmr, CCM_BASE_ADDR + CLKCTL_CBCMR); + + /* Make sure change is effective */ + while (readl(CCM_BASE_ADDR + CLKCTL_CDHIPR) != 0) + ; + puts("\n"); + } + + return 0; +} + +int config_ddr_clk(u32 emi_clk) +{ + u32 clk_src; + s32 shift = 0, clk_sel, div = 1; + u32 cbcmr = readl(CCM_BASE_ADDR + CLKCTL_CBCMR); + u32 cbcdr = readl(CCM_BASE_ADDR + CLKCTL_CBCDR); + + if (emi_clk > MAX_DDR_CLK) { + printf("DDR clock should be less than" + "%d MHz, assuming max value \n", + (MAX_DDR_CLK / SZ_DEC_1M)); + emi_clk = MAX_DDR_CLK; + } + + clk_src = __get_periph_clk(); + /* Find DDR clock input */ + clk_sel = (cbcmr >> 10) & 0x3; + switch (clk_sel) { + case 0: + shift = 16; + break; + case 1: + shift = 19; + break; + case 2: + shift = 22; + break; + case 3: + shift = 10; + break; + default: + return -1; + } + + if ((clk_src % emi_clk) == 0) + div = clk_src / emi_clk; + else + div = (clk_src / emi_clk) + 1; + if (div > 8) + div = 8; + + cbcdr = cbcdr & ~(0x7 << shift); + cbcdr |= ((div - 1) << shift); + writel(cbcdr, CCM_BASE_ADDR + CLKCTL_CBCDR); + while (readl(CCM_BASE_ADDR + CLKCTL_CDHIPR) != 0) + ; + writel(0x0, CCM_BASE_ADDR + CLKCTL_CCDR); + + return 0; +} + +/*! + * This function assumes the expected core clock has to be changed by + * modifying the PLL. This is NOT true always but for most of the times, + * it is. So it assumes the PLL output freq is the same as the expected + * core clock (presc=1) unless the core clock is less than PLL_FREQ_MIN. + * In the latter case, it will try to increase the presc value until + * (presc*core_clk) is greater than PLL_FREQ_MIN. It then makes call to + * calc_pll_params() and obtains the values of PD, MFI,MFN, MFD based + * on the targeted PLL and reference input clock to the PLL. Lastly, + * it sets the register based on these values along with the dividers. + * Note 1) There is no value checking for the passed-in divider values + * so the caller has to make sure those values are sensible. + * 2) Also adjust the NFC divider such that the NFC clock doesn't + * exceed NFC_CLK_MAX. + * 3) IPU HSP clock is independent of AHB clock. Even it can go up to + * 177MHz for higher voltage, this function fixes the max to 133MHz. + * 4) This function should not have allowed diag_printf() calls since + * the serial driver has been stoped. But leave then here to allow + * easy debugging by NOT calling the cyg_hal_plf_serial_stop(). + * + * @param ref pll input reference clock (24MHz) + * @param freq core clock in Hz + * @param clk_type clock type, e.g CPU_CLK, DDR_CLK, etc. + * @return 0 if successful; non-zero otherwise + */ +int clk_config(u32 ref, u32 freq, u32 clk_type) +{ + freq *= SZ_DEC_1M; + + switch (clk_type) { + case CPU_CLK: + if (config_core_clk(ref, freq)) + return -1; + break; + case PERIPH_CLK: + if (config_periph_clk(ref, freq)) + return -1; + break; + case DDR_CLK: + if (config_ddr_clk(freq)) + return -1; + break; + default: + printf("Unsupported or invalid clock type! :(\n"); + } + + return 0; +} +#endif + +#if defined(CONFIG_DISPLAY_CPUINFO) +int print_cpuinfo(void) +{ + printf("CPU: Freescale i.MX53 family %d.%dV at %d MHz\n", + (get_board_rev() & 0xFF) >> 4, + (get_board_rev() & 0xF), + __get_mcu_main_clk() / 1000000); + return 0; +} +#endif + +#if defined(CONFIG_MXC_FEC) +extern int mxc_fec_initialize(bd_t *bis); +extern void mxc_fec_set_mac_from_env(char *mac_addr); +#endif + +int cpu_eth_init(bd_t *bis) +{ + int rc = -ENODEV; +#if defined(CONFIG_MXC_FEC) + rc = mxc_fec_initialize(bis); +#endif + return rc; +} + +#if defined(CONFIG_ARCH_CPU_INIT) +int arch_cpu_init(void) +{ + icache_enable(); + dcache_enable(); + +#ifdef CONFIG_L2_OFF + l2_cache_disable(); +#else + l2_cache_enable(); +#endif + return 0; +} +#endif + diff --git a/cpu/arm_cortexa8/mx53/interrupts.c b/cpu/arm_cortexa8/mx53/interrupts.c new file mode 100644 index 0000000000..0b7bd95df9 --- /dev/null +++ b/cpu/arm_cortexa8/mx53/interrupts.c @@ -0,0 +1,39 @@ +/* + * (C) Copyright 2007 + * Sascha Hauer, Pengutronix + * + * Copyright (C) 2010 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +/* nothing really to do with interrupts, just starts up a counter. */ +int interrupt_init(void) +{ + return 0; +} + +void reset_cpu(ulong addr) +{ + __REG16(WDOG1_BASE_ADDR) = 4; +} diff --git a/cpu/arm_cortexa8/mx53/iomux.c b/cpu/arm_cortexa8/mx53/iomux.c new file mode 100644 index 0000000000..6e52561e1e --- /dev/null +++ b/cpu/arm_cortexa8/mx53/iomux.c @@ -0,0 +1,148 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @defgroup GPIO_MX53 Board GPIO and Muxing Setup + * @ingroup MSL_MX53 + */ +/*! + * @file mach-mx53/iomux.c + * + * @brief I/O Muxing control functions + * + * @ingroup GPIO_MX53 + */ +#include +#include +#include +#include +#include + +/*! + * IOMUX register (base) addresses + */ +enum iomux_reg_addr { + IOMUXGPR0 = IOMUXC_BASE_ADDR, + IOMUXGPR1 = IOMUXC_BASE_ADDR + 0x004, + IOMUXGPR2 = IOMUXC_BASE_ADDR + 0x008, + IOMUXSW_MUX_CTL = IOMUXC_BASE_ADDR, + IOMUXSW_MUX_END = IOMUXC_BASE_ADDR + MUX_I_END, + IOMUXSW_PAD_CTL = IOMUXC_BASE_ADDR + PAD_I_START, + IOMUXSW_INPUT_CTL = IOMUXC_BASE_ADDR + INPUT_CTL_START, +}; + +static inline u32 _get_mux_reg(iomux_pin_name_t pin) +{ + u32 mux_reg = PIN_TO_IOMUX_MUX(pin); + + mux_reg += IOMUXSW_MUX_CTL; + + return mux_reg; +} + +static inline u32 _get_pad_reg(iomux_pin_name_t pin) +{ + u32 pad_reg = PIN_TO_IOMUX_PAD(pin); + + pad_reg += IOMUXSW_PAD_CTL; + + return pad_reg; +} + +static inline u32 _get_mux_end(void) +{ + return IOMUXSW_MUX_END; +} + +/*! + * This function is used to configure a pin through the IOMUX module. + * FIXED ME: for backward compatible. Will be static function! + * @param pin a pin number as defined in \b #iomux_pin_name_t + * @param cfg an output function as defined in \b #iomux_pin_cfg_t + * + * @return 0 if successful; Non-zero otherwise + */ +static int iomux_config_mux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg) +{ + u32 mux_reg = _get_mux_reg(pin); + + if ((mux_reg > _get_mux_end()) || (mux_reg < IOMUXSW_MUX_CTL)) + return -1; + if (cfg == IOMUX_CONFIG_GPIO) + writel(PIN_TO_ALT_GPIO(pin), mux_reg); + else + writel(cfg, mux_reg); + + return 0; +} + +/*! + * Request ownership for an IO pin. This function has to be the first one + * being called before that pin is used. The caller has to check the + * return value to make sure it returns 0. + * + * @param pin a name defined by \b iomux_pin_name_t + * @param cfg an input function as defined in \b #iomux_pin_cfg_t + * + * @return 0 if successful; Non-zero otherwise + */ +int mxc_request_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg) +{ + int ret = iomux_config_mux(pin, cfg); + + return ret; +} + +/*! + * Release ownership for an IO pin + * + * @param pin a name defined by \b iomux_pin_name_t + * @param cfg an input function as defined in \b #iomux_pin_cfg_t + */ +void mxc_free_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg) +{ +} + +/*! + * This function configures the pad value for a IOMUX pin. + * + * @param pin a pin number as defined in \b #iomux_pin_name_t + * @param config the ORed value of elements defined in \b #iomux_pad_config_t + */ +void mxc_iomux_set_pad(iomux_pin_name_t pin, u32 config) +{ + u32 pad_reg = _get_pad_reg(pin); + + writel(config, pad_reg); +} + +unsigned int mxc_iomux_get_pad(iomux_pin_name_t pin) +{ + u32 pad_reg = _get_pad_reg(pin); + + return readl(pad_reg); +} +/*! + * This function configures input path. + * + * @param input index of input select register as defined in \b + * #iomux_input_select_t + * @param config the binary value of elements defined in \b + * #iomux_input_config_t + */ +void mxc_iomux_set_input(iomux_input_select_t input, u32 config) +{ + u32 reg = IOMUXSW_INPUT_CTL + (input << 2); + + writel(config, reg); +} diff --git a/cpu/arm_cortexa8/mx53/serial.c b/cpu/arm_cortexa8/mx53/serial.c new file mode 100644 index 0000000000..ce8b5c00f9 --- /dev/null +++ b/cpu/arm_cortexa8/mx53/serial.c @@ -0,0 +1,226 @@ +/* + * (c) 2007 Sascha Hauer + * + * Copyright (C) 2010 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#include + +#if defined CONFIG_MX53_UART + +#include + +#ifdef CONFIG_MX53_UART1 +#define UART_PHYS UART1_BASE_ADDR +#elif defined(CONFIG_MX53_UART2) +#define UART_PHYS UART2_BASE_ADDR +#elif defined(CONFIG_MX53_UART3) +#define UART_PHYS UART3_BASE_ADDR +#else +#error "define CFG_MX53_UARTx to use the mx53 UART driver" +#endif + +/* Register definitions */ +#define URXD 0x0 /* Receiver Register */ +#define UTXD 0x40 /* Transmitter Register */ +#define UCR1 0x80 /* Control Register 1 */ +#define UCR2 0x84 /* Control Register 2 */ +#define UCR3 0x88 /* Control Register 3 */ +#define UCR4 0x8c /* Control Register 4 */ +#define UFCR 0x90 /* FIFO Control Register */ +#define USR1 0x94 /* Status Register 1 */ +#define USR2 0x98 /* Status Register 2 */ +#define UESC 0x9c /* Escape Character Register */ +#define UTIM 0xa0 /* Escape Timer Register */ +#define UBIR 0xa4 /* BRM Incremental Register */ +#define UBMR 0xa8 /* BRM Modulator Register */ +#define UBRC 0xac /* Baud Rate Count Register */ +#define UTS 0xb4 /* UART Test Register (mx31) */ + +/* UART Control Register Bit Fields.*/ +#define URXD_CHARRDY (1<<15) +#define URXD_ERR (1<<14) +#define URXD_OVRRUN (1<<13) +#define URXD_FRMERR (1<<12) +#define URXD_BRK (1<<11) +#define URXD_PRERR (1<<10) +#define UCR1_ADEN (1<<15) /* Auto dectect interrupt */ +#define UCR1_ADBR (1<<14) /* Auto detect baud rate */ +#define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */ +#define UCR1_IDEN (1<<12) /* Idle condition interrupt */ +#define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */ +#define UCR1_RDMAEN (1<<8) /* Recv ready DMA enable */ +#define UCR1_IREN (1<<7) /* Infrared interface enable */ +#define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */ +#define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */ +#define UCR1_SNDBRK (1<<4) /* Send break */ +#define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */ +#define UCR1_UARTCLKEN (1<<2) /* UART clock enabled */ +#define UCR1_DOZE (1<<1) /* Doze */ +#define UCR1_UARTEN (1<<0) /* UART enabled */ +#define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */ +#define UCR2_IRTS (1<<14) /* Ignore RTS pin */ +#define UCR2_CTSC (1<<13) /* CTS pin control */ +#define UCR2_CTS (1<<12) /* Clear to send */ +#define UCR2_ESCEN (1<<11) /* Escape enable */ +#define UCR2_PREN (1<<8) /* Parity enable */ +#define UCR2_PROE (1<<7) /* Parity odd/even */ +#define UCR2_STPB (1<<6) /* Stop */ +#define UCR2_WS (1<<5) /* Word size */ +#define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */ +#define UCR2_TXEN (1<<2) /* Transmitter enabled */ +#define UCR2_RXEN (1<<1) /* Receiver enabled */ +#define UCR2_SRST (1<<0) /* SW reset */ +#define UCR3_DTREN (1<<13) /* DTR interrupt enable */ +#define UCR3_PARERREN (1<<12) /* Parity enable */ +#define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */ +#define UCR3_DSR (1<<10) /* Data set ready */ +#define UCR3_DCD (1<<9) /* Data carrier detect */ +#define UCR3_RI (1<<8) /* Ring indicator */ +#define UCR3_TIMEOUTEN (1<<7) /* Timeout interrupt enable */ +#define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */ +#define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */ +#define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */ +#define UCR3_REF25 (1<<3) /* Ref freq 25 MHz */ +#define UCR3_REF30 (1<<2) /* Ref Freq 30 MHz */ +#define UCR3_INVT (1<<1) /* Inverted Infrared transmission */ +#define UCR3_BPEN (1<<0) /* Preset registers enable */ +#define UCR4_CTSTL_32 (32<<10) /* CTS trigger level (32 chars) */ +#define UCR4_INVR (1<<9) /* Inverted infrared reception */ +#define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */ +#define UCR4_WKEN (1<<7) /* Wake interrupt enable */ +#define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */ +#define UCR4_IRSC (1<<5) /* IR special case */ +#define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */ +#define UCR4_BKEN (1<<2) /* Break condition interrupt enable */ +#define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */ +#define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */ +#define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */ +#define UFCR_RFDIV (7<<7) /* Reference freq divider mask */ +#define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */ +#define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */ +#define USR1_RTSS (1<<14) /* RTS pin status */ +#define USR1_TRDY (1<<13)/* Transmitter ready interrupt/dma flag */ +#define USR1_RTSD (1<<12) /* RTS delta */ +#define USR1_ESCF (1<<11) /* Escape seq interrupt flag */ +#define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */ +#define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */ +#define USR1_TIMEOUT (1<<7) /* Receive timeout interrupt status */ +#define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */ +#define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */ +#define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */ +#define USR2_ADET (1<<15) /* Auto baud rate detect complete */ +#define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */ +#define USR2_DTRF (1<<13) /* DTR edge interrupt flag */ +#define USR2_IDLE (1<<12) /* Idle condition */ +#define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */ +#define USR2_WAKE (1<<7) /* Wake */ +#define USR2_RTSF (1<<4) /* RTS edge interrupt flag */ +#define USR2_TXDC (1<<3) /* Transmitter complete */ +#define USR2_BRCD (1<<2) /* Break condition */ +#define USR2_ORE (1<<1) /* Overrun error */ +#define USR2_RDR (1<<0) /* Recv data ready */ +#define UTS_FRCPERR (1<<13) /* Force parity error */ +#define UTS_LOOP (1<<12) /* Loop tx and rx */ +#define UTS_TXEMPTY (1<<6) /* TxFIFO empty */ +#define UTS_RXEMPTY (1<<5) /* RxFIFO empty */ +#define UTS_TXFULL (1<<4) /* TxFIFO full */ +#define UTS_RXFULL (1<<3) /* RxFIFO full */ +#define UTS_SOFTRST (1<<0) /* Software reset */ + +DECLARE_GLOBAL_DATA_PTR; + +void serial_setbrg(void) +{ + u32 clk = mxc_get_clock(MXC_UART_CLK); + + if (!gd->baudrate) + gd->baudrate = CONFIG_BAUDRATE; + __REG(UART_PHYS + UFCR) = 0x4 << 7; /* divide input clock by 2 */ + __REG(UART_PHYS + UBIR) = 0xf; + __REG(UART_PHYS + UBMR) = clk / (2 * gd->baudrate); +} + +int serial_getc(void) +{ + while (__REG(UART_PHYS + UTS) & UTS_RXEMPTY) + ; + return __REG(UART_PHYS + URXD); +} + +void serial_putc(const char c) +{ + __REG(UART_PHYS + UTXD) = c; + + /* wait for transmitter to be ready */ + while (!(__REG(UART_PHYS + UTS) & UTS_TXEMPTY)) + ; + + /* If \n, also do \r */ + if (c == '\n') + serial_putc('\r'); +} + +/* + * Test whether a character is in the RX buffer + */ +int serial_tstc(void) +{ + /* If receive fifo is empty, return false */ + if (__REG(UART_PHYS + UTS) & UTS_RXEMPTY) + return 0; + return 1; +} + +void serial_puts(const char *s) +{ + while (*s) + serial_putc(*s++); +} + +/* + * Initialise the serial port with the given baudrate. The settings + * are always 8 data bits, no parity, 1 stop bit, no start bits. + * + */ +int serial_init(void) +{ + __REG(UART_PHYS + UCR1) = 0x0; + __REG(UART_PHYS + UCR2) = 0x0; + + while (!(__REG(UART_PHYS + UCR2) & UCR2_SRST)) + ; + + __REG(UART_PHYS + UCR3) = 0x0704; + __REG(UART_PHYS + UCR4) = 0x8000; + __REG(UART_PHYS + UESC) = 0x002b; + __REG(UART_PHYS + UTIM) = 0x0; + + __REG(UART_PHYS + UTS) = 0x0; + + serial_setbrg(); + + __REG(UART_PHYS + UCR2) = + UCR2_WS | UCR2_IRTS | UCR2_RXEN | UCR2_TXEN | UCR2_SRST; + + __REG(UART_PHYS + UCR1) = UCR1_UARTEN; + + return 0; +} + +#endif /* CONFIG_MX53_UART */ diff --git a/cpu/arm_cortexa8/mx53/timer.c b/cpu/arm_cortexa8/mx53/timer.c new file mode 100644 index 0000000000..e6b78466f1 --- /dev/null +++ b/cpu/arm_cortexa8/mx53/timer.c @@ -0,0 +1,127 @@ +/* + * (C) Copyright 2007 + * Sascha Hauer, Pengutronix + * + * Copyright (C) 2010 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +/* General purpose timers registers */ +#define GPTCR __REG(GPT1_BASE_ADDR) /* Control register */ +#define GPTPR __REG(GPT1_BASE_ADDR + 0x4) /* Prescaler register */ +#define GPTSR __REG(GPT1_BASE_ADDR + 0x8) /* Status register */ +#define GPTCNT __REG(GPT1_BASE_ADDR + 0x24) /* Counter register */ + +/* General purpose timers bitfields */ +#define GPTCR_SWR (1<<15) /* Software reset */ +#define GPTCR_FRR (1<<9) /* Freerun / restart */ +#define GPTCR_CLKSOURCE_32 (0x100<<6) /* Clock source */ +#define GPTCR_CLKSOURCE_IPG (0x001<<6) /* Clock source */ +#define GPTCR_TEN (1) /* Timer enable */ +#define GPTPR_VAL (50) + +static inline void setup_gpt(void) +{ + int i; + static int init_done; + + if (init_done) + return; + + init_done = 1; + + /* setup GP Timer 1 */ + GPTCR = GPTCR_SWR; + for (i = 0; i < 100; i++) + GPTCR = 0; /* We have no udelay by now */ + GPTPR = GPTPR_VAL; /* 50Mhz / 50 */ + /* Freerun Mode, PERCLK1 input */ + GPTCR |= GPTCR_CLKSOURCE_IPG | GPTCR_TEN; +} + +int timer_init(void) +{ + setup_gpt(); + + return 0; +} + +void reset_timer_masked(void) +{ + GPTCR = 0; + /* Freerun Mode, PERCLK1 input */ + GPTCR = GPTCR_CLKSOURCE_IPG | GPTCR_TEN; +} + +inline ulong get_timer_masked(void) +{ + ulong val = GPTCNT; + + return val; +} + +void reset_timer(void) +{ + reset_timer_masked(); +} + +ulong get_timer(ulong base) +{ + ulong tmp; + + tmp = get_timer_masked(); + + if (tmp <= (base * 1000)) { + /* Overflow */ + tmp += (0xffffffff - base); + } + + return (tmp / 1000) - base; +} + +void set_timer(ulong t) +{ +} + +/* delay x useconds AND perserve advance timstamp value */ +/* GPTCNT is now supposed to tick 1 by 1 us. */ +void udelay(unsigned long usec) +{ + ulong tmp; + + setup_gpt(); + + tmp = get_timer_masked(); /* get current timestamp */ + + /* if setting this forward will roll time stamp */ + if ((usec + tmp + 1) < tmp) { + /* reset "advancing" timestamp to 0, set lastinc value */ + reset_timer_masked(); + } else { + /* else, set advancing stamp wake up time */ + tmp += usec; + } + + while (get_timer_masked() < tmp) /* loop till event */ + /*NOP*/; +} diff --git a/cpu/arm_cortexa8/start.S b/cpu/arm_cortexa8/start.S index 6bd65521bd..4bbb56ae2f 100644 --- a/cpu/arm_cortexa8/start.S +++ b/cpu/arm_cortexa8/start.S @@ -9,6 +9,7 @@ * Copyright (c) 2003 Richard Woodruff * Copyright (c) 2003 Kshitij * Copyright (c) 2006-2008 Syed Mohammed Khasim + * Copyright (c) 2009 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -177,6 +178,9 @@ clbss_l: add r0, r0, #4 @ increment clear index pointer bne clbss_l @ keep clearing till at end +#ifdef CONFIG_ARCH_MMU + bl board_mmu_init +#endif ldr pc, _start_armboot @ jump to C code _start_armboot: .word start_armboot diff --git a/disk/part.c b/disk/part.c index b92fb45b86..139a923cfa 100644 --- a/disk/part.c +++ b/disk/part.c @@ -51,6 +51,9 @@ static const struct block_drvr block_drvr[] = { #if defined(CONFIG_CMD_IDE) { .name = "ide", .get_dev = ide_get_dev, }, #endif +#if defined(CONFIG_CMD_PATA) + { .name = "pata", .get_dev = pata_get_dev, }, +#endif #if defined(CONFIG_CMD_SATA) {.name = "sata", .get_dev = sata_get_dev, }, #endif @@ -95,6 +98,7 @@ block_dev_desc_t *get_dev(char* ifname, int dev) #endif #if (defined(CONFIG_CMD_IDE) || \ + defined(CONFIG_CMD_PATA) || \ defined(CONFIG_CMD_MG_DISK) || \ defined(CONFIG_CMD_SATA) || \ defined(CONFIG_CMD_SCSI) || \ @@ -213,6 +217,7 @@ void dev_print (block_dev_desc_t *dev_desc) #endif #if (defined(CONFIG_CMD_IDE) || \ + defined(CONFIG_CMD_PATA) || \ defined(CONFIG_CMD_MG_DISK) || \ defined(CONFIG_CMD_SATA) || \ defined(CONFIG_CMD_SCSI) || \ diff --git a/drivers/block/Makefile b/drivers/block/Makefile index 3f6ad5c12d..1ce481e557 100644 --- a/drivers/block/Makefile +++ b/drivers/block/Makefile @@ -27,6 +27,7 @@ LIB := $(obj)libblock.a COBJS-$(CONFIG_ATA_PIIX) += ata_piix.o COBJS-$(CONFIG_CMD_MG_DISK) += mg_disk.o +COBJS-$(CONFIG_DWC_AHSATA) += dwc_ahsata.o COBJS-$(CONFIG_FSL_SATA) += fsl_sata.o COBJS-$(CONFIG_IDE_SIL680) += sil680.o COBJS-$(CONFIG_LIBATA) += libata.o @@ -36,6 +37,7 @@ COBJS-$(CONFIG_SATA_SIL3114) += sata_sil3114.o COBJS-$(CONFIG_SCSI_AHCI) += ahci.o COBJS-$(CONFIG_SCSI_SYM53C8XX) += sym53c8xx.o COBJS-$(CONFIG_SYSTEMACE) += systemace.o +COBJS-$(CONFIG_MXC_ATA) += mxc_ata.o COBJS := $(COBJS-y) SRCS := $(COBJS:.o=.c) diff --git a/drivers/block/ahci.c b/drivers/block/ahci.c index a3ca2dcaf7..0ca220dbc7 100644 --- a/drivers/block/ahci.c +++ b/drivers/block/ahci.c @@ -1,4 +1,7 @@ /* + * (C) Copyright 2008-2010 Freescale Semiconductor, Inc. + * Terry Lv + * * Copyright (C) Freescale Semiconductor, Inc. 2006. * Author: Jason Jin * Zhang Wei @@ -390,7 +393,7 @@ static int ahci_port_start(u8 port) */ pp->cmd_slot = (struct ahci_cmd_hdr *)mem; debug("cmd_slot = 0x%x\n", pp->cmd_slot); - mem += (AHCI_CMD_SLOT_SZ + 224); + mem += (AHCI_CMD_SLOT_SZ * AHCI_MAX_CMD_SLOT); /* * Second item: Received-FIS area diff --git a/drivers/block/dwc_ahsata.c b/drivers/block/dwc_ahsata.c new file mode 100644 index 0000000000..5b6f20ea5d --- /dev/null +++ b/drivers/block/dwc_ahsata.c @@ -0,0 +1,1119 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. + * Terry Lv + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * with the reference on libata and ahci drvier in kernel + * + */ + +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#ifdef CONFIG_ARCH_MMU +#include +#endif + +#include "dwc_ahsata.h" + +struct sata_port_regs { + u32 clb; + u32 clbu; + u32 fb; + u32 fbu; + u32 is; + u32 ie; + u32 cmd; + u32 res1[1]; + u32 tfd; + u32 sig; + u32 ssts; + u32 sctl; + u32 serr; + u32 sact; + u32 ci; + u32 sntf; + u32 res2[1]; + u32 dmacr; + u32 res3[1]; + u32 phycr; + u32 physr; +}; + +struct sata_host_regs { + u32 cap; + u32 ghc; + u32 is; + u32 pi; + u32 vs; + u32 ccc_ctl; + u32 ccc_ports; + u32 res1[2]; + u32 cap2; + u32 res2[30]; + u32 bistafr; + u32 bistcr; + u32 bistfctr; + u32 bistsr; + u32 bistdecr; + u32 res3[2]; + u32 oobr; + u32 res4[8]; + u32 timer1ms; + u32 res5[1]; + u32 gparam1r; + u32 gparam2r; + u32 pparamr; + u32 testr; + u32 versionr; + u32 idr; +}; + +#define MAX_DATA_BYTES_PER_SG (4 * 1024 * 1024) +#define MAX_BYTES_PER_TRANS (AHCI_MAX_SG * MAX_DATA_BYTES_PER_SG) + +#define writel_with_flush(a, b) do { writel(a, b); readl(b); } while (0) + +#ifdef CONFIG_ARCH_MMU +static u8 *dma_buf; +#endif +static int is_ready; +extern block_dev_desc_t sata_dev_desc[CONFIG_SYS_SATA_MAX_DEVICE]; + +static inline void mdelay(u32 msec) +{ + u32 i; + for (i = 0; i < msec; ++i) + udelay(1000); +} + +static inline void sdelay(u32 sec) +{ + u32 i; + for (i = 0; i < sec; ++i) + mdelay(1000); +} + +void dprint_buffer(u8 *buf, s32 len) +{ + s32 i, j; + + i = 0; + j = 0; + printf("\n\r"); + + for (i = 0; i < len; ++i) { + printf("%02x ", *buf++); + j++; + if (j == 16) { + printf("\n\r"); + j = 0; + } + } + printf("\n\r"); +} + +static inline u32 ahci_port_base(u32 base, u32 port) +{ + return base + 0x100 + (port * 0x80); +} + + +static void ahci_setup_port(struct ahci_ioports *port, u32 base, + u32 port_idx) +{ + base = ahci_port_base(base, port_idx); +} + +static int waiting_for_cmd_completed(u8 *offset, + int timeout_msec, + u32 sign) +{ + int i; + u32 status; + + for (i = 0; + ((status = readl(offset)) & sign) && i < timeout_msec; + ++i) + mdelay(1); + + return (i < timeout_msec) ? 0 : -1; +} + +static int ahci_setup_oobr(struct ahci_probe_ent *probe_ent, + int clk) +{ + struct sata_host_regs *host_mmio = + (struct sata_host_regs *)probe_ent->mmio_base; + + writel(SATA_HOST_OOBR_WE, &(host_mmio->oobr)); + writel(0x02060b14, &(host_mmio->oobr)); + + return 0; +} + +static int ahci_host_init(struct ahci_probe_ent *probe_ent) +{ + u32 tmp, cap_save, num_ports; + int i, j, timeout = 1000; + struct sata_port_regs *port_mmio = NULL; + struct sata_host_regs *host_mmio = + (struct sata_host_regs *)probe_ent->mmio_base; + int clk = mxc_get_clock(MXC_SATA_CLK); + + cap_save = readl(&(host_mmio->cap)); + cap_save |= SATA_HOST_CAP_SSS; + + /* global controller reset */ + tmp = readl(&(host_mmio->ghc)); + if ((tmp & SATA_HOST_GHC_HR) == 0) + writel_with_flush(tmp | SATA_HOST_GHC_HR, &(host_mmio->ghc)); + + while ((readl(&(host_mmio->ghc)) & SATA_HOST_GHC_HR) + && --timeout) + ; + + if (timeout <= 0) { + debug("controller reset failed (0x%x)\n", tmp); + return -1; + } + + /* Set timer 1ms */ + writel(clk / 1000, &(host_mmio->timer1ms)); + + ahci_setup_oobr(probe_ent, 0); + + writel_with_flush(SATA_HOST_GHC_AE, &(host_mmio->ghc)); + writel(cap_save, &(host_mmio->cap)); + num_ports = (cap_save & SATA_HOST_CAP_NP_MASK) + 1; + writel_with_flush((1 << num_ports) - 1, + &(host_mmio->pi)); + + /* Determine which Ports are implemented by the DWC_ahsata, + * by reading the PI register. This bit map value aids the + * software to determine how many Ports are available and + * which Port registers need to be initialized. */ + probe_ent->cap = readl(&(host_mmio->cap)); + probe_ent->port_map = readl(&(host_mmio->pi)); + /* Determine how many command slots the HBA supports */ + probe_ent->n_ports = + (probe_ent->cap & SATA_HOST_CAP_NP_MASK) + 1; + + debug("cap 0x%x port_map 0x%x n_ports %d\n", + probe_ent->cap, probe_ent->port_map, probe_ent->n_ports); + + for (i = 0; i < probe_ent->n_ports; i++) { + probe_ent->port[i].port_mmio = + ahci_port_base((u32)host_mmio, i); + port_mmio = + (struct sata_port_regs *)probe_ent->port[i].port_mmio; + ahci_setup_port(&probe_ent->port[i], (u32)host_mmio, i); + + /* make sure port is not active */ + /* Ensure that the DWC_ahsata is in idle state */ + tmp = readl(&(port_mmio->cmd)); + /* When P#CMD.ST, P#CMD.CR, P#CMD.FRE and P#CMD.FR + * are all cleared, the Port is in an idle state. */ + if (tmp & (SATA_PORT_CMD_CR | SATA_PORT_CMD_FR | + SATA_PORT_CMD_FRE | SATA_PORT_CMD_ST)) { + /* System software places a Port into the idle state by + * clearing P#CMD.ST and waiting for P#CMD.CR to return + * 0 when read. */ + + tmp &= ~SATA_PORT_CMD_ST; + writel_with_flush(tmp, &(port_mmio->cmd)); + + /* spec says 500 msecs for each bit, so + * this is slightly incorrect. + */ + mdelay(500); + + timeout = 1000; + while ((readl(&(port_mmio->cmd)) & SATA_PORT_CMD_CR) + && --timeout) + ; + + if (timeout <= 0) { + debug("port reset failed (0x%x)\n", tmp); + return -1; + } + } + + /* Spin-up device */ + tmp = readl(&(port_mmio->cmd)); + writel((tmp | SATA_PORT_CMD_SUD), &(port_mmio->cmd)); + + /* Wait for spin-up to finish */ + timeout = 1000; + while (!(readl(&(port_mmio->cmd)) | SATA_PORT_CMD_SUD) + && --timeout) + ; + if (timeout <= 0) { + debug("Spin-Up can't finish!\n"); + return -1; + } + + for (j = 0; j < 100; ++j) { + mdelay(10); + tmp = readl(&(port_mmio->ssts)); + if (((tmp & SATA_PORT_SSTS_DET_MASK) == 0x3) || + ((tmp & SATA_PORT_SSTS_DET_MASK) == 0x1)) + break; + } + + /* Wait for COMINIT bit 26 (DIAG_X) in SERR */ + timeout = 1000; + while (!(readl(&(port_mmio->serr)) | SATA_PORT_SERR_DIAG_X) + && --timeout) + ; + if (timeout <= 0) { + debug("Can't find DIAG_X set!\n"); + return -1; + } + + /* For each implemented Port, clear the P#SERR + * register, by writing ones to each implemented\ + * bit location. */ + tmp = readl(&(port_mmio->serr)); + debug("P#SERR 0x%x\n", + tmp); + writel(tmp, &(port_mmio->serr)); + + /* Ack any pending irq events for this port */ + tmp = readl(&(host_mmio->is)); + debug("IS 0x%x\n", tmp); + if (tmp) + writel(tmp, &(host_mmio->is)); + + writel(1 << i, &(host_mmio->is)); + + /* set irq mask (enables interrupts) */ + writel(DEF_PORT_IRQ, &(port_mmio->ie)); + + /*register linkup ports */ + tmp = readl(&(port_mmio->ssts)); + debug("Port %d status: 0x%x\n", i, tmp); + if ((tmp & SATA_PORT_SSTS_DET_MASK) == 0x03) + probe_ent->link_port_map |= (0x01 << i); + } + + tmp = readl(&(host_mmio->ghc)); + debug("GHC 0x%x\n", tmp); + writel(tmp | SATA_HOST_GHC_IE, &(host_mmio->ghc)); + tmp = readl(&(host_mmio->ghc)); + debug("GHC 0x%x\n", tmp); + + return 0; +} + +static void ahci_print_info(struct ahci_probe_ent *probe_ent) +{ + struct sata_host_regs *host_mmio = + (struct sata_host_regs *)probe_ent->mmio_base; + u32 vers, cap, impl, speed; + const char *speed_s; + const char *scc_s; + + vers = readl(&(host_mmio->vs)); + cap = probe_ent->cap; + impl = probe_ent->port_map; + + speed = (cap & SATA_HOST_CAP_ISS_MASK) + >> SATA_HOST_CAP_ISS_OFFSET; + if (speed == 1) + speed_s = "1.5"; + else if (speed == 2) + speed_s = "3"; + else + speed_s = "?"; + + scc_s = "SATA"; + + printf("AHCI %02x%02x.%02x%02x " + "%u slots %u ports %s Gbps 0x%x impl %s mode\n", + (vers >> 24) & 0xff, + (vers >> 16) & 0xff, + (vers >> 8) & 0xff, + vers & 0xff, + ((cap >> 8) & 0x1f) + 1, + (cap & 0x1f) + 1, + speed_s, + impl, + scc_s); + + printf("flags: " + "%s%s%s%s%s%s" + "%s%s%s%s%s%s%s\n", + cap & (1 << 31) ? "64bit " : "", + cap & (1 << 30) ? "ncq " : "", + cap & (1 << 28) ? "ilck " : "", + cap & (1 << 27) ? "stag " : "", + cap & (1 << 26) ? "pm " : "", + cap & (1 << 25) ? "led " : "", + cap & (1 << 24) ? "clo " : "", + cap & (1 << 19) ? "nz " : "", + cap & (1 << 18) ? "only " : "", + cap & (1 << 17) ? "pmp " : "", + cap & (1 << 15) ? "pio " : "", + cap & (1 << 14) ? "slum " : "", + cap & (1 << 13) ? "part " : ""); +} + +static int ahci_init_one(int pdev) +{ + int rc; + struct ahci_probe_ent *probe_ent = NULL; + + probe_ent = malloc(sizeof(struct ahci_probe_ent)); + memset(probe_ent, 0, sizeof(struct ahci_probe_ent)); + probe_ent->dev = pdev; + + probe_ent->host_flags = ATA_FLAG_SATA + | ATA_FLAG_NO_LEGACY + | ATA_FLAG_MMIO + | ATA_FLAG_PIO_DMA + | ATA_FLAG_NO_ATAPI; + + probe_ent->mmio_base = CONFIG_DWC_AHSATA_BASE_ADDR; + + /* initialize adapter */ + rc = ahci_host_init(probe_ent); + if (rc) + goto err_out; + + ahci_print_info(probe_ent); + +#ifdef CONFIG_ARCH_MMU + dma_buf = (u8 *)memalign(ATA_MAX_SECTORS * ATA_SECT_SIZE, 4); + if (NULL == dma_buf) { + printf("Fail to alloc buf for dma access!\n"); + return 0; + } +#endif + + /* Save the private struct to block device struct */ + sata_dev_desc[pdev].priv = (void *)probe_ent; + + return 0; + +err_out: + return rc; +} + +static int ahci_fill_sg(struct ahci_probe_ent *probe_ent, + u8 port, unsigned char *buf, int buf_len) +{ + struct ahci_ioports *pp = &(probe_ent->port[port]); +#ifdef CONFIG_ARCH_MMU + struct ahci_sg *ahci_sg = + (struct ahci_sg *)ioremap_nocache( + iomem_to_phys((unsigned long)pp->cmd_tbl_sg), + 0); +#else + struct ahci_sg *ahci_sg = pp->cmd_tbl_sg; +#endif + u32 sg_count, max_bytes; + int i; + + max_bytes = MAX_DATA_BYTES_PER_SG; + sg_count = ((buf_len - 1) / max_bytes) + 1; + if (sg_count > AHCI_MAX_SG) { + printf("Error:Too much sg!\n"); + return -1; + } + + for (i = 0; i < sg_count; i++) { +#ifdef CONFIG_ARCH_MMU + ahci_sg->addr = + iomem_to_phys(cpu_to_le32((u32)buf + i * max_bytes)); +#else + ahci_sg->addr = + cpu_to_le32((u32)buf + i * max_bytes); +#endif + ahci_sg->addr_hi = 0; + ahci_sg->flags_size = cpu_to_le32(0x3fffff & + (buf_len < max_bytes + ? (buf_len - 1) + : (max_bytes - 1))); + ahci_sg++; + buf_len -= max_bytes; + } + + return sg_count; +} + +static void ahci_fill_cmd_slot(struct ahci_ioports *pp, u32 cmd_slot, u32 opts) +{ +#ifdef CONFIG_ARCH_MMU + struct ahci_cmd_hdr *cmd_hdr = + (struct ahci_cmd_hdr *)ioremap_nocache( + iomem_to_phys((unsigned long)pp->cmd_slot + + AHCI_CMD_SLOT_SZ * cmd_slot), 0); +#else + struct ahci_cmd_hdr *cmd_hdr = (struct ahci_cmd_hdr *)(pp->cmd_slot + + AHCI_CMD_SLOT_SZ * cmd_slot); +#endif + + memset(cmd_hdr, 0, AHCI_CMD_SLOT_SZ); + cmd_hdr->opts = cpu_to_le32(opts); + cmd_hdr->status = 0; +#ifdef CONFIG_ARCH_MMU + cmd_hdr->tbl_addr = + iomem_to_phys(cpu_to_le32(pp->cmd_tbl & 0xffffffff)); +#else + cmd_hdr->tbl_addr = cpu_to_le32(pp->cmd_tbl & 0xffffffff); +#endif + cmd_hdr->tbl_addr_hi = 0; +} + +#define AHCI_GET_CMD_SLOT(c) ((c) ? ffs(c) : 0) + +static int ahci_exec_ata_cmd(struct ahci_probe_ent *probe_ent, + u8 port, struct sata_fis_h2d *cfis, + u8 *buf, u32 buf_len, s32 is_write) +{ + struct ahci_ioports *pp = &(probe_ent->port[port]); + struct sata_port_regs *port_mmio = + (struct sata_port_regs *)pp->port_mmio; + u32 opts; + int sg_count = 0, cmd_slot = 0; + + cmd_slot = AHCI_GET_CMD_SLOT(readl(&(port_mmio->ci))); + if (32 == cmd_slot) { + printf("Can't find empty command slot!\n"); + return 0; + } + /* Check xfer length */ + if (buf_len > MAX_BYTES_PER_TRANS) { + printf("Max transfer length is %dB\n\r", + MAX_BYTES_PER_TRANS); + return 0; + } + + memcpy((u8 *)(pp->cmd_tbl), cfis, sizeof(struct sata_fis_h2d)); + if (buf && buf_len) + sg_count = ahci_fill_sg(probe_ent, port, buf, buf_len); + opts = (sizeof(struct sata_fis_h2d) >> 2) | (sg_count << 16); + if (is_write) + opts |= 0x40; + ahci_fill_cmd_slot(pp, cmd_slot, opts); + + writel_with_flush(1 << cmd_slot, &(port_mmio->ci)); + + if (waiting_for_cmd_completed((u8 *)&(port_mmio->ci), + 10000, 0x1 << cmd_slot)) { + printf("timeout exit!\n"); + return -1; + } + debug("ahci_exec_ata_cmd: %d byte transferred.\n", + pp->cmd_slot->status); + + return buf_len; +} + +static void ahci_set_feature(u8 dev, u8 port) +{ + struct ahci_probe_ent *probe_ent = + (struct ahci_probe_ent *)sata_dev_desc[dev].priv; + struct sata_fis_h2d h2d, *cfis = &h2d; + + /*set feature */ + memset(cfis, 0, sizeof(struct sata_fis_h2d)); + cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D; + cfis->pm_port_c = 1 << 7; + cfis->command = ATA_CMD_SET_FEATURES; + cfis->features = SETFEATURES_XFER; + cfis->sector_count = ffs(probe_ent->udma_mask + 1) + 0x3e; + + ahci_exec_ata_cmd(probe_ent, port, cfis, NULL, 0, READ_CMD); +} + +static int ahci_port_start(struct ahci_probe_ent *probe_ent, + u8 port) +{ + struct ahci_ioports *pp = &(probe_ent->port[port]); + struct sata_port_regs *port_mmio = + (struct sata_port_regs *)pp->port_mmio; + u32 port_status; + u32 mem; + int timeout = 1000; + + debug("Enter start port: %d\n", port); + port_status = readl(&(port_mmio->ssts)); + debug("Port %d status: %x\n", port, port_status); + if ((port_status & 0xf) != 0x03) { + printf("No Link on this port!\n"); + return -1; + } + + mem = (u32)malloc(AHCI_PORT_PRIV_DMA_SZ + 1024); + if (!mem) { + free(pp); + printf("No mem for table!\n"); + return -ENOMEM; + } + + mem = (mem + 0x400) & (~0x3ff); /* Aligned to 1024-bytes */ + memset((u8 *)mem, 0, AHCI_PORT_PRIV_DMA_SZ); + + /* + * First item in chunk of DMA memory: 32-slot command table, + * 32 bytes each in size + */ +#ifdef CONFIG_ARCH_MMU + pp->cmd_slot = + (struct ahci_cmd_hdr *)ioremap_nocache(iomem_to_phys((ulong)mem), + AHCI_CMD_SLOT_SZ); +#else + pp->cmd_slot = (struct ahci_cmd_hdr *)mem; +#endif + debug("cmd_slot = 0x%x\n", pp->cmd_slot); + mem += (AHCI_CMD_SLOT_SZ * DWC_AHSATA_MAX_CMD_SLOTS); + + /* + * Second item: Received-FIS area, 256-Byte aligned + */ +#ifdef CONFIG_ARCH_MMU + pp->rx_fis = (u32)ioremap_nocache(iomem_to_phys((ulong)mem), + AHCI_RX_FIS_SZ); +#else + pp->rx_fis = mem; +#endif + mem += AHCI_RX_FIS_SZ; + + /* + * Third item: data area for storing a single command + * and its scatter-gather table + */ +#ifdef CONFIG_ARCH_MMU + pp->cmd_tbl = (u32)ioremap_nocache(iomem_to_phys((ulong)mem), + AHCI_CMD_TBL_HDR); +#else + pp->cmd_tbl = mem; +#endif + debug("cmd_tbl_dma = 0x%x\n", pp->cmd_tbl); + + mem += AHCI_CMD_TBL_HDR; + + writel_with_flush(0x00004444, &(port_mmio->dmacr)); +#ifdef CONFIG_ARCH_MMU + pp->cmd_tbl_sg = + (struct ahci_sg *)ioremap_nocache(iomem_to_phys((ulong)mem), + AHCI_CMD_TBL_HDR); + writel_with_flush(iomem_to_phys((unsigned long)pp->cmd_slot), &port_mmio->clb); + writel_with_flush(iomem_to_phys(pp->rx_fis), &port_mmio->fb); +#else + pp->cmd_tbl_sg = (struct ahci_sg *)mem; + writel_with_flush((u32)pp->cmd_slot, &(port_mmio->clb)); + writel_with_flush(pp->rx_fis, &(port_mmio->fb)); +#endif + + /* Enable FRE */ + writel_with_flush((SATA_PORT_CMD_FRE | readl(&(port_mmio->cmd))), + &(port_mmio->cmd)); + + /* Wait device ready */ + while ((readl(&(port_mmio->tfd)) & (SATA_PORT_TFD_STS_ERR | + SATA_PORT_TFD_STS_DRQ | SATA_PORT_TFD_STS_BSY)) + && --timeout) + ; + if (timeout <= 0) { + debug("Device not ready for BSY, DRQ and" + "ERR in TFD!\n"); + return -1; + } + + writel_with_flush(PORT_CMD_ICC_ACTIVE | PORT_CMD_FIS_RX | + PORT_CMD_POWER_ON | PORT_CMD_SPIN_UP | + PORT_CMD_START, &(port_mmio->cmd)); + + debug("Exit start port %d\n", port); + + return 0; +} + +int init_sata(int dev) +{ + int i; + u32 linkmap; + struct ahci_probe_ent *probe_ent = NULL; + + if (dev < 0 || dev > (CONFIG_SYS_SATA_MAX_DEVICE - 1)) { + printf("The sata index %d is out of ranges\n\r", dev); + return -1; + } + + ahci_init_one(dev); + + probe_ent = (struct ahci_probe_ent *)sata_dev_desc[dev].priv; + linkmap = probe_ent->link_port_map; + + if (0 == linkmap) { + printf("No port device detected!\n"); + return 1; + } + + for (i = 0; i < probe_ent->n_ports; i++) { + if ((linkmap >> i) && ((linkmap >> i) & 0x01)) { + if (ahci_port_start(probe_ent, (u8)i)) { + printf("Can not start port %d\n", i); + return 1; + } + /* ahci_set_feature(dev, (u8)i); */ + probe_ent->hard_port_no = i; + break; + } + } + + return 0; +} + +static void dwc_ahsata_print_info(int dev) +{ + block_dev_desc_t *pdev = &(sata_dev_desc[dev]); + + printf("SATA Device Info:\n\r"); +#ifdef CONFIG_SYS_64BIT_LBA + printf("S/N: %s\n\rProduct model number: %s\n\r" + "Firmware version: %s\n\rCapacity: %lld sectors\n\r", + pdev->product, pdev->vendor, pdev->revision, pdev->lba); +#else + printf("S/N: %s\n\rProduct model number: %s\n\r" + "Firmware version: %s\n\rCapacity: %ld sectors\n\r", + pdev->product, pdev->vendor, pdev->revision, pdev->lba); +#endif +} + +static void dwc_ahsata_identify(int dev, u16 *id) +{ + struct ahci_probe_ent *probe_ent = + (struct ahci_probe_ent *)sata_dev_desc[dev].priv; + struct sata_fis_h2d h2d, *cfis = &h2d; + u8 port = probe_ent->hard_port_no; + + memset(cfis, 0, sizeof(struct sata_fis_h2d)); + + cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D; + cfis->pm_port_c = 0x80; /* is command */ + cfis->command = ATA_CMD_ID_ATA; + + ahci_exec_ata_cmd(probe_ent, port, cfis, + (u8 *)id, ATA_ID_WORDS * 2, READ_CMD); + ata_swap_buf_le16(id, ATA_ID_WORDS); +} + +static void dwc_ahsata_xfer_mode(int dev, u16 *id) +{ + struct ahci_probe_ent *probe_ent = + (struct ahci_probe_ent *)sata_dev_desc[dev].priv; + + probe_ent->pio_mask = id[ATA_ID_PIO_MODES]; + probe_ent->udma_mask = id[ATA_ID_UDMA_MODES]; + debug("pio %04x, udma %04x\n\r", + probe_ent->pio_mask, probe_ent->udma_mask); +} + +static u32 dwc_ahsata_rw_cmd(int dev, u32 start, u32 blkcnt, + u8 *buffer, int is_write) +{ + struct ahci_probe_ent *probe_ent = + (struct ahci_probe_ent *)sata_dev_desc[dev].priv; + struct sata_fis_h2d h2d, *cfis = &h2d; + u8 port = probe_ent->hard_port_no; + u32 block; +#ifdef CONFIG_ARCH_MMU + u8 *dma_buf_virt = NULL; + + dma_buf_virt = (u8 *)ioremap_nocache((ulong)dma_buf, 0); + memset(dma_buf_virt, 0, blkcnt * ATA_SECT_SIZE); +#endif + + block = start; + + memset(cfis, 0, sizeof(struct sata_fis_h2d)); + + cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D; + cfis->pm_port_c = 0x80; /* is command */ + cfis->command = (is_write) ? ATA_CMD_WRITE : ATA_CMD_READ; + cfis->device = ATA_LBA; + + cfis->device |= (block >> 24) & 0xf; + cfis->lba_high = (block >> 16) & 0xff; + cfis->lba_mid = (block >> 8) & 0xff; + cfis->lba_low = block & 0xff; + cfis->sector_count = (u8)(blkcnt & 0xff); + +#ifdef CONFIG_ARCH_MMU + if (is_write) + memcpy(dma_buf_virt, buffer, ATA_SECT_SIZE * blkcnt); + if (ahci_exec_ata_cmd(probe_ent, port, cfis, dma_buf_virt, + ATA_SECT_SIZE * blkcnt, is_write) > 0) { + if (!is_write) + memcpy(buffer, dma_buf_virt, ATA_SECT_SIZE * blkcnt); + } else + blkcnt = 0; + + return blkcnt; +#else + if (ahci_exec_ata_cmd(probe_ent, port, cfis, + buffer, ATA_SECT_SIZE * blkcnt, is_write) > 0) + return blkcnt; + else + return 0; +#endif +} + +void dwc_ahsata_flush_cache(int dev) +{ + struct ahci_probe_ent *probe_ent = + (struct ahci_probe_ent *)sata_dev_desc[dev].priv; + struct sata_fis_h2d h2d, *cfis = &h2d; + u8 port = probe_ent->hard_port_no; + + memset(cfis, 0, sizeof(struct sata_fis_h2d)); + + cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D; + cfis->pm_port_c = 0x80; /* is command */ + cfis->command = ATA_CMD_FLUSH; + + ahci_exec_ata_cmd(probe_ent, port, cfis, NULL, 0, 0); +} + +static u32 dwc_ahsata_rw_cmd_ext(int dev, u32 start, lbaint_t blkcnt, + u8 *buffer, int is_write) +{ + struct ahci_probe_ent *probe_ent = + (struct ahci_probe_ent *)sata_dev_desc[dev].priv; + struct sata_fis_h2d h2d, *cfis = &h2d; + u8 port = probe_ent->hard_port_no; + u64 block; +#ifdef CONFIG_ARCH_MMU + u8 *dma_buf_virt = NULL; + + dma_buf_virt = (u8 *)ioremap_nocache((ulong)dma_buf, 0); + memset(dma_buf_virt, 0, blkcnt * ATA_SECT_SIZE); +#endif + + block = (u64)start; + + memset(cfis, 0, sizeof(struct sata_fis_h2d)); + + cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D; + cfis->pm_port_c = 0x80; /* is command */ + + cfis->command = (is_write) ? ATA_CMD_WRITE_EXT + : ATA_CMD_READ_EXT; + + cfis->lba_high_exp = (block >> 40) & 0xff; + cfis->lba_mid_exp = (block >> 32) & 0xff; + cfis->lba_low_exp = (block >> 24) & 0xff; + cfis->lba_high = (block >> 16) & 0xff; + cfis->lba_mid = (block >> 8) & 0xff; + cfis->lba_low = block & 0xff; + cfis->device = ATA_LBA; + cfis->sector_count_exp = (blkcnt >> 8) & 0xff; + cfis->sector_count = blkcnt & 0xff; + +#ifdef CONFIG_ARCH_MMU + if (is_write) + memcpy(dma_buf_virt, buffer, ATA_SECT_SIZE * blkcnt); + if (ahci_exec_ata_cmd(probe_ent, port, cfis, dma_buf_virt, + ATA_SECT_SIZE * blkcnt, is_write) > 0) { + if (!is_write) + memcpy(buffer, dma_buf_virt, ATA_SECT_SIZE * blkcnt); + } else + blkcnt = 0; + + return blkcnt; +#else + if (ahci_exec_ata_cmd(probe_ent, port, cfis, buffer, + ATA_SECT_SIZE * blkcnt, is_write) > 0) + return blkcnt; + else + return 0; +#endif +} + +u32 dwc_ahsata_rw_ncq_cmd(int dev, u32 start, lbaint_t blkcnt, + u8 *buffer, int is_write) +{ + struct ahci_probe_ent *probe_ent = + (struct ahci_probe_ent *)sata_dev_desc[dev].priv; + struct sata_fis_h2d h2d, *cfis = &h2d; + u8 port = probe_ent->hard_port_no; + u8 queue_depth; + int ncq_channel; + u64 block; + + if (sata_dev_desc[dev].lba48 != 1) { + printf("execute FPDMA command on non-LBA48 hard disk\n\r"); + return -1; + } + + block = (u64)start; + + memset(cfis, 0, sizeof(struct sata_fis_h2d)); + + cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D; + cfis->pm_port_c = 0x80; /* is command */ + + cfis->command = (is_write) ? ATA_CMD_FPDMA_WRITE + : ATA_CMD_FPDMA_READ; + + cfis->lba_high_exp = (block >> 40) & 0xff; + cfis->lba_mid_exp = (block >> 32) & 0xff; + cfis->lba_low_exp = (block >> 24) & 0xff; + cfis->lba_high = (block >> 16) & 0xff; + cfis->lba_mid = (block >> 8) & 0xff; + cfis->lba_low = block & 0xff; + + cfis->device = ATA_LBA; + cfis->features_exp = (blkcnt >> 8) & 0xff; + cfis->features = blkcnt & 0xff; + + queue_depth = probe_ent->flags & SATA_FLAG_Q_DEP_MASK; + if (queue_depth >= DWC_AHSATA_HC_MAX_CMD) + ncq_channel = DWC_AHSATA_HC_MAX_CMD - 1; + else + ncq_channel = queue_depth - 1; + + /* Use the latest queue */ + ahci_exec_ata_cmd(probe_ent, port, cfis, + buffer, ATA_SECT_SIZE * blkcnt, is_write); + + return blkcnt; +} + +void dwc_ahsata_flush_cache_ext(int dev) +{ + struct ahci_probe_ent *probe_ent = + (struct ahci_probe_ent *)sata_dev_desc[dev].priv; + struct sata_fis_h2d h2d, *cfis = &h2d; + u8 port = probe_ent->hard_port_no; + + memset(cfis, 0, sizeof(struct sata_fis_h2d)); + + cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D; + cfis->pm_port_c = 0x80; /* is command */ + cfis->command = ATA_CMD_FLUSH_EXT; + + ahci_exec_ata_cmd(probe_ent, port, cfis, NULL, 0, 0); +} + +static void dwc_ahsata_init_wcache(int dev, u16 *id) +{ + struct ahci_probe_ent *probe_ent = + (struct ahci_probe_ent *)sata_dev_desc[dev].priv; + + if (ata_id_has_wcache(id) && ata_id_wcache_enabled(id)) + probe_ent->flags |= SATA_FLAG_WCACHE; + if (ata_id_has_flush(id)) + probe_ent->flags |= SATA_FLAG_FLUSH; + if (ata_id_has_flush_ext(id)) + probe_ent->flags |= SATA_FLAG_FLUSH_EXT; +} + +u32 ata_low_level_rw_lba48(int dev, u32 blknr, lbaint_t blkcnt, + void *buffer, int is_write) +{ + u32 start, blks; + u8 *addr; + int max_blks; + + start = blknr; + blks = blkcnt; + addr = (u8 *)buffer; + +#ifdef CONFIG_ARCH_MMU + max_blks = ATA_MAX_SECTORS; +#else + max_blks = ATA_MAX_SECTORS_LBA48; +#endif + + do { + if (blks > max_blks) { + if (max_blks != dwc_ahsata_rw_cmd_ext(dev, start, + max_blks, addr, is_write)) + return 0; + start += max_blks; + blks -= max_blks; + addr += ATA_SECT_SIZE * max_blks; + } else { + if (blks != dwc_ahsata_rw_cmd_ext(dev, start, + blks, addr, is_write)) + return 0; + start += blks; + blks = 0; + addr += ATA_SECT_SIZE * blks; + } + } while (blks != 0); + + return blkcnt; +} + +u32 ata_low_level_rw_lba28(int dev, u32 blknr, lbaint_t blkcnt, + void *buffer, int is_write) +{ + u32 start, blks; + u8 *addr; + int max_blks; + + start = blknr; + blks = blkcnt; + addr = (u8 *)buffer; + + max_blks = ATA_MAX_SECTORS; + do { + if (blks > max_blks) { + if (max_blks != dwc_ahsata_rw_cmd(dev, start, + max_blks, addr, is_write)) + return 0; + start += max_blks; + blks -= max_blks; + addr += ATA_SECT_SIZE * max_blks; + } else { + if (blks != dwc_ahsata_rw_cmd(dev, start, + blks, addr, is_write)) + return 0; + start += blks; + blks = 0; + addr += ATA_SECT_SIZE * blks; + } + } while (blks != 0); + + return blkcnt; +} + +/* + * SATA interface between low level driver and command layer + */ +ulong sata_read(int dev, unsigned long blknr, lbaint_t blkcnt, void *buffer) +{ + u32 rc; + + if (sata_dev_desc[dev].lba48) + rc = ata_low_level_rw_lba48(dev, blknr, blkcnt, + buffer, READ_CMD); + else + rc = ata_low_level_rw_lba28(dev, blknr, blkcnt, + buffer, READ_CMD); + return rc; +} + +ulong sata_write(int dev, unsigned long blknr, lbaint_t blkcnt, void *buffer) +{ + u32 rc; + struct ahci_probe_ent *probe_ent = + (struct ahci_probe_ent *)sata_dev_desc[dev].priv; + u32 flags = probe_ent->flags; + + if (sata_dev_desc[dev].lba48) { + rc = ata_low_level_rw_lba48(dev, blknr, blkcnt, + buffer, WRITE_CMD); + if ((flags & SATA_FLAG_WCACHE) && + (flags & SATA_FLAG_FLUSH_EXT)) + dwc_ahsata_flush_cache_ext(dev); + } else { + rc = ata_low_level_rw_lba28(dev, blknr, blkcnt, + buffer, WRITE_CMD); + if ((flags & SATA_FLAG_WCACHE) && + (flags & SATA_FLAG_FLUSH)) + dwc_ahsata_flush_cache(dev); + } + return rc; +} + +int scan_sata(int dev) +{ + u8 serial[ATA_ID_SERNO_LEN + 1] = { 0 }; + u8 firmware[ATA_ID_FW_REV_LEN + 1] = { 0 }; + u8 product[ATA_ID_PROD_LEN + 1] = { 0 }; + u16 *id; + u64 n_sectors; + struct ahci_probe_ent *probe_ent = + (struct ahci_probe_ent *)sata_dev_desc[dev].priv; + u8 port = probe_ent->hard_port_no; + block_dev_desc_t *pdev = &(sata_dev_desc[dev]); + + id = (u16 *)malloc(ATA_ID_WORDS * 2); + if (!id) { + printf("id malloc failed\n\r"); + return -1; + } + + /* Identify device to get information */ + dwc_ahsata_identify(dev, id); + + /* Serial number */ + ata_id_c_string(id, serial, ATA_ID_SERNO, sizeof(serial)); + memcpy(pdev->product, serial, sizeof(serial)); + + /* Firmware version */ + ata_id_c_string(id, firmware, ATA_ID_FW_REV, sizeof(firmware)); + memcpy(pdev->revision, firmware, sizeof(firmware)); + + /* Product model */ + ata_id_c_string(id, product, ATA_ID_PROD, sizeof(product)); + memcpy(pdev->vendor, product, sizeof(product)); + + /* Totoal sectors */ + n_sectors = ata_id_n_sectors(id); + pdev->lba = (u32)n_sectors; + + pdev->type = DEV_TYPE_HARDDISK; + pdev->blksz = ATA_SECT_SIZE; + pdev->lun = 0 ; + + /* Check if support LBA48 */ + if (ata_id_has_lba48(id)) { + pdev->lba48 = 1; + debug("Device support LBA48\n\r"); + } + + /* Get the NCQ queue depth from device */ + probe_ent->flags &= (~SATA_FLAG_Q_DEP_MASK); + probe_ent->flags |= ata_id_queue_depth(id); + + /* Get the xfer mode from device */ + dwc_ahsata_xfer_mode(dev, id); + + /* Get the write cache status from device */ + dwc_ahsata_init_wcache(dev, id); + + /* Set the xfer mode to highest speed */ + ahci_set_feature(dev, port); + + free((void *)id); + + dwc_ahsata_print_info(dev); + + is_ready = 1; + + return 0; +} + diff --git a/drivers/block/dwc_ahsata.h b/drivers/block/dwc_ahsata.h new file mode 100644 index 0000000000..4dac5dcae2 --- /dev/null +++ b/drivers/block/dwc_ahsata.h @@ -0,0 +1,333 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. + * Terry Lv + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __FSL_SATA_H__ +#define __FSL_SATA_H__ + +#define DWC_AHSATA_MAX_CMD_SLOTS 32 + +/* Max host controller numbers */ +#define SATA_HC_MAX_NUM 4 +/* Max command queue depth per host controller */ +#define DWC_AHSATA_HC_MAX_CMD 32 +/* Max port number per host controller */ +#define SATA_HC_MAX_PORT 16 + +/* Generic Host Register */ + +/* HBA Capabilities Register */ +#define SATA_HOST_CAP_S64A 0x80000000 +#define SATA_HOST_CAP_SNCQ 0x40000000 +#define SATA_HOST_CAP_SSNTF 0x20000000 +#define SATA_HOST_CAP_SMPS 0x10000000 +#define SATA_HOST_CAP_SSS 0x08000000 +#define SATA_HOST_CAP_SALP 0x04000000 +#define SATA_HOST_CAP_SAL 0x02000000 +#define SATA_HOST_CAP_SCLO 0x01000000 +#define SATA_HOST_CAP_ISS_MASK 0x00f00000 +#define SATA_HOST_CAP_ISS_OFFSET 20 +#define SATA_HOST_CAP_SNZO 0x00080000 +#define SATA_HOST_CAP_SAM 0x00040000 +#define SATA_HOST_CAP_SPM 0x00020000 +#define SATA_HOST_CAP_PMD 0x00008000 +#define SATA_HOST_CAP_SSC 0x00004000 +#define SATA_HOST_CAP_PSC 0x00002000 +#define SATA_HOST_CAP_NCS 0x00001f00 +#define SATA_HOST_CAP_CCCS 0x00000080 +#define SATA_HOST_CAP_EMS 0x00000040 +#define SATA_HOST_CAP_SXS 0x00000020 +#define SATA_HOST_CAP_NP_MASK 0x0000001f + +/* Global HBA Control Register */ +#define SATA_HOST_GHC_AE 0x80000000 +#define SATA_HOST_GHC_IE 0x00000002 +#define SATA_HOST_GHC_HR 0x00000001 + +/* Interrupt Status Register */ + +/* Ports Implemented Register */ + +/* AHCI Version Register */ +#define SATA_HOST_VS_MJR_MASK 0xffff0000 +#define SATA_HOST_VS_MJR_OFFSET 16 +#define SATA_HOST_VS_MJR_MNR 0x0000ffff + +/* Command Completion Coalescing Control */ +#define SATA_HOST_CCC_CTL_TV_MASK 0xffff0000 +#define SATA_HOST_CCC_CTL_TV_OFFSET 16 +#define SATA_HOST_CCC_CTL_CC_MASK 0x0000ff00 +#define SATA_HOST_CCC_CTL_CC_OFFSET 8 +#define SATA_HOST_CCC_CTL_INT_MASK 0x000000f8 +#define SATA_HOST_CCC_CTL_INT_OFFSET 3 +#define SATA_HOST_CCC_CTL_EN 0x00000001 + +/* Command Completion Coalescing Ports */ + +/* HBA Capabilities Extended Register */ +#define SATA_HOST_CAP2_APST 0x00000004 + +/* BIST Activate FIS Register */ +#define SATA_HOST_BISTAFR_NCP_MASK 0x0000ff00 +#define SATA_HOST_BISTAFR_NCP_OFFSET 8 +#define SATA_HOST_BISTAFR_PD_MASK 0x000000ff +#define SATA_HOST_BISTAFR_PD_OFFSET 0 + +/* BIST Control Register */ +#define SATA_HOST_BISTCR_FERLB 0x00100000 +#define SATA_HOST_BISTCR_TXO 0x00040000 +#define SATA_HOST_BISTCR_CNTCLR 0x00020000 +#define SATA_HOST_BISTCR_NEALB 0x00010000 +#define SATA_HOST_BISTCR_LLC_MASK 0x00000700 +#define SATA_HOST_BISTCR_LLC_OFFSET 8 +#define SATA_HOST_BISTCR_ERREN 0x00000040 +#define SATA_HOST_BISTCR_FLIP 0x00000020 +#define SATA_HOST_BISTCR_PV 0x00000010 +#define SATA_HOST_BISTCR_PATTERN_MASK 0x0000000f +#define SATA_HOST_BISTCR_PATTERN_OFFSET 0 + +/* BIST FIS Count Register */ + +/* BIST Status Register */ +#define SATA_HOST_BISTSR_FRAMERR_MASK 0x0000ffff +#define SATA_HOST_BISTSR_FRAMERR_OFFSET 0 +#define SATA_HOST_BISTSR_BRSTERR_MASK 0x00ff0000 +#define SATA_HOST_BISTSR_BRSTERR_OFFSET 16 + +/* BIST DWORD Error Count Register */ + +/* OOB Register*/ +#define SATA_HOST_OOBR_WE 0x80000000 +#define SATA_HOST_OOBR_cwMin_MASK 0x7f000000 +#define SATA_HOST_OOBR_cwMAX_MASK 0x00ff0000 +#define SATA_HOST_OOBR_ciMin_MASK 0x0000ff00 +#define SATA_HOST_OOBR_ciMax_MASK 0x000000ff + +/* Timer 1-ms Register */ + +/* Global Parameter 1 Register */ +#define SATA_HOST_GPARAM1R_ALIGN_M 0x80000000 +#define SATA_HOST_GPARAM1R_RX_BUFFER 0x40000000 +#define SATA_HOST_GPARAM1R_PHY_DATA_MASK 0x30000000 +#define SATA_HOST_GPARAM1R_PHY_RST 0x08000000 +#define SATA_HOST_GPARAM1R_PHY_CTRL_MASK 0x07e00000 +#define SATA_HOST_GPARAM1R_PHY_STAT_MASK 0x001f8000 +#define SATA_HOST_GPARAM1R_LATCH_M 0x00004000 +#define SATA_HOST_GPARAM1R_BIST_M 0x00002000 +#define SATA_HOST_GPARAM1R_PHY_TYPE 0x00001000 +#define SATA_HOST_GPARAM1R_RETURN_ERR 0x00000400 +#define SATA_HOST_GPARAM1R_AHB_ENDIAN_MASK 0x00000300 +#define SATA_HOST_GPARAM1R_S_HADDR 0X00000080 +#define SATA_HOST_GPARAM1R_M_HADDR 0X00000040 + +/* Global Parameter 2 Register */ +#define SATA_HOST_GPARAM2R_DEV_CP 0x00004000 +#define SATA_HOST_GPARAM2R_DEV_MP 0x00002000 +#define SATA_HOST_GPARAM2R_DEV_ENCODE_M 0x00001000 +#define SATA_HOST_GPARAM2R_RXOOB_CLK_M 0x00000800 +#define SATA_HOST_GPARAM2R_RXOOB_M 0x00000400 +#define SATA_HOST_GPARAM2R_TX_OOB_M 0x00000200 +#define SATA_HOST_GPARAM2R_RXOOB_CLK_MASK 0x000001ff + +/* Port Parameter Register */ +#define SATA_HOST_PPARAMR_TX_MEM_M 0x00000200 +#define SATA_HOST_PPARAMR_TX_MEM_S 0x00000100 +#define SATA_HOST_PPARAMR_RX_MEM_M 0x00000080 +#define SATA_HOST_PPARAMR_RX_MEM_S 0x00000040 +#define SATA_HOST_PPARAMR_TXFIFO_DEPTH_MASK 0x00000038 +#define SATA_HOST_PPARAMR_RXFIFO_DEPTH_MASK 0x00000007 + +/* Test Register */ +#define SATA_HOST_TESTR_PSEL_MASK 0x00070000 +#define SATA_HOST_TESTR_TEST_IF 0x00000001 + +/* Port Register Descriptions */ +/* Port# Command List Base Address Register */ +#define SATA_PORT_CLB_CLB_MASK 0xfffffc00 + +/* Port# Command List Base Address Upper 32-Bits Register */ + +/* Port# FIS Base Address Register */ +#define SATA_PORT_FB_FB_MASK 0xfffffff0 + +/* Port# FIS Base Address Upper 32-Bits Register */ + +/* Port# Interrupt Status Register */ +#define SATA_PORT_IS_CPDS 0x80000000 +#define SATA_PORT_IS_TFES 0x40000000 +#define SATA_PORT_IS_HBFS 0x20000000 +#define SATA_PORT_IS_HBDS 0x10000000 +#define SATA_PORT_IS_IFS 0x08000000 +#define SATA_PORT_IS_INFS 0x04000000 +#define SATA_PORT_IS_OFS 0x01000000 +#define SATA_PORT_IS_IPMS 0x00800000 +#define SATA_PORT_IS_PRCS 0x00400000 +#define SATA_PORT_IS_DMPS 0x00000080 +#define SATA_PORT_IS_PCS 0x00000040 +#define SATA_PORT_IS_DPS 0x00000020 +#define SATA_PORT_IS_UFS 0x00000010 +#define SATA_PORT_IS_SDBS 0x00000008 +#define SATA_PORT_IS_DSS 0x00000004 +#define SATA_PORT_IS_PSS 0x00000002 +#define SATA_PORT_IS_DHRS 0x00000001 + +/* Port# Interrupt Enable Register */ +#define SATA_PORT_IE_CPDE 0x80000000 +#define SATA_PORT_IE_TFEE 0x40000000 +#define SATA_PORT_IE_HBFE 0x20000000 +#define SATA_PORT_IE_HBDE 0x10000000 +#define SATA_PORT_IE_IFE 0x08000000 +#define SATA_PORT_IE_INFE 0x04000000 +#define SATA_PORT_IE_OFE 0x01000000 +#define SATA_PORT_IE_IPME 0x00800000 +#define SATA_PORT_IE_PRCE 0x00400000 +#define SATA_PORT_IE_DMPE 0x00000080 +#define SATA_PORT_IE_PCE 0x00000040 +#define SATA_PORT_IE_DPE 0x00000020 +#define SATA_PORT_IE_UFE 0x00000010 +#define SATA_PORT_IE_SDBE 0x00000008 +#define SATA_PORT_IE_DSE 0x00000004 +#define SATA_PORT_IE_PSE 0x00000002 +#define SATA_PORT_IE_DHRE 0x00000001 + +/* Port# Command Register */ +#define SATA_PORT_CMD_ICC_MASK 0xf0000000 +#define SATA_PORT_CMD_ASP 0x08000000 +#define SATA_PORT_CMD_ALPE 0x04000000 +#define SATA_PORT_CMD_DLAE 0x02000000 +#define SATA_PORT_CMD_ATAPI 0x01000000 +#define SATA_PORT_CMD_APSTE 0x00800000 +#define SATA_PORT_CMD_ESP 0x00200000 +#define SATA_PORT_CMD_CPD 0x00100000 +#define SATA_PORT_CMD_MPSP 0x00080000 +#define SATA_PORT_CMD_HPCP 0x00040000 +#define SATA_PORT_CMD_PMA 0x00020000 +#define SATA_PORT_CMD_CPS 0x00010000 +#define SATA_PORT_CMD_CR 0x00008000 +#define SATA_PORT_CMD_FR 0x00004000 +#define SATA_PORT_CMD_MPSS 0x00002000 +#define SATA_PORT_CMD_CCS_MASK 0x00001f00 +#define SATA_PORT_CMD_FRE 0x00000010 +#define SATA_PORT_CMD_CLO 0x00000008 +#define SATA_PORT_CMD_POD 0x00000004 +#define SATA_PORT_CMD_SUD 0x00000002 +#define SATA_PORT_CMD_ST 0x00000001 + +/* Port# Task File Data Register */ +#define SATA_PORT_TFD_ERR_MASK 0x0000ff00 +#define SATA_PORT_TFD_STS_MASK 0x000000ff +#define SATA_PORT_TFD_STS_ERR 0x00000001 +#define SATA_PORT_TFD_STS_DRQ 0x00000008 +#define SATA_PORT_TFD_STS_BSY 0x00000080 + +/* Port# Signature Register */ + +/* Port# Serial ATA Status {SStatus} Register */ +#define SATA_PORT_SSTS_IPM_MASK 0x00000f00 +#define SATA_PORT_SSTS_SPD_MASK 0x000000f0 +#define SATA_PORT_SSTS_DET_MASK 0x0000000f + +/* Port# Serial ATA Control {SControl} Register */ +#define SATA_PORT_SCTL_IPM_MASK 0x00000f00 +#define SATA_PORT_SCTL_SPD_MASK 0x000000f0 +#define SATA_PORT_SCTL_DET_MASK 0x0000000f + +/* Port# Serial ATA Error {SError} Register */ +#define SATA_PORT_SERR_DIAG_X 0x04000000 +#define SATA_PORT_SERR_DIAG_F 0x02000000 +#define SATA_PORT_SERR_DIAG_T 0x01000000 +#define SATA_PORT_SERR_DIAG_S 0x00800000 +#define SATA_PORT_SERR_DIAG_H 0x00400000 +#define SATA_PORT_SERR_DIAG_C 0x00200000 +#define SATA_PORT_SERR_DIAG_D 0x00100000 +#define SATA_PORT_SERR_DIAG_B 0x00080000 +#define SATA_PORT_SERR_DIAG_W 0x00040000 +#define SATA_PORT_SERR_DIAG_I 0x00020000 +#define SATA_PORT_SERR_DIAG_N 0x00010000 +#define SATA_PORT_SERR_ERR_E 0x00000800 +#define SATA_PORT_SERR_ERR_P 0x00000400 +#define SATA_PORT_SERR_ERR_C 0x00000200 +#define SATA_PORT_SERR_ERR_T 0x00000100 +#define SATA_PORT_SERR_ERR_M 0x00000002 +#define SATA_PORT_SERR_ERR_I 0x00000001 + +/* Port# Serial ATA Active {SActive} Register */ + +/* Port# Command Issue Register */ + +/* Port# Serial ATA Notification Register */ + +/* Port# DMA Control Register */ +#define SATA_PORT_DMACR_RXABL_MASK 0x0000f000 +#define SATA_PORT_DMACR_TXABL_MASK 0x00000f00 +#define SATA_PORT_DMACR_RXTS_MASK 0x000000f0 +#define SATA_PORT_DMACR_TXTS_MASK 0x0000000f + +/* Port# PHY Control Register */ + +/* Port# PHY Status Register */ + +#define SATA_HC_CMD_HDR_ENTRY_SIZE sizeof(struct cmd_hdr_entry) + +/* DW0 +*/ +#define CMD_HDR_DI_CFL_MASK 0x0000001f +#define CMD_HDR_DI_CFL_OFFSET 0 +#define CMD_HDR_DI_A 0x00000020 +#define CMD_HDR_DI_W 0x00000040 +#define CMD_HDR_DI_P 0x00000080 +#define CMD_HDR_DI_R 0x00000100 +#define CMD_HDR_DI_B 0x00000200 +#define CMD_HDR_DI_C 0x00000400 +#define CMD_HDR_DI_PMP_MASK 0x0000f000 +#define CMD_HDR_DI_PMP_OFFSET 12 +#define CMD_HDR_DI_PRDTL 0xffff0000 +#define CMD_HDR_DI_PRDTL_OFFSET 16 + +/* prde_fis_len +*/ +#define CMD_HDR_PRD_ENTRY_SHIFT 16 +#define CMD_HDR_PRD_ENTRY_MASK 0x003f0000 +#define CMD_HDR_FIS_LEN_SHIFT 2 + +/* attribute +*/ +#define CMD_HDR_ATTR_RES 0x00000800 /* Reserved bit, should be 1 */ +#define CMD_HDR_ATTR_VBIST 0x00000400 /* Vendor BIST */ +/* Snoop enable for all descriptor */ +#define CMD_HDR_ATTR_SNOOP 0x00000200 +#define CMD_HDR_ATTR_FPDMA 0x00000100 /* FPDMA queued command */ +#define CMD_HDR_ATTR_RESET 0x00000080 /* Reset - a SRST or device reset */ +/* BIST - require the host to enter BIST mode */ +#define CMD_HDR_ATTR_BIST 0x00000040 +#define CMD_HDR_ATTR_ATAPI 0x00000020 /* ATAPI command */ +#define CMD_HDR_ATTR_TAG 0x0000001f /* TAG mask */ + +#define FLAGS_DMA 0x00000000 +#define FLAGS_FPDMA 0x00000001 + +#define SATA_FLAG_Q_DEP_MASK 0x0000000f +#define SATA_FLAG_WCACHE 0x00000100 +#define SATA_FLAG_FLUSH 0x00000200 +#define SATA_FLAG_FLUSH_EXT 0x00000400 + +#define READ_CMD 0 +#define WRITE_CMD 1 + +#endif /* __FSL_SATA_H__ */ diff --git a/drivers/block/mxc_ata.c b/drivers/block/mxc_ata.c new file mode 100644 index 0000000000..aed7476219 --- /dev/null +++ b/drivers/block/mxc_ata.c @@ -0,0 +1,454 @@ +/* + * (C) Copyright 2008-2009 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include "mxc_ata.h" + +#include +#include +#include +#include +#include +#include + +extern block_dev_desc_t pata_dev_desc[CONFIG_SYS_ATA_MAX_DEVICE]; +extern void setup_ata(void); + +struct mxc_ata_time_regs { + u8 time_off, time_on, time_1, time_2w; + u8 time_2r, time_ax, time_pio_rdx, time_4; + u8 time_9, time_m, time_jn, time_d; + u8 time_k, time_ack, time_env, time_rpx; + u8 time_zah, time_mlix, time_dvh, time_dzfs; + u8 time_dvs, time_cvh, time_ss, time_cyc; +}; + +/* + * This structure contains the timing parameters for + * ATA bus timing in the 5 PIO modes. The timings + * are in nanoseconds, and are converted to clock + * cycles before being stored in the ATA controller + * timing registers. + */ +static struct { + s16 t0, t1, t2_8, t2_16, t2i, t4, t9, tA; +} pio_specs[] = { + [0] = { + .t0 = 600, .t1 = 70, .t2_8 = 290, .t2_16 = 165, .t2i = 40, .t4 = + 30, .t9 = 20, .tA = 50,}, + [1] = { + .t0 = 383, .t1 = 50, .t2_8 = 290, .t2_16 = 125, .t2i = 0, .t4 = + 20, .t9 = 15, .tA = 50,}, + [2] = { + .t0 = 240, .t1 = 30, .t2_8 = 290, .t2_16 = 100, .t2i = 0, .t4 = + 15, .t9 = 10, .tA = 50,}, + [3] = { + .t0 = 180, .t1 = 30, .t2_8 = 80, .t2_16 = 80, .t2i = 0, .t4 = + 10, .t9 = 10, .tA = 50,}, + [4] = { + .t0 = 120, .t1 = 25, .t2_8 = 70, .t2_16 = 70, .t2i = 0, .t4 = + 10, .t9 = 10, .tA = 50,}, + }; + +#define NR_PIO_SPECS (sizeof(pio_specs) / sizeof(pio_specs[0])) + +static inline void mdelay(u32 msec) +{ + u32 i; + for (i = 0; i < msec; i++) + udelay(1000); +} + +static inline void sdelay(u32 sec) +{ + u32 i; + for (i = 0; i < sec; i++) + mdelay(1000); +} + +void dprint_buffer(u8 *buf, s32 len) +{ + s32 i, j; + + i = 0; + j = 0; + printf("\n\r"); + + for (i = 0; i < len; i++) { + printf("%02x ", *buf++); + j++; + if (j == 16) { + printf("\n\r"); + j = 0; + } + } + printf("\n\r"); +} + + +static void update_timing_config(struct mxc_ata_time_regs *tp) +{ + u32 *lp = (u32 *)tp; + u32 *ctlp = (u32 *) ATA_BASE_ADDR; + s32 i; + + for (i = 0; i < 5; ++i) { + writel(*lp, ctlp); + lp++; + ctlp++; + } +} + +static void set_ata_bus_timing(u8 xfer_mode) +{ + s32 speed = xfer_mode; + struct mxc_ata_time_regs tr = { 0 }; + s32 T = 1 * 1000 * 1000 * 1000 / mxc_get_clock(MXC_IPG_CLK); + + if (speed >= NR_PIO_SPECS) + return; + + tr.time_off = 3; + tr.time_on = 3; + + tr.time_1 = (pio_specs[speed].t1 + T) / T; + tr.time_2w = (pio_specs[speed].t2_8 + T) / T; + + tr.time_2r = (pio_specs[speed].t2_8 + T) / T; + tr.time_ax = (pio_specs[speed].tA + T) / T + 2; + tr.time_pio_rdx = 1; + tr.time_4 = (pio_specs[speed].t4 + T) / T; + + tr.time_9 = (pio_specs[speed].t9 + T) / T; + + update_timing_config(&tr); +} + +static u8 ata_sff_busy_wait(u32 bits, u32 max, u32 delay) +{ + u8 status; + u32 iterations = 1; + + if (max != 0) + iterations = max; + + do { + udelay(delay); + status = readb(CONFIG_SYS_ATA_BASE_ADDR + MXC_ATA_DCDR); + if (max != 0) + iterations--; + } while (status != 0xff && (status & bits) && (iterations > 0)); + + if (iterations == 0) { + printf("ata_sff_busy_wait timeout status = %x\n", status); + return 0xff; + } + + return status; +} + +static void ata_sff_exec_command(u16 cmd) +{ + writeb(cmd, CONFIG_SYS_ATA_BASE_ADDR + MXC_ATA_DCDR); + readb(CONFIG_SYS_ATA_BASE_ADDR + MXC_ATA_DRIVE_CONTROL); + udelay(4); +} + +static s32 ata_identify(int dev, u16 *id) +{ + int i; + int CIS[256] = { 0 }; + + ata_sff_exec_command(ATA_CMD_ID_ATA); + if (ata_sff_busy_wait(ATA_BUSY, 5000, 500) == 0xff) + return -1; + + for (i = 0 ; i < 256; ++i) + id[i] = (u16)readw(CONFIG_SYS_ATA_BASE_ADDR + MXC_ATA_DRIVE_DATA); + + ata_swap_buf_le16(id, ATA_ID_WORDS); + + return 0; +} + +static s32 ata_dev_set_feature(int dev, u32 feature) +{ + u8 status; + + writeb(feature, CONFIG_SYS_ATA_BASE_ADDR + MXC_ATA_DFTR); + /* Issue Set feature command */ + ata_sff_exec_command(ATA_CMD_SET_FEATURES); + status = ata_sff_busy_wait(ATA_BUSY, 5000, 500); + + if (status == 0xff) + return 1; + if (status & ATA_ERR) + return 1; + + return 0; +} + +static void write_sector_pio(u32 *addr, s32 num_of_sectors) +{ + int i, j; + + for (i = 0; i < num_of_sectors; i++) { + for (j = 0; j < ATA_SECTOR_SIZE; j = j + 4) { + /* Write 4 bytes in each iteration */ + writew((*addr & 0xFFFF), + ATA_BASE_ADDR + MXC_ATA_DRIVE_DATA) ; + writew(((*addr >> 16) & 0xFFFF), + ATA_BASE_ADDR + MXC_ATA_DRIVE_DATA) ; + addr++; + } + ata_sff_busy_wait(ATA_BUSY, 5000, 50); + } + readb(CONFIG_SYS_ATA_BASE_ADDR + MXC_ATA_DRIVE_CONTROL); +} + +static void read_sector_pio(u32 *addr, s32 num_of_sectors) +{ + int i, j; + u32 data[2]; + + for (i = 0; i < num_of_sectors; i++) { + for (j = 0; j < ATA_SECTOR_SIZE; j = j + 4) { + /* Read 4 bytes in each iteration */ + data[0] = readw(CONFIG_SYS_ATA_BASE_ADDR + MXC_ATA_DRIVE_DATA); + data[1] = readw(CONFIG_SYS_ATA_BASE_ADDR + MXC_ATA_DRIVE_DATA); + *addr = ((data[1] << 16) & 0xFFFF0000) | \ + (data[0] & 0xFFFF); + addr++; + } + ata_sff_busy_wait(ATA_BUSY, 5000, 10); + } + readb(CONFIG_SYS_ATA_BASE_ADDR + MXC_ATA_DRIVE_CONTROL); +} + +static s32 mxc_pata_reset(int dev) +{ + setup_ata(); + + /* Deassert the reset bit to enable the interface */ + writel(MXC_ATA_CTRL_ATA_RST_B, \ + CONFIG_SYS_ATA_BASE_ADDR + MXC_ATA_CONTROL); + writel(MXC_ATA_CTRL_ATA_RST_B | MXC_ATA_CTRL_FIFO_RST_B, \ + CONFIG_SYS_ATA_BASE_ADDR + MXC_ATA_CONTROL); + /* Set initial timing and mode */ + set_ata_bus_timing(PIO_XFER_MODE_4); + /* set fifo alarm to 20 halfwords, midway */ + writeb(20, CONFIG_SYS_ATA_BASE_ADDR + MXC_ATA_FIFO_ALARM); + + /* software reset */ + writeb(ATA_NIEN, \ + CONFIG_SYS_ATA_BASE_ADDR + MXC_ATA_DRIVE_CONTROL); + udelay(20); + writeb(ATA_NIEN | ATA_SRST, \ + CONFIG_SYS_ATA_BASE_ADDR + MXC_ATA_DRIVE_CONTROL); + udelay(20); + writeb(ATA_NIEN, \ + CONFIG_SYS_ATA_BASE_ADDR + MXC_ATA_DRIVE_CONTROL); + + writeb(0, CONFIG_SYS_ATA_BASE_ADDR + MXC_ATA_DDHR); + + if (ata_sff_busy_wait(ATA_BUSY | ATA_DRQ, \ + 6000, 1000) == 0xff) { + puts("Failed to initialize the ATA drive\n"); + return -1; + } + + return 0; +} + +/* + * PATA interface between low level driver and command layer + */ +int init_pata(int dev) +{ + if (dev < 0 || dev > (CONFIG_SYS_ATA_MAX_DEVICE - 1)) { + printf("the pata index %d is out of ranges\n\r", dev); + return -1; + } + + return mxc_pata_reset(dev); +} + +ulong pata_read(int dev, ulong blknr, ulong blkcnt, void *buffer) +{ + u8 lba_addr[4] = { 0 }; + u32 num_of_sectors = 0; + u8 status = 0; + u32 total_blks = blkcnt; + + while (blkcnt > 0) { + lba_addr[0] = blknr & 0xFF; + lba_addr[1] = (blknr >> 8) & 0xFF; + lba_addr[2] = (blknr >> 16) & 0xFF; + /* Enable the LBA bit */ + lba_addr[3] = (1 << 6) | ((blknr >> 24) & 0xF); + + if (blkcnt >= MAX_SECTORS) + num_of_sectors = 0; + else + num_of_sectors = blkcnt; + + ata_sff_busy_wait(ATA_BUSY | ATA_DRQ, 5000, 50); + writeb(num_of_sectors, CONFIG_SYS_ATA_BASE_ADDR + MXC_ATA_DSCR); + writeb(lba_addr[0], CONFIG_SYS_ATA_BASE_ADDR + MXC_ATA_DSNR); + writeb(lba_addr[1], CONFIG_SYS_ATA_BASE_ADDR + MXC_ATA_DCLR); + writeb(lba_addr[2], CONFIG_SYS_ATA_BASE_ADDR + MXC_ATA_DCHR); + writeb(lba_addr[3], CONFIG_SYS_ATA_BASE_ADDR + MXC_ATA_DDHR); + + /* Issue Read command */ + ata_sff_exec_command(ATA_CMD_PIO_READ); + status = ata_sff_busy_wait(ATA_BUSY, 5000, 50); + if (status & ATA_ERR) { + puts("Error while issuing ATA Read command\n"); + return -1; + } + if (num_of_sectors == 0) { + read_sector_pio((u32 *)buffer, MAX_SECTORS); + blkcnt -= MAX_SECTORS; + blknr += MAX_SECTORS; + buffer += (MAX_SECTORS * ATA_SECTOR_SIZE); + } else { + read_sector_pio((u32 *)buffer, num_of_sectors); + blkcnt -= num_of_sectors; + blknr += num_of_sectors; + buffer += (num_of_sectors * ATA_SECTOR_SIZE); + } + } + + return total_blks; +} + +ulong pata_write(int dev, ulong blknr, ulong blkcnt, const void *buffer) +{ + s32 lba_addr[4] = { 0 }, + num_of_sectors = 0; + u8 status = 0; + u32 total_blks = blkcnt; + + while (blkcnt > 0) { + lba_addr[0] = blknr & 0xFF; + lba_addr[1] = (blknr >> 8) & 0xFF; + lba_addr[2] = (blknr >> 16) & 0xFF; + /* Enable the LBA bit */ + lba_addr[3] = (1 << 6) | ((blknr >> 24) & 0xF); + + if (blkcnt >= MAX_SECTORS) + num_of_sectors = 0; + else + num_of_sectors = blkcnt; + + ata_sff_busy_wait(ATA_BUSY | ATA_DRQ, 5000, 50); + writeb(num_of_sectors, CONFIG_SYS_ATA_BASE_ADDR + MXC_ATA_DSCR); + writeb(lba_addr[0], CONFIG_SYS_ATA_BASE_ADDR + MXC_ATA_DSNR); + writeb(lba_addr[1], CONFIG_SYS_ATA_BASE_ADDR + MXC_ATA_DCLR); + writeb(lba_addr[2], CONFIG_SYS_ATA_BASE_ADDR + MXC_ATA_DCHR); + writeb(lba_addr[3], CONFIG_SYS_ATA_BASE_ADDR + MXC_ATA_DDHR); + + /* Issue Write command */ + ata_sff_exec_command(ATA_CMD_PIO_WRITE); + ata_sff_busy_wait(ATA_BUSY, 5000, 50); + if (status & ATA_ERR) { + puts("Error while issuing ATA Write command\n"); + return -1; + } + if (num_of_sectors == 0) { + write_sector_pio((u32 *)buffer, MAX_SECTORS); + blkcnt -= MAX_SECTORS; + blknr += MAX_SECTORS; + buffer += (MAX_SECTORS * ATA_SECTOR_SIZE); + } else { + write_sector_pio((u32 *)buffer, num_of_sectors); + blkcnt -= num_of_sectors; + blknr += num_of_sectors; + buffer += (num_of_sectors * ATA_SECTOR_SIZE); + } + } + + return total_blks; +} + +int scan_pata(int dev) +{ + u8 serial[ATA_ID_SERNO_LEN + 1]; + u8 firmware[ATA_ID_FW_REV_LEN + 1]; + u8 product[ATA_ID_PROD_LEN + 1]; + u16 *id; + u64 n_sectors; + + id = (u16 *)malloc(ATA_ID_WORDS * 2); + if (!id) { + printf("id malloc failed\n\r"); + return -1; + } + +retry: + /* Identify device to get information */ + ata_identify(dev, id); + + if (ata_id_is_ata(id)) { + if ((id[2] == 0x37c8 || id[2] == 0x738c)) { + s32 err_mask = 0; + + err_mask = ata_dev_set_feature(dev, SETFEATURES_SPINUP); + if (err_mask && id[2] != 0x738c) { + puts("ATA SPINUP Failed \n"); + return -1; + } + if (id[2] == 0x37c8) + goto retry; + } + } else { + puts("ATA IDENTIFY DEVICE command Failed \n"); + } + + /* Serial number */ + ata_id_c_string(id, serial, ATA_ID_SERNO, sizeof(serial)); + memcpy(pata_dev_desc[dev].product, serial, sizeof(serial)); + + /* Firmware version */ + ata_id_c_string(id, firmware, ATA_ID_FW_REV, sizeof(firmware)); + memcpy(pata_dev_desc[dev].revision, firmware, sizeof(firmware)); + + /* Product model */ + ata_id_c_string(id, product, ATA_ID_PROD, sizeof(product)); + memcpy(pata_dev_desc[dev].vendor, product, sizeof(product)); + + /* Totoal sectors */ + n_sectors = ata_id_n_sectors(id); + pata_dev_desc[dev].lba = (u32)n_sectors; + + /* Check if support LBA48 */ + if (ata_id_has_lba48(id)) { + pata_dev_desc[dev].lba48 = 1; + debug("Device support LBA48\n\r"); + } + +#ifdef DEBUG + fsl_pata_identify(dev, id); + ata_dump_id(id); +#endif + free((void *)id); + return 0; +} diff --git a/drivers/block/mxc_ata.h b/drivers/block/mxc_ata.h new file mode 100644 index 0000000000..5d198f1247 --- /dev/null +++ b/drivers/block/mxc_ata.h @@ -0,0 +1,90 @@ +#ifndef _MXC_ATA_H_ +#define _MXC_ATA_H_ + +/* + * (C) Copyright 2008-2009 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#define MXC_ATA_TIMING_REGS 0x00 +#define MXC_ATA_FIFO_FILL 0x20 +#define MXC_ATA_CONTROL 0x24 +#define MXC_ATA_INT_PEND 0x28 +#define MXC_ATA_INT_EN 0x2C +#define MXC_ATA_INT_CLEAR 0x30 +#define MXC_ATA_FIFO_ALARM 0x34 +#define MXC_ATA_ADMA_ERROR_STATUS 0x38 +#define MXC_ATA_SYS_DMA_BADDR 0x3C +#define MXC_ATA_ADMA_SYS_ADDR 0x40 +#define MXC_ATA_BLOCK_COUNT 0x48 +#define MXC_ATA_BURST_LENGTH 0x4C +#define MXC_ATA_SECTOR_SIZE 0x50 +#define MXC_ATA_DRIVE_DATA 0xA0 +#define MXC_ATA_DFTR 0xA4 +#define MXC_ATA_DSCR 0xA8 +#define MXC_ATA_DSNR 0xAC +#define MXC_ATA_DCLR 0xB0 +#define MXC_ATA_DCHR 0xB4 +#define MXC_ATA_DDHR 0xB8 +#define MXC_ATA_DCDR 0xBC +#define MXC_ATA_DRIVE_CONTROL 0xD8 + +/* bits within MXC_ATA_CONTROL */ +#define MXC_ATA_CTRL_DMA_SRST 0x1000 +#define MXC_ATA_CTRL_DMA_64ADMA 0x800 +#define MXC_ATA_CTRL_DMA_32ADMA 0x400 +#define MXC_ATA_CTRL_DMA_STAT_STOP 0x200 +#define MXC_ATA_CTRL_DMA_ENABLE 0x100 +#define MXC_ATA_CTRL_FIFO_RST_B 0x80 +#define MXC_ATA_CTRL_ATA_RST_B 0x40 +#define MXC_ATA_CTRL_FIFO_TX_EN 0x20 +#define MXC_ATA_CTRL_FIFO_RCV_EN 0x10 +#define MXC_ATA_CTRL_DMA_PENDING 0x08 +#define MXC_ATA_CTRL_DMA_ULTRA 0x04 +#define MXC_ATA_CTRL_DMA_WRITE 0x02 +#define MXC_ATA_CTRL_IORDY_EN 0x01 + +/* bits within the interrupt control registers */ +#define MXC_ATA_INTR_ATA_INTRQ1 0x80 +#define MXC_ATA_INTR_FIFO_UNDERFLOW 0x40 +#define MXC_ATA_INTR_FIFO_OVERFLOW 0x20 +#define MXC_ATA_INTR_CTRL_IDLE 0x10 +#define MXC_ATA_INTR_ATA_INTRQ2 0x08 +#define MXC_ATA_INTR_DMA_ERR 0x04 +#define MXC_ATA_INTR_DMA_TRANS_OVER 0x02 + +/* ADMA Addr Descriptor Attribute Filed */ +#define MXC_ADMA_DES_ATTR_VALID 0x01 +#define MXC_ADMA_DES_ATTR_END 0x02 +#define MXC_ADMA_DES_ATTR_INT 0x04 +#define MXC_ADMA_DES_ATTR_SET 0x10 +#define MXC_ADMA_DES_ATTR_TRAN 0x20 +#define MXC_ADMA_DES_ATTR_LINK 0x30 + +#define PIO_XFER_MODE_0 0 +#define PIO_XFER_MODE_1 1 +#define PIO_XFER_MODE_2 2 +#define PIO_XFER_MODE_3 3 +#define PIO_XFER_MODE_4 4 + +#define ATA_SECTOR_SIZE 512 +#define MAX_SECTORS 256 + +#endif /* _IMX_ATA_H_ */ diff --git a/drivers/i2c/mxc_i2c.c b/drivers/i2c/mxc_i2c.c index 8e10fbb21c..4c402c9995 100644 --- a/drivers/i2c/mxc_i2c.c +++ b/drivers/i2c/mxc_i2c.c @@ -3,6 +3,8 @@ * * (c) 2007 Pengutronix, Sascha Hauer * + * (C) Copyright 2008-2010 Freescale Semiconductor, Inc. + * * See file CREDITS for list of people who contributed to this * project. * @@ -26,9 +28,6 @@ #if defined(CONFIG_HARD_I2C) -#include -#include - #define IADR 0x00 #define IFDR 0x04 #define I2CR 0x08 @@ -47,19 +46,17 @@ #define I2SR_IIF (1 << 1) #define I2SR_RX_NO_AK (1 << 0) -#ifdef CONFIG_SYS_I2C_MX31_PORT1 -#define I2C_BASE 0x43f80000 -#define I2C_CLK_OFFSET 26 -#elif defined (CONFIG_SYS_I2C_MX31_PORT2) -#define I2C_BASE 0x43f98000 -#define I2C_CLK_OFFSET 28 -#elif defined (CONFIG_SYS_I2C_MX31_PORT3) -#define I2C_BASE 0x43f84000 -#define I2C_CLK_OFFSET 30 +#ifdef CONFIG_SYS_I2C_PORT +# define I2C_BASE CONFIG_SYS_I2C_PORT #else -#error "define CONFIG_SYS_I2C_MX31_PORTx to use the mx31 I2C driver" +# error "define CONFIG_SYS_I2C_PORT(I2C base address) to use the I2C driver" #endif +#define I2C_MAX_TIMEOUT 100000 +#define I2C_TIMEOUT_TICKET 1 + +#undef DEBUG + #ifdef DEBUG #define DPRINTF(args...) printf(args) #else @@ -67,36 +64,77 @@ #endif static u16 div[] = { 30, 32, 36, 42, 48, 52, 60, 72, 80, 88, 104, 128, 144, - 160, 192, 240, 288, 320, 384, 480, 576, 640, 768, 960, - 1152, 1280, 1536, 1920, 2304, 2560, 3072, 3840}; + 160, 192, 240, 288, 320, 384, 480, 576, 640, 768, 960, + 1152, 1280, 1536, 1920, 2304, 2560, 3072, 3840 +}; + +static inline void i2c_reset(void) +{ + __REG16(I2C_BASE + I2CR) = 0; /* Reset module */ + __REG16(I2C_BASE + I2SR) = 0; + __REG16(I2C_BASE + I2CR) = I2CR_IEN; +} void i2c_init(int speed, int unused) { - int freq = mx31_get_ipg_clk(); + int freq; int i; - /* start the required I2C clock */ - __REG(CCM_CGR0) = __REG(CCM_CGR0) | (3 << I2C_CLK_OFFSET); - +#ifdef CONFIG_MX31 + freq = mx31_get_ipg_clk(); +#else + freq = mxc_get_clock(MXC_IPG_PERCLK); +#endif for (i = 0; i < 0x1f; i++) if (freq / div[i] <= speed) break; - DPRINTF("%s: speed: %d\n",__FUNCTION__, speed); + DPRINTF("%s: root clock: %d, speed: %d div: %x\n", + __func__, freq, speed, i); - __REG16(I2C_BASE + I2CR) = 0; /* Reset module */ __REG16(I2C_BASE + IFDR) = i; - __REG16(I2C_BASE + I2CR) = I2CR_IEN; - __REG16(I2C_BASE + I2SR) = 0; + i2c_reset(); +} + +static int wait_idle(void) +{ + int timeout = I2C_MAX_TIMEOUT; + + while ((__REG16(I2C_BASE + I2SR) & I2SR_IBB) && --timeout) { + __REG16(I2C_BASE + I2SR) = 0; + udelay(I2C_TIMEOUT_TICKET); + } + DPRINTF("%s:%x\n", __func__, __REG16(I2C_BASE + I2SR)); + return timeout ? timeout : (!(__REG16(I2C_BASE + I2SR) & I2SR_IBB)); } static int wait_busy(void) { - int timeout = 10000; + int timeout = I2C_MAX_TIMEOUT; - while (!(__REG16(I2C_BASE + I2SR) & I2SR_IIF) && --timeout) - udelay(1); - __REG16(I2C_BASE + I2SR) = 0; /* clear interrupt */ + while ((!(__REG16(I2C_BASE + I2SR) & I2SR_IBB) && (--timeout))) { + __REG16(I2C_BASE + I2SR) = 0; + udelay(I2C_TIMEOUT_TICKET); + } + return timeout ? timeout : (__REG16(I2C_BASE + I2SR) & I2SR_IBB); +} + +static int wait_complete(void) +{ + int timeout = I2C_MAX_TIMEOUT; + + while ((!(__REG16(I2C_BASE + I2SR) & I2SR_ICF)) && (--timeout)) { + __REG16(I2C_BASE + I2SR) = 0; + udelay(I2C_TIMEOUT_TICKET); + } + DPRINTF("%s:%x\n", __func__, __REG16(I2C_BASE + I2SR)); + { + int i; + for (i = 0; i < 200; i++) + udelay(10); + + } + __REG16(I2C_BASE + I2SR) = 0; /* clear interrupt */ return timeout; } @@ -105,90 +143,133 @@ static int tx_byte(u8 byte) { __REG16(I2C_BASE + I2DR) = byte; - if (!wait_busy() || __REG16(I2C_BASE + I2SR) & I2SR_RX_NO_AK) + if (!wait_complete() || __REG16(I2C_BASE + I2SR) & I2SR_RX_NO_AK) { + DPRINTF("%s:%x <= %x\n", __func__, __REG16(I2C_BASE + I2SR), + byte); return -1; + } + DPRINTF("%s:%x\n", __func__, byte); return 0; } -static int rx_byte(void) +static int rx_byte(u32 *pdata, int last) { - if (!wait_busy()) + if (!wait_complete()) return -1; - return __REG16(I2C_BASE + I2DR); + if (last) + __REG16(I2C_BASE + I2CR) = I2CR_IEN; + + *pdata = __REG16(I2C_BASE + I2DR); + DPRINTF("%s:%x\n", __func__, *pdata); + return 0; } int i2c_probe(uchar chip) { int ret; - __REG16(I2C_BASE + I2CR) = 0; /* Reset module */ + __REG16(I2C_BASE + I2CR) = 0; /* Reset module */ __REG16(I2C_BASE + I2CR) = I2CR_IEN; - - __REG16(I2C_BASE + I2CR) = I2CR_IEN | I2CR_MSTA | I2CR_MTX; + for (ret = 0; ret < 1000; ret++) + udelay(1); + __REG16(I2C_BASE + I2CR) = I2CR_IEN | I2CR_MSTA | I2CR_MTX; ret = tx_byte(chip << 1); - __REG16(I2C_BASE + I2CR) = I2CR_IEN | I2CR_MTX; + __REG16(I2C_BASE + I2CR) = I2CR_IEN; return ret; } static int i2c_addr(uchar chip, uint addr, int alen) { - __REG16(I2C_BASE + I2SR) = 0; /* clear interrupt */ - __REG16(I2C_BASE + I2CR) = I2CR_IEN | I2CR_MSTA | I2CR_MTX; - - if (tx_byte(chip << 1)) + int i, retry = 0; + for (retry = 0; retry < 3; retry++) { + if (wait_idle()) + break; + i2c_reset(); + for (i = 0; i < I2C_MAX_TIMEOUT; i++) + udelay(I2C_TIMEOUT_TICKET); + } + if (retry >= 3) { + printf("%s:bus is busy(%x)\n", + __func__, __REG16(I2C_BASE + I2SR)); return -1; - + } + __REG16(I2C_BASE + I2CR) = I2CR_IEN | I2CR_MSTA | I2CR_MTX; + if (!wait_busy()) { + printf("%s:trigger start fail(%x)\n", + __func__, __REG16(I2C_BASE + I2SR)); + return -1; + } + if (tx_byte(chip << 1) || (__REG16(I2C_BASE + I2SR) & I2SR_RX_NO_AK)) { + printf("%s:chip address cycle fail(%x)\n", + __func__, __REG16(I2C_BASE + I2SR)); + return -1; + } while (alen--) - if (tx_byte((addr >> (alen * 8)) & 0xff)) + if (tx_byte((addr >> (alen * 8)) & 0xff) || + (__REG16(I2C_BASE + I2SR) & I2SR_RX_NO_AK)) { + printf("%s:device address cycle fail(%x)\n", + __func__, __REG16(I2C_BASE + I2SR)); return -1; + } return 0; } int i2c_read(uchar chip, uint addr, int alen, uchar *buf, int len) { - int timeout = 10000; - int ret; + int timeout = I2C_MAX_TIMEOUT; + uint ret; - DPRINTF("%s chip: 0x%02x addr: 0x%04x alen: %d len: %d\n",__FUNCTION__, chip, addr, alen, len); + DPRINTF("%s chip: 0x%02x addr: 0x%04x alen: %d len: %d\n", + __func__, chip, addr, alen, len); if (i2c_addr(chip, addr, alen)) { printf("i2c_addr failed\n"); return -1; } - __REG16(I2C_BASE + I2CR) = I2CR_IEN | I2CR_MSTA | I2CR_MTX | I2CR_RSTA; + __REG16(I2C_BASE + I2CR) = I2CR_IEN | I2CR_MSTA | I2CR_MTX | I2CR_RSTA; - if (tx_byte(chip << 1 | 1)) + if (tx_byte(chip << 1 | 1) || + (__REG16(I2C_BASE + I2SR) & I2SR_RX_NO_AK)) { + printf("%s:Send 2th chip address fail(%x)\n", + __func__, __REG16(I2C_BASE + I2SR)); return -1; - - __REG16(I2C_BASE + I2CR) = I2CR_IEN | I2CR_MSTA | ((len == 1) ? I2CR_TX_NO_AK : 0); - + } + __REG16(I2C_BASE + I2CR) = I2CR_IEN | I2CR_MSTA | + ((len == 1) ? I2CR_TX_NO_AK : 0); + DPRINTF("CR=%x\n", __REG16(I2C_BASE + I2CR)); ret = __REG16(I2C_BASE + I2DR); while (len--) { - if ((ret = rx_byte()) < 0) + if (len == 0) + __REG16(I2C_BASE + I2CR) = I2CR_IEN | I2CR_MSTA | + I2CR_TX_NO_AK; + + if (rx_byte(&ret, len == 0) < 0) { + printf("Read: rx_byte fail\n"); return -1; + } *buf++ = ret; - if (len <= 1) - __REG16(I2C_BASE + I2CR) = I2CR_IEN | I2CR_MSTA | I2CR_TX_NO_AK; } - wait_busy(); - - __REG16(I2C_BASE + I2CR) = I2CR_IEN; - - while (__REG16(I2C_BASE + I2SR) & I2SR_IBB && --timeout) - udelay(1); - + while (__REG16(I2C_BASE + I2SR) & I2SR_IBB && --timeout) { + __REG16(I2C_BASE + I2SR) = 0; + udelay(I2C_TIMEOUT_TICKET); + } + if (!timeout) { + printf("%s:trigger stop fail(%x)\n", + __func__, __REG16(I2C_BASE + I2SR)); + } return 0; } int i2c_write(uchar chip, uint addr, int alen, uchar *buf, int len) { - int timeout = 10000; - DPRINTF("%s chip: 0x%02x addr: 0x%04x alen: %d len: %d\n",__FUNCTION__, chip, addr, alen, len); + int timeout = I2C_MAX_TIMEOUT; + DPRINTF("%s chip: 0x%02x addr: 0x%04x alen: %d len: %d\n", + __func__, chip, addr, alen, len); if (i2c_addr(chip, addr, alen)) return -1; @@ -200,9 +281,9 @@ int i2c_write(uchar chip, uint addr, int alen, uchar *buf, int len) __REG16(I2C_BASE + I2CR) = I2CR_IEN; while (__REG16(I2C_BASE + I2SR) & I2SR_IBB && --timeout) - udelay(1); + udelay(I2C_TIMEOUT_TICKET); return 0; } -#endif /* CONFIG_HARD_I2C */ +#endif /* CONFIG_HARD_I2C */ diff --git a/drivers/input/Makefile b/drivers/input/Makefile index 9a14407399..fcf96430ef 100644 --- a/drivers/input/Makefile +++ b/drivers/input/Makefile @@ -30,6 +30,7 @@ ifdef CONFIG_PS2KBD COBJS-y += keyboard.o pc_keyb.o COBJS-$(CONFIG_PS2MULT) += ps2mult.o ps2ser.o endif +COBJS-${CONFIG_MXC_KPD} += mxc_keyb.o COBJS := $(COBJS-y) SRCS := $(COBJS:.o=.c) diff --git a/drivers/input/mxc_keyb.c b/drivers/input/mxc_keyb.c new file mode 100644 index 0000000000..ec65ab5c77 --- /dev/null +++ b/drivers/input/mxc_keyb.c @@ -0,0 +1,598 @@ +/* + * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file mxc_keyb.c + * + * @brief Driver for the Freescale Semiconductor MXC keypad port. + * + * The keypad driver is designed as a standard Input driver which interacts + * with low level keypad port hardware. Upon opening, the Keypad driver + * initializes the keypad port. When the keypad interrupt happens the driver + * calles keypad polling timer and scans the keypad matrix for key + * press/release. If all key press/release happened it comes out of timer and + * waits for key press interrupt. The scancode for key press and release events + * are passed to Input subsytem. + * + * @ingroup keypad + */ + +#include +#include +#include +#include +#include +#include + +/* + * * Module header file + * */ +#include + +/*! + * Comment KPP_DEBUG to disable debug messages + */ + +#undef KPP_DEBUG + +#ifdef KPP_DEBUG +#define KPP_PRINTF(fmt, args...) printf(fmt , ##args) + +static void mxc_kpp_dump_regs() +{ + unsigned short t1, t2, t3; + + t1 = __raw_readw(KPCR); + t2 = __raw_readw(KPSR); + t3 = __raw_readw(KDDR); + /* + KPP_PRINTF("KPCR=0x%04x, KPSR=0x%04x, KDDR=0x%04x\n", + t1, t2, t3); + */ +} +#else +#define KPP_PRINTF(fmt, args...) +#endif + +static u16 mxc_key_mapping[] = CONFIG_MXC_KEYMAPPING; + +/*! + * This structure holds the keypad private data structure. + */ +static struct keypad_priv kpp_dev; + +/*! Indicates if the key pad device is enabled. */ + +/*! This static variable indicates whether a key event is pressed/released. */ +static unsigned short KPress; + +/*! cur_rcmap and prev_rcmap array is used to detect key press and release. */ +static unsigned short *cur_rcmap; /* max 64 bits (8x8 matrix) */ +static unsigned short *prev_rcmap; + +/*! + * Debounce polling period(10ms) in system ticks. + */ +static unsigned short KScanRate = (10 * CONFIG_SYS_HZ) / 1000; + +/*! + * These arrays are used to store press and release scancodes. + */ +static short **press_scancode; +static short **release_scancode; + +static const unsigned short *mxckpd_keycodes; +static unsigned short mxckpd_keycodes_size; + +/*! + * These functions are used to configure and the GPIO pins for keypad to + * activate and deactivate it. + */ +extern void setup_mxc_kpd(void); + +/*! + * This function is called to scan the keypad matrix to find out the key press + * and key release events. Make scancode and break scancode are generated for + * key press and key release events. + * + * The following scanning sequence are done for + * keypad row and column scanning, + * -# Write 1's to KPDR[15:8], setting column data to 1's + * -# Configure columns as totem pole outputs(for quick discharging of keypad + * capacitance) + * -# Configure columns as open-drain + * -# Write a single column to 0, others to 1. + * -# Sample row inputs and save data. Multiple key presses can be detected on + * a single column. + * -# Repeat steps the above steps for remaining columns. + * -# Return all columns to 0 in preparation for standby mode. + * -# Clear KPKD and KPKR status bit(s) by writing to a 1, + * Set the KPKR synchronizer chain by writing "1" to KRSS register, + * Clear the KPKD synchronizer chain by writing "1" to KDSC register + * + * @result Number of key pressed/released. + */ +static int mxc_kpp_scan_matrix(void) +{ + unsigned short reg_val; + int col, row; + short scancode = 0; + int keycnt = 0; /* How many keys are still pressed */ + + /* + * wmb() linux kernel function which guarantees orderings in write + * operations + */ + /* wmb(); */ + + /* save cur keypad matrix to prev */ + memcpy(prev_rcmap, cur_rcmap, kpp_dev.kpp_rows * sizeof(prev_rcmap[0])); + memset(cur_rcmap, 0, kpp_dev.kpp_rows * sizeof(cur_rcmap[0])); + + for (col = 0; col < kpp_dev.kpp_cols; col++) { /* Col */ + /* 2. Write 1.s to KPDR[15:8] setting column data to 1.s */ + reg_val = __raw_readw(KPDR); + reg_val |= 0xff00; + __raw_writew(reg_val, KPDR); + + /* + * 3. Configure columns as totem pole outputs(for quick + * discharging of keypad capacitance) + */ + reg_val = __raw_readw(KPCR); + reg_val &= 0x00ff; + __raw_writew(reg_val, KPCR); + + udelay(2); + +#ifdef KPP_DEBUG + mxc_kpp_dump_regs(); +#endif + + /* + * 4. Configure columns as open-drain + */ + reg_val = __raw_readw(KPCR); + reg_val |= ((1 << kpp_dev.kpp_cols) - 1) << 8; + __raw_writew(reg_val, KPCR); + + /* + * 5. Write a single column to 0, others to 1. + * 6. Sample row inputs and save data. Multiple key presses + * can be detected on a single column. + * 7. Repeat steps 2 - 6 for remaining columns. + */ + + /* Col bit starts at 8th bit in KPDR */ + reg_val = __raw_readw(KPDR); + reg_val &= ~(1 << (8 + col)); + __raw_writew(reg_val, KPDR); + + /* Delay added to avoid propagating the 0 from column to row + * when scanning. */ + + udelay(5); + +#ifdef KPP_DEBUG + mxc_kpp_dump_regs(); +#endif + + /* Read row input */ + reg_val = __raw_readw(KPDR); + for (row = 0; row < kpp_dev.kpp_rows; row++) { /* sample row */ + if (TEST_BIT(reg_val, row) == 0) { + cur_rcmap[row] = BITSET(cur_rcmap[row], col); + keycnt++; + } + } + } + + /* + * 8. Return all columns to 0 in preparation for standby mode. + * 9. Clear KPKD and KPKR status bit(s) by writing to a .1., + * set the KPKR synchronizer chain by writing "1" to KRSS register, + * clear the KPKD synchronizer chain by writing "1" to KDSC register + */ + reg_val = 0x00; + __raw_writew(reg_val, KPDR); + reg_val = __raw_readw(KPDR); + reg_val = __raw_readw(KPSR); + reg_val |= KBD_STAT_KPKD | KBD_STAT_KPKR | KBD_STAT_KRSS | + KBD_STAT_KDSC; + __raw_writew(reg_val, KPSR); + +#ifdef KPP_DEBUG + mxc_kpp_dump_regs(); +#endif + + /* Check key press status change */ + + /* + * prev_rcmap array will contain the previous status of the keypad + * matrix. cur_rcmap array will contains the present status of the + * keypad matrix. If a bit is set in the array, that (row, col) bit is + * pressed, else it is not pressed. + * + * XORing these two variables will give us the change in bit for + * particular row and column. If a bit is set in XOR output, then that + * (row, col) has a change of status from the previous state. From + * the diff variable the key press and key release of row and column + * are found out. + * + * If the key press is determined then scancode for key pressed + * can be generated using the following statement: + * scancode = ((row * 8) + col); + * + * If the key release is determined then scancode for key release + * can be generated using the following statement: + * scancode = ((row * 8) + col) + MXC_KEYRELEASE; + */ + for (row = 0; row < kpp_dev.kpp_rows; row++) { + unsigned char diff; + + /* + * Calculate the change in the keypad row status + */ + diff = prev_rcmap[row] ^ cur_rcmap[row]; + + for (col = 0; col < kpp_dev.kpp_cols; col++) { + if ((diff >> col) & 0x1) { + /* There is a status change on col */ + if ((prev_rcmap[row] & BITSET(0, col)) == 0) { + /* + * Previous state is 0, so now + * a key is pressed + */ + scancode = + ((row * kpp_dev.kpp_cols) + + col); + KPress = 1; + kpp_dev.iKeyState = KStateUp; + + KPP_PRINTF("Press (%d, %d) scan=%d " + "Kpress=%d\n", + row, col, scancode, KPress); + press_scancode[row][col] = + (short)scancode; + } else { + /* + * Previous state is not 0, so + * now a key is released + */ + scancode = + (row * kpp_dev.kpp_cols) + + col + MXC_KEYRELEASE; + KPress = 0; + kpp_dev.iKeyState = KStateDown; + + KPP_PRINTF + ("Release (%d, %d) scan=%d Kpress=%d\n", + row, col, scancode, KPress); + release_scancode[row][col] = + (short)scancode; + keycnt++; + } + } + } + } + + return keycnt; +} + +static int mxc_kpp_reset(void) +{ + unsigned short reg_val; + int i; + + /* + * Stop scanning and wait for interrupt. + * Enable press interrupt and disable release interrupt. + */ + __raw_writew(0x00FF, KPDR); + reg_val = __raw_readw(KPSR); + reg_val |= (KBD_STAT_KPKR | KBD_STAT_KPKD); + reg_val |= KBD_STAT_KRSS | KBD_STAT_KDSC; + __raw_writew(reg_val, KPSR); + reg_val |= KBD_STAT_KDIE; + reg_val &= ~KBD_STAT_KRIE; + __raw_writew(reg_val, KPSR); + +#ifdef KPP_DEBUG + mxc_kpp_dump_regs(); +#endif + + /* + * No more keys pressed... make sure unwanted key codes are + * not given upstairs + */ + for (i = 0; i < kpp_dev.kpp_rows; i++) { + memset(press_scancode[i], -1, + sizeof(press_scancode[0][0]) * kpp_dev.kpp_cols); + memset(release_scancode[i], -1, + sizeof(release_scancode[0][0]) * + kpp_dev.kpp_cols); + } + + return 0; +} + +int mxc_kpp_getc(struct kpp_key_info *key_info) +{ + int col, row; + static int key_cnt; + unsigned short reg_val; + short scancode = 0; + + reg_val = __raw_readw(KPSR); + + if (!key_cnt) { + if (reg_val & KBD_STAT_KPKD) { + /* + * Disable key press(KDIE status bit) interrupt + */ + reg_val &= ~KBD_STAT_KDIE; + __raw_writew(reg_val, KPSR); + +#ifdef KPP_DEBUG + mxc_kpp_dump_regs(); +#endif + + key_cnt = mxc_kpp_scan_matrix(); + } else { + return 0; + } + } + + /* + * This switch case statement is the + * implementation of state machine of debounc + * logic for key press/release. + * The explaination of state machine is as + * follows: + * + * KStateUp State: + * This is in intial state of the state machine + * this state it checks for any key presses. + * The key press can be checked using the + * variable KPress. If KPress is set, then key + * press is identified and switches the to + * KStateFirstDown state for key press to + * debounce. + * + * KStateFirstDown: + * After debounce delay(10ms), if the KPress is + * still set then pass scancode generated to + * input device and change the state to + * KStateDown, else key press debounce is not + * satisfied so change the state to KStateUp. + * + * KStateDown: + * In this state it checks for any key release. + * If KPress variable is cleared, then key + * release is indicated and so, switch the + * state to KStateFirstUp else to state + * KStateDown. + * + * KStateFirstUp: + * After debounce delay(10ms), if the KPress is + * still reset then pass the key release + * scancode to input device and change + * the state to KStateUp else key release is + * not satisfied so change the state to + * KStateDown. + */ + + for (row = 0; row < kpp_dev.kpp_rows; row++) { + for (col = 0; col < kpp_dev.kpp_cols; col++) { + if ((press_scancode[row][col] != -1)) { + /* Still Down, so add scancode */ + scancode = + press_scancode[row][col]; + + key_info->val = mxckpd_keycodes[scancode]; + key_info->evt = KDepress; + + KPP_PRINTF("KStateFirstDown: scan=%d val=%d\n", + scancode, mxckpd_keycodes[scancode]); + kpp_dev.iKeyState = KStateDown; + press_scancode[row][col] = -1; + + goto key_detect; + } + } + } + + for (row = 0; row < kpp_dev.kpp_rows; row++) { + for (col = 0; col < kpp_dev.kpp_cols; col++) { + if ((release_scancode[row][col] != -1)) { + scancode = + release_scancode[row][col]; + scancode = + scancode - MXC_KEYRELEASE; + + key_info->val = mxckpd_keycodes[scancode]; + key_info->evt = KRelease; + + KPP_PRINTF("KStateFirstUp: scan=%d val=%d\n", + scancode, mxckpd_keycodes[scancode]); + + kpp_dev.iKeyState = KStateUp; + release_scancode[row][col] = -1; + + goto key_detect; + } + } + } + + return 0; + +key_detect: + /* udelay(KScanRate); */ + key_cnt = mxc_kpp_scan_matrix(); + + if (0 == key_cnt) + mxc_kpp_reset(); + return 1; +} + +/*! + * This function is called to free the allocated memory for local arrays + */ +static void mxc_kpp_free_allocated(void) +{ + int i; + + if (press_scancode) { + for (i = 0; i < kpp_dev.kpp_rows; i++) { + if (press_scancode[i]) + free(press_scancode[i]); + } + free(press_scancode); + } + + if (release_scancode) { + for (i = 0; i < kpp_dev.kpp_rows; i++) { + if (release_scancode[i]) + free(release_scancode[i]); + } + free(release_scancode); + } + + if (cur_rcmap) + free(cur_rcmap); + + if (prev_rcmap) + free(prev_rcmap); +} + +/*! + * This function is called during the driver binding process. + * + * @param pdev the device structure used to store device specific + * information that is used by the suspend, resume and remove + * functions. + * + * @return The function returns 0 on successful registration. Otherwise returns + * specific error code. + */ +int mxc_kpp_init(void) +{ + int i; + int retval; + unsigned int reg_val; + + kpp_dev.kpp_cols = CONFIG_MXC_KPD_COLMAX; + kpp_dev.kpp_rows = CONFIG_MXC_KPD_ROWMAX; + + /* clock and IOMUX configuration for keypad */ + setup_mxc_kpd(); + + /* Configure keypad */ + + /* Enable number of rows in keypad (KPCR[7:0]) + * Configure keypad columns as open-drain (KPCR[15:8]) + * + * Configure the rows/cols in KPP + * LSB nibble in KPP is for 8 rows + * MSB nibble in KPP is for 8 cols + */ + reg_val = __raw_readw(KPCR); + reg_val |= (1 << kpp_dev.kpp_rows) - 1; /* LSB */ + reg_val |= ((1 << kpp_dev.kpp_cols) - 1) << 8; /* MSB */ + __raw_writew(reg_val, KPCR); + + /* Write 0's to KPDR[15:8] */ + reg_val = __raw_readw(KPDR); + reg_val &= 0x00ff; + __raw_writew(reg_val, KPDR); + + /* Configure columns as output, + * rows as input (KDDR[15:0]) */ + reg_val = __raw_readw(KDDR); + reg_val |= 0xff00; + reg_val &= 0xff00; + __raw_writew(reg_val, KDDR); + + /* Clear the KPKD Status Flag + * and Synchronizer chain. */ + reg_val = __raw_readw(KPSR); + reg_val &= ~(KBD_STAT_KPKR | KBD_STAT_KPKD); + reg_val |= KBD_STAT_KPKD; + reg_val |= KBD_STAT_KRSS | KBD_STAT_KDSC; + __raw_writew(reg_val, KPSR); + /* Set the KDIE control bit, and clear the KRIE + * control bit (avoid false release events). */ + reg_val |= KBD_STAT_KDIE; + reg_val &= ~KBD_STAT_KRIE; + __raw_writew(reg_val, KPSR); + +#ifdef KPP_DEBUG + mxc_kpp_dump_regs(); +#endif + + mxckpd_keycodes = mxc_key_mapping; + mxckpd_keycodes_size = kpp_dev.kpp_cols * kpp_dev.kpp_rows; + + if ((mxckpd_keycodes == (void *)0) + || (mxckpd_keycodes_size == 0)) { + retval = -ENODEV; + goto err; + } + + /* allocate required memory */ + press_scancode = (short **)malloc(kpp_dev.kpp_rows * sizeof(press_scancode[0])); + release_scancode = (short **)malloc(kpp_dev.kpp_rows * sizeof(release_scancode[0])); + + if (!press_scancode || !release_scancode) { + retval = -ENOMEM; + goto err; + } + + for (i = 0; i < kpp_dev.kpp_rows; i++) { + press_scancode[i] = (short *)malloc(kpp_dev.kpp_cols + * sizeof(press_scancode[0][0])); + release_scancode[i] = + (short *)malloc(kpp_dev.kpp_cols * sizeof(release_scancode[0][0])); + + if (!press_scancode[i] || !release_scancode[i]) { + retval = -ENOMEM; + goto err; + } + } + + cur_rcmap = + (unsigned short *)malloc(kpp_dev.kpp_rows * sizeof(cur_rcmap[0])); + prev_rcmap = + (unsigned short *)malloc(kpp_dev.kpp_rows * sizeof(prev_rcmap[0])); + + if (!cur_rcmap || !prev_rcmap) { + retval = -ENOMEM; + goto err; + } + + for (i = 0; i < kpp_dev.kpp_rows; i++) { + memset(press_scancode[i], -1, + sizeof(press_scancode[0][0]) * kpp_dev.kpp_cols); + memset(release_scancode[i], -1, + sizeof(release_scancode[0][0]) * kpp_dev.kpp_cols); + } + memset(cur_rcmap, 0, kpp_dev.kpp_rows * sizeof(cur_rcmap[0])); + memset(prev_rcmap, 0, kpp_dev.kpp_rows * sizeof(prev_rcmap[0])); + + return 0; + +err: + mxc_kpp_free_allocated(); + return retval; +} + diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile index f6df60faef..448b9cb020 100644 --- a/drivers/misc/Makefile +++ b/drivers/misc/Makefile @@ -28,6 +28,7 @@ LIB := $(obj)libmisc.a COBJS-$(CONFIG_ALI152X) += ali512x.o COBJS-$(CONFIG_DS4510) += ds4510.o COBJS-$(CONFIG_FSL_LAW) += fsl_law.o +COBJS-$(CONFIG_IMX_IIM) += imx_iim.o COBJS-$(CONFIG_NS87308) += ns87308.o COBJS-$(CONFIG_STATUS_LED) += status_led.o COBJS-$(CONFIG_TWL4030_LED) += twl4030_led.o diff --git a/drivers/misc/imx_iim.c b/drivers/misc/imx_iim.c new file mode 100644 index 0000000000..4bbd4ca416 --- /dev/null +++ b/drivers/misc/imx_iim.c @@ -0,0 +1,343 @@ +/* + * (C) Copyright 2008-2010 Freescale Semiconductor, Inc. + * Terry Lv + * + * Copyright 2007, Freescale Semiconductor, Inc + * Andy Fleming + * + * Based vaguely on the pxa mmc code: + * (C) Copyright 2003 + * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include + +static const struct iim_regs *imx_iim = + (struct iim_regs *)IMX_IIM_BASE; + +static void quick_itoa(u32 num, char *a) +{ + int i, j, k; + for (i = 0; i <= 7; i++) { + j = (num >> (4 * i)) & 0xf; + k = (j < 10) ? '0' : ('a' - 0xa); + a[i] = j + k; + } +} + +/* slen - streng length, e.g.: 23 -> slen=2; abcd -> slen=4 */ +/* only convert hex value as string input. so "12" is 0x12. */ +static u32 quick_atoi(char *a, u32 slen) +{ + u32 i, num = 0, digit; + + for (i = 0; i < slen; i++) { + if (a[i] >= '0' && a[i] <= '9') { + digit = a[i] - '0'; + } else if (a[i] >= 'a' && a[i] <= 'f') { + digit = a[i] - 'a' + 10; + } else if (a[i] >= 'A' && a[i] <= 'F') { + digit = a[i] - 'A' + 10; + } else { + printf("ERROR: %c\n", a[i]); + return -1; + } + num = (num * 16) + digit; + } + + return num; +} + +static void fuse_op_start(void) +{ + /* Do not generate interrupt */ + writel(0, &(imx_iim->statm)); + /* clear the status bits and error bits */ + writel(0x3, &(imx_iim->stat)); + writel(0xfe, &(imx_iim->err)); +} + +/* + * The action should be either: + * POLL_FUSE_PRGD + * or: + * POLL_FUSE_SNSD + */ +static s32 poll_fuse_op_done(s32 action) +{ + u32 status, error; + + if (action != POLL_FUSE_PRGD && action != POLL_FUSE_SNSD) { + printf("%s(%d) invalid operation\n", __func__, action); + return -1; + } + + /* Poll busy bit till it is NOT set */ + while ((readl(&(imx_iim->stat)) & IIM_STAT_BUSY) != 0) + ; + + /* Test for successful write */ + status = readl(&(imx_iim->stat)); + error = readl(&(imx_iim->err)); + + if ((status & action) != 0 && \ + (error & (action >> IIM_ERR_SHIFT)) == 0) { + if (error) { + printf("Even though the operation" + "seems successful...\n"); + printf("There are some error(s) " + "at addr=0x%x: 0x%x\n", + (u32)&(imx_iim->err), error); + } + return 0; + } + printf("%s(%d) failed\n", __func__, action); + printf("status address=0x%x, value=0x%x\n", + (u32)&(imx_iim->stat), status); + printf("There are some error(s) at addr=0x%x: 0x%x\n", + (u32)&(imx_iim->err), error); + return -1; +} + +static u32 sense_fuse(s32 bank, s32 row, s32 bit) +{ + s32 addr, addr_l, addr_h, reg_addr; + + fuse_op_start(); + + addr = ((bank << 11) | (row << 3) | (bit & 0x7)); + /* Set IIM Program Upper Address */ + addr_h = (addr >> 8) & 0x000000FF; + /* Set IIM Program Lower Address */ + addr_l = (addr & 0x000000FF); + +#ifdef IIM_FUSE_DEBUG + printf("%s: addr_h=0x%x, addr_l=0x%x\n", + __func__, addr_h, addr_l); +#endif + writel(addr_h, &(imx_iim->ua)); + writel(addr_l, &(imx_iim->la)); + + /* Start sensing */ + writel(0x8, &(imx_iim->fctl)); + if (poll_fuse_op_done(POLL_FUSE_SNSD) != 0) { + printf("%s(bank: %d, row: %d, bit: %d failed\n", + __func__, bank, row, bit); + } + reg_addr = &(imx_iim->sdat); + + return readl(reg_addr); +} + +int iim_read(int bank, char row) +{ + u32 fuse_val; + s32 err = 0; + + printf("Read fuse at bank:%d row:%d\n", bank, row); + fuse_val = sense_fuse(bank, row, 0); + printf("fuses at (bank:%d, row:%d) = 0x%x\n", bank, row, fuse_val); + + return err; +} + +/* Blow fuses based on the bank, row and bit positions (all 0-based) +*/ +static s32 fuse_blow_bit(s32 bank, s32 row, s32 bit) +{ + int addr, addr_l, addr_h, ret = -1; + + fuse_op_start(); + + /* Disable IIM Program Protect */ + writel(0xaa, &(imx_iim->preg_p)); + + addr = ((bank << 11) | (row << 3) | (bit & 0x7)); + /* Set IIM Program Upper Address */ + addr_h = (addr >> 8) & 0x000000FF; + /* Set IIM Program Lower Address */ + addr_l = (addr & 0x000000FF); + +#ifdef IIM_FUSE_DEBUG + printf("blowing addr_h=0x%x, addr_l=0x%x\n", addr_h, addr_l); +#endif + + writel(addr_h, &(imx_iim->ua)); + writel(addr_l, &(imx_iim->la)); + + /* Start Programming */ + writel(0x31, &(imx_iim->fctl)); + if (poll_fuse_op_done(POLL_FUSE_PRGD) == 0) + ret = 0; + + /* Enable IIM Program Protect */ + writel(0x0, &(imx_iim->preg_p)); + + return ret; +} + +static void fuse_blow_row(s32 bank, s32 row, s32 value) +{ + u32 reg, i; + + /* enable fuse blown */ + reg = readl(CCM_BASE_ADDR + 0x64); + reg |= 0x10; + writel(reg, CCM_BASE_ADDR + 0x64); + + for (i = 0; i < 8; i++) { + if (((value >> i) & 0x1) == 0) + continue; + if (fuse_blow_bit(bank, row, i) != 0) { + printf("fuse_blow_bit(bank: %d, row: %d, " + "bit: %d failed\n", + bank, row, i); + } + } + reg &= ~0x10; + writel(reg, CCM_BASE_ADDR + 0x64); +} + +int iim_blow(int bank, int row, int val) +{ + u32 fuse_val, err = 0; + + printf("Blowing fuse at bank:%d row:%d value:%d\n", + bank, row, val); + fuse_blow_row(bank, row, val); + fuse_val = sense_fuse(bank, row, 0); + printf("fuses at (bank:%d, row:%d) = 0x%x\n", bank, row, fuse_val); + + return err; +} + +static int iim_read_mac_addr(u8 *data) +{ + s32 bank = CONFIG_IIM_MAC_BANK; + s32 row = CONFIG_IIM_MAC_ROW; + + data[0] = sense_fuse(bank, row, 0) ; + data[1] = sense_fuse(bank, row + 1, 0) ; + data[2] = sense_fuse(bank, row + 2, 0) ; + data[3] = sense_fuse(bank, row + 3, 0) ; + data[4] = sense_fuse(bank, row + 4, 0) ; + data[5] = sense_fuse(bank, row + 5, 0) ; + + if (!memcmp(data, "\0\0\0\0\0\0", 6)) + return 0; + else + return 1; +} + +int iim_blow_func(char *func_name, char *func_val) +{ + u32 value, i; + char *s; + char val[3]; + s32 err = 0; + + if (0 == strcmp(func_name, "scc")) { + /* fuse_blow scc + C3D153EDFD2EA9982226EF5047D3B9A0B9C7138EA87C028401D28C2C2C0B9AA2 */ + printf("Ready to burn SCC fuses\n"); + s = func_val; + for (i = 0; ; ++i) { + memcpy(val, s, 2); + val[2] = '\0'; + value = quick_atoi(val, 2); + /* printf("fuse_blow_row(2, %d, value=0x%x)\n", + i, value); */ + fuse_blow_row(2, i, value); + + if ((++s)[0] == '\0') { + printf("ERROR: Odd string input\n"); + err = -1; + break; + } + if ((++s)[0] == '\0') { + printf("Successful\n"); + break; + } + } + } else if (0 == strcmp(func_name, "srk")) { + /* fuse_blow srk + 418bccd09b53bee1ab59e2662b3c7877bc0094caee201052add49be8780dff95 */ + printf("Ready to burn SRK key fuses\n"); + s = func_val; + for (i = 0; ; ++i) { + memcpy(val, s, 2); + val[2] = '\0'; + value = quick_atoi(val, 2); + if (i == 0) { + /* 0x41 goes to SRK_HASH[255:248], + * bank 1, row 1 */ + fuse_blow_row(1, 1, value); + } else { + /* 0x8b in SRK_HASH[247:240] bank 3, row 1 */ + /* 0xcc in SRK_HASH[239:232] bank 3, row 2 */ + /* ... */ + fuse_blow_row(3, i, value); + + if ((++s)[0] == '\0') { + printf("ERROR: Odd string input\n"); + err = -1; + break; + } + if ((++s)[0] == '\0') { + printf("Successful\n"); + break; + } + } + } + } else if (0 == strcmp(func_name, "fecmac")) { + u8 ea[6] = { 0 }; + + if (NULL == func_val) { + /* Read the Mac address and print it */ + iim_read_mac_addr(ea); + + printf("FEC MAC address: "); + printf("0x%02x:0x%02x:0x%02x:0x%02x:0x%02x:0x%02x\n\n", + ea[0], ea[1], ea[2], ea[3], ea[4], ea[5]); + + return 0; + } + + eth_parse_enetaddr(func_val, ea); + if (!is_valid_ether_addr(ea)) { + printf("Error: invalid mac address parameter!\n"); + err = -1; + } else { + for (i = 0; i < 6; ++i) + fuse_blow_row(1, i + 9, ea[i]); + } + } else { + printf("This command is not supported\n"); + } + + return err; +} + + diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile index 6fa04b84fc..39a8913cb0 100644 --- a/drivers/mmc/Makefile +++ b/drivers/mmc/Makefile @@ -32,6 +32,9 @@ COBJS-$(CONFIG_OMAP3_MMC) += omap3_mmc.o COBJS-$(CONFIG_FSL_ESDHC) += fsl_esdhc.o COBJS-$(CONFIG_MXC_MMC) += mxcmmc.o COBJS-$(CONFIG_PXA_MMC) += pxa_mmc.o +COBJS-$(CONFIG_FSL_MMC) += fsl_esdhc.o +COBJS-$(CONFIG_IMX_MMC) += imx_esdhc.o +COBJS-$(CONFIG_IMX_SSP_MMC) += imx_ssp_mmc.o COBJS := $(COBJS-y) SRCS := $(COBJS:.o=.c) diff --git a/drivers/mmc/imx_esdhc.c b/drivers/mmc/imx_esdhc.c new file mode 100644 index 0000000000..a57aa74496 --- /dev/null +++ b/drivers/mmc/imx_esdhc.c @@ -0,0 +1,505 @@ +/* + * (C) Copyright 2008-2010 Freescale Semiconductor, Inc. + * Terry Lv, Jason Liu + * + * Copyright 2007, Freescale Semiconductor, Inc + * Andy Fleming + * + * Based vaguely on the pxa mmc code: + * (C) Copyright 2003 + * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + + +DECLARE_GLOBAL_DATA_PTR; + +#define SDHCI_IRQ_EN_BITS (IRQSTATEN_CC | IRQSTATEN_TC | \ + IRQSTATEN_BWR | IRQSTATEN_BRR | IRQSTATEN_CINT | \ + IRQSTATEN_CTOE | IRQSTATEN_CCE | IRQSTATEN_CEBE | \ + IRQSTATEN_CIE | IRQSTATEN_DTOE | IRQSTATEN_DCE | IRQSTATEN_DEBE) + +struct fsl_esdhc { + uint dsaddr; + uint blkattr; + uint cmdarg; + uint xfertyp; + uint cmdrsp0; + uint cmdrsp1; + uint cmdrsp2; + uint cmdrsp3; + uint datport; + uint prsstat; + uint proctl; + uint sysctl; + uint irqstat; + uint irqstaten; + uint irqsigen; + uint autoc12err; + uint hostcapblt; + uint wml; + char reserved1[8]; + uint fevt; + char reserved2[12]; + uint dllctrl; + uint dllstatus; + char reserved3[148]; + uint hostver; +}; + +/* Return the XFERTYP flags for a given command and data packet */ +uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data) +{ + uint xfertyp = 0; + + if (data) { + xfertyp |= XFERTYP_DPSEL; + + if (data->blocks > 1) { + xfertyp |= XFERTYP_MSBSEL; + xfertyp |= XFERTYP_BCEN; + } + + if (data->flags & MMC_DATA_READ) + xfertyp |= XFERTYP_DTDSEL; + } + + if (cmd->resp_type & MMC_RSP_CRC) + xfertyp |= XFERTYP_CCCEN; + if (cmd->resp_type & MMC_RSP_OPCODE) + xfertyp |= XFERTYP_CICEN; + if (cmd->resp_type & MMC_RSP_136) + xfertyp |= XFERTYP_RSPTYP_136; + else if (cmd->resp_type & MMC_RSP_BUSY) + xfertyp |= XFERTYP_RSPTYP_48_BUSY; + else if (cmd->resp_type & MMC_RSP_PRESENT) + xfertyp |= XFERTYP_RSPTYP_48; + + return XFERTYP_CMD(cmd->cmdidx) | xfertyp; +} + +static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data) +{ + uint wml_value; + int timeout; + u32 tmp; + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base; + + wml_value = data->blocksize / 4; + + if (wml_value > 0x80) + wml_value = 0x80; + + if (!(data->flags & MMC_DATA_READ)) { + if ((readl(®s->prsstat) & PRSSTAT_WPSPL) == 0) { + printf("\nThe SD card is locked. Can not write to a locked card.\n\n"); + return TIMEOUT; + } + wml_value = wml_value << 16; + } + + writel(wml_value, ®s->wml); + + writel(data->blocks << 16 | data->blocksize, ®s->blkattr); + + /* Calculate the timeout period for data transactions */ + /* + timeout = fls(mmc->tran_speed / 10) - 1; + timeout -= 13; + + if (timeout > 14) + timeout = 14; + + if (timeout < 0) + timeout = 0; + */ + timeout = 14; + + tmp = (readl(®s->sysctl) & (~SYSCTL_TIMEOUT_MASK)) | (timeout << 16); + writel(tmp, ®s->sysctl); + + return 0; +} + + +/* + * Sends a command out on the bus. Takes the mmc pointer, + * a command pointer, and an optional data pointer. + */ +static int +esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) +{ + uint xfertyp; + uint irqstat; + u32 tmp; + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + volatile struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base; + + writel(-1, ®s->irqstat); + + sync(); + + tmp = readl(®s->irqstaten) | SDHCI_IRQ_EN_BITS; + writel(tmp, ®s->irqstaten); + + /* Wait for the bus to be idle */ + while ((readl(®s->prsstat) & PRSSTAT_CICHB) || + (readl(®s->prsstat) & PRSSTAT_CIDHB)) + ; + + while (readl(®s->prsstat) & PRSSTAT_DLA); + + /* Wait at least 8 SD clock cycles before the next command */ + /* + * Note: This is way more than 8 cycles, but 1ms seems to + * resolve timing issues with some cards + */ + udelay(10000); + + /* Set up for a data transfer if we have one */ + if (data) { + int err; + + err = esdhc_setup_data(mmc, data); + if(err) + return err; + } + + /* Figure out the transfer arguments */ + xfertyp = esdhc_xfertyp(cmd, data); + + if (mmc->bus_width == EMMC_MODE_4BIT_DDR || + mmc->bus_width == EMMC_MODE_8BIT_DDR) + xfertyp |= XFERTYP_DDR_EN; + + /* Send the command */ + writel(cmd->cmdarg, ®s->cmdarg); + writel(xfertyp, ®s->xfertyp); + + /* Mask all irqs */ + writel(0, ®s->irqsigen); + + /* Wait for the command to complete */ + while (!(readl(®s->irqstat) & IRQSTAT_CC)); + + irqstat = readl(®s->irqstat); + writel(irqstat, ®s->irqstat); + + if (irqstat & CMD_ERR) + return COMM_ERR; + + if (irqstat & IRQSTAT_CTOE) + return TIMEOUT; + + /* Copy the response to the response buffer */ + if (cmd->resp_type & MMC_RSP_136) { + u32 cmdrsp3, cmdrsp2, cmdrsp1, cmdrsp0; + + cmdrsp3 = readl(®s->cmdrsp3); + cmdrsp2 = readl(®s->cmdrsp2); + cmdrsp1 = readl(®s->cmdrsp1); + cmdrsp0 = readl(®s->cmdrsp0); + cmd->response[0] = (cmdrsp3 << 8) | (cmdrsp2 >> 24); + cmd->response[1] = (cmdrsp2 << 8) | (cmdrsp1 >> 24); + cmd->response[2] = (cmdrsp1 << 8) | (cmdrsp0 >> 24); + cmd->response[3] = (cmdrsp0 << 8); + } else + cmd->response[0] = readl(®s->cmdrsp0); + + /* Wait until all of the blocks are transferred */ + if (data) { + int i = 0, j = 0; + u32 *tmp_ptr = NULL; + uint block_size = data->blocksize; + uint block_cnt = data->blocks; + + tmp = readl(®s->irqstaten) | SDHCI_IRQ_EN_BITS; + writel(tmp, ®s->irqstaten); + + if (data->flags & MMC_DATA_READ) { + tmp_ptr = (u32 *)data->dest; + + for (i = 0; i < (block_cnt); ++i) { + while (!(readl(®s->irqstat) & IRQSTAT_BRR)) + ; + + for (j = 0; j < (block_size >> 2); ++j, ++tmp_ptr) { + *tmp_ptr = readl(®s->datport); + } + + tmp = readl(®s->irqstat) & (IRQSTAT_BRR); + writel(tmp, ®s->irqstat); + } + } else { + tmp_ptr = (u32 *)data->src; + + for (i = 0; i < (block_cnt); ++i) { + while (!(readl(®s->irqstat) & IRQSTAT_BWR)) + ; + + for (j = 0; j < (block_size >> 2); ++j, ++tmp_ptr) { + writel(*tmp_ptr, ®s->datport); + } + + tmp = readl(®s->irqstat) & (IRQSTAT_BWR); + writel(tmp, ®s->irqstat); + } + } + + while (!(readl(®s->irqstat) & IRQSTAT_TC)) ; + } + + if (readl(®s->irqstat) & 0xFFFF0000) + return COMM_ERR; + + writel(-1, ®s->irqstat); + + return 0; +} + +void set_sysctl(struct mmc *mmc, uint clock) +{ + int sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); + int div, pre_div; + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + volatile struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base; + uint clk; + u32 tmp; + + if (sdhc_clk / 16 > clock) { + for (pre_div = 2; pre_div < 256; pre_div *= 2) + if ((sdhc_clk / pre_div) <= (clock * 16)) + break; + } else + pre_div = 2; + + for (div = 1; div <= 16; div++) + if ((sdhc_clk / (div * pre_div)) <= clock) + break; + + pre_div >>= 1; + div -= 1; + + clk = (pre_div << 8) | (div << 4); + +#ifndef CONFIG_IMX_ESDHC_V1 + tmp = readl(®s->sysctl) & (~SYSCTL_SDCLKEN); + writel(tmp, ®s->sysctl); +#endif + + tmp = (readl(®s->sysctl) & (~SYSCTL_CLOCK_MASK)) | clk; + writel(tmp, ®s->sysctl); + + udelay(10000); + +#ifdef CONFIG_IMX_ESDHC_V1 + tmp = readl(®s->sysctl) | SYSCTL_PEREN; + writel(tmp, ®s->sysctl); +#else + while (!(readl(®s->prsstat) & PRSSTAT_SDSTB)) ; + + tmp = readl(®s->sysctl) | (SYSCTL_SDCLKEN); + writel(tmp, ®s->sysctl); +#endif +} + +static void esdhc_dll_setup(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base; + + uint dll_control = readl(®s->dllctrl); + dll_control &= ~(ESDHC_DLLCTRL_SLV_OVERRIDE_VAL_MASK | + ESDHC_DLLCTRL_SLV_OVERRIDE); + dll_control |= ((ESDHC_DLLCTRL_SLV_OVERRIDE_VAL << + ESDHC_DLLCTRL_SLV_OVERRIDE_VAL_SHIFT) | + ESDHC_DLLCTRL_SLV_OVERRIDE); + + writel(dll_control, ®s->dllctrl); + +} + +static void esdhc_set_ios(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base; + u32 tmp; + + /* Set the clock speed */ + set_sysctl(mmc, mmc->clock); + + /* Set the bus width */ + tmp = readl(®s->proctl) & (~(PROCTL_DTW_4 | PROCTL_DTW_8)); + writel(tmp, ®s->proctl); + + if (mmc->bus_width == 4) { + tmp = readl(®s->proctl) | PROCTL_DTW_4; + writel(tmp, ®s->proctl); + } else if (mmc->bus_width == 8) { + tmp = readl(®s->proctl) | PROCTL_DTW_8; + writel(tmp, ®s->proctl); + } else if (mmc->bus_width == EMMC_MODE_4BIT_DDR) { + tmp = readl(®s->proctl) | PROCTL_DTW_4; + writel(tmp, ®s->proctl); + esdhc_dll_setup(mmc); + } else if (mmc->bus_width == EMMC_MODE_8BIT_DDR) { + tmp = readl(®s->proctl) | PROCTL_DTW_8; + writel(tmp, ®s->proctl); + esdhc_dll_setup(mmc); + } +} + +static int esdhc_init(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base; + u32 tmp; + + /* Reset the eSDHC by writing 1 to RSTA bit of SYSCTRL Register */ + tmp = readl(®s->sysctl) | SYSCTL_RSTA; + writel(tmp, ®s->sysctl); + + while (readl(®s->sysctl) & SYSCTL_RSTA) + ; + +#ifdef CONFIG_IMX_ESDHC_V1 + tmp = readl(®s->sysctl) | (SYSCTL_HCKEN | SYSCTL_IPGEN); + writel(tmp, ®s->sysctl); +#endif + + /* Set the initial clock speed */ + set_sysctl(mmc, 400000); + + /* Put the PROCTL reg back to the default */ + writel(PROCTL_INIT, ®s->proctl); + + /* FIXME: For our CINS bit doesn't work. So this section is disabled. */ + /* + while (!(readl(®s->prsstat) & PRSSTAT_CINS) && --timeout) + ; + + if (timeout <= 0) { + printf("No MMC card detected!\n"); + return NO_CARD_ERR; + } + */ + +#ifndef CONFIG_IMX_ESDHC_V1 + tmp = readl(®s->sysctl) | SYSCTL_INITA; + writel(tmp, ®s->sysctl); + + while (readl(®s->sysctl) & SYSCTL_INITA) + ; +#endif + + return 0; +} + +int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg) +{ + struct fsl_esdhc *regs; + struct mmc *mmc; + u32 caps; + + if (!cfg) + return -1; + + mmc = malloc(sizeof(struct mmc)); + + sprintf(mmc->name, "FSL_ESDHC"); + regs = (struct fsl_esdhc *)cfg->esdhc_base; + mmc->priv = cfg; + mmc->send_cmd = esdhc_send_cmd; + mmc->set_ios = esdhc_set_ios; + mmc->init = esdhc_init; + + caps = readl(®s->hostcapblt); + if (caps & ESDHC_HOSTCAPBLT_VS30) + mmc->voltages |= MMC_VDD_29_30 | MMC_VDD_30_31; + if (caps & ESDHC_HOSTCAPBLT_VS33) + mmc->voltages |= MMC_VDD_32_33 | MMC_VDD_33_34; + + mmc->host_caps = MMC_MODE_4BIT; + + if (caps & ESDHC_HOSTCAPBLT_HSS) + mmc->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS; + + if (((readl(®s->hostver) & ESDHC_HOSTVER_VVN_MASK) + >> ESDHC_HOSTVER_VVN_SHIFT) >= ESDHC_HOSTVER_DDR_SUPPORT) + mmc->host_caps |= EMMC_MODE_4BIT_DDR; + + mmc->f_min = 400000; + mmc->f_max = MIN(mxc_get_clock(MXC_ESDHC_CLK), 50000000); + + mmc_register(mmc); + +#ifdef CONFIG_MMC_8BIT_PORTS + if ((1 << mmc->block_dev.dev) & CONFIG_MMC_8BIT_PORTS) { + mmc->host_caps |= MMC_MODE_8BIT; + + if (mmc->host_caps & EMMC_MODE_4BIT_DDR) + mmc->host_caps |= EMMC_MODE_8BIT_DDR; + } +#endif + + return 0; +} + +int fsl_esdhc_mmc_init(bd_t *bis) +{ + struct fsl_esdhc_cfg *cfg; + + cfg = malloc(sizeof(struct fsl_esdhc_cfg)); + memset(cfg, 0, sizeof(struct fsl_esdhc_cfg)); + cfg->esdhc_base = CONFIG_SYS_FSL_ESDHC_ADDR; + return fsl_esdhc_initialize(bis, cfg); +} + +#ifdef CONFIG_OF_LIBFDT +void fdt_fixup_esdhc(void *blob, bd_t *bd) +{ + const char *compat = "fsl,esdhc"; + const char *status = "okay"; + + if (!hwconfig("esdhc")) { + status = "disabled"; + goto out; + } + + do_fixup_by_compat_u32(blob, compat, "clock-frequency", + gd->sdhc_clk, 1); +out: + do_fixup_by_compat(blob, compat, "status", status, + strlen(status) + 1, 1); +} +#endif diff --git a/drivers/mmc/imx_ssp_mmc.c b/drivers/mmc/imx_ssp_mmc.c new file mode 100644 index 0000000000..fc480a567f --- /dev/null +++ b/drivers/mmc/imx_ssp_mmc.c @@ -0,0 +1,385 @@ +/* + * (C) Copyright 2008-2010 Freescale Semiconductor, Inc. + * Terry Lv + * + * Copyright 2007, Freescale Semiconductor, Inc + * Andy Fleming + * + * Based vaguely on the pxa mmc code: + * (C) Copyright 2003 + * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include +#include +#include +#include +#include +#include + +#undef IMX_SSP_MMC_DEBUG + +static inline int ssp_mmc_read(struct mmc *mmc, uint reg) +{ + struct imx_ssp_mmc_cfg *cfg = (struct imx_ssp_mmc_cfg *)mmc->priv; + return REG_RD(cfg->ssp_mmc_base, reg); +} + +static inline void ssp_mmc_write(struct mmc *mmc, uint reg, uint val) +{ + struct imx_ssp_mmc_cfg *cfg = (struct imx_ssp_mmc_cfg *)mmc->priv; + REG_WR(cfg->ssp_mmc_base, reg, val); +} + +static inline void mdelay(unsigned long msec) +{ + unsigned long i; + for (i = 0; i < msec; i++) + udelay(1000); +} + +static inline void sdelay(unsigned long sec) +{ + unsigned long i; + for (i = 0; i < sec; i++) + mdelay(1000); +} + +/* + * Sends a command out on the bus. Takes the mmc pointer, + * a command pointer, and an optional data pointer. + */ +static int +ssp_mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) +{ + int i; + +#ifdef IMX_SSP_MMC_DEBUG + printf("MMC%d: CMD%d\n", mmc->block_dev.dev, cmd->cmdidx); +#endif + + /* Check bus busy */ + i = 0; + while (ssp_mmc_read(mmc, HW_SSP_STATUS) & (BM_SSP_STATUS_BUSY | + BM_SSP_STATUS_DATA_BUSY | BM_SSP_STATUS_CMD_BUSY)) { + mdelay(1); + i++; + if (i == 1000) { + printf("MMC%d: Bus busy timeout!\n", + mmc->block_dev.dev); + return TIMEOUT; + } + } + + /* See if card is present */ + if (ssp_mmc_read(mmc, HW_SSP_STATUS) & BM_SSP_STATUS_CARD_DETECT) { + printf("MMC%d: No card detected!\n", mmc->block_dev.dev); + return NO_CARD_ERR; + } + + /* Clear all control bits except bus width */ + ssp_mmc_write(mmc, HW_SSP_CTRL0_CLR, 0xff3fffff); + + /* Set up command */ + if (!(cmd->resp_type & MMC_RSP_CRC)) + ssp_mmc_write(mmc, HW_SSP_CTRL0_SET, BM_SSP_CTRL0_IGNORE_CRC); + if (cmd->resp_type & MMC_RSP_PRESENT) /* Need to get response */ + ssp_mmc_write(mmc, HW_SSP_CTRL0_SET, BM_SSP_CTRL0_GET_RESP); + if (cmd->resp_type & MMC_RSP_136) /* It's a 136 bits response */ + ssp_mmc_write(mmc, HW_SSP_CTRL0_SET, BM_SSP_CTRL0_LONG_RESP); + + /* Command index */ + ssp_mmc_write(mmc, HW_SSP_CMD0, + (ssp_mmc_read(mmc, HW_SSP_CMD0) & ~BM_SSP_CMD0_CMD) | + (cmd->cmdidx << BP_SSP_CMD0_CMD)); + /* Command argument */ + ssp_mmc_write(mmc, HW_SSP_CMD1, cmd->cmdarg); + + /* Set up data */ + if (data) { + /* READ or WRITE */ + if (data->flags & MMC_DATA_READ) { + ssp_mmc_write(mmc, HW_SSP_CTRL0_SET, + BM_SSP_CTRL0_READ); + } else if (ssp_mmc_is_wp(mmc)) { + printf("MMC%d: Can not write a locked card!\n", + mmc->block_dev.dev); + return UNUSABLE_ERR; + } + ssp_mmc_write(mmc, HW_SSP_CTRL0_SET, BM_SSP_CTRL0_DATA_XFER); + ssp_mmc_write(mmc, HW_SSP_BLOCK_SIZE, + ((data->blocks - 1) << + BP_SSP_BLOCK_SIZE_BLOCK_COUNT) | + ((ffs(data->blocksize) - 1) << + BP_SSP_BLOCK_SIZE_BLOCK_SIZE)); + ssp_mmc_write(mmc, HW_SSP_XFER_SIZE, + data->blocksize * data->blocks); + } + + /* Kick off the command */ + ssp_mmc_write(mmc, HW_SSP_CTRL0_SET, BM_SSP_CTRL0_WAIT_FOR_IRQ); + ssp_mmc_write(mmc, HW_SSP_CTRL0_SET, BM_SSP_CTRL0_ENABLE); + ssp_mmc_write(mmc, HW_SSP_CTRL0_SET, BM_SSP_CTRL0_RUN); + + /* Wait for the command to complete */ + i = 0; + do { + mdelay(10); + if (i++ == 100) { + printf("MMC%d: Command %d busy\n", + mmc->block_dev.dev, + cmd->cmdidx); + break; + } + } while (ssp_mmc_read(mmc, HW_SSP_STATUS) & + BM_SSP_STATUS_CMD_BUSY); + + /* Check command timeout */ + if (ssp_mmc_read(mmc, HW_SSP_STATUS) & + BM_SSP_STATUS_RESP_TIMEOUT) { +#ifdef IMX_SSP_MMC_DEBUG + printf("MMC%d: Command %d timeout\n", mmc->block_dev.dev, + cmd->cmdidx); +#endif + return TIMEOUT; + } + + /* Check command errors */ + if (ssp_mmc_read(mmc, HW_SSP_STATUS) & + (BM_SSP_STATUS_RESP_CRC_ERR | BM_SSP_STATUS_RESP_ERR)) { + printf("MMC%d: Command %d error (status 0x%08x)!\n", + mmc->block_dev.dev, cmd->cmdidx, + ssp_mmc_read(mmc, HW_SSP_STATUS)); + return COMM_ERR; + } + + /* Copy response to response buffer */ + if (cmd->resp_type & MMC_RSP_136) { + cmd->response[3] = ssp_mmc_read(mmc, HW_SSP_SDRESP0); + cmd->response[2] = ssp_mmc_read(mmc, HW_SSP_SDRESP1); + cmd->response[1] = ssp_mmc_read(mmc, HW_SSP_SDRESP2); + cmd->response[0] = ssp_mmc_read(mmc, HW_SSP_SDRESP3); + } else + cmd->response[0] = ssp_mmc_read(mmc, HW_SSP_SDRESP0); + + /* Return if no data to process */ + if (!data) + return 0; + + /* Process the data */ + u32 xfer_cnt = data->blocksize * data->blocks; + u32 *tmp_ptr; + + if (data->flags & MMC_DATA_READ) { + tmp_ptr = (u32 *)data->dest; + while (xfer_cnt > 0) { + if ((ssp_mmc_read(mmc, HW_SSP_STATUS) & + BM_SSP_STATUS_FIFO_EMPTY) == 0) { + *tmp_ptr++ = ssp_mmc_read(mmc, HW_SSP_DATA); + xfer_cnt -= 4; + } + } + } else { + tmp_ptr = (u32 *)data->src; + while (xfer_cnt > 0) { + if ((ssp_mmc_read(mmc, HW_SSP_STATUS) & + BM_SSP_STATUS_FIFO_FULL) == 0) { + ssp_mmc_write(mmc, HW_SSP_DATA, *tmp_ptr++); + xfer_cnt -= 4; + } + } + } + + /* Check data errors */ + if (ssp_mmc_read(mmc, HW_SSP_STATUS) & + (BM_SSP_STATUS_TIMEOUT | BM_SSP_STATUS_DATA_CRC_ERR | + BM_SSP_STATUS_FIFO_OVRFLW | BM_SSP_STATUS_FIFO_UNDRFLW)) { + printf("MMC%d: Data error with command %d (status 0x%08x)!\n", + mmc->block_dev.dev, cmd->cmdidx, + ssp_mmc_read(mmc, HW_SSP_STATUS)); + return COMM_ERR; + } + + return 0; +} + +static void set_bit_clock(struct mmc *mmc, u32 clock) +{ + const u32 sspclk = 480000 * 18 / 29 / 1; /* 297931 KHz */ + u32 divide, rate, tgtclk; + + /* + * SSP bit rate = SSPCLK / (CLOCK_DIVIDE * (1 + CLOCK_RATE)), + * CLOCK_DIVIDE has to be an even value from 2 to 254, and + * CLOCK_RATE could be any integer from 0 to 255. + */ + clock /= 1000; /* KHz */ + for (divide = 2; divide < 254; divide += 2) { + rate = sspclk / clock / divide; + if (rate <= 256) + break; + } + + tgtclk = sspclk / divide / rate; + while (tgtclk > clock) { + rate++; + tgtclk = sspclk / divide / rate; + } + if (rate > 256) + rate = 256; + + /* Always set timeout the maximum */ + ssp_mmc_write(mmc, HW_SSP_TIMING, BM_SSP_TIMING_TIMEOUT | + divide << BP_SSP_TIMING_CLOCK_DIVIDE | + (rate - 1) << BP_SSP_TIMING_CLOCK_RATE); + +#ifdef IMX_SSP_MMC_DEBUG + printf("MMC%d: Set clock rate to %d KHz (requested %d KHz)\n", + mmc->block_dev.dev, tgtclk, clock); +#endif +} + +static void ssp_mmc_set_ios(struct mmc *mmc) +{ + u32 regval; + + /* Set the clock speed */ + if (mmc->clock) + set_bit_clock(mmc, mmc->clock); + + /* Set the bus width */ + regval = ssp_mmc_read(mmc, HW_SSP_CTRL0); + regval &= ~BM_SSP_CTRL0_BUS_WIDTH; + switch (mmc->bus_width) { + case 1: + regval |= (BV_SSP_CTRL0_BUS_WIDTH__ONE_BIT << + BP_SSP_CTRL0_BUS_WIDTH); + break; + case 4: + regval |= (BV_SSP_CTRL0_BUS_WIDTH__FOUR_BIT << + BP_SSP_CTRL0_BUS_WIDTH); + break; + case 8: + regval |= (BV_SSP_CTRL0_BUS_WIDTH__EIGHT_BIT << + BP_SSP_CTRL0_BUS_WIDTH); + } + ssp_mmc_write(mmc, HW_SSP_CTRL0, regval); + +#ifdef IMX_SSP_MMC_DEBUG + printf("MMC%d: Set %d bits bus width\n", + mmc->block_dev.dev, mmc->bus_width); +#endif +} + +static int ssp_mmc_init(struct mmc *mmc) +{ + struct imx_ssp_mmc_cfg *cfg = (struct imx_ssp_mmc_cfg *)mmc->priv; + u32 regval; + + /* + * Set up SSPCLK + */ + /* Set REF_IO0 at 297.731 MHz */ + regval = REG_RD(REGS_CLKCTRL_BASE, HW_CLKCTRL_FRAC0); + regval &= ~BM_CLKCTRL_FRAC0_IO0FRAC; + REG_WR(REGS_CLKCTRL_BASE, HW_CLKCTRL_FRAC0, + regval | (29 << BP_CLKCTRL_FRAC0_IO0FRAC)); + /* Enable REF_IO0 */ + REG_CLR(REGS_CLKCTRL_BASE, HW_CLKCTRL_FRAC0, + BM_CLKCTRL_FRAC0_CLKGATEIO0); + + /* Source SSPCLK from REF_IO0 */ + REG_CLR(REGS_CLKCTRL_BASE, HW_CLKCTRL_CLKSEQ, + cfg->clkctrl_clkseq_ssp_offset); + /* Turn on SSPCLK */ + REG_WR(REGS_CLKCTRL_BASE, cfg->clkctrl_ssp_offset, + REG_RD(REGS_CLKCTRL_BASE, cfg->clkctrl_ssp_offset) & + ~BM_CLKCTRL_SSP_CLKGATE); + /* Set SSPCLK divide 1 */ + regval = REG_RD(REGS_CLKCTRL_BASE, cfg->clkctrl_ssp_offset); + regval &= ~(BM_CLKCTRL_SSP_DIV_FRAC_EN | BM_CLKCTRL_SSP_DIV); + REG_WR(REGS_CLKCTRL_BASE, cfg->clkctrl_ssp_offset, + regval | (1 << BP_CLKCTRL_SSP_DIV)); + /* Wait for new divide ready */ + do { + udelay(10); + } while (REG_RD(REGS_CLKCTRL_BASE, cfg->clkctrl_ssp_offset) & + BM_CLKCTRL_SSP_BUSY); + + /* Prepare for software reset */ + ssp_mmc_write(mmc, HW_SSP_CTRL0_CLR, BM_SSP_CTRL0_SFTRST); + ssp_mmc_write(mmc, HW_SSP_CTRL0_CLR, BM_SSP_CTRL0_CLKGATE); + /* Assert reset */ + ssp_mmc_write(mmc, HW_SSP_CTRL0_SET, BM_SSP_CTRL0_SFTRST); + /* Wait for confirmation */ + while (!(ssp_mmc_read(mmc, HW_SSP_CTRL0) & BM_SSP_CTRL0_CLKGATE)) + ; + /* Done */ + ssp_mmc_write(mmc, HW_SSP_CTRL0_CLR, BM_SSP_CTRL0_SFTRST); + ssp_mmc_write(mmc, HW_SSP_CTRL0_CLR, BM_SSP_CTRL0_CLKGATE); + + /* 8 bits word length in MMC mode */ + regval = ssp_mmc_read(mmc, HW_SSP_CTRL1); + regval &= ~(BM_SSP_CTRL1_SSP_MODE | BM_SSP_CTRL1_WORD_LENGTH); + ssp_mmc_write(mmc, HW_SSP_CTRL1, regval | + (BV_SSP_CTRL1_SSP_MODE__SD_MMC << BP_SSP_CTRL1_SSP_MODE) | + (BV_SSP_CTRL1_WORD_LENGTH__EIGHT_BITS << + BP_SSP_CTRL1_WORD_LENGTH)); + + /* Set initial bit clock 400 KHz */ + set_bit_clock(mmc, 400000); + + /* Send initial 74 clock cycles (185 us @ 400 KHz)*/ + ssp_mmc_write(mmc, HW_SSP_CMD0_SET, BM_SSP_CMD0_CONT_CLKING_EN); + udelay(200); + ssp_mmc_write(mmc, HW_SSP_CMD0_CLR, BM_SSP_CMD0_CONT_CLKING_EN); + + return 0; +} + +int imx_ssp_mmc_initialize(bd_t *bis, struct imx_ssp_mmc_cfg *cfg) +{ + struct mmc *mmc; + + mmc = malloc(sizeof(struct mmc)); + sprintf(mmc->name, "IMX_SSP_MMC"); + mmc->send_cmd = ssp_mmc_send_cmd; + mmc->set_ios = ssp_mmc_set_ios; + mmc->init = ssp_mmc_init; + mmc->priv = cfg; + + mmc->voltages = MMC_VDD_32_33 | MMC_VDD_31_32 | MMC_VDD_30_31 | + MMC_VDD_29_30 | MMC_VDD_28_29 | MMC_VDD_27_28; + + mmc->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT | + MMC_MODE_HS_52MHz | MMC_MODE_HS; + + /* + * SSPCLK = 480 * 18 / 29 / 1 = 297.731 MHz + * SSP bit rate = SSPCLK / (CLOCK_DIVIDE * (1 + CLOCK_RATE)), + * CLOCK_DIVIDE has to be an even value from 2 to 254, and + * CLOCK_RATE could be any integer from 0 to 255. + */ + mmc->f_min = 400000; + mmc->f_max = 148000000; /* 297.731 MHz / 2 */ + + mmc_register(mmc); + return 0; +} diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index b69ce152a8..9f915cd57a 100644 --- a/drivers/mmc/mmc.c +++ b/drivers/mmc/mmc.c @@ -1,4 +1,7 @@ /* + * (C) Copyright 2008-2010 Freescale Semiconductor, Inc. + * Terry Lv + * * Copyright 2008, Freescale Semiconductor, Inc * Andy Fleming * @@ -32,16 +35,18 @@ #include #include #include +#include static struct list_head mmc_devices; static int cur_dev_num = -1; -int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) +static int mmc_send_cmd(struct mmc *mmc, + struct mmc_cmd *cmd, struct mmc_data *data) { return mmc->send_cmd(mmc, cmd, data); } -int mmc_set_blocklen(struct mmc *mmc, int len) +static int mmc_set_blocklen(struct mmc *mmc, int len) { struct mmc_cmd cmd; @@ -79,56 +84,71 @@ mmc_bwrite(int dev_num, ulong start, lbaint_t blkcnt, const void*src) int stoperr = 0; struct mmc *mmc = find_mmc_device(dev_num); int blklen; + lbaint_t blk_offset = 0, blk_left = blkcnt; if (!mmc) return -1; blklen = mmc->write_bl_len; +#ifdef CONFIG_EMMC_DDR_MODE + if (mmc->bus_width == EMMC_MODE_4BIT_DDR || + mmc->bus_width == EMMC_MODE_8BIT_DDR) { + err = 0; + blklen = 512; + } else +#endif err = mmc_set_blocklen(mmc, mmc->write_bl_len); if (err) { - printf("set write bl len failed\n\r"); + puts("set write bl len failed\n\r"); return err; } - if (blkcnt > 1) - cmd.cmdidx = MMC_CMD_WRITE_MULTIPLE_BLOCK; - else - cmd.cmdidx = MMC_CMD_WRITE_SINGLE_BLOCK; + do { + cmd.cmdidx = (blk_left > 1) \ + ? MMC_CMD_WRITE_MULTIPLE_BLOCK \ + : MMC_CMD_WRITE_SINGLE_BLOCK; - if (mmc->high_capacity) - cmd.cmdarg = start; - else - cmd.cmdarg = start * blklen; + cmd.cmdarg = (mmc->high_capacity) \ + ? (start + blk_offset) \ + : ((start + blk_offset) * blklen); - cmd.resp_type = MMC_RSP_R1; - cmd.flags = 0; + cmd.resp_type = MMC_RSP_R1; + cmd.flags = 0; - data.src = src; - data.blocks = blkcnt; - data.blocksize = blklen; - data.flags = MMC_DATA_WRITE; + data.src = src + blk_offset * blklen; + data.blocks = (blk_left > MAX_BLK_CNT) \ + ? MAX_BLK_CNT : blk_left; + data.blocksize = blklen; + data.flags = MMC_DATA_WRITE; - err = mmc_send_cmd(mmc, &cmd, &data); + err = mmc_send_cmd(mmc, &cmd, &data); - if (err) { - printf("mmc write failed\n\r"); - return err; - } + if (err) { + puts("mmc write failed\n\r"); + return err; + } - if (blkcnt > 1) { - cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION; - cmd.cmdarg = 0; - cmd.resp_type = MMC_RSP_R1b; - cmd.flags = 0; - stoperr = mmc_send_cmd(mmc, &cmd, NULL); - } + if (blk_left > 1) { + cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION; + cmd.cmdarg = 0; + cmd.resp_type = MMC_RSP_R1b; + cmd.flags = 0; + stoperr = mmc_send_cmd(mmc, &cmd, NULL); + } + + if (blk_left > MAX_BLK_CNT) { + blk_left -= MAX_BLK_CNT; + blk_offset += MAX_BLK_CNT; + } else + break; + } while (blk_left > 0); return blkcnt; } -int mmc_read_block(struct mmc *mmc, void *dst, uint blocknum) +static int mmc_read_block(struct mmc *mmc, void *dst, uint blocknum) { struct mmc_cmd cmd; struct mmc_data data; @@ -160,6 +180,12 @@ int mmc_read(struct mmc *mmc, u64 src, uchar *dst, int size) int endblock = lldiv(src + size - 1, mmc->read_bl_len); int err = 0; +#ifdef CONFIG_EMMC_DDR_MODE + if (mmc->bus_width == EMMC_MODE_4BIT_DDR || + mmc->bus_width == EMMC_MODE_8BIT_DDR) + blklen = 512; +#endif + /* Make a buffer big enough to hold all the blocks we might read */ buffer = malloc(blklen); @@ -168,11 +194,17 @@ int mmc_read(struct mmc *mmc, u64 src, uchar *dst, int size) return -1; } +#ifdef CONFIG_EMMC_DDR_MODE + if (mmc->bus_width == EMMC_MODE_4BIT_DDR || + mmc->bus_width == EMMC_MODE_8BIT_DDR) + err = 0; + else +#endif /* We always do full block reads from the card */ err = mmc_set_blocklen(mmc, mmc->read_bl_len); if (err) - return err; + goto free_buffer; for (i = startblock; i <= endblock; i++) { int segment_size; @@ -205,33 +237,76 @@ free_buffer: static ulong mmc_bread(int dev_num, ulong start, lbaint_t blkcnt, void *dst) { + struct mmc_cmd cmd; + struct mmc_data data; int err; - int i; + int stoperr = 0; struct mmc *mmc = find_mmc_device(dev_num); + int blklen; + lbaint_t blk_offset = 0, blk_left = blkcnt; if (!mmc) - return 0; + return -1; - /* We always do full block reads from the card */ - err = mmc_set_blocklen(mmc, mmc->read_bl_len); + if (mmc->bus_width == EMMC_MODE_4BIT_DDR || + mmc->bus_width == EMMC_MODE_8BIT_DDR) { + blklen = 512; + err = 0; + } else { + blklen = mmc->read_bl_len; + err = mmc_set_blocklen(mmc, blklen); + } if (err) { - return 0; + puts("set read bl len failed\n\r"); + return err; } - for (i = start; i < start + blkcnt; i++, dst += mmc->read_bl_len) { - err = mmc_read_block(mmc, dst, i); + do { + cmd.cmdidx = (blk_left > 1) \ + ? MMC_CMD_READ_MULTIPLE_BLOCK \ + : MMC_CMD_READ_SINGLE_BLOCK; + + cmd.cmdarg = (mmc->high_capacity) \ + ? (start + blk_offset) \ + : ((start + blk_offset) * blklen); + + cmd.resp_type = MMC_RSP_R1; + cmd.flags = 0; + + data.dest = dst + blk_offset * blklen; + data.blocks = (blk_left > MAX_BLK_CNT) ? MAX_BLK_CNT : blk_left; + data.blocksize = blklen; + data.flags = MMC_DATA_READ; + + err = mmc_send_cmd(mmc, &cmd, &data); if (err) { - printf("block read failed: %d\n", err); - return i - start; + puts("mmc read failed\n\r"); + return err; + } + + if (blk_left > 1) { + cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION; + cmd.cmdarg = 0; + cmd.resp_type = MMC_RSP_R1b; + cmd.flags = 0; + stoperr = mmc_send_cmd(mmc, &cmd, NULL); } - } + + if (blk_left > MAX_BLK_CNT) { + blk_left -= MAX_BLK_CNT; + blk_offset += MAX_BLK_CNT; + } else + break; + } while (blk_left > 0); return blkcnt; } -int mmc_go_idle(struct mmc* mmc) +#define CARD_STATE(r) ((u32)((r) & 0x1e00) >> 9) + +static int mmc_go_idle(struct mmc *mmc) { struct mmc_cmd cmd; int err; @@ -253,7 +328,7 @@ int mmc_go_idle(struct mmc* mmc) return 0; } -int +static int sd_send_op_cond(struct mmc *mmc) { int timeout = 1000; @@ -273,7 +348,15 @@ sd_send_op_cond(struct mmc *mmc) cmd.cmdidx = SD_CMD_APP_SEND_OP_COND; cmd.resp_type = MMC_RSP_R3; - cmd.cmdarg = mmc->voltages; + + /* + * Most cards do not answer if some reserved bits + * in the ocr are set. However, Some controller + * can set bit 7 (reserved for low voltages), but + * how to manage low voltages SD card is not yet + * specified. + */ + cmd.cmdarg = mmc->voltages & 0xff8000; if (mmc->version == SD_VERSION_2) cmd.cmdarg |= OCR_HCS; @@ -300,7 +383,7 @@ sd_send_op_cond(struct mmc *mmc) return 0; } -int mmc_send_op_cond(struct mmc *mmc) +static int mmc_send_op_cond(struct mmc *mmc) { int timeout = 1000; struct mmc_cmd cmd; @@ -336,7 +419,7 @@ int mmc_send_op_cond(struct mmc *mmc) } -int mmc_send_ext_csd(struct mmc *mmc, char *ext_csd) +static int mmc_send_ext_csd(struct mmc *mmc, char *ext_csd) { struct mmc_cmd cmd; struct mmc_data data; @@ -359,7 +442,7 @@ int mmc_send_ext_csd(struct mmc *mmc, char *ext_csd) } -int mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value) +static int mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value) { struct mmc_cmd cmd; @@ -373,9 +456,9 @@ int mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value) return mmc_send_cmd(mmc, &cmd, NULL); } -int mmc_change_freq(struct mmc *mmc) +static int mmc_change_freq(struct mmc *mmc) { - char ext_csd[512]; + char *ext_csd; char cardtype; int err; @@ -385,43 +468,71 @@ int mmc_change_freq(struct mmc *mmc) if (mmc->version < MMC_VERSION_4) return 0; - mmc->card_caps |= MMC_MODE_4BIT; + mmc->card_caps |= ((mmc->host_caps & MMC_MODE_8BIT) + ? MMC_MODE_8BIT : MMC_MODE_4BIT); + + ext_csd = (char *)malloc(512); + + if (!ext_csd) { + puts("Could not allocate buffer for MMC ext csd!\n"); + return -1; + } err = mmc_send_ext_csd(mmc, ext_csd); if (err) - return err; + goto err_rtn; - if (ext_csd[212] || ext_csd[213] || ext_csd[214] || ext_csd[215]) - mmc->high_capacity = 1; + if (mmc->high_capacity) { + mmc->capacity = ext_csd[EXT_CSD_SEC_CNT + 3] << 24 | + ext_csd[EXT_CSD_SEC_CNT + 2] << 16 | + ext_csd[EXT_CSD_SEC_CNT + 1] << 8 | + ext_csd[EXT_CSD_SEC_CNT]; + mmc->capacity *= 512; + } - cardtype = ext_csd[196] & 0xf; + cardtype = ext_csd[EXT_CSD_CARD_TYPE] & 0xf; err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_HS_TIMING, 1); if (err) - return err; + goto err_rtn; /* Now check to see that it worked */ err = mmc_send_ext_csd(mmc, ext_csd); if (err) - return err; + goto err_rtn; /* No high-speed support */ - if (!ext_csd[185]) - return 0; + if (!ext_csd[EXT_CSD_HS_TIMING]) + goto no_err_rtn; /* High Speed is set, there are two types: 52MHz and 26MHz */ if (cardtype & MMC_HS_52MHZ) mmc->card_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS; else mmc->card_caps |= MMC_MODE_HS; +#ifdef CONFIG_EMMC_DDR_MODE + if (cardtype & EMMC_MODE_DDR_3V) { + if (mmc->card_caps & MMC_MODE_8BIT) + mmc->card_caps |= EMMC_MODE_8BIT_DDR; + else + mmc->card_caps |= EMMC_MODE_4BIT_DDR; + } + +#endif +no_err_rtn: + free(ext_csd); return 0; + +err_rtn: + free(ext_csd); + return err; } -int sd_switch(struct mmc *mmc, int mode, int group, u8 value, u8 *resp) +static int sd_switch(struct mmc *mmc, int mode, int group, u8 value, u8 *resp) { struct mmc_cmd cmd; struct mmc_data data; @@ -443,7 +554,7 @@ int sd_switch(struct mmc *mmc, int mode, int group, u8 value, u8 *resp) } -int sd_change_freq(struct mmc *mmc) +static int sd_change_freq(struct mmc *mmc) { int err; struct mmc_cmd cmd; @@ -542,7 +653,7 @@ retry_scr: /* frequency bases */ /* divided by 10 to be nice to platforms without floating point */ -int fbase[] = { +static int fbase[] = { 10000, 100000, 1000000, @@ -552,7 +663,7 @@ int fbase[] = { /* Multiplier values for TRAN_SPEED. Multiplied by 10 to be nice * to platforms without floating point. */ -int multipliers[] = { +static int multipliers[] = { 0, /* reserved */ 10, 12, @@ -571,12 +682,12 @@ int multipliers[] = { 80, }; -void mmc_set_ios(struct mmc *mmc) +static void mmc_set_ios(struct mmc *mmc) { mmc->set_ios(mmc); } -void mmc_set_clock(struct mmc *mmc, uint clock) +static void mmc_set_clock(struct mmc *mmc, uint clock) { if (clock > mmc->f_max) clock = mmc->f_max; @@ -589,14 +700,209 @@ void mmc_set_clock(struct mmc *mmc, uint clock) mmc_set_ios(mmc); } -void mmc_set_bus_width(struct mmc *mmc, uint width) +static void mmc_set_bus_width(struct mmc *mmc, uint width) { mmc->bus_width = width; mmc_set_ios(mmc); } -int mmc_startup(struct mmc *mmc) +#ifdef CONFIG_BOOT_PARTITION_ACCESS +/* Return 0/1/2 for partition id before switch; Return -1 if fail to switch */ +int mmc_switch_partition(struct mmc *mmc, uint part, uint enable_boot) +{ + char *ext_csd; + int err; + uint old_part, new_part; + char boot_config; +#ifdef CONFIG_EMMC_DDR_MODE + char boot_bus_width, card_boot_bus_width; +#endif + + /* partition must be - + 0 - user area + 1 - boot partition 1 + 2 - boot partition 2 + */ + if (part > 2) { + printf("\nWrong partition id - " + "0 (user area), 1 (boot1), 2 (boot2)\n"); + return 1; + } + + /* Before calling this func, "mmc" struct must have been initialized */ + if (mmc->version < MMC_VERSION_4) { + puts("\nError: invalid mmc version! " + "mmc version is below version 4!"); + return -1; + } + + if (mmc->boot_size_mult <= 0) { + /* it's a normal SD/MMC but user request to boot partition */ + printf("\nError: This is a normal SD/MMC card but you" + "request to access boot partition\n"); + return -1; + } + + /* + * Part must be 0 (user area), 1 (boot partition1) + * or 2 (boot partition2) + */ + if (part > 2) { + puts("\nError: partition id must be 0(user area), " + "1(boot partition1) or 2(boot partition2)\n"); + return -1; + } + + ext_csd = (char *)malloc(512); + if (!ext_csd) { + puts("\nError: Could not allocate buffer for MMC ext csd!\n"); + return -1; + } + + err = mmc_send_ext_csd(mmc, ext_csd); + if (err) { + puts("\nWarning: fail to get ext csd for MMC!\n"); + goto err_rtn; + } + + old_part = ext_csd[EXT_CSD_BOOT_CONFIG] & + EXT_CSD_BOOT_PARTITION_ACCESS_MASK; + + /* Send SWITCH command to change partition for access */ + boot_config = (ext_csd[EXT_CSD_BOOT_CONFIG] & + ~EXT_CSD_BOOT_PARTITION_ACCESS_MASK) | + (char)part; + + /* enable access plus boot from that partition and boot_ack bit */ + if (enable_boot != 0) + boot_config = (char)(part) | (char)(part << 3) | (char)(1 << 6); + + err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, + EXT_CSD_BOOT_CONFIG, boot_config); + if (err) { + puts("\nError: fail to send SWITCH command to card " + "to swich partition for access!\n"); + goto err_rtn; + } + + /* Now check whether it works */ + err = mmc_send_ext_csd(mmc, ext_csd); + if (err) { + puts("\nWarning: fail to get ext csd for MMC!\n"); + goto err_rtn; + } + + new_part = ext_csd[EXT_CSD_BOOT_CONFIG] & + EXT_CSD_BOOT_PARTITION_ACCESS_MASK; + if ((char)part != new_part) { + printf("\nWarning: after SWITCH, current part id %d is " + "not same as requested partition %d!\n", + new_part, part); + goto err_rtn; + } + +#ifdef CONFIG_EMMC_DDR_MODE + /* Program boot_bus_width field for eMMC 4.4 boot mode */ + if ((ext_csd[EXT_CSD_CARD_TYPE] & 0xC) && enable_boot != 0) { + + /* Configure according to this host's capabilities */ + if (mmc->host_caps & EMMC_MODE_8BIT_DDR) + boot_bus_width = EXT_CSD_BOOT_BUS_WIDTH_DDR | + EXT_CSD_BOOT_BUS_WIDTH_8BIT; + else if (mmc->host_caps & EMMC_MODE_4BIT_DDR) + boot_bus_width = EXT_CSD_BOOT_BUS_WIDTH_DDR | + EXT_CSD_BOOT_BUS_WIDTH_4BIT; + else if (mmc->host_caps & MMC_MODE_8BIT) + boot_bus_width = EXT_CSD_BOOT_BUS_WIDTH_8BIT; + else if (mmc->host_caps & MMC_MODE_4BIT) + boot_bus_width = EXT_CSD_BOOT_BUS_WIDTH_4BIT; + else + boot_bus_width = 0; + + err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, + EXT_CSD_BOOT_BUS_WIDTH, boot_bus_width); + + /* Ensure that it programmed properly */ + err = mmc_send_ext_csd(mmc, ext_csd); + if (err) { + puts("\nWarning: fail to get ext csd for MMC!\n"); + goto err_rtn; + } + + card_boot_bus_width = ext_csd[EXT_CSD_BOOT_BUS_WIDTH]; + if (card_boot_bus_width != boot_bus_width) { + printf("\nWarning: current boot_bus_width, 0x%x, is " + "not same as requested boot_bus_width 0x%x!\n", + card_boot_bus_width, boot_bus_width); + goto err_rtn; + } + } +#endif + + /* Seems everything is ok, return the partition id before switch */ + free(ext_csd); + return old_part; + +err_rtn: + free(ext_csd); + return -1; +} + +int sd_switch_partition(struct mmc *mmc, uint part) +{ + struct mmc_cmd cmd; + int err; + + if (part > 1) { + printf("\nWrong partition id - 0 (user area), 1 (boot1)\n"); + return 1; + } + + cmd.cmdidx = SD_CMD_SELECT_PARTITION; + cmd.resp_type = MMC_RSP_R1; + cmd.cmdarg = part << 24; + cmd.flags = 0; + + err = mmc_send_cmd(mmc, &cmd, NULL); + + if (err) + return -1; + + return 0; +} + +static int mmc_get_cur_boot_partition(struct mmc *mmc) +{ + char *ext_csd; + int err; + + ext_csd = (char *)malloc(512); + + if (!ext_csd) { + puts("\nError! Could not allocate buffer for MMC ext csd!\n"); + return -1; + } + + err = mmc_send_ext_csd(mmc, ext_csd); + + if (err) { + mmc->boot_config = 0; + mmc->boot_size_mult = 0; + /* continue since it's not a fatal error */ + } else { + mmc->boot_config = ext_csd[EXT_CSD_BOOT_CONFIG]; + mmc->boot_size_mult = ext_csd[EXT_CSD_BOOT_SIZE_MULT]; + } + + free(ext_csd); + + return err; +} + +#endif + +static int mmc_startup(struct mmc *mmc) { int err; uint mult, freq; @@ -688,10 +994,25 @@ int mmc_startup(struct mmc *mmc) else mmc->write_bl_len = 1 << ((cmd.response[3] >> 22) & 0xf); - if (mmc->high_capacity) { - csize = (mmc->csd[1] & 0x3f) << 16 - | (mmc->csd[2] & 0xffff0000) >> 16; - cmult = 8; + if (IS_SD(mmc)) { + int csd_struct = (cmd.response[0] >> 30) & 0x3; + + switch (csd_struct) { + case 1: + csize = (mmc->csd[1] & 0x3f) << 16 + | (mmc->csd[2] & 0xffff0000) >> 16; + cmult = 8; + break; + case 0: + default: + if (0 != csd_struct) + printf("unrecognised CSD structure version %d\n", + csd_struct); + csize = (mmc->csd[1] & 0x3ff) << 2 + | (mmc->csd[2] & 0xc0000000) >> 30; + cmult = (mmc->csd[2] & 0x00038000) >> 15; + break; + } } else { csize = (mmc->csd[1] & 0x3ff) << 2 | (mmc->csd[2] & 0xc0000000) >> 30; @@ -777,6 +1098,32 @@ int mmc_startup(struct mmc *mmc) mmc_set_bus_width(mmc, 8); } +#ifdef CONFIG_EMMC_DDR_MODE + + if (mmc->card_caps & EMMC_MODE_8BIT_DDR) { + /* Set the card to use 8 bit DDR mode */ + err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, + EXT_CSD_BUS_WIDTH, + EXT_CSD_BUS_WIDTH_8_DDR); + if (err) + return err; + + + /* Setup the host controller for DDR mode */ + mmc_set_bus_width(mmc, EMMC_MODE_8BIT_DDR); + } else if (mmc->card_caps & EMMC_MODE_4BIT_DDR) { + /* Set the card to use 4 bit DDR mode */ + err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, + EXT_CSD_BUS_WIDTH, + EXT_CSD_BUS_WIDTH_4_DDR); + if (err) + return err; + + /* Setup the host controller for DDR mode */ + mmc_set_bus_width(mmc, EMMC_MODE_4BIT_DDR); + } +#endif + if (mmc->card_caps & MMC_MODE_HS) { if (mmc->card_caps & MMC_MODE_HS_52MHz) mmc_set_clock(mmc, 52000000); @@ -784,6 +1131,10 @@ int mmc_startup(struct mmc *mmc) mmc_set_clock(mmc, 26000000); } else mmc_set_clock(mmc, 20000000); + +#ifdef CONFIG_BOOT_PARTITION_ACCESS + mmc_get_cur_boot_partition(mmc); +#endif } /* fill in device description */ @@ -803,7 +1154,7 @@ int mmc_startup(struct mmc *mmc) return 0; } -int mmc_send_if_cond(struct mmc *mmc) +static int mmc_send_if_cond(struct mmc *mmc) { struct mmc_cmd cmd; int err; @@ -835,6 +1186,22 @@ int mmc_register(struct mmc *mmc) mmc->block_dev.removable = 1; mmc->block_dev.block_read = mmc_bread; mmc->block_dev.block_write = mmc_bwrite; +#if defined(CONFIG_DOS_PARTITION) + mmc->block_dev.part_type = PART_TYPE_DOS; + mmc->block_dev.type = DEV_TYPE_HARDDISK; +#elif defined(CONFIG_MAC_PARTITION) + mmc->block_dev.part_type = PART_TYPE_MAC; + mmc->block_dev.type = DEV_TYPE_HARDDISK; +#elif defined(CONFIG_ISO_PARTITION) + mmc->block_dev.part_type = PART_TYPE_ISO; + mmc->block_dev.type = DEV_TYPE_HARDDISK; +#elif defined(CONFIG_AMIGA_PARTITION) + mmc->block_dev.part_type = PART_TYPE_AMIGA; + mmc->block_dev.type = DEV_TYPE_HARDDISK; +#elif defined(CONFIG_EFI_PARTITION) + mmc->block_dev.part_type = PART_TYPE_EFI; + mmc->block_dev.type = DEV_TYPE_HARDDISK; +#endif INIT_LIST_HEAD (&mmc->link); @@ -928,3 +1295,4 @@ int mmc_initialize(bd_t *bis) return 0; } + diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile index 89ccec2802..cd0b76dca6 100644 --- a/drivers/mtd/nand/Makefile +++ b/drivers/mtd/nand/Makefile @@ -46,6 +46,9 @@ COBJS-$(CONFIG_NAND_S3C2410) += s3c2410_nand.o COBJS-$(CONFIG_NAND_S3C64XX) += s3c64xx.o COBJS-$(CONFIG_NAND_OMAP_GPMC) += omap_gpmc.o COBJS-$(CONFIG_NAND_PLAT) += nand_plat.o +COBJS-$(CONFIG_MX31_NAND) += mx31_nand.o +COBJS-$(CONFIG_MXC_NAND) += mxc_nand.o nand_device_info.o +COBJS-$(CONFIG_MXS_NAND) += mxs_gpmi.o endif COBJS := $(COBJS-y) diff --git a/drivers/mtd/nand/mx31_nand.c b/drivers/mtd/nand/mx31_nand.c new file mode 100644 index 0000000000..867f34762d --- /dev/null +++ b/drivers/mtd/nand/mx31_nand.c @@ -0,0 +1,968 @@ +/* + * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include + +/* + * Define delays in microsec for NAND device operations + */ +#define TROP_US_DELAY 2000 + +/* + * Macros to get byte and bit positions of ECC + */ +#define COLPOS(x) ((x) >> 4) +#define BITPOS(x) ((x) & 0xf) + +/* Define single bit Error positions in Main & Spare area */ +#define MAIN_SINGLEBIT_ERROR 0x4 +#define SPARE_SINGLEBIT_ERROR 0x1 + +struct nand_info { + int oob; + int read_status; + int largepage; + u16 col; +}; + +static struct nand_info nandinfo; +static int ecc_disabled; + +/* + * OOB placement block for use with hardware ecc generation + */ +static struct nand_ecclayout nand_hw_eccoob_8 = { + .eccbytes = 5, + .eccpos = {6, 7, 8, 9, 10}, + .oobfree = { + {0, 5}, + {11, 5} + } +}; + +static struct nand_ecclayout nand_hw_eccoob_2k = { + .eccbytes = 20, + .eccpos = {6, 7, 8, 9, 10, 22, 23, 24, 25, 26, + 38, 39, 40, 41, 42, 54, 55, 56, 57, 58}, + .oobfree = { + {0, 5}, + {11, 10}, + {27, 10}, + {43, 10}, + {59, 5} + } +}; + +/* Define some generic bad / good block scan pattern which are used + * while scanning a device for factory marked good / bad blocks. */ +static uint8_t scan_ff_pattern[] = { 0xff, 0xff }; + +static struct nand_bbt_descr smallpage_memorybased = { + .options = NAND_BBT_SCAN2NDPAGE, + .offs = 5, + .len = 1, + .pattern = scan_ff_pattern +}; + +static struct nand_bbt_descr largepage_memorybased = { + .options = 0, + .offs = 0, + .len = 2, + .pattern = scan_ff_pattern +}; + +/* Generic flash bbt decriptors */ +static uint8_t bbt_pattern[] = { 'B', 'b', 't', '0' }; +static uint8_t mirror_pattern[] = { '1', 't', 'b', 'B' }; + +static struct nand_bbt_descr bbt_main_descr = { + .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE + | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP, + .offs = 0, + .len = 4, + .veroffs = 4, + .maxblocks = 4, + .pattern = bbt_pattern +}; + +static struct nand_bbt_descr bbt_mirror_descr = { + .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE + | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP, + .offs = 0, + .len = 4, + .veroffs = 4, + .maxblocks = 4, + .pattern = mirror_pattern +}; + +/** + * memcpy variant that copies 32 bit words. This is needed since the + * NFC only allows 32 bit accesses. Added for U-boot. + */ +static void *memcpy_32(void *dest, const void *src, size_t n) +{ + u32 *dst_32 = (u32 *) dest; + const u32 *src_32 = (u32 *) src; + + while (n > 0) { + *dst_32++ = *src_32++; + n -= 4; + } + + return dest; +} + +/** + * This function polls the NANDFC to wait for the basic operation to + * complete by checking the INT bit of config2 register. + * + * @param max_retries number of retry attempts (separated by 1 us) + */ +static void wait_op_done(int max_retries) +{ + while (max_retries-- > 0) { + if (NFC_CONFIG2 & NFC_INT) { + NFC_CONFIG2 &= ~NFC_INT; + break; + } + udelay(1); + } + if (max_retries <= 0) + MTDDEBUG(MTD_DEBUG_LEVEL0, "wait: INT not set\n"); +} + +/** + * This function issues the specified command to the NAND device and + * waits for completion. + * + * @param cmd command for NAND Flash + */ +static void send_cmd(u16 cmd) +{ + MTDDEBUG(MTD_DEBUG_LEVEL3, "send_cmd(0x%x)\n", cmd); + + NFC_FLASH_CMD = (u16) cmd; + NFC_CONFIG2 = NFC_CMD; + + /* Wait for operation to complete */ + wait_op_done(TROP_US_DELAY); +} + +/** + * This function sends an address (or partial address) to the + * NAND device. The address is used to select the source/destination for + * a NAND command. + * + * @param addr address to be written to NFC. + * @param islast 1 if this is the last address cycle for command + */ +static void send_addr(u16 addr) +{ + MTDDEBUG(MTD_DEBUG_LEVEL3, "send_addr(0x%x %d)\n", addr); + + NFC_FLASH_ADDR = addr; + NFC_CONFIG2 = NFC_ADDR; + + /* Wait for operation to complete */ + wait_op_done(TROP_US_DELAY); +} + +/** + * This function requests the NANDFC to initate the transfer + * of data currently in the NANDFC RAM buffer to the NAND device. + * + * @param buf_id Specify Internal RAM Buffer number (0-3) + * @param oob set to 1 if only the spare area is transferred + */ +static void send_prog_page(u8 buf_id) +{ + MTDDEBUG(MTD_DEBUG_LEVEL3, "send_prog_page (%d)\n", nandinfo.oob); + + /* NANDFC buffer 0 is used for page read/write */ + + NFC_BUF_ADDR = buf_id; + + /* Configure spare or page+spare access */ + if (!nandinfo.largepage) { + if (nandinfo.oob) + NFC_CONFIG1 |= NFC_SP_EN; + else + NFC_CONFIG1 &= ~NFC_SP_EN; + } + NFC_CONFIG2 = NFC_INPUT; + + /* Wait for operation to complete */ + wait_op_done(TROP_US_DELAY); +} + +/** + * This function will correct the single bit ECC error + * + * @param buf_id Specify Internal RAM Buffer number (0-3) + * @param eccpos Ecc byte and bit position + * @param oob set to 1 if only spare area needs correction + */ +static void mxc_nd_correct_error(u8 buf_id, u16 eccpos, int oob) +{ + u16 col; + u8 pos; + u16 *buf; + + /* Get col & bit position of error + these macros works for both 8 & 16 bits */ + col = COLPOS(eccpos); /* Get half-word position */ + pos = BITPOS(eccpos); /* Get bit position */ + + MTDDEBUG(MTD_DEBUG_LEVEL3, + "mxc_nd_correct_error (col=%d pos=%d)\n", col, pos); + + /* Set the pointer for main / spare area */ + if (!oob) + buf = (u16 *)(MAIN_AREA0 + col + (256 * buf_id)); + else + buf = (u16 *)(SPARE_AREA0 + col + (8 * buf_id)); + + /* Fix the data */ + *buf ^= 1 << pos; +} + +/** + * This function will maintains state of single bit Error + * in Main & spare area + * + * @param buf_id Specify Internal RAM Buffer number (0-3) + * @param spare set to 1 if only spare area needs correction + */ +static void mxc_nd_correct_ecc(u8 buf_id, int spare) +{ + u16 value, ecc_status; + + /* Read the ECC result */ + ecc_status = NFC_ECC_STATUS_RESULT; + MTDDEBUG(MTD_DEBUG_LEVEL3, + "mxc_nd_correct_ecc (Ecc status=%x)\n", ecc_status); + + if (((ecc_status & 0xC) == MAIN_SINGLEBIT_ERROR) + || ((ecc_status & 0x3) == SPARE_SINGLEBIT_ERROR)) { + if (ecc_disabled) { + if ((ecc_status & 0xC) == MAIN_SINGLEBIT_ERROR) { + value = NFC_RSLTMAIN_AREA; + /* Correct single bit error in Mainarea + NFC will not correct the error in + current page */ + mxc_nd_correct_error(buf_id, value, 0); + } + if ((ecc_status & 0x3) == SPARE_SINGLEBIT_ERROR) { + value = NFC_RSLTSPARE_AREA; + /* Correct single bit error in Mainarea + NFC will not correct the error in + current page */ + mxc_nd_correct_error(buf_id, value, 1); + } + + } else { + /* Disable ECC */ + NFC_CONFIG1 &= ~NFC_ECC_EN; + ecc_disabled = 1; + } + } else if (ecc_status == 0) { + if (ecc_disabled) { + /* Enable ECC */ + NFC_CONFIG1 |= NFC_ECC_EN; + ecc_disabled = 0; + } + } /* else 2-bit Error. Do nothing */ +} + +/** + * This function requests the NANDFC to initated the transfer + * of data from the NAND device into in the NANDFC ram buffer. + * + * @param buf_id Specify Internal RAM Buffer number (0-3) + * @param oob set 1 if only the spare area is + * transferred + */ +static void send_read_page(u8 buf_id) +{ + MTDDEBUG(MTD_DEBUG_LEVEL3, "send_read_page (%d)\n", nandinfo.oob); + + /* NANDFC buffer 0 is used for page read/write */ + NFC_BUF_ADDR = buf_id; + + /* Configure spare or page+spare access */ + if (!nandinfo.largepage) { + if (nandinfo.oob) + NFC_CONFIG1 |= NFC_SP_EN; + else + NFC_CONFIG1 &= ~NFC_SP_EN; + } + + NFC_CONFIG2 = NFC_OUTPUT; + + /* Wait for operation to complete */ + wait_op_done(TROP_US_DELAY); + + /* If there are single bit errors in + two consecutive page reads then + the error is not corrected by the + NFC for the second page. + Correct single bit error in driver */ + + mxc_nd_correct_ecc(buf_id, nandinfo.oob); +} + +/** + * This function requests the NANDFC to perform a read of the + * NAND device ID. + */ +static void send_read_id(void) +{ + /* NANDFC buffer 0 is used for device ID output */ + NFC_BUF_ADDR = 0x0; + + /* Read ID into main buffer */ + NFC_CONFIG1 &= ~NFC_SP_EN; + NFC_CONFIG2 = NFC_ID; + + /* Wait for operation to complete */ + wait_op_done(TROP_US_DELAY); +} + +/** + * This function requests the NANDFC to perform a read of the + * NAND device status and returns the current status. + * + * @return device status + */ +static u16 get_dev_status(void) +{ + volatile u16 *mainbuf = MAIN_AREA1; + u32 store; + u16 ret; + /* Issue status request to NAND device */ + + /* store the main area1 first word, later do recovery */ + store = *((u32 *) mainbuf); + /* + * NANDFC buffer 1 is used for device status to prevent + * corruption of read/write buffer on status requests. + */ + NFC_BUF_ADDR = 1; + + /* Read status into main buffer */ + NFC_CONFIG1 &= ~NFC_SP_EN; + NFC_CONFIG2 = NFC_STATUS; + + /* Wait for operation to complete */ + wait_op_done(TROP_US_DELAY); + + /* Status is placed in first word of main buffer */ + /* get status, then recovery area 1 data */ + ret = mainbuf[0]; + *((u32 *) mainbuf) = store; + + return ret; +} + +static void mxc_nand_enable_hwecc(struct mtd_info *mtd, int mode) +{ + /* + * If HW ECC is enabled, we turn it on during init. There is + * no need to enable again here. + */ +} + +static int mxc_nand_correct_data(struct mtd_info *mtd, unsigned char *dat, + unsigned char *read_ecc, unsigned char *calc_ecc) +{ + /* + * 1-Bit errors are automatically corrected in HW. No need for + * additional correction. 2-Bit errors cannot be corrected by + * HW ECC, so we need to return failure + */ + u16 ecc_status = NFC_ECC_STATUS_RESULT; + + if (((ecc_status & 0x3) == 2) || ((ecc_status >> 2) == 2)) { + MTDDEBUG(MTD_DEBUG_LEVEL0, + "MXC_NAND: HWECC uncorrectable 2-bit ECC error\n"); + return -1; + } + + return 0; +} + +static int mxc_nand_calculate_ecc(struct mtd_info *mtd, const unsigned char *dat, + unsigned char *ecc_code) +{ + /* + * Just return success. HW ECC does not read/write the NFC spare + * buffer. Only the FLASH spare area contains the calcuated ECC. + */ + return 0; +} + +/** + * This function reads byte from the NAND Flash + * + * @param mtd MTD structure for the NAND Flash + * + * @return data read from the NAND Flash + */ +static unsigned char mxc_nand_read_byte(struct mtd_info *mtd) +{ + unsigned char ret_val = 0; + u16 col, rd_word; + volatile u16 *mainbuf = MAIN_AREA0; + volatile u16 *sparebuf = SPARE_AREA0; + + /* Check for status request */ + if (nandinfo.read_status) + return get_dev_status() & 0xFF; + + /* Get column for 16-bit access */ + col = nandinfo.col >> 1; + + /* If we are accessing the spare region */ + if (nandinfo.oob) + rd_word = sparebuf[col]; + else + rd_word = mainbuf[col]; + + /* Pick upper/lower byte of word from RAM buffer */ + if (nandinfo.col & 0x1) + ret_val = (rd_word >> 8) & 0xFF; + else + ret_val = rd_word & 0xFF; + + /* Update saved column address */ + nandinfo.col++; + + return ret_val; +} + +/** + * This function reads word from the NAND Flash + * + * @param mtd MTD structure for the NAND Flash + * + * @return data read from the NAND Flash + */ +static u16 mxc_nand_read_word(struct mtd_info *mtd) +{ + u16 col; + u16 rd_word, ret_val; + volatile u16 *p; + + MTDDEBUG(MTD_DEBUG_LEVEL3, "mxc_nand_read_word(col = %d)\n", nandinfo.col); + + col = nandinfo.col; + /* Adjust saved column address */ + if (col < mtd->writesize && nandinfo.oob) + col += mtd->writesize; + + if (col < mtd->writesize) + p = (MAIN_AREA0) + (col >> 1); + else + p = (SPARE_AREA0) + ((col - mtd->writesize) >> 1); + + if (col & 1) { + rd_word = *p; + ret_val = (rd_word >> 8) & 0xff; + rd_word = *(p + 1); + ret_val |= (rd_word << 8) & 0xff00; + + } else + ret_val = *p; + + /* Update saved column address */ + nandinfo.col = col + 2; + + return ret_val; +} + +/** + * This function writes data of length \b len to buffer \b buf. The data + * to be written on NAND Flash is first copied to RAMbuffer. After the + * Data Input Operation by the NFC, the data is written to NAND Flash. + * + * @param mtd MTD structure for the NAND Flash + * @param buf data to be written to NAND Flash + * @param len number of bytes to be written + */ +static void mxc_nand_write_buf(struct mtd_info *mtd, + const unsigned char *buf, int len) +{ + int n; + int col; + int i = 0; + + MTDDEBUG(MTD_DEBUG_LEVEL3, + "mxc_nand_write_buf(col = %d, len = %d)\n", nandinfo.col, len); + + col = nandinfo.col; + + /* Adjust saved column address */ + if (col < mtd->writesize && nandinfo.oob) + col += mtd->writesize; + + n = mtd->writesize + mtd->oobsize - col; + if (len > mtd->writesize + mtd->oobsize - col) + MTDDEBUG(MTD_DEBUG_LEVEL1, "Error: too much data.\n"); + + n = min(len, n); + + MTDDEBUG(MTD_DEBUG_LEVEL3, + "%s:%d: col = %d, n = %d\n", __FUNCTION__, __LINE__, col, n); + + while (n) { + volatile u32 *p; + if (col < mtd->writesize) + p = (volatile u32 *)((ulong) (MAIN_AREA0) + (col & ~3)); + else + p = (volatile u32 *)((ulong) (SPARE_AREA0) - + mtd->writesize + (col & ~3)); + + MTDDEBUG(MTD_DEBUG_LEVEL3, "%s:%d: p = %p\n", + __FUNCTION__, __LINE__, p); + + if (((col | (int)&buf[i]) & 3) || n < 16) { + u32 data = 0; + + if (col & 3 || n < 4) + data = *p; + + switch (col & 3) { + case 0: + if (n) { + data = (data & 0xffffff00) | + (buf[i++] << 0); + n--; + col++; + } + case 1: + if (n) { + data = (data & 0xffff00ff) | + (buf[i++] << 8); + n--; + col++; + } + case 2: + if (n) { + data = (data & 0xff00ffff) | + (buf[i++] << 16); + n--; + col++; + } + case 3: + if (n) { + data = (data & 0x00ffffff) | + (buf[i++] << 24); + n--; + col++; + } + } + + *p = data; + } else { + int m = mtd->writesize - col; + + if (col >= mtd->writesize) + m += mtd->oobsize; + + m = min(n, m) & ~3; + + MTDDEBUG(MTD_DEBUG_LEVEL3, + "%s:%d: n = %d, m = %d, i = %d, col = %d\n", + __FUNCTION__, __LINE__, n, m, i, col); + + memcpy_32((void *)(p), &buf[i], m); + col += m; + i += m; + n -= m; + } + } + /* Update saved column address */ + nandinfo.col = col; +} + +/** + * This function id is used to read the data buffer from the NAND Flash. To + * read the data from NAND Flash first the data output cycle is initiated by + * the NFC, which copies the data to RAMbuffer. This data of length \b len is + * then copied to buffer \b buf. + * + * @param mtd MTD structure for the NAND Flash + * @param buf data to be read from NAND Flash + * @param len number of bytes to be read + */ +static void mxc_nand_read_buf(struct mtd_info *mtd, unsigned char *buf, int len) +{ + int n; + int col; + int i = 0; + + MTDDEBUG(MTD_DEBUG_LEVEL3, + "mxc_nand_read_buf(col = %d, len = %d)\n", nandinfo.col, len); + + col = nandinfo.col; + /** + * Adjust saved column address + * for nand_read_oob will pass col within oobsize + */ + if (col < mtd->writesize && nandinfo.oob) + col += mtd->writesize; + + n = mtd->writesize + mtd->oobsize - col; + n = min(len, n); + + while (n) { + volatile u32 *p; + + if (col < mtd->writesize) + p = (volatile u32 *)((ulong) (MAIN_AREA0) + (col & ~3)); + else + p = (volatile u32 *)((ulong) (SPARE_AREA0) - + mtd->writesize + (col & ~3)); + + if (((col | (int)&buf[i]) & 3) || n < 16) { + u32 data; + + data = *p; + switch (col & 3) { + case 0: + if (n) { + buf[i++] = (u8) (data); + n--; + col++; + } + case 1: + if (n) { + buf[i++] = (u8) (data >> 8); + n--; + col++; + } + case 2: + if (n) { + buf[i++] = (u8) (data >> 16); + n--; + col++; + } + case 3: + if (n) { + buf[i++] = (u8) (data >> 24); + n--; + col++; + } + } + } else { + int m = mtd->writesize - col; + + if (col >= mtd->writesize) + m += mtd->oobsize; + + m = min(n, m) & ~3; + memcpy_32(&buf[i], (void *)(p), m); + col += m; + i += m; + n -= m; + } + } + /* Update saved column address */ + nandinfo.col = col; +} + +/** + * This function is used by the upper layer to verify the data in NAND Flash + * with the data in the \b buf. + * + * @param mtd MTD structure for the NAND Flash + * @param buf data to be verified + * @param len length of the data to be verified + * + * @return -EFAULT if error else 0 + */ +static int +mxc_nand_verify_buf(struct mtd_info *mtd, const unsigned char *buf, int len) +{ + return -1; /* Was -EFAULT */ +} + +/** + * This function is used by upper layer for select and deselect of the NAND + * chip. + * + * @param mtd MTD structure for the NAND Flash + * @param chip val indicating select or deselect + */ +static void mxc_nand_select_chip(struct mtd_info *mtd, int chip) +{ +} + +/** + * This function is used by the upper layer to write command to NAND Flash + * for different operations to be carried out on NAND Flash + * + * @param mtd MTD structure for the NAND Flash + * @param command command for NAND Flash + * @param column column offset for the page read + * @param page_addr page to be read from NAND Flash + */ +static void mxc_nand_command(struct mtd_info *mtd, unsigned command, + int column, int page_addr) +{ + MTDDEBUG(MTD_DEBUG_LEVEL3, + "mxc_nand_command (cmd = 0x%x, col = 0x%x, page = 0x%x)\n", + command, column, page_addr); + + /* Reset command state information */ + nandinfo.read_status = 0; + nandinfo.oob = 0; + + /* Command pre-processing step */ + switch (command) { + + case NAND_CMD_STATUS: + nandinfo.col = 0; + nandinfo.read_status = 1; + break; + + case NAND_CMD_READ0: + nandinfo.col = column; + break; + + case NAND_CMD_READOOB: + nandinfo.col = column; + nandinfo.oob = 1; + if (nandinfo.largepage) + command = NAND_CMD_READ0; + break; + + case NAND_CMD_SEQIN: + if (column >= mtd->writesize) { + /* write oob routine caller */ + if (nandinfo.largepage) { + /* + * FIXME: before send SEQIN command for + * write OOB, we must read one page out. + * For 2K nand has no READ1 command to set + * current HW pointer to spare area, we must + * write the whole page including OOB together. + */ + /* call itself to read a page */ + mxc_nand_command(mtd, NAND_CMD_READ0, 0, + page_addr); + } + nandinfo.col = column - mtd->writesize; + nandinfo.oob = 1; + /* Set program pointer to spare region */ + if (!nandinfo.largepage) + send_cmd(NAND_CMD_READOOB); + } else { + nandinfo.oob = 0; + nandinfo.col = column; + /* Set program pointer to page start */ + if (!nandinfo.largepage) + send_cmd(NAND_CMD_READ0); + } + break; + + case NAND_CMD_PAGEPROG: + if (ecc_disabled) { + /* Enable Ecc for page writes */ + NFC_CONFIG1 |= NFC_ECC_EN; + } + send_prog_page(0); + + if (nandinfo.largepage) { + /* data in 4 areas datas */ + send_prog_page(1); + send_prog_page(2); + send_prog_page(3); + } + + break; + + case NAND_CMD_ERASE1: + break; + } + + /* + * Write out the command to the device. + */ + send_cmd(command); + + /* + * Write out column address, if necessary + */ + if (column != -1) { + /* + * MXC NANDFC can only perform full page+spare or + * spare-only read/write. When the upper layers + * layers perform a read/write buf operation, + * we will used the saved column adress to index into + * the full page. + */ + send_addr(0); + if (nandinfo.largepage) + /* another col addr cycle for 2k page */ + send_addr(0); + } + + /* + * Write out page address, if necessary + */ + if (page_addr != -1) { + /* paddr_0 - p_addr_7 */ + send_addr((page_addr & 0xff)); + + if (nandinfo.largepage) { + /* One more address cycle for higher + * density devices */ + + if (mtd->size >= 0x10000000) { + /* paddr_8 - paddr_15 */ + send_addr((page_addr >> 8) & 0xff); + send_addr((page_addr >> 16) & 0xff); + } else + /* paddr_8 - paddr_15 */ + send_addr((page_addr >> 8) & 0xff); + } else { + /* One more address cycle for higher + * density devices */ + + if (mtd->size >= 0x4000000) { + /* paddr_8 - paddr_15 */ + send_addr((page_addr >> 8) & 0xff); + send_addr((page_addr >> 16) & 0xff); + } else + /* paddr_8 - paddr_15 */ + send_addr((page_addr >> 8) & 0xff); + } + } + + /* + * Command post-processing step + */ + switch (command) { + + case NAND_CMD_RESET: + break; + + case NAND_CMD_READOOB: + case NAND_CMD_READ0: + if (nandinfo.largepage) { + /* send read confirm command */ + send_cmd(NAND_CMD_READSTART); + /* read for each AREA */ + send_read_page(0); + send_read_page(1); + send_read_page(2); + send_read_page(3); + } else + send_read_page(0); + break; + + case NAND_CMD_READID: + send_read_id(); + nandinfo.col = column; + break; + + case NAND_CMD_PAGEPROG: + if (ecc_disabled) { + /* Disable Ecc after page writes */ + NFC_CONFIG1 &= ~NFC_ECC_EN; + } + break; + + case NAND_CMD_ERASE2: + break; + } +} + +static int mxc_nand_scan_bbt(struct mtd_info *mtd) +{ + struct nand_chip *this = mtd->priv; + + /* Config before scanning */ + /* Do not rely on NFMS_BIT, set/clear NFMS bit based + * on mtd->writesize */ + if (mtd->writesize == 2048) + NFMS |= 1 << NFMS_BIT; + else if ((NFMS >> NFMS_BIT) & 0x1) + NFMS &= ~(1 << NFMS_BIT); + + /* use flash based bbt */ + this->bbt_td = &bbt_main_descr; + this->bbt_md = &bbt_mirror_descr; + + /* update flash based bbt */ + this->options |= NAND_USE_FLASH_BBT; + + if (!this->badblock_pattern) { + if (nandinfo.largepage) + this->badblock_pattern = &smallpage_memorybased; + else + this->badblock_pattern = (mtd->writesize > 512) ? + &largepage_memorybased : &smallpage_memorybased; + } + /* Build bad block table */ + return nand_scan_bbt(mtd, this->badblock_pattern); +} + +int board_nand_init(struct nand_chip *nand) +{ + nand->chip_delay = 0; + + nand->cmdfunc = mxc_nand_command; + nand->select_chip = mxc_nand_select_chip; + nand->read_byte = mxc_nand_read_byte; + nand->read_word = mxc_nand_read_word; + nand->write_buf = mxc_nand_write_buf; + nand->read_buf = mxc_nand_read_buf; + nand->verify_buf = mxc_nand_verify_buf; + nand->scan_bbt = mxc_nand_scan_bbt; + nand->ecc.calculate = mxc_nand_calculate_ecc; + nand->ecc.correct = mxc_nand_correct_data; + nand->ecc.hwctl = mxc_nand_enable_hwecc; + nand->ecc.mode = NAND_ECC_HW; + nand->ecc.bytes = 3; + nand->ecc.size = 512; + + /* Reset NAND */ + NFC_CONFIG1 |= NFC_INT_MSK | NFC_RST | NFC_ECC_EN; + + /* Unlock the internal RAM buffer */ + NFC_CONFIG = 0x2; + + /* Block to be unlocked */ + NFC_UNLOCKSTART_BLKADDR = 0x0; + NFC_UNLOCKEND_BLKADDR = 0x4000; + + /* Unlock Block Command for given address range */ + NFC_WRPROT = 0x4; + + /* Only 8 bit bus support for now */ + nand->options |= 0; + + if ((NFMS >> NFMS_BIT) & 1) { + nandinfo.largepage = 1; + nand->ecc.layout = &nand_hw_eccoob_2k; + } else { + nandinfo.largepage = 0; + nand->ecc.layout = &nand_hw_eccoob_8; + } + + return 0; +} diff --git a/drivers/mtd/nand/mxc_nand.c b/drivers/mtd/nand/mxc_nand.c new file mode 100644 index 0000000000..ccb7af17b7 --- /dev/null +++ b/drivers/mtd/nand/mxc_nand.c @@ -0,0 +1,1348 @@ +/* + * Copyright 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include +#include +#include "nand_device_info.h" + +struct nand_info { + int status_req; + int large_page; + int auto_mode; + u16 col_addr; + u8 num_of_intlv; + int page_mask; + int hw_ecc; + u8 *data_buf; + u8 *oob_buf; +}; + +/* + * Define delays in microsec for NAND device operations + */ +#define TROP_US_DELAY 2000 + +/* + * OOB placement block for use with hardware ecc generation + */ +static struct nand_ecclayout nand_hw_eccoob_512 = { + .eccbytes = 9, + .eccpos = {7, 8, 9, 10, 11, 12, 13, 14, 15}, + .oobfree = {{0, 4} } +}; + +static struct nand_ecclayout nand_hw_eccoob_2k = { + .eccbytes = 9, + .eccpos = {7, 8, 9, 10, 11, 12, 13, 14, 15}, + .oobfree = {{2, 4} } +}; + +static struct nand_ecclayout nand_hw_eccoob_4k = { + .eccbytes = 9, + .eccpos = {7, 8, 9, 10, 11, 12, 13, 14, 15}, + .oobfree = {{2, 4} } +}; + + +static void mxc_nand_bi_swap(struct mtd_info *mtd) +{ + struct nand_chip *this = mtd->priv; + struct nand_info *info = this->priv; + u16 ma, sa, nma, nsa; + + if (!IS_LARGE_PAGE_NAND) + return; + + ma = __raw_readw(BAD_BLK_MARKER_MAIN); + sa = __raw_readw(BAD_BLK_MARKER_SP); + + nma = (ma & 0xFF00) | (sa >> 8); + nsa = (sa & 0x00FF) | (ma << 8); + + __raw_writew(nma, BAD_BLK_MARKER_MAIN); + __raw_writew(nsa, BAD_BLK_MARKER_SP); + +} + +/*! + * @defgroup NAND_MTD NAND Flash MTD Driver for MXC processors + */ + +/*! + * @file mxc_nd2.c + * + * @brief This file contains the hardware specific layer for NAND Flash on + * MXC processor + * + * @ingroup NAND_MTD + */ + +/*! + * Half word access.Added for U-boot. + */ +static void *nfc_memcpy(void *dest, const void *src, size_t n) +{ + u16 *dst_16 = (u16 *) dest; + const u16 *src_16 = (u16 *) src; + + while (n > 0) { + *dst_16++ = *src_16++; + n -= 2; + } + + return dest; +} + +/* + * Functions to transfer data to/from spare erea. + */ +static void +copy_spare(struct mtd_info *mtd, void *pbuf, void *pspare, int len, int bfrom) +{ + u16 i, j; + u16 m = mtd->oobsize; + u16 n = mtd->writesize >> 9; + u8 *d = (u8 *) pbuf; + u8 *s = (u8 *) pspare; + u16 t = SPARE_LEN; + struct nand_chip *this = mtd->priv; + struct nand_info *info = this->priv; + + m /= info->num_of_intlv; + n /= info->num_of_intlv; + + j = (m / n >> 1) << 1; + + if (bfrom) { + for (i = 0; i < n - 1; i++) + nfc_memcpy(&d[i * j], &s[i * t], j); + + /* the last section */ + nfc_memcpy(&d[i * j], &s[i * t], len - i * j); + } else { + for (i = 0; i < n - 1; i++) + nfc_memcpy(&s[i * t], &d[i * j], j); + + /* the last section */ + nfc_memcpy(&s[i * t], &d[i * j], len - i * j); + } +} + +/*! + * This function polls the NFC to wait for the basic operation to complete by + * checking the INT bit of config2 register. + * + * @param maxRetries number of retry attempts (separated by 1 us) + * @param useirq True if IRQ should be used rather than polling + */ +static void wait_op_done(int max_retries) +{ + + while (max_retries-- > 0) { + if (raw_read(REG_NFC_OPS_STAT) & NFC_OPS_STAT) { + WRITE_NFC_IP_REG((raw_read(REG_NFC_OPS_STAT) & + ~NFC_OPS_STAT), + REG_NFC_OPS_STAT); + break; + } + udelay(1); + } + if (max_retries <= 0) + MTDDEBUG(MTD_DEBUG_LEVEL0, "wait: INT not set\n"); +} + +/*! + * This function sends an address (or partial address) to the + * NAND device. The address is used to select the source/destination for + * a NAND command. + * + * @param addr address to be written to NFC. + * @param useirq True if IRQ should be used rather than polling + */ +static void send_addr(u16 addr) +{ + MTDDEBUG(MTD_DEBUG_LEVEL3, "send_addr(0x%x)\n", addr); + + /* fill address */ + raw_write((addr << NFC_FLASH_ADDR_SHIFT), REG_NFC_FLASH_ADDR); + + /* clear status */ + ACK_OPS; + + /* send out address */ + raw_write(NFC_ADDR, REG_NFC_OPS); + + /* Wait for operation to complete */ + wait_op_done(TROP_US_DELAY); +} + +static void mxc_do_addr_cycle_auto(struct mtd_info *mtd, int column, + int page_addr) +{ +#ifdef CONFIG_MXC_NFC_SP_AUTO + if (page_addr != -1 && column != -1) { + u32 mask = 0xFFFF; + /* the column address */ + raw_write(column & mask, NFC_FLASH_ADDR0); + raw_write((raw_read(NFC_FLASH_ADDR0) | + ((page_addr & mask) << 16)), NFC_FLASH_ADDR0); + /* the row address */ + raw_write(((raw_read(NFC_FLASH_ADDR8) & (mask << 16)) | + ((page_addr & (mask << 16)) >> 16)), + NFC_FLASH_ADDR8); + } else if (page_addr != -1) { + raw_write(page_addr, NFC_FLASH_ADDR0); + } + + MTDDEBUG(MTD_DEBUG_LEVEL3, + "AutoMode:the ADDR REGS value is (0x%x, 0x%x)\n", + raw_read(NFC_FLASH_ADDR0), raw_read(NFC_FLASH_ADDR8)); +#endif +} + +static void mxc_do_addr_cycle_atomic(struct mtd_info *mtd, int column, + int page_addr) +{ + struct nand_chip *this = mtd->priv; + struct nand_info *info = this->priv; + + u32 page_mask = info->page_mask; + + if (column != -1) { + send_addr(column & 0xFF); + if (IS_2K_PAGE_NAND) { + /* another col addr cycle for 2k page */ + send_addr((column >> 8) & 0xF); + } else if (IS_4K_PAGE_NAND) { + /* another col addr cycle for 4k page */ + send_addr((column >> 8) & 0x1F); + } + } + if (page_addr != -1) { + do { + send_addr(page_addr & 0xff); + page_mask >>= 8; + page_addr >>= 8; + } while (page_mask != 0); + } +} + +/* + * Function to perform the address cycles. + */ +static void mxc_nand_addr_cycle(struct mtd_info *mtd, int column, int page_addr) +{ + struct nand_chip *this = mtd->priv; + struct nand_info *info = this->priv; + + if (info->auto_mode) + mxc_do_addr_cycle_auto(mtd, column, page_addr); + else + mxc_do_addr_cycle_atomic(mtd, column, page_addr); +} + +static void send_cmd_atomic(struct mtd_info *mtd, u16 cmd) +{ + /* fill command */ + raw_write(cmd, REG_NFC_FLASH_CMD); + + /* clear status */ + ACK_OPS; + + /* send out command */ + raw_write(NFC_CMD, REG_NFC_OPS); + + /* Wait for operation to complete */ + wait_op_done(TROP_US_DELAY); +} + +/* + * Function to record the ECC corrected/uncorrected errors resulted + * after a page read. This NFC detects and corrects upto to 4 symbols + * of 9-bits each. + */ +static int mxc_nand_ecc_status(struct mtd_info *mtd) +{ + u32 ecc_stat, err; + int no_subpages = 1; + int ret = 0; + u8 ecc_bit_mask, err_limit; + struct nand_chip *this = mtd->priv; + struct nand_info *info = this->priv; + + ecc_bit_mask = (IS_4BIT_ECC ? 0x7 : 0xf); + err_limit = (IS_4BIT_ECC ? 0x4 : 0x8); + + no_subpages = mtd->writesize >> 9; + + no_subpages /= info->num_of_intlv; + + ecc_stat = GET_NFC_ECC_STATUS(); + do { + err = ecc_stat & ecc_bit_mask; + if (err > err_limit) { + printk(KERN_WARNING "UnCorrectable RS-ECC Error\n"); + return -1; + } else { + ret += err; + } + ecc_stat >>= 4; + } while (--no_subpages); + + MTDDEBUG(MTD_DEBUG_LEVEL3, "%d Symbol Correctable RS-ECC Error\n", ret); + + return ret; +} + +/*! + * This function handle the interleave related work + * @param mtd mtd info + * @param cmd command + */ +static void send_cmd_interleave(struct mtd_info *mtd, u16 cmd) +{ +#ifdef CONFIG_MXC_NFC_SP_AUTO + + struct nand_chip *this = mtd->priv; + struct nand_info *info = this->priv; + u32 addr_low = raw_read(NFC_FLASH_ADDR0); + u32 addr_high = raw_read(NFC_FLASH_ADDR8); + u32 page_addr = addr_low >> 16 | addr_high << 16; + u32 i, j = info->num_of_intlv; + u8 *dbuf = info->data_buf; + u8 *obuf = info->oob_buf; + u32 dlen = mtd->writesize / j; + u32 olen = mtd->oobsize / j; + + /* adjust the addr value + * since ADD_OP mode is 01 + */ + if (j > 1) + page_addr *= j; + else + page_addr *= this->numchips; + + switch (cmd) { + case NAND_CMD_PAGEPROG: + for (i = 0; i < j; i++) { + /* reset addr cycle */ + if (j > 1) + mxc_nand_addr_cycle(mtd, 0, page_addr++); + + /* data transfer */ + nfc_memcpy(MAIN_AREA0, dbuf, dlen); + copy_spare(mtd, obuf, SPARE_AREA0, olen, 0); + mxc_nand_bi_swap(mtd); + + /* update the value */ + dbuf += dlen; + obuf += olen; + + NFC_SET_RBA(0); + raw_write(0, REG_NFC_OPS_STAT); + raw_write(NFC_AUTO_PROG, REG_NFC_OPS); + + /* wait auto_prog_done bit set */ + while (!(raw_read(REG_NFC_OPS_STAT) & NFC_OP_DONE)) + ; + } + + wait_op_done(TROP_US_DELAY); + while (!(raw_read(REG_NFC_OPS_STAT) & NFC_RB)); + + break; + case NAND_CMD_READSTART: + for (i = 0; i < j; i++) { + /* reset addr cycle */ + if (j > 1) + mxc_nand_addr_cycle(mtd, 0, page_addr++); + + NFC_SET_RBA(0); + raw_write(0, REG_NFC_OPS_STAT); + raw_write(NFC_AUTO_READ, REG_NFC_OPS); + wait_op_done(TROP_US_DELAY); + + /* check ecc error */ + mxc_nand_ecc_status(mtd); + + /* data transfer */ + mxc_nand_bi_swap(mtd); + nfc_memcpy(dbuf, MAIN_AREA0, dlen); + copy_spare(mtd, obuf, SPARE_AREA0, olen, 1); + + /* update the value */ + dbuf += dlen; + obuf += olen; + } + break; + case NAND_CMD_ERASE2: + for (i = 0; i < j; i++) { + if (!i) { + page_addr = addr_low; + page_addr *= (j > 1 ? j : this->numchips); + } + mxc_nand_addr_cycle(mtd, -1, page_addr++); + raw_write(0, REG_NFC_OPS_STAT); + raw_write(NFC_AUTO_ERASE, REG_NFC_OPS); + wait_op_done(TROP_US_DELAY); + } + break; + case NAND_CMD_RESET: + for (i = 0; i < j; i++) { + if (j > 1) + NFC_SET_NFC_ACTIVE_CS(i); + send_cmd_atomic(mtd, cmd); + } + break; + default: + break; + } +#endif +} + +static void send_cmd_auto(struct mtd_info *mtd, u16 cmd) +{ +#ifdef CONFIG_MXC_NFC_SP_AUTO + switch (cmd) { + case NAND_CMD_READ0: + case NAND_CMD_READOOB: + raw_write(NAND_CMD_READ0, REG_NFC_FLASH_CMD); + break; + case NAND_CMD_SEQIN: + case NAND_CMD_ERASE1: + raw_write(cmd, REG_NFC_FLASH_CMD); + break; + case NAND_CMD_PAGEPROG: + case NAND_CMD_ERASE2: + case NAND_CMD_READSTART: + raw_write(raw_read(REG_NFC_FLASH_CMD) | cmd << NFC_CMD_1_SHIFT, + REG_NFC_FLASH_CMD); + send_cmd_interleave(mtd, cmd); + break; + case NAND_CMD_READID: + send_cmd_atomic(mtd, cmd); + send_addr(0); + break; + case NAND_CMD_RESET: + send_cmd_interleave(mtd, cmd); + break; + case NAND_CMD_STATUS: + send_cmd_atomic(mtd, cmd); + break; + default: + break; + } +#endif +} + +/*! + * This function issues the specified command to the NAND device and + * waits for completion. + * + * @param cmd command for NAND Flash + * @param useirq True if IRQ should be used rather than polling + */ +static void send_cmd(struct mtd_info *mtd, u16 cmd) +{ + + struct nand_chip *this = mtd->priv; + struct nand_info *info = this->priv; + + if (info->auto_mode) + send_cmd_auto(mtd, cmd); + else + send_cmd_atomic(mtd, cmd); + + MTDDEBUG(MTD_DEBUG_LEVEL3, "send_cmd(0x%x)\n", cmd); +} + +/*! + * This function requests the NFC to initate the transfer + * of data currently in the NFC RAM buffer to the NAND device. + * + * @param buf_id Specify Internal RAM Buffer number + */ +static void send_prog_page(struct mtd_info *mtd, u8 buf_id) +{ + struct nand_chip *this = mtd->priv; + struct nand_info *info = this->priv; + + if (!info->auto_mode) { + /* set ram buffer id */ + NFC_SET_RBA(buf_id); + + /* clear status */ + ACK_OPS; + + /* transfer data from NFC ram to nand */ + raw_write(NFC_INPUT, REG_NFC_OPS); + + /* Wait for operation to complete */ + wait_op_done(TROP_US_DELAY); + + MTDDEBUG(MTD_DEBUG_LEVEL3, "%s\n", __func__); + } +} + +/*! + * This function requests the NFC to initated the transfer + * of data from the NAND device into in the NFC ram buffer. + * + * @param buf_id Specify Internal RAM Buffer number + */ +static void send_read_page(struct mtd_info *mtd, u8 buf_id) +{ + struct nand_chip *this = mtd->priv; + struct nand_info *info = this->priv; + + if (!info->auto_mode) { + + /* set ram buffer id */ + NFC_SET_RBA(buf_id); + + /* clear status */ + ACK_OPS; + + /* transfer data from nand to NFC ram */ + raw_write(NFC_OUTPUT, REG_NFC_OPS); + + /* Wait for operation to complete */ + wait_op_done(TROP_US_DELAY); + + MTDDEBUG(MTD_DEBUG_LEVEL3, "%s(%d)\n", __func__, buf_id); + + } + +} + +/*! + * This function requests the NFC to perform a read of the + * NAND device ID. + */ +static void send_read_id(void) +{ + /* Set RBA bits for BUFFER0 */ + NFC_SET_RBA(0); + + /* clear status */ + ACK_OPS; + + /* Read ID into main buffer */ + raw_write(NFC_ID, REG_NFC_OPS); + + /* Wait for operation to complete */ + wait_op_done(TROP_US_DELAY); + +} + +static u16 mxc_do_status_auto(struct mtd_info *mtd) +{ + u16 status = 0; +#ifdef CONFIG_MXC_NFC_SP_AUTO + int i = 0; + u32 mask = 0xFF << 16; + struct nand_chip *this = mtd->priv; + struct nand_info *info = this->priv; + + for (; i < info->num_of_intlv; i++) { + + /* set ative cs */ + NFC_SET_NFC_ACTIVE_CS(i); + + /* clear status */ + ACK_OPS; + + /* use atomic mode to read status instead + * of using auto mode,auto-mode has issues + * and the status is not correct. + */ + raw_write(NFC_STATUS, REG_NFC_OPS); + + wait_op_done(TROP_US_DELAY); + + status = (raw_read(NFC_CONFIG1) & mask) >> 16; + + if (status & NAND_STATUS_FAIL) + break; + } +#endif + return status; +} + +static u16 mxc_do_status_atomic(struct mtd_info *mtd) +{ + volatile u16 *mainBuf = MAIN_AREA1; + u8 val = 1; + u16 ret; + + /* Set ram buffer id */ + NFC_SET_RBA(val); + + /* clear status */ + ACK_OPS; + + /* Read status into main buffer */ + raw_write(NFC_STATUS, REG_NFC_OPS); + + /* Wait for operation to complete */ + wait_op_done(TROP_US_DELAY); + + /* Status is placed in first word of main buffer */ + /* get status, then recovery area 1 data */ + ret = *mainBuf; + + return ret; +} + +/*! + * This function requests the NFC to perform a read of the + * NAND device status and returns the current status. + * + * @return device status + */ +static u16 mxc_nand_get_status(struct mtd_info *mtd) +{ + struct nand_chip *this = mtd->priv; + struct nand_info *info = this->priv; + u16 status; + + if (info->auto_mode) + status = mxc_do_status_auto(mtd); + else + status = mxc_do_status_atomic(mtd); + + return status; + +} + +static void mxc_nand_enable_hwecc(struct mtd_info *mtd, int mode) +{ + raw_write((raw_read(REG_NFC_ECC_EN) | NFC_ECC_EN), REG_NFC_ECC_EN); + return; +} + +/* + * Function to correct the detected errors. This NFC corrects all the errors + * detected. So this function just return 0. + */ +static int mxc_nand_correct_data(struct mtd_info *mtd, u_char *dat, + u_char *read_ecc, u_char *calc_ecc) +{ + return 0; +} + +/* + * Function to calculate the ECC for the data to be stored in the Nand device. + * This NFC has a hardware RS(511,503) ECC engine together with the RS ECC + * CONTROL blocks are responsible for detection and correction of up to + * 8 symbols of 9 bits each in 528 byte page. + * So this function is just return 0. + */ + +static int mxc_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat, + u_char *ecc_code) +{ + return 0; +} + +/*! + * This function id is used to read the data buffer from the NAND Flash. To + * read the data from NAND Flash first the data output cycle is initiated by + * the NFC, which copies the data to RAMbuffer. This data of length \b len is + * then copied to buffer \b buf. + * + * @param mtd MTD structure for the NAND Flash + * @param buf data to be read from NAND Flash + * @param len number of bytes to be read + */ +static void mxc_nand_read_buf(struct mtd_info *mtd, u_char * buf, int len) +{ + struct nand_chip *this = mtd->priv; + struct nand_info *info = this->priv; + u16 col = info->col_addr; + u8 *data_buf = info->data_buf; + u8 *oob_buf = info->oob_buf; + + if (mtd->writesize) { + + int j = mtd->writesize - col; + int n = mtd->oobsize + j; + + n = min(n, len); + + if (j > 0) { + if (n > j) { + memcpy(buf, &data_buf[col], j); + memcpy(buf + j, &oob_buf[0], n - j); + } else { + memcpy(buf, &data_buf[col], n); + } + } else { + col -= mtd->writesize; + memcpy(buf, &oob_buf[col], len); + } + + /* update */ + info->col_addr += n; + + } else { + /* At flash identify phase, + * mtd->writesize has not been + * set correctly, it should + * be zero.And len will less 2 + */ + memcpy(buf, &data_buf[col], len); + + /* update */ + info->col_addr += len; + } + +} + +/*! + * This function reads byte from the NAND Flash + * + * @param mtd MTD structure for the NAND Flash + * + * @return data read from the NAND Flash + */ +static uint8_t mxc_nand_read_byte(struct mtd_info *mtd) +{ + struct nand_chip *this = mtd->priv; + struct nand_info *info = this->priv; + uint8_t ret; + + /* Check for status request */ + if (info->status_req) + return mxc_nand_get_status(mtd) & 0xFF; + + mxc_nand_read_buf(mtd, &ret, 1); + + return ret; +} + +/*! + * This function reads word from the NAND Flash + * + * @param mtd MTD structure for the NAND Flash + * + * @return data read from the NAND Flash + */ +static u16 mxc_nand_read_word(struct mtd_info *mtd) +{ + u16 ret; + + mxc_nand_read_buf(mtd, (uint8_t *) &ret, sizeof(u16)); + + return ret; +} + +/*! + * This function reads byte from the NAND Flash + * + * @param mtd MTD structure for the NAND Flash + * + * @return data read from the NAND Flash + */ +static u_char mxc_nand_read_byte16(struct mtd_info *mtd) +{ + struct nand_chip *this = mtd->priv; + struct nand_info *info = this->priv; + + /* Check for status request */ + if (info->status_req) + return mxc_nand_get_status(mtd) & 0xFF; + + return mxc_nand_read_word(mtd) & 0xFF; +} + + +/*! + * This function writes data of length \b len from buffer \b buf to the NAND + * internal RAM buffer's MAIN area 0. + * + * @param mtd MTD structure for the NAND Flash + * @param buf data to be written to NAND Flash + * @param len number of bytes to be written + */ +static void mxc_nand_write_buf(struct mtd_info *mtd, + const u_char *buf, int len) +{ + struct nand_chip *this = mtd->priv; + struct nand_info *info = this->priv; + u16 col = info->col_addr; + u8 *data_buf = info->data_buf; + u8 *oob_buf = info->oob_buf; + int j = mtd->writesize - col; + int n = mtd->oobsize + j; + + n = min(n, len); + + if (j > 0) { + if (n > j) { + memcpy(&data_buf[col], buf, j); + memcpy(&oob_buf[0], buf + j, n - j); + } else { + memcpy(&data_buf[col], buf, n); + } + } else { + col -= mtd->writesize; + memcpy(&oob_buf[col], buf, len); + } + + /* update */ + info->col_addr += n; +} + +/*! + * This function is used by the upper layer to verify the data in NAND Flash + * with the data in the \b buf. + * + * @param mtd MTD structure for the NAND Flash + * @param buf data to be verified + * @param len length of the data to be verified + * + * @return -EFAULT if error else 0 + * + */ +static int mxc_nand_verify_buf(struct mtd_info *mtd, const u_char *buf, + int len) +{ + struct nand_chip *this = mtd->priv; + struct nand_info *info = this->priv; + u_char *s = info->data_buf; + + const u_char *p = buf; + + for (; len > 0; len--) { + if (*p++ != *s++) + return -1; + } + + return 0; +} + +/*! + * This function is used by upper layer for select and deselect of the NAND + * chip + * + * @param mtd MTD structure for the NAND Flash + * @param chip val indicating select or deselect + */ +static void mxc_nand_select_chip(struct mtd_info *mtd, int chip) +{ + + switch (chip) { + case -1: + break; + + case 0 ... 7: + NFC_SET_NFC_ACTIVE_CS(chip); + break; + + default: + break; + } +} + +/*! + * This function is used by the upper layer to write command to NAND Flash for + * different operations to be carried out on NAND Flash + * + * @param mtd MTD structure for the NAND Flash + * @param command command for NAND Flash + * @param column column offset for the page read + * @param page_addr page to be read from NAND Flash + */ +static void mxc_nand_command(struct mtd_info *mtd, unsigned command, + int column, int page_addr) +{ + struct nand_chip *this = mtd->priv; + struct nand_info *info = this->priv; + + MTDDEBUG(MTD_DEBUG_LEVEL3, + "mxc_nand_command (cmd = 0x%x, col = 0x%x, page = 0x%x)\n", + command, column, page_addr); + /* + * Reset command state information + */ + info->status_req = 0; + + /* + * Command pre-processing step + */ + switch (command) { + case NAND_CMD_STATUS: + info->col_addr = 0; + info->status_req = 1; + break; + + case NAND_CMD_READ0: + info->col_addr = column; + break; + + case NAND_CMD_READOOB: + info->col_addr = column; + command = NAND_CMD_READ0; + break; + + case NAND_CMD_SEQIN: + if (column != 0) { + + /* FIXME: before send SEQIN command for + * partial write,We need read one page out. + * FSL NFC does not support partial write + * It alway send out 512+ecc+512+ecc ... + * for large page nand flash. But for small + * page nand flash, it did support SPARE + * ONLY operation. But to make driver + * simple. We take the same as large page,read + * whole page out and update. As for MLC nand + * NOP(num of operation) = 1. Partial written + * on one programed page is not allowed! We + * can't limit it on the driver, it need the + * upper layer applicaiton take care it + */ + + mxc_nand_command(mtd, NAND_CMD_READ0, 0, page_addr); + } + + info->col_addr = column; + break; + + case NAND_CMD_PAGEPROG: + if (!info->auto_mode) { + nfc_memcpy(MAIN_AREA0, info->data_buf, mtd->writesize); + copy_spare(mtd, info->oob_buf, SPARE_AREA0, + mtd->oobsize, 0); + mxc_nand_bi_swap(mtd); + } + + send_prog_page(mtd, 0); + break; + + case NAND_CMD_ERASE1: + case NAND_CMD_ERASE2: + break; + } + + /* + * Write out the command to the device. + */ + send_cmd(mtd, command); + + mxc_nand_addr_cycle(mtd, column, page_addr); + + /* + * Command post-processing step + */ + switch (command) { + + case NAND_CMD_READOOB: + case NAND_CMD_READ0: + if (info->large_page) + /* send read confirm command */ + send_cmd(mtd, NAND_CMD_READSTART); + + send_read_page(mtd, 0); + + if (!info->auto_mode) { + mxc_nand_ecc_status(mtd); + mxc_nand_bi_swap(mtd); + nfc_memcpy(info->data_buf, MAIN_AREA0, mtd->writesize); + copy_spare(mtd, info->oob_buf, SPARE_AREA0, + mtd->oobsize, 1); + } + break; + + case NAND_CMD_READID: + send_read_id(); + info->col_addr = column; + nfc_memcpy(info->data_buf, MAIN_AREA0, 2048); + break; + } +} + +static int mxc_nand_read_oob(struct mtd_info *mtd, + struct nand_chip *chip, int page, int sndcmd) +{ + struct nand_chip *this = mtd->priv; + struct nand_info *info = this->priv; + + if (sndcmd) { + + chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page); + sndcmd = 0; + } + + memcpy(chip->oob_poi, info->oob_buf, mtd->oobsize); + + return sndcmd; +} + +static int mxc_nand_read_page(struct mtd_info *mtd, struct nand_chip *chip, + uint8_t *buf) +{ + struct nand_chip *this = mtd->priv; + struct nand_info *info = this->priv; + +#ifndef CONFIG_MXC_NFC_SP_AUTO + mxc_nand_ecc_status(mtd); +#endif + + memcpy(buf, info->data_buf, mtd->writesize); + memcpy(chip->oob_poi, info->oob_buf, mtd->oobsize); + + return 0; +} + +static void mxc_nand_write_page(struct mtd_info *mtd, struct nand_chip *chip, + const uint8_t *buf) +{ + struct nand_chip *this = mtd->priv; + struct nand_info *info = this->priv; + + memcpy(info->data_buf, buf, mtd->writesize); + memcpy(info->oob_buf, chip->oob_poi, mtd->oobsize); + +} + +/** + * mxc_nand_prog_page - [REPLACEABLE] write one page + * @mtd: MTD device structure + * @chip: NAND chip descriptor + * @buf: the data to write + * @page: page number to write + * @cached: cached programming + * @raw: use _raw version of write_page + */ +static int mxc_nand_prog_page(struct mtd_info *mtd, struct nand_chip *chip, + const uint8_t *buf, int page, int cached, int raw) +{ + int status; + int i; + + for (i = 0; i < mtd->writesize; i += 4) { + if (*(u32 *)(buf + i) != (u32)-1) + break; + } + + if (i == mtd->writesize) + return 0; + + chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page); + + if (unlikely(raw)) + chip->ecc.write_page_raw(mtd, chip, buf); + else + chip->ecc.write_page(mtd, chip, buf); + + /* + * Cached progamming disabled for now, Not sure if its worth the + * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s) + */ + cached = 0; + + if (!cached || !(chip->options & NAND_CACHEPRG)) { + + chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1); + status = chip->waitfunc(mtd, chip); + /* + * See if operation failed and additional status checks are + * available + */ + if ((status & NAND_STATUS_FAIL) && (chip->errstat)) + status = chip->errstat(mtd, chip, FL_WRITING, status, + page); + + if (status & NAND_STATUS_FAIL) + return -EIO; + } else { + chip->cmdfunc(mtd, NAND_CMD_CACHEDPROG, -1, -1); + status = chip->waitfunc(mtd, chip); + } + + + #ifdef CONFIG_MTD_NAND_VERIFY_WRITE + /* Send command to read back the data */ + chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page); + + if (chip->verify_buf(mtd, buf, mtd->writesize)) + return -EIO; + #endif + return 0; +} + +/* Define some generic bad / good block scan pattern which are used + * while scanning a device for factory marked good / bad blocks. */ +static uint8_t scan_ff_pattern[] = { 0xff, 0xff }; + +static struct nand_bbt_descr smallpage_memorybased = { + .options = NAND_BBT_SCAN2NDPAGE, + .offs = 5, + .len = 1, + .pattern = scan_ff_pattern +}; + +static struct nand_bbt_descr largepage_memorybased = { + .options = 0, + .offs = 0, + .len = 2, + .pattern = scan_ff_pattern +}; + +/* Generic flash bbt decriptors +*/ +static uint8_t bbt_pattern[] = { 'B', 'b', 't', '0' }; +static uint8_t mirror_pattern[] = { '1', 't', 'b', 'B' }; + +static struct nand_bbt_descr bbt_main_descr = { + .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE + | NAND_BBT_2BIT | NAND_BBT_VERSION, + .offs = 0, + .len = 4, + .veroffs = 4, + .maxblocks = 4, + .pattern = bbt_pattern +}; + +static struct nand_bbt_descr bbt_mirror_descr = { + .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE + | NAND_BBT_2BIT | NAND_BBT_VERSION, + .offs = 0, + .len = 4, + .veroffs = 4, + .maxblocks = 4, + .pattern = mirror_pattern +}; + +static int mxc_nand_scan_bbt(struct mtd_info *mtd) +{ + int i; + uint8_t id_bytes[NAND_DEVICE_ID_BYTE_COUNT]; + struct nand_chip *this = mtd->priv; + struct nand_info *info = this->priv; + struct nand_device_info *dev_info; + + info->page_mask = this->pagemask; + + if (!IS_LARGE_PAGE_NAND) + goto skip_it; + + /* Read ID bytes from the first NAND Flash chip. */ + this->select_chip(mtd, 0); + + this->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1); + + for (i = 0; i < NAND_DEVICE_ID_BYTE_COUNT; i++) + id_bytes[i] = this->read_byte(mtd); + + /* Get information about this device, based on the ID bytes. */ + dev_info = nand_device_get_info(id_bytes); + + /* Check if we understand this device. */ + if (!dev_info) { + printk(KERN_ERR "Unrecognized NAND Flash device.\n"); + return !0; + } + + nand_device_print_info(dev_info); + + /* Correct mtd setting */ + this->chipsize = dev_info->chip_size_in_bytes; + mtd->size = dev_info->chip_size_in_bytes * this->numchips; + mtd->writesize = dev_info->page_total_size_in_bytes & ~0x3ff; + mtd->oobsize = dev_info->page_total_size_in_bytes & 0x3ff;; + mtd->erasesize = dev_info->block_size_in_pages * mtd->writesize; + + /* limit to 2G size due to Kernel + * larger 4G space support,need fix + * it later + */ + if ((u32)mtd->size == 0) { + mtd->size = (u32)(1 << 31); + this->numchips = 1; + this->chipsize = mtd->size; + } + + /* Calculate the address shift from the page size */ + this->page_shift = ffs(mtd->writesize) - 1; + /* Convert chipsize to number of pages per chip -1. */ + this->pagemask = (this->chipsize >> this->page_shift) - 1; + + this->bbt_erase_shift = this->phys_erase_shift = + ffs(mtd->erasesize) - 1; + this->chip_shift = ffs(this->chipsize) - 1; + this->oob_poi = this->buffers->databuf + mtd->writesize; + +skip_it: + if (IS_2K_PAGE_NAND) { + NFC_SET_NFMS(1 << NFMS_NF_PG_SZ); + this->ecc.layout = &nand_hw_eccoob_2k; + info->large_page = 1; + } else if (IS_4K_PAGE_NAND) { + NFC_SET_NFMS(1 << NFMS_NF_PG_SZ); + this->ecc.layout = &nand_hw_eccoob_4k; + info->large_page = 1; + } else { + this->ecc.layout = &nand_hw_eccoob_512; + info->large_page = 0; + } + + /* propagate ecc.layout to mtd_info */ + mtd->ecclayout = this->ecc.layout; + + /* jffs2 not write oob */ + /*mtd->flags &= ~MTD_OOB_WRITEABLE;*/ + + /* fix up the offset */ + largepage_memorybased.offs = BAD_BLK_MARKER_OOB_OFFS; + + /* use flash based bbt */ + this->bbt_td = &bbt_main_descr; + this->bbt_md = &bbt_mirror_descr; + + /* update flash based bbt */ + this->options |= NAND_USE_FLASH_BBT; + + if (!this->badblock_pattern) { + this->badblock_pattern = (mtd->writesize > 512) ? + &largepage_memorybased : &smallpage_memorybased; + } + + /* Build bad block table */ + return nand_scan_bbt(mtd, this->badblock_pattern); +} + +static void mxc_nfc_init(void) +{ + /* Disable interrupt */ + raw_write((raw_read(REG_NFC_INTRRUPT) | NFC_INT_MSK), REG_NFC_INTRRUPT); + + /* disable spare enable */ + raw_write(raw_read(REG_NFC_SP_EN) & ~NFC_SP_EN, REG_NFC_SP_EN); + + /* Unlock the internal RAM Buffer */ + raw_write(NFC_SET_BLS(NFC_BLS_UNLCOKED), REG_NFC_BLS); + + /* Blocks to be unlocked */ + UNLOCK_ADDR(0x0, 0xFFFF); + + /* Unlock Block Command for given address range */ + raw_write(NFC_SET_WPC(NFC_WPC_UNLOCK), REG_NFC_WPC); + + /* Enable hw ecc */ + raw_write((raw_read(REG_NFC_ECC_EN) | NFC_ECC_EN), REG_NFC_ECC_EN); +} + +static int mxc_alloc_buf(struct nand_info *info) +{ + int err = 0; + + info->data_buf = kmalloc(NAND_MAX_PAGESIZE, GFP_KERNEL); + if (!info->data_buf) { + printk(KERN_ERR "%s: failed to allocate data_buf\n", __func__); + err = -ENOMEM; + return err; + } + memset(info->data_buf, 0, NAND_MAX_PAGESIZE); + + info->oob_buf = kmalloc(NAND_MAX_OOBSIZE, GFP_KERNEL); + if (!info->oob_buf) { + printk(KERN_ERR "%s: failed to allocate oob_buf\n", __func__); + err = -ENOMEM; + return err; + } + memset(info->oob_buf, 0, NAND_MAX_OOBSIZE); + + return err; +} + +/*! + * This function is called during the driver binding process. + * + * @param pdev the device structure used to store device specific + * information that is used by the suspend, resume and + * remove functions + * + * @return The function always returns 0. + */ +int board_nand_init(struct nand_chip *nand) +{ + struct nand_info *info; + struct nand_chip *this = nand; + struct mtd_info *mtd; /* dummy for compile */ + int err; + + info = kmalloc(sizeof(struct nand_info), GFP_KERNEL); + if (!info) { + printk(KERN_ERR "%s: failed to allocate nand_info\n", + __func__); + err = -ENOMEM; + return err; + } + memset(info, 0, sizeof(struct nand_info)); + + if (mxc_alloc_buf(info)) { + err = -ENOMEM; + return err; + } + + info->num_of_intlv = 1; + +#ifdef CONFIG_MXC_NFC_SP_AUTO + info->auto_mode = 1; +#endif + + /* init the nfc */ + mxc_nfc_init(); + + this->priv = info; + this->cmdfunc = mxc_nand_command; + this->select_chip = mxc_nand_select_chip; + this->read_byte = mxc_nand_read_byte; + this->read_word = mxc_nand_read_word; + this->write_buf = mxc_nand_write_buf; + this->read_buf = mxc_nand_read_buf; + this->verify_buf = mxc_nand_verify_buf; + this->scan_bbt = mxc_nand_scan_bbt; + this->write_page = mxc_nand_prog_page; + this->ecc.read_page = mxc_nand_read_page; + this->ecc.write_page = mxc_nand_write_page; + this->ecc.read_oob = mxc_nand_read_oob; + this->ecc.calculate = mxc_nand_calculate_ecc; + this->ecc.correct = mxc_nand_correct_data; + this->ecc.hwctl = mxc_nand_enable_hwecc; + this->ecc.layout = &nand_hw_eccoob_512; + this->ecc.mode = NAND_ECC_HW; + this->ecc.bytes = 9; + this->ecc.size = 512; + +#ifdef CONFIG_NAND_FW_16BIT + if (CONFIG_NAND_FW_16BIT == 1) { + this->read_byte = mxc_nand_read_byte16; + this->options |= NAND_BUSWIDTH_16; + NFC_SET_NFMS(1 << NFMS_NF_DWIDTH); + } else { + NFC_SET_NFMS(0); + } +#else + NFC_SET_NFMS(0); +#endif + + return 0; +} diff --git a/drivers/mtd/nand/mxs_gpmi.c b/drivers/mtd/nand/mxs_gpmi.c new file mode 100644 index 0000000000..e5f803a7f4 --- /dev/null +++ b/drivers/mtd/nand/mxs_gpmi.c @@ -0,0 +1,1613 @@ +/* + * Freescale GPMI NFC NAND Flash Driver + * + * Copyright (C) 2010 Freescale Semiconductor, Inc. + * Copyright (C) 2008 Embedded Alley Solutions, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#ifdef CONFIG_MTD_PARTITIONS +#include +#endif + +#include +#include +#include +#include +#include + +#ifdef CONFIG_JFFS2_NAND +#include +#endif + +#include +#include +#include + +#ifdef _DEBUG +static int debug = 1; +#define dbg_lvl(l) (debug > (l)) +#define DBG(l, fmt...) do { if (dbg_lvl(l)) printk(KERN_DEBUG fmt); } while (0) +#else +#define dbg_lvl(n) 0 +#define DBG(l, fmt...) do { } while (0) +#endif + +#define dma_timeout 1000 +#define create_bbt 1 + +#define MAX_CHIP_COUNT CONFIG_SYS_MAX_NAND_DEVICE +#define COMMAND_BUFFER_SIZE 10 +#define MAX_PIO_WORDS 16 + +/* dmaengine interface */ +enum dma_status { + DMA_SUCCESS, + DMA_IN_PROGRESS, + DMA_PAUSED, + DMA_ERROR, +}; + +/* MXS APBH DMA controller interface */ +#define HW_APBHX_CTRL0 0x000 +#define BM_APBH_CTRL0_APB_BURST8_EN (1 << 29) +#define BM_APBH_CTRL0_APB_BURST_EN (1 << 28) +#define BP_APBH_CTRL0_CLKGATE_CHANNEL 8 +#define BP_APBH_CTRL0_RESET_CHANNEL 16 +#define HW_APBHX_CTRL1 0x010 +#define HW_APBHX_CTRL2 0x020 +#define HW_APBHX_CHANNEL_CTRL 0x030 +#define BP_APBHX_CHANNEL_CTRL_RESET_CHANNEL 16 +#define HW_APBH_VERSION (cpu_is_mx23() ? 0x3f0 : 0x800) +#define HW_APBX_VERSION 0x800 +#define BP_APBHX_VERSION_MAJOR 24 +#define HW_APBHX_CHn_NXTCMDAR(n) (0x110 + (n) * 0x70) +#define HW_APBHX_CHn_SEMA(n) (0x140 + (n) * 0x70) + +/* + * ccw bits definitions + * + * COMMAND: 0..1 (2) + * CHAIN: 2 (1) + * IRQ: 3 (1) + * NAND_LOCK: 4 (1) - not implemented + * NAND_WAIT4READY: 5 (1) - not implemented + * DEC_SEM: 6 (1) + * WAIT4END: 7 (1) + * HALT_ON_TERMINATE: 8 (1) + * TERMINATE_FLUSH: 9 (1) + * RESERVED: 10..11 (2) + * PIO_NUM: 12..15 (4) + */ +#define BP_CCW_COMMAND 0 +#define BM_CCW_COMMAND (3 << 0) +#define CCW_CHAIN (1 << 2) +#define CCW_IRQ (1 << 3) +#define CCW_DEC_SEM (1 << 6) +#define CCW_WAIT4END (1 << 7) +#define CCW_HALT_ON_TERM (1 << 8) +#define CCW_TERM_FLUSH (1 << 9) +#define BP_CCW_PIO_NUM 12 +#define BM_CCW_PIO_NUM (0xf << 12) + +#define BF_CCW(value, field) (((value) << BP_CCW_##field) & BM_CCW_##field) + +#define MXS_DMA_CMD_NO_XFER 0 +#define MXS_DMA_CMD_WRITE 1 +#define MXS_DMA_CMD_READ 2 +#define MXS_DMA_CMD_DMA_SENSE 3 + +struct mxs_dma_ccw { + u32 next; + u16 bits; + u16 xfer_bytes; +#define MAX_XFER_BYTES 0xff00 + u32 bufaddr; +#define MXS_PIO_WORDS 16 + u32 pio_words[MXS_PIO_WORDS]; +}; + +#define NUM_CCW (int)(PAGE_SIZE / sizeof(struct mxs_dma_ccw)) + +struct mxs_dma_chan { + struct mxs_dma_engine *mxs_dma; + int chan_id; + struct mxs_dma_ccw *ccw; + int ccw_idx; + unsigned long ccw_phys; + enum dma_status status; +#define MXS_DMA_SG_LOOP (1 << 0) +}; + +#define MXS_DMA_CHANNELS 16 +#define MXS_DMA_CHANNELS_MASK 0xffff + +struct mxs_dma_engine { + int dev_id; + void __iomem *base; + struct mxs_dma_chan mxs_chans[MAX_CHIP_COUNT]; +}; + +struct mxs_gpmi { + struct mxs_dma_engine mxs_dma; + void __iomem *gpmi_regs; + void __iomem *bch_regs; + void __iomem *dma_regs; + + unsigned int chip_count; + + struct mtd_partition *parts; + unsigned int nr_parts; + struct mtd_info *mtd; + struct nand_chip *chip; + struct nand_ecclayout ecc_layout; + + int current_chip; + + void *page_buf; + void *oob_buf; + void *data_buf; + + int command_length; + u32 pio_data[MAX_PIO_WORDS]; + u8 cmd_buf[COMMAND_BUFFER_SIZE]; + + unsigned block0_ecc_strength:5, + blockn_ecc_strength:5, + swap_block_mark:1, + block_mark_bit_offset:3, + block_mark_byte_offset:14; +}; + +static uint8_t scan_ff_pattern[] = { 0xff }; +static struct nand_bbt_descr gpmi_bbt_descr = { + .options = 0, + .offs = 0, + .len = 1, + .pattern = scan_ff_pattern +}; + +static uint8_t bbt_pattern[] = {'B', 'b', 't', '0' }; +static uint8_t mirror_pattern[] = {'1', 't', 'b', 'B' }; + +static struct nand_bbt_descr mxs_gpmi_bbt_main_descr = { + .options = NAND_BBT_LASTBLOCK | NAND_BBT_2BIT | + NAND_BBT_VERSION | NAND_BBT_PERCHIP | + NAND_BBT_NO_OOB, + .offs = 0, + .len = 4, + .veroffs = 4, + .maxblocks = 4, + .pattern = bbt_pattern, +}; + +static struct nand_bbt_descr mxs_gpmi_bbt_mirror_descr = { + .options = NAND_BBT_LASTBLOCK | NAND_BBT_2BIT | + NAND_BBT_VERSION | NAND_BBT_PERCHIP | + NAND_BBT_NO_OOB, + .offs = 0, + .len = 4, + .veroffs = 4, + .maxblocks = 4, + .pattern = mirror_pattern, +}; + +/* MXS DMA implementation */ +#ifdef _DEBUG +static inline u32 __mxs_dma_readl(struct mxs_dma_engine *mxs_dma, + unsigned int reg, + const char *name, const char *fn, int ln) +{ + u32 val; + void __iomem *addr = mxs_dma->base + reg; + + val = readl(addr); + DBG(3, "%s@%d: Read %08x from %s[%08x]\n", fn, ln, val, name, + APBHDMA_BASE_ADDR + reg); + return val; +} +#define mxs_dma_readl(t, r) __mxs_dma_readl(t, r, #r, __func__, __LINE__) + +static inline void __mxs_dma_writel(u32 val, + struct mxs_dma_engine *mxs_dma, unsigned int reg, + const char *name, const char *fn, int ln) +{ + void __iomem *addr = mxs_dma->base + reg; + + DBG(3, "%s@%d: Writing %08x to %s[%08x]\n", fn, ln, val, name, + APBHDMA_BASE_ADDR + reg); + writel(val, addr); +} +#define mxs_dma_writel(v, t, r) __mxs_dma_writel(v, t, r, #r, __func__, __LINE__) +#else +static inline u32 mxs_dma_readl(struct mxs_dma_engine *mxs_dma, + unsigned int reg) +{ + BUG_ON(mxs_dma->base == NULL); + return readl(mxs_dma->base + reg); +} + +static inline void mxs_dma_writel(u32 val, struct mxs_dma_engine *mxs_dma, + unsigned int reg) +{ + BUG_ON(mxs_dma->base == NULL); + writel(val, mxs_dma->base + reg); +} +#endif + +static inline void mxs_dma_clkgate(struct mxs_dma_chan *mxs_chan, int enable) +{ + struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma; + int chan_id = mxs_chan->chan_id; + int set_clr = enable ? MXS_CLR_ADDR : MXS_SET_ADDR; + + /* enable apbh channel clock */ + mxs_dma_writel(1 << chan_id, + mxs_dma, HW_APBHX_CTRL0 + set_clr); +} + +static void mxs_dma_reset_chan(struct mxs_dma_chan *mxs_chan) +{ + struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma; + int chan_id = mxs_chan->chan_id; + + mxs_dma_writel(1 << (chan_id + BP_APBHX_CHANNEL_CTRL_RESET_CHANNEL), + mxs_dma, HW_APBHX_CHANNEL_CTRL + MXS_SET_ADDR); +} + +static void mxs_dma_enable_chan(struct mxs_dma_chan *mxs_chan) +{ + struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma; + int chan_id = mxs_chan->chan_id; + + /* clkgate needs to be enabled before writing other registers */ + mxs_dma_clkgate(mxs_chan, 1); + + /* set cmd_addr up */ + mxs_dma_writel(mxs_chan->ccw_phys, + mxs_dma, HW_APBHX_CHn_NXTCMDAR(chan_id)); + + /* write 1 to SEMA to kick off the channel */ + mxs_dma_writel(1, mxs_dma, HW_APBHX_CHn_SEMA(chan_id)); +} + +static void mxs_dma_disable_chan(struct mxs_dma_chan *mxs_chan) +{ + /* disable apbh channel clock */ + mxs_dma_clkgate(mxs_chan, 0); + + mxs_chan->status = DMA_SUCCESS; +} + +#ifdef _DEBUG +static inline u32 __mxs_gpmi_readl(struct mxs_gpmi *gpmi, + unsigned int reg, + const char *name, const char *fn, int ln) +{ + u32 val; + void __iomem *addr = gpmi->gpmi_regs + reg; + + val = readl(addr); + DBG(3, "%s@%d: Read %08x from %s[%08x]\n", fn, ln, val, name, + GPMI_BASE_ADDR + reg); + return val; +} +#define mxs_gpmi_readl(t, r) __mxs_gpmi_readl(t, r, #r, __func__, __LINE__) + +static inline void __mxs_gpmi_writel(u32 val, + struct mxs_gpmi *gpmi, unsigned int reg, + const char *name, const char *fn, int ln) +{ + void __iomem *addr = gpmi->gpmi_regs + reg; + + DBG(3, "%s@%d: Writing %08x to %s[%08x]\n", fn, ln, val, name, + GPMI_BASE_ADDR + reg); + writel(val, addr); +} +#define mxs_gpmi_writel(v, t, r) __mxs_gpmi_writel(v, t, r, #r, __func__, __LINE__) + +static inline u32 __mxs_bch_readl(struct mxs_gpmi *gpmi, + unsigned int reg, const char *name, + const char *fn, int ln) +{ + u32 val; + void __iomem *addr = gpmi->bch_regs + reg; + + val = readl(addr); + DBG(3, "%s@%d: Read %08x from %s[%08x]\n", fn, ln, val, name, + BCH_BASE_ADDR + reg); + return val; +} +#define mxs_bch_readl(t, r) __mxs_bch_readl(t, r, #r, __func__, __LINE__) + +static inline void __mxs_bch_writel(u32 val, + struct mxs_gpmi *gpmi, unsigned int reg, + const char *name, const char *fn, int ln) +{ + void __iomem *addr = gpmi->bch_regs + reg; + + DBG(3, "%s@%d: Writing %08x to %s[%08x]\n", fn, ln, val, name, + BCH_BASE_ADDR + reg); + writel(val, addr); +} +#define mxs_bch_writel(v, t, r) __mxs_bch_writel(v, t, r, #r, __func__, __LINE__) +#else +static inline u32 mxs_gpmi_readl(struct mxs_gpmi *gpmi, unsigned int reg) +{ + return readl(gpmi->gpmi_regs + reg); +} + +static inline void mxs_gpmi_writel(u32 val, + struct mxs_gpmi *gpmi, unsigned int reg) +{ + writel(val, gpmi->gpmi_regs + reg); +} + +static inline u32 mxs_bch_readl(struct mxs_gpmi *gpmi, unsigned int reg) +{ + return readl(gpmi->bch_regs + reg); +} + +static inline void mxs_bch_writel(u32 val, + struct mxs_gpmi *gpmi, unsigned int reg) +{ + writel(val, gpmi->bch_regs + reg); +} +#endif + +static inline struct mxs_dma_chan *mxs_gpmi_dma_chan(struct mxs_gpmi *gpmi, + unsigned int dma_channel) +{ + BUG_ON(dma_channel >= ARRAY_SIZE(gpmi->mxs_dma.mxs_chans)); + DBG(3, "%s: DMA chan[%d]=%p[%d]\n", __func__, + dma_channel, &gpmi->mxs_dma.mxs_chans[dma_channel], + gpmi->mxs_dma.mxs_chans[dma_channel].chan_id); + return &gpmi->mxs_dma.mxs_chans[dma_channel]; +} + +#define DUMP_DMA_CONTEXT + +static int first = 1; +#ifdef DUMP_DMA_CONTEXT + +#define APBH_DMA_PHYS_ADDR (MXS_IO_BASE_ADDR + 0x004000) + +static void dump_dma_context(struct mxs_gpmi *gpmi, const char *title) +{ + void *q; + u32 *p; + unsigned int i; + + if (!dbg_lvl(3)) + return; + + DBG(0, "%s: %s\n", __func__, title); + + DBG(0, "%s: GPMI:\n", __func__); + { + void __iomem *GPMI = gpmi->gpmi_regs; + static u32 old[13]; + + p = q = GPMI; + + for (i = 0; i < ARRAY_SIZE(old); i++) { + u32 val = readl(gpmi->gpmi_regs + i * 0x10); + + if (first || val != old[i]) { + if (first) + DBG(0, " [%p] 0x%08x\n", + p, val); + else + DBG(0, " [%p] 0x%08x -> 0x%08x\n", + p, old[i], val); + old[i] = val; + } + q += 0x10; + p = q; + } + } + + DBG(0, "%s: BCH:\n", __func__); + { + void *BCH = gpmi->bch_regs; + static u32 old[22]; + + p = q = BCH; + + for (i = 0; i < ARRAY_SIZE(old); i++) { + u32 val = readl(gpmi->bch_regs + i * 0x10); + + if (first || val != old[i]) { + if (first) + DBG(0, " [%p] 0x%08x\n", + q, val); + else + DBG(0, " [%p] 0x%08x -> 0x%08x\n", + q, old[i], val); + old[i] = val; + } + q += 0x10; + p = q; + } + } + + DBG(0, "%s: APBH:\n", __func__); + { + void *APBH = gpmi->dma_regs; + static u32 old[7]; + static u32 chan[16][7]; + + p = q = APBH; + + for (i = 0; i < ARRAY_SIZE(old); i++) { + u32 val = readl(gpmi->dma_regs + i * 0x10); + + if (first || val != old[i]) { + if (first) + DBG(0, " [%p] 0x%08x\n", + q, val); + else + DBG(0, " [%p] 0x%08x -> 0x%08x\n", + q, old[i], val); + old[i] = val; + } + q += 0x10; + p = q; + } + for (i = 0; i < ARRAY_SIZE(chan); i++) { + int j; + + printk("CHAN %2d:\n", i); + for (j = 0; j < ARRAY_SIZE(chan[i]); j++) { + u32 val; + + p = q = APBH + 0x100 + i * 0x70 + j * 0x10; + + val = readl(gpmi->dma_regs + 0x100 + i * 0x70 + j * 0x10); + + if (first || val != chan[i][j]) { + if (first) + DBG(0, " [%p] 0x%08x\n", + q, val); + else + DBG(0, " [%p] 0x%08x -> 0x%08x\n", + q, chan[i][j], val); + chan[i][j] = val; + } + q += 0x10; + p = q; + } + } + } + first = 0; +} +#else +static inline void dump_dma_context(struct mxs_gpmi *gpmi, char *title) +{ +} +#endif + +static int mxs_gpmi_init_hw(struct mxs_gpmi *gpmi) +{ + dump_dma_context(gpmi, "BEFORE INIT"); + + if (mxs_gpmi_readl(gpmi, HW_GPMI_CTRL0) & 0xc0000000) { + DBG(0, "%s: Resetting GPMI\n", __func__); + mxs_reset_block(gpmi->gpmi_regs); + } + + mxs_gpmi_writel(BM_GPMI_CTRL1_GPMI_MODE, gpmi, HW_GPMI_CTRL1_CLR); + mxs_gpmi_writel(BM_GPMI_CTRL1_ATA_IRQRDY_POLARITY, + gpmi, HW_GPMI_CTRL1_SET); + + /* Disable write protection and Select BCH ECC */ + mxs_gpmi_writel(BM_GPMI_CTRL1_DEV_RESET | BM_GPMI_CTRL1_BCH_MODE, + gpmi, HW_GPMI_CTRL1_SET); + + /* Select BCH ECC. */ + mxs_gpmi_writel(BM_GPMI_CTRL1_BCH_MODE, + gpmi, HW_GPMI_CTRL1_SET); + + dump_dma_context(gpmi, "AFTER INIT"); + return 0; +} + +static int mxs_dma_chan_init(struct mxs_dma_chan *mxs_chan, int chan_id) +{ + mxs_chan->ccw = dma_alloc_coherent(PAGE_SIZE, &mxs_chan->ccw_phys); + if (mxs_chan->ccw == NULL) + return -ENOMEM; + + DBG(0, "%s: mxs_chan[%d]=%p ccw=%p\n", __func__, + chan_id, mxs_chan, mxs_chan->ccw); + + memset(mxs_chan->ccw, 0, PAGE_SIZE); + mxs_chan->chan_id = chan_id; + + mxs_dma_clkgate(mxs_chan, 1); + mxs_dma_reset_chan(mxs_chan); + mxs_dma_clkgate(mxs_chan, 0); + return 0; +} + +static int mxs_dma_init(struct mxs_gpmi *gpmi, int dma_chan, + int num_dma_channels) +{ + int ret; + struct mxs_dma_engine *mxs_dma = &gpmi->mxs_dma; + int i; + + writel(readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_GPMI) & ~BM_CLKCTRL_GPMI_CLKGATE, + CLKCTRL_BASE_ADDR + HW_CLKCTRL_GPMI); + + mxs_dma->base = gpmi->dma_regs; + + ret = mxs_reset_block(mxs_dma->base); + if (ret) { + printk(KERN_ERR "%s: Failed to reset APBH DMA controller\n", __func__); + return ret; + } + + mxs_dma_writel(BM_APBH_CTRL0_APB_BURST_EN, + mxs_dma, HW_APBHX_CTRL0 + MXS_SET_ADDR); + mxs_dma_writel(BM_APBH_CTRL0_APB_BURST8_EN, + mxs_dma, HW_APBHX_CTRL0 + MXS_SET_ADDR); + + for (i = 0; i < num_dma_channels; i++) { + struct mxs_dma_chan *mxs_chan = &mxs_dma->mxs_chans[i]; + + mxs_chan->mxs_dma = mxs_dma; + ret = mxs_dma_chan_init(mxs_chan, dma_chan + i); + if (ret) + return ret; + } + return 0; +} + +static int mxs_dma_prep_slave(struct mxs_dma_chan *mxs_chan, void *buffer, + dma_addr_t buf_dma, int len, + enum dma_data_direction direction, + int append) +{ + int ret; + int idx = append ? mxs_chan->ccw_idx : 0; + struct mxs_dma_ccw *ccw; + + DBG(1, "%s: mxs_chan=%p status=%d append=%d ccw=%p\n", __func__, + mxs_chan, mxs_chan->status, append, mxs_chan->ccw); + + BUG_ON(mxs_chan->ccw == NULL); + BUG_ON(mxs_chan == NULL); + + if (mxs_chan->status == DMA_IN_PROGRESS && !append) + return -EBUSY; + + if (mxs_chan->status != DMA_IN_PROGRESS && append) { + ret = -EINVAL; + goto err_out; + } + + if (idx >= NUM_CCW) { + printk(KERN_ERR "maximum number of segments exceeded: %d > %d\n", + idx, NUM_CCW); + ret = -EINVAL; + goto err_out; + } + + mxs_chan->status = DMA_IN_PROGRESS; + + if (append) { + BUG_ON(idx < 1); + ccw = &mxs_chan->ccw[idx - 1]; + ccw->next = mxs_chan->ccw_phys + sizeof(*ccw) * idx; + ccw->bits |= CCW_CHAIN; + ccw->bits &= ~CCW_IRQ; + ccw->bits &= ~CCW_DEC_SEM; + ccw->bits &= ~CCW_WAIT4END; + + DBG(3, "%s: Appending sg to list[%d]@%p: next=0x%08x bits=0x%08x\n", + __func__, idx, ccw, ccw->next, ccw->bits); + } else { + idx = 0; + } + ccw = &mxs_chan->ccw[idx++]; + if (direction == DMA_NONE) { + int j; + u32 *pio = buffer; + + for (j = 0; j < len; j++) + ccw->pio_words[j] = *pio++; + + if (dbg_lvl(3)) { + DBG(0, "%s: Storing %d PIO words in ccw[%d]@%p:", __func__, + len, idx - 1, ccw); + for (j = 0; j < len; j++) { + printk(" %08x", ccw->pio_words[j]); + } + printk("\n"); + } + ccw->bits = 0; + ccw->bits |= CCW_IRQ; + ccw->bits |= CCW_DEC_SEM; + ccw->bits |= CCW_WAIT4END; + ccw->bits |= CCW_HALT_ON_TERM; + ccw->bits |= CCW_TERM_FLUSH; + ccw->bits |= BF_CCW(len, PIO_NUM); + ccw->bits |= BF_CCW(MXS_DMA_CMD_NO_XFER, COMMAND); + } else { + if (len > MAX_XFER_BYTES) { + printk(KERN_ERR "maximum bytes for sg entry exceeded: %d > %d\n", + len, MAX_XFER_BYTES); + ret = -EINVAL; + goto err_out; + } + + ccw->next = mxs_chan->ccw_phys + sizeof(*ccw) * idx; + ccw->bufaddr = buf_dma; + ccw->xfer_bytes = len; + + ccw->bits = 0; + ccw->bits |= CCW_CHAIN; + ccw->bits |= CCW_HALT_ON_TERM; + ccw->bits |= CCW_TERM_FLUSH; + ccw->bits |= BF_CCW(direction == DMA_FROM_DEVICE ? + MXS_DMA_CMD_WRITE : MXS_DMA_CMD_READ, + COMMAND); + + ccw->bits &= ~CCW_CHAIN; + ccw->bits |= CCW_IRQ; + ccw->bits |= CCW_DEC_SEM; + ccw->bits |= CCW_WAIT4END; + DBG(3, "%s: DMA descriptor: ccw=%p next=0x%08x bufadr=%08x xfer_bytes=%08x bits=0x%08x\n", + __func__, ccw, ccw->next, ccw->bufaddr, + ccw->xfer_bytes, ccw->bits); + } + + mxs_chan->ccw_idx = idx; + + return 0; + +err_out: + mxs_chan->ccw_idx = 0; + mxs_chan->status = DMA_ERROR; + return ret; +} + +static int mxs_dma_submit(struct mxs_gpmi *gpmi, struct mxs_dma_chan *mxs_chan) +{ + int ret; + int first = 1; + u32 stat1, stat2; + int chan_id = mxs_chan->chan_id; + u32 chan_mask = 1 << chan_id; + struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma; + long timeout = 1000; + + dump_dma_context(gpmi, "BEFORE"); + + mxs_dma_enable_chan(mxs_chan); + + dump_dma_context(gpmi, "WITHIN"); + + while (1) { + stat1 = mxs_dma_readl(mxs_dma, HW_APBHX_CTRL1); + stat2 = mxs_dma_readl(mxs_dma, HW_APBHX_CTRL2); + if ((stat1 & chan_mask) || (stat2 & chan_mask)) { + break; + } + if (first) { + DBG(1, "Waiting for DMA channel %d to finish\n", + chan_id); + first = 0; + } + if (timeout-- < 0) + return -ETIME; + udelay(100); + } + + dump_dma_context(gpmi, "AFTER"); + + mxs_dma_writel(chan_mask, mxs_dma, HW_APBHX_CTRL1 + MXS_CLR_ADDR); + mxs_dma_writel(chan_mask, mxs_dma, HW_APBHX_CTRL2 + MXS_CLR_ADDR); + stat2 = ((stat2 >> MXS_DMA_CHANNELS) & stat2) | + (~(stat2 >> MXS_DMA_CHANNELS) & stat2 & ~stat1); + if (stat2 & chan_mask) { + printk(KERN_ERR "DMA error in channel %d\n", chan_id); + ret = -EIO; + } else if (stat1 & chan_mask) { + DBG(0, "DMA channel %d finished\n", chan_id); + ret = 0; + } else { + printk(KERN_ERR "DMA channel %d early termination\n", chan_id); + ret = -EINVAL; + } + mxs_chan->status = ret == 0 ? DMA_SUCCESS : DMA_ERROR; + return ret; +} + +static void mxs_dma_terminate_all(struct mxs_dma_chan *mxs_chan) +{ + mxs_dma_disable_chan(mxs_chan); +} + +static int poll_bit(void __iomem *addr, unsigned int mask, long timeout) +{ + while (!(readl(addr) & mask)) { + udelay(1000); + timeout--; + } + return timeout == 0 ? -ETIME : 0; +} + +static int mxs_gpmi_dma_go(struct mxs_gpmi *gpmi, + int wait_for_bch) +{ + int error; + struct mxs_dma_chan *mxs_chan = mxs_gpmi_dma_chan(gpmi, + gpmi->current_chip); + + DBG(1, "> %s\n", __func__); + + error = mxs_dma_submit(gpmi, mxs_chan); + DBG(1, "%s: mxs_dma_submit returned %d\n", __func__, + error); + if (error) + goto err; + + if (wait_for_bch) { + DBG(1, "%s: Waiting for BCH completion\n", __func__); + error = poll_bit(gpmi->bch_regs + HW_BCH_CTRL, + BM_BCH_CTRL_COMPLETE_IRQ, + dma_timeout); + DBG(1, "%s: poll_bit returned %d\n", __func__, + error); + DBG(1, "%s: BCH status %08x\n", __func__, + mxs_bch_readl(gpmi, HW_BCH_STATUS0)); + if (mxs_bch_readl(gpmi, HW_BCH_CTRL) & BM_BCH_CTRL_COMPLETE_IRQ) { + DBG(1, "%s: Clearing BCH IRQ\n", __func__); + mxs_bch_writel(BM_BCH_CTRL_COMPLETE_IRQ, gpmi, HW_BCH_CTRL_CLR); + } + + if (error) + goto err; + } +out: + DBG(1, "< %s: %d\n", __func__, error); + return error; + +err: + { + struct mxs_dma_chan *mxs_chan = mxs_gpmi_dma_chan(gpmi, + gpmi->current_chip); + dump_dma_context(gpmi, "ERROR"); + mxs_dma_terminate_all(mxs_chan); + } + goto out; +} + +int mxs_gpmi_dma_setup(struct mxs_gpmi *gpmi, void *buffer, int length, + int pio_words, enum dma_data_direction dir, int append) + +{ + int ret; + struct mxs_dma_chan *mxs_chan; + dma_addr_t buf_dma; + + mxs_chan = mxs_gpmi_dma_chan(gpmi, gpmi->current_chip); + if (mxs_chan == NULL) + return -EINVAL; + + DBG(1, "%s: buffer=%p len=%u pio=%d append=%d\n", __func__, + buffer, length, pio_words, append); + + if (pio_words) { + ret = mxs_dma_prep_slave(mxs_chan, gpmi->pio_data, ~0, + pio_words, DMA_NONE, append); + if (ret) { + mxs_dma_terminate_all(mxs_chan); + printk(KERN_ERR + "%s: Failed to setup DMA PIO xfer for %d words: %d\n", + __func__, pio_words, ret); + return ret; + } + if (buffer == NULL) + return ret; + + append = 1; + } + +#if 0 + if (dir == DMA_FROM_DEVICE) + memset(buffer, 0x55, length); +#endif + buf_dma = dma_map_single(buffer, length, dir); + + DBG(1, "%s: buffer=%p dma_addr=%08x\n", __func__, buffer, buf_dma); + + ret = mxs_dma_prep_slave(mxs_chan, buffer, buf_dma, length, dir, append); + if (ret) { + mxs_dma_terminate_all(mxs_chan); + DBG(1, "%s: mxs_dma_prep_slave() returned %d\n", + __func__, ret); + dma_unmap_single(buffer, length, dir); + } + return ret; +} + +static int mxs_gpmi_dma_xfer(struct mxs_gpmi *gpmi, + void *buffer, int length, int pio_words, + enum dma_data_direction dir) +{ + int ret; + + ret = mxs_gpmi_dma_setup(gpmi, buffer, length, + pio_words, dir, 0); + + if (ret) { + DBG(1, "%s: mxs_gpmi_dma_setup() returned %d\n", + __func__, ret); + return ret; + } + + DBG(1, "%s: starting DMA xfer\n", __func__); + ret = mxs_gpmi_dma_go(gpmi, 0); + + DBG(1, "%s: DMA xfer done: %d\n", __func__, ret); + return ret; +} + +/* low level accessor functions */ +static int mxs_gpmi_read_data(struct mxs_gpmi *gpmi, int cs, + void *buffer, size_t length) +{ + int ret; + u32 command_mode; + u32 address; + + DBG(2, "%s: buf=%p len=%d\n", __func__, buffer, length); + + memset(buffer, 0x44, length); + + command_mode = BV_GPMI_CTRL0_COMMAND_MODE__READ; + address = BV_GPMI_CTRL0_ADDRESS__NAND_DATA; + + gpmi->pio_data[0] = + BF_GPMI_CTRL0_COMMAND_MODE(command_mode) | + BF_GPMI_CTRL0_CS_V1(cs) | + BM_GPMI_CTRL0_WORD_LENGTH | + BF_GPMI_CTRL0_ADDRESS(address) | + BF_GPMI_CTRL0_XFER_COUNT(length); + gpmi->pio_data[1] = 0; + + ret = mxs_gpmi_dma_xfer(gpmi, buffer, length, 2, DMA_FROM_DEVICE); + return ret; +} + +/* mtd layer interface */ +static void mxs_gpmi_select_chip(struct mtd_info *mtd, int cs) +{ + struct nand_chip *chip = mtd->priv; + struct mxs_gpmi *gpmi = chip->priv; + + gpmi->current_chip = cs; +} + +static int mxs_gpmi_dev_ready(struct mtd_info *mtd) +{ + int ready; + struct nand_chip *chip = mtd->priv; + struct mxs_gpmi *gpmi = chip->priv; + u32 mask; + u32 reg; + int cs = gpmi->current_chip; + + if (cs < 0) + return 0; + + DBG(1, "> %s\n", __func__); + + mask = BF_GPMI_STAT_READY_BUSY(1 << cs); + reg = mxs_gpmi_readl(gpmi, HW_GPMI_STAT); + + ready = !!(reg & mask); + DBG(1, "< %s: %d\n", __func__, ready); + return ready; +} + +static void mxs_gpmi_swap_bb_mark(struct mxs_gpmi *gpmi, + void *payload, void *auxiliary) +{ + unsigned char *p = payload + gpmi->block_mark_byte_offset; + unsigned char *a = auxiliary; + unsigned int bit = gpmi->block_mark_bit_offset; + unsigned char mask; + unsigned char from_data; + unsigned char from_oob; + + /* + * Get the byte from the data area that overlays the block mark. Since + * the ECC engine applies its own view to the bits in the page, the + * physical block mark won't (in general) appear on a byte boundary in + * the data. + */ + from_data = (p[0] >> bit) | (p[1] << (8 - bit)); + + /* Get the byte from the OOB. */ + from_oob = a[0]; + + /* Swap them. */ + a[0] = from_data; + + mask = (0x1 << bit) - 1; + p[0] = (p[0] & mask) | (from_oob << bit); + + mask = ~0 << bit; + p[1] = (p[1] & mask) | (from_oob >> (8 - bit)); +} + +static int mxs_gpmi_read_page(struct mtd_info *mtd, struct nand_chip *chip, + uint8_t *buf) +{ + int ret = -1; + struct mxs_gpmi *gpmi = chip->priv; + int cs = gpmi->current_chip; + u32 command_mode; + u32 address; + u32 ecc_command; + u32 buffer_mask; + dma_addr_t buf_dma; + dma_addr_t oob_dma; + + DBG(3, "%s: read page to buffer %p\n", __func__, buf); + + buf_dma = dma_map_single(gpmi->page_buf, mtd->writesize, + DMA_FROM_DEVICE); + + oob_dma = dma_map_single(gpmi->oob_buf, mtd->oobsize, + DMA_FROM_DEVICE); + + command_mode = BV_GPMI_CTRL0_COMMAND_MODE__WAIT_FOR_READY; + address = BV_GPMI_CTRL0_ADDRESS__NAND_DATA; + + gpmi->pio_data[0] = + BF_GPMI_CTRL0_COMMAND_MODE(command_mode) | + BF_GPMI_CTRL0_CS_V1(cs) | + BM_GPMI_CTRL0_WORD_LENGTH | + BF_GPMI_CTRL0_ADDRESS(address) | + BF_GPMI_CTRL0_XFER_COUNT(0); + gpmi->pio_data[1] = 0; + + ret = mxs_gpmi_dma_setup(gpmi, NULL, 0, 2, DMA_NONE, 0); + if (ret) { + goto unmap; + } + + command_mode = BV_GPMI_CTRL0_COMMAND_MODE__READ; + address = BV_GPMI_CTRL0_ADDRESS__NAND_DATA; + ecc_command = BV_GPMI_ECCCTRL_ECC_CMD__DECODE; + buffer_mask = BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_PAGE | + BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_AUXONLY; + + gpmi->pio_data[0] = BF_GPMI_CTRL0_COMMAND_MODE(command_mode) | + BM_GPMI_CTRL0_WORD_LENGTH | + BF_GPMI_CTRL0_CS_V1(cs) | + BF_GPMI_CTRL0_ADDRESS(address) | + BF_GPMI_CTRL0_XFER_COUNT(mtd->writesize + mtd->oobsize); + + gpmi->pio_data[1] = 0; + + gpmi->pio_data[2] = BM_GPMI_ECCCTRL_ENABLE_ECC | + BF_GPMI_ECCCTRL_ECC_CMD(ecc_command) | + BF_GPMI_ECCCTRL_BUFFER_MASK(buffer_mask); + + gpmi->pio_data[3] = mtd->writesize + mtd->oobsize; + gpmi->pio_data[4] = buf_dma; + gpmi->pio_data[5] = oob_dma; + + ret = mxs_gpmi_dma_setup(gpmi, NULL, 0, 6, DMA_NONE, 1); + if (ret) { + goto unmap; + } + + command_mode = BV_GPMI_CTRL0_COMMAND_MODE__WAIT_FOR_READY; + address = BV_GPMI_CTRL0_ADDRESS__NAND_DATA; + + gpmi->pio_data[0] = + BF_GPMI_CTRL0_COMMAND_MODE(command_mode) | + BM_GPMI_CTRL0_WORD_LENGTH | + BF_GPMI_CTRL0_CS_V1(cs) | + BF_GPMI_CTRL0_ADDRESS(address) | + BF_GPMI_CTRL0_XFER_COUNT(mtd->writesize + mtd->oobsize); + + gpmi->pio_data[1] = 0; + + ret = mxs_gpmi_dma_setup(gpmi, NULL, 0, 2, DMA_NONE, 1); + if (ret == 0) { + ret = mxs_gpmi_dma_go(gpmi, 1); + } +unmap: + dma_unmap_single(gpmi->oob_buf, mtd->oobsize, + DMA_FROM_DEVICE); + dma_unmap_single(gpmi->page_buf, mtd->writesize, + DMA_FROM_DEVICE); + { +#define STATUS_GOOD 0x00 +#define STATUS_ERASED 0xff +#define STATUS_UNCORRECTABLE 0xfe + /* Loop over status bytes, accumulating ECC status. */ + struct nand_chip *chip = mtd->priv; + int failed = 0; + int corrected = 0; + u8 *status = gpmi->oob_buf + mtd->oobavail; + int i; + + for (i = 0; i < mtd->writesize / chip->ecc.size; i++, status++) { + if ((*status == STATUS_GOOD) || (*status == STATUS_ERASED)) + continue; + + if (*status == STATUS_UNCORRECTABLE) { + failed++; + continue; + } + corrected += *status; + } + /* + * Propagate ECC status to the owning MTD only when failed or + * corrected times nearly reaches our ECC correction threshold. + */ + if (failed || corrected >= (chip->ecc.size - 1)) { + DBG(0, "%s: ECC failures: %d\n", __func__, failed); + mtd->ecc_stats.failed += failed; + mtd->ecc_stats.corrected += corrected; + } + } + if (ret == 0) { + if (gpmi->swap_block_mark) + mxs_gpmi_swap_bb_mark(gpmi, gpmi->page_buf, gpmi->oob_buf); + if (buf) { + memcpy(buf, gpmi->page_buf, mtd->writesize); + } + } else { + printk(KERN_ERR "%s: FAILED to read page to buffer %p\n", __func__, buf); + } + return ret; +} + +static int mxs_gpmi_read_oob(struct mtd_info *mtd, struct nand_chip *chip, + int page, int sndcmd) +{ + DBG(3, "%s: reading OOB of page %d\n", __func__, page); + + memset(chip->oob_poi, dbg_lvl(0) ? 0xfe : 0xff, mtd->oobsize); + chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page); + chip->read_buf(mtd, chip->oob_poi, mtd->oobavail); + return 1; +} + +static void mxs_gpmi_write_page(struct mtd_info *mtd, struct nand_chip *chip, + const uint8_t *buf) +{ + int ret = -1; + struct mxs_gpmi *gpmi = chip->priv; + int cs = gpmi->current_chip; + u32 command_mode; + u32 address; + u32 ecc_command; + u32 buffer_mask; + dma_addr_t buf_dma; + dma_addr_t oob_dma; + + DBG(3, "%s: Writing buffer %p\n", __func__, buf); + + memset(gpmi->oob_buf + mtd->oobavail, dbg_lvl(0) ? 0xef : 0xff, + mtd->oobsize - mtd->oobavail); + + if (buf) + memcpy(gpmi->page_buf, buf, mtd->writesize); + + if (gpmi->swap_block_mark) + mxs_gpmi_swap_bb_mark(gpmi, gpmi->page_buf, gpmi->oob_buf); + + buf_dma = dma_map_single(gpmi->page_buf, mtd->writesize, + DMA_TO_DEVICE); + + oob_dma = dma_map_single(gpmi->oob_buf, mtd->oobsize, + DMA_TO_DEVICE); + + command_mode = BV_GPMI_CTRL0_COMMAND_MODE__WRITE; + address = BV_GPMI_CTRL0_ADDRESS__NAND_DATA; + ecc_command = BV_GPMI_ECCCTRL_ECC_CMD__ENCODE; + buffer_mask = BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_PAGE | + BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_AUXONLY; + + gpmi->pio_data[0] = + BF_GPMI_CTRL0_COMMAND_MODE(command_mode) | + BM_GPMI_CTRL0_WORD_LENGTH | + BF_GPMI_CTRL0_CS_V1(cs) | + BF_GPMI_CTRL0_ADDRESS(address) | + BF_GPMI_CTRL0_XFER_COUNT(0); + gpmi->pio_data[1] = 0; + gpmi->pio_data[2] = + BM_GPMI_ECCCTRL_ENABLE_ECC | + BF_GPMI_ECCCTRL_ECC_CMD(ecc_command) | + BF_GPMI_ECCCTRL_BUFFER_MASK(buffer_mask); + gpmi->pio_data[3] = mtd->writesize + mtd->oobsize; + gpmi->pio_data[4] = buf_dma; + gpmi->pio_data[5] = oob_dma; + + ret = mxs_gpmi_dma_setup(gpmi, NULL, 0, 6, DMA_NONE, 0); + if (ret == 0) { + ret = mxs_gpmi_dma_go(gpmi, 1); + } + + dma_unmap_single(gpmi->oob_buf, mtd->oobsize, + DMA_TO_DEVICE); + dma_unmap_single(gpmi->page_buf, mtd->writesize, + DMA_TO_DEVICE); + if (ret) { + printk(KERN_ERR "%s: FAILED!\n", __func__); + } +} + +static int mxs_gpmi_write_oob(struct mtd_info *mtd, struct nand_chip *chip, + int page) +{ + return -EINVAL; +} + +#if 0 +static void mxs_gpmi_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip, + const uint8_t *buf) +{ + memcpy(gpmi->page_buf, buf, mtd->writesize); + +} +#endif + +static void mxs_gpmi_read_buf(struct mtd_info *mtd, u_char *buf, int len) +{ + struct nand_chip *chip = mtd->priv; + struct mxs_gpmi *gpmi = chip->priv; + void *xfer_buf; + int ret = 0; + + if (len > mtd->writesize + mtd->oobsize) { + DBG(0, "%s: Allocating temporary buffer\n", __func__); + xfer_buf = kzalloc(len, GFP_KERNEL); + if (xfer_buf == NULL) { + printk(KERN_ERR + "Failed to allocate %u byte for xfer buffer\n", + len); + memset(buf, 0xee, len); + } + } else { + xfer_buf = buf; + } + + DBG(3, "%s: reading %u byte to %p(%p)\n", __func__, + len, buf, xfer_buf); + + ret = mxs_gpmi_read_data(gpmi, gpmi->current_chip, xfer_buf, len); + if (xfer_buf != buf) { + if (ret == 0) { + memcpy(buf, xfer_buf, len); + } + kfree(xfer_buf); + } + DBG(1, "< %s %d\n", __func__, ret); +} + +static u_char mxs_gpmi_read_byte(struct mtd_info *mtd) +{ + struct nand_chip *chip = mtd->priv; + struct mxs_gpmi *gpmi = chip->priv; + u_char *buf = (u_char *)gpmi->pio_data; + + mxs_gpmi_read_buf(mtd, buf, 1); + return *buf; +} + +static void mxs_gpmi_write_buf(struct mtd_info *mtd, const u_char *buf, + int len) +{ + int ret; + struct nand_chip *chip = mtd->priv; + struct mxs_gpmi *gpmi = chip->priv; + void *xfer_buf = (void *)buf; /* cast away the 'const' */ +#if 1 + u32 command_mode; + u32 address; + int cs = gpmi->current_chip; + + DBG(3, "%s: writing %u byte from %p\n", __func__, len, buf); + + command_mode = BV_GPMI_CTRL0_COMMAND_MODE__WRITE; + address = BV_GPMI_CTRL0_ADDRESS__NAND_DATA; + + gpmi->pio_data[0] = + BF_GPMI_CTRL0_COMMAND_MODE(command_mode) | + BF_GPMI_CTRL0_CS_V1(cs) | + BM_GPMI_CTRL0_WORD_LENGTH | + BF_GPMI_CTRL0_ADDRESS(address) | + BF_GPMI_CTRL0_XFER_COUNT(len); + gpmi->pio_data[1] = 0; + + ret = mxs_gpmi_dma_xfer(gpmi, xfer_buf, len, 2, DMA_TO_DEVICE); +#else + ret = mxs_gpmi_send_data(gpmi, gpmi->current_chip, xfer_buf, len); +#endif + if (ret) + printk(KERN_ERR "%s: Failed to write %u byte from %p\n", __func__, + len, buf); +} + +static int mxs_gpmi_scan_bbt(struct mtd_info *mtd) +{ + int ret; + + DBG(0, "%s: \n", __func__); + ret = nand_scan_bbt(mtd, create_bbt ? &gpmi_bbt_descr : NULL); + DBG(0, "%s: nand_scan_bbt() returned %d\n", __func__, ret); + return ret; +} + +static int mxs_gpmi_send_command(struct mxs_gpmi *gpmi, unsigned cs, + void *buffer, unsigned int length) +{ + int error; + u32 command_mode; + u32 address; + + DBG(1, "%s: Sending NAND command\n", __func__); + + command_mode = BV_GPMI_CTRL0_COMMAND_MODE__WRITE; + address = BV_GPMI_CTRL0_ADDRESS__NAND_CLE; + + gpmi->pio_data[0] = + BF_GPMI_CTRL0_COMMAND_MODE(command_mode) | + BF_GPMI_CTRL0_CS_V1(cs) | + BM_GPMI_CTRL0_WORD_LENGTH | + BF_GPMI_CTRL0_ADDRESS(address) | + BM_GPMI_CTRL0_ADDRESS_INCREMENT | + BF_GPMI_CTRL0_XFER_COUNT(length); + + gpmi->pio_data[1] = 0; + + gpmi->pio_data[2] = 0; + + error = mxs_gpmi_dma_xfer(gpmi, buffer, length, 3, + DMA_TO_DEVICE); + if (error) + printk(KERN_ERR "[%s] DMA error\n", __func__); + + return error; +} + +static void mxs_gpmi_cmdctrl(struct mtd_info *mtd, + int data, unsigned int ctrl) +{ + int ret; + struct nand_chip *chip = mtd->priv; + struct mxs_gpmi *gpmi = chip->priv; + unsigned int i; + + DBG(2, "%s: data=%04x ctrl=%04x\n", __func__, + data, ctrl); + /* + * Every operation begins with a command byte and a series of zero or + * more address bytes. These are distinguished by either the Address + * Latch Enable (ALE) or Command Latch Enable (CLE) signals being + * asserted. When MTD is ready to execute the command, it will deassert + * both latch enables. + * + * Rather than run a separate DMA operation for every single byte, we + * queue them up and run a single DMA operation for the entire series + * of command and data bytes. + */ + if ((ctrl & (NAND_ALE | NAND_CLE))) { + if (data != NAND_CMD_NONE) { + DBG(3, "%s: Storing cmd byte %02x\n", __func__, data & 0xff); + gpmi->cmd_buf[gpmi->command_length++] = data; + } + return; + } + /* + * If control arrives here, MTD has deasserted both the ALE and CLE, + * which means it's ready to run an operation. Check if we have any + * bytes to send. + */ + if (gpmi->command_length == 0) + return; + + DBG(1, "%s: sending command...\n", __func__); + for (i = 0; i < gpmi->command_length; i++) + DBG(2, " 0x%02x", gpmi->cmd_buf[i]); + DBG(2, "\n"); + + ret = mxs_gpmi_send_command(gpmi, + gpmi->current_chip, gpmi->cmd_buf, + gpmi->command_length); + if (ret) { + printk(KERN_ERR "[%s] Chip: %u, Error %d\n", + __func__, gpmi->current_chip, ret); + } + + gpmi->command_length = 0; + DBG(1, "%s: ...Finished\n", __func__); +} + +static int mxs_gpmi_set_ecclayout(struct mxs_gpmi *gpmi, + int page_size, int oob_size) +{ + struct nand_chip *chip = gpmi->chip; + struct mtd_info *mtd = gpmi->mtd; + struct nand_ecclayout *layout = &gpmi->ecc_layout; + const int meta_size = 10; + const int block0_size = 512; + const int blockn_size = 512; + const int fl0_nblocks = (mtd->writesize >> 9) - !!block0_size; + int i; + + chip->ecc.mode = NAND_ECC_HW; + chip->ecc.size = blockn_size; + chip->ecc.layout = layout; + + chip->bbt_td = &mxs_gpmi_bbt_main_descr; + chip->bbt_md = &mxs_gpmi_bbt_mirror_descr; + + if (create_bbt) { + chip->bbt_td->options |= NAND_BBT_WRITE | NAND_BBT_CREATE; + chip->bbt_md->options |= NAND_BBT_WRITE | NAND_BBT_CREATE; + } + + switch (page_size) { + case 2048: + /* default GPMI OOB layout */ + layout->eccbytes = 4 * 10 + 9; + gpmi->block0_ecc_strength = 8; + gpmi->blockn_ecc_strength = 8; + break; + + case 4096: + if (mtd->oobsize == 128) { + gpmi->block0_ecc_strength = 8; + gpmi->blockn_ecc_strength = 8; + } else { + gpmi->block0_ecc_strength = 16; + gpmi->blockn_ecc_strength = 16; + } + break; + + case 8192: + gpmi->block0_ecc_strength = 24; + gpmi->blockn_ecc_strength = 24; + break; + + default: + printk(KERN_ERR "unsupported page size: %u\n", page_size); + return -EINVAL; + } + + { + int chunk0_data_size_in_bits = block0_size * 8; + int chunk0_ecc_size_in_bits = gpmi->block0_ecc_strength * 13; + int chunkn_data_size_in_bits = blockn_size * 8; + int chunkn_ecc_size_in_bits = gpmi->blockn_ecc_strength * 13; + int chunkn_total_size_in_bits = chunkn_data_size_in_bits + + chunkn_ecc_size_in_bits; + + /* Compute the bit offset of the block mark within the physical page. */ + int block_mark_bit_offset = mtd->writesize * 8; + + /* Subtract the metadata bits. */ + block_mark_bit_offset -= meta_size * 8; + + /* if the first block is metadata only, + * subtract the number of ecc bits of that block + */ + if (block0_size == 0) { + block_mark_bit_offset -= chunk0_ecc_size_in_bits; + } + /* + * Compute the chunk number (starting at zero) in which the block mark + * appears. + */ + int block_mark_chunk_number = + block_mark_bit_offset / chunkn_total_size_in_bits; + + /* + * Compute the bit offset of the block mark within its chunk, and + * validate it. + */ + int block_mark_chunk_bit_offset = block_mark_bit_offset - + (block_mark_chunk_number * chunkn_total_size_in_bits); + + if (block_mark_chunk_bit_offset > chunkn_data_size_in_bits) { + /* + * If control arrives here, the block mark actually appears in + * the ECC bits of this chunk. This wont' work. + */ + printf("Unsupported page geometry (block mark in ECC): %u:%u", + mtd->writesize, mtd->oobsize); + return -EINVAL; + } + + /* + * Now that we know the chunk number in which the block mark appears, + * we can subtract all the ECC bits that appear before it. + */ + block_mark_bit_offset -= block_mark_chunk_number * + chunkn_ecc_size_in_bits; + + /* + * We now know the absolute bit offset of the block mark within the + * ECC-based data. We can now compute the byte offset and the bit + * offset within the byte. + */ + gpmi->block_mark_byte_offset = block_mark_bit_offset / 8; + gpmi->block_mark_bit_offset = block_mark_bit_offset % 8; + + DBG(0, "NAND geometry:\n"); + DBG(0, "page size : %5u byte\n", mtd->writesize); + DBG(0, "oob size : %5u byte\n", mtd->oobsize); + DBG(0, "erase size : %5u byte\n", mtd->erasesize); + DBG(0, "metadata : %5u byte\n", meta_size); + DBG(0, "ECC:\n"); + DBG(0, "chunk0 level: %5u\n", gpmi->block0_ecc_strength); + DBG(0, "chunk0 data : %5u bit (%5u byte)\n", + chunk0_data_size_in_bits, + DIV_ROUND_UP(chunk0_data_size_in_bits, 8)); + DBG(0, "chunk0 ECC : %5u bit (%5u byte)\n", + chunk0_ecc_size_in_bits, + DIV_ROUND_UP(chunk0_ecc_size_in_bits, 8)); + + DBG(0, "chunkn level: %5u\n", gpmi->blockn_ecc_strength); + DBG(0, "chunkn data : %5u bit (%5u byte)\n", + chunkn_data_size_in_bits, + DIV_ROUND_UP(chunkn_data_size_in_bits, 8)); + DBG(0, "chunkn ECC : %5u bit (%5u byte)\n", + chunkn_ecc_size_in_bits, + DIV_ROUND_UP(chunkn_ecc_size_in_bits, 8)); + DBG(0, "BB chunk : %5d\n", block_mark_chunk_number); + DBG(0, "BB byte offs: %5u\n", gpmi->block_mark_byte_offset); + DBG(0, "BB bit offs : %5u\n", gpmi->block_mark_bit_offset); + } + + for (i = 0; i < layout->eccbytes; i++) { + layout->eccpos[i] = mtd->oobsize - i - 1; + } + layout->oobfree[0].length = meta_size; + + chip->ecc.bytes = layout->eccbytes; + + DBG(0, "%s: Resetting BCH\n", __func__); + mxs_reset_block(gpmi->bch_regs); + + mxs_bch_writel( + BF_BCH_FLASH0LAYOUT0_NBLOCKS(fl0_nblocks) | + BF_BCH_FLASH0LAYOUT0_META_SIZE(meta_size) | + BF_BCH_FLASH0LAYOUT0_ECC0(gpmi->block0_ecc_strength >> 1) | + BF_BCH_FLASH0LAYOUT0_DATA0_SIZE(block0_size), + gpmi, HW_BCH_FLASH0LAYOUT0); + + mxs_bch_writel( + BF_BCH_FLASH0LAYOUT1_PAGE_SIZE(mtd->writesize + mtd->oobsize) | + BF_BCH_FLASH0LAYOUT1_ECCN(gpmi->blockn_ecc_strength >> 1) | + BF_BCH_FLASH0LAYOUT1_DATAN_SIZE(blockn_size), + gpmi, HW_BCH_FLASH0LAYOUT1); + + mxs_bch_writel(0, gpmi, HW_BCH_LAYOUTSELECT); + + mxs_bch_writel(BM_BCH_CTRL_COMPLETE_IRQ_EN, gpmi, HW_BCH_CTRL_SET); + return 0; +} + +int mxs_gpmi_nand_init(struct mtd_info *mtd, struct nand_chip *chip) +{ + int ret; + struct mxs_gpmi *gpmi; + + gpmi = kzalloc(sizeof(struct mxs_gpmi), GFP_KERNEL); + if (gpmi == NULL) { + ret = -ENOMEM; + return ret; + } + gpmi->mtd = mtd; + gpmi->chip = chip; + + gpmi->chip_count = CONFIG_SYS_MAX_NAND_DEVICE; + gpmi->swap_block_mark = 1; + + gpmi->gpmi_regs = __ioremap(GPMI_BASE_ADDR, SZ_4K, 1); + if (gpmi->gpmi_regs == NULL) { + ret = -ENOMEM; + goto out; + } + + gpmi->bch_regs = __ioremap(BCH_BASE_ADDR, SZ_4K, 1); + if (gpmi->bch_regs == NULL) { + ret = -ENOMEM; + goto out; + } + + gpmi->dma_regs = __ioremap(APBHDMA_BASE_ADDR, SZ_4K, 1); + if (gpmi->dma_regs == NULL) { + ret = -ENOMEM; + goto out; + } + + ret = mxs_dma_init(gpmi, CONFIG_SYS_MXS_DMA_CHANNEL, + CONFIG_SYS_MAX_NAND_DEVICE); + if (ret) + goto out; + + ret = mxs_gpmi_init_hw(gpmi); + if (ret) + goto out; + + chip->priv = gpmi; + + chip->select_chip = mxs_gpmi_select_chip; + chip->cmd_ctrl = mxs_gpmi_cmdctrl; + chip->dev_ready = mxs_gpmi_dev_ready; + + chip->read_byte = mxs_gpmi_read_byte; + chip->read_buf = mxs_gpmi_read_buf; + chip->write_buf = mxs_gpmi_write_buf; + + chip->scan_bbt = mxs_gpmi_scan_bbt; + + chip->options |= NAND_NO_SUBPAGE_WRITE; + chip->options |= NAND_USE_FLASH_BBT | NAND_USE_FLASH_BBT_NO_OOB; + + chip->ecc.read_page = mxs_gpmi_read_page; + chip->ecc.read_oob = mxs_gpmi_read_oob; + chip->ecc.write_page = mxs_gpmi_write_page; + chip->ecc.write_oob = mxs_gpmi_write_oob; + + DBG(0, "%s: Scanning for NAND chips\n", __func__); + ret = nand_scan_ident(mtd, gpmi->chip_count); + if (ret) { + DBG(0, "%s: Failed to scan for NAND chips\n", __func__); + goto out; + } + DBG(0, "%s: pagesize=%d oobsize=%d\n", __func__, + mtd->writesize, mtd->oobsize); + + gpmi->page_buf = kzalloc(mtd->writesize + mtd->oobsize, GFP_KERNEL); + if (gpmi->page_buf == NULL) { + ret = -ENOMEM; + return ret; + } + gpmi->oob_buf = gpmi->page_buf + mtd->writesize; + + ret = mxs_gpmi_set_ecclayout(gpmi, mtd->writesize, mtd->oobsize); + if (ret) { + DBG(0, "%s: Unsupported ECC layout\n", __func__); + return ret; + } + DBG(0, "%s: NAND scan succeeded\n", __func__); + return 0; +out: + kfree(gpmi); + return ret; +} diff --git a/drivers/mtd/nand/mxs_gpmi.h b/drivers/mtd/nand/mxs_gpmi.h new file mode 100644 index 0000000000..a5c273fc55 --- /dev/null +++ b/drivers/mtd/nand/mxs_gpmi.h @@ -0,0 +1,361 @@ +/* + * Freescale GPMI NFC NAND Flash Driver + * + * Copyright (C) 2010 Freescale Semiconductor, Inc. + * Copyright (C) 2008 Embedded Alley Solutions, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef __DRIVERS_MTD_NAND_GPMI_NFC_H +#define __DRIVERS_MTD_NAND_GPMI_NFC_H + +/* + *------------------------------------------------------------------------------ + * Fundamental Macros + *------------------------------------------------------------------------------ + */ + +#define NFC_DMA_DESCRIPTOR_COUNT 4 + +/* Define this macro to enable detailed information messages. */ +#define DETAILED_INFO + +/* Define this macro to enable event reporting. */ +/*#define EVENT_REPORTING*/ + +/* + *------------------------------------------------------------------------------ + * Fundamental Data Structures + *------------------------------------------------------------------------------ + */ + +#define COMMAND_BUFFER_SIZE 10 + +/** + * struct gpmi_nfc_timing - GPMI NFC timing parameters. + * + * This structure contains the fundamental timing attributes for the NAND Flash + * bus and the GPMI NFC hardware. + * + * @data_setup_in_ns: The data setup time, in nanoseconds. Usually the + * maximum of tDS and tWP. A negative value + * indicates this characteristic isn't known. + * @data_hold_in_ns: The data hold time, in nanoseconds. Usually the + * maximum of tDH, tWH and tREH. A negative value + * indicates this characteristic isn't known. + * @address_setup_in_ns: The address setup time, in nanoseconds. Usually + * the maximum of tCLS, tCS and tALS. A negative + * value indicates this characteristic isn't known. + * @gpmi_sample_time_in_ns: A GPMI-specific timing parameter. A negative + * value indicates this characteristic isn't known. + * @tREA_in_ns: tREA, in nanoseconds, from the data sheet. A + * negative value indicates this characteristic + * isn't known. + * @tRLOH_in_ns: tRLOH, in nanoseconds, from the data sheet. A + * negative value indicates this characteristic + * isn't known. + * @tRHOH_in_ns: tRHOH, in nanoseconds, from the data sheet. A + * negative value indicates this characteristic + * isn't known. + */ +struct gpmi_nfc_timing { + int8_t data_setup_in_ns; + int8_t data_hold_in_ns; + int8_t address_setup_in_ns; + int8_t gpmi_sample_delay_in_ns; + int8_t tREA_in_ns; + int8_t tRLOH_in_ns; + int8_t tRHOH_in_ns; +}; +#if 0 +enum nand_device_cell_technology { + NAND_DEVICE_CELL_TECH_SLC = 0, + NAND_DEVICE_CELL_TECH_MLC = 1, +}; + +struct nand_device_info { + /* End of table marker */ + bool end_of_table; + + /* Manufacturer and Device codes */ + uint8_t manufacturer_code; + uint8_t device_code; + + /* Technology */ + enum nand_device_cell_technology cell_technology; + + /* Geometry */ + uint64_t chip_size_in_bytes; + uint32_t block_size_in_pages; + uint16_t page_total_size_in_bytes; + + /* ECC */ + uint8_t ecc_strength_in_bits; + uint16_t ecc_size_in_bytes; + + /* Timing */ + int8_t data_setup_in_ns; + int8_t data_hold_in_ns; + int8_t address_setup_in_ns; + int8_t gpmi_sample_delay_in_ns; + int8_t tREA_in_ns; + int8_t tRLOH_in_ns; + int8_t tRHOH_in_ns; + + /* human readable device description */ + const char *description; +}; + +/** + * struct gpmi_nfc_data - i.MX NFC per-device data. + * + * Note that the "device" managed by this driver represents the NAND Flash + * controller *and* the NAND Flash medium behind it. Thus, the per-device data + * structure has information about the controller, the chips to which it is + * connected, and properties of the medium as a whole. + * + * @dev: A pointer to the owning struct device. + * @pdev: A pointer to the owning struct platform_device. + * @pdata: A pointer to the device's platform data. + * @device_info: A structure that contains detailed information about + * the NAND Flash device. + * @nfc: A pointer to a structure that represents the underlying + * NFC hardware. + * @rom: A pointer to a structure that represents the underlying + * Boot ROM. + * @mil: A collection of information used by the MTD Interface + * Layer. + */ +struct gpmi_nfc_data { + /* System Interface */ + struct device *dev; + struct platform_device *pdev; + struct gpmi_nfc_platform_data *pdata; + + /* Resources */ + struct clk *clock; + void __iomem *gpmi_regs; + void __iomem *bch_regs; + unsigned int bch_interrupt; + unsigned int dma_low_channel; + unsigned int dma_high_channel; + unsigned int dma_interrupt; + +// struct resources resources; + + /* NFC HAL */ + /* Hardware attributes. */ + unsigned int max_chip_count; + + /* Working variables. */ + struct mxs_dma_desc *dma_descriptors[NFC_DMA_DESCRIPTOR_COUNT]; + int isr_dma_channel; + struct completion dma_done; + struct completion bch_done; + struct gpmi_nfc_timing timing; +// struct nfc_hal *nfc; + int current_chip; + + /* MTD Interface Layer */ + struct mtd_info mtd; + struct nand_chip chip; + struct nand_ecclayout oob_layout; + struct mtd_partition *partitions; + unsigned int partition_count; + + /* DMA Buffers */ + u8 *cmd_virt; + dma_addr_t cmd_phys; + unsigned int command_length; + + void *page_buffer_virt; + dma_addr_t page_buffer_phys; + unsigned int page_buffer_size; + + void *payload_virt; + dma_addr_t payload_phys; + + void *auxiliary_virt; + dma_addr_t auxiliary_phys; +}; + +/** + * struct nfc_hal - GPMI NFC HAL + * + * This structure embodies an abstract interface to the underlying NFC hardware. + * + * @version: The NFC hardware version. + * @description: A pointer to a human-readable description of + * the NFC hardware. + * @max_chip_count: The maximum number of chips the NFC can + * possibly support (this value is a constant + * for each NFC version). This may *not* be the + * actual number of chips connected. + * @max_data_setup_cycles: The maximum number of data setup cycles + * that can be expressed in the hardware. + * @max_data_sample_delay_cycles: The maximum number of data sample delay + * cycles that can be expressed in the hardware. + * @max_dll_clock_period_in_ns: The maximum period of the GPMI clock that the + * sample delay DLL hardware can possibly work + * with (the DLL is unusable with longer + * periods). At HALF this value, the DLL must be + * configured to use half-periods. + * @dma_descriptors: A pool of DMA descriptors. + * @isr_dma_channel: The DMA channel with which the NFC HAL is + * working. We record this here so the ISR knows + * which DMA channel to acknowledge. + * @dma_done: The completion structure used for DMA + * interrupts. + * @bch_done: The completion structure used for BCH + * interrupts. + * @timing: The current timing configuration. + * @init: Initializes the NFC hardware and data + * structures. This function will be called + * after everything has been set up for + * communication with the NFC itself, but before + * the platform has set up off-chip + * communication. Thus, this function must not + * attempt to communicate with the NAND Flash + * hardware. + * @set_geometry: Configures the NFC hardware and data + * structures to match the physical NAND Flash + * geometry. + * @set_geometry: Configures the NFC hardware and data + * structures to match the physical NAND Flash + * geometry. + * @exit: Shuts down the NFC hardware and data + * structures. This function will be called + * after the platform has shut down off-chip + * communication but while communication with + * the NFC itself still works. + * @clear_bch: Clears a BCH interrupt (intended to be called + * by a more general interrupt handler to do + * device-specific clearing). + * @is_ready: Returns true if the given chip is ready. + * @begin: Begins an interaction with the NFC. This + * function must be called before *any* of the + * following functions so the NFC can prepare + * itself. + * @end: Ends interaction with the NFC. This function + * should be called to give the NFC a chance to, + * among other things, enter a lower-power + * state. + * @send_command: Sends the given buffer of command bytes. + * @send_data: Sends the given buffer of data bytes. + * @read_data: Reads data bytes into the given buffer. + * @send_page: Sends the given given data and OOB bytes, + * using the ECC engine. + * @read_page: Reads a page through the ECC engine and + * delivers the data and OOB bytes to the given + * buffers. + */ + +struct nfc_hal { + /* Hardware attributes. */ + const unsigned int version; + const char *description; + const unsigned int max_chip_count; + const unsigned int max_data_setup_cycles; + const unsigned int max_data_sample_delay_cycles; + const unsigned int max_dll_clock_period_in_ns; + + /* Working variables. */ + struct mxs_dma_desc *dma_descriptors[NFC_DMA_DESCRIPTOR_COUNT]; + int isr_dma_channel; + struct completion dma_done; + struct completion bch_done; + struct gpmi_nfc_timing timing; + + /* Configuration functions. */ + int (*init) (struct gpmi_nfc_data *); + int (*set_geometry)(struct gpmi_nfc_data *); + int (*set_timing) (struct gpmi_nfc_data *, + const struct gpmi_nfc_timing *); + void (*exit) (struct gpmi_nfc_data *); + + /* Call these functions to begin and end I/O. */ + + void (*begin) (struct gpmi_nfc_data *); + void (*end) (struct gpmi_nfc_data *); + + /* Call these I/O functions only between begin() and end(). */ + + void (*clear_bch) (struct gpmi_nfc_data *); + int (*is_ready) (struct gpmi_nfc_data *, unsigned chip); + int (*send_command)(struct gpmi_nfc_data *, unsigned chip, + dma_addr_t buffer, unsigned length); + int (*send_data) (struct gpmi_nfc_data *, unsigned chip, + dma_addr_t buffer, unsigned length); + int (*read_data) (struct gpmi_nfc_data *, unsigned chip, + dma_addr_t buffer, unsigned length); + int (*send_page) (struct gpmi_nfc_data *, unsigned chip, + dma_addr_t payload, dma_addr_t auxiliary); + int (*read_page) (struct gpmi_nfc_data *, unsigned chip, + dma_addr_t payload, dma_addr_t auxiliary); +}; + +/** + * struct boot_rom_helper - Boot ROM Helper + * + * This structure embodies the interface to an object that assists the driver + * in making decisions that relate to the Boot ROM. + * + * @version: The Boot ROM version. + * @description: A pointer to a human-readable description of the + * Boot ROM. + * @swap_block_mark: Indicates that the Boot ROM will swap the block + * mark with the first byte of the OOB. + * @set_geometry: Configures the Boot ROM geometry. + * @check_transcription_stamp: Checks for a transcription stamp. This pointer + * is ignored if swap_block_mark is set. + * @write_transcription_stamp: Writes a transcription stamp. This pointer + * is ignored if swap_block_mark is set. + */ + +struct boot_rom_helper { + const unsigned int version; + const char *description; + const int swap_block_mark; + int (*set_geometry) (struct gpmi_nfc_data *); + int (*check_transcription_stamp)(struct gpmi_nfc_data *); + int (*write_transcription_stamp)(struct gpmi_nfc_data *); +}; + +/* + *------------------------------------------------------------------------------ + * External Symbols + *------------------------------------------------------------------------------ + */ + +/* Event Reporting */ + +#if defined(EVENT_REPORTING) +#if 0 + extern void gpmi_nfc_start_event_trace(char *description); + extern void gpmi_nfc_add_event(char *description, int delta); + extern void gpmi_nfc_stop_event_trace(char *description); + extern void gpmi_nfc_dump_event_trace(void); +#endif +#else + #define gpmi_nfc_start_event_trace(description) do {} while (0) + #define gpmi_nfc_add_event(description, delta) do {} while (0) + #define gpmi_nfc_stop_event_trace(description) do {} while (0) + #define gpmi_nfc_dump_event_trace() do {} while (0) +#endif /* EVENT_REPORTING */ + +#endif /* 0 */ + +#endif /* __DRIVERS_MTD_NAND_GPMI_NFC_H */ diff --git a/drivers/mtd/nand/nand.c b/drivers/mtd/nand/nand.c index 9065fa91c6..4930b76237 100644 --- a/drivers/mtd/nand/nand.c +++ b/drivers/mtd/nand/nand.c @@ -50,7 +50,7 @@ static void nand_init_chip(struct mtd_info *mtd, struct nand_chip *nand, mtd->priv = nand; nand->IO_ADDR_R = nand->IO_ADDR_W = (void __iomem *)base_addr; - if (board_nand_init(nand) == 0) { + if (board_nand_init(mtd, nand) == 0) { if (nand_scan(mtd, maxchips) == 0) { if (!mtd->name) mtd->name = (char *)default_nand_name; diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c index 360b070849..04787401c0 100644 --- a/drivers/mtd/nand/nand_base.c +++ b/drivers/mtd/nand/nand_base.c @@ -867,8 +867,8 @@ static int nand_wait(struct mtd_info *mtd, struct nand_chip *this) while (1) { if (get_timer(0) > timeo) { - printf("Timeout!"); - return 0x01; + /*printf("Timeout!");*/ + /*return 0x01;*/ } if (this->dev_ready) { @@ -2529,7 +2529,8 @@ static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd, mtd->writesize = 1024 << (extid & 0x3); extid >>= 2; /* Calc oobsize */ - mtd->oobsize = (8 << (extid & 0x01)) * (mtd->writesize >> 9); + mtd->oobsize = (*maf_id == 0x2c && dev_id == 0xd5) ? + 218 : (8 << (extid & 0x01)) * (mtd->writesize >> 9); extid >>= 2; /* Calc blocksize. Blocksize is multiples of 64KiB */ mtd->erasesize = (64 * 1024) << (extid & 0x03); @@ -2866,10 +2867,9 @@ int nand_scan_tail(struct mtd_info *mtd) mtd->ecclayout = chip->ecc.layout; /* Check, if we should skip the bad block table scan */ - if (chip->options & NAND_SKIP_BBTSCAN) - chip->options |= NAND_BBT_SCANNED; + chip->options |= NAND_BBT_SCANNED; - return 0; + return chip->scan_bbt(mtd); } /* module_text_address() isn't exported, and it's mostly a pointless diff --git a/drivers/mtd/nand/nand_bbt.c b/drivers/mtd/nand/nand_bbt.c index d68a315f19..5f60edb6da 100644 --- a/drivers/mtd/nand/nand_bbt.c +++ b/drivers/mtd/nand/nand_bbt.c @@ -13,27 +13,36 @@ * Description: * * When nand_scan_bbt is called, then it tries to find the bad block table - * depending on the options in the bbt descriptor(s). If a bbt is found - * then the contents are read and the memory based bbt is created. If a - * mirrored bbt is selected then the mirror is searched too and the - * versions are compared. If the mirror has a greater version number - * than the mirror bbt is used to build the memory based bbt. + * depending on the options in the BBT descriptor(s). If no flash based BBT + * (NAND_USE_FLASH_BBT) is specified then the device is scanned for factory + * marked good / bad blocks. This information is used to create a memory BBT. + * Once a new bad block is discovered then the "factory" information is updated + * on the device. + * If a flash based BBT is specified then the function first tries to find the + * BBT on flash. If a BBT is found then the contents are read and the memory + * based BBT is created. If a mirrored BBT is selected then the mirror is + * searched too and the versions are compared. If the mirror has a greater + * version number than the mirror BBT is used to build the memory based BBT. * If the tables are not versioned, then we "or" the bad block information. - * If one of the bbt's is out of date or does not exist it is (re)created. - * If no bbt exists at all then the device is scanned for factory marked + * If one of the BBTs is out of date or does not exist it is (re)created. + * If no BBT exists at all then the device is scanned for factory marked * good / bad blocks and the bad block tables are created. * - * For manufacturer created bbts like the one found on M-SYS DOC devices - * the bbt is searched and read but never created + * For manufacturer created BBTs like the one found on M-SYS DOC devices + * the BBT is searched and read but never created * - * The autogenerated bad block table is located in the last good blocks + * The auto generated bad block table is located in the last good blocks * of the device. The table is mirrored, so it can be updated eventually. - * The table is marked in the oob area with an ident pattern and a version - * number which indicates which of both tables is more up to date. + * The table is marked in the OOB area with an ident pattern and a version + * number which indicates which of both tables is more up to date. If the NAND + * controller needs the complete OOB area for the ECC information then the + * option NAND_USE_FLASH_BBT_NO_OOB should be used: it moves the ident pattern + * and the version byte into the data area and the OOB area will remain + * untouched. * * The table uses 2 bits per block - * 11b: block is good - * 00b: block is factory marked bad + * 11b: block is good + * 00b: block is factory marked bad * 01b, 10b: block is marked bad due to wear * * The memory bad block table uses the following scheme: @@ -70,6 +79,15 @@ #include #include #endif +static int check_pattern_no_oob(uint8_t *buf, struct nand_bbt_descr *td) +{ + int ret; + + ret = memcmp(buf, td->pattern, td->len); + if (!ret) + return ret; + return -1; +} /** * check_pattern - [GENERIC] check if a pattern is in the buffer @@ -89,6 +107,9 @@ static int check_pattern(uint8_t *buf, int len, int paglen, struct nand_bbt_desc int i, end = 0; uint8_t *p = buf; + if (td->options & NAND_BBT_NO_OOB) + return check_pattern_no_oob(buf, td); + end = paglen + td->offs; if (td->options & NAND_BBT_SCANEMPTY) { for (i = 0; i < end; i++) { @@ -138,33 +159,64 @@ static int check_short_pattern(uint8_t *buf, struct nand_bbt_descr *td) return 0; } +/** + * add_marker_len - compute the length of the marker in data area + * @td: BBT descriptor used for computation + * + * The length will be 0 if the markeris located in OOB area. + */ +static u32 add_marker_len(struct nand_bbt_descr *td) +{ + u32 len; + + if (!(td->options & NAND_BBT_NO_OOB)) + return 0; + + len = td->len; + if (td->options & NAND_BBT_VERSION) + len++; + return len; +} + /** * read_bbt - [GENERIC] Read the bad block table starting from page * @mtd: MTD device structure * @buf: temporary buffer * @page: the starting page * @num: the number of bbt descriptors to read - * @bits: number of bits per block + * @td: the bbt describtion table * @offs: offset in the memory table - * @reserved_block_code: Pattern to identify reserved blocks * * Read the bad block table starting from page. * */ static int read_bbt(struct mtd_info *mtd, uint8_t *buf, int page, int num, - int bits, int offs, int reserved_block_code) + struct nand_bbt_descr *td, int offs) { int res, i, j, act = 0; struct nand_chip *this = mtd->priv; size_t retlen, len, totlen; loff_t from; + int bits = td->options & NAND_BBT_NRBITS_MSK; uint8_t msk = (uint8_t) ((1 << bits) - 1); + u32 marker_len; + int reserved_block_code = td->reserved_block_code; totlen = (num * bits) >> 3; + marker_len = add_marker_len(td); from = ((loff_t) page) << this->page_shift; while (totlen) { len = min(totlen, (size_t) (1 << this->bbt_erase_shift)); + if (marker_len) { + /* + * In case the BBT marker is not in the OOB area it + * will be just in the first page. + */ + len -= marker_len; + from += marker_len; + marker_len = 0; + } res = mtd->read(mtd, from, len, &retlen, buf); if (res < 0) { if (retlen != len) { @@ -190,8 +242,8 @@ static int read_bbt(struct mtd_info *mtd, uint8_t *buf, int page, int num, } /* Leave it for now, if its matured we can move this * message to MTD_DEBUG_LEVEL0 */ - printk(KERN_DEBUG "nand_read_bbt: Bad block at 0x%08x\n", - ((offs << 2) + (act >> 1)) << this->bbt_erase_shift); + MTDDEBUG(MTD_DEBUG_LEVEL0, "nand_read_bbt: Bad block at 0x%08x\n", + ((offs << 2) + (act >> 1)) << this->bbt_erase_shift); /* Factory marked bad or worn out ? */ if (tmp == 0) this->bbt[offs + (act >> 3)] |= 0x3 << (act & 0x06); @@ -221,42 +273,86 @@ static int read_abs_bbt(struct mtd_info *mtd, uint8_t *buf, struct nand_bbt_desc { struct nand_chip *this = mtd->priv; int res = 0, i; - int bits; - bits = td->options & NAND_BBT_NRBITS_MSK; if (td->options & NAND_BBT_PERCHIP) { int offs = 0; for (i = 0; i < this->numchips; i++) { if (chip == -1 || chip == i) - res = read_bbt (mtd, buf, td->pages[i], this->chipsize >> this->bbt_erase_shift, bits, offs, td->reserved_block_code); + res = read_bbt(mtd, buf, td->pages[i], + this->chipsize >> this->bbt_erase_shift, + td, offs); if (res) return res; offs += this->chipsize >> (this->bbt_erase_shift + 2); } } else { - res = read_bbt (mtd, buf, td->pages[0], mtd->size >> this->bbt_erase_shift, bits, 0, td->reserved_block_code); + res = read_bbt(mtd, buf, td->pages[0], + mtd->size >> this->bbt_erase_shift, td, 0); if (res) return res; } return 0; } +/* + * BBT marker is in the first page, no OOB. + */ +static int scan_read_raw_data(struct mtd_info *mtd, uint8_t *buf, loff_t offs, + struct nand_bbt_descr *td) +{ + size_t retlen; + size_t len; + + len = td->len; + if (td->options & NAND_BBT_VERSION) + len++; + + return mtd->read(mtd, offs, len, &retlen, buf); +} + /* * Scan read raw data from flash */ -static int scan_read_raw(struct mtd_info *mtd, uint8_t *buf, loff_t offs, +static int scan_read_raw_oob(struct mtd_info *mtd, uint8_t *buf, loff_t offs, size_t len) { struct mtd_oob_ops ops; + int res; ops.mode = MTD_OOB_RAW; ops.ooboffs = 0; ops.ooblen = mtd->oobsize; - ops.oobbuf = buf; - ops.datbuf = buf; - ops.len = len; - return mtd->read_oob(mtd, offs, &ops); + + while (len > 0) { + if (len <= mtd->writesize) { + ops.oobbuf = buf + len; + ops.datbuf = buf; + ops.len = len; + return mtd->read_oob(mtd, offs, &ops); + } else { + ops.oobbuf = buf + mtd->writesize; + ops.datbuf = buf; + ops.len = mtd->writesize; + res = mtd->read_oob(mtd, offs, &ops); + + if (res) + return res; + } + + buf += mtd->oobsize + mtd->writesize; + len -= mtd->writesize; + } + return 0; +} + +static int scan_read_raw(struct mtd_info *mtd, uint8_t *buf, loff_t offs, + size_t len, struct nand_bbt_descr *td) +{ + if (td->options & NAND_BBT_NO_OOB) + return scan_read_raw_data(mtd, buf, offs, td); + else + return scan_read_raw_oob(mtd, buf, offs, len); } /* @@ -277,6 +373,15 @@ static int scan_write_bbt(struct mtd_info *mtd, loff_t offs, size_t len, return mtd->write_oob(mtd, offs, &ops); } +static u32 bbt_get_ver_offs(struct mtd_info *mtd, struct nand_bbt_descr *td) +{ + u32 ver_offs = td->veroffs; + + if (!(td->options & NAND_BBT_NO_OOB)) + ver_offs += mtd->writesize; + return ver_offs; +} + /** * read_abs_bbts - [GENERIC] Read the bad block table(s) for all chips starting at a given page * @mtd: MTD device structure @@ -296,8 +401,8 @@ static int read_abs_bbts(struct mtd_info *mtd, uint8_t *buf, /* Read the primary version, if available */ if (td->options & NAND_BBT_VERSION) { scan_read_raw(mtd, buf, td->pages[0] << this->page_shift, - mtd->writesize); - td->version[0] = buf[mtd->writesize + td->veroffs]; + mtd->writesize, td); + td->version[0] = buf[bbt_get_ver_offs(mtd, td)]; printk(KERN_DEBUG "Bad block table at page %d, version 0x%02X\n", td->pages[0], td->version[0]); } @@ -305,8 +410,8 @@ static int read_abs_bbts(struct mtd_info *mtd, uint8_t *buf, /* Read the mirror version, if available */ if (md && (md->options & NAND_BBT_VERSION)) { scan_read_raw(mtd, buf, md->pages[0] << this->page_shift, - mtd->writesize); - md->version[0] = buf[mtd->writesize + md->veroffs]; + mtd->writesize, td); + md->version[0] = buf[bbt_get_ver_offs(mtd, md)]; printk(KERN_DEBUG "Bad block table at page %d, version 0x%02X\n", md->pages[0], md->version[0]); } @@ -322,7 +427,7 @@ static int scan_block_full(struct mtd_info *mtd, struct nand_bbt_descr *bd, { int ret, j; - ret = scan_read_raw(mtd, buf, offs, readlen); + ret = scan_read_raw_oob(mtd, buf, offs, readlen); if (ret) return ret; @@ -386,16 +491,14 @@ static int create_bbt(struct mtd_info *mtd, uint8_t *buf, loff_t from; size_t readlen; - MTDDEBUG (MTD_DEBUG_LEVEL0, "Scanning device for bad blocks\n"); + printk(KERN_INFO "Scanning device for bad blocks\n"); if (bd->options & NAND_BBT_SCANALLPAGES) len = 1 << (this->bbt_erase_shift - this->page_shift); - else { - if (bd->options & NAND_BBT_SCAN2NDPAGE) - len = 2; - else - len = 1; - } + else if (bd->options & NAND_BBT_SCAN2NDPAGE) + len = 2; + else + len = 1; if (!(bd->options & NAND_BBT_SCANEMPTY)) { /* We need only read few bytes from the OOB area */ @@ -428,6 +531,8 @@ static int create_bbt(struct mtd_info *mtd, uint8_t *buf, for (i = startblock; i < numblocks;) { int ret; + BUG_ON(bd->options & NAND_BBT_NO_OOB); + if (bd->options & NAND_BBT_SCANALLPAGES) ret = scan_block_full(mtd, bd, from, buf, readlen, scanlen, len); @@ -439,9 +544,8 @@ static int create_bbt(struct mtd_info *mtd, uint8_t *buf, if (ret) { this->bbt[i >> 3] |= 0x03 << (i & 0x6); - MTDDEBUG (MTD_DEBUG_LEVEL0, - "Bad eraseblock %d at 0x%08x\n", - i >> 1, (unsigned int)from); + printk(KERN_WARNING "Bad eraseblock %d at 0x%012llx\n", + i >> 1, (unsigned long long)from); mtd->ecc_stats.badblocks++; } @@ -510,11 +614,12 @@ static int search_bbt(struct mtd_info *mtd, uint8_t *buf, struct nand_bbt_descr loff_t offs = actblock << this->bbt_erase_shift; /* Read first page */ - scan_read_raw(mtd, buf, offs, mtd->writesize); + scan_read_raw(mtd, buf, offs, mtd->writesize, td); if (!check_pattern(buf, scanlen, mtd->writesize, td)) { td->pages[i] = actblock << blocktopage; if (td->options & NAND_BBT_VERSION) { - td->version[i] = buf[mtd->writesize + td->veroffs]; + offs = bbt_get_ver_offs(mtd, td); + td->version[i] = buf[offs]; } break; } @@ -526,8 +631,9 @@ static int search_bbt(struct mtd_info *mtd, uint8_t *buf, struct nand_bbt_descr if (td->pages[i] == -1) printk(KERN_WARNING "Bad block table not found for chip %d\n", i); else - printk(KERN_DEBUG "Bad block table found at page %d, version 0x%02X\n", td->pages[i], - td->version[i]); + MTDDEBUG(MTD_DEBUG_LEVEL0, + "Bad block table found at page %d, version 0x%02X\n", + td->pages[i], td->version[i]); } return 0; } @@ -698,12 +804,26 @@ static int write_bbt(struct mtd_info *mtd, uint8_t *buf, memset(&buf[offs], 0xff, (size_t) (numblocks >> sft)); ooboffs = len + (pageoffs * mtd->oobsize); + } else if (td->options & NAND_BBT_NO_OOB) { + ooboffs = 0; + offs = td->len; + /* the version byte */ + if (td->options & NAND_BBT_VERSION) + offs++; + /* Calc length */ + len = (size_t) (numblocks >> sft); + len += offs; + /* Make it page aligned ! */ + len = ALIGN(len, mtd->writesize); + /* Preset the buffer with 0xff */ + memset(buf, 0xff, len); + /* Pattern is located at the begin of first page */ + memcpy(buf, td->pattern, td->len); } else { /* Calc length */ len = (size_t) (numblocks >> sft); /* Make it page aligned ! */ - len = (len + (mtd->writesize - 1)) & - ~(mtd->writesize - 1); + len = ALIGN(len, mtd->writesize); /* Preset the buffer with 0xff */ memset(buf, 0xff, len + (len >> this->page_shift)* mtd->oobsize); @@ -737,7 +857,9 @@ static int write_bbt(struct mtd_info *mtd, uint8_t *buf, if (res < 0) goto outerr; - res = scan_write_bbt(mtd, to, len, buf, &buf[len]); + res = scan_write_bbt(mtd, to, len, buf, + td->options & NAND_BBT_NO_OOB ? NULL : + &buf[len]); if (res < 0) goto outerr; @@ -943,10 +1065,54 @@ static void mark_bbt_region(struct mtd_info *mtd, struct nand_bbt_descr *td) new ones have been marked, then we need to update the stored bbts. This should only happen once. */ if (update && td->reserved_block_code) - nand_update_bbt(mtd, (block - 2) << (this->bbt_erase_shift - 1)); + nand_update_bbt(mtd, (loff_t)(block - 2) << (this->bbt_erase_shift - 1)); } } +/** + * verify_bbt_descr - verify the bad block description + * @mtd: MTD device structure + * @bd: the table to verify + * + * This functions performs a few sanity checks on the bad block description + * table. + */ +static void verify_bbt_descr(struct mtd_info *mtd, struct nand_bbt_descr *bd) +{ + struct nand_chip *this = mtd->priv; + u32 pattern_len = bd->len; + u32 bits = bd->options & NAND_BBT_NRBITS_MSK; + u32 table_size; + + if (!bd) + return; + BUG_ON((this->options & NAND_USE_FLASH_BBT_NO_OOB) && + !(this->options & NAND_USE_FLASH_BBT)); + BUG_ON(!bits); + + if (bd->options & NAND_BBT_VERSION) + pattern_len++; + + if (bd->options & NAND_BBT_NO_OOB) { + BUG_ON(!(this->options & NAND_USE_FLASH_BBT)); + BUG_ON(!(this->options & NAND_USE_FLASH_BBT_NO_OOB)); + BUG_ON(bd->offs); + if (bd->options & NAND_BBT_VERSION) + BUG_ON(bd->veroffs != bd->len); + BUG_ON(bd->options & NAND_BBT_SAVECONTENT); + } + + if (bd->options & NAND_BBT_PERCHIP) + table_size = this->chipsize >> this->bbt_erase_shift; + else + table_size = mtd->size >> this->bbt_erase_shift; + table_size >>= 3; + table_size *= bits; + if (bd->options & NAND_BBT_NO_OOB) + table_size += pattern_len; + BUG_ON(table_size > (1 << this->bbt_erase_shift)); +} + /** * nand_scan_bbt - [NAND Interface] scan, find, read and maybe create bad block table(s) * @mtd: MTD device structure @@ -988,6 +1154,8 @@ int nand_scan_bbt(struct mtd_info *mtd, struct nand_bbt_descr *bd) } return res; } + verify_bbt_descr(mtd, td); + verify_bbt_descr(mtd, md); /* Allocate a temporary buffer for one eraseblock incl. oob */ len = (1 << this->bbt_erase_shift); @@ -1039,7 +1207,6 @@ int nand_update_bbt(struct mtd_info *mtd, loff_t offs) if (!this->bbt || !td) return -EINVAL; - len = mtd->size >> (this->bbt_erase_shift + 2); /* Allocate a temporary buffer for one eraseblock incl. oob */ len = (1 << this->bbt_erase_shift); len += (len >> this->page_shift) * mtd->oobsize; @@ -1084,30 +1251,16 @@ int nand_update_bbt(struct mtd_info *mtd, loff_t offs) * while scanning a device for factory marked good / bad blocks. */ static uint8_t scan_ff_pattern[] = { 0xff, 0xff }; -static struct nand_bbt_descr smallpage_memorybased = { - .options = NAND_BBT_SCAN2NDPAGE, - .offs = 5, - .len = 1, - .pattern = scan_ff_pattern -}; - -static struct nand_bbt_descr largepage_memorybased = { - .options = 0, - .offs = 0, - .len = 2, - .pattern = scan_ff_pattern -}; - static struct nand_bbt_descr smallpage_flashbased = { .options = NAND_BBT_SCAN2NDPAGE, - .offs = 5, + .offs = NAND_SMALL_BADBLOCK_POS, .len = 1, .pattern = scan_ff_pattern }; static struct nand_bbt_descr largepage_flashbased = { .options = NAND_BBT_SCAN2NDPAGE, - .offs = 0, + .offs = NAND_LARGE_BADBLOCK_POS, .len = 2, .pattern = scan_ff_pattern }; @@ -1146,6 +1299,63 @@ static struct nand_bbt_descr bbt_mirror_descr = { .pattern = mirror_pattern }; +static struct nand_bbt_descr bbt_main_no_bbt_descr = { + .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE + | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP + | NAND_BBT_NO_OOB, + .len = 4, + .veroffs = 4, + .maxblocks = 4, + .pattern = bbt_pattern +}; + +static struct nand_bbt_descr bbt_mirror_no_bbt_descr = { + .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE + | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP + | NAND_BBT_NO_OOB, + .len = 4, + .veroffs = 4, + .maxblocks = 4, + .pattern = mirror_pattern +}; + +#define BBT_SCAN_OPTIONS (NAND_BBT_SCANLASTPAGE | NAND_BBT_SCAN2NDPAGE | \ + NAND_BBT_SCANBYTE1AND6) +/** + * nand_create_default_bbt_descr - [Internal] Creates a BBT descriptor structure + * @this: NAND chip to create descriptor for + * + * This function allocates and initializes a nand_bbt_descr for BBM detection + * based on the properties of "this". The new descriptor is stored in + * this->badblock_pattern. Thus, this->badblock_pattern should be NULL when + * passed to this function. + * + * TODO: Handle other flags, replace other static structs + * (e.g. handle NAND_BBT_FLASH for flash-based BBT, + * replace smallpage_flashbased) + * + */ +static int nand_create_default_bbt_descr(struct nand_chip *this) +{ + struct nand_bbt_descr *bd; + if (this->badblock_pattern) { + printk(KERN_WARNING "BBT descr already allocated; not replacing.\n"); + return -EINVAL; + } + bd = kzalloc(sizeof(*bd), GFP_KERNEL); + if (!bd) { + printk(KERN_ERR "nand_create_default_bbt_descr: Out of memory\n"); + return -ENOMEM; + } + bd->options = this->options & BBT_SCAN_OPTIONS; + bd->offs = this->badblockpos; + bd->len = (this->options & NAND_BUSWIDTH_16) ? 2 : 1; + bd->pattern = scan_ff_pattern; + bd->options |= NAND_BBT_DYNAMICSTRUCT; + this->badblock_pattern = bd; + return 0; +} + /** * nand_default_bbt - [NAND Interface] Select a default bad block table for the device * @mtd: MTD device structure @@ -1179,8 +1389,13 @@ int nand_default_bbt(struct mtd_info *mtd) if (this->options & NAND_USE_FLASH_BBT) { /* Use the default pattern descriptors */ if (!this->bbt_td) { - this->bbt_td = &bbt_main_descr; - this->bbt_md = &bbt_mirror_descr; + if (this->options & NAND_USE_FLASH_BBT_NO_OOB) { + this->bbt_td = &bbt_main_no_bbt_descr; + this->bbt_md = &bbt_mirror_no_bbt_descr; + } else { + this->bbt_td = &bbt_main_descr; + this->bbt_md = &bbt_mirror_descr; + } } if (!this->badblock_pattern) { this->badblock_pattern = (mtd->writesize > 512) ? &largepage_flashbased : &smallpage_flashbased; @@ -1188,10 +1403,8 @@ int nand_default_bbt(struct mtd_info *mtd) } else { this->bbt_td = NULL; this->bbt_md = NULL; - if (!this->badblock_pattern) { - this->badblock_pattern = (mtd->writesize > 512) ? - &largepage_memorybased : &smallpage_memorybased; - } + if (!this->badblock_pattern) + nand_create_default_bbt_descr(this); } return nand_scan_bbt(mtd, this->badblock_pattern); } @@ -1214,7 +1427,7 @@ int nand_isbad_bbt(struct mtd_info *mtd, loff_t offs, int allowbbt) res = (this->bbt[block >> 3] >> (block & 0x06)) & 0x03; MTDDEBUG (MTD_DEBUG_LEVEL2, "nand_isbad_bbt(): bbt info for offs 0x%08x: " - "(block %d) 0x%02x\n", (unsigned int)offs, res, block >> 1); + "(block %d) 0x%02x\n", (unsigned int)offs, res, block >> 1); switch ((int)res) { case 0x00: diff --git a/drivers/mtd/nand/nand_device_info.c b/drivers/mtd/nand/nand_device_info.c new file mode 100644 index 0000000000..2f3bbb6c7b --- /dev/null +++ b/drivers/mtd/nand/nand_device_info.c @@ -0,0 +1,2296 @@ +/* + * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include "nand_device_info.h" + +/* + * Type 2 + */ +static struct nand_device_info nand_device_info_table_type_2[] = +{ + { + .end_of_table = false, + .manufacturer_code = 0x20, + .device_code = 0xf1, + .cell_technology = NAND_DEVICE_CELL_TECH_SLC, + .chip_size_in_bytes = 128LL*SZ_1M, + .block_size_in_pages = 64, + .page_total_size_in_bytes = 2*SZ_1K + 64, + .ecc_strength_in_bits = 4, + .ecc_size_in_bytes = 512, + .data_setup_in_ns = 30, + .data_hold_in_ns = 20, + .address_setup_in_ns = 25, + .gpmi_sample_delay_in_ns = 6, + .tREA_in_ns = -1, + .tRLOH_in_ns = -1, + .tRHOH_in_ns = -1, + "NAND01GW3", + }, + { + .end_of_table = false, + .manufacturer_code = 0xad, + .device_code = 0xf1, + .cell_technology = NAND_DEVICE_CELL_TECH_SLC, + .chip_size_in_bytes = 128LL*SZ_1M, + .block_size_in_pages = 64, + .page_total_size_in_bytes = 2*SZ_1K + 64, + .ecc_strength_in_bits = 4, + .ecc_size_in_bytes = 512, + .data_setup_in_ns = 45, + .data_hold_in_ns = 30, + .address_setup_in_ns = 25, + .gpmi_sample_delay_in_ns = 6, + .tREA_in_ns = -1, + .tRLOH_in_ns = -1, + .tRHOH_in_ns = -1, + NULL, + }, + { + .end_of_table = false, + .manufacturer_code = 0x2c, + .device_code = 0xf1, + .cell_technology = NAND_DEVICE_CELL_TECH_SLC, + .chip_size_in_bytes = 128LL*SZ_1M, + .block_size_in_pages = 64, + .page_total_size_in_bytes = 2*SZ_1K + 64, + .ecc_strength_in_bits = 4, + .ecc_size_in_bytes = 512, + .data_setup_in_ns = 30, + .data_hold_in_ns = 20, + .address_setup_in_ns = 10, + .gpmi_sample_delay_in_ns = 6, + .tREA_in_ns = -1, + .tRLOH_in_ns = -1, + .tRHOH_in_ns = -1, + NULL, + }, + { + .end_of_table = false, + .manufacturer_code = 0xec, + .device_code = 0xf1, + .cell_technology = NAND_DEVICE_CELL_TECH_SLC, + .chip_size_in_bytes = 128LL*SZ_1M, + .block_size_in_pages = 64, + .page_total_size_in_bytes = 2*SZ_1K + 64, + .ecc_strength_in_bits = 4, + .ecc_size_in_bytes = 512, + .data_setup_in_ns = 35, + .data_hold_in_ns = 25, + .address_setup_in_ns = 0, + .gpmi_sample_delay_in_ns = 6, + .tREA_in_ns = -1, + .tRLOH_in_ns = -1, + .tRHOH_in_ns = -1, + "K9F1F08", + }, + { + .end_of_table = false, + .manufacturer_code = 0x98, + .device_code = 0xf1, + .cell_technology = NAND_DEVICE_CELL_TECH_SLC, + .chip_size_in_bytes = 128LL*SZ_1M, + .block_size_in_pages = 64, + .page_total_size_in_bytes = 2*SZ_1K + 64, + .ecc_strength_in_bits = 4, + .ecc_size_in_bytes = 512, + .data_setup_in_ns = 30, + .data_hold_in_ns = 20, + .address_setup_in_ns = 0, + .gpmi_sample_delay_in_ns = 6, + .tREA_in_ns = -1, + .tRLOH_in_ns = -1, + .tRHOH_in_ns = -1, + "TC58NVG0S3", + }, + { + .end_of_table = false, + .manufacturer_code = 0x45, + .device_code = 0xf1, + .cell_technology = NAND_DEVICE_CELL_TECH_SLC, + .chip_size_in_bytes = 128LL*SZ_1M, + .block_size_in_pages = 64, + .page_total_size_in_bytes = 2*SZ_1K + 64, + .ecc_strength_in_bits = 4, + .ecc_size_in_bytes = 512, + .data_setup_in_ns = 45, + .data_hold_in_ns = 32, + .address_setup_in_ns = 0, + .gpmi_sample_delay_in_ns = 6, + .tREA_in_ns = -1, + .tRLOH_in_ns = -1, + .tRHOH_in_ns = -1, + NULL, + }, + { + .end_of_table = false, + .manufacturer_code = 0x20, + .device_code = 0xda, + .cell_technology = NAND_DEVICE_CELL_TECH_SLC, + .chip_size_in_bytes = 256LL*SZ_1M, + .block_size_in_pages = 64, + .page_total_size_in_bytes = 2*SZ_1K + 64, + .ecc_strength_in_bits = 4, + .ecc_size_in_bytes = 512, + .data_setup_in_ns = 20, + .data_hold_in_ns = 30, + .address_setup_in_ns = 0, + .gpmi_sample_delay_in_ns = 6, + .tREA_in_ns = -1, + .tRLOH_in_ns = -1, + .tRHOH_in_ns = -1, + "NAND02GW3", + }, + { + .end_of_table = false, + .manufacturer_code = 0xad, + .device_code = 0xda, + .cell_technology = NAND_DEVICE_CELL_TECH_SLC, + .chip_size_in_bytes = 256LL*SZ_1M, + .block_size_in_pages = 64, + .page_total_size_in_bytes = 2*SZ_1K + 64, + .ecc_strength_in_bits = 4, + .ecc_size_in_bytes = 512, + .data_setup_in_ns = 30, + .data_hold_in_ns = 25, + .address_setup_in_ns = 10, + .gpmi_sample_delay_in_ns = 6, + .tREA_in_ns = -1, + .tRLOH_in_ns = -1, + .tRHOH_in_ns = -1, + "HY27UF082G2M, HY27UG082G2M, HY27UG082G1M", + }, + { + .end_of_table = false, + .manufacturer_code = 0x2c, + .device_code = 0xda, + .cell_technology = NAND_DEVICE_CELL_TECH_SLC, + .chip_size_in_bytes = 256LL*SZ_1M, + .block_size_in_pages = 64, + .page_total_size_in_bytes = 2*SZ_1K + 64, + .ecc_strength_in_bits = 4, + .ecc_size_in_bytes = 512, + .data_setup_in_ns = 20, + .data_hold_in_ns = 10, + .address_setup_in_ns = 10, + .gpmi_sample_delay_in_ns = 6, + .tREA_in_ns = -1, + .tRLOH_in_ns = -1, + .tRHOH_in_ns = -1, + "MT29F2G08", + }, + { + .end_of_table = false, + .manufacturer_code = 0xec, + .device_code = 0xda, + .cell_technology = NAND_DEVICE_CELL_TECH_SLC, + .chip_size_in_bytes = 256LL*SZ_1M, + .block_size_in_pages = 64, + .page_total_size_in_bytes = 2*SZ_1K + 64, + .ecc_strength_in_bits = 4, + .ecc_size_in_bytes = 512, + .data_setup_in_ns = 20, + .data_hold_in_ns = 10, + .address_setup_in_ns = 20, + .gpmi_sample_delay_in_ns = 6, + .tREA_in_ns = -1, + .tRLOH_in_ns = -1, + .tRHOH_in_ns = -1, + "K9F2G08U0M", + }, + { + .end_of_table = false, + .manufacturer_code = 0x98, + .device_code = 0xda, + .cell_technology = NAND_DEVICE_CELL_TECH_SLC, + .chip_size_in_bytes = 256LL*SZ_1M, + .block_size_in_pages = 64, + .page_total_size_in_bytes = 2*SZ_1K + 64, + .ecc_strength_in_bits = 4, + .ecc_size_in_bytes = 512, + .data_setup_in_ns = 20, + .data_hold_in_ns = 30, + .address_setup_in_ns = 0, + .gpmi_sample_delay_in_ns = 6, + .tREA_in_ns = -1, + .tRLOH_in_ns = -1, + .tRHOH_in_ns = -1, + "TC58NVG1S3", + }, + { + .end_of_table = false, + .manufacturer_code = 0x45, + .device_code = 0xda, + .cell_technology = NAND_DEVICE_CELL_TECH_SLC, + .chip_size_in_bytes = 256LL*SZ_1M, + .block_size_in_pages = 64, + .page_total_size_in_bytes = 2*SZ_1K + 64, + .ecc_strength_in_bits = 4, + .ecc_size_in_bytes = 512, + .data_setup_in_ns = 45, + .data_hold_in_ns = 32, + .address_setup_in_ns = 0, + .gpmi_sample_delay_in_ns = 6, + .tREA_in_ns = -1, + .tRLOH_in_ns = -1, + .tRHOH_in_ns = -1, + NULL, + }, + { + .end_of_table = false, + .manufacturer_code = 0x20, + .device_code = 0xdc, + .cell_technology = NAND_DEVICE_CELL_TECH_SLC, + .chip_size_in_bytes = 512LL*SZ_1M, + .block_size_in_pages = 64, + .page_total_size_in_bytes = 2*SZ_1K + 64, + .ecc_strength_in_bits = 4, + .ecc_size_in_bytes = 512, + .data_setup_in_ns = 45, + .data_hold_in_ns = 30, + .address_setup_in_ns = 10, + .gpmi_sample_delay_in_ns = 6, + .tREA_in_ns = -1, + .tRLOH_in_ns = -1, + .tRHOH_in_ns = -1, + NULL, + }, + { + .end_of_table = false, + .manufacturer_code = 0xad, + .device_code = 0xdc, + .cell_technology = NAND_DEVICE_CELL_TECH_SLC, + .chip_size_in_bytes = 512LL*SZ_1M, + .block_size_in_pages = 64, + .page_total_size_in_bytes = 2*SZ_1K + 64, + .ecc_strength_in_bits = 4, + .ecc_size_in_bytes = 512, + .data_setup_in_ns = 45, + .data_hold_in_ns = 30, + .address_setup_in_ns = 10, + .gpmi_sample_delay_in_ns = 10, + .tREA_in_ns = -1, + .tRLOH_in_ns = -1, + .tRHOH_in_ns = -1, + "HY27UH084G2M, HY27UG084G2M, HY27UH084G1M", + }, + { + .end_of_table = false, + .manufacturer_code = 0x2c, + .device_code = 0xdc, + .cell_technology = NAND_DEVICE_CELL_TECH_SLC, + .chip_size_in_bytes = 512LL*SZ_1M, + .block_size_in_pages = 64, + .page_total_size_in_bytes = 2*SZ_1K + 64, + .ecc_strength_in_bits = 4, + .ecc_size_in_bytes = 512, + .data_setup_in_ns = 20, + .data_hold_in_ns = 10, + .address_setup_in_ns = 10, + .gpmi_sample_delay_in_ns = 6, + .tREA_in_ns = -1, + .tRLOH_in_ns = -1, + .tRHOH_in_ns = -1, + "MT29F4G08", + }, + { + .end_of_table = false, + .manufacturer_code = 0xec, + .device_code = 0xdc, + .cell_technology = NAND_DEVICE_CELL_TECH_SLC, + .chip_size_in_bytes = 512LL*SZ_1M, + .block_size_in_pages = 64, + .page_total_size_in_bytes = 2*SZ_1K + 64, + .ecc_strength_in_bits = 4, + .ecc_size_in_bytes = 512, + .data_setup_in_ns = 25, + .data_hold_in_ns = 25, + .address_setup_in_ns = 20, + .gpmi_sample_delay_in_ns = 6, + .tREA_in_ns = -1, + .tRLOH_in_ns = -1, + .tRHOH_in_ns = -1, + NULL, + }, + { + .end_of_table = false, + .manufacturer_code = 0x98, + .device_code = 0xdc, + .cell_technology = NAND_DEVICE_CELL_TECH_SLC, + .chip_size_in_bytes = 512LL*SZ_1M, + .block_size_in_pages = 64, + .page_total_size_in_bytes = 2*SZ_1K + 64, + .ecc_strength_in_bits = 4, + .ecc_size_in_bytes = 512, + .data_setup_in_ns = 25, + .data_hold_in_ns = 25, + .address_setup_in_ns = 0, + .gpmi_sample_delay_in_ns = 6, + .tREA_in_ns = -1, + .tRLOH_in_ns = -1, + .tRHOH_in_ns = -1, + "TH58NVG2S3", + }, + { + .end_of_table = false, + .manufacturer_code = 0x45, + .device_code = 0xdc, + .cell_technology = NAND_DEVICE_CELL_TECH_SLC, + .chip_size_in_bytes = 512LL*SZ_1M, + .block_size_in_pages = 64, + .page_total_size_in_bytes = 2*SZ_1K + 64, + .ecc_strength_in_bits = 4, + .ecc_size_in_bytes = 512, + .data_setup_in_ns = 45, + .data_hold_in_ns = 32, + .address_setup_in_ns = 0, + .gpmi_sample_delay_in_ns = 6, + .tREA_in_ns = -1, + .tRLOH_in_ns = -1, + .tRHOH_in_ns = -1, + NULL, + }, + { + .end_of_table = false, + .manufacturer_code = 0xad, + .device_code = 0xd3, + .cell_technology = NAND_DEVICE_CELL_TECH_SLC, + .chip_size_in_bytes = 1LL*SZ_1G, + .block_size_in_pages = 64, + .page_total_size_in_bytes = 2*SZ_1K + 64, + .ecc_strength_in_bits = 4, + .ecc_size_in_bytes = 512, + .data_setup_in_ns = 30, + .data_hold_in_ns = 25, + .address_setup_in_ns = 20, + .gpmi_sample_delay_in_ns = 6, + .tREA_in_ns = -1, + .tRLOH_in_ns = -1, + .tRHOH_in_ns = -1, + "HY27UH088G2M", + }, + { + .end_of_table = false, + .manufacturer_code = 0x20, + .device_code = 0xd3, + .cell_technology = NAND_DEVICE_CELL_TECH_SLC, + .chip_size_in_bytes = 1LL*SZ_1G, + .block_size_in_pages = 64, + .page_total_size_in_bytes = 2*SZ_1K + 64, + .ecc_strength_in_bits = 4, + .ecc_size_in_bytes = 512, + .data_setup_in_ns = 45, + .data_hold_in_ns = 30, + .address_setup_in_ns = 10, + .gpmi_sample_delay_in_ns = 6, + .tREA_in_ns = -1, + .tRLOH_in_ns = -1, + .tRHOH_in_ns = -1, + "NAND08GW3BxANx", + }, + { + .end_of_table = false, + .manufacturer_code = 0x2c, + .device_code = 0xd3, + .cell_technology = NAND_DEVICE_CELL_TECH_SLC, + .chip_size_in_bytes = 1LL*SZ_1G, + .block_size_in_pages = 64, + .page_total_size_in_bytes = 2*SZ_1K + 64, + .ecc_strength_in_bits = 4, + .ecc_size_in_bytes = 512, + .data_setup_in_ns = 25, + .data_hold_in_ns = 15, + .address_setup_in_ns = 10, + .gpmi_sample_delay_in_ns = 6, + .tREA_in_ns = -1, + .tRLOH_in_ns = -1, + .tRHOH_in_ns = -1, + "MT29F8G08FABWG", + }, + { + .end_of_table = false, + .manufacturer_code = 0x98, + .device_code = 0xd3, + .cell_technology = NAND_DEVICE_CELL_TECH_SLC, + .chip_size_in_bytes = 1LL*SZ_1G, + .block_size_in_pages = 64, + .page_total_size_in_bytes = 2*SZ_1K + 64, + .ecc_strength_in_bits = 4, + .ecc_size_in_bytes = 512, + .data_setup_in_ns = 45, + .data_hold_in_ns = 32, + .address_setup_in_ns = 0, + .gpmi_sample_delay_in_ns = 6, + .tREA_in_ns = -1, + .tRLOH_in_ns = -1, + .tRHOH_in_ns = -1, + NULL, + }, + { + .end_of_table = false, + .manufacturer_code = 0x20, + .device_code = 0xd5, + .cell_technology = NAND_DEVICE_CELL_TECH_SLC, + .chip_size_in_bytes = 2LL*SZ_1G, + .block_size_in_pages = 64, + .page_total_size_in_bytes = 2*SZ_1K + 64, + .ecc_strength_in_bits = 4, + .ecc_size_in_bytes = 512, + .data_setup_in_ns = 45, + .data_hold_in_ns = 30, + .address_setup_in_ns = 10, + .gpmi_sample_delay_in_ns = 6, + .tREA_in_ns = -1, + .tRLOH_in_ns = -1, + .tRHOH_in_ns = -1, + NULL, + }, + { + .end_of_table = false, + .manufacturer_code = 0xad, + .device_code = 0xd5, + .cell_technology = NAND_DEVICE_CELL_TECH_SLC, + .chip_size_in_bytes = 2LL*SZ_1G, + .block_size_in_pages = 64, + .page_total_size_in_bytes = 2*SZ_1K + 64, + .ecc_strength_in_bits = 4, + .ecc_size_in_bytes = 512, + .data_setup_in_ns = 25, + .data_hold_in_ns = 30, + .address_setup_in_ns = 10, + .gpmi_sample_delay_in_ns = 6, + .tREA_in_ns = -1, + .tRLOH_in_ns = -1, + .tRHOH_in_ns = -1, + NULL, + }, + { + .end_of_table = false, + .manufacturer_code = 0x2c, + .device_code = 0xd5, + .cell_technology = NAND_DEVICE_CELL_TECH_SLC, + .chip_size_in_bytes = 2LL*SZ_1G, + .block_size_in_pages = 64, + .page_total_size_in_bytes = 2*SZ_1K + 64, + .ecc_strength_in_bits = 4, + .ecc_size_in_bytes = 512, + .data_setup_in_ns = 45, + .data_hold_in_ns = 32, + .address_setup_in_ns = 0, + .gpmi_sample_delay_in_ns = 6, + .tREA_in_ns = -1, + .tRLOH_in_ns = -1, + .tRHOH_in_ns = -1, + NULL, + }, + {true} +}; + +/* + * Large MLC + */ +static struct nand_device_info nand_device_info_table_large_mlc[] = +{ + { + .end_of_table = false, + .manufacturer_code = 0x98, + .device_code = 0xda, + .cell_technology = NAND_DEVICE_CELL_TECH_MLC, + .chip_size_in_bytes = 256LL*SZ_1M, + .block_size_in_pages = 128, + .page_total_size_in_bytes = 2*SZ_1K + 64, + .ecc_strength_in_bits = 4, + .ecc_size_in_bytes = 512, + .data_setup_in_ns = 20, + .data_hold_in_ns = 30, + .address_setup_in_ns = 0, + .gpmi_sample_delay_in_ns = 6, + .tREA_in_ns = -1, + .tRLOH_in_ns = -1, + .tRHOH_in_ns = -1, + "TC58NVG1D4BFT00", + }, + { + .end_of_table = false, + .manufacturer_code = 0x45, + .device_code = 0xda, + .cell_technology = NAND_DEVICE_CELL_TECH_MLC, + .chip_size_in_bytes = 256LL*SZ_1M, + .block_size_in_pages = 128, + .page_total_size_in_bytes = 2*SZ_1K + 64, + .ecc_strength_in_bits = 4, + .ecc_size_in_bytes = 512, + .data_setup_in_ns = 20, + .data_hold_in_ns = 30, + .address_setup_in_ns = 0, + .gpmi_sample_delay_in_ns = 6, + .tREA_in_ns = -1, + .tRLOH_in_ns = -1, + .tRHOH_in_ns = -1, + NULL, + }, + { + .end_of_table = false, + .manufacturer_code = 0x45, + .device_code = 0xdc, + .cell_technology = NAND_DEVICE_CELL_TECH_MLC, + .chip_size_in_bytes = 512LL*SZ_1M, + .block_size_in_pages = 128, + .page_total_size_in_bytes = 2*SZ_1K + 64, + .ecc_strength_in_bits = 4, + .ecc_size_in_bytes = 512, + .data_setup_in_ns = 20, + .data_hold_in_ns = 30, + .address_setup_in_ns = 0, + .gpmi_sample_delay_in_ns = 6, + .tREA_in_ns = -1, + .tRLOH_in_ns = -1, + .tRHOH_in_ns = -1, + NULL, + }, + { + .end_of_table = false, + .manufacturer_code = 0x98, + .device_code = 0xd3, + .cell_technology = NAND_DEVICE_CELL_TECH_MLC, + .chip_size_in_bytes = 1LL*SZ_1G, + .block_size_in_pages = 128, + .page_total_size_in_bytes = 2*SZ_1K + 64, + .ecc_strength_in_bits = 4, + .ecc_size_in_bytes = 512, + .data_setup_in_ns = 35, + .data_hold_in_ns = 30, + .address_setup_in_ns = 0, + .gpmi_sample_delay_in_ns = 6, + .tREA_in_ns = -1, + .tRLOH_in_ns = -1, + .tRHOH_in_ns = -1, + "TH58NVG3D4xFT00", + }, + { + .end_of_table = false, + .manufacturer_code = 0x45, + .device_code = 0xd3, + .cell_technology = NAND_DEVICE_CELL_TECH_MLC, + .chip_size_in_bytes = 1LL*SZ_1G, + .block_size_in_pages = 128, + .page_total_size_in_bytes = 2*SZ_1K + 64, + .ecc_strength_in_bits = 4, + .ecc_size_in_bytes = 512, + .data_setup_in_ns = 35, + .data_hold_in_ns = 20, + .address_setup_in_ns = 0, + .gpmi_sample_delay_in_ns = 6, + .tREA_in_ns = -1, + .tRLOH_in_ns = -1, + .tRHOH_in_ns = -1, + NULL, + }, + { + .end_of_table = false, + .manufacturer_code = 0x98, + .device_code = 0xd5, + .cell_technology = NAND_DEVICE_CELL_TECH_MLC, + .chip_size_in_bytes = 2LL*SZ_1G, + .block_size_in_pages = 128, + .page_total_size_in_bytes = 2*SZ_1K + 64, + .ecc_strength_in_bits = 4, + .ecc_size_in_bytes = 512, + .data_setup_in_ns = 35, + .data_hold_in_ns = 15, + .address_setup_in_ns = 0, + .gpmi_sample_delay_in_ns = 6, + .tREA_in_ns = -1, + .tRLOH_in_ns = -1, + .tRHOH_in_ns = -1, + "TH58NVG4D4xFT00", + }, + { + .end_of_table = false, + .manufacturer_code = 0x45, + .device_code = 0xd5, + .cell_technology = NAND_DEVICE_CELL_TECH_MLC, + .chip_size_in_bytes = 2LL*SZ_1G, + .block_size_in_pages = 128, + .page_total_size_in_bytes = 2*SZ_1K + 64, + .ecc_strength_in_bits = 4, + .ecc_size_in_bytes = 512, + .data_setup_in_ns = 35, + .data_hold_in_ns = 15, + .address_setup_in_ns = 0, + .gpmi_sample_delay_in_ns = 6, + .tREA_in_ns = -1, + .tRLOH_in_ns = -1, + .tRHOH_in_ns = -1, + NULL, + }, + { + .end_of_table = false, + .manufacturer_code = 0x98, + .device_code = 0xdc, + .cell_technology = NAND_DEVICE_CELL_TECH_MLC, + .chip_size_in_bytes = 512LL*SZ_1M, + .block_size_in_pages = 128, + .page_total_size_in_bytes = 2*SZ_1K + 64, + .ecc_strength_in_bits = 4, + .ecc_size_in_bytes = 512, + .data_setup_in_ns = 20, + .data_hold_in_ns = 30, + .address_setup_in_ns = 0, + .gpmi_sample_delay_in_ns = 6, + .tREA_in_ns = -1, + .tRLOH_in_ns = -1, + .tRHOH_in_ns = -1, + "TC58NVG2D4BFT00", + }, + { + .end_of_table = false, + .manufacturer_code = 0xec, + .device_code = 0xdc, + .cell_technology = NAND_DEVICE_CELL_TECH_MLC, + .chip_size_in_bytes = 512LL*SZ_1M, + .block_size_in_pages = 128, + .page_total_size_in_bytes = 2*SZ_1K + 64, + .ecc_strength_in_bits = 4, + .ecc_size_in_bytes = 512, + .data_setup_in_ns = 25, + .data_hold_in_ns = 15, + .address_setup_in_ns = 25, + .gpmi_sample_delay_in_ns = 6, + .tREA_in_ns = -1, + .tRLOH_in_ns = -1, + .tRHOH_in_ns = -1, + "K9G4G08U0M", + }, + { + .end_of_table = false, + .manufacturer_code = 0xad, + .device_code = 0xdc, + .cell_technology = NAND_DEVICE_CELL_TECH_MLC, + .chip_size_in_bytes = 512LL*SZ_1M, + .block_size_in_pages = 128, + .page_total_size_in_bytes = 2*SZ_1K + 64, + .ecc_strength_in_bits = 4, + .ecc_size_in_bytes = 512, + .data_setup_in_ns = 45, + .data_hold_in_ns = 25, + .address_setup_in_ns = 50, + .gpmi_sample_delay_in_ns = 6, + .tREA_in_ns = -1, + .tRLOH_in_ns = -1, + .tRHOH_in_ns = -1, + "HY27UT084G2M, HY27UU088G5M", + }, + { + .end_of_table = false, + .manufacturer_code = 0x20, + .device_code = 0xdc, + .cell_technology = NAND_DEVICE_CELL_TECH_MLC, + .chip_size_in_bytes = 512LL*SZ_1M, + .block_size_in_pages = 128, + .page_total_size_in_bytes = 2*SZ_1K + 64, + .ecc_strength_in_bits = 4, + .ecc_size_in_bytes = 512, + .data_setup_in_ns = 40, + .data_hold_in_ns = 20, + .address_setup_in_ns = 30, + .gpmi_sample_delay_in_ns = 6, + .tREA_in_ns = -1, + .tRLOH_in_ns = -1, + .tRHOH_in_ns = -1, + "NAND04GW3C2AN1E", + }, + { + .end_of_table = false, + .manufacturer_code = 0xec, + .device_code = 0xd3, + .cell_technology = NAND_DEVICE_CELL_TECH_MLC, + .chip_size_in_bytes = 1LL*SZ_1G, + .block_size_in_pages = 128, + .page_total_size_in_bytes = 2*SZ_1K + 64, + .ecc_strength_in_bits = 4, + .ecc_size_in_bytes = 512, + .data_setup_in_ns = 20, + .data_hold_in_ns = 15, + .address_setup_in_ns = 20, + .gpmi_sample_delay_in_ns = 6, + .tREA_in_ns = -1, + .tRLOH_in_ns = -1, + .tRHOH_in_ns = -1, + "K9G8G08U0M, K9HAG08U1M", + }, + { + .end_of_table = false, + .manufacturer_code = 0xad, + .device_code = 0xd3, + .cell_technology = NAND_DEVICE_CELL_TECH_MLC, + .chip_size_in_bytes = 1LL*SZ_1G, + .block_size_in_pages = 128, + .page_total_size_in_bytes = 2*SZ_1K + 64, + .ecc_strength_in_bits = 4, + .ecc_size_in_bytes = 512, + .data_setup_in_ns = 60, + .data_hold_in_ns = 30, + .address_setup_in_ns = 50, + .gpmi_sample_delay_in_ns = 6, + .tREA_in_ns = -1, + .tRLOH_in_ns = -1, + .tRHOH_in_ns = -1, + "HY27UV08AG5M", + }, + { + .end_of_table = false, + .manufacturer_code = 0x2c, + .device_code = 0xd3, + .cell_technology = NAND_DEVICE_CELL_TECH_MLC, + .chip_size_in_bytes = 1LL*SZ_1G, + .block_size_in_pages = 128, + .page_total_size_in_bytes = 2*SZ_1K + 64, + .ecc_strength_in_bits = 4, + .ecc_size_in_bytes = 512, + .data_setup_in_ns = 15, + .data_hold_in_ns = 15, + .address_setup_in_ns = 15, + .gpmi_sample_delay_in_ns = 6, + .tREA_in_ns = -1, + .tRLOH_in_ns = -1, + .tRHOH_in_ns = -1, + "Intel JS29F08G08AAMiB1 and Micron MT29F8G08MAA; " + "Intel JS29F08G08CAMiB1 and Micron MT29F16G08QAA", + }, + { + .end_of_table = false, + .manufacturer_code = 0xec, + .device_code = 0xd5, + .cell_technology = NAND_DEVICE_CELL_TECH_MLC, + .chip_size_in_bytes = 2LL*SZ_1G, + .block_size_in_pages = 128, + .page_total_size_in_bytes = 2*SZ_1K + 64, + .ecc_strength_in_bits = 4, + .ecc_size_in_bytes = 512, + .data_setup_in_ns = 20, + .data_hold_in_ns = 15, + .address_setup_in_ns = 20, + .gpmi_sample_delay_in_ns = 6, + .tREA_in_ns = -1, + .tRLOH_in_ns = -1, + .tRHOH_in_ns = -1, + "K9LAG08U0M K9HBG08U1M K9GAG08U0M", + }, + { + .end_of_table = false, + .manufacturer_code = 0x2c, + .device_code = 0xd5, + .cell_technology = NAND_DEVICE_CELL_TECH_MLC, + .chip_size_in_bytes = 2LL*SZ_1G, + .block_size_in_pages = 128, + .page_total_size_in_bytes = 2*SZ_1K + 64, + .ecc_strength_in_bits = 4, + .ecc_size_in_bytes = 512, + .data_setup_in_ns = 15, + .data_hold_in_ns = 10, + .address_setup_in_ns = 15, + .gpmi_sample_delay_in_ns = 6, + .tREA_in_ns = -1, + .tRLOH_in_ns = -1, + .tRHOH_in_ns = -1, + "Intel JS29F32G08FAMiB1 and Micron MT29F32G08TAA", + }, + { + .end_of_table = false, + .manufacturer_code = 0x2c, + .device_code = 0xdc, + .cell_technology = NAND_DEVICE_CELL_TECH_MLC, + .chip_size_in_bytes = 512LL*SZ_1M, + .block_size_in_pages = 128, + .page_total_size_in_bytes = 2*SZ_1K + 64, + .ecc_strength_in_bits = 4, + .ecc_size_in_bytes = 512, + .data_setup_in_ns = 20, + .data_hold_in_ns = 20, + .address_setup_in_ns = 20, + .gpmi_sample_delay_in_ns = 6, + .tREA_in_ns = -1, + .tRLOH_in_ns = -1, + .tRHOH_in_ns = -1, + "MT29F4G08", + }, + { + .end_of_table = false, + .manufacturer_code = 0x89, + .device_code = 0xd3, + .cell_technology = NAND_DEVICE_CELL_TECH_MLC, + .chip_size_in_bytes = 1LL*SZ_1G, + .block_size_in_pages = 128, + .page_total_size_in_bytes = 2*SZ_1K + 64, + .ecc_strength_in_bits = 4, + .ecc_size_in_bytes = 512, + .data_setup_in_ns = 15, + .data_hold_in_ns = 10, + .address_setup_in_ns = 15, + .gpmi_sample_delay_in_ns = 6, + .tREA_in_ns = -1, + .tRLOH_in_ns = -1, + .tRHOH_in_ns = -1, + "JS29F08G08AAMiB2, JS29F08G08CAMiB2", + }, + { + .end_of_table = false, + .manufacturer_code = 0x89, + .device_code = 0xd5, + .cell_technology = NAND_DEVICE_CELL_TECH_MLC, + .chip_size_in_bytes = 2LL*SZ_1G, + .block_size_in_pages = 128, + .page_total_size_in_bytes = 2*SZ_1K + 64, + .ecc_strength_in_bits = 4, + .ecc_size_in_bytes = 512, + .data_setup_in_ns = 15, + .data_hold_in_ns = 10, + .address_setup_in_ns = 15, + .gpmi_sample_delay_in_ns = 6, + .tREA_in_ns = -1, + .tRLOH_in_ns = -1, + .tRHOH_in_ns = -1, + "JS29F32G08FAMiB2", + }, + { + .end_of_table = false, + .manufacturer_code = 0xad, + .device_code = 0xd5, + .cell_technology = NAND_DEVICE_CELL_TECH_MLC, + .chip_size_in_bytes = 2LL*SZ_1G, + .block_size_in_pages = 128, + .page_total_size_in_bytes = 2*SZ_1K + 64, + .ecc_strength_in_bits = 4, + .ecc_size_in_bytes = 512, + .data_setup_in_ns = 15, + .data_hold_in_ns = 10, + .address_setup_in_ns = 20, + .gpmi_sample_delay_in_ns = 6, + .tREA_in_ns = -1, + .tRLOH_in_ns = -1, + .tRHOH_in_ns = -1, + "HY27UW08CGFM", + }, + {true} +}; + +/* + * Type 7 + */ +static struct nand_device_info nand_device_info_table_type_7[] = +{ + { + .end_of_table = false, + .manufacturer_code = 0x2c, + .device_code = 0xd3, + .cell_technology = NAND_DEVICE_CELL_TECH_SLC, + .chip_size_in_bytes = 1LL*SZ_1G, + .block_size_in_pages = 64, + .page_total_size_in_bytes = 2*SZ_1K + 64, + .ecc_strength_in_bits = 4, + .ecc_size_in_bytes = 512, + .data_setup_in_ns = 25, + .data_hold_in_ns = 15, + .address_setup_in_ns = 10, + .gpmi_sample_delay_in_ns = 6, + .tREA_in_ns = -1, + .tRLOH_in_ns = -1, + .tRHOH_in_ns = -1, + "MT29F8G08FABWG", + }, + { + .end_of_table = false, + .manufacturer_code = 0x2c, + .device_code = 0xdc, + .cell_technology = NAND_DEVICE_CELL_TECH_SLC, + .chip_size_in_bytes = 512LL*SZ_1M, + .block_size_in_pages = 64, + .page_total_size_in_bytes = 2*SZ_1K + 64, + .ecc_strength_in_bits = 4, + .ecc_size_in_bytes = 512, + .data_setup_in_ns = 20, + .data_hold_in_ns = 10, + .address_setup_in_ns = 10, + .gpmi_sample_delay_in_ns = 6, + .tREA_in_ns = -1, + .tRLOH_in_ns = -1, + .tRHOH_in_ns = -1, + "MT29F4G08AAA", + }, + { + .end_of_table = false, + .manufacturer_code = 0xec, + .device_code = 0xdc, + .cell_technology = NAND_DEVICE_CELL_TECH_SLC, + .chip_size_in_bytes = 512LL*SZ_1M, + .block_size_in_pages = 64, + .page_total_size_in_bytes = 2*SZ_1K + 64, + .ecc_strength_in_bits = 4, + .ecc_size_in_bytes = 512, + .data_setup_in_ns = 15, + .data_hold_in_ns = 12, + .address_setup_in_ns = 25, + .gpmi_sample_delay_in_ns = 6, + .tREA_in_ns = -1, + .tRLOH_in_ns = -1, + .tRHOH_in_ns = -1, + "K9F4G08", + }, + { + .end_of_table = false, + .manufacturer_code = 0xec, + .device_code = 0xd3, + .cell_technology = NAND_DEVICE_CELL_TECH_SLC, + .chip_size_in_bytes = 1LL*SZ_1G, + .block_size_in_pages = 64, + .page_total_size_in_bytes = 2*SZ_1K + 64, + .ecc_strength_in_bits = 4, + .ecc_size_in_bytes = 512, + .data_setup_in_ns = 25, + .data_hold_in_ns = 15, + .address_setup_in_ns = 35, + .gpmi_sample_delay_in_ns = 6, + .tREA_in_ns = -1, + .tRLOH_in_ns = -1, + .tRHOH_in_ns = -1, + "K9K8G08UXM, K9NBG08U5A, K9WAG08U1A", + }, + { + .end_of_table = false, + .manufacturer_code = 0xec, + .device_code = 0xd5, + .cell_technology = NAND_DEVICE_CELL_TECH_SLC, + .chip_size_in_bytes = 2LL*SZ_1G, + .block_size_in_pages = 64, + .page_total_size_in_bytes = 2*SZ_1K + 64, + .ecc_strength_in_bits = 4, + .ecc_size_in_bytes = 512, + .data_setup_in_ns = 15, + .data_hold_in_ns = 12, + .address_setup_in_ns = 25, + .gpmi_sample_delay_in_ns = 6, + .tREA_in_ns = -1, + .tRLOH_in_ns = -1, + .tRHOH_in_ns = -1, + "K9WAG08UXM", + }, + { + .end_of_table = false, + .manufacturer_code = 0xec, + .device_code = 0xda, + .cell_technology = NAND_DEVICE_CELL_TECH_SLC, + .chip_size_in_bytes = 256LL*SZ_1M, + .block_size_in_pages = 64, + .page_total_size_in_bytes = 2*SZ_1K + 64, + .ecc_strength_in_bits = 4, + .ecc_size_in_bytes = 512, + .data_setup_in_ns = 20, + .data_hold_in_ns = 10, + .address_setup_in_ns = 20, + .gpmi_sample_delay_in_ns = 6, + .tREA_in_ns = -1, + .tRLOH_in_ns = -1, + .tRHOH_in_ns = -1, + "K9F2G08U0A", + }, + { + .end_of_table = false, + .manufacturer_code = 0xec, + .device_code = 0xf1, + .cell_technology = NAND_DEVICE_CELL_TECH_SLC, + .chip_size_in_bytes = 128LL*SZ_1M, + .block_size_in_pages = 64, + .page_total_size_in_bytes = 2*SZ_1K + 64, + .ecc_strength_in_bits = 4, + .ecc_size_in_bytes = 512, + .data_setup_in_ns = 15, + .data_hold_in_ns = 12, + .address_setup_in_ns = 20, + .gpmi_sample_delay_in_ns = 6, + .tREA_in_ns = -1, + .tRLOH_in_ns = -1, + .tRHOH_in_ns = -1, + "K9F1F08", + }, + {true} +}; + +/* + * Type 8 + */ +static struct nand_device_info nand_device_info_table_type_8[] = +{ + { + .end_of_table = false, + .manufacturer_code = 0xec, + .device_code = 0xd5, + .cell_technology = NAND_DEVICE_CELL_TECH_MLC, + .chip_size_in_bytes = 2LL*SZ_1G, + .block_size_in_pages = 128, + .page_total_size_in_bytes = 4*SZ_1K + 128, + .ecc_strength_in_bits = 4, + .ecc_size_in_bytes = 512, + .data_setup_in_ns = 15, + .data_hold_in_ns = 10, + .address_setup_in_ns = 20, + .gpmi_sample_delay_in_ns = 6, + .tREA_in_ns = -1, + .tRLOH_in_ns = -1, + .tRHOH_in_ns = -1, + "K9GAG08U0M", + }, + { + .end_of_table = false, + .manufacturer_code = 0xec, + .device_code = 0xd7, + .cell_technology = NAND_DEVICE_CELL_TECH_MLC, + .chip_size_in_bytes = 4LL*SZ_1G, + .block_size_in_pages = 128, + .page_total_size_in_bytes = 4*SZ_1K + 128, + .ecc_strength_in_bits = 4, + .ecc_size_in_bytes = 512, + .data_setup_in_ns = 15, + .data_hold_in_ns = 15, + .address_setup_in_ns = 25, + .gpmi_sample_delay_in_ns = 6, + .tREA_in_ns = -1, + .tRLOH_in_ns = -1, + .tRHOH_in_ns = -1, + "K9LBG08U0M (32Gb), K9HCG08U1M (64Gb), K9MDG08U5M (128Gb)", + }, + { + .end_of_table = false, + .manufacturer_code = 0xad, + .device_code = 0xd5, + .cell_technology = NAND_DEVICE_CELL_TECH_MLC, + .chip_size_in_bytes = 2LL*SZ_1G, + .block_size_in_pages = 128, + .page_total_size_in_bytes = 4*SZ_1K + 128, + .ecc_strength_in_bits = 4, + .ecc_size_in_bytes = 512, + .data_setup_in_ns = 20, + .data_hold_in_ns = 20, + .address_setup_in_ns = 20, + .gpmi_sample_delay_in_ns = 0, + .tREA_in_ns = -1, + .tRLOH_in_ns = -1, + .tRHOH_in_ns = -1, + "H27UAG, H27UBG", + }, + { + .end_of_table = false, + .manufacturer_code = 0xad, + .device_code = 0xd7, + .cell_technology = NAND_DEVICE_CELL_TECH_MLC, + .chip_size_in_bytes = 4LL*SZ_1G, + .block_size_in_pages = 128, + .page_total_size_in_bytes = 4*SZ_1K + 128, + .ecc_strength_in_bits = 4, + .ecc_size_in_bytes = 512, + .data_setup_in_ns = 23, + .data_hold_in_ns = 20, + .address_setup_in_ns = 25, + .gpmi_sample_delay_in_ns = 0, + .tREA_in_ns = -1, + .tRLOH_in_ns = -1, + .tRHOH_in_ns = -1, + "H27UCG", + }, + {true} +}; + +/* + * Type 9 + */ +static struct nand_device_info nand_device_info_table_type_9[] = +{ + { + .end_of_table = false, + .manufacturer_code = 0x98, + .device_code = 0xd3, + .cell_technology = NAND_DEVICE_CELL_TECH_MLC, + .chip_size_in_bytes = 1LL*SZ_1G, + .block_size_in_pages = 128, + .page_total_size_in_bytes = 4*SZ_1K + 218, + .ecc_strength_in_bits = 8, + .ecc_size_in_bytes = 512, + .data_setup_in_ns = 15, + .data_hold_in_ns = 15, + .address_setup_in_ns = 10, + .gpmi_sample_delay_in_ns = 6, + .tREA_in_ns = -1, + .tRLOH_in_ns = -1, + .tRHOH_in_ns = -1, + "TC58NVG3D1DTG00", + }, + { + .end_of_table = false, + .manufacturer_code = 0x98, + .device_code = 0xd5, + .cell_technology = NAND_DEVICE_CELL_TECH_MLC, + .chip_size_in_bytes = 2LL*SZ_1G, + .block_size_in_pages = 128, + .page_total_size_in_bytes = 4*SZ_1K + 218, + .ecc_strength_in_bits = 8, + .ecc_size_in_bytes = 512, + .data_setup_in_ns = 15, + .data_hold_in_ns = 15, + .address_setup_in_ns = 10, + .gpmi_sample_delay_in_ns = 6, + .tREA_in_ns = -1, + .tRLOH_in_ns = -1, + .tRHOH_in_ns = -1, + "TC58NVG4D1DTG00", + }, + { + .end_of_table = false, + .manufacturer_code = 0x98, + .device_code = 0xd7, + .cell_technology = NAND_DEVICE_CELL_TECH_MLC, + .chip_size_in_bytes = 4LL*SZ_1G, + .block_size_in_pages = 128, + .page_total_size_in_bytes = 4*SZ_1K + 218, + .ecc_strength_in_bits = 8, + .ecc_size_in_bytes = 512, + .data_setup_in_ns = 15, + .data_hold_in_ns = 15, + .address_setup_in_ns = 10, + .gpmi_sample_delay_in_ns = 6, + .tREA_in_ns = -1, + .tRLOH_in_ns = -1, + .tRHOH_in_ns = -1, + "TH58NVG6D1DTG20", + }, + { + .end_of_table = false, + .manufacturer_code = 0x89, + .device_code = 0xd5, + .cell_technology = NAND_DEVICE_CELL_TECH_MLC, + .chip_size_in_bytes = 2LL*SZ_1G, + .block_size_in_pages = 128, + .page_total_size_in_bytes = 4*SZ_1K + 218, + .ecc_strength_in_bits = 8, + .ecc_size_in_bytes = 512, + .data_setup_in_ns = 10, + .data_hold_in_ns = 10, + .address_setup_in_ns = 15, + .gpmi_sample_delay_in_ns = 6, + .tREA_in_ns = -1, + .tRLOH_in_ns = -1, + .tRHOH_in_ns = -1, + "JS29F16G08AAMC1, JS29F32G08CAMC1", + }, + { + .end_of_table = false, + .manufacturer_code = 0x2c, + .device_code = 0xd5, + .cell_technology = NAND_DEVICE_CELL_TECH_MLC, + .chip_size_in_bytes = 2LL*SZ_1G, + .block_size_in_pages = 128, + .page_total_size_in_bytes = 4*SZ_1K + 218, + .ecc_strength_in_bits = 8, + .ecc_size_in_bytes = 512, + .data_setup_in_ns = 15, + .data_hold_in_ns = 10, + .address_setup_in_ns = 15, + .gpmi_sample_delay_in_ns = 6, + .tREA_in_ns = -1, + .tRLOH_in_ns = -1, + .tRHOH_in_ns = -1, + "MT29F16G08MAA, MT29F32G08QAA", + }, + { + .end_of_table = false, + .manufacturer_code = 0x2c, + .device_code = 0xd7, + .cell_technology = NAND_DEVICE_CELL_TECH_MLC, + .chip_size_in_bytes = 4LL*SZ_1G, + .block_size_in_pages = 128, + .page_total_size_in_bytes = 4*SZ_1K + 218, + .ecc_strength_in_bits = 8, + .ecc_size_in_bytes = 512, + .data_setup_in_ns = 15, + .data_hold_in_ns = 10, + .address_setup_in_ns = 15, + .gpmi_sample_delay_in_ns = 6, + .tREA_in_ns = -1, + .tRLOH_in_ns = -1, + .tRHOH_in_ns = -1, + "MT29F64G08TAA (32Gb), MT29F32G08CBAAA (32Gb) MT29F64G08CFAAA (64Gb)", + }, + { + .end_of_table = false, + .manufacturer_code = 0x2c, + .device_code = 0xd9, + .cell_technology = NAND_DEVICE_CELL_TECH_MLC, + .chip_size_in_bytes = 8LL*SZ_1G, + .block_size_in_pages = 128, + .page_total_size_in_bytes = 4*SZ_1K + 218, + .ecc_strength_in_bits = 8, + .ecc_size_in_bytes = 512, + .data_setup_in_ns = 10, + .data_hold_in_ns = 10, + .address_setup_in_ns = 15, + .gpmi_sample_delay_in_ns = 6, + .tREA_in_ns = -1, + .tRLOH_in_ns = -1, + .tRHOH_in_ns = -1, + "MT29F128G08CJAAA", + }, + { + .end_of_table = false, + .manufacturer_code = 0x89, + .device_code = 0xd7, + .cell_technology = NAND_DEVICE_CELL_TECH_MLC, + .chip_size_in_bytes = 4LL*SZ_1G, + .block_size_in_pages = 128, + .page_total_size_in_bytes = 4*SZ_1K + 218, + .ecc_strength_in_bits = 8, + .ecc_size_in_bytes = 512, + .data_setup_in_ns = 10, + .data_hold_in_ns = 10, + .address_setup_in_ns = 15, + .gpmi_sample_delay_in_ns = 6, + .tREA_in_ns = -1, + .tRLOH_in_ns = -1, + .tRHOH_in_ns = -1, + "JSF64G08FAMC1", + }, + { + .end_of_table = false, + .manufacturer_code = 0xec, + .device_code = 0xd7, + .cell_technology = NAND_DEVICE_CELL_TECH_MLC, + .chip_size_in_bytes = 4LL*SZ_1G, + .block_size_in_pages = 128, + .page_total_size_in_bytes = 4*SZ_1K + 218, + .ecc_strength_in_bits = 8, + .ecc_size_in_bytes = 512, + .data_setup_in_ns = 20, + .data_hold_in_ns = 10, + .address_setup_in_ns = 25, + .gpmi_sample_delay_in_ns = 6, + .tREA_in_ns = -1, + .tRLOH_in_ns = -1, + .tRHOH_in_ns = -1, + "K9LBG08U0D", + }, + { + .end_of_table = false, + .manufacturer_code = 0xec, + .device_code = 0xd5, + .cell_technology = NAND_DEVICE_CELL_TECH_MLC, + .chip_size_in_bytes = 2LL*SZ_1G, + .block_size_in_pages = 128, + .page_total_size_in_bytes = 4*SZ_1K + 218, + .ecc_strength_in_bits = 8, + .ecc_size_in_bytes = 512, + .data_setup_in_ns = 20, + .data_hold_in_ns = 10, + .address_setup_in_ns = 20, + .gpmi_sample_delay_in_ns = 6, + .tREA_in_ns = -1, + .tRLOH_in_ns = -1, + .tRHOH_in_ns = -1, + "K9GAG08U0D, K9LBG08U1D, K9HCG08U5D", + }, + {true} +}; + +/* + * Type 10 + */ +static struct nand_device_info nand_device_info_table_type_10[] = +{ + { + .end_of_table = false, + .manufacturer_code = 0xec, + .device_code = 0xd3, + .cell_technology = NAND_DEVICE_CELL_TECH_SLC, + .chip_size_in_bytes = 1LL*SZ_1G, + .block_size_in_pages = 64, + .page_total_size_in_bytes = 4*SZ_1K + 128, + .ecc_strength_in_bits = 4, + .ecc_size_in_bytes = 512, + .data_setup_in_ns = 15, + .data_hold_in_ns = 10, + .address_setup_in_ns = 20, + .gpmi_sample_delay_in_ns = 6, + .tREA_in_ns = -1, + .tRLOH_in_ns = -1, + .tRHOH_in_ns = -1, + NULL, + }, + { + .end_of_table = false, + .manufacturer_code = 0xec, + .device_code = 0xd5, + .cell_technology = NAND_DEVICE_CELL_TECH_SLC, + .chip_size_in_bytes = 2LL*SZ_1G, + .block_size_in_pages = 64, + .page_total_size_in_bytes = 4*SZ_1K + 128, + .ecc_strength_in_bits = 4, + .ecc_size_in_bytes = 512, + .data_setup_in_ns = 25, + .data_hold_in_ns = 15, + .address_setup_in_ns = 30, + .gpmi_sample_delay_in_ns = 6, + .tREA_in_ns = -1, + .tRLOH_in_ns = -1, + .tRHOH_in_ns = -1, + "K9NCG08U5M", + }, + { + .end_of_table = false, + .manufacturer_code = 0xec, + .device_code = 0xd7, + .cell_technology = NAND_DEVICE_CELL_TECH_SLC, + .chip_size_in_bytes = 4LL*SZ_1G, + .block_size_in_pages = 64, + .page_total_size_in_bytes = 4*SZ_1K + 128, + .ecc_strength_in_bits = 4, + .ecc_size_in_bytes = 512, + .data_setup_in_ns = 15, + .data_hold_in_ns = 15, + .address_setup_in_ns = 25, + .gpmi_sample_delay_in_ns = 6, + .tREA_in_ns = -1, + .tRLOH_in_ns = -1, + .tRHOH_in_ns = -1, + NULL, + }, + {true} +}; + +/* + * Type 11 + */ +static struct nand_device_info nand_device_info_table_type_11[] = +{ + { + .end_of_table = false, + .manufacturer_code = 0x98, + .device_code = 0xd7, + .cell_technology = NAND_DEVICE_CELL_TECH_MLC, + .chip_size_in_bytes = 4LL*SZ_1G, + .block_size_in_pages = 128, + .page_total_size_in_bytes = 8*SZ_1K + 376, + .ecc_strength_in_bits = 14, + .ecc_size_in_bytes = 512, + .data_setup_in_ns = 15, + .data_hold_in_ns = 10, + .address_setup_in_ns = 8, + .gpmi_sample_delay_in_ns = 6, + .tREA_in_ns = 20, + .tRLOH_in_ns = 5, + .tRHOH_in_ns = 25, + "TC58NVG5D2ELAM8 (4GB), TH58NVG6D2ELAM8 (8GB)", + }, + { + .end_of_table = false, + .manufacturer_code = 0x98, + .device_code = 0xde, + .cell_technology = NAND_DEVICE_CELL_TECH_MLC, + .chip_size_in_bytes = 8LL*SZ_1G, + .block_size_in_pages = 128, + .page_total_size_in_bytes = 8*SZ_1K + 376, + .ecc_strength_in_bits = 14, + .ecc_size_in_bytes = 512, + .data_setup_in_ns = 15, + .data_hold_in_ns = 10, + .address_setup_in_ns = 8, + .gpmi_sample_delay_in_ns = 6, + .tREA_in_ns = 20, + .tRLOH_in_ns = 5, + .tRHOH_in_ns = 25, + "TH58NVG7D2ELAM8", + }, + {true} +}; + +/* + * Type 15 + */ +static struct nand_device_info nand_device_info_table_type_15[] = +{ + { + .end_of_table = false, + .manufacturer_code = 0xec, + .device_code = 0xd7, + .cell_technology = NAND_DEVICE_CELL_TECH_MLC, + .chip_size_in_bytes = 4LL*SZ_1G, + .block_size_in_pages = 128, + .page_total_size_in_bytes = 8*SZ_1K + 436, + .ecc_strength_in_bits = 16, + .ecc_size_in_bytes = 512, + .data_setup_in_ns = 20, + .data_hold_in_ns = 10, + .address_setup_in_ns = 25, + .gpmi_sample_delay_in_ns = 6, + .tREA_in_ns = 25, + .tRLOH_in_ns = 5, + .tRHOH_in_ns = 15, + "K9GBG08U0M (4GB, 1CE); K9LCG08U1M (8GB, 2CE); K9HDG08U5M (16GB, 4CE)", + }, + {true} +}; + +/* + * BCH ECC12 + */ +static struct nand_device_info nand_device_info_table_bch_ecc12[] = +{ + { + .end_of_table = false, + .manufacturer_code = 0xad, + .device_code = 0xd7, + .cell_technology = NAND_DEVICE_CELL_TECH_MLC, + .chip_size_in_bytes = 4LL*SZ_1G, + .block_size_in_pages = 128, + .page_total_size_in_bytes = 4*SZ_1K + 224, + .ecc_strength_in_bits = 12, + .ecc_size_in_bytes = 512, + .data_setup_in_ns = 15, + .data_hold_in_ns = 10, + .address_setup_in_ns = 20, + .gpmi_sample_delay_in_ns = 6, + .tREA_in_ns = 20, + .tRLOH_in_ns = 5, + .tRHOH_in_ns = 15, + "H27UBG8T2M (4GB, 1CE), H27UCG8UDM (8GB, 2CE), H27UDG8VEM (16GB, 4CE)", + }, + { + .end_of_table = false, + .manufacturer_code = 0xad, + .device_code = 0xde, + .cell_technology = NAND_DEVICE_CELL_TECH_MLC, + .chip_size_in_bytes = 8LL*SZ_1G, + .block_size_in_pages = 128, + .page_total_size_in_bytes = 4*SZ_1K + 224, + .ecc_strength_in_bits = 12, + .ecc_size_in_bytes = 512, + .data_setup_in_ns = 15, + .data_hold_in_ns = 10, + .address_setup_in_ns = 20, + .gpmi_sample_delay_in_ns = 6, + .tREA_in_ns = 20, + .tRLOH_in_ns = 5, + .tRHOH_in_ns = 15, + "H27UEG8YEM (32GB, 4CE)", + }, + { + .end_of_table = false, + .manufacturer_code = 0x2c, + .device_code = 0xd7, + .cell_technology = NAND_DEVICE_CELL_TECH_MLC, + .chip_size_in_bytes = 4LL*SZ_1G, + .block_size_in_pages = 128, + .page_total_size_in_bytes = 4*SZ_1K + 218, + .ecc_strength_in_bits = 12, + .ecc_size_in_bytes = 512, + .data_setup_in_ns = 10, + .data_hold_in_ns = 10, + .address_setup_in_ns = 15, + .gpmi_sample_delay_in_ns = 6, + .tREA_in_ns = 16, + .tRLOH_in_ns = 5, + .tRHOH_in_ns = 15, + "MT29F32G08CBAAA (4GB, 1CE), MT29F64G08CFAAA (8GB, 2CE)", + }, + { + .end_of_table = false, + .manufacturer_code = 0x2c, + .device_code = 0xd9, + .cell_technology = NAND_DEVICE_CELL_TECH_MLC, + .chip_size_in_bytes = 8LL*SZ_1G, + .block_size_in_pages = 128, + .page_total_size_in_bytes = 4*SZ_1K + 218, + .ecc_strength_in_bits = 12, + .ecc_size_in_bytes = 512, + .data_setup_in_ns = 10, + .data_hold_in_ns = 10, + .address_setup_in_ns = 15, + .gpmi_sample_delay_in_ns = 6, + .tREA_in_ns = 16, + .tRLOH_in_ns = 5, + .tRHOH_in_ns = 15, + "MT29F128G08CJAAA (16GB, 2CE)", + }, + { + .end_of_table = false, + .manufacturer_code = 0x2c, + .device_code = 0x48, + .cell_technology = NAND_DEVICE_CELL_TECH_MLC, + .chip_size_in_bytes = 2LL*SZ_1G, + .block_size_in_pages = 256, + .page_total_size_in_bytes = 4*SZ_1K + 224, + .ecc_strength_in_bits = 12, + .ecc_size_in_bytes = 512, + .data_setup_in_ns = 15, + .data_hold_in_ns = 10, + .address_setup_in_ns = 20, + .gpmi_sample_delay_in_ns = 6, + .tREA_in_ns = 20, + .tRLOH_in_ns = 5, + .tRHOH_in_ns = 15, + "MT29F16G08CBABA (2GB, 1CE)", + }, + { + .end_of_table = false, + .manufacturer_code = 0x2c, + .device_code = 0x68, + .cell_technology = NAND_DEVICE_CELL_TECH_MLC, + .chip_size_in_bytes = 4LL*SZ_1G, + .block_size_in_pages = 256, + .page_total_size_in_bytes = 4*SZ_1K + 224, + .ecc_strength_in_bits = 12, + .ecc_size_in_bytes = 512, + .data_setup_in_ns = 15, + .data_hold_in_ns = 10, + .address_setup_in_ns = 20, + .gpmi_sample_delay_in_ns = 6, + .tREA_in_ns = 20, + .tRLOH_in_ns = 5, + .tRHOH_in_ns = 15, + "MT29F32G08CBABA (4GB, 1CE); " + "MT29F64G08CEABA (8GB, 2CE); " + "MT29F64G08CFABA (8GB, 2CE)", + }, + { + .end_of_table = false, + .manufacturer_code = 0x2c, + .device_code = 0x88, + .cell_technology = NAND_DEVICE_CELL_TECH_MLC, + .chip_size_in_bytes = 8LL*SZ_1G, + .block_size_in_pages = 256, + .page_total_size_in_bytes = 4*SZ_1K + 224, + .ecc_strength_in_bits = 12, + .ecc_size_in_bytes = 512, + .data_setup_in_ns = 15, + .data_hold_in_ns = 10, + .address_setup_in_ns = 20, + .gpmi_sample_delay_in_ns = 6, + .tREA_in_ns = 20, + .tRLOH_in_ns = 5, + .tRHOH_in_ns = 15, + "MT29F128G08CJABA (16GB, 2CE); " + "MT29F128G08CKABA (16GB, 2CE); " + "MT29F256G08CUABA (32GB, 4CE)", + }, + {true} +}; + +/* + * The following macros make it convenient to extract information from an ID + * byte array. All these macros begin with the prefix "ID_". + * + * Macros of the form: + * + * ID_GET_[_[_]] + * + * extract the given field from an ID byte array. Macros of the form: + * + * ID_[_[_]]_ + * + * contain the value for the given field that has the given meaning. + * + * If the appears, it means this macro represents a view of this + * field that is specific to the given manufacturer. + * + * If the appears, it means this macro represents a view of this + * field that the given manufacturer applies only under specific conditions. + * + * Here is a simple example: + * + * ID_PAGE_SIZE_CODE_2K + * + * This macro has the value of the "Page Size" field that indicates the page + * size is 2K. + * + * A more complicated example: + * + * ID_SAMSUNG_6_BYTE_PAGE_SIZE_CODE_8K (0x2) + * + * This macro has the value of the "Page Size" field for Samsung parts that + * indicates the page size is 8K. However, this interpretation is only correct + * for devices that return 6 ID bytes. + */ + +/* Byte 1 ------------------------------------------------------------------- */ + +#define ID_GET_BYTE_1(id) ((id)[0]) + +#define ID_GET_MFR_CODE(id) ID_GET_BYTE_1(id) + +/* Byte 2 ------------------------------------------------------------------- */ + +#define ID_GET_BYTE_2(id) ((id)[1]) + +#define ID_GET_DEVICE_CODE(id) ID_GET_BYTE_2(id) + #define ID_SAMSUNG_DEVICE_CODE_1_GBIT (0xf1) + #define ID_SAMSUNG_DEVICE_CODE_2_GBIT (0xda) + #define ID_HYNIX_DEVICE_CODE_ECC12 (0xd7) + #define ID_HYNIX_DEVICE_CODE_ECC12_LARGE (0xde) + #define ID_MICRON_DEVICE_CODE_ECC12 (0xd7) /* ECC12 */ + #define ID_MICRON_DEVICE_CODE_ECC12_LARGE (0xd9) /* ECC12 8GB/CE */ + #define ID_MICRON_DEVICE_CODE_ECC12_2GB_PER_CE (0x48) /* L63B 2GB/CE */ + #define ID_MICRON_DEVICE_CODE_ECC12_4GB_PER_CE (0x68) /* L63B 4GB/CE */ + #define ID_MICRON_DEVICE_CODE_ECC12_8GB_PER_CE (0x88) /* L63B 8GB/CE */ + +/* Byte 3 ------------------------------------------------------------------- */ + +#define ID_GET_BYTE_3(id) ((id)[2]) + +#define ID_GET_DIE_COUNT_CODE(id) ((ID_GET_BYTE_3(id) >> 0) & 0x3) + +#define ID_GET_CELL_TYPE_CODE(id) ((ID_GET_BYTE_3(id) >> 2) & 0x3) + #define ID_CELL_TYPE_CODE_SLC (0x0) /* All others => MLC. */ + +#define ID_GET_SAMSUNG_SIMUL_PROG(id) ((ID_GET_BYTE_3(id) >> 4) & 0x3) + +#define ID_GET_MICRON_SIMUL_PROG(id) ((ID_GET_BYTE_3(id) >> 4) & 0x3) + +#define ID_GET_CACHE_PROGRAM(id) ((ID_GET_BYTE_3(id) >> 7) & 0x1) + +/* Byte 4 ------------------------------------------------------------------- */ + +#define ID_GET_BYTE_4(id) ((id)[3]) + #define ID_HYNIX_BYTE_4_ECC12_DEVICE (0x25) + +#define ID_GET_PAGE_SIZE_CODE(id) ((ID_GET_BYTE_4(id) >> 0) & 0x3) + #define ID_PAGE_SIZE_CODE_1K (0x0) + #define ID_PAGE_SIZE_CODE_2K (0x1) + #define ID_PAGE_SIZE_CODE_4K (0x2) + #define ID_PAGE_SIZE_CODE_8K (0x3) + #define ID_SAMSUNG_6_BYTE_PAGE_SIZE_CODE_8K (0x2) + +#define ID_GET_OOB_SIZE_CODE(id) ((ID_GET_BYTE_4(id) >> 2) & 0x1) + +#define ID_GET_BLOCK_SIZE_CODE(id) ((ID_GET_BYTE_4(id) >> 4) & 0x3) + +/* Byte 5 ------------------------------------------------------------------- */ + +#define ID_GET_BYTE_5(id) ((id)[4]) + #define ID_MICRON_BYTE_5_ECC12 (0x84) + +#define ID_GET_SAMSUNG_ECC_LEVEL_CODE(id) ((ID_GET_BYTE_5(id) >> 4) & 0x7) + #define ID_SAMSUNG_ECC_LEVEL_CODE_8 (0x03) + #define ID_SAMSUNG_ECC_LEVEL_CODE_24 (0x05) + +#define ID_GET_PLANE_COUNT_CODE(id) ((ID_GET_BYTE_5(id) >> 2) & 0x3) + +/* Byte 6 ------------------------------------------------------------------- */ + +#define ID_GET_BYTE_6(id) ((id)[5]) + #define ID_TOSHIBA_BYTE_6_PAGE_SIZE_CODE_8K (0x54) + #define ID_TOSHIBA_BYTE_6_PAGE_SIZE_CODE_4K (0x13) + +#define ID_GET_SAMSUNG_DEVICE_VERSION_CODE(id) ((ID_GET_BYTE_6(id)>>0) & 0x7) + #define ID_SAMSUNG_DEVICE_VERSION_CODE_40NM (0x01) + +/* -------------------------------------------------------------------------- */ + +void nand_device_print_info(struct nand_device_info *info) +{ + unsigned i; + const char *mfr_name; + const char *cell_technology_name; + uint64_t chip_size; + const char *chip_size_units; + unsigned page_data_size_in_bytes; + unsigned page_oob_size_in_bytes; + + /* Check for nonsense. */ + + if (!info) + return; + + /* Prepare the manufacturer name. */ + + mfr_name = "Unknown"; + + for (i = 0; nand_manuf_ids[i].id; i++) { + if (nand_manuf_ids[i].id == info->manufacturer_code) { + mfr_name = nand_manuf_ids[i].name; + break; + } + } + + /* Prepare the name of the cell technology. */ + + switch (info->cell_technology) { + case NAND_DEVICE_CELL_TECH_SLC: + cell_technology_name = "SLC"; + break; + case NAND_DEVICE_CELL_TECH_MLC: + cell_technology_name = "MLC"; + break; + default: + cell_technology_name = "Unknown"; + break; + } + + /* Prepare the chip size. */ + + if ((info->chip_size_in_bytes >= SZ_1G) && + !(info->chip_size_in_bytes % SZ_1G)) { + chip_size = info->chip_size_in_bytes / ((uint64_t) SZ_1G); + chip_size_units = "GiB"; + } else if ((info->chip_size_in_bytes >= SZ_1M) && + !(info->chip_size_in_bytes % SZ_1M)) { + chip_size = info->chip_size_in_bytes / ((uint64_t) SZ_1M); + chip_size_units = "MiB"; + } else { + chip_size = info->chip_size_in_bytes; + chip_size_units = "B"; + } + + /* Prepare the page geometry. */ + + page_data_size_in_bytes = info->page_total_size_in_bytes & ~0x3ff; + page_oob_size_in_bytes = info->page_total_size_in_bytes & 0x3ff; + + /* Print the information. */ + + printk(KERN_INFO "Manufacturer : %s (0x%02x)\n", mfr_name, + info->manufacturer_code); + printk(KERN_INFO "Device Code : 0x%02x\n", info->device_code); + printk(KERN_INFO "Cell Technology : %s\n", cell_technology_name); + printk(KERN_INFO "Chip Size : %u %s\n", (u32)chip_size, + chip_size_units); + printk(KERN_INFO "Pages per Block : %u\n", + info->block_size_in_pages); + printk(KERN_INFO "Page Geometry : %u+%u\n", page_data_size_in_bytes, + page_oob_size_in_bytes); + printk(KERN_INFO "ECC Strength : %u bits\n", + info->ecc_strength_in_bits); + printk(KERN_INFO "ECC Size : %u B\n", info->ecc_size_in_bytes); + printk(KERN_INFO "Data Setup Time : %u ns\n", info->data_setup_in_ns); + printk(KERN_INFO "Data Hold Time : %u ns\n", info->data_hold_in_ns); + printk(KERN_INFO "Address Setup Time: %u ns\n", + info->address_setup_in_ns); + printk(KERN_INFO "GPMI Sample Delay : %u ns\n", + info->gpmi_sample_delay_in_ns); + if (info->tREA_in_ns >= 0) + printk(KERN_INFO "tREA : %u ns\n", + info->tREA_in_ns); + else + printk(KERN_INFO "tREA : Unknown\n"); + if (info->tREA_in_ns >= 0) + printk(KERN_INFO "tRLOH : %u ns\n", + info->tRLOH_in_ns); + else + printk(KERN_INFO "tRLOH : Unknown\n"); + if (info->tREA_in_ns >= 0) + printk(KERN_INFO "tRHOH : %u ns\n", + info->tRHOH_in_ns); + else + printk(KERN_INFO "tRHOH : Unknown\n"); + if (info->description) + printk(KERN_INFO "Description : %s\n", info->description); + else + printk(KERN_INFO "Description : \n"); + +} + +static struct nand_device_info *nand_device_info_search( + struct nand_device_info *table, uint8_t mfr_code, uint8_t device_code) +{ + + for (; !table->end_of_table; table++) { + if (table->manufacturer_code != mfr_code) + continue; + if (table->device_code != device_code) + continue; + return table; + } + + return 0; + +} + +static struct nand_device_info *nand_device_info_fn_toshiba(const uint8_t id[]) +{ + struct nand_device_info *table; + + /* Check for an SLC device. */ + + if (ID_GET_CELL_TYPE_CODE(id) == ID_CELL_TYPE_CODE_SLC) { + /* Type 2 */ + return nand_device_info_search(nand_device_info_table_type_2, + ID_GET_MFR_CODE(id), ID_GET_DEVICE_CODE(id)); + } + + /* + * Look for 8K page Toshiba MLC devices. + * + * The page size field in byte 4 can't be used because the field was + * redefined in the 8K parts so the value meaning "8K page" is the same + * as the value meaning "4K page" on the 4K page devices. + * + * The only identifiable difference between the 4K and 8K page Toshiba + * devices with a device code of 0xd7 is the undocumented 6th ID byte. + * The 4K device returns a value of 0x13 and the 8K a value of 0x54. + * Toshiba has verified that this is an acceptable method to distinguish + * the two device families. + */ + + if (ID_GET_BYTE_6(id) == ID_TOSHIBA_BYTE_6_PAGE_SIZE_CODE_8K) { + /* Type 11 */ + table = nand_device_info_table_type_11; + } else if (ID_GET_PAGE_SIZE_CODE(id) == ID_PAGE_SIZE_CODE_4K) { + /* Type 9 */ + table = nand_device_info_table_type_9; + } else { + /* Large MLC */ + table = nand_device_info_table_large_mlc; + } + + return nand_device_info_search(table, ID_GET_MFR_CODE(id), + ID_GET_DEVICE_CODE(id)); + +} + +static struct nand_device_info *nand_device_info_fn_samsung(const uint8_t id[]) +{ + struct nand_device_info *table; + + /* Check for an MLC device. */ + + if (ID_GET_CELL_TYPE_CODE(id) != ID_CELL_TYPE_CODE_SLC) { + + /* Is this a Samsung 8K Page MLC device with 16 bit ECC? */ + if ((ID_GET_SAMSUNG_ECC_LEVEL_CODE(id) == + ID_SAMSUNG_ECC_LEVEL_CODE_24) && + (ID_GET_PAGE_SIZE_CODE(id) == + ID_SAMSUNG_6_BYTE_PAGE_SIZE_CODE_8K)) { + /* Type 15 */ + table = nand_device_info_table_type_15; + } + /* Is this a Samsung 42nm ECC8 device with a 6 byte ID? */ + else if ((ID_GET_SAMSUNG_ECC_LEVEL_CODE(id) == + ID_SAMSUNG_ECC_LEVEL_CODE_8) && + (ID_GET_SAMSUNG_DEVICE_VERSION_CODE(id) == + ID_SAMSUNG_DEVICE_VERSION_CODE_40NM)) { + /* Type 9 */ + table = nand_device_info_table_type_9; + } else if (ID_GET_PAGE_SIZE_CODE(id) == ID_PAGE_SIZE_CODE_4K) { + /* Type 8 */ + table = nand_device_info_table_type_8; + } else { + /* Large MLC */ + table = nand_device_info_table_large_mlc; + } + + } else { + + /* Check the page size first. */ + if (ID_GET_PAGE_SIZE_CODE(id) == ID_PAGE_SIZE_CODE_4K) { + /* Type 10 */ + table = nand_device_info_table_type_10; + } + /* Check the chip size. */ + else if (ID_GET_DEVICE_CODE(id) == + ID_SAMSUNG_DEVICE_CODE_1_GBIT) { + if (!ID_GET_CACHE_PROGRAM(id)) { + /* + * 128 MiB Samsung chips without cache program + * are Type 7. + * + * The K9F1G08U0B does not support multi-plane + * program, so the if statement below cannot be + * used to identify it. + */ + table = nand_device_info_table_type_7; + + } else { + /* Smaller sizes are Type 2 by default. */ + table = nand_device_info_table_type_2; + } + } else { + /* Check number of simultaneously programmed pages. */ + if (ID_GET_SAMSUNG_SIMUL_PROG(id) && + ID_GET_PLANE_COUNT_CODE(id)) { + /* Type 7 */ + table = nand_device_info_table_type_7; + } else { + /* Type 2 */ + table = nand_device_info_table_type_2; + } + + } + + } + + return nand_device_info_search(table, ID_GET_MFR_CODE(id), + ID_GET_DEVICE_CODE(id)); + +} + +static struct nand_device_info *nand_device_info_fn_stmicro(const uint8_t id[]) +{ + struct nand_device_info *table; + + /* Check for an SLC device. */ + + if (ID_GET_CELL_TYPE_CODE(id) == ID_CELL_TYPE_CODE_SLC) + /* Type 2 */ + table = nand_device_info_table_type_2; + else + /* Large MLC */ + table = nand_device_info_table_large_mlc; + + return nand_device_info_search(table, ID_GET_MFR_CODE(id), + ID_GET_DEVICE_CODE(id)); + +} + +static struct nand_device_info *nand_device_info_fn_hynix(const uint8_t id[]) +{ + struct nand_device_info *table; + + /* Check for an SLC device. */ + + if (ID_GET_CELL_TYPE_CODE(id) == ID_CELL_TYPE_CODE_SLC) { + /* Type 2 */ + return nand_device_info_search(nand_device_info_table_type_2, + ID_GET_MFR_CODE(id), ID_GET_DEVICE_CODE(id)); + } + + /* + * Check for ECC12 devices. + * + * We look at the 4th ID byte to distinguish some Hynix ECC12 devices + * from the similar ECC8 part. For example H27UBG8T2M (ECC12) 4th byte + * is 0x25, whereas H27UDG8WFM (ECC8) 4th byte is 0xB6. + */ + + if ((ID_GET_DEVICE_CODE(id) == ID_HYNIX_DEVICE_CODE_ECC12 && + ID_GET_BYTE_4(id) == ID_HYNIX_BYTE_4_ECC12_DEVICE) || + (ID_GET_DEVICE_CODE(id) == ID_HYNIX_DEVICE_CODE_ECC12_LARGE)) { + /* BCH ECC 12 */ + table = nand_device_info_table_bch_ecc12; + } else if (ID_GET_PAGE_SIZE_CODE(id) == ID_PAGE_SIZE_CODE_4K) { + /* + * So far, all other Samsung and Hynix 4K page devices are + * Type 8. + */ + table = nand_device_info_table_type_8; + } else + /* Large MLC */ + table = nand_device_info_table_large_mlc; + + return nand_device_info_search(table, ID_GET_MFR_CODE(id), + ID_GET_DEVICE_CODE(id)); + +} + +static struct nand_device_info *nand_device_info_fn_micron(const uint8_t id[]) +{ + struct nand_device_info *table; + + /* Check for an SLC device. */ + + if (ID_GET_CELL_TYPE_CODE(id) == ID_CELL_TYPE_CODE_SLC) { + + /* Check number of simultaneously programmed pages. */ + + if (ID_GET_MICRON_SIMUL_PROG(id)) { + /* Type 7 */ + table = nand_device_info_table_type_7; + } else { + /* Zero simultaneously programmed pages means Type 2. */ + table = nand_device_info_table_type_2; + } + + return nand_device_info_search(table, ID_GET_MFR_CODE(id), + ID_GET_DEVICE_CODE(id)); + + } + + /* + * We look at the 5th ID byte to distinguish some Micron ECC12 NANDs + * from the similar ECC8 part. + * + * For example MT29F64G08CFAAA (ECC12) 5th byte is 0x84, whereas + * MT29F64G08TAA (ECC8) 5th byte is 0x78. + * + * We also have a special case for the Micron L63B family + * (256 page/block), which has unique device codes but no ID fields that + * can easily be used to distinguish the family. + */ + + if ((ID_GET_DEVICE_CODE(id) == ID_MICRON_DEVICE_CODE_ECC12 && + ID_GET_BYTE_5(id) == ID_MICRON_BYTE_5_ECC12) || + (ID_GET_DEVICE_CODE(id) == ID_MICRON_DEVICE_CODE_ECC12_LARGE) || + (ID_GET_DEVICE_CODE(id) == ID_MICRON_DEVICE_CODE_ECC12_2GB_PER_CE) || + (ID_GET_DEVICE_CODE(id) == ID_MICRON_DEVICE_CODE_ECC12_4GB_PER_CE) || + (ID_GET_DEVICE_CODE(id) == ID_MICRON_DEVICE_CODE_ECC12_8GB_PER_CE)) { + /* BCH ECC 12 */ + table = nand_device_info_table_bch_ecc12; + } else if (ID_GET_PAGE_SIZE_CODE(id) == ID_PAGE_SIZE_CODE_4K) { + /* Toshiba devices with 4K pages are Type 9. */ + table = nand_device_info_table_type_9; + } else { + /* Large MLC */ + table = nand_device_info_table_large_mlc; + } + + return nand_device_info_search(table, ID_GET_MFR_CODE(id), + ID_GET_DEVICE_CODE(id)); + +} + +static struct nand_device_info *nand_device_info_fn_sandisk(const uint8_t id[]) +{ + struct nand_device_info *table; + + if (ID_GET_CELL_TYPE_CODE(id) != ID_CELL_TYPE_CODE_SLC) { + /* Large MLC */ + table = nand_device_info_table_large_mlc; + } else { + /* Type 2 */ + table = nand_device_info_table_type_2; + } + + return nand_device_info_search(table, ID_GET_MFR_CODE(id), + ID_GET_DEVICE_CODE(id)); + +} + +static struct nand_device_info *nand_device_info_fn_intel(const uint8_t id[]) +{ + struct nand_device_info *table; + + /* Check for an SLC device. */ + + if (ID_GET_CELL_TYPE_CODE(id) == ID_CELL_TYPE_CODE_SLC) { + /* Type 2 */ + return nand_device_info_search(nand_device_info_table_type_2, + ID_GET_MFR_CODE(id), ID_GET_DEVICE_CODE(id)); + } + + if (ID_GET_PAGE_SIZE_CODE(id) == ID_PAGE_SIZE_CODE_4K) { + /* Type 9 */ + table = nand_device_info_table_type_9; + } else { + /* Large MLC */ + table = nand_device_info_table_large_mlc; + } + + return nand_device_info_search(table, ID_GET_MFR_CODE(id), + ID_GET_DEVICE_CODE(id)); + +} + +/** + * struct nand_device_type_info - Information about a NAND Flash type. + * + * @name: A human-readable name for this type. + * @table: The device info table for this type. + */ + +struct nand_device_type_info { + struct nand_device_info *table; + const char *name; +}; + +/* + * A table that maps manufacturer IDs to device information tables. + */ + +static struct nand_device_type_info nand_device_type_directory[] = +{ + {nand_device_info_table_type_2, "Type 2" }, + {nand_device_info_table_large_mlc, "Large MLC"}, + {nand_device_info_table_type_7, "Type 7" }, + {nand_device_info_table_type_8, "Type 8" }, + {nand_device_info_table_type_9, "Type 9" }, + {nand_device_info_table_type_10, "Type 10" }, + {nand_device_info_table_type_11, "Type 11" }, + {nand_device_info_table_type_15, "Type 15" }, + {nand_device_info_table_bch_ecc12, "BCH ECC12"}, + {0, 0}, +}; + +/** + * struct nand_device_mfr_info - Information about a NAND Flash manufacturer. + * + * @id: The value of the first NAND Flash ID byte, which identifies the + * manufacturer. + * @fn: A pointer to a function to use for identifying devices from the + * given manufacturer. + */ + +struct nand_device_mfr_info { + uint8_t id; + struct nand_device_info *(*fn)(const uint8_t id[]); +}; + +/* + * A table that maps manufacturer IDs to device information tables. + */ + +static struct nand_device_mfr_info nand_device_mfr_directory[] = +{ + { + .id = NAND_MFR_TOSHIBA, + .fn = nand_device_info_fn_toshiba, + }, + { + .id = NAND_MFR_SAMSUNG, + .fn = nand_device_info_fn_samsung, + }, + { + .id = NAND_MFR_FUJITSU, + .fn = 0, + }, + { + .id = NAND_MFR_NATIONAL, + .fn = 0, + }, + { + .id = NAND_MFR_RENESAS, + .fn = 0, + }, + { + .id = NAND_MFR_STMICRO, + .fn = nand_device_info_fn_stmicro, + }, + { + .id = NAND_MFR_HYNIX, + .fn = nand_device_info_fn_hynix, + }, + { + .id = NAND_MFR_MICRON, + .fn = nand_device_info_fn_micron, + }, + { + .id = NAND_MFR_AMD, + .fn = 0, + }, + { + .id = NAND_MFR_SANDISK, + .fn = nand_device_info_fn_sandisk, + }, + { + .id = NAND_MFR_INTEL, + .fn = nand_device_info_fn_intel, + }, + {0, 0} +}; + +/** + * nand_device_info_test_table - Validate a device info table. + * + * This function runs tests on the given device info table to check that it + * meets the current assumptions. + */ + +static void nand_device_info_test_table( + struct nand_device_info *table, const char * name) +{ + unsigned i; + unsigned j; + uint8_t mfr_code; + uint8_t device_code; + + /* Loop over entries in this table. */ + + for (i = 0; !table[i].end_of_table; i++) { + + /* Get discriminating attributes of the current device. */ + + mfr_code = table[i].manufacturer_code; + device_code = table[i].device_code; + + /* Compare with the remaining devices in this table. */ + + for (j = i + 1; !table[j].end_of_table; j++) { + if ((mfr_code == table[j].manufacturer_code) && + (device_code == table[j].device_code)) + goto error; + } + + } + + return; + +error: + + printk(KERN_EMERG + "\n== NAND Flash device info table failed validity check ==\n"); + + printk(KERN_EMERG "\nDevice Info Table: %s\n", name); + printk(KERN_EMERG "\nTable Index %u\n", i); + nand_device_print_info(table + i); + printk(KERN_EMERG "\nTable Index %u\n", j); + nand_device_print_info(table + j); + printk(KERN_EMERG "\n"); + + BUG(); + +} + +/** + * nand_device_info_test_data - Test the NAND Flash device data. + */ + +static void nand_device_info_test_data(void) +{ + + unsigned i; + + for (i = 0; nand_device_type_directory[i].name; i++) { + nand_device_info_test_table( + nand_device_type_directory[i].table, + nand_device_type_directory[i].name); + } + +} + +struct nand_device_info *nand_device_get_info(const uint8_t id[]) +{ + unsigned i; + uint8_t mfr_id = ID_GET_MFR_CODE(id); + struct nand_device_info *(*fn)(const uint8_t id[]) = 0; + + /* Test the data. */ + + nand_device_info_test_data(); + + /* Look for information about this manufacturer. */ + + for (i = 0; nand_device_mfr_directory[i].id; i++) { + if (nand_device_mfr_directory[i].id == mfr_id) { + fn = nand_device_mfr_directory[i].fn; + break; + } + } + + if (!fn) + return 0; + + /* + * If control arrives here, we found both a table of device information, + * and a function we can use to identify the current device. Attempt to + * identify the device and return the result. + */ + + return fn(id); + +} diff --git a/drivers/mtd/nand/nand_device_info.h b/drivers/mtd/nand/nand_device_info.h new file mode 100644 index 0000000000..9b7923a5d4 --- /dev/null +++ b/drivers/mtd/nand/nand_device_info.h @@ -0,0 +1,144 @@ +/* + * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#ifndef __DRIVERS_NAND_DEVICE_INFO_H +#define __DRIVERS_NAND_DEVICE_INFO_H + + /* + * The number of ID bytes to read from the NAND Flash device and hand over to + * the identification system. + */ + +#define NAND_DEVICE_ID_BYTE_COUNT (6) + +#define bool int +#define false 0 +#define true 1 + + /* + * The number of ID bytes to read from the NAND Flash device and hand over to + * the identification system. + */ + +enum nand_device_cell_technology { + NAND_DEVICE_CELL_TECH_SLC = 0, + NAND_DEVICE_CELL_TECH_MLC = 1, +}; + +/** + * struct nand_device_info - Information about a single NAND Flash device. + * + * This structure contains all the *essential* information about a NAND Flash + * device, derived from the device's data sheet. For each manufacturer, we have + * an array of these structures. + * + * @end_of_table: If true, marks the end of a table of device + * information. + * @manufacturer_code: The manufacturer code (1st ID byte) reported by + * the device. + * @device_code: The device code (2nd ID byte) reported by the + * device. + * @cell_technology: The storage cell technology. + * @chip_size_in_bytes: The total size of the storage behind a single + * chip select, in bytes. Notice that this is *not* + * necessarily the total size of the storage in a + * *package*, which may contain several chips. + * @block_size_in_pages: The number of pages in a block. + * @page_total_size_in_bytes: The total size of a page, in bytes, including + * both the data and the OOB. + * @ecc_strength_in_bits: The strength of the ECC called for by the + * manufacturer, in number of correctable bits. + * @ecc_size_in_bytes: The size of the data block over which the + * manufacturer calls for the given ECC algorithm + * and strength. + * @data_setup_in_ns: The data setup time, in nanoseconds. Usually the + * maximum of tDS and tWP. A negative value + * indicates this characteristic isn't known. + * @data_hold_in_ns: The data hold time, in nanoseconds. Usually the + * maximum of tDH, tWH and tREH. A negative value + * indicates this characteristic isn't known. + * @address_setup_in_ns: The address setup time, in nanoseconds. Usually + * the maximum of tCLS, tCS and tALS. A negative + * value indicates this characteristic isn't known. + * @gpmi_sample_delay_in_ns: A GPMI-specific timing parameter. A negative + * value indicates this characteristic isn't known. + * @tREA_in_ns: tREA, in nanoseconds, from the data sheet. A + * negative value indicates this characteristic + * isn't known. + * @tRLOH_in_ns: tRLOH, in nanoseconds, from the data sheet. A + * negative value indicates this characteristic + * isn't known. + * @tRHOH_in_ns: tRHOH, in nanoseconds, from the data sheet. A + * negative value indicates this characteristic + * isn't known. + */ + +struct nand_device_info { + + /* End of table marker */ + + bool end_of_table; + + /* Manufacturer and Device codes */ + + uint8_t manufacturer_code; + uint8_t device_code; + + /* Technology */ + + enum nand_device_cell_technology cell_technology; + + /* Geometry */ + + uint64_t chip_size_in_bytes; + uint32_t block_size_in_pages; + uint16_t page_total_size_in_bytes; + + /* ECC */ + + uint8_t ecc_strength_in_bits; + uint16_t ecc_size_in_bytes; + + /* Timing */ + + int8_t data_setup_in_ns; + int8_t data_hold_in_ns; + int8_t address_setup_in_ns; + int8_t gpmi_sample_delay_in_ns; + int8_t tREA_in_ns; + int8_t tRLOH_in_ns; + int8_t tRHOH_in_ns; + + /* Description */ + + const char *description; + +}; + +/** + * nand_device_get_info - Get info about a device based on ID bytes. + * + * @id_bytes: An array of NAND_DEVICE_ID_BYTE_COUNT ID bytes retrieved from the + * NAND Flash device. + */ + +struct nand_device_info *nand_device_get_info(const uint8_t id_bytes[]); + +/** + * nand_device_print_info - Prints information about a NAND Flash device. + * + * @info A pointer to a NAND Flash device information structure. + */ + +void nand_device_print_info(struct nand_device_info *info); + +#endif diff --git a/drivers/mtd/nand/nand_ids.c b/drivers/mtd/nand/nand_ids.c index 077c3051bc..e4be857e50 100644 --- a/drivers/mtd/nand/nand_ids.c +++ b/drivers/mtd/nand/nand_ids.c @@ -23,14 +23,13 @@ * 512 512 Byte page size */ struct nand_flash_dev nand_flash_ids[] = { - #ifdef CONFIG_MTD_NAND_MUSEUM_IDS - {"NAND 1MiB 5V 8-bit", 0x6e, 256, 1, 0x1000, 0}, - {"NAND 2MiB 5V 8-bit", 0x64, 256, 2, 0x1000, 0}, - {"NAND 4MiB 5V 8-bit", 0x6b, 512, 4, 0x2000, 0}, - {"NAND 1MiB 3,3V 8-bit", 0xe8, 256, 1, 0x1000, 0}, - {"NAND 1MiB 3,3V 8-bit", 0xec, 256, 1, 0x1000, 0}, - {"NAND 2MiB 3,3V 8-bit", 0xea, 256, 2, 0x1000, 0}, + {"NAND 1MiB 5V 8-bit", 0x6e, 256, 1, 0x1000, 0}, + {"NAND 2MiB 5V 8-bit", 0x64, 256, 2, 0x1000, 0}, + {"NAND 4MiB 5V 8-bit", 0x6b, 512, 4, 0x2000, 0}, + {"NAND 1MiB 3,3V 8-bit", 0xe8, 256, 1, 0x1000, 0}, + {"NAND 1MiB 3,3V 8-bit", 0xec, 256, 1, 0x1000, 0}, + {"NAND 2MiB 3,3V 8-bit", 0xea, 256, 2, 0x1000, 0}, {"NAND 4MiB 3,3V 8-bit", 0xd5, 512, 4, 0x2000, 0}, {"NAND 4MiB 3,3V 8-bit", 0xe3, 512, 4, 0x2000, 0}, {"NAND 4MiB 3,3V 8-bit", 0xe5, 512, 4, 0x2000, 0}, @@ -41,7 +40,6 @@ struct nand_flash_dev nand_flash_ids[] = { {"NAND 8MiB 1,8V 16-bit", 0x49, 512, 8, 0x2000, NAND_BUSWIDTH_16}, {"NAND 8MiB 3,3V 16-bit", 0x59, 512, 8, 0x2000, NAND_BUSWIDTH_16}, #endif - {"NAND 16MiB 1,8V 8-bit", 0x33, 512, 16, 0x4000, 0}, {"NAND 16MiB 3,3V 8-bit", 0x73, 512, 16, 0x4000, 0}, {"NAND 16MiB 1,8V 16-bit", 0x43, 512, 16, 0x4000, NAND_BUSWIDTH_16}, @@ -110,6 +108,9 @@ struct nand_flash_dev nand_flash_ids[] = { {"NAND 2GiB 1,8V 16-bit", 0xB5, 0, 2048, 0, LP_OPTIONS16}, {"NAND 2GiB 3,3V 16-bit", 0xC5, 0, 2048, 0, LP_OPTIONS16}, + /* 32 Gigabit ,only use 2G due to the linux mtd limitation*/ + {"NAND 4GiB 3,3V 8-bit", 0xD7, 0, 2048, 0, LP_OPTIONS}, + /* * Renesas AND 1 Gigabit. Those chips do not support extended id and * have a strange page/block layout ! The chosen minimum erasesize is @@ -124,7 +125,6 @@ struct nand_flash_dev nand_flash_ids[] = { NAND_IS_AND | NAND_NO_AUTOINCR |NAND_NO_READRDY | NAND_4PAGE_ARRAY | BBT_AUTO_REFRESH }, - {NULL,} }; @@ -141,5 +141,8 @@ struct nand_manufacturers nand_manuf_ids[] = { {NAND_MFR_HYNIX, "Hynix"}, {NAND_MFR_MICRON, "Micron"}, {NAND_MFR_AMD, "AMD"}, + {NAND_MFR_SANDISK, "SanDisk"} , + {NAND_MFR_INTEL, "Intel"} , + {0x0, "Unknown"} }; diff --git a/drivers/mtd/spi/Makefile b/drivers/mtd/spi/Makefile index e3e0292808..9d92bf5a79 100644 --- a/drivers/mtd/spi/Makefile +++ b/drivers/mtd/spi/Makefile @@ -32,6 +32,9 @@ COBJS-$(CONFIG_SPI_FLASH_SPANSION) += spansion.o COBJS-$(CONFIG_SPI_FLASH_SST) += sst.o COBJS-$(CONFIG_SPI_FLASH_STMICRO) += stmicro.o COBJS-$(CONFIG_SPI_M95XXX) += eeprom_m95xxx.o +COBJS-$(CONFIG_SPI_FLASH_IMX) += imx_spi_nor.o +COBJS-$(CONFIG_SPI_FLASH_IMX_SST) += imx_spi_nor_sst.o +COBJS-$(CONFIG_SPI_FLASH_IMX_ATMEL) += imx_spi_nor_atmel.o COBJS := $(COBJS-y) SRCS := $(COBJS:.o=.c) diff --git a/drivers/mtd/spi/imx_spi_nor_atmel.c b/drivers/mtd/spi/imx_spi_nor_atmel.c new file mode 100644 index 0000000000..5575498633 --- /dev/null +++ b/drivers/mtd/spi/imx_spi_nor_atmel.c @@ -0,0 +1,532 @@ +/* + * (C) Copyright 2008-2010 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +static u8 g_tx_buf[256]; +static u8 g_rx_buf[256]; + +#define WRITE_ENABLE(a) spi_nor_cmd_1byte(a, WREN) +#define ENABLE_WRITE_STATUS(a) spi_nor_cmd_1byte(a, EWSR) + +struct imx_spi_flash_params { + u8 idcode1; + u32 block_size; + u32 block_count; + u32 device_size; + const char *name; +}; + +struct imx_spi_flash { + const struct imx_spi_flash_params *params; + struct spi_flash flash; +}; + +static inline struct imx_spi_flash * +to_imx_spi_flash(struct spi_flash *flash) +{ + return container_of(flash, struct imx_spi_flash, flash); +} + +static const struct imx_spi_flash_params imx_spi_flash_table[] = { + { + .idcode1 = 0x27, + .block_size = SZ_64K, + .block_count = 64, + .device_size = SZ_64K * 64, + .name = "AT45DB321D - 4MB", + }, +}; + +static s32 spi_nor_flash_query(struct spi_flash *flash, void* data) +{ + u8 au8Tmp[4] = { 0 }; + u8 *pData = (u8 *)data; + + g_tx_buf[3] = JEDEC_ID; + + if (spi_xfer(flash->spi, (4 << 3), g_tx_buf, au8Tmp, + SPI_XFER_BEGIN | SPI_XFER_END)) { + return -1; + } + + printf("JEDEC ID: 0x%02x:0x%02x:0x%02x\n", + au8Tmp[2], au8Tmp[1], au8Tmp[0]); + + pData[0] = au8Tmp[2]; + pData[1] = au8Tmp[1]; + pData[2] = au8Tmp[0]; + + return 0; +} + +static s32 spi_nor_status(struct spi_flash *flash) +{ + g_tx_buf[1] = STAT_READ; + + if (spi_xfer(flash->spi, 2 << 3, g_tx_buf, g_rx_buf, + SPI_XFER_BEGIN | SPI_XFER_END) != 0) { + printf("Error: %s(): %d\n", __func__, __LINE__); + return 0; + } + return g_rx_buf[0]; +} + +#if 0 +/*! + * Erase a block_size data from block_addr offset in the flash + */ +static int spi_nor_erase_page(struct spi_flash *flash, + void *page_addr) +{ + u32 addr = (u32)page_addr; + + if ((addr & 512) != 0) { + printf("Error - page_addr is not " + "512 Bytes aligned: %p\n", + page_addr); + return -1; + } + + /* now do the block erase */ + if (spi_xfer(flash->spi, 4 << 3, g_tx_buf, g_rx_buf, + SPI_XFER_BEGIN | SPI_XFER_END) != 0) { + return -1; + } + + while (spi_nor_status(flash) & RDSR_BUSY) + ; + + return 0; +} +#endif + +static int spi_nor_flash_read(struct spi_flash *flash, u32 offset, + size_t len, void *buf) +{ + struct imx_spi_flash *imx_sf = to_imx_spi_flash(flash); + u32 *cmd = (u32 *)g_tx_buf; + u32 max_rx_sz = (MAX_SPI_BYTES) - 4; + u8 *d_buf = (u8 *)buf; + u8 *s_buf; + s32 s32remain_size = len; + int i; + + if (!(flash->spi)) + return -1; + + printf("Reading SPI NOR flash 0x%x [0x%x bytes] -> ram 0x%p\n", + offset, len, buf); + debug("%s(from flash=0x%08x to ram=%p len=0x%x)\n", + __func__, + offset, buf, len); + + if (len == 0) + return 0; + + *cmd = (READ << 24) | ((u32)offset & 0x00FFFFFF); + + for (; s32remain_size > 0; + s32remain_size -= max_rx_sz, *cmd += max_rx_sz) { + debug("Addr:0x%p=>Offset:0x%08x, %d bytes transferred\n", + d_buf, + (*cmd & 0x00FFFFFF), + (len - s32remain_size)); + debug("%d%% completed\n", ((len - s32remain_size) * 100 / len)); + + if (s32remain_size < max_rx_sz) { + debug("100%% completed\n"); + + if (spi_xfer(flash->spi, (s32remain_size + 4) << 3, + g_tx_buf, g_rx_buf, + SPI_XFER_BEGIN | SPI_XFER_END) != 0) { + printf("Error: %s(%d): failed\n", + __FILE__, __LINE__); + return -1; + } + /* throw away 4 bytes (5th received bytes is real) */ + s_buf = g_rx_buf + 4; + + /* now adjust the endianness */ + for (i = s32remain_size; i >= 0; i -= 4, s_buf += 4) { + if (i < 4) { + if (i == 1) { + *d_buf = s_buf[0]; + } else if (i == 2) { + *d_buf++ = s_buf[1]; + *d_buf++ = s_buf[0]; + } else if (i == 3) { + *d_buf++ = s_buf[2]; + *d_buf++ = s_buf[1]; + *d_buf++ = s_buf[0]; + } + printf("SUCCESS\n\n"); + return 0; + } + /* copy 4 bytes */ + *d_buf++ = s_buf[3]; + *d_buf++ = s_buf[2]; + *d_buf++ = s_buf[1]; + *d_buf++ = s_buf[0]; + } + } + + /* now grab max_rx_sz data (+4 is + *needed due to 4-throw away bytes */ + if (spi_xfer(flash->spi, (max_rx_sz + 4) << 3, + g_tx_buf, g_rx_buf, + SPI_XFER_BEGIN | SPI_XFER_END) != 0) { + printf("Error: %s(%d): failed\n", __FILE__, __LINE__); + return -1; + } + /* throw away 4 bytes (5th received bytes is real) */ + s_buf = g_rx_buf + 4; + /* now adjust the endianness */ + for (i = 0; i < max_rx_sz; i += 4, s_buf += 4) { + *d_buf++ = s_buf[3]; + *d_buf++ = s_buf[2]; + *d_buf++ = s_buf[1]; + *d_buf++ = s_buf[0]; + } + + if ((s32remain_size % imx_sf->params->block_size) == 0) + printf("."); + } + printf("SUCCESS\n\n"); + + return -1; +} + +static int spi_nor_flash_write(struct spi_flash *flash, u32 offset, + size_t len, const void *buf) +{ + u32 d_addr = offset; + u8 *s_buf = (u8 *)buf; + unsigned int final_addr = 0; + int page_size = 528, trans_bytes = 0, buf_ptr = 0, + bytes_sent = 0, byte_sent_per_iter = 0; + int page_no = 0, buf_addr = 0, page_off = 0, + i = 0, j = 0, k = 0, fifo_size = 32; + int remain_len = 0; + + if (!(flash->spi)) + return -1; + + if (len == 0) + return 0; + + printf("Writing SPI NOR flash 0x%x [0x%x bytes] <- ram 0x%p\n", + offset, len, buf); + debug("%s(flash addr=0x%08x, ram=%p, len=0x%x)\n", + __func__, offset, buf, len); + + /* Read the status register to get the Page size */ + if (spi_nor_status(flash) & STAT_PG_SZ) { + page_size = 512; + } else { + puts("Unsupported Page Size of 528 bytes\n"); + g_tx_buf[0] = CONFIG_REG4; + g_tx_buf[1] = CONFIG_REG3; + g_tx_buf[2] = CONFIG_REG2; + g_tx_buf[3] = CONFIG_REG1; + + if (spi_xfer(flash->spi, 4 << 3, g_tx_buf, g_rx_buf, + SPI_XFER_BEGIN | SPI_XFER_END) != 0) { + printf("Error: %s(): %d", __func__, __LINE__); + return -1; + } + + while (!(spi_nor_status(flash) & STAT_BUSY)) + ; + + puts("Reprogrammed the Page Size to 512 bytes\n"); + puts("Please Power Cycle the board for the change to take effect\n"); + + return -1; + } + + /* Due to the way CSPI operates send data less + that 4 bytes in a different manner */ + remain_len = len % 4; + if (remain_len) + len -= remain_len; + + while (1) { + page_no = d_addr / page_size; + /* Get the offset within the page + if address is not page-aligned */ + page_off = (d_addr % page_size); + if (page_off) { + if (page_no == 0) + buf_addr = d_addr; + else + buf_addr = page_off; + + trans_bytes = page_size - buf_addr; + } else { + buf_addr = 0; + trans_bytes = page_size; + } + + if (len <= 0) + break; + + if (trans_bytes > len) + trans_bytes = len; + + bytes_sent = trans_bytes; + /* Write the data to the SPI-NOR Buffer first */ + while (trans_bytes > 0) { + final_addr = (buf_addr & 0x3FF); + g_tx_buf[0] = final_addr; + g_tx_buf[1] = final_addr >> 8; + g_tx_buf[2] = final_addr >> 16; + g_tx_buf[3] = BUF1_WR; /*Opcode */ + + /* 4 bytes already used for Opcode & address bytes, + check to ensure we do not overflow the SPI TX buffer */ + if (trans_bytes > (fifo_size - 4)) + byte_sent_per_iter = fifo_size; + else + byte_sent_per_iter = trans_bytes + 4; + + for (i = 4; i < byte_sent_per_iter; i += 4) { + g_tx_buf[i + 3] = s_buf[buf_ptr++]; + g_tx_buf[i + 2] = s_buf[buf_ptr++]; + g_tx_buf[i + 1] = s_buf[buf_ptr++]; + g_tx_buf[i] = s_buf[buf_ptr++]; + } + + if (spi_xfer(flash->spi, byte_sent_per_iter << 3, + g_tx_buf, g_rx_buf, + SPI_XFER_BEGIN | SPI_XFER_END) != 0) { + printf("Error: %s(%d): failed\n", + __FILE__, __LINE__); + return -1; + } + + while (!(spi_nor_status(flash) & STAT_BUSY)) + ; + + /* Deduct 4 bytes as it is used for Opcode & address bytes */ + trans_bytes -= (byte_sent_per_iter - 4); + /* Update the destination buffer address */ + buf_addr += (byte_sent_per_iter - 4); + } + + /* Send the command to write data from the SPI-NOR Buffer to Flash memory */ + final_addr = (page_size == 512) ? ((page_no & 0x1FFF) << 9) : \ + ((page_no & 0x1FFF) << 10); + + /* Specify the Page address in Flash where the data should be written to */ + g_tx_buf[0] = final_addr; + g_tx_buf[1] = final_addr >> 8; + g_tx_buf[2] = final_addr >> 16; + g_tx_buf[3] = BUF1_TO_MEM; /*Opcode */ + if (spi_xfer(flash->spi, 4 << 3, g_tx_buf, g_rx_buf, + SPI_XFER_BEGIN | SPI_XFER_END) != 0) { + printf("Error: %s(%d): failed\n", __FILE__, __LINE__); + return -1; + } + + while (!(spi_nor_status(flash) & STAT_BUSY)) + ; + + d_addr += bytes_sent; + len -= bytes_sent; + if (d_addr % (page_size * 50) == 0) + puts("."); + } + + if (remain_len) { + buf_ptr += remain_len; + /* Write the remaining data bytes first */ + for (i = 0; i < remain_len; ++i) + g_tx_buf[i] = s_buf[buf_ptr--]; + + /* Write the address bytes next in the same word + as the data byte from the next byte */ + for (j = i, k = 0; j < 4; j++, k++) + g_tx_buf[j] = final_addr >> (k * 8); + + /* Write the remaining address bytes in the next word */ + j = 0; + final_addr = (buf_addr & 0x3FF); + + for (j = 0; k < 3; j++, k++) + g_tx_buf[j] = final_addr >> (k * 8); + + /* Finally the Opcode to write the data to the buffer */ + g_tx_buf[j] = BUF1_WR; /*Opcode */ + + if (spi_xfer(flash->spi, (remain_len + 4) << 3, + g_tx_buf, g_rx_buf, + SPI_XFER_BEGIN | SPI_XFER_END) != 0) { + printf("Error: %s(%d): failed\n", __FILE__, __LINE__); + return -1; + } + + while (!(spi_nor_status(flash) & STAT_BUSY)) + ; + + if (page_size == 512) + final_addr = (page_no & 0x1FFF) << 9; + else + final_addr = (page_no & 0x1FFF) << 10; + + g_tx_buf[0] = final_addr; + g_tx_buf[1] = final_addr >> 8; + g_tx_buf[2] = final_addr >> 16; + g_tx_buf[3] = BUF1_TO_MEM; /*Opcode */ + if (spi_xfer(flash->spi, 4 << 3, g_tx_buf, g_rx_buf, + SPI_XFER_BEGIN | SPI_XFER_END) != 0) { + printf("Error: %s(%d): failed\n", __FILE__, __LINE__); + return -1; + } + + while (!(spi_nor_status(flash) & STAT_BUSY)) + ; + } + + printf("SUCCESS\n\n"); + + return 0; +} + +static int spi_nor_flash_erase(struct spi_flash *flash, u32 offset, + size_t len) +{ + printf("Erase is built in program.\n"); + + return 0; +} + +struct spi_flash *spi_flash_probe(unsigned int bus, unsigned int cs, unsigned int max_hz, unsigned int spi_mode) +{ + struct spi_slave *spi = NULL; + const struct imx_spi_flash_params *params = NULL; + struct imx_spi_flash *imx_sf = NULL; + u8 idcode[4] = { 0 }; + u32 i = 0; + s32 ret = 0; + + if (CONFIG_SPI_FLASH_CS != cs) { + printf("Invalid cs for SPI NOR.\n"); + return NULL; + } + + spi = spi_setup_slave(bus, cs, max_hz, spi_mode); + + if (!spi) { + debug("SF: Failed to set up slave\n"); + return NULL; + } + + ret = spi_claim_bus(spi); + if (ret) { + debug("SF: Failed to claim SPI bus: %d\n", ret); + goto err_claim_bus; + } + + imx_sf = (struct imx_spi_flash *)malloc(sizeof(struct imx_spi_flash)); + + if (!imx_sf) { + debug("SF: Failed to allocate memory\n"); + spi_free_slave(spi); + return NULL; + } + + imx_sf->flash.spi = spi; + + /* Read the ID codes */ + ret = spi_nor_flash_query(&(imx_sf->flash), idcode); + if (ret) + goto err_read_id; + + for (i = 0; i < ARRAY_SIZE(imx_spi_flash_table); ++i) { + params = &imx_spi_flash_table[i]; + if (params->idcode1 == idcode[1]) + break; + } + + if (i == ARRAY_SIZE(imx_spi_flash_table)) { + debug("SF: Unsupported DataFlash ID %02x\n", + idcode[1]); + + goto err_invalid_dev; + } + + imx_sf->params = params; + + imx_sf->flash.name = params->name; + imx_sf->flash.size = params->device_size; + + imx_sf->flash.read = spi_nor_flash_read; + imx_sf->flash.write = spi_nor_flash_write; + imx_sf->flash.erase = spi_nor_flash_erase; + + debug("SF: Detected %s with block size %lu, " + "block count %lu, total %u bytes\n", + params->name, + params->block_size, + params->block_count, + params->device_size); + + return &(imx_sf->flash); + +err_read_id: + spi_release_bus(spi); +err_invalid_dev: + if (imx_sf) + free(imx_sf); +err_claim_bus: + if (spi) + spi_free_slave(spi); + return NULL; +} + +void spi_flash_free(struct spi_flash *flash) +{ + struct imx_spi_flash *imx_sf = NULL; + + if (!flash) + return; + + imx_sf = to_imx_spi_flash(flash); + + if (flash->spi) { + spi_free_slave(flash->spi); + flash->spi = NULL; + } + + free(imx_sf); +} + diff --git a/drivers/mtd/spi/imx_spi_nor_sst.c b/drivers/mtd/spi/imx_spi_nor_sst.c new file mode 100644 index 0000000000..d484a51447 --- /dev/null +++ b/drivers/mtd/spi/imx_spi_nor_sst.c @@ -0,0 +1,564 @@ +/* + * (C) Copyright 2008-2010 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +static u8 g_tx_buf[256]; +static u8 g_rx_buf[256]; + +#define WRITE_ENABLE(a) spi_nor_cmd_1byte(a, WREN) +#define WRITE_DISABLE(a) spi_nor_cmd_1byte(a, WRDI) +#define ENABLE_WRITE_STATUS(a) spi_nor_cmd_1byte(a, EWSR) + +struct imx_spi_flash_params { + u8 idcode1; + u32 block_size; + u32 block_count; + u32 device_size; + const char *name; +}; + +struct imx_spi_flash { + const struct imx_spi_flash_params *params; + struct spi_flash flash; +}; + +static inline struct imx_spi_flash * +to_imx_spi_flash(struct spi_flash *flash) +{ + return container_of(flash, struct imx_spi_flash, flash); +} + +static const struct imx_spi_flash_params imx_spi_flash_table[] = { + { + .idcode1 = 0x25, + .block_size = SZ_64K, + .block_count = 32, + .device_size = SZ_64K * 32, + .name = "SST25VF016B - 2MB", + }, +}; + +static s32 spi_nor_flash_query(struct spi_flash *flash, void* data) +{ + u8 au8Tmp[4] = { 0 }; + u8 *pData = (u8 *)data; + + g_tx_buf[3] = JEDEC_ID; + + if (spi_xfer(flash->spi, (4 << 3), g_tx_buf, au8Tmp, + SPI_XFER_BEGIN | SPI_XFER_END)) { + return -1; + } + + printf("JEDEC ID: 0x%02x:0x%02x:0x%02x\n", + au8Tmp[2], au8Tmp[1], au8Tmp[0]); + + pData[0] = au8Tmp[2]; + pData[1] = au8Tmp[1]; + pData[2] = au8Tmp[0]; + + return 0; +} + +static s32 spi_nor_cmd_1byte(struct spi_flash *flash, u8 cmd) +{ + g_tx_buf[0] = cmd; + + if (spi_xfer(flash->spi, (1 << 3), g_tx_buf, g_rx_buf, + SPI_XFER_BEGIN | SPI_XFER_END) != 0) { + printf("Error: %s(): %d\n", __func__, __LINE__); + return -1; + } + return 0; +} + +static s32 spi_nor_status(struct spi_flash *flash) +{ + g_tx_buf[1] = RDSR; + + if (spi_xfer(flash->spi, 2 << 3, g_tx_buf, g_rx_buf, + SPI_XFER_BEGIN | SPI_XFER_END) != 0) { + printf("Error: %s(): %d\n", __func__, __LINE__); + return 0; + } + return g_rx_buf[0]; +} + +static int spi_nor_program_1byte(struct spi_flash *flash, + u8 data, void *addr) +{ + u32 addr_val = (u32)addr; + + /* need to do write-enable command */ + if (WRITE_ENABLE(flash) != 0) { + printf("Error : %d\n", __LINE__); + return -1; + } + g_tx_buf[0] = BYTE_PROG; /* need to skip bytes 1, 2, 3 */ + g_tx_buf[4] = data; + g_tx_buf[5] = addr_val & 0xFF; + g_tx_buf[6] = (addr_val >> 8) & 0xFF; + g_tx_buf[7] = (addr_val >> 16) & 0xFF; + + debug("0x%x: 0x%x\n", *(u32 *)g_tx_buf, *(u32 *)(g_tx_buf + 4)); + debug("addr=0x%x\n", addr_val); + + if (spi_xfer(flash->spi, 5 << 3, g_tx_buf, g_rx_buf, + SPI_XFER_BEGIN | SPI_XFER_END) != 0) { + printf("Error: %s(%d): failed\n", __FILE__, __LINE__); + return -1; + } + + while (spi_nor_status(flash) & RDSR_BUSY) + ; + + return 0; +} + +/*! + * Write 'val' to flash WRSR (write status register) + */ +static int spi_nor_write_status(struct spi_flash *flash, u8 val) +{ + g_tx_buf[0] = val; + g_tx_buf[1] = WRSR; + + if (spi_xfer(flash->spi, 2 << 3, g_tx_buf, g_rx_buf, + SPI_XFER_BEGIN | SPI_XFER_END) != 0) { + printf("Error: %s(): %d\n", __func__, __LINE__); + return -1; + } + return 0; +} + +/*! + * Erase a block_size data from block_addr offset in the flash + */ +static int spi_nor_erase_block(struct spi_flash *flash, + void *block_addr, u32 block_size) +{ + u32 *cmd = (u32 *)g_tx_buf; + u32 addr = (u32) block_addr; + + if (block_size != SZ_64K && + block_size != SZ_32K && + block_size != SZ_4K) { + printf("Error - block_size is not " + "4kB, 32kB or 64kB: 0x%x\n", + block_size); + return -1; + } + + if ((addr & (block_size - 1)) != 0) { + printf("Error - block_addr is not " + "4kB, 32kB or 64kB aligned: %p\n", + block_addr); + return -1; + } + + if (ENABLE_WRITE_STATUS(flash) != 0 || + spi_nor_write_status(flash, 0) != 0) { + printf("Error: %s: %d\n", __func__, __LINE__); + return -1; + } + + /* need to do write-enable command */ + if (WRITE_ENABLE(flash) != 0) { + printf("Error : %d\n", __LINE__); + return -1; + } + + if (block_size == SZ_64K) + *cmd = (ERASE_64K << 24) | (addr & 0x00FFFFFF); + else if (block_size == SZ_32K) + *cmd = (ERASE_32K << 24) | (addr & 0x00FFFFFF); + else if (block_size == SZ_4K) + *cmd = (ERASE_4K << 24) | (addr & 0x00FFFFFF); + + /* now do the block erase */ + if (spi_xfer(flash->spi, 4 << 3, g_tx_buf, g_rx_buf, + SPI_XFER_BEGIN | SPI_XFER_END) != 0) { + return -1; + } + + while (spi_nor_status(flash) & RDSR_BUSY) + ; + + return 0; +} + +static int spi_nor_flash_read(struct spi_flash *flash, u32 offset, + size_t len, void *buf) +{ + struct imx_spi_flash *imx_sf = to_imx_spi_flash(flash); + u32 *cmd = (u32 *)g_tx_buf; + u32 max_rx_sz = (MAX_SPI_BYTES) - 4; + u8 *d_buf = (u8 *)buf; + u8 *s_buf; + s32 s32remain_size = len; + int i; + + if (!(flash->spi)) + return -1; + + printf("Reading SPI NOR flash 0x%x [0x%x bytes] -> ram 0x%p\n", + offset, len, buf); + debug("%s(from flash=0x%08x to ram=%p len=0x%x)\n", + __func__, + offset, buf, len); + + if (len == 0) + return 0; + + *cmd = (READ << 24) | ((u32)offset & 0x00FFFFFF); + + for (; s32remain_size > 0; s32remain_size -= max_rx_sz, *cmd += max_rx_sz) { + debug("Addr:0x%p=>Offset:0x%08x, %d bytes transferred\n", + d_buf, + (*cmd & 0x00FFFFFF), + (len - s32remain_size)); + debug("%d%% completed\n", ((len - s32remain_size) * 100 / len)); + + if (s32remain_size < max_rx_sz) { + debug("100%% completed\n"); + + if (spi_xfer(flash->spi, (s32remain_size + 4) << 3, + g_tx_buf, g_rx_buf, + SPI_XFER_BEGIN | SPI_XFER_END) != 0) { + printf("Error: %s(%d): failed\n", __FILE__, __LINE__); + return -1; + } + /* throw away 4 bytes (5th received bytes is real) */ + s_buf = g_rx_buf + 4; + + /* now adjust the endianness */ + for (i = s32remain_size; i >= 0; i -= 4, s_buf += 4) { + if (i < 4) { + if (i == 1) { + *d_buf = s_buf[0]; + } else if (i == 2) { + *d_buf++ = s_buf[1]; + *d_buf++ = s_buf[0]; + } else if (i == 3) { + *d_buf++ = s_buf[2]; + *d_buf++ = s_buf[1]; + *d_buf++ = s_buf[0]; + } + printf("SUCCESS\n\n"); + return 0; + } + /* copy 4 bytes */ + *d_buf++ = s_buf[3]; + *d_buf++ = s_buf[2]; + *d_buf++ = s_buf[1]; + *d_buf++ = s_buf[0]; + } + } + + /* now grab max_rx_sz data (+4 is + *needed due to 4-throw away bytes */ + if (spi_xfer(flash->spi, (max_rx_sz + 4) << 3, + g_tx_buf, g_rx_buf, SPI_XFER_BEGIN | SPI_XFER_END) != 0) { + printf("Error: %s(%d): failed\n", __FILE__, __LINE__); + return -1; + } + /* throw away 4 bytes (5th received bytes is real) */ + s_buf = g_rx_buf + 4; + /* now adjust the endianness */ + for (i = 0; i < max_rx_sz; i += 4, s_buf += 4) { + *d_buf++ = s_buf[3]; + *d_buf++ = s_buf[2]; + *d_buf++ = s_buf[1]; + *d_buf++ = s_buf[0]; + } + + if ((s32remain_size % imx_sf->params->block_size) == 0) + printf("."); + } + printf("SUCCESS\n\n"); + + return -1; +} + +static int spi_nor_flash_write(struct spi_flash *flash, u32 offset, + size_t len, const void *buf) +{ + struct imx_spi_flash *imx_sf = to_imx_spi_flash(flash); + u32 d_addr = offset; + u8 *s_buf = (u8 *)buf; + s32 s32remain_size = len; + + if (!(flash->spi)) + return -1; + + if (len == 0) + return 0; + + printf("Writing SPI NOR flash 0x%x [0x%x bytes] <- ram 0x%p\n", + offset, len, buf); + debug("%s(flash addr=0x%08x, ram=%p, len=0x%x)\n", + __func__, offset, buf, len); + + if (ENABLE_WRITE_STATUS(flash) != 0 || + spi_nor_write_status(flash, 0) != 0) { + printf("Error: %s: %d\n", __func__, __LINE__); + return -1; + } + + if ((d_addr & 1) != 0) { + /* program 1st byte */ + if (spi_nor_program_1byte(flash, s_buf[0], + (void *)d_addr) != 0) { + printf("Error: %s(%d)\n", __func__, __LINE__); + return -1; + } + if (--s32remain_size == 0) + return 0; + d_addr++; + s_buf++; + } + + /* need to do write-enable command */ + if (WRITE_ENABLE(flash) != 0) { + printf("Error : %d\n", __LINE__); + return -1; + } + + /* + These two bytes write will be copied to txfifo first with + g_tx_buf[1] being shifted out and followed by g_tx_buf[0]. + The reason for this is we will specify burst len=6. So SPI will + do this kind of data movement. + */ + g_tx_buf[0] = d_addr >> 16; + g_tx_buf[1] = AAI_PROG; /* need to skip bytes 1, 2 */ + /* byte shifted order is: 7, 6, 5, 4 */ + g_tx_buf[4] = s_buf[1]; + g_tx_buf[5] = s_buf[0]; + g_tx_buf[6] = d_addr; + g_tx_buf[7] = d_addr >> 8; + if (spi_xfer(flash->spi, 6 << 3, g_tx_buf, g_rx_buf, + SPI_XFER_BEGIN | SPI_XFER_END) != 0) { + printf("Error: %s(%d): failed\n", + __FILE__, __LINE__); + return -1; + } + + while (spi_nor_status(flash) & RDSR_BUSY) + ; + + for (d_addr += 2, s_buf += 2, s32remain_size -= 2; + s32remain_size > 1; + d_addr += 2, s_buf += 2, s32remain_size -= 2) { + debug("%d%% transferred\n", + ((len - s32remain_size) * 100 / len)); + /* byte shifted order is: 2,1,0 */ + g_tx_buf[2] = AAI_PROG; + g_tx_buf[1] = s_buf[0]; + g_tx_buf[0] = s_buf[1]; + + if (spi_xfer(flash->spi, 3 << 3, g_tx_buf, g_rx_buf, + SPI_XFER_BEGIN | SPI_XFER_END) != 0) { + printf("Error: %s(%d): failed\n", + __FILE__, __LINE__); + return -1; + } + + while (spi_nor_status(flash) & RDSR_BUSY) + ; + + if ((s32remain_size % imx_sf->params->block_size) == 0) + printf("."); + } + printf("SUCCESS\n\n"); + debug("100%% transferred\n"); + + WRITE_DISABLE(flash); + while (spi_nor_status(flash) & RDSR_BUSY) + ; + + if (WRITE_ENABLE(flash) != 0) { + printf("Error : %d\n", __LINE__); + return -1; + } + + if (len == 1) { + /* need to do write-enable command */ + /* only 1 byte left */ + if (spi_nor_program_1byte(flash, s_buf[0], + (void *)d_addr) != 0) { + printf("Error: %s(%d)\n", + __func__, __LINE__); + return -1; + } + } + return 0; +} + +static int spi_nor_flash_erase(struct spi_flash *flash, u32 offset, + size_t len) +{ + s32 s32remain_size = len; + + if (!(flash->spi)) + return -1; + + printf("Erasing SPI NOR flash 0x%x [0x%x bytes]\n", + offset, len); + + if ((len % SZ_4K) != 0 || len == 0) { + printf("Error: size (0x%x) is not integer multiples of 4kB(0x1000)\n", + len); + return -1; + } + if ((offset & (SZ_4K - 1)) != 0) { + printf("Error - addr is not 4kB(0x1000) aligned: 0x%08x\n", + offset); + return -1; + } + for (; s32remain_size > 0; s32remain_size -= SZ_4K, offset += SZ_4K) { + debug("Erasing 0x%08x, %d%% erased\n", + offset, + ((len - s32remain_size) * 100 / len)); + if (spi_nor_erase_block(flash, + (void *)offset, SZ_4K) != 0) { + printf("Error: spi_nor_flash_erase(): %d\n", __LINE__); + return -1; + } + printf("."); + } + printf("SUCCESS\n\n"); + debug("100%% erased\n"); + return 0; +} + +struct spi_flash *spi_flash_probe(unsigned int bus, unsigned int cs, unsigned int max_hz, unsigned int spi_mode) +{ + struct spi_slave *spi = NULL; + const struct imx_spi_flash_params *params = NULL; + struct imx_spi_flash *imx_sf = NULL; + u8 idcode[4] = { 0 }; + u32 i = 0; + s32 ret = 0; + + if (CONFIG_SPI_FLASH_CS != cs) { + printf("Invalid cs for SPI NOR.\n"); + return NULL; + } + + spi = spi_setup_slave(bus, cs, max_hz, spi_mode); + + if (!spi) { + debug("SF: Failed to set up slave\n"); + return NULL; + } + + ret = spi_claim_bus(spi); + if (ret) { + debug("SF: Failed to claim SPI bus: %d\n", ret); + goto err_claim_bus; + } + + imx_sf = (struct imx_spi_flash *)malloc(sizeof(struct imx_spi_flash)); + + if (!imx_sf) { + debug("SF: Failed to allocate memory\n"); + spi_free_slave(spi); + return NULL; + } + + imx_sf->flash.spi = spi; + + /* Read the ID codes */ + ret = spi_nor_flash_query(&(imx_sf->flash), idcode); + if (ret) + goto err_read_id; + + for (i = 0; i < ARRAY_SIZE(imx_spi_flash_table); ++i) { + params = &imx_spi_flash_table[i]; + if (params->idcode1 == idcode[1]) + break; + } + + if (i == ARRAY_SIZE(imx_spi_flash_table)) { + debug("SF: Unsupported DataFlash ID %02x\n", + idcode[1]); + + goto err_invalid_dev; + } + + imx_sf->params = params; + + imx_sf->flash.name = params->name; + imx_sf->flash.size = params->device_size; + + imx_sf->flash.read = spi_nor_flash_read; + imx_sf->flash.write = spi_nor_flash_write; + imx_sf->flash.erase = spi_nor_flash_erase; + + debug("SF: Detected %s with block size %lu, " + "block count %lu, total %u bytes\n", + params->name, + params->block_size, + params->block_count, + params->device_size); + + return &(imx_sf->flash); + +err_read_id: + spi_release_bus(spi); +err_invalid_dev: + if (imx_sf) + free(imx_sf); +err_claim_bus: + if (spi) + spi_free_slave(spi); + return NULL; +} + +void spi_flash_free(struct spi_flash *flash) +{ + struct imx_spi_flash *imx_sf = NULL; + + if (!flash) + return; + + imx_sf = to_imx_spi_flash(flash); + + if (flash->spi) { + spi_free_slave(flash->spi); + flash->spi = NULL; + } + + free(imx_sf); +} + diff --git a/drivers/mtd/spi/spi_flash_internal.h b/drivers/mtd/spi/spi_flash_internal.h index 0612383c69..c4b561cdb8 100644 --- a/drivers/mtd/spi/spi_flash_internal.h +++ b/drivers/mtd/spi/spi_flash_internal.h @@ -49,3 +49,4 @@ struct spi_flash *spi_flash_probe_atmel(struct spi_slave *spi, u8 *idcode); struct spi_flash *spi_flash_probe_macronix(struct spi_slave *spi, u8 *idcode); struct spi_flash *spi_flash_probe_sst(struct spi_slave *spi, u8 *idcode); struct spi_flash *spi_flash_probe_stmicro(struct spi_slave *spi, u8 *idcode); +struct spi_flash *spi_flash_probe_imx(struct spi_slave *spi, u8 *idcode); diff --git a/drivers/net/smc911x.c b/drivers/net/smc911x.c index 18a729cfbc..adcb9c9a8f 100644 --- a/drivers/net/smc911x.c +++ b/drivers/net/smc911x.c @@ -146,10 +146,9 @@ static void smc911x_enable(struct eth_device *dev) static int smc911x_init(struct eth_device *dev, bd_t * bd) { - printf(DRIVERNAME ": initializing\n"); + struct chip_id *id = dev->priv; - if (smc911x_detect_chip(dev)) - goto err_out; + printf(DRIVERNAME ": detected %s controller\n", id->name); smc911x_reset(dev); @@ -162,9 +161,6 @@ static int smc911x_init(struct eth_device *dev, bd_t * bd) smc911x_enable(dev); return 0; - -err_out: - return -1; } static int smc911x_send(struct eth_device *dev, @@ -224,7 +220,7 @@ static int smc911x_rx(struct eth_device *dev) smc911x_reg_write(dev, RX_CFG, 0); - tmplen = (pktlen + 2+ 3) / 4; + tmplen = (pktlen + 3) / 4; while (tmplen--) *data++ = pkt_data_pull(dev, RX_DATA_FIFO); @@ -253,6 +249,12 @@ int smc911x_initialize(u8 dev_num, int base_addr) dev->iobase = base_addr; + /* Try to detect chip. Will fail if not present. */ + if (smc911x_detect_chip(dev)) { + free(dev); + return 0; + } + addrh = smc911x_get_mac_csr(dev, ADDRH); addrl = smc911x_get_mac_csr(dev, ADDRL); dev->enetaddr[0] = addrl; diff --git a/drivers/net/smc911x.h b/drivers/net/smc911x.h index 053e33016b..02c33b3fbb 100644 --- a/drivers/net/smc911x.h +++ b/drivers/net/smc911x.h @@ -30,7 +30,8 @@ #define DRIVERNAME "smc911x" #if defined (CONFIG_SMC911X_32_BIT) && \ - defined (CONFIG_SMC911X_16_BIT) + defined (CONFIG_SMC911X_16_BIT) && \ + defined(CONFIG_SMC911X_CPLD) #error "SMC911X: Only one of CONFIG_SMC911X_32_BIT and \ CONFIG_SMC911X_16_BIT shall be set" #endif @@ -62,6 +63,19 @@ static inline void smc911x_reg_write(struct eth_device *dev, *(volatile u16 *)(dev->iobase + offset) = (u16)val; *(volatile u16 *)(dev->iobase + offset + 2) = (u16)(val >> 16); } +#elif defined(CONFIG_SMC911X_CPLD) +#include +static inline u32 smc911x_reg_read(struct eth_device *dev, u32 offset) +{ + return cpld_reg_xfer(offset, 0x0, 1) | \ + (cpld_reg_xfer(offset + 0x2, 0x0, 1) << 16); +} +static void smc911x_reg_write(struct eth_device *dev, + u32 offset, u32 val) +{ + cpld_reg_xfer(offset, val, 0); + cpld_reg_xfer(offset + 0x2, (val >> 16), 0); +} #else #error "SMC911X: undefined bus width" #endif /* CONFIG_SMC911X_16_BIT */ @@ -393,6 +407,7 @@ static inline void smc911x_reg_write(struct eth_device *dev, #define CHIP_9216 0x116a #define CHIP_9217 0x117a #define CHIP_9218 0x118a +#define CHIP_9220 0x9220 #define CHIP_9221 0x9221 struct chip_id { @@ -410,6 +425,7 @@ static const struct chip_id chip_ids[] = { { CHIP_9216, "LAN9216" }, { CHIP_9217, "LAN9217" }, { CHIP_9218, "LAN9218" }, + { CHIP_9220, "LAN9220" }, { CHIP_9221, "LAN9221" }, { 0, NULL }, }; @@ -441,7 +457,10 @@ static int smc911x_detect_chip(struct eth_device *dev) unsigned long val, i; val = smc911x_reg_read(dev, BYTE_TEST); - if (val != 0x87654321) { + if (val == 0xffffffff) { + /* Special case -- no chip present */ + return -1; + } else if (val != 0x87654321) { printf(DRIVERNAME ": Invalid chip endian 0x%08lx\n", val); return -1; } @@ -455,7 +474,7 @@ static int smc911x_detect_chip(struct eth_device *dev) return -1; } - printf(DRIVERNAME ": detected %s controller\n", chip_ids[i].name); + dev->priv = (void *)&chip_ids[i]; return 0; } diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile index 64882a2e8e..ed562696dc 100644 --- a/drivers/serial/Makefile +++ b/drivers/serial/Makefile @@ -52,6 +52,8 @@ COBJS-$(CONFIG_S3C44B0_SERIAL) += serial_s3c44b0.o COBJS-$(CONFIG_XILINX_UARTLITE) += serial_xuartlite.o COBJS-$(CONFIG_SCIF_CONSOLE) += serial_sh.o COBJS-$(CONFIG_USB_TTY) += usbtty.o +COBJS-$(CONFIG_VCTH_SERIAL) += vcth.o +COBJS-$(CONFIG_STMP3XXX_DBGUART) += stmp3xxx_dbguart.o COBJS := $(sort $(COBJS-y)) SRCS := $(COBJS:.o=.c) diff --git a/drivers/serial/stmp3xxx_dbguart.c b/drivers/serial/stmp3xxx_dbguart.c new file mode 100644 index 0000000000..1d24da85ce --- /dev/null +++ b/drivers/serial/stmp3xxx_dbguart.c @@ -0,0 +1,114 @@ +/* + * (c) 2007 Sascha Hauer + * + * (C) Copyright 2009 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ +#include + +#ifdef CONFIG_STMP3XXX_DBGUART + +#include "stmp3xxx_dbguart.h" + +DECLARE_GLOBAL_DATA_PTR; + +/* + * Set baud rate. The settings are always 8n1: + * 8 data bits, no parity, 1 stop bit + */ +void serial_setbrg(void) +{ + u32 cr, lcr_h; + u32 quot; + + /* Disable everything */ + cr = REG_RD(DBGUART_BASE + UARTDBGCR); + REG_WR(DBGUART_BASE + UARTDBGCR, 0); + + /* Calculate and set baudrate */ + quot = (CONFIG_DBGUART_CLK * 4) / gd->baudrate; + REG_WR(DBGUART_BASE + UARTDBGFBRD, quot & 0x3f); + REG_WR(DBGUART_BASE + UARTDBGIBRD, quot >> 6); + + /* Set 8n1 mode, enable FIFOs */ + lcr_h = WLEN8 | FEN; + REG_WR(DBGUART_BASE + UARTDBGLCR_H, lcr_h); + + /* Enable Debug UART */ + REG_WR(DBGUART_BASE + UARTDBGCR, cr); +} + +int serial_init(void) +{ + u32 cr; + + /* Disable UART */ + REG_WR(DBGUART_BASE + UARTDBGCR, 0); + + /* Mask interrupts */ + REG_WR(DBGUART_BASE + UARTDBGIMSC, 0); + + /* Set default baudrate */ + serial_setbrg(); + + /* Enable UART */ + cr = TXE | RXE | UARTEN; + REG_WR(DBGUART_BASE + UARTDBGCR, cr); + + return 0; +} + +/* Send a character */ +void serial_putc(const char c) +{ + /* Wait for room in TX FIFO */ + while (REG_RD(DBGUART_BASE + UARTDBGFR) & TXFF) + ; + + /* Write the data byte */ + REG_WR(DBGUART_BASE + UARTDBGDR, c); + + if (c == '\n') + serial_putc('\r'); +} + +void serial_puts(const char *s) +{ + while (*s) { + serial_putc(*s++); + } +} + +/* Test whether a character is in TX buffer */ +int serial_tstc(void) +{ + /* Check if RX FIFO is not empty */ + return !(REG_RD(DBGUART_BASE + UARTDBGFR) & RXFE); +} + +/* Receive character */ +int serial_getc(void) +{ + /* Wait while TX FIFO is empty */ + while (REG_RD(DBGUART_BASE + UARTDBGFR) & RXFE) + ; + + /* Read data byte */ + return REG_RD(DBGUART_BASE + UARTDBGDR) & 0xff; +} + +#endif /* CONFIG_STMP378X_DBGUART */ diff --git a/drivers/serial/stmp3xxx_dbguart.h b/drivers/serial/stmp3xxx_dbguart.h new file mode 100644 index 0000000000..5ad4a8580f --- /dev/null +++ b/drivers/serial/stmp3xxx_dbguart.h @@ -0,0 +1,61 @@ +/* + * Debug UART register definitions + * (C) Copyright 2009 Freescale Semiconductor, Inc. + */ + +#ifndef STMP3XXX_DBGUART_H +#define STMP3XXX_DBGUART_H + +#include + +#define UARTDBGDR 0x00 +#define UARTDBGRSR_ECR 0x04 +#define UARTDBGFR 0x18 +#define UARTDBGILPR 0x20 +#define UARTDBGIBRD 0x24 +#define UARTDBGFBRD 0x28 +#define UARTDBGLCR_H 0x2c +#define UARTDBGCR 0x30 +#define UARTDBGIFLS 0x34 +#define UARTDBGIMSC 0x38 +#define UARTDBGRIS 0x3c +#define UARTDBGMIS 0x40 +#define UARTDBGICR 0x44 +#define UARTDBGDMACR 0x48 + +/* UARTDBGFR - Flag Register bits */ +#define CTS 0x0001 +#define DSR 0x0002 +#define DCD 0x0004 +#define BUSY 0x0008 +#define RXFE 0x0010 +#define TXFF 0x0020 +#define RXFF 0x0040 +#define TXFE 0x0080 +#define RI 0x0100 + +/* UARTDBGLCR_H - Line Control Register bits */ +#define BRK 0x0001 +#define PEN 0x0002 +#define EPS 0x0004 +#define STP2 0x0008 +#define FEN 0x0010 +#define WLEN5 0x0000 +#define WLEN6 0x0020 +#define WLEN7 0x0040 +#define WLEN8 0x0060 +#define SPS 0x0080 + +/* UARTDBGCR - Control Register bits */ +#define UARTEN 0x0001 +#define LBE 0x0080 +#define TXE 0x0100 +#define RXE 0x0200 +#define DTR 0x0400 +#define RTS 0x0800 +#define OUT1 0x1000 +#define OUT2 0x2000 +#define RTSEN 0x4000 +#define CTSEN 0x8000 + +#endif /* STMP3XXX_DBGUART_H */ diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index 824d8e740c..d8a1675a3b 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -34,6 +34,10 @@ COBJS-$(CONFIG_MPC52XX_SPI) += mpc52xx_spi.o COBJS-$(CONFIG_MPC8XXX_SPI) += mpc8xxx_spi.o COBJS-$(CONFIG_MXC_SPI) += mxc_spi.o COBJS-$(CONFIG_SOFT_SPI) += soft_spi.o +COBJS-$(CONFIG_IMX_ECSPI) += imx_ecspi.o +COBJS-$(CONFIG_IMX_CSPI) += imx_cspi.o +COBJS-$(CONFIG_IMX_SPI_PMIC) += imx_spi_pmic.o +COBJS-$(CONFIG_IMX_SPI_CPLD) += imx_spi_cpld.o COBJS := $(COBJS-y) SRCS := $(COBJS:.o=.c) diff --git a/drivers/spi/imx_cspi.c b/drivers/spi/imx_cspi.c new file mode 100644 index 0000000000..438ab8df5a --- /dev/null +++ b/drivers/spi/imx_cspi.c @@ -0,0 +1,255 @@ +/* + * (C) Copyright 2008-2010 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include + +#include + +extern s32 spi_get_cfg(struct imx_spi_dev_t *dev); + +static inline struct imx_spi_dev_t *to_imx_spi_slave(struct spi_slave *slave) +{ + return container_of(slave, struct imx_spi_dev_t, slave); +} + +static s32 spi_reset(struct spi_slave *slave) +{ + u32 clk_src = mxc_get_clock(MXC_CSPI_CLK); + s32 div = 0, i, reg_ctrl; + struct imx_spi_dev_t *dev = to_imx_spi_slave(slave); + struct spi_reg_t *reg = &(dev->reg); + int lim = 0; + unsigned int baud_rate_div[] = { 4, 8, 16, 32, 64, 128, 256, 512 }; + + if (dev->freq == 0) { + printf("Error: desired clock is 0\n"); + return 1; + } + + reg_ctrl = readl(dev->base + SPI_CON_REG); + /* Reset spi */ + writel(0, dev->base + SPI_CON_REG); + writel((reg_ctrl | SPI_CTRL_EN), dev->base + SPI_CON_REG); + + lim = sizeof(baud_rate_div) / sizeof(unsigned int); + if (clk_src > dev->freq) { + div = clk_src / dev->freq; + + for (i = 0; i < lim; i++) { + if (div <= baud_rate_div[i]) + break; + } + } + debug("div = %d\n", baud_rate_div[i]); + + reg_ctrl = + (reg_ctrl & ~SPI_CTRL_SS_MASK) | (dev->ss << SPI_CTRL_SS_OFF); + reg_ctrl = (reg_ctrl & ~SPI_CTRL_DATA_MASK) | (i << SPI_CTRL_DATA_OFF); + reg_ctrl |= SPI_CTRL_MODE; /* always set to master mode !!!! */ + reg_ctrl &= ~SPI_CTRL_EN; /* disable spi */ + + /* configuration register setup */ + reg_ctrl = + (reg_ctrl & ~SPI_CTRL_SSPOL) | (dev->ss_pol << SPI_CTRL_SSPOL_OFF); + reg_ctrl = + (reg_ctrl & ~SPI_CTRL_SSCTL) | (dev->ssctl << SPI_CTRL_SSCTL_OFF); + reg_ctrl = + (reg_ctrl & ~SPI_CTRL_SCLK_POL) | (dev-> + sclkpol << + SPI_CTRL_SCLK_POL_OFF); + reg_ctrl = + (reg_ctrl & ~SPI_CTRL_SCLK_PHA) | (dev-> + sclkpha << + SPI_CTRL_SCLK_PHA_OFF); + + debug("reg_ctrl = 0x%x\n", reg_ctrl); + writel(reg_ctrl, dev->base + SPI_CON_REG); + /* save control register */ + reg->ctrl_reg = reg_ctrl; + + /* clear interrupt reg */ + writel(0, dev->base + SPI_INT_REG); + writel(SPI_INT_STAT_TC, dev->base + SPI_STAT_REG); + + return 0; +} + +void spi_init(void) +{ +} + +struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, + unsigned int max_hz, unsigned int mode) +{ + struct imx_spi_dev_t *imx_spi_slave = NULL; + + if (!spi_cs_is_valid(bus, cs)) + return NULL; + + imx_spi_slave = + (struct imx_spi_dev_t *)malloc(sizeof(struct imx_spi_dev_t)); + if (!imx_spi_slave) + return NULL; + + imx_spi_slave->slave.bus = bus; + imx_spi_slave->slave.cs = cs; + + spi_get_cfg(imx_spi_slave); + + spi_io_init(imx_spi_slave); + + spi_reset(&(imx_spi_slave->slave)); + + return &(imx_spi_slave->slave); +} + +void spi_free_slave(struct spi_slave *slave) +{ + struct imx_spi_dev_t *imx_spi_slave; + + if (slave) { + imx_spi_slave = to_imx_spi_slave(slave); + free(imx_spi_slave); + } +} + +int spi_claim_bus(struct spi_slave *slave) +{ + return 0; +} + +void spi_release_bus(struct spi_slave *slave) +{ + +} + +/* + * SPI transfer: + * + * See include/spi.h and http://www.altera.com/literature/ds/ds_nios_spi.pdf + * for more informations. + */ +int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, + void *din, unsigned long flags) +{ + s32 val = SPI_RETRY_TIMES; + u32 *p_buf; + u32 reg; + s32 len = 0, ret_val = 0; + s32 burst_bytes = bitlen >> 3; + struct imx_spi_dev_t *dev = to_imx_spi_slave(slave); + struct spi_reg_t *spi_reg = &(dev->reg); + + if (!slave) + return -1; + + if ((bitlen % 8) != 0) + burst_bytes++; + + if (burst_bytes > (dev->fifo_sz)) { + printf("Error: maximum burst size is 0x%x bytes, asking 0x%x\n", + dev->fifo_sz, burst_bytes); + return -1; + } + + if (flags & SPI_XFER_BEGIN) { + spi_cs_activate(slave); + + if (spi_reg->ctrl_reg == 0) { + printf + ("Error: spi(base=0x%x) has not been initialized\n", + dev->base); + return -1; + } + + spi_reg->ctrl_reg = (spi_reg->ctrl_reg & ~SPI_CTRL_BURST_MASK) | + ((bitlen - 1) << SPI_CTRL_BURST_OFF); + writel(spi_reg->ctrl_reg | SPI_CTRL_EN, + dev->base + SPI_CON_REG); + debug("ctrl_reg=0x%x\n", readl(dev->base + SPI_CON_REG)); + + /* move data to the tx fifo */ + if (dout) { + for (p_buf = (u32 *) dout, len = burst_bytes; len > 0; + p_buf++, len -= 4) + writel(*p_buf, dev->base + SPI_TX_DATA); + } + + reg = readl(dev->base + SPI_CON_REG); + reg |= SPI_CTRL_REG_XCH_BIT; /* set xch bit */ + debug("control reg = 0x%08x\n", reg); + writel(reg, dev->base + SPI_CON_REG); + + /* poll on the TC bit (transfer complete) */ + while ((val-- > 0) && + (((reg = + readl(dev->base + SPI_STAT_REG)) & SPI_INT_STAT_TC) == + 0)); + + /* clear the TC bit */ + writel(reg | SPI_INT_STAT_TC, dev->base + SPI_STAT_REG); + if (val <= 0) { + printf + ("Error: re-tried %d times without response. Give up\n", + SPI_RETRY_TIMES); + ret_val = -1; + goto error; + } + } + + /* move data in the rx buf */ + if (flags & SPI_XFER_END) { + if (din) { + for (p_buf = (u32 *) din, len = burst_bytes; len > 0; + p_buf++, len -= 4) + *p_buf = readl(dev->base + SPI_RX_DATA); + } + } +error: + spi_cs_deactivate(slave); + return ret_val; +} + +int spi_cs_is_valid(unsigned int bus, unsigned int cs) +{ + return 1; +} + +void spi_cs_activate(struct spi_slave *slave) +{ + struct imx_spi_dev_t *dev = to_imx_spi_slave(slave); + + spi_io_init(dev); +} + +void spi_cs_deactivate(struct spi_slave *slave) +{ + struct imx_spi_dev_t *dev = to_imx_spi_slave(slave); + + writel(0, dev->base + SPI_CON_REG); +} diff --git a/drivers/spi/imx_ecspi.c b/drivers/spi/imx_ecspi.c new file mode 100644 index 0000000000..1e86cf1fae --- /dev/null +++ b/drivers/spi/imx_ecspi.c @@ -0,0 +1,302 @@ +/* + * (C) Copyright 2008-2010 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include + +#include + +#ifdef DEBUG + +/* ----------------------------------------------- + * Helper functions to peek into tx and rx buffers + * ----------------------------------------------- */ +static const char * const hex_digit = "0123456789ABCDEF"; + +static char quickhex(int i) +{ + return hex_digit[i]; +} + +static void memdump(const void *pv, int num) +{ + +} + +#else /* !DEBUG */ + +#define memdump(p, n) + +#endif /* DEBUG */ + +extern s32 spi_get_cfg(struct imx_spi_dev_t *dev); + +static inline struct imx_spi_dev_t *to_imx_spi_slave(struct spi_slave *slave) +{ + return container_of(slave, struct imx_spi_dev_t, slave); +} + +static s32 spi_reset(struct spi_slave *slave) +{ + u32 clk_src = mxc_get_clock(MXC_CSPI_CLK); + s32 pre_div = 0, post_div = 0, i, reg_ctrl, reg_config; + struct imx_spi_dev_t *dev = to_imx_spi_slave(slave); + struct spi_reg_t *reg = &(dev->reg); + + if (dev->freq == 0) { + printf("Error: desired clock is 0\n"); + return 1; + } + + reg_ctrl = readl(dev->base + SPI_CON_REG); + /* Reset spi */ + writel(0, dev->base + SPI_CON_REG); + writel((reg_ctrl | 0x1), dev->base + SPI_CON_REG); + + /* Control register setup */ + if (clk_src > dev->freq) { + pre_div = clk_src / dev->freq; + if (pre_div > 16) { + post_div = pre_div / 16; + pre_div = 15; + } + if (post_div != 0) { + for (i = 0; i < 16; i++) { + if ((1 << i) >= post_div) + break; + } + if (i == 16) { + printf("Error: no divider can meet the freq: %d\n", + dev->freq); + return -1; + } + post_div = i; + } + } + + debug("pre_div = %d, post_div=%d\n", pre_div, post_div); + reg_ctrl = (reg_ctrl & ~(3 << 18)) | dev->ss << 18; + reg_ctrl = (reg_ctrl & ~(0xF << 12)) | pre_div << 12; + reg_ctrl = (reg_ctrl & ~(0xF << 8)) | post_div << 8; + reg_ctrl |= 1 << (dev->ss + 4); /* always set to master mode !!!! */ + reg_ctrl &= ~0x1; /* disable spi */ + + reg_config = readl(dev->base + SPI_CFG_REG); + /* configuration register setup */ + reg_config = (reg_config & ~(1 << ((dev->ss + 12)))) | + (dev->ss_pol << (dev->ss + 12)); + reg_config = (reg_config & ~(1 << ((dev->ss + 20)))) | + (dev->in_sctl << (dev->ss + 20)); + reg_config = (reg_config & ~(1 << ((dev->ss + 16)))) | + (dev->in_dctl << (dev->ss + 16)); + reg_config = (reg_config & ~(1 << ((dev->ss + 8)))) | + (dev->ssctl << (dev->ss + 8)); + reg_config = (reg_config & ~(1 << ((dev->ss + 4)))) | + (dev->sclkpol << (dev->ss + 4)); + reg_config = (reg_config & ~(1 << ((dev->ss + 0)))) | + (dev->sclkpha << (dev->ss + 0)); + + debug("reg_ctrl = 0x%x\n", reg_ctrl); + writel(reg_ctrl, dev->base + SPI_CON_REG); + debug("reg_config = 0x%x\n", reg_config); + writel(reg_config, dev->base + SPI_CFG_REG); + + /* save config register and control register */ + reg->cfg_reg = reg_config; + reg->ctrl_reg = reg_ctrl; + + /* clear interrupt reg */ + writel(0, dev->base + SPI_INT_REG); + writel(3 << 6, dev->base + SPI_STAT_REG); + + return 0; +} + +void spi_init(void) +{ +} + +struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, + unsigned int max_hz, unsigned int mode) +{ + struct imx_spi_dev_t *imx_spi_slave = NULL; + + if (!spi_cs_is_valid(bus, cs)) + return NULL; + + imx_spi_slave = (struct imx_spi_dev_t *)malloc(sizeof(struct imx_spi_dev_t)); + if (!imx_spi_slave) + return NULL; + + imx_spi_slave->slave.bus = bus; + imx_spi_slave->slave.cs = cs; + + spi_get_cfg(imx_spi_slave); + + spi_io_init(imx_spi_slave); + + spi_reset(&(imx_spi_slave->slave)); + + return &(imx_spi_slave->slave); +} + +void spi_free_slave(struct spi_slave *slave) +{ + struct imx_spi_dev_t *imx_spi_slave; + + if (slave) { + imx_spi_slave = to_imx_spi_slave(slave); + free(imx_spi_slave); + } +} + +int spi_claim_bus(struct spi_slave *slave) +{ + return 0; +} + +void spi_release_bus(struct spi_slave *slave) +{ + +} + +/* + * SPI transfer: + * + * See include/spi.h and http://www.altera.com/literature/ds/ds_nios_spi.pdf + * for more informations. + */ +int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, + void *din, unsigned long flags) +{ + s32 val = SPI_RETRY_TIMES; + u32 *p_buf; + u32 reg; + s32 len = 0, + ret_val = 0; + s32 burst_bytes = bitlen >> 3; + s32 tmp = 0; + struct imx_spi_dev_t *dev = to_imx_spi_slave(slave); + struct spi_reg_t *spi_reg = &(dev->reg); + + if (!slave) + return -1; + + if (burst_bytes > (MAX_SPI_BYTES)) { + printf("Error: maximum burst size is 0x%x bytes, asking 0x%x\n", + MAX_SPI_BYTES, burst_bytes); + return -1; + } + + if (flags & SPI_XFER_BEGIN) { + spi_cs_activate(slave); + + if (spi_reg->ctrl_reg == 0) { + printf("Error: spi(base=0x%x) has not been initialized yet\n", + dev->base); + return -1; + } + spi_reg->ctrl_reg = (spi_reg->ctrl_reg & ~0xFFF00000) | \ + ((burst_bytes * 8 - 1) << 20); + + writel(spi_reg->ctrl_reg | 0x1, dev->base + SPI_CON_REG); + writel(spi_reg->cfg_reg, dev->base + SPI_CFG_REG); + debug("ctrl_reg=0x%x, cfg_reg=0x%x\n", + readl(dev->base + SPI_CON_REG), + readl(dev->base + SPI_CFG_REG)); + + /* move data to the tx fifo */ + if (dout) { + for (p_buf = (u32 *)dout, len = burst_bytes; len > 0; + p_buf++, len -= 4) + writel(*p_buf, dev->base + SPI_TX_DATA); + } else { + for (len = burst_bytes; len > 0; len -= 4) + writel(tmp, dev->base + SPI_TX_DATA); + } + + reg = readl(dev->base + SPI_CON_REG); + reg |= (1 << 2); /* set xch bit */ + debug("control reg = 0x%08x\n", reg); + writel(reg, dev->base + SPI_CON_REG); + + /* poll on the TC bit (transfer complete) */ + while ((val-- > 0) && + (readl(dev->base + SPI_STAT_REG) & (1 << 7)) == 0) { + udelay(100); + } + + /* clear the TC bit */ + writel(3 << 6, dev->base + SPI_STAT_REG); + if (val <= 0) { + printf("Error: re-tried %d times without response. Give up\n", + SPI_RETRY_TIMES); + ret_val = -1; + goto error; + } + } + + /* move data in the rx buf */ + if (flags & SPI_XFER_END) { + if (din) { + for (p_buf = (u32 *)din, len = burst_bytes; len > 0; + ++p_buf, len -= 4) + *p_buf = readl(dev->base + SPI_RX_DATA); + } else { + for (len = burst_bytes; len > 0; len -= 4) + tmp = readl(dev->base + SPI_RX_DATA); + } + + spi_cs_deactivate(slave); + } + + return ret_val; + +error: + spi_cs_deactivate(slave); + return ret_val; +} + +int spi_cs_is_valid(unsigned int bus, unsigned int cs) +{ + return 1; +} + +void spi_cs_activate(struct spi_slave *slave) +{ + struct imx_spi_dev_t *dev = to_imx_spi_slave(slave); + + spi_io_init(dev); +} + +void spi_cs_deactivate(struct spi_slave *slave) +{ + struct imx_spi_dev_t *dev = to_imx_spi_slave(slave); + + writel(0, dev->base + SPI_CON_REG); +} + diff --git a/drivers/spi/imx_spi_cpld.c b/drivers/spi/imx_spi_cpld.c new file mode 100644 index 0000000000..6e1e556749 --- /dev/null +++ b/drivers/spi/imx_spi_cpld.c @@ -0,0 +1,118 @@ +/* + * (C) Copyright 2009 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include + +#include +#include + +static struct spi_slave *cpld_slave; + +void cpld_reg_write(u32 offset, u32 val) +{ + cpld_reg_xfer(offset, val, 0); + cpld_reg_xfer(offset + 0x2, (val >> 16), 0); +} + +u32 cpld_reg_read(u32 offset) +{ + return cpld_reg_xfer(offset, 0x0, 1) | \ + (cpld_reg_xfer(offset + 0x2, 0x0, 1) << 16); +} + +/*! + * To read/write to a CPLD register. + * + * @param reg register number inside the CPLD + * @param val data to be written to the register; don't care for read + * @param read 0 for write; 1 for read + * + * @return the actual data in the CPLD register + */ +unsigned int cpld_reg_xfer(unsigned int reg, unsigned int val, + unsigned int read) +{ + unsigned int local_val1, local_val2; + unsigned int g_tx_buf[2], g_rx_buf[2]; + + reg >>= 1; + + local_val1 = (read << 13) | ((reg & 0x0001FFFF) >> 5) | 0x00001000; + if (read) + local_val2 = (((reg & 0x0000001F) << 27) | 0x0200001f); + else + local_val2 = + (((reg & 0x0000001F) << 27) | ((val & 0x0000FFFF) << 6) | + 0x03C00027); + + *g_tx_buf = local_val1; + *(g_tx_buf + 1) = local_val2; + + if (read) { + if (spi_xfer(cpld_slave, 46, (u8 *) g_tx_buf, (u8 *) g_rx_buf, + SPI_XFER_BEGIN | SPI_XFER_END)) { + return -1; + } + } else { + if (spi_xfer(cpld_slave, 46, (u8 *) g_tx_buf, (u8 *) g_rx_buf, + SPI_XFER_BEGIN)) { + return -1; + } + } + return ((*(g_rx_buf + 1)) >> 6) & 0xffff; +} + +struct spi_slave *spi_cpld_probe() +{ + u32 reg; + cpld_slave = spi_setup_slave(0, 0, 25000000, 0); + + udelay(1000); + + /* Reset interrupt status reg */ + cpld_reg_write(PBC_INT_REST, 0x1F); + cpld_reg_write(PBC_INT_REST, 0); + cpld_reg_write(PBC_INT_MASK, 0xFFFF); + /* Reset the XUART and Ethernet controllers */ + reg = cpld_reg_read(PBC_SW_RESET); + reg |= 0x9; + cpld_reg_write(PBC_SW_RESET, reg); + reg &= ~0x9; + cpld_reg_write(PBC_SW_RESET, reg); + + return cpld_slave; +} + +void mxc_cpld_spi_init(void) +{ + spi_cpld_probe(); +} + +void spi_cpld_free(struct spi_slave *slave) +{ + if (slave) + spi_free_slave(slave); +} diff --git a/drivers/spi/imx_spi_pmic.c b/drivers/spi/imx_spi_pmic.c new file mode 100644 index 0000000000..ec32277dfd --- /dev/null +++ b/drivers/spi/imx_spi_pmic.c @@ -0,0 +1,131 @@ +/* + * (C) Copyright 2008-2009 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include + +#include + +static u32 pmic_tx, pmic_rx; + +/*! + * To read/write to a PMIC register. For write, it does another read for the + * actual register value. + * + * @param reg register number inside the PMIC + * @param val data to be written to the register; don't care for read + * @param write 0 for read; 1 for write + * + * @return the actual data in the PMIC register + */ +u32 pmic_reg(struct spi_slave *slave, u32 reg, u32 val, u32 write) +{ + if (!slave) + return 0; + + if (reg > 63 || write > 1) { + printf(" = %d is invalide. Should be less then 63\n", + reg); + return 0; + } + pmic_tx = (write << 31) | (reg << 25) | (val & 0x00FFFFFF); + debug("reg=0x%x, val=0x%08x\n", reg, pmic_tx); + + if (spi_xfer(slave, 4 << 3, (u8 *)&pmic_tx, (u8 *)&pmic_rx, + SPI_XFER_BEGIN | SPI_XFER_END)) { + return -1; + } + + if (write) { + pmic_tx &= ~(1 << 31); + if (spi_xfer(slave, 4 << 3, (u8 *)&pmic_tx, (u8 *)&pmic_rx, + SPI_XFER_BEGIN | SPI_XFER_END)) { + return -1; + } + } + + return pmic_rx; +} + +void show_pmic_info(struct spi_slave *slave) +{ + volatile u32 rev_id; + + if (!slave) + return; + + rev_id = pmic_reg(slave, 7, 0, 0); + debug("PMIC ID: 0x%08x [Rev: ", rev_id); + switch (rev_id & 0x1F) { + case 0x1: + printf("1.0"); + break; + case 0x9: + printf("1.1"); + break; + case 0xA: + printf("1.2"); + break; + case 0x10: + printf("2.0"); + break; + case 0x11: + printf("2.1"); + break; + case 0x18: + printf("3.0"); + break; + case 0x19: + printf("3.1"); + break; + case 0x1A: + printf("3.2"); + break; + case 0x2: + printf("3.2A"); + break; + case 0x1B: + printf("3.3"); + break; + case 0x1D: + printf("3.5"); + break; + default: + printf("unknown"); + break; + } + printf("]\n"); +} + +struct spi_slave *spi_pmic_probe(void) +{ + return spi_setup_slave(0, CONFIG_IMX_SPI_PMIC_CS, 2500000, 0); +} + +void spi_pmic_free(struct spi_slave *slave) +{ + if (slave) + spi_free_slave(slave); +} diff --git a/drivers/video/Makefile b/drivers/video/Makefile index bb6b5a0d51..cb57f8a3df 100644 --- a/drivers/video/Makefile +++ b/drivers/video/Makefile @@ -28,6 +28,8 @@ LIB := $(obj)libvideo.a COBJS-$(CONFIG_ATI_RADEON_FB) += ati_radeon_fb.o COBJS-$(CONFIG_ATMEL_LCD) += atmel_lcdfb.o COBJS-$(CONFIG_CFB_CONSOLE) += cfb_console.o +COBJS-$(CONFIG_MXC2_LCD) += mx2fb.o +COBJS-$(CONFIG_MXC_EPDC) += mxc_epdc_fb.o COBJS-$(CONFIG_S6E63D6) += s6e63d6.o COBJS-$(CONFIG_VIDEO_CT69000) += ct69000.o COBJS-$(CONFIG_VIDEO_MB862xx) += mb862xx.o diff --git a/drivers/video/mx2fb.c b/drivers/video/mx2fb.c new file mode 100644 index 0000000000..35d1e000b9 --- /dev/null +++ b/drivers/video/mx2fb.c @@ -0,0 +1,125 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. + * + * Configuration settings for the MX53-EVK Freescale board. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +void *lcd_base; /* Start of framebuffer memory */ +void *lcd_console_address; /* Start of console buffer */ + +int lcd_line_length; +int lcd_color_fg; +int lcd_color_bg; + +short console_col; +short console_row; + + +void lcd_initcolregs(void) +{ +} + +void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue) +{ +} + +void lcd_enable(void) +{ +} + +void lcd_disable(void) +{ +} + +void lcd_panel_disable(void) +{ +} + +void lcd_ctrl_init(void *lcdbase) +{ + u32 ccm_ipg_cg, pcr; + + /* LSSAR */ + writel(gd->fb_base, LCDC_BASE + 0x00); + /* LSR = x << 20 + y */ + writel(((panel_info.vl_col >> 4) << 20) + panel_info.vl_row, + LCDC_BASE + 0x04); + /* LVPWR = x_res * 2 / 2 */ + writel(panel_info.vl_col / 2, LCDC_BASE + 0x08); + /* LPCR = To be fixed using Linux BSP Value for now */ + switch (panel_info.vl_bpix) { + /* bpix = 4 (16bpp) */ + case 4: + pcr = LCDC_LPCR | (0x5 << 25); + break; + default: + pcr = LCDC_LPCR; + break; + } + + pcr |= (panel_info.vl_sync & FB_SYNC_CLK_LAT_FALL) ? 0x00200000 : 0; + pcr |= (panel_info.vl_sync & FB_SYNC_DATA_INVERT) ? 0x01000000 : 0; + pcr |= (panel_info.vl_sync & FB_SYNC_SHARP_MODE) ? 0x00000040 : 0; + pcr |= (panel_info.vl_sync & FB_SYNC_OE_LOW_ACT) ? 0x00100000 : 0; + + pcr |= LCDC_LPCR_PCD; + + writel(pcr, LCDC_BASE + 0x18); + /* LHCR = H Pulse width, Right and Left Margins */ + writel(((panel_info.vl_hsync - 1) << 26) + \ + ((panel_info.vl_right_margin - 1) << 8) + \ + (panel_info.vl_left_margin - 3), + LCDC_BASE + 0x1c); + /* LVCR = V Pulse width, lower and upper margins */ + writel((panel_info.vl_vsync << 26) + \ + (panel_info.vl_lower_margin << 8) + \ + (panel_info.vl_upper_margin), + LCDC_BASE + 0x20); + /* LSCR */ + writel(LCDC_LSCR, LCDC_BASE + 0x28); + /* LRMCR */ + writel(LCDC_LRMCR, LCDC_BASE + 0x34); + /* LDCR */ + writel(LCDC_LDCR, LCDC_BASE + 0x30); + /* LPCCR = PWM */ + writel(LCDC_LPCCR, LCDC_BASE + 0x2c); + + /* On and off clock gating */ + ccm_ipg_cg = readl(CCM_BASE + 0x10); + + writel(ccm_ipg_cg&0xDFFFFFFF, CCM_BASE + 0x10); + writel(ccm_ipg_cg|0x20000000, CCM_BASE + 0x10); +} + +ulong calc_fbsize(void) +{ + return panel_info.vl_row * panel_info.vl_col * 2 \ + * NBITS(panel_info.vl_bpix) / 8; +} + + diff --git a/drivers/video/mxc_epdc_fb.c b/drivers/video/mxc_epdc_fb.c new file mode 100644 index 0000000000..6430cc95d0 --- /dev/null +++ b/drivers/video/mxc_epdc_fb.c @@ -0,0 +1,446 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ +/* + * Based on STMP378X LCDIF + * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. + */ + +#include +#include +#include +#include +#include +#include + +#include "mxc_epdc_fb.h" + + +extern int setup_waveform_file(); +extern void epdc_power_on(); +extern void epdc_power_off(); + +DECLARE_GLOBAL_DATA_PTR; + +void *lcd_base; /* Start of framebuffer memory */ +void *lcd_console_address; /* Start of console buffer */ + +int lcd_line_length; +int lcd_color_fg; +int lcd_color_bg; + +short console_col; +short console_row; + +void lcd_initcolregs(void) +{ +} + +void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue) +{ +} + +#define TEMP_USE_DEFAULT 8 + +#define UPDATE_MODE_PARTIAL 0x0 +#define UPDATE_MODE_FULL 0x1 + +#define TRUE 1 +#define FALSE 0 + +#define msleep(a) udelay(a * 1000) + + +/******************************************************** + * Start Low-Level EPDC Functions + ********************************************************/ + +static inline void epdc_set_screen_res(u32 width, u32 height) +{ + u32 val = (height << EPDC_RES_VERTICAL_OFFSET) | width; + + REG_WR(EPDC_BASE, EPDC_RES, val); +} + +static inline void epdc_set_update_coord(u32 x, u32 y) +{ + u32 val = (y << EPDC_UPD_CORD_YCORD_OFFSET) | x; + + REG_WR(EPDC_BASE, EPDC_UPD_CORD, val); +} + +static inline void epdc_set_update_dimensions(u32 width, u32 height) +{ + u32 val = (height << EPDC_UPD_SIZE_HEIGHT_OFFSET) | width; + + REG_WR(EPDC_BASE, EPDC_UPD_SIZE, val); +} + +static void epdc_submit_update(u32 lut_num, u32 waveform_mode, u32 update_mode, + int use_test_mode, u32 np_val) +{ + u32 reg_val = 0; + + if (use_test_mode) { + reg_val |= + ((np_val << EPDC_UPD_FIXED_FIXNP_OFFSET) & + EPDC_UPD_FIXED_FIXNP_MASK) | EPDC_UPD_FIXED_FIXNP_EN; + + REG_WR(EPDC_BASE, EPDC_UPD_FIXED, reg_val); + + reg_val = EPDC_UPD_CTRL_USE_FIXED; + } else { + REG_WR(EPDC_BASE, EPDC_UPD_FIXED, reg_val); + } + + reg_val |= + ((lut_num << EPDC_UPD_CTRL_LUT_SEL_OFFSET) & + EPDC_UPD_CTRL_LUT_SEL_MASK) | + ((waveform_mode << EPDC_UPD_CTRL_WAVEFORM_MODE_OFFSET) & + EPDC_UPD_CTRL_WAVEFORM_MODE_MASK) | + update_mode; + + REG_WR(EPDC_BASE, EPDC_UPD_CTRL, reg_val); +} + +static inline int epdc_is_lut_active(u32 lut_num) +{ + u32 val = REG_RD(EPDC_BASE, EPDC_STATUS_LUTS); + int is_active = val & (1 << lut_num) ? TRUE : FALSE; + + return is_active; +} + +static void epdc_set_horizontal_timing(u32 horiz_start, u32 horiz_end, + u32 hsync_width, u32 hsync_line_length) +{ + u32 reg_val = + ((hsync_width << EPDC_TCE_HSCAN1_LINE_SYNC_WIDTH_OFFSET) & + EPDC_TCE_HSCAN1_LINE_SYNC_WIDTH_MASK) + | ((hsync_line_length << EPDC_TCE_HSCAN1_LINE_SYNC_OFFSET) & + EPDC_TCE_HSCAN1_LINE_SYNC_MASK); + REG_WR(EPDC_BASE, EPDC_TCE_HSCAN1, reg_val); + + reg_val = + ((horiz_start << EPDC_TCE_HSCAN2_LINE_BEGIN_OFFSET) & + EPDC_TCE_HSCAN2_LINE_BEGIN_MASK) + | ((horiz_end << EPDC_TCE_HSCAN2_LINE_END_OFFSET) & + EPDC_TCE_HSCAN2_LINE_END_MASK); + REG_WR(EPDC_BASE, EPDC_TCE_HSCAN2, reg_val); +} + +static void epdc_set_vertical_timing(u32 vert_start, u32 vert_end, + u32 vsync_width) +{ + u32 reg_val = + ((vert_start << EPDC_TCE_VSCAN_FRAME_BEGIN_OFFSET) & + EPDC_TCE_VSCAN_FRAME_BEGIN_MASK) + | ((vert_end << EPDC_TCE_VSCAN_FRAME_END_OFFSET) & + EPDC_TCE_VSCAN_FRAME_END_MASK) + | ((vsync_width << EPDC_TCE_VSCAN_FRAME_SYNC_OFFSET) & + EPDC_TCE_VSCAN_FRAME_SYNC_MASK); + REG_WR(EPDC_BASE, EPDC_TCE_VSCAN, reg_val); +} + +static void epdc_init_settings(void) +{ + u32 reg_val; + + /* EPDC_CTRL */ + reg_val = REG_RD(EPDC_BASE, EPDC_CTRL); + reg_val &= ~EPDC_CTRL_UPD_DATA_SWIZZLE_MASK; + reg_val |= EPDC_CTRL_UPD_DATA_SWIZZLE_NO_SWAP; + reg_val &= ~EPDC_CTRL_LUT_DATA_SWIZZLE_MASK; + reg_val |= EPDC_CTRL_LUT_DATA_SWIZZLE_NO_SWAP; + REG_SET(EPDC_BASE, EPDC_CTRL, reg_val); + + /* EPDC_FORMAT - 2bit TFT and 4bit Buf pixel format */ + reg_val = EPDC_FORMAT_TFT_PIXEL_FORMAT_2BIT + | EPDC_FORMAT_BUF_PIXEL_FORMAT_P4N + | ((0x0 << EPDC_FORMAT_DEFAULT_TFT_PIXEL_OFFSET) & + EPDC_FORMAT_DEFAULT_TFT_PIXEL_MASK); + REG_WR(EPDC_BASE, EPDC_FORMAT, reg_val); + + /* EPDC_FIFOCTRL (disabled) */ + reg_val = + ((100 << EPDC_FIFOCTRL_FIFO_INIT_LEVEL_OFFSET) & + EPDC_FIFOCTRL_FIFO_INIT_LEVEL_MASK) + | ((200 << EPDC_FIFOCTRL_FIFO_H_LEVEL_OFFSET) & + EPDC_FIFOCTRL_FIFO_H_LEVEL_MASK) + | ((100 << EPDC_FIFOCTRL_FIFO_L_LEVEL_OFFSET) & + EPDC_FIFOCTRL_FIFO_L_LEVEL_MASK); + REG_WR(EPDC_BASE, EPDC_FIFOCTRL, reg_val); + + /* EPDC_TEMP - Use default temperature */ + REG_WR(EPDC_BASE, EPDC_TEMP, TEMP_USE_DEFAULT); + + /* EPDC_RES */ + epdc_set_screen_res(panel_info.vl_col, panel_info.vl_row); + + /* + * EPDC_TCE_CTRL + * VSCAN_HOLDOFF = 4 + * VCOM_MODE = MANUAL + * VCOM_VAL = 0 + * DDR_MODE = DISABLED + * LVDS_MODE_CE = DISABLED + * LVDS_MODE = DISABLED + * DUAL_SCAN = DISABLED + * SDDO_WIDTH = 8bit + * PIXELS_PER_SDCLK = 4 + */ + reg_val = + ((4 << EPDC_TCE_CTRL_VSCAN_HOLDOFF_OFFSET) & + EPDC_TCE_CTRL_VSCAN_HOLDOFF_MASK) + | EPDC_TCE_CTRL_PIXELS_PER_SDCLK_4; + REG_WR(EPDC_BASE, EPDC_TCE_CTRL, reg_val); + + /* EPDC_TCE_HSCAN */ + epdc_set_horizontal_timing(panel_info.vl_left_margin, + panel_info.vl_right_margin, + panel_info.vl_hsync, + panel_info.vl_hsync); + + /* EPDC_TCE_VSCAN */ + epdc_set_vertical_timing(panel_info.vl_upper_margin, + panel_info.vl_lower_margin, + panel_info.vl_vsync); + + /* EPDC_TCE_OE */ + reg_val = + ((10 << EPDC_TCE_OE_SDOED_WIDTH_OFFSET) & + EPDC_TCE_OE_SDOED_WIDTH_MASK) + | ((20 << EPDC_TCE_OE_SDOED_DLY_OFFSET) & + EPDC_TCE_OE_SDOED_DLY_MASK) + | ((10 << EPDC_TCE_OE_SDOEZ_WIDTH_OFFSET) & + EPDC_TCE_OE_SDOEZ_WIDTH_MASK) + | ((20 << EPDC_TCE_OE_SDOEZ_DLY_OFFSET) & + EPDC_TCE_OE_SDOEZ_DLY_MASK); + REG_WR(EPDC_BASE, EPDC_TCE_OE, reg_val); + + /* EPDC_TCE_TIMING1 */ + REG_WR(EPDC_BASE, EPDC_TCE_TIMING1, 0x0); + + /* EPDC_TCE_TIMING2 */ + reg_val = + ((480 << EPDC_TCE_TIMING2_GDCLK_HP_OFFSET) & + EPDC_TCE_TIMING2_GDCLK_HP_MASK) + | ((20 << EPDC_TCE_TIMING2_GDSP_OFFSET_OFFSET) & + EPDC_TCE_TIMING2_GDSP_OFFSET_MASK); + REG_WR(EPDC_BASE, EPDC_TCE_TIMING2, reg_val); + + /* EPDC_TCE_TIMING3 */ + reg_val = + ((0 << EPDC_TCE_TIMING3_GDOE_OFFSET_OFFSET) & + EPDC_TCE_TIMING3_GDOE_OFFSET_MASK) + | ((1 << EPDC_TCE_TIMING3_GDCLK_OFFSET_OFFSET) & + EPDC_TCE_TIMING3_GDCLK_OFFSET_MASK); + REG_WR(EPDC_BASE, EPDC_TCE_TIMING3, reg_val); + + /* + * EPDC_TCE_SDCFG + * SDCLK_HOLD = 1 + * SDSHR = 1 + * NUM_CE = 1 + * SDDO_REFORMAT = FLIP_PIXELS + * SDDO_INVERT = DISABLED + * PIXELS_PER_CE = display horizontal resolution + */ + reg_val = EPDC_TCE_SDCFG_SDCLK_HOLD | EPDC_TCE_SDCFG_SDSHR + | ((1 << EPDC_TCE_SDCFG_NUM_CE_OFFSET) & EPDC_TCE_SDCFG_NUM_CE_MASK) + | EPDC_TCE_SDCFG_SDDO_REFORMAT_FLIP_PIXELS + | ((panel_info.vl_col << EPDC_TCE_SDCFG_PIXELS_PER_CE_OFFSET) & + EPDC_TCE_SDCFG_PIXELS_PER_CE_MASK); + REG_WR(EPDC_BASE, EPDC_TCE_SDCFG, reg_val); + + /* + * EPDC_TCE_GDCFG + * GDRL = 1 + * GDOE_MODE = 0; + * GDSP_MODE = 0; + */ + reg_val = EPDC_TCE_SDCFG_GDRL; + REG_WR(EPDC_BASE, EPDC_TCE_GDCFG, reg_val); + + /* + * EPDC_TCE_POLARITY + * SDCE_POL = ACTIVE LOW + * SDLE_POL = ACTIVE HIGH + * SDOE_POL = ACTIVE HIGH + * GDOE_POL = ACTIVE HIGH + * GDSP_POL = ACTIVE LOW + */ + reg_val = EPDC_TCE_POLARITY_SDLE_POL_ACTIVE_HIGH + | EPDC_TCE_POLARITY_SDOE_POL_ACTIVE_HIGH + | EPDC_TCE_POLARITY_GDOE_POL_ACTIVE_HIGH; + REG_WR(EPDC_BASE, EPDC_TCE_POLARITY, reg_val); + + /* EPDC_IRQ_MASK */ + REG_WR(EPDC_BASE, EPDC_IRQ_MASK, + EPDC_IRQ_TCE_UNDERRUN_IRQ); + + /* + * EPDC_GPIO + * PWRCOM = ? + * PWRCTRL = ? + * BDR = ? + */ + reg_val = ((0 << EPDC_GPIO_PWRCTRL_OFFSET) & EPDC_GPIO_PWRCTRL_MASK) + | ((0 << EPDC_GPIO_BDR_OFFSET) & EPDC_GPIO_BDR_MASK); + REG_WR(EPDC_BASE, EPDC_GPIO, reg_val); +} + +static void draw_mode0(void) +{ + int i; + + /* Program EPDC update to process buffer */ + epdc_set_update_coord(0, 0); + epdc_set_update_dimensions(panel_info.vl_col, panel_info.vl_row); + epdc_submit_update(0, panel_info.epdc_data.wv_modes.mode_init, + UPDATE_MODE_FULL, FALSE, 0); + + debug("Mode0 update - Waiting for LUT to complete...\n"); + + /* Will timeout after ~4-5 seconds */ + + for (i = 0; i < 40; i++) { + if (!epdc_is_lut_active(0)) { + debug("Mode0 init complete\n"); + return; + } + msleep(100); + } + + debug("Mode0 init failed!\n"); + +} + +static void draw_splash_screen(void) +{ + int i; + int lut_num = 0; + + /* Program EPDC update to process buffer */ + epdc_set_update_coord(0, 0); + epdc_set_update_dimensions(panel_info.vl_col, panel_info.vl_row); + epdc_submit_update(lut_num, panel_info.epdc_data.wv_modes.mode_gc16, + UPDATE_MODE_FULL, FALSE, 0); + + for (i = 0; i < 40; i++) { + if (!epdc_is_lut_active(lut_num)) { + debug("Splash screen update complete\n"); + return; + } + msleep(100); + } + debug("Splash screen update failed!\n"); + +} + +void lcd_enable(void) +{ + int i; + + epdc_power_on(); + + /* Draw black border around framebuffer*/ + memset(lcd_base, 0xFF, panel_info.vl_col * panel_info.vl_row); + memset(lcd_base, 0x0, 24 * panel_info.vl_col); + for (i = 24; i < (panel_info.vl_row - 24); i++) { + memset((u8 *)lcd_base + i * panel_info.vl_col, 0x00, 24); + memset((u8 *)lcd_base + i * panel_info.vl_col + + panel_info.vl_col - 24, 0x00, 24); + } + memset((u8 *)lcd_base + panel_info.vl_col * (panel_info.vl_row - 24), + 0x00, 24 * panel_info.vl_col); + + /* Draw data to display */ + draw_mode0(); + + draw_splash_screen(); +} + +void lcd_disable(void) +{ + debug("lcd_disable\n"); + + /* Disable clocks to EPDC */ + REG_SET(EPDC_BASE, EPDC_CTRL, EPDC_CTRL_CLKGATE); +} + +void lcd_panel_disable(void) +{ + epdc_power_off(); +} + +void lcd_ctrl_init(void *lcdbase) +{ + /* + * We rely on lcdbase being a physical address, i.e., either MMU off, + * or 1-to-1 mapping. Might want to add some virt2phys here. + */ + if (!lcdbase) + return; + + lcd_color_fg = 0xFF; + lcd_color_bg = 0xFF; + + /* Reset */ + REG_SET(EPDC_BASE, EPDC_CTRL, EPDC_CTRL_SFTRST); + while (!(REG_RD(EPDC_BASE, EPDC_CTRL) & EPDC_CTRL_CLKGATE)) + ; + REG_CLR(EPDC_BASE, EPDC_CTRL, EPDC_CTRL_SFTRST); + + /* Enable clock gating (clear to enable) */ + REG_CLR(EPDC_BASE, EPDC_CTRL, EPDC_CTRL_CLKGATE); + while (REG_RD(EPDC_BASE, EPDC_CTRL) & + (EPDC_CTRL_SFTRST | EPDC_CTRL_CLKGATE)) + ; + + debug("resolution %dx%d, bpp %d\n", (int)panel_info.vl_col, + (int)panel_info.vl_row, NBITS(panel_info.vl_bpix)); + + /* Set framebuffer pointer */ + REG_WR(EPDC_BASE, EPDC_UPD_ADDR, (u32)lcdbase); + + /* Set Working Buffer pointer */ + REG_WR(EPDC_BASE, EPDC_WB_ADDR, panel_info.epdc_data.working_buf_addr); + + /* Get waveform data address and offset */ + if (setup_waveform_file()) { + printf("Can't load waveform data!\n"); + return; + } + + /* Set Waveform Buffer pointer */ + REG_WR(EPDC_BASE, EPDC_WVADDR, + panel_info.epdc_data.waveform_buf_addr); + + /* Initialize EPDC, passing pointer to EPDC registers */ + epdc_init_settings(); + + return; +} + +ulong calc_fbsize(void) +{ + return panel_info.vl_row * panel_info.vl_col * 2 \ + * NBITS(panel_info.vl_bpix) / 8; +} + diff --git a/drivers/video/mxc_epdc_fb.h b/drivers/video/mxc_epdc_fb.h new file mode 100644 index 0000000000..e078538bd5 --- /dev/null +++ b/drivers/video/mxc_epdc_fb.h @@ -0,0 +1,299 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ +#ifndef __EPDC_REGS_INCLUDED__ +#define __EPDC_REGS_INCLUDED__ + +#include +#include + +/************************************* + * Register addresses + *************************************/ +#define EPDC_BASE (EPDC_BASE_ADDR) + +#define EPDC_CTRL (0x000) +#define EPDC_CTRL_SET (0x004) +#define EPDC_CTRL_CLR (0x008) +#define EPDC_CTRL_TOG (0x00c) +#define EPDC_WVADDR (0x020) +#define EPDC_WB_ADDR (0x030) +#define EPDC_RES (0x040) +#define EPDC_FORMAT (0x050) +#define EPDC_FORMAT_SET (0x054) +#define EPDC_FORMAT_CLR (0x058) +#define EPDC_FORMAT_TOG (0x05c) +#define EPDC_FIFOCTRL (0x0a0) +#define EPDC_FIFOCTRL_SET (0x0a4) +#define EPDC_FIFOCTRL_CLR (0x0a8) +#define EPDC_FIFOCTRL_TOG (0x0ac) +#define EPDC_UPD_ADDR (0x100) +#define EPDC_UPD_CORD (0x120) +#define EPDC_UPD_SIZE (0x140) +#define EPDC_UPD_CTRL (0x160) +#define EPDC_UPD_FIXED (0x180) +#define EPDC_TEMP (0x1a0) +#define EPDC_TCE_CTRL (0x200) +#define EPDC_TCE_SDCFG (0x220) +#define EPDC_TCE_GDCFG (0x240) +#define EPDC_TCE_HSCAN1 (0x260) +#define EPDC_TCE_HSCAN2 (0x280) +#define EPDC_TCE_VSCAN (0x2a0) +#define EPDC_TCE_OE (0x2c0) +#define EPDC_TCE_POLARITY (0x2e0) +#define EPDC_TCE_TIMING1 (0x300) +#define EPDC_TCE_TIMING2 (0x310) +#define EPDC_TCE_TIMING3 (0x320) +#define EPDC_IRQ_MASK (0x400) +#define EPDC_IRQ_MASK_SET (0x404) +#define EPDC_IRQ_MASK_CLR (0x408) +#define EPDC_IRQ_MASK_TOG (0x40c) +#define EPDC_IRQ (0x420) +#define EPDC_IRQ_SET (0x424) +#define EPDC_IRQ_CLR (0x428) +#define EPDC_IRQ_TOG (0x42c) +#define EPDC_STATUS_LUTS (0x440) +#define EPDC_STATUS_LUTS_SET (0x444) +#define EPDC_STATUS_LUTS_CLR (0x448) +#define EPDC_STATUS_LUTS_TOG (0x44c) +#define EPDC_STATUS_NEXTLUT (0x460) +#define EPDC_STATUS_COL (0x480) +#define EPDC_STATUS (0x4a0) +#define EPDC_STATUS_SET (0x4a4) +#define EPDC_STATUS_CLR (0x4a8) +#define EPDC_STATUS_TOG (0x4ac) +#define EPDC_DEBUG (0x500) +#define EPDC_DEBUG_LUT0 (0x540) +#define EPDC_DEBUG_LUT1 (0x550) +#define EPDC_DEBUG_LUT2 (0x560) +#define EPDC_DEBUG_LUT3 (0x570) +#define EPDC_DEBUG_LUT4 (0x580) +#define EPDC_DEBUG_LUT5 (0x590) +#define EPDC_DEBUG_LUT6 (0x5a0) +#define EPDC_DEBUG_LUT7 (0x5b0) +#define EPDC_DEBUG_LUT8 (0x5c0) +#define EPDC_DEBUG_LUT9 (0x5d0) +#define EPDC_DEBUG_LUT10 (0x5e0) +#define EPDC_DEBUG_LUT11 (0x5f0) +#define EPDC_DEBUG_LUT12 (0x600) +#define EPDC_DEBUG_LUT13 (0x610) +#define EPDC_DEBUG_LUT14 (0x620) +#define EPDC_DEBUG_LUT15 (0x630) +#define EPDC_GPIO (0x700) +#define EPDC_VERSION (0x7f0) + +enum { + /* EPDC_CTRL field values */ + EPDC_CTRL_SFTRST = 0x80000000, + EPDC_CTRL_CLKGATE = 0x40000000, + EPDC_CTRL_SRAM_POWERDOWN = 0x100, + EPDC_CTRL_UPD_DATA_SWIZZLE_MASK = 0xc0, + EPDC_CTRL_UPD_DATA_SWIZZLE_NO_SWAP = 0, + EPDC_CTRL_UPD_DATA_SWIZZLE_ALL_BYTES_SWAP = 0x40, + EPDC_CTRL_UPD_DATA_SWIZZLE_HWD_SWAP = 0x80, + EPDC_CTRL_UPD_DATA_SWIZZLE_HWD_BYTE_SWAP = 0xc0, + EPDC_CTRL_LUT_DATA_SWIZZLE_MASK = 0x30, + EPDC_CTRL_LUT_DATA_SWIZZLE_NO_SWAP = 0, + EPDC_CTRL_LUT_DATA_SWIZZLE_ALL_BYTES_SWAP = 0x10, + EPDC_CTRL_LUT_DATA_SWIZZLE_HWD_SWAP = 0x20, + EPDC_CTRL_LUT_DATA_SWIZZLE_HWD_BYTE_SWAP = 0x30, + EPDC_CTRL_BURST_LEN_8_8 = 0x1, + EPDC_CTRL_BURST_LEN_8_16 = 0, + + /* EPDC_RES field values */ + EPDC_RES_VERTICAL_MASK = 0x1fff0000, + EPDC_RES_VERTICAL_OFFSET = 16, + EPDC_RES_HORIZONTAL_MASK = 0x1fff, + EPDC_RES_HORIZONTAL_OFFSET = 0, + + /* EPDC_FORMAT field values */ + EPDC_FORMAT_BUF_PIXEL_SCALE_ROUND = 0x1000000, + EPDC_FORMAT_DEFAULT_TFT_PIXEL_MASK = 0xff0000, + EPDC_FORMAT_DEFAULT_TFT_PIXEL_OFFSET = 16, + EPDC_FORMAT_BUF_PIXEL_FORMAT_P2N = 0x200, + EPDC_FORMAT_BUF_PIXEL_FORMAT_P3N = 0x300, + EPDC_FORMAT_BUF_PIXEL_FORMAT_P4N = 0x400, + EPDC_FORMAT_BUF_PIXEL_FORMAT_P5N = 0x500, + EPDC_FORMAT_TFT_PIXEL_FORMAT_2BIT = 0x0, + EPDC_FORMAT_TFT_PIXEL_FORMAT_2BIT_VCOM = 0x1, + EPDC_FORMAT_TFT_PIXEL_FORMAT_4BIT = 0x2, + EPDC_FORMAT_TFT_PIXEL_FORMAT_4BIT_VCOM = 0x3, + + /* EPDC_FIFOCTRL field values */ + EPDC_FIFOCTRL_ENABLE_PRIORITY = 0x80000000, + EPDC_FIFOCTRL_FIFO_INIT_LEVEL_MASK = 0xff0000, + EPDC_FIFOCTRL_FIFO_INIT_LEVEL_OFFSET = 16, + EPDC_FIFOCTRL_FIFO_H_LEVEL_MASK = 0xff00, + EPDC_FIFOCTRL_FIFO_H_LEVEL_OFFSET = 8, + EPDC_FIFOCTRL_FIFO_L_LEVEL_MASK = 0xff, + EPDC_FIFOCTRL_FIFO_L_LEVEL_OFFSET = 0, + + /* EPDC_UPD_CORD field values */ + EPDC_UPD_CORD_YCORD_MASK = 0x1fff0000, + EPDC_UPD_CORD_YCORD_OFFSET = 16, + EPDC_UPD_CORD_XCORD_MASK = 0x1fff, + EPDC_UPD_CORD_XCORD_OFFSET = 0, + + /* EPDC_UPD_SIZE field values */ + EPDC_UPD_SIZE_HEIGHT_MASK = 0x1fff0000, + EPDC_UPD_SIZE_HEIGHT_OFFSET = 16, + EPDC_UPD_SIZE_WIDTH_MASK = 0x1fff, + EPDC_UPD_SIZE_WIDTH_OFFSET = 0, + + /* EPDC_UPD_CTRL field values */ + EPDC_UPD_CTRL_USE_FIXED = 0x80000000, + EPDC_UPD_CTRL_LUT_SEL_MASK = 0xf0000, + EPDC_UPD_CTRL_LUT_SEL_OFFSET = 16, + EPDC_UPD_CTRL_WAVEFORM_MODE_MASK = 0xff00, + EPDC_UPD_CTRL_WAVEFORM_MODE_OFFSET = 8, + EPDC_UPD_CTRL_UPDATE_MODE_FULL = 0x1, + + /* EPDC_UPD_FIXED field values */ + EPDC_UPD_FIXED_FIXNP_EN = 0x80000000, + EPDC_UPD_FIXED_FIXCP_EN = 0x40000000, + EPDC_UPD_FIXED_FIXNP_MASK = 0xff00, + EPDC_UPD_FIXED_FIXNP_OFFSET = 8, + EPDC_UPD_FIXED_FIXCP_MASK = 0xff, + EPDC_UPD_FIXED_FIXCP_OFFSET = 0, + + /* EPDC_TCE_CTRL field values */ + EPDC_TCE_CTRL_VSCAN_HOLDOFF_MASK = 0x1ff0000, + EPDC_TCE_CTRL_VSCAN_HOLDOFF_OFFSET = 16, + EPDC_TCE_CTRL_VCOM_VAL_MASK = 0xc00, + EPDC_TCE_CTRL_VCOM_VAL_OFFSET = 10, + EPDC_TCE_CTRL_VCOM_MODE_AUTO = 0x200, + EPDC_TCE_CTRL_VCOM_MODE_MANUAL = 0x000, + EPDC_TCE_CTRL_DDR_MODE_ENABLE = 0x100, + EPDC_TCE_CTRL_LVDS_MODE_CE_ENABLE = 0x80, + EPDC_TCE_CTRL_LVDS_MODE_ENABLE = 0x40, + EPDC_TCE_CTRL_SCAN_DIR_1_UP = 0x20, + EPDC_TCE_CTRL_SCAN_DIR_0_UP = 0x10, + EPDC_TCE_CTRL_DUAL_SCAN_ENABLE = 0x8, + EPDC_TCE_CTRL_SDDO_WIDTH_16BIT = 0x4, + EPDC_TCE_CTRL_PIXELS_PER_SDCLK_2 = 1, + EPDC_TCE_CTRL_PIXELS_PER_SDCLK_4 = 2, + EPDC_TCE_CTRL_PIXELS_PER_SDCLK_8 = 3, + + /* EPDC_TCE_SDCFG field values */ + EPDC_TCE_SDCFG_SDCLK_HOLD = 0x200000, + EPDC_TCE_SDCFG_SDSHR = 0x100000, + EPDC_TCE_SDCFG_NUM_CE_MASK = 0xf0000, + EPDC_TCE_SDCFG_NUM_CE_OFFSET = 16, + EPDC_TCE_SDCFG_SDDO_REFORMAT_STANDARD = 0, + EPDC_TCE_SDCFG_SDDO_REFORMAT_FLIP_PIXELS = 0x4000, + EPDC_TCE_SDCFG_SDDO_INVERT_ENABLE = 0x2000, + EPDC_TCE_SDCFG_PIXELS_PER_CE_MASK = 0x1fff, + EPDC_TCE_SDCFG_PIXELS_PER_CE_OFFSET = 0, + + /* EPDC_TCE_GDCFG field values */ + EPDC_TCE_SDCFG_GDRL = 0x10, + EPDC_TCE_SDCFG_GDOE_MODE_DELAYED_GDCLK = 0x2, + EPDC_TCE_SDCFG_GDSP_MODE_FRAME_SYNC = 0x1, + EPDC_TCE_SDCFG_GDSP_MODE_ONE_LINE = 0x0, + + /* EPDC_TCE_HSCAN1 field values */ + EPDC_TCE_HSCAN1_LINE_SYNC_WIDTH_MASK = 0xfff0000, + EPDC_TCE_HSCAN1_LINE_SYNC_WIDTH_OFFSET = 16, + EPDC_TCE_HSCAN1_LINE_SYNC_MASK = 0xfff, + EPDC_TCE_HSCAN1_LINE_SYNC_OFFSET = 0, + + /* EPDC_TCE_HSCAN2 field values */ + EPDC_TCE_HSCAN2_LINE_END_MASK = 0xfff0000, + EPDC_TCE_HSCAN2_LINE_END_OFFSET = 16, + EPDC_TCE_HSCAN2_LINE_BEGIN_MASK = 0xfff, + EPDC_TCE_HSCAN2_LINE_BEGIN_OFFSET = 0, + + /* EPDC_TCE_VSCAN field values */ + EPDC_TCE_VSCAN_FRAME_END_MASK = 0xff0000, + EPDC_TCE_VSCAN_FRAME_END_OFFSET = 16, + EPDC_TCE_VSCAN_FRAME_BEGIN_MASK = 0xff00, + EPDC_TCE_VSCAN_FRAME_BEGIN_OFFSET = 8, + EPDC_TCE_VSCAN_FRAME_SYNC_MASK = 0xff, + EPDC_TCE_VSCAN_FRAME_SYNC_OFFSET = 0, + + /* EPDC_TCE_OE field values */ + EPDC_TCE_OE_SDOED_WIDTH_MASK = 0xff000000, + EPDC_TCE_OE_SDOED_WIDTH_OFFSET = 24, + EPDC_TCE_OE_SDOED_DLY_MASK = 0xff0000, + EPDC_TCE_OE_SDOED_DLY_OFFSET = 16, + EPDC_TCE_OE_SDOEZ_WIDTH_MASK = 0xff00, + EPDC_TCE_OE_SDOEZ_WIDTH_OFFSET = 8, + EPDC_TCE_OE_SDOEZ_DLY_MASK = 0xff, + EPDC_TCE_OE_SDOEZ_DLY_OFFSET = 0, + + /* EPDC_TCE_POLARITY field values */ + EPDC_TCE_POLARITY_GDSP_POL_ACTIVE_HIGH = 0x10, + EPDC_TCE_POLARITY_GDOE_POL_ACTIVE_HIGH = 0x8, + EPDC_TCE_POLARITY_SDOE_POL_ACTIVE_HIGH = 0x4, + EPDC_TCE_POLARITY_SDLE_POL_ACTIVE_HIGH = 0x2, + EPDC_TCE_POLARITY_SDCE_POL_ACTIVE_HIGH = 0x1, + + /* EPDC_TCE_TIMING1 field values */ + EPDC_TCE_TIMING1_SDLE_SHIFT_NONE = 0x00, + EPDC_TCE_TIMING1_SDLE_SHIFT_1 = 0x10, + EPDC_TCE_TIMING1_SDLE_SHIFT_2 = 0x20, + EPDC_TCE_TIMING1_SDLE_SHIFT_3 = 0x30, + EPDC_TCE_TIMING1_SDCLK_INVERT = 0x8, + EPDC_TCE_TIMING1_SDCLK_SHIFT_NONE = 0, + EPDC_TCE_TIMING1_SDCLK_SHIFT_1CYCLE = 1, + EPDC_TCE_TIMING1_SDCLK_SHIFT_2CYCLES = 2, + EPDC_TCE_TIMING1_SDCLK_SHIFT_3CYCLES = 3, + + /* EPDC_TCE_TIMING2 field values */ + EPDC_TCE_TIMING2_GDCLK_HP_MASK = 0xffff0000, + EPDC_TCE_TIMING2_GDCLK_HP_OFFSET = 16, + EPDC_TCE_TIMING2_GDSP_OFFSET_MASK = 0xffff, + EPDC_TCE_TIMING2_GDSP_OFFSET_OFFSET = 0, + + /* EPDC_TCE_TIMING3 field values */ + EPDC_TCE_TIMING3_GDOE_OFFSET_MASK = 0xffff0000, + EPDC_TCE_TIMING3_GDOE_OFFSET_OFFSET = 16, + EPDC_TCE_TIMING3_GDCLK_OFFSET_MASK = 0xffff, + EPDC_TCE_TIMING3_GDCLK_OFFSET_OFFSET = 0, + + /* EPDC_IRQ_MASK/EPDC_IRQ field values */ + EPDC_IRQ_WB_CMPLT_IRQ = 0x10000, + EPDC_IRQ_LUT_COL_IRQ = 0x20000, + EPDC_IRQ_TCE_UNDERRUN_IRQ = 0x40000, + EPDC_IRQ_FRAME_END_IRQ = 0x80000, + EPDC_IRQ_BUS_ERROR_IRQ = 0x100000, + EPDC_IRQ_TCE_IDLE_IRQ = 0x200000, + + /* EPDC_STATUS_NEXTLUT field values */ + EPDC_STATUS_NEXTLUT_NEXT_LUT_VALID = 0x100, + EPDC_STATUS_NEXTLUT_NEXT_LUT_MASK = 0xf, + EPDC_STATUS_NEXTLUT_NEXT_LUT_OFFSET = 0, + + /* EPDC_STATUS field values */ + EPDC_STATUS_LUTS_UNDERRUN = 0x4, + EPDC_STATUS_LUTS_BUSY = 0x2, + EPDC_STATUS_WB_BUSY = 0x1, + + /* EPDC_DEBUG field values */ + EPDC_DEBUG_UNDERRUN_RECOVER = 0x2, + EPDC_DEBUG_COLLISION_OFF = 0x1, + + /* EPDC_GPIO field values */ + EPDC_GPIO_PWRCOM = 0x40, + EPDC_GPIO_PWRCTRL_MASK = 0x3c, + EPDC_GPIO_PWRCTRL_OFFSET = 2, + EPDC_GPIO_BDR_MASK = 0x3, + EPDC_GPIO_BDR_OFFSET = 0, +}; + +#endif diff --git a/fs/ubifs/super.c b/fs/ubifs/super.c index 391dea4256..9efe7cd3c4 100644 --- a/fs/ubifs/super.c +++ b/fs/ubifs/super.c @@ -1178,6 +1178,7 @@ int ubifs_mount(char *vol_name) ubifs_umount(ubifs_sb->s_fs_info); INIT_LIST_HEAD(&ubifs_infos); + INIT_LIST_HEAD(&(ubifs_fs_type.fs_supers)); /* * Mount in read-only mode diff --git a/fs/ubifs/ubifs.c b/fs/ubifs/ubifs.c index 8ede188e14..82f1c547da 100644 --- a/fs/ubifs/ubifs.c +++ b/fs/ubifs/ubifs.c @@ -124,9 +124,13 @@ int ubifs_decompress(const void *in_buf, int in_len, void *out_buf, static int __init compr_init(struct ubifs_compressor *compr) { ubifs_compressors[compr->compr_type] = compr; + +#ifndef CONFIG_RELOC_FIXUP_WORKS ubifs_compressors[compr->compr_type]->name += gd->reloc_off; ubifs_compressors[compr->compr_type]->capi_name += gd->reloc_off; ubifs_compressors[compr->compr_type]->decompress += gd->reloc_off; +#endif + return 0; } @@ -379,9 +383,11 @@ static unsigned long ubifs_findfile(struct super_block *sb, char *filename) int ret; char *next; char fpath[128]; + char symlinkpath[128]; char *name = fpath; unsigned long root_inum = 1; unsigned long inum; + int symlink_count = 0; /* Don't allow symlink recursion */ strcpy(fpath, filename); @@ -397,6 +403,9 @@ static unsigned long ubifs_findfile(struct super_block *sb, char *filename) return inum; for (;;) { + struct inode *inode; + struct ubifs_inode *ui; + /* Extract the actual part from the pathname. */ next = strchr(name, '/'); if (next) { @@ -406,18 +415,48 @@ static unsigned long ubifs_findfile(struct super_block *sb, char *filename) } ret = ubifs_finddir(sb, name, root_inum, &inum); + if (!ret) + return 0; + inode = ubifs_iget(sb, inum); + + if (!inode) + return 0; + ui = ubifs_inode(inode); + + if ((inode->i_mode & S_IFMT) == S_IFLNK) { + char link_name[64]; + char buf[128]; + + /* We have some sort of symlink recursion, bail out */ + if (symlink_count++ > 8) { + printf("Symlink recursion, aborting\n"); + return 0; + } + memcpy(link_name, ui->data, ui->data_len); + link_name[ui->data_len] = '\0'; + + if (link_name[0] == '/') { + /* Absolute path, redo everything without + * the leading slash */ + next = name = link_name + 1; + root_inum = 1; + continue; + } + /* Relative to cur dir */ + sprintf(buf, "%s/%s", + link_name, next == NULL ? "" : next); + memcpy(symlinkpath, buf, sizeof(buf)); + next = name = symlinkpath; + continue; + } /* * Check if directory with this name exists */ /* Found the node! */ - if (!next || *next == '\0') { - if (ret) - return inum; - - break; - } + if (!next || *next == '\0') + return inum; root_inum = inum; name = next; @@ -614,10 +653,10 @@ int ubifs_load(char *filename, u32 addr, u32 size) int err = 0; int i; int count; - char link_name[64]; - struct ubifs_inode *ui; c->ubi = ubi_open_volume(c->vi.ubi_num, c->vi.vol_id, UBI_READONLY); + /* ubifs_findfile will resolve symlinks, so we know that we get + * the real file here */ inum = ubifs_findfile(ubifs_sb, filename); if (!inum) { err = -1; @@ -634,23 +673,6 @@ int ubifs_load(char *filename, u32 addr, u32 size) goto out; } - /* - * Check for symbolic link - */ - ui = ubifs_inode(inode); - if (((inode->i_mode & S_IFMT) == S_IFLNK) && ui->data_len) { - memcpy(link_name, ui->data, ui->data_len); - link_name[ui->data_len] = '\0'; - printf("%s is linked to %s!\n", filename, link_name); - ubifs_iput(inode); - - /* - * Now we have the "real" filename, call ubifs_load() - * again (recursive call) to load this file instead - */ - return ubifs_load(link_name, addr, size); - } - /* * If no size was specified or if size bigger than filesize * set size to filesize diff --git a/fs/ubifs/ubifs.h b/fs/ubifs/ubifs.h index 43865aa66e..06772af36f 100644 --- a/fs/ubifs/ubifs.h +++ b/fs/ubifs/ubifs.h @@ -449,38 +449,6 @@ static inline ino_t parent_ino(struct dentry *dentry) return res; } -/* linux/include/linux/bitops.h */ - -#define BIT_MASK(nr) (1UL << ((nr) % BITS_PER_LONG)) -#define BIT_WORD(nr) ((nr) / BITS_PER_LONG) - -/* linux/include/asm-generic/bitops/non-atomic.h */ - -/** - * __set_bit - Set a bit in memory - * @nr: the bit to set - * @addr: the address to start counting from - * - * Unlike set_bit(), this function is non-atomic and may be reordered. - * If it's called on the same region of memory simultaneously, the effect - * may be that only one operation succeeds. - */ -static inline void __set_bit(int nr, volatile unsigned long *addr) -{ - unsigned long mask = BIT_MASK(nr); - unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); - - *p |= mask; -} - -static inline void __clear_bit(int nr, volatile unsigned long *addr) -{ - unsigned long mask = BIT_MASK(nr); - unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); - - *p &= ~mask; -} - /* debug.c */ #define DEFINE_SPINLOCK(...) diff --git a/include/ahci.h b/include/ahci.h index 0c6bbbdc56..12f653a58d 100644 --- a/include/ahci.h +++ b/include/ahci.h @@ -1,4 +1,7 @@ /* + * (C) Copyright 2008-2010 Freescale Semiconductor, Inc. + * Terry Lv + * * Copyright (C) Freescale Semiconductor, Inc. 2006. * Author: Jason Jin * Zhang Wei @@ -25,15 +28,18 @@ #ifndef _AHCI_H_ #define _AHCI_H_ +#include + #define AHCI_PCI_BAR 0x24 #define AHCI_MAX_SG 56 /* hardware max is 64K */ +#define AHCI_MAX_CMD_SLOT 32 #define AHCI_CMD_SLOT_SZ 32 #define AHCI_RX_FIS_SZ 256 #define AHCI_CMD_TBL_HDR 0x80 #define AHCI_CMD_TBL_CDB 0x40 -#define AHCI_CMD_TBL_SZ AHCI_CMD_TBL_HDR + (AHCI_MAX_SG * 16) -#define AHCI_PORT_PRIV_DMA_SZ AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_SZ \ - + AHCI_RX_FIS_SZ +#define AHCI_CMD_TBL_SZ (AHCI_CMD_TBL_HDR + (AHCI_MAX_SG * 16)) +#define AHCI_PORT_PRIV_DMA_SZ (AHCI_CMD_SLOT_SZ * AHCI_MAX_CMD_SLOT + \ + AHCI_CMD_TBL_SZ + AHCI_RX_FIS_SZ) #define AHCI_CMD_ATAPI (1 << 5) #define AHCI_CMD_WRITE (1 << 6) #define AHCI_CMD_PREFETCH (1 << 7) @@ -179,7 +185,7 @@ struct ahci_probe_ent { u32 host_flags; u32 host_set_flags; u32 mmio_base; - u32 pio_mask; + u32 pio_mask; u32 udma_mask; u32 flags; u32 cap; /* cache of HOST_CAP register */ diff --git a/include/asm-arm/arch-mx23/clkctrl.h b/include/asm-arm/arch-mx23/clkctrl.h new file mode 100644 index 0000000000..f0cf735e23 --- /dev/null +++ b/include/asm-arm/arch-mx23/clkctrl.h @@ -0,0 +1,64 @@ +/* + * Copyright (C) 2008 Embedded Alley Solutions Inc. + * + * (C) Copyright 2009-2010 Freescale Semiconductor, Inc. + * + * Clock control register descriptions + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#ifndef CLKCTRL_H +#define CLKCTRL_H + +#include + +#define CLKCTRL_BASE (MX23_REGS_BASE + 0x40000) + +#define CLKCTRL_PLLCTRL0 0x000 +#define CLKCTRL_PLLCTRL1 0x010 +#define CLKCTRL_CPU 0x020 +#define CLKCTRL_HBUS 0x030 +#define CLKCTRL_XBUS 0x040 +#define CLKCTRL_XTAL 0x050 +#define CLKCTRL_PIX 0x060 +#define CLKCTRL_SSP 0x070 +#define CLKCTRL_GPMI 0x080 +#define CLKCTRL_SPDIF 0x090 +#define CLKCTRL_EMI 0x0a0 +#define CLKCTRL_IR 0x0b0 +#define CLKCTRL_SAIF 0x0c0 +#define CLKCTRL_TV 0x0d0 +#define CLKCTRL_ETM 0x0e0 +#define CLKCTRL_FRAC 0x0f0 +#define CLKCTRL_FRAC1 0x100 +#define CLKCTRL_CLKSEQ 0x110 +#define CLKCTRL_RESET 0x120 +#define CLKCTRL_STATUS 0x130 +#define CLKCTRL_VERSION 0x140 + +/* CLKCTRL_SSP register bits, bit fields and values */ +#define SSP_CLKGATE (1 << 31) +#define SSP_BUSY (1 << 29) +#define SSP_DIV_FRAC_EN (1 << 9) +#define SSP_DIV 0 + +/* CLKCTRL_FRAC register bits, bit fields and values */ +#define FRAC_CLKGATEIO (1 << 31) +#define FRAC_IOFRAC 24 + +/* CLKCTRL_FRAC register bits, bit fields and values */ +#define CLKSEQ_BYPASS_SSP (1 << 5) + +#endif /* CLKCTRL_H */ diff --git a/include/asm-arm/arch-mx23/dbguart.h b/include/asm-arm/arch-mx23/dbguart.h new file mode 100644 index 0000000000..567cde6922 --- /dev/null +++ b/include/asm-arm/arch-mx23/dbguart.h @@ -0,0 +1,30 @@ +/* + * Copyright (C) 2008 Embedded Alley Solutions Inc. + * + * (C) Copyright 2009-2010 Freescale Semiconductor, Inc. + * + * Debug UART register definitions + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef DBGUART_H +#define DBGUART_H + +#include + +#define DBGUART_BASE (MX23_REGS_BASE + 0x00070000) + +#endif /* DBGUART_H */ diff --git a/include/asm-arm/arch-mx23/mx23.h b/include/asm-arm/arch-mx23/mx23.h new file mode 100644 index 0000000000..d24a1126ad --- /dev/null +++ b/include/asm-arm/arch-mx23/mx23.h @@ -0,0 +1,40 @@ +/* + * Copyright (C) 2008 Embedded Alley Solutions Inc. + * + * (C) Copyright 2009-2010 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#ifndef MX23_H +#define MX23_H + +/* + * Most of 378x SoC registers are associated with four addresses + * used for different operations - read/write, set, clear and toggle bits. + * + * Some of registers do not implement such feature and, thus, should be + * accessed/manipulated via single address in common way. + */ +#define REG_RD(x) (*(volatile unsigned int *)(x)) +#define REG_WR(x, v) ((*(volatile unsigned int *)(x)) = (v)) +#define REG_SET(x, v) ((*(volatile unsigned int *)((x) + 0x04)) = (v)) +#define REG_CLR(x, v) ((*(volatile unsigned int *)((x) + 0x08)) = (v)) +#define REG_TOG(x, v) ((*(volatile unsigned int *)((x) + 0x0c)) = (v)) + +#define MX23_OCRAM_BASE 0x00000000 +#define MX23_SDRAM_BASE 0x40000000 +#define MX23_REGS_BASE 0x80000000 + +#endif /* STMP378X_H */ diff --git a/include/asm-arm/arch-mx23/ocotp.h b/include/asm-arm/arch-mx23/ocotp.h new file mode 100644 index 0000000000..cdf27cd8d8 --- /dev/null +++ b/include/asm-arm/arch-mx23/ocotp.h @@ -0,0 +1,69 @@ +/* Copyright 2009-2010 Freescale Semiconductor, Inc. + * + * On-Chip OTP register descriptions + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#ifndef OCOTP_H +#define OCOTP_H + +#include + +#define OCOTP_BASE (MX23_REGS_BASE + 0x2c000) + +#define OCOTP_CTRL 0x000 +#define OCOTP_CTRL_SET 0x004 +#define OCOTP_CTRL_CLR 0x008 +#define OCOTP_CTRL_TOG 0x00c +#define OCOTP_DATA 0x010 +#define OCOTP_CUST0 0x020 +#define OCOTP_CUST1 0x030 +#define OCOTP_CUST2 0x040 +#define OCOTP_CUST3 0x050 +#define OCOTP_CRYPTO1 0x070 +#define OCOTP_CRYPTO2 0x080 +#define OCOTP_CRYPTO3 0x090 +#define OCOTP_HWCAP0 0x0a0 +#define OCOTP_HWCAP1 0x0b0 +#define OCOTP_HWCAP2 0x0c0 +#define OCOTP_HWCAP3 0x0d0 +#define OCOTP_HWCAP4 0x0e0 +#define OCOTP_HWCAP5 0x0f0 +#define OCOTP_SWCAP 0x100 +#define OCOTP_CUSTCAP 0x110 +#define OCOTP_LOCK 0x120 +#define OCOTP_OPS0 0x130 +#define OCOTP_OPS1 0x140 +#define OCOTP_OPS2 0x150 +#define OCOTP_OPS3 0x160 +#define OCOTP_UN0 0x170 +#define OCOTP_UN1 0x180 +#define OCOTP_UN2 0x190 +#define OCOTP_ROM0 0x1a0 +#define OCOTP_ROM1 0x1b0 +#define OCOTP_ROM2 0x1c0 +#define OCOTP_ROM3 0x1d0 +#define OCOTP_ROM4 0x1e0 +#define OCOTP_ROM5 0x1f0 +#define OCOTP_ROM6 0x200 +#define OCOTP_ROM7 0x210 +#define OCOTP_VERSION 0x220 + + +/* OCOTP_CTRL register bits, bit fields and values */ +#define CTRL_RD_BANK_OPEN (1 << 12) +#define CTRL_BUSY (8 << 12) + +#endif /* OCOTP_H */ diff --git a/include/asm-arm/arch-mx23/pinmux.h b/include/asm-arm/arch-mx23/pinmux.h new file mode 100644 index 0000000000..29c5ca20eb --- /dev/null +++ b/include/asm-arm/arch-mx23/pinmux.h @@ -0,0 +1,42 @@ +/* + * Copyright (C) 2008 Embedded Alley Solutions Inc. + * + * (C) Copyright 2009-2010 Freescale Semiconductor, Inc. + * + * Clock control register descriptions + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#ifndef PINMUX_H +#define PINMUX_H + +#include + +#define PINCTRL_BASE (MX23_REGS_BASE + 0x18000) + +#define PINCTRL_CTRL 0x000 +#define PINCTRL_MUXSEL(n) (0x100 + 0x10*(n)) +#define PINCTRL_DRIVE(n) (0x200 + 0x10*(n)) +#define PINCTRL_PULL(n) (0x400 + 0x10*(n)) +#define PINCTRL_DOUT(n) (0x500 + 0x10*(n)) +#define PINCTRL_DIN(n) (0x600 + 0x10*(n)) +#define PINCTRL_DOE(n) (0x700 + 0x10*(n)) +#define PINCTRL_PIN2IRQ(n) (0x800 + 0x10*(n)) +#define PINCTRL_IRQEN(n) (0x900 + 0x10*(n)) +#define PINCTRL_IRQLEVEL(n) (0xa00 + 0x10*(n)) +#define PINCTRL_IRQPOL(n) (0xb00 + 0x10*(n)) +#define PINCTRL_IRQSTAT(n) (0xc00 + 0x10*(n)) + +#endif /* PINMUX_H */ diff --git a/include/asm-arm/arch-mx23/spi.h b/include/asm-arm/arch-mx23/spi.h new file mode 100644 index 0000000000..d23d16e39c --- /dev/null +++ b/include/asm-arm/arch-mx23/spi.h @@ -0,0 +1,69 @@ +/* + * Copyright (C) 2008 Embedded Alley Solutions Inc. + * + * (C) Copyright 2009-2010 Freescale Semiconductor, Inc. + * + * SSP/SPI driver + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#ifndef SPI_H +#define SPI_H + +#include +#include +#include + +/* + * Flags to set SPI mode + */ +#define SPI_PHASE 0x1 /* Set phase to 1 */ +#define SPI_POLARITY 0x2 /* Set polarity to 1 */ + +/* Various flags to control SPI transfers */ +#define SPI_START 0x1 /* Lock CS signal */ +#define SPI_STOP 0x2 /* Unlock CS signal */ + +/* + * Init SSPx interface, must be called first + */ +void spi_init(void); + +/* + * Set phase, polarity and CS number (SS0, SS1, SS2) + */ +void spi_set_cfg(unsigned int bus, unsigned int cs, unsigned long mode); + + +/* + * Send @rx_len bytes from @dout, then receive @rx_len bytes + * saving them to @din + */ +void spi_txrx(const char *dout, unsigned int tx_len, char *din, + unsigned int rx_len, unsigned long flags); + + +/* Lock/unlock SPI bus */ +static inline void spi_lock(void) +{ + disable_interrupts(); +} + +static inline void spi_unlock(void) +{ + enable_interrupts(); +} + +#endif /* SPI_H */ diff --git a/include/asm-arm/arch-mx23/ssp.h b/include/asm-arm/arch-mx23/ssp.h new file mode 100644 index 0000000000..cf93f82113 --- /dev/null +++ b/include/asm-arm/arch-mx23/ssp.h @@ -0,0 +1,100 @@ +/* + * Copyright (C) 2008 Embedded Alley Solutions Inc. + * + * (C) Copyright 2009-2010 Freescale Semiconductor, Inc. + * + * SSP register definitions + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#ifndef SSP_H +#define SSP_H + +#include + +#define SSP1_BASE (MX23_REGS_BASE + 0x10000) +#define SSP2_BASE (MX23_REGS_BASE + 0x34000) + +#define SSP_CTRL0 0x000 +#define SSP_CMD0 0x010 +#define SSP_CMD1 0x020 +#define SSP_COMPREF 0x030 +#define SSP_COMPMASK 0x040 +#define SSP_TIMING 0x050 +#define SSP_CTRL1 0x060 +#define SSP_DATA 0x070 +#define SSP_SDRESP0 0x080 +#define SSP_SDRESP1 0x090 +#define SSP_SDRESP2 0x0a0 +#define SSP_SDRESP3 0x0b0 +#define SSP_STATUS 0x0c0 +#define SSP_DEBUG 0x100 +#define SSP_VERSION 0x110 + +/* CTRL0 bits, bit fields and values */ +#define CTRL0_SFTRST (0x1 << 31) +#define CTRL0_CLKGATE (0x1 << 30) +#define CTRL0_RUN (0x1 << 29) +#define CTRL0_LOCK_CS (0x1 << 27) +#define CTRL0_IGNORE_CRC (0x1 << 26) +#define CTRL0_DATA_XFER (0x1 << 24) +#define CTRL0_READ (0x1 << 25) +#define CTRL0_BUS_WIDTH 22 +#define CTRL0_WAIT_FOR_IRQ (0x1 << 21) +#define CTRL0_WAIT_FOR_CMD (0x1 << 20) +#define CTRL0_XFER_COUNT 0 + +#define BUS_WIDTH_SPI1 (0x0 << CTRL0_BUS_WIDTH) +#define BUS_WIDTH_SPI4 (0x1 << CTRL0_BUS_WIDTH) +#define BUS_WIDTH_SPI8 (0x2 << CTRL0_BUS_WIDTH) + +#define SPI_CS0 0x0 +#define SPI_CS1 CTRL0_WAIT_FOR_CMD +#define SPI_CS2 CTRL0_WAIT_FOR_IRQ +#define SPI_CS_CLR_MASK (CTRL0_WAIT_FOR_CMD | CTRL0_WAIT_FOR_IRQ) + +/* CMD0 bits, bit fields and values */ +#define CMD0_BLOCK_SIZE 16 +#define CMD0_BLOCK_COUNT 12 +#define CMD0_CMD 0 + +/* TIMING bits, bit fields and values */ +#define TIMING_TIMEOUT 16 +#define TIMING_CLOCK_DIVIDE 8 +#define TIMING_CLOCK_RATE 0 + +/* CTRL1 bits, bit fields and values */ +#define CTRL1_DMA_ENABLE (0x1 << 13) +#define CTRL1_PHASE (0x1 << 10) +#define CTRL1_POLARITY (0x1 << 9) +#define CTRL1_SLAVE_MODE (0x1 << 8) +#define CTRL1_WORD_LENGTH 4 +#define CTRL1_SSP_MODE 0 + +#define WORD_LENGTH4 (0x3 << CTRL1_WORD_LENGTH) +#define WORD_LENGTH8 (0x7 << CTRL1_WORD_LENGTH) +#define WORD_LENGTH16 (0xF << CTRL1_WORD_LENGTH) + +#define SSP_MODE_SPI (0x0 << CTRL1_SSP_MODE) +#define SSP_MODE_SSI (0x1 << CTRL1_SSP_MODE) +#define SSP_MODE_SD_MMC (0x3 << CTRL1_SSP_MODE) +#define SSP_MODE_MS (0x4 << CTRL1_SSP_MODE) +#define SSP_MODE_ATA (0x7 << CTRL1_SSP_MODE) + +/* CTRL1 bits, bit fields and values */ +#define STATUS_FIFO_EMPTY (1 << 5) +#define STATUS_FIFO_FULL (1 << 8) + +#endif /* SSP_H */ diff --git a/include/asm-arm/arch-mx23/timrot.h b/include/asm-arm/arch-mx23/timrot.h new file mode 100644 index 0000000000..2022232a2b --- /dev/null +++ b/include/asm-arm/arch-mx23/timrot.h @@ -0,0 +1,63 @@ +/* + * Copyright (C) 2008 Embedded Alley Solutions Inc. + * + * (C) Copyright 2009-2010 Freescale Semiconductor, Inc. + * + * Timers and rotary encoder register definitions + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#ifndef TIMROT_H +#define TIMROT_H + +#include + +#define TIMROT_BASE (MX23_REGS_BASE + 0x00068000) + +/* Timer and rotary encoder register offsets */ +#define ROTCTRL 0x0 +#define ROTCOUNT 0x10 +#define TIMCTRL0 0x20 +#define TIMCOUNT0 0x30 +#define TIMCTRL1 0x40 +#define TIMCOUNT1 0x50 +#define TIMCTRL2 0x60 +#define TIMCOUNT2 0x70 +#define TIMCTRL3 0x80 +#define TIMCTRL3 0x90 + +/* TIMCTRL bits, bit fields and values */ +#define TIMCTRL_SELECT 0 +#define TIMCTRL_PRESCALE 4 +#define TIMCTRL_RELOAD (1 << 6) +#define TIMCTRL_UPDATE (1 << 7) +#define TIMCTRL_POLARITY (1 << 8) +#define TIMCTRL_IRQEN (1 << 14) +#define TIMCTRL_IRQ (1 << 15) + +#define TIMCTRL_SELECT_PWM0 (0x1 << TIMCTRL_SELECT) +#define TIMCTRL_SELECT_PWM1 (0x2 << TIMCTRL_SELECT) +#define TIMCTRL_SELECT_PWM2 (0x3 << TIMCTRL_SELECT) +#define TIMCTRL_SELECT_PWM3 (0x4 << TIMCTRL_SELECT) +#define TIMCTRL_SELECT_PWM4 (0x5 << TIMCTRL_SELECT) +#define TIMCTRL_SELECT_ROTARYA (0x6 << TIMCTRL_SELECT) +#define TIMCTRL_SELECT_ROTARYB (0x7 << TIMCTRL_SELECT) +#define TIMCTRL_SELECT_32KHZ (0x8 << TIMCTRL_SELECT) +#define TIMCTRL_SELECT_8KHZ (0x9 << TIMCTRL_SELECT) +#define TIMCTRL_SELECT_4KHZ (0xa << TIMCTRL_SELECT) +#define TIMCTRL_SELECT_1KHZ (0xb << TIMCTRL_SELECT) +#define TIMCTRL_SELECT_ALWAYS (0xc << TIMCTRL_SELECT) + +#endif /* TIMROT_H */ diff --git a/include/asm-arm/arch-mx25/gpio.h b/include/asm-arm/arch-mx25/gpio.h new file mode 100644 index 0000000000..69eb987e98 --- /dev/null +++ b/include/asm-arm/arch-mx25/gpio.h @@ -0,0 +1,33 @@ +/* + * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#ifndef __MACH_MX25_GPIO_H__ +#define __MACH_MX25_GPIO_H__ + +#include + +static void _set_gpio_direction(u32 port, u32 index, int is_input); + +void mxc_set_gpio_direction(iomux_pin_name_t pin, int is_input); + +static void _set_gpio_dataout(u32 port, u32 index, u32 data); + +void mxc_set_gpio_dataout(iomux_pin_name_t pin, u32 data); + +/*! + * @file mach-mx25/gpio.h + * + * @brief Simple GPIO definitions and functions + * + * @ingroup GPIO_MX25 + */ +#endif diff --git a/include/asm-arm/arch-mx25/imx_spi_cpld.h b/include/asm-arm/arch-mx25/imx_spi_cpld.h new file mode 100644 index 0000000000..4bf1388a45 --- /dev/null +++ b/include/asm-arm/arch-mx25/imx_spi_cpld.h @@ -0,0 +1,46 @@ +/* + * (C) Copyright 2009 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _IMX_SPI_CPLD_H_ +#define _IMX_SPI_CPLD_H_ + +#include + +#define PBC_LED_CTRL 0x20000 +#define PBC_SB_STAT 0x20008 +#define PBC_ID_AAAA 0x20040 +#define PBC_ID_5555 0x20048 +#define PBC_VERSION 0x20050 +#define PBC_ID_CAFE 0x20058 +#define PBC_INT_STAT 0x20010 +#define PBC_INT_MASK 0x20038 +#define PBC_INT_REST 0x20020 +#define PBC_SW_RESET 0x20060 + +void cpld_reg_write(u32 offset, u32 val); +u32 cpld_reg_read(u32 offset); +struct spi_slave *spi_cpld_probe(); +void spi_cpld_free(struct spi_slave *slave); +unsigned int cpld_reg_xfer(unsigned int reg, unsigned int val, + unsigned int read); + +#endif /* _IMX_SPI_CPLD_H_ */ diff --git a/include/asm-arm/arch-mx25/iomux.h b/include/asm-arm/arch-mx25/iomux.h new file mode 100644 index 0000000000..0719c7927c --- /dev/null +++ b/include/asm-arm/arch-mx25/iomux.h @@ -0,0 +1,220 @@ +/* + * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#ifndef __MACH_MX25_IOMUX_H__ +#define __MACH_MX25_IOMUX_H__ + +#include + +/*! + * @file mach-mx25/iomux.h + * + * @brief I/O Muxing control definitions and functions + * + * @ingroup GPIO_MX25 + */ + +/*! + * IOMUX functions + * SW_MUX_CTL + */ +typedef enum iomux_pin_config { + MUX_CONFIG_FUNC = 0, /*!< used as function */ + MUX_CONFIG_ALT1, /*!< used as alternate function 1 */ + MUX_CONFIG_ALT2, /*!< used as alternate function 2 */ + MUX_CONFIG_ALT3, /*!< used as alternate function 3 */ + MUX_CONFIG_ALT4, /*!< used as alternate function 4 */ + MUX_CONFIG_ALT5, /*!< used as alternate function 5 */ + MUX_CONFIG_ALT6, /*!< used as alternate function 6 */ + MUX_CONFIG_ALT7, /*!< used as alternate function 7 */ + MUX_CONFIG_SION = 0x1 << 4, /*!< used as LOOPBACK:MUX SION bit */ + MUX_CONFIG_GPIO = MUX_CONFIG_ALT5, /*!< used as GPIO */ +} iomux_pin_cfg_t; + +/*! + * IOMUX pad functions + * SW_PAD_CTL + */ +typedef enum iomux_pad_config { + PAD_CTL_DRV_3_3V = 0x0 << 13, + PAD_CTL_DRV_1_8V = 0x1 << 13, + PAD_CTL_HYS_CMOS = 0x0 << 8, + PAD_CTL_HYS_SCHMITZ = 0x1 << 8, + PAD_CTL_PKE_NONE = 0x0 << 7, + PAD_CTL_PKE_ENABLE = 0x1 << 7, + PAD_CTL_PUE_KEEPER = 0x0 << 6, + PAD_CTL_PUE_PUD = 0x1 << 6, + PAD_CTL_100K_PD = 0x0 << 4, + PAD_CTL_47K_PU = 0x1 << 4, + PAD_CTL_100K_PU = 0x2 << 4, + PAD_CTL_22K_PU = 0x3 << 4, + PAD_CTL_ODE_CMOS = 0x0 << 3, + PAD_CTL_ODE_OpenDrain = 0x1 << 3, + PAD_CTL_DRV_NORMAL = 0x0 << 1, + PAD_CTL_DRV_HIGH = 0x1 << 1, + PAD_CTL_DRV_MAX = 0x2 << 1, + PAD_CTL_SRE_SLOW = 0x0 << 0, + PAD_CTL_SRE_FAST = 0x1 << 0 +} iomux_pad_config_t; + +/*! + * IOMUX general purpose functions + * IOMUXC_GPR1 + */ +typedef enum iomux_gp_func { + MUX_SDCTL_CSD0_SEL = 0x1 << 0, + MUX_SDCTL_CSD1_SEL = 0x1 << 1, +} iomux_gp_func_t; + +/*! + * IOMUX SELECT_INPUT register index + * Base register is IOMUXSW_INPUT_CTL in iomux.c + */ +typedef enum iomux_input_select { + MUX_IN_AUDMUX_P4_INPUT_DA_AMX = 0, + MUX_IN_AUDMUX_P4_INPUT_DB_AMX, + MUX_IN_AUDMUX_P4_INPUT_RXCLK_AMX, + MUX_IN_AUDMUX_P4_INPUT_RXFS_AMX, + MUX_IN_AUDMUX_P4_INPUT_TXCLK_AMX, + MUX_IN_AUDMUX_P4_INPUT_TXFS_AMX, + MUX_IN_AUDMUX_P7_INPUT_DA_AMX, + MUX_IN_AUDMUX_P7_INPUT_TXFS_AMX, + MUX_IN_CAN1_IPP_IND_CANRX, + MUX_IN_CAN2_IPP_IND_CANRX, + MUX_IN_CSI_IPP_CSI_D_0, + MUX_IN_CSI_IPP_CSI_D_1, + MUX_IN_CSPI1_IPP_IND_SS3_B, + MUX_IN_CSPI2_IPP_CSPI_CLK_IN, + MUX_IN_CSPI2_IPP_IND_DATAREADY_B, + MUX_IN_CSPI2_IPP_IND_MISO, + MUX_IN_CSPI2_IPP_IND_MOSI, + MUX_IN_CSPI2_IPP_IND_SS0_B, + MUX_IN_CSPI2_IPP_IND_SS1_B, + MUX_IN_CSPI3_IPP_CSPI_CLK_IN, + MUX_IN_CSPI3_IPP_IND_DATAREADY_B, + MUX_IN_CSPI3_IPP_IND_MISO, + MUX_IN_CSPI3_IPP_IND_MOSI, + MUX_IN_CSPI3_IPP_IND_SS0_B, + MUX_IN_CSPI3_IPP_IND_SS1_B, + MUX_IN_CSPI3_IPP_IND_SS2_B, + MUX_IN_CSPI3_IPP_IND_SS3_B, + MUX_IN_ESDHC1_IPP_DAT4_IN, + MUX_IN_ESDHC1_IPP_DAT5_IN, + MUX_IN_ESDHC1_IPP_DAT6_IN, + MUX_IN_ESDHC1_IPP_DAT7_IN, + MUX_IN_ESDHC2_IPP_CARD_CLK_IN, + MUX_IN_ESDHC2_IPP_CMD_IN, + MUX_IN_ESDHC2_IPP_DAT0_IN, + MUX_IN_ESDHC2_IPP_DAT1_IN, + MUX_IN_ESDHC2_IPP_DAT2_IN, + MUX_IN_ESDHC2_IPP_DAT3_IN, + MUX_IN_ESDHC2_IPP_DAT4_IN, + MUX_IN_ESDHC2_IPP_DAT5_IN, + MUX_IN_ESDHC2_IPP_DAT6_IN, + MUX_IN_ESDHC2_IPP_DAT7_IN, + MUX_IN_FEC_FEC_COL, + MUX_IN_FEC_FEC_CRS, + MUX_IN_FEC_FEC_RDATA_2, + MUX_IN_FEC_FEC_RDATA_3, + MUX_IN_FEC_FEC_RX_CLK, + MUX_IN_FEC_FEC_RX_ER, + MUX_IN_I2C2_IPP_SCL_IN, + MUX_IN_I2C2_IPP_SDA_IN, + MUX_IN_I2C3_IPP_SCL_IN, + MUX_IN_I2C3_IPP_SDA_IN, + MUX_IN_KPP_IPP_IND_COL_4, + MUX_IN_KPP_IPP_IND_COL_5, + MUX_IN_KPP_IPP_IND_COL_6, + MUX_IN_KPP_IPP_IND_COL_7, + MUX_IN_KPP_IPP_IND_ROW_4, + MUX_IN_KPP_IPP_IND_ROW_5, + MUX_IN_KPP_IPP_IND_ROW_6, + MUX_IN_KPP_IPP_IND_ROW_7, + MUX_IN_SIM1_PIN_SIM_RCVD1_IN, + MUX_IN_SIM1_PIN_SIM_SIMPD1, + MUX_IN_SIM1_SIM_RCVD1_IO, + MUX_IN_SIM2_PIN_SIM_RCVD1_IN, + MUX_IN_SIM2_PIN_SIM_SIMPD1, + MUX_IN_SIM2_SIM_RCVD1_IO, + MUX_IN_UART3_IPP_UART_RTS_B, + MUX_IN_UART3_IPP_UART_RXD_MUX, + MUX_IN_UART4_IPP_UART_RTS_B, + MUX_IN_UART4_IPP_UART_RXD_MUX, + MUX_IN_UART5_IPP_UART_RTS_B, + MUX_IN_UART5_IPP_UART_RXD_MUX, + MUX_IN_USB_TOP_IPP_IND_OTG_USB_OC, + MUX_IN_USB_TOP_IPP_IND_UH2_USB_OC, +} iomux_input_select_t; + +/*! + * IOMUX input functions + * SW_SELECT_INPUT bits 2-0 + */ +typedef enum iomux_input_config { + INPUT_CTL_PATH0 = 0x0, + INPUT_CTL_PATH1, + INPUT_CTL_PATH2, + INPUT_CTL_PATH3, + INPUT_CTL_PATH4, + INPUT_CTL_PATH5, + INPUT_CTL_PATH6, + INPUT_CTL_PATH7, +} iomux_input_cfg_t; + +/*! + * Request ownership for an IO pin. This function has to be the first one + * being called before that pin is used. The caller has to check the + * return value to make sure it returns 0. + * + * @param pin a name defined by \b iomux_pin_name_t + * @param cfg an input function as defined in \b #iomux_pin_cfg_t + * + * @return 0 if successful; Non-zero otherwise + */ +int mxc_request_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg); + +/*! + * Release ownership for an IO pin + * + * @param pin a name defined by \b iomux_pin_name_t + * @param cfg an input function as defined in \b #iomux_pin_cfg_t + */ +void mxc_free_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg); + +/*! + * This function enables/disables the general purpose function for a particular + * signal. + * + * @param gp one signal as defined in \b #iomux_gp_func_t + * @param en \b #true to enable; \b #false to disable + */ +void mxc_iomux_set_gpr(iomux_gp_func_t gp, int en); + +/*! + * This function configures the pad value for a IOMUX pin. + * + * @param pin a pin number as defined in \b #iomux_pin_name_t + * @param config the ORed value of elements defined in \b + * #iomux_pad_config_t + */ +void mxc_iomux_set_pad(iomux_pin_name_t pin, u32 config); + +/*! + * This function configures input path. + * + * @param input index of input select register as defined in \b + * #iomux_input_select_t + * @param config the binary value of elements defined in \b + * #iomux_input_cfg_t + */ +void mxc_iomux_set_input(iomux_input_select_t input, u32 config); +#endif diff --git a/include/asm-arm/arch-mx25/mx25-regs.h b/include/asm-arm/arch-mx25/mx25-regs.h new file mode 100644 index 0000000000..77fb4f5b22 --- /dev/null +++ b/include/asm-arm/arch-mx25/mx25-regs.h @@ -0,0 +1,380 @@ +/* + * + * (c) 2007 Pengutronix, Sascha Hauer + * + * (C) Copyright 2009 Freescale Semiconductor + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ASM_ARCH_MX25_REGS_H +#define __ASM_ARCH_MX25_REGS_H + +#define __REG(x) (*((volatile u32 *)(x))) +#define __REG16(x) (*((volatile u16 *)(x))) +#define __REG8(x) (*((volatile u8 *)(x))) + +/* + * AIPS 1 + */ +#define AIPS1_BASE 0x43F00000 +#define AIPS1_CTRL_BASE AIPS1_BASE +#define MAX_BASE 0x43F04000 +#define CLKCTL_BASE 0x43F08000 +#define ETB_SLOT4_BASE 0x43F0C000 +#define ETB_SLOT5_BASE 0x43F1000l +#define ECT_CTIO_BASE 0x43F18000 +#define I2C1_BASE 0x43F80000 +#define I2C3_BASE 0x43F84000 +#define CAN1_BASE 0x43F88000 +#define CAN2_BASE 0x43F8C000 +#define UART1_BASE 0x43F90000 +#define UART2_BASE 0x43F94000 +#define I2C2_BASE 0x43F98000 +#define OWIRE_BASE 0x43F9C000 +#define CSPI1_BASE 0x43FA4000 +#define KPP_BASE 0x43FA8000 +#define IOMUXC_BASE 0x43FAC000 +#define AUDMUX_BASE 0x43FB0000 +#define ECT_IP1_BASE 0x43FB8000 +#define ECT_IP2_BASE 0x43FBC000 + +/* + * SPBA + */ +#define SPBA_BASE 0x50000000 +#define CSPI3_BASE 0x50040000 +#define UART4_BASE 0x50008000 +#define UART3_BASE 0x5000C000 +#define CSPI2_BASE 0x50010000 +#define SSI2_BASE 0x50014000 +#define ESAI_BASE 0x50018000 +#define ATA_DMA_BASE 0x50020000 +#define SIM1_BASE 0x50024000 +#define SIM2_BASE 0x50028000 +#define UART5_BASE 0x5002C000 +#define TSC_BASE 0x50030000 +#define SSI1_BASE 0x50034000 +#define FEC_BASE 0x50038000 +#define SOC_FEC FEC_BASE +#define SPBA_CTRL_BASE 0x5003C000 + +/* + * AIPS 2 + */ +#define AIPS2_BASE 0x53F00000 +#define AIPS2_CTRL_BASE AIPS2_BASE +#define CCM_BASE 0x53F80000 +#define GPT4_BASE 0x53F84000 +#define GPT3_BASE 0x53F88000 +#define GPT2_BASE 0x53F8C000 +#define GPT1_BASE 0x53F90000 +#define EPIT1_BASE 0x53F94000 +#define EPIT2_BASE 0x53F98000 +#define GPIO4_BASE 0x53F9C000 +#define PWM2_BASE 0x53FA0000 +#define GPIO3_BASE 0x53FA4000 +#define PWM3_BASE 0x53FA8000 +#define SCC_BASE 0x53FAC000 +#define SCM_BASE 0x53FAE000 +#define SMN_BASE 0x53FAF000 +#define RNGD_BASE 0x53FB0000 +#define MMC_SDHC1_BASE 0x53FB4000 +#define MMC_SDHC2_BASE 0x53FB8000 +#define ESDHC1_REG_BASE MMC_SDHC1_BASE +#define LCDC_BASE 0x53FBC000 +#define SLCDC_BASE 0x53FC0000 +#define PWM4_BASE 0x53FC8000 +#define GPIO1_BASE 0x53FCC000 +#define GPIO2_BASE 0x53FD0000 +#define SDMA_BASE 0x53FD4000 +#define WDOG_BASE 0x53FDC000 +#define PWM1_BASE 0x53FE0000 +#define RTIC_BASE 0x53FEC000 +#define IIM_BASE 0x53FF0000 +#define USB_BASE 0x53FF4000 +#define CSI_BASE 0x53FF8000 +#define DRYICE_BASE 0x53FFC000 + +/* + * ROMPATCH and ASIC + */ +#define ROMPATCH_BASE 0x60000000 +#define ROMPATCH_REV 0x40 +#define ASIC_BASE 0x68000000 + +#define RAM_BASE 0x78000000 + +/* + * NAND, SDRAM, WEIM, M3IF, EMI controllers + */ +#define EXT_MEM_CTRL_BASE 0xB8000000 +#define ESDCTL_BASE 0xB8001000 +#define WEIM_BASE 0xB8002000 +#define WEIM_CTRL_CS0 WEIM_BASE +#define WEIM_CTRL_CS1 (WEIM_BASE + 0x10) +#define WEIM_CTRL_CS2 (WEIM_BASE + 0x20) +#define WEIM_CTRL_CS3 (WEIM_BASE + 0x30) +#define WEIM_CTRL_CS4 (WEIM_BASE + 0x40) +#define WEIM_CTRL_CS5 (WEIM_BASE + 0x50) +#define M3IF_BASE 0xB8003000 +#define EMI_BASE 0xB8004000 + +#define NFC_BASE_ADDR 0xBB000000 +/* + * Memory regions and CS + */ +#define CSD0_BASE 0x80000000 +#define CSD1_BASE 0x90000000 +#define CS0_BASE 0xA0000000 +#define CS1_BASE 0xA8000000 +#define CS2_BASE 0xB0000000 +#define CS3_BASE 0xB2000000 +#define CS4_BASE 0xB4000000 +#define CS5_BASE 0xB6000000 + +/* CCM */ +#define CCM_MPCTL (CCM_BASE + 0x00) +#define CCM_UPCTL (CCM_BASE + 0x04) +#define CCM_CCTL (CCM_BASE + 0x08) +#define CCM_CGR0 (CCM_BASE + 0x0C) +#define CCM_CGR1 (CCM_BASE + 0x10) +#define CCM_CGR2 (CCM_BASE + 0x14) +#define CCM_PCDR0 (CCM_BASE + 0x18) +#define CCM_PCDR1 (CCM_BASE + 0x1C) +#define CCM_PCDR2 (CCM_BASE + 0x20) +#define CCM_PCDR3 (CCM_BASE + 0x24) +#define CCM_RCSR (CCM_BASE + 0x28) +#define CCM_CRDR (CCM_BASE + 0x2C) +#define CCM_DCVR0 (CCM_BASE + 0x30) +#define CCM_DCVR1 (CCM_BASE + 0x34) +#define CCM_DCVR2 (CCM_BASE + 0x38) +#define CCM_DCVR3 (CCM_BASE + 0x3C) +#define CCM_LTR0 (CCM_BASE + 0x40) +#define CCM_LTR1 (CCM_BASE + 0x44) +#define CCM_LTR2 (CCM_BASE + 0x48) +#define CCM_LTR3 (CCM_BASE + 0x4C) +#define CCM_LTBR0 (CCM_BASE + 0x50) +#define CCM_LTBR1 (CCM_BASE + 0x54) +#define CCM_PCMR0 (CCM_BASE + 0x58) +#define CCM_PCMR1 (CCM_BASE + 0x5C) +#define CCM_PCMR2 (CCM_BASE + 0x60) +#define CCM_MCR (CCM_BASE + 0x64) +#define CCM_LPIMR0 (CCM_BASE + 0x68) +#define CCM_LPIMR1 (CCM_BASE + 0x6C) + +#define CRM_CCTL_ARM_SRC (1 << 14) +#define CRM_CCTL_AHB_OFFSET 28 + + +#define FREQ_24MHZ 24000000 +#define PLL_REF_CLK FREQ_24MHZ + +/* + * FIXME - Constants verified up to this point. + * Offsets and derived constants below should be confirmed. + */ + +#define CLKMODE_AUTO 0 +#define CLKMODE_CONSUMER 1 + +/* WEIM - CS0 */ +#define CSCRU 0x00 +#define CSCRL 0x04 +#define CSCRA 0x08 + +#define CHIP_REV_1_0 0x0 /* PASS 1.0 */ +#define CHIP_REV_1_1 0x1 /* PASS 1.1 */ +#define CHIP_REV_2_0 0x2 /* PASS 2.0 */ +#define CHIP_LATEST CHIP_REV_1_1 + +#define IIM_STAT 0x00 +#define IIM_STAT_BUSY (1 << 7) +#define IIM_STAT_PRGD (1 << 1) +#define IIM_STAT_SNSD (1 << 0) +#define IIM_STATM 0x04 +#define IIM_ERR 0x08 +#define IIM_ERR_PRGE (1 << 7) +#define IIM_ERR_WPE (1 << 6) +#define IIM_ERR_OPE (1 << 5) +#define IIM_ERR_RPE (1 << 4) +#define IIM_ERR_WLRE (1 << 3) +#define IIM_ERR_SNSE (1 << 2) +#define IIM_ERR_PARITYE (1 << 1) +#define IIM_EMASK 0x0C +#define IIM_FCTL 0x10 +#define IIM_UAF 0x14 +#define IIM_LA 0x18 +#define IIM_SDAT 0x1C +#define IIM_PREV 0x20 +#define IIM_SREV 0x24 +#define IIM_PREG_P 0x28 +#define IIM_SCS0 0x2C +#define IIM_SCS1 0x30 +#define IIM_SCS2 0x34 +#define IIM_SCS3 0x38 + +#define EPIT_BASE EPIT1_BASE +#define EPITCR 0x00 +#define EPITSR 0x04 +#define EPITLR 0x08 +#define EPITCMPR 0x0C +#define EPITCNR 0x10 + +#define GPT_BASE GPT1_BASE +/*#define GPTCR 0x00 +#define GPTPR 0x04 +#define GPTSR 0x08 +#define GPTIR 0x0C +#define GPTOCR1 0x10 +#define GPTOCR2 0x14 +#define GPTOCR3 0x18 +#define GPTICR1 0x1C +#define GPTICR2 0x20 +#define GPTCNT 0x24*/ + +/* ESDCTL */ +#define ESDCTL_ESDCTL0 0x00 +#define ESDCTL_ESDCFG0 0x04 +#define ESDCTL_ESDCTL1 0x08 +#define ESDCTL_ESDCFG1 0x0C +#define ESDCTL_ESDMISC 0x10 + +/* DRYICE */ +#define DRYICE_DTCMR 0x00 +#define DRYICE_DTCLR 0x04 +#define DRYICE_DCAMR 0x08 +#define DRYICE_DCALR 0x0C +#define DRYICE_DCR 0x10 +#define DRYICE_DSR 0x14 +#define DRYICE_DIER 0x18 +#define DRYICE_DMCR 0x1C +#define DRYICE_DKSR 0x20 +#define DRYICE_DKCR 0x24 +#define DRYICE_DTCR 0x28 +#define DRYICE_DACR 0x2C +#define DRYICE_DGPR 0x3C +#define DRYICE_DPKR0 0x40 +#define DRYICE_DPKR1 0x44 +#define DRYICE_DPKR2 0x48 +#define DRYICE_DPKR3 0x4C +#define DRYICE_DPKR4 0x50 +#define DRYICE_DPKR5 0x54 +#define DRYICE_DPKR6 0x58 +#define DRYICE_DPKR7 0x5C +#define DRYICE_DRKR0 0x60 +#define DRYICE_DRKR1 0x64 +#define DRYICE_DRKR2 0x68 +#define DRYICE_DRKR3 0x6C +#define DRYICE_DRKR4 0x70 +#define DRYICE_DRKR5 0x74 +#define DRYICE_DRKR6 0x78 +#define DRYICE_DRKR7 0x7C + +/* GPIO */ +#define GPIO_DR 0x00 +#define GPIO_GDIR 0x04 +#define GPIO_PSR0 0x08 +#define GPIO_ICR1 0x0C +#define GPIO_ICR2 0x10 +#define GPIO_IMR 0x14 +#define GPIO_ISR 0x18 +#define GPIO_EDGE_SEL 0x1C + + +#if (PLL_REF_CLK != 24000000) +#error Wrong PLL reference clock! The following macros will not work. +#endif + +/* Assuming 24MHz input clock */ +/* PD MFD MFI MFN */ +#define MPCTL_PARAM_399 (((1-1) << 26) + ((16-1) << 16) + \ + (8 << 10) + (5 << 0)) +#define MPCTL_PARAM_532 ((1 << 31) + ((1-1) << 26) + \ + ((12-1) << 16) + (11 << 10) + (1 << 0)) +#define MPCTL_PARAM_665 (((1-1) << 26) + ((48-1) << 16) + \ + (13 << 10) + (41 << 0)) + +/* UPCTL PD MFD MFI MFN */ +#define UPCTL_PARAM_300 (((1-1) << 26) + ((4-1) << 16) + \ + (6 << 10) + (1 << 0)) + +#define NFC_V1_1 + +#define NAND_REG_BASE (NFC_BASE + 0x1E00) +#define NFC_BUFSIZE_REG_OFF (0 + 0x00) +#define RAM_BUFFER_ADDRESS_REG_OFF (0 + 0x04) +#define NAND_FLASH_ADD_REG_OFF (0 + 0x06) +#define NAND_FLASH_CMD_REG_OFF (0 + 0x08) +#define NFC_CONFIGURATION_REG_OFF (0 + 0x0A) +#define ECC_STATUS_RESULT_REG_OFF (0 + 0x0C) +#define ECC_RSLT_MAIN_AREA_REG_OFF (0 + 0x0E) +#define ECC_RSLT_SPARE_AREA_REG_OFF (0 + 0x10) +#define NF_WR_PROT_REG_OFF (0 + 0x12) +#define NAND_FLASH_WR_PR_ST_REG_OFF (0 + 0x18) +#define NAND_FLASH_CONFIG1_REG_OFF (0 + 0x1A) +#define NAND_FLASH_CONFIG2_REG_OFF (0 + 0x1C) +#define UNLOCK_START_BLK_ADD_REG_OFF (0 + 0x20) +#define UNLOCK_END_BLK_ADD_REG_OFF (0 + 0x22) +#define RAM_BUFFER_ADDRESS_RBA_3 0x3 +#define NFC_BUFSIZE_1KB 0x0 +#define NFC_BUFSIZE_2KB 0x1 +#define NFC_CONFIGURATION_UNLOCKED 0x2 +#define ECC_STATUS_RESULT_NO_ERR 0x0 +#define ECC_STATUS_RESULT_1BIT_ERR 0x1 +#define ECC_STATUS_RESULT_2BIT_ERR 0x2 +#define NF_WR_PROT_UNLOCK 0x4 +#define NAND_FLASH_CONFIG1_FORCE_CE (1 << 7) +#define NAND_FLASH_CONFIG1_RST (1 << 6) +#define NAND_FLASH_CONFIG1_BIG (1 << 5) +#define NAND_FLASH_CONFIG1_INT_MSK (1 << 4) +#define NAND_FLASH_CONFIG1_ECC_EN (1 << 3) +#define NAND_FLASH_CONFIG1_SP_EN (1 << 2) +#define NAND_FLASH_CONFIG2_INT_DONE (1 << 15) +#define NAND_FLASH_CONFIG2_FDO_PAGE (0 << 3) +#define NAND_FLASH_CONFIG2_FDO_ID (2 << 3) +#define NAND_FLASH_CONFIG2_FDO_STATUS (4 << 3) +#define NAND_FLASH_CONFIG2_FDI_EN (1 << 2) +#define NAND_FLASH_CONFIG2_FADD_EN (1 << 1) +#define NAND_FLASH_CONFIG2_FCMD_EN (1 << 0) +#define FDO_PAGE_SPARE_VAL 0x8 +#define NAND_BUF_NUM 8 + +#define MXC_NAND_BASE_DUMMY 0x00000000 +#define MXC_MMC_BASE_DUMMY 0x00000000 +#define NOR_FLASH_BOOT 0 +#define NAND_FLASH_BOOT 0x10000000 +#define SDRAM_NON_FLASH_BOOT 0x20000000 +#define MMC_FLASH_BOOT 0x40000000 +#define MXCBOOT_FLAG_REG (CSI_BASE_ADDR + 0x28) +#define MXCFIS_NOTHING 0x00000000 +#define MXCFIS_NAND 0x10000000 +#define MXCFIS_NOR 0x20000000 +#define MXCFIS_MMC 0x40000000 +#define MXCFIS_FLAG_REG (CSI_BASE_ADDR + 0x2C) + +/*! + * * NFMS bit in RCSR register for pagesize of nandflash + * */ +#define NFMS (*((volatile u32 *)(CCM_BASE+0x28))) +#define NFMS_BIT 8 +#define NFMS_NF_DWIDTH 14 +#define NFMS_NF_PG_SZ 8 + +#endif diff --git a/include/asm-arm/arch-mx25/mx25.h b/include/asm-arm/arch-mx25/mx25.h new file mode 100644 index 0000000000..aa3dac039b --- /dev/null +++ b/include/asm-arm/arch-mx25/mx25.h @@ -0,0 +1,46 @@ +/* + * + * (c) 2007 Pengutronix, Sascha Hauer + * + * (C) Copyright 2009 Freescale Semiconductor + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ASM_ARCH_MX25_H +#define __ASM_ARCH_MX25_H +#ifndef __ASSEMBLER__ + +#define GPIO_PORT_NUM 3 +#define GPIO_NUM_PIN 32 + +enum mxc_clock { + MXC_ARM_CLK = 0, + MXC_AHB_CLK, + MXC_IPG_CLK, + MXC_IPG_PERCLK, + MXC_UART_CLK, + MXC_CSPI_CLK, + MXC_ESDHC_CLK, +}; + +extern unsigned int mx25_get_ipg_clk(void); +extern unsigned int mxc_get_clock(enum mxc_clock clk); +#endif +#endif /* __ASM_ARCH_MX25_H */ diff --git a/include/asm-arm/arch-mx25/mx25_pins.h b/include/asm-arm/arch-mx25/mx25_pins.h new file mode 100644 index 0000000000..984f55d572 --- /dev/null +++ b/include/asm-arm/arch-mx25/mx25_pins.h @@ -0,0 +1,259 @@ +/* + * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#ifndef __ASM_ARCH_MXC_MX25_PINS_H__ +#define __ASM_ARCH_MXC_MX25_PINS_H__ + +/*! + * @file arch-mxc/mx25_pins.h + * + * @brief MX25 I/O Pin List + * + * @ingroup GPIO_MX25 + */ + +#ifndef __ASSEMBLY__ + +/*! + * @name IOMUX/PAD Bit field definitions + */ + +/*! @{ */ + +/*! + * In order to identify pins more effectively, each mux-controlled pin's + * enumerated value is constructed in the following way: + * + * ------------------------------------------------------------------- + * 31-29 | 28 - 24 |23 - 21| 20 - 10| 9 - 0 + * ------------------------------------------------------------------- + * IO_P | IO_I | RSVD | PAD_I | MUX_I + * ------------------------------------------------------------------- + * + * Bit 0 to 7 contains MUX_I used to identify the register + * offset (base is IOMUX_module_base ) defined in the Section + * "sw_pad_ctl & sw_mux_ctl details" of the IC Spec. Similar field + * definitions are used for the pad control register. For example, + * MX25_PIN_A14 is defined in the enumeration: + * ( 0x10 << MUX_I) | ( 0x230 << PAD_I) + * So the absolute address is: IOMUX_module_base + 0x10. + * The pad control register offset is: 0x230. + */ + +/*! + * Starting bit position within each entry of \b iomux_pins to represent the + * MUX control register offset + */ +#define MUX_I 0 +/*! + * Starting bit position within each entry of \b iomux_pins to represent the + * PAD control register offset + */ +#define PAD_I 10 + +/*! + * Starting bit position within each entry of \b iomux_pins to represent the + * reserved filed + */ +#define RSVD_I 21 + +#define MUX_IO_P 29 +#define MUX_IO_I 24 +#define IOMUX_TO_GPIO(pin) ((((unsigned int)pin >> MUX_IO_P) * \ + GPIO_NUM_PIN) + ((pin >> MUX_IO_I) &\ + ((1 << (MUX_IO_P - MUX_IO_I)) - 1))) +#define IOMUX_TO_IRQ(pin) (MXC_GPIO_INT_BASE + IOMUX_TO_GPIO(pin)) +#define GPIO_TO_PORT(n) (n / GPIO_NUM_PIN) +#define GPIO_TO_INDEX(n) (n % GPIO_NUM_PIN) + +#define NON_GPIO_I 0x7 +#define PIN_TO_MUX_MASK ((1<<(PAD_I - MUX_I)) - 1) +#define PIN_TO_PAD_MASK ((1<<(RSVD_I - PAD_I)) - 1) +#define NON_MUX_I PIN_TO_MUX_MASK + +#define _MXC_BUILD_PIN(gp, gi, mi, pi) \ + (((gp) << MUX_IO_P) | ((gi) << MUX_IO_I) | \ + ((mi) << MUX_I) | ((pi) << PAD_I)) + +#define _MXC_BUILD_GPIO_PIN(gp, gi, mi, pi) \ + _MXC_BUILD_PIN(gp, gi, mi, pi) + +#define _MXC_BUILD_NON_GPIO_PIN(mi, pi) \ + _MXC_BUILD_PIN(NON_GPIO_I, 0, mi, pi) + +#define PIN_TO_IOMUX_MUX(pin) ((pin >> MUX_I) & PIN_TO_MUX_MASK) +#define PIN_TO_IOMUX_PAD(pin) ((pin >> PAD_I) & PIN_TO_PAD_MASK) + +/*! @} End IOMUX/PAD Bit field definitions */ + +typedef enum iomux_pins { + MX25_PIN_A10 = _MXC_BUILD_GPIO_PIN(3, 0, 0x8, 0x0), + MX25_PIN_A13 = _MXC_BUILD_GPIO_PIN(3, 1, 0x0c, 0x22C), + MX25_PIN_A14 = _MXC_BUILD_GPIO_PIN(1, 0, 0x10, 0x230), + MX25_PIN_A15 = _MXC_BUILD_GPIO_PIN(1, 1, 0x14, 0x234), + MX25_PIN_A16 = _MXC_BUILD_GPIO_PIN(1, 2, 0x18, 0x0), + MX25_PIN_A17 = _MXC_BUILD_GPIO_PIN(1, 3, 0x1c, 0x238), + MX25_PIN_A18 = _MXC_BUILD_GPIO_PIN(1, 4, 0x20, 0x23c), + MX25_PIN_A19 = _MXC_BUILD_GPIO_PIN(1, 5, 0x24, 0x240), + MX25_PIN_A20 = _MXC_BUILD_GPIO_PIN(1, 6, 0x28, 0x244), + MX25_PIN_A21 = _MXC_BUILD_GPIO_PIN(1, 7, 0x2c, 0x248), + MX25_PIN_A22 = _MXC_BUILD_GPIO_PIN(1, 8, 0x30, 0x0), + MX25_PIN_A23 = _MXC_BUILD_GPIO_PIN(1, 9, 0x34, 0x24c), + MX25_PIN_A24 = _MXC_BUILD_GPIO_PIN(1, 10, 0x38, 0x250), + MX25_PIN_A25 = _MXC_BUILD_GPIO_PIN(1, 11, 0x3c, 0x254), + MX25_PIN_EB0 = _MXC_BUILD_GPIO_PIN(1, 12, 0x40, 0x258), + MX25_PIN_EB1 = _MXC_BUILD_GPIO_PIN(1, 13, 0x44, 0x25c), + MX25_PIN_OE = _MXC_BUILD_GPIO_PIN(1, 14, 0x48, 0x260), + MX25_PIN_CS0 = _MXC_BUILD_GPIO_PIN(3, 2, 0x4c, 0x0), + MX25_PIN_CS1 = _MXC_BUILD_GPIO_PIN(3, 3, 0x50, 0x0), + MX25_PIN_CS4 = _MXC_BUILD_GPIO_PIN(2, 20, 0x54, 0x264), + MX25_PIN_CS5 = _MXC_BUILD_GPIO_PIN(2, 21, 0x58, 0x268), + MX25_PIN_NF_CE0 = _MXC_BUILD_GPIO_PIN(2, 22, 0x5c, 0x26c), + MX25_PIN_ECB = _MXC_BUILD_GPIO_PIN(2, 23, 0x60, 0x270), + MX25_PIN_LBA = _MXC_BUILD_GPIO_PIN(2, 24, 0x64, 0x274), + MX25_PIN_BCLK = _MXC_BUILD_GPIO_PIN(3, 4, 0x68, 0x0), + MX25_PIN_RW = _MXC_BUILD_GPIO_PIN(2, 25, 0x6c, 0x278), + MX25_PIN_NFWE_B = _MXC_BUILD_GPIO_PIN(2, 26, 0x70, 0x0), + MX25_PIN_NFRE_B = _MXC_BUILD_GPIO_PIN(2, 27, 0x74, 0x0), + MX25_PIN_NFALE = _MXC_BUILD_GPIO_PIN(2, 28, 0x78, 0x0), + MX25_PIN_NFCLE = _MXC_BUILD_GPIO_PIN(2, 29, 0x7c, 0x0), + MX25_PIN_NFWP_B = _MXC_BUILD_GPIO_PIN(2, 30, 0x80, 0x0), + MX25_PIN_NFRB = _MXC_BUILD_GPIO_PIN(2, 31, 0x84, 0x27c), + MX25_PIN_D15 = _MXC_BUILD_GPIO_PIN(3, 5, 0x88, 0x280), + MX25_PIN_D14 = _MXC_BUILD_GPIO_PIN(3, 6, 0x8c, 0x284), + MX25_PIN_D13 = _MXC_BUILD_GPIO_PIN(3, 7, 0x90, 0x288), + MX25_PIN_D12 = _MXC_BUILD_GPIO_PIN(3, 8, 0x94, 0x28c), + MX25_PIN_D11 = _MXC_BUILD_GPIO_PIN(3, 9, 0x98, 0x290), + MX25_PIN_D10 = _MXC_BUILD_GPIO_PIN(3, 10, 0x9c, 0x294), + MX25_PIN_D9 = _MXC_BUILD_GPIO_PIN(3, 11, 0xa0, 0x298), + MX25_PIN_D8 = _MXC_BUILD_GPIO_PIN(3, 12, 0xa4, 0x29c), + MX25_PIN_D7 = _MXC_BUILD_GPIO_PIN(3, 13, 0xa8, 0x2a0), + MX25_PIN_D6 = _MXC_BUILD_GPIO_PIN(3, 14, 0xac, 0x2a4), + MX25_PIN_D5 = _MXC_BUILD_GPIO_PIN(3, 15, 0xb0, 0x2a8), + MX25_PIN_D4 = _MXC_BUILD_GPIO_PIN(3, 16, 0xb4, 0x2ac), + MX25_PIN_D3 = _MXC_BUILD_GPIO_PIN(3, 17, 0xb8, 0x2b0), + MX25_PIN_D2 = _MXC_BUILD_GPIO_PIN(3, 18, 0xbc, 0x2b4), + MX25_PIN_D1 = _MXC_BUILD_GPIO_PIN(3, 19, 0xc0, 0x2b8), + MX25_PIN_D0 = _MXC_BUILD_GPIO_PIN(3, 20, 0xc4, 0x2bc), + MX25_PIN_LD0 = _MXC_BUILD_GPIO_PIN(1, 15, 0xc8, 0x2c0), + MX25_PIN_LD1 = _MXC_BUILD_GPIO_PIN(1, 16, 0xcc, 0x2c4), + MX25_PIN_LD2 = _MXC_BUILD_GPIO_PIN(1, 17, 0xd0, 0x2c8), + MX25_PIN_LD3 = _MXC_BUILD_GPIO_PIN(1, 18, 0xd4, 0x2cc), + MX25_PIN_LD4 = _MXC_BUILD_GPIO_PIN(1, 19, 0xd8, 0x2d0), + MX25_PIN_LD5 = _MXC_BUILD_GPIO_PIN(0, 19, 0xdc, 0x2d4), + MX25_PIN_LD6 = _MXC_BUILD_GPIO_PIN(0, 20, 0xe0, 0x2d8), + MX25_PIN_LD7 = _MXC_BUILD_GPIO_PIN(0, 21, 0xe4, 0x2dc), + MX25_PIN_LD8 = _MXC_BUILD_NON_GPIO_PIN(0xe8, 0x2e0), + MX25_PIN_LD9 = _MXC_BUILD_NON_GPIO_PIN(0xec, 0x2e4), + MX25_PIN_LD10 = _MXC_BUILD_NON_GPIO_PIN(0xf0, 0x2e8), + MX25_PIN_LD11 = _MXC_BUILD_NON_GPIO_PIN(0xf4, 0x2ec), + MX25_PIN_LD12 = _MXC_BUILD_NON_GPIO_PIN(0xf8, 0x2f0), + MX25_PIN_LD13 = _MXC_BUILD_NON_GPIO_PIN(0xfc, 0x2f4), + MX25_PIN_LD14 = _MXC_BUILD_NON_GPIO_PIN(0x100, 0x2f8), + MX25_PIN_LD15 = _MXC_BUILD_NON_GPIO_PIN(0x104, 0x2fc), + MX25_PIN_HSYNC = _MXC_BUILD_GPIO_PIN(0, 22, 0x108, 0x300), + MX25_PIN_VSYNC = _MXC_BUILD_GPIO_PIN(0, 23, 0x10c, 0x304), + MX25_PIN_LSCLK = _MXC_BUILD_GPIO_PIN(0, 24, 0x110, 0x308), + MX25_PIN_OE_ACD = _MXC_BUILD_GPIO_PIN(0, 25, 0x114, 0x30c), + MX25_PIN_CONTRAST = _MXC_BUILD_NON_GPIO_PIN(0x118, 0x310), + MX25_PIN_PWM = _MXC_BUILD_GPIO_PIN(0, 26, 0x11c, 0x314), + MX25_PIN_CSI_D2 = _MXC_BUILD_GPIO_PIN(0, 27, 0x120, 0x318), + MX25_PIN_CSI_D3 = _MXC_BUILD_GPIO_PIN(0, 28, 0x124, 0x31c), + MX25_PIN_CSI_D4 = _MXC_BUILD_GPIO_PIN(0, 29, 0x128, 0x320), + MX25_PIN_CSI_D5 = _MXC_BUILD_GPIO_PIN(0, 30, 0x12c, 0x324), + MX25_PIN_CSI_D6 = _MXC_BUILD_GPIO_PIN(0, 31, 0x130, 0x328), + MX25_PIN_CSI_D7 = _MXC_BUILD_GPIO_PIN(0, 6, 0x134, 0x32c), + MX25_PIN_CSI_D8 = _MXC_BUILD_GPIO_PIN(0, 7, 0x138, 0x330), + MX25_PIN_CSI_D9 = _MXC_BUILD_GPIO_PIN(3, 21, 0x13c, 0x334), + MX25_PIN_CSI_MCLK = _MXC_BUILD_GPIO_PIN(0, 8, 0x140, 0x338), + MX25_PIN_CSI_VSYNC = _MXC_BUILD_GPIO_PIN(0, 9, 0x144, 0x33c), + MX25_PIN_CSI_HSYNC = _MXC_BUILD_GPIO_PIN(0, 10, 0x148, 0x340), + MX25_PIN_CSI_PIXCLK = _MXC_BUILD_GPIO_PIN(0, 11, 0x14c, 0x344), + MX25_PIN_I2C1_CLK = _MXC_BUILD_GPIO_PIN(0, 12, 0x150, 0x348), + MX25_PIN_I2C1_DAT = _MXC_BUILD_GPIO_PIN(0, 13, 0x154, 0x34c), + MX25_PIN_CSPI1_MOSI = _MXC_BUILD_GPIO_PIN(0, 14, 0x158, 0x350), + MX25_PIN_CSPI1_MISO = _MXC_BUILD_GPIO_PIN(0, 15, 0x15c, 0x354), + MX25_PIN_CSPI1_SS0 = _MXC_BUILD_GPIO_PIN(0, 16, 0x160, 0x358), + MX25_PIN_CSPI1_SS1 = _MXC_BUILD_GPIO_PIN(0, 17, 0x164, 0x35c), + MX25_PIN_CSPI1_SCLK = _MXC_BUILD_GPIO_PIN(0, 18, 0x168, 0x360), + MX25_PIN_CSPI1_RDY = _MXC_BUILD_GPIO_PIN(1, 22, 0x16c, 0x364), + MX25_PIN_UART1_RXD = _MXC_BUILD_GPIO_PIN(3, 22, 0x170, 0x368), + MX25_PIN_UART1_TXD = _MXC_BUILD_GPIO_PIN(3, 23, 0x174, 0x36c), + MX25_PIN_UART1_RTS = _MXC_BUILD_GPIO_PIN(3, 24, 0x178, 0x370), + MX25_PIN_UART1_CTS = _MXC_BUILD_GPIO_PIN(3, 25, 0x17c, 0x374), + MX25_PIN_UART2_RXD = _MXC_BUILD_GPIO_PIN(3, 26, 0x180, 0x378), + MX25_PIN_UART2_TXD = _MXC_BUILD_GPIO_PIN(3, 27, 0x184, 0x37c), + MX25_PIN_UART2_RTS = _MXC_BUILD_GPIO_PIN(3, 28, 0x188, 0x380), + MX25_PIN_UART2_CTS = _MXC_BUILD_GPIO_PIN(3, 29, 0x18c, 0x384), + MX25_PIN_SD1_CMD = _MXC_BUILD_GPIO_PIN(1, 23, 0x190, 0x388), + MX25_PIN_SD1_CLK = _MXC_BUILD_GPIO_PIN(1, 24, 0x194, 0x38c), + MX25_PIN_SD1_DATA0 = _MXC_BUILD_GPIO_PIN(1, 25, 0x198, 0x390), + MX25_PIN_SD1_DATA1 = _MXC_BUILD_GPIO_PIN(1, 26, 0x19c, 0x394), + MX25_PIN_SD1_DATA2 = _MXC_BUILD_GPIO_PIN(1, 27, 0x1a0, 0x398), + MX25_PIN_SD1_DATA3 = _MXC_BUILD_GPIO_PIN(1, 28, 0x1a4, 0x39c), + MX25_PIN_KPP_ROW0 = _MXC_BUILD_GPIO_PIN(1, 29, 0x1a8, 0x3a0), + MX25_PIN_KPP_ROW1 = _MXC_BUILD_GPIO_PIN(1, 30, 0x1ac, 0x3a4), + MX25_PIN_KPP_ROW2 = _MXC_BUILD_GPIO_PIN(1, 31, 0x1b0, 0x3a8), + MX25_PIN_KPP_ROW3 = _MXC_BUILD_GPIO_PIN(2, 0, 0x1b4, 0x3ac), + MX25_PIN_KPP_COL0 = _MXC_BUILD_GPIO_PIN(2, 1, 0x1b8, 0x3b0), + MX25_PIN_KPP_COL1 = _MXC_BUILD_GPIO_PIN(2, 2, 0x1bc, 0x3b4), + MX25_PIN_KPP_COL2 = _MXC_BUILD_GPIO_PIN(2, 3, 0x1c0, 0x3b8), + MX25_PIN_KPP_COL3 = _MXC_BUILD_GPIO_PIN(2, 4, 0x1c4, 0x3bc), + MX25_PIN_FEC_MDC = _MXC_BUILD_GPIO_PIN(2, 5, 0x1c8, 0x3c0), + MX25_PIN_FEC_MDIO = _MXC_BUILD_GPIO_PIN(2, 6, 0x1cc, 0x3c4), + MX25_PIN_FEC_TDATA0 = _MXC_BUILD_GPIO_PIN(2, 7, 0x1d0, 0x3c8), + MX25_PIN_FEC_TDATA1 = _MXC_BUILD_GPIO_PIN(2, 8, 0x1d4, 0x3cc), + MX25_PIN_FEC_TX_EN = _MXC_BUILD_GPIO_PIN(2, 9, 0x1d8, 0x3d0), + MX25_PIN_FEC_RDATA0 = _MXC_BUILD_GPIO_PIN(2, 10, 0x1dc, 0x3d4), + MX25_PIN_FEC_RDATA1 = _MXC_BUILD_GPIO_PIN(2, 11, 0x1e0, 0x3d8), + MX25_PIN_FEC_RX_DV = _MXC_BUILD_GPIO_PIN(2, 12, 0x1e4, 0x3dc), + MX25_PIN_FEC_TX_CLK = _MXC_BUILD_GPIO_PIN(2, 13, 0x1e8, 0x3e0), + MX25_PIN_RTCK = _MXC_BUILD_GPIO_PIN(2, 14, 0x1ec, 0x3e4), + MX25_PIN_DE_B = _MXC_BUILD_GPIO_PIN(1, 20, 0x1f0, 0x3ec), + MX25_PIN_TDO = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x3e8), + MX25_PIN_GPIO_A = _MXC_BUILD_GPIO_PIN(0, 0, 0x1f4, 0x3f0), + MX25_PIN_GPIO_B = _MXC_BUILD_GPIO_PIN(0, 1, 0x1f8, 0x3f4), + MX25_PIN_GPIO_C = _MXC_BUILD_GPIO_PIN(0, 2, 0x1fc, 0x3f8), + MX25_PIN_GPIO_D = _MXC_BUILD_GPIO_PIN(0, 3, 0x200, 0x3fc), + MX25_PIN_GPIO_E = _MXC_BUILD_GPIO_PIN(0, 4, 0x204, 0x400), + MX25_PIN_GPIO_F = _MXC_BUILD_GPIO_PIN(0, 5, 0x208, 0x404), + MX25_PIN_EXT_ARMCLK = _MXC_BUILD_GPIO_PIN(2, 15, 0x20c, 0x0), + MX25_PIN_UPLL_BYPCLK = _MXC_BUILD_GPIO_PIN(2, 16, 0x210, 0x0), + MX25_PIN_VSTBY_REQ = _MXC_BUILD_GPIO_PIN(2, 17, 0x214, 0x408), + MX25_PIN_VSTBY_ACK = _MXC_BUILD_GPIO_PIN(2, 18, 0x218, 0x40c), + MX25_PIN_POWER_FAIL = _MXC_BUILD_GPIO_PIN(2, 19, 0x21c, 0x410), + MX25_PIN_CLKO = _MXC_BUILD_GPIO_PIN(1, 21, 0x220, 0x414), + MX25_PIN_BOOT_MODE0 = _MXC_BUILD_GPIO_PIN(3, 30, 0x224, 0x0), + MX25_PIN_BOOT_MODE1 = _MXC_BUILD_GPIO_PIN(3, 31, 0x228, 0x0), + + MX25_PIN_CTL_GRP_DVS_MISC = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x418), + MX25_PIN_CTL_GRP_DSE_FEC = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x41c), + MX25_PIN_CTL_GRP_DVS_JTAG = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x420), + MX25_PIN_CTL_GRP_DSE_NFC = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x424), + MX25_PIN_CTL_GRP_DSE_CSI = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x428), + MX25_PIN_CTL_GRP_DSE_WEIM = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x42c), + MX25_PIN_CTL_GRP_DSE_DDR = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x430), + MX25_PIN_CTL_GRP_DVS_CRM = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x434), + MX25_PIN_CTL_GRP_DSE_KPP = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x438), + MX25_PIN_CTL_GRP_DSE_SDHC1 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x43c), + MX25_PIN_CTL_GRP_DSE_LCD = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x440), + MX25_PIN_CTL_GRP_DSE_UART = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x444), + MX25_PIN_CTL_GRP_DVS_NFC = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x448), + MX25_PIN_CTL_GRP_DVS_CSI = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x44c), + MX25_PIN_CTL_GRP_DSE_CSPI1 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x450), + MX25_PIN_CTL_GRP_DDRTYPE = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x454), + MX25_PIN_CTL_GRP_DVS_SDHC1 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x458), + MX25_PIN_CTL_GRP_DVS_LCD = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x45c) +} iomux_pin_name_t; + +#endif +#endif diff --git a/include/asm-arm/arch-mx25/mxc_nand.h b/include/asm-arm/arch-mx25/mxc_nand.h new file mode 100644 index 0000000000..de273ac947 --- /dev/null +++ b/include/asm-arm/arch-mx25/mxc_nand.h @@ -0,0 +1,228 @@ +/* + * Copyright 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file mxc_nd2.h + * + * @brief This file contains the NAND Flash Controller register information. + * + * + * @ingroup NAND_MTD + */ + +#ifndef __MXC_NAND_H__ +#define __MXC_NAND_H__ + +#include + +#define IS_2K_PAGE_NAND ((mtd->writesize / info->num_of_intlv) \ + == NAND_PAGESIZE_2KB) +#define IS_4K_PAGE_NAND ((mtd->writesize / info->num_of_intlv) \ + == NAND_PAGESIZE_4KB) +#define IS_LARGE_PAGE_NAND ((mtd->writesize / info->num_of_intlv) > 512) + +#define GET_NAND_OOB_SIZE (mtd->oobsize / info->num_of_intlv) +#define GET_NAND_PAGE_SIZE (mtd->writesize / info->num_of_intlv) + +/* + * main area for bad block marker is in the last data section + * the spare area for swapped bad block marker is the second + * byte of last spare section + */ +#define NAND_SECTIONS (GET_NAND_PAGE_SIZE >> 9) +#define NAND_OOB_PER_SECTION (((GET_NAND_OOB_SIZE / NAND_SECTIONS) >> 1) << 1) +#define NAND_CHUNKS (GET_NAND_PAGE_SIZE / (512 + NAND_OOB_PER_SECTION)) + +#define BAD_BLK_MARKER_MAIN_OFFS \ + (GET_NAND_PAGE_SIZE - NAND_CHUNKS * NAND_OOB_PER_SECTION) + +#define BAD_BLK_MARKER_SP_OFFS (NAND_CHUNKS * SPARE_LEN) + +#define BAD_BLK_MARKER_OOB_OFFS (NAND_CHUNKS * NAND_OOB_PER_SECTION) + +#define BAD_BLK_MARKER_MAIN \ + ((u32)MAIN_AREA0 + BAD_BLK_MARKER_MAIN_OFFS) + +#define BAD_BLK_MARKER_SP \ + ((u32)SPARE_AREA0 + BAD_BLK_MARKER_SP_OFFS) + +#define NAND_PAGESIZE_2KB 2048 +#define NAND_PAGESIZE_4KB 4096 +#define NAND_MAX_PAGESIZE 4096 + +/* + * Addresses for NFC registers + */ +#define NFC_REG_BASE (NFC_BASE_ADDR + 0x1000) +#define NFC_BUF_ADDR (NFC_REG_BASE + 0xE04) +#define NFC_FLASH_ADDR (NFC_REG_BASE + 0xE06) +#define NFC_FLASH_CMD (NFC_REG_BASE + 0xE08) +#define NFC_CONFIG (NFC_REG_BASE + 0xE0A) +#define NFC_ECC_STATUS_RESULT (NFC_REG_BASE + 0xE0C) +#define NFC_SPAS (NFC_REG_BASE + 0xE10) +#define NFC_WRPROT (NFC_REG_BASE + 0xE12) +#define NFC_UNLOCKSTART_BLKADDR (NFC_REG_BASE + 0xE20) +#define NFC_UNLOCKEND_BLKADDR (NFC_REG_BASE + 0xE22) +#define NFC_CONFIG1 (NFC_REG_BASE + 0xE1A) +#define NFC_CONFIG2 (NFC_REG_BASE + 0xE1C) + +/*! + * Addresses for NFC RAM BUFFER Main area 0 + */ +#define MAIN_AREA0 (u16 *)(NFC_BASE_ADDR + 0x000) +#define MAIN_AREA1 (u16 *)(NFC_BASE_ADDR + 0x200) + +/*! + * Addresses for NFC SPARE BUFFER Spare area 0 + */ +#define SPARE_AREA0 (u16 *)(NFC_BASE_ADDR + 0x1000) +#define SPARE_LEN 64 +#define SPARE_COUNT 8 +#define SPARE_SIZE (SPARE_LEN * SPARE_COUNT) + + +#define SPAS_SHIFT (0) +#define SPAS_MASK (0xFF00) +#define IS_4BIT_ECC \ + ((raw_read(REG_NFC_ECC_MODE) & NFC_ECC_MODE_4) >> 0) + +#define NFC_SET_SPAS(v) \ + raw_write(((raw_read(REG_NFC_SPAS) & SPAS_MASK) | \ + ((v<> 1); \ + } \ +} while (0) + + +#define WRITE_NFC_IP_REG(val, reg) \ + raw_write((raw_read(REG_NFC_OPS_STAT) & ~NFC_OPS_STAT), \ + REG_NFC_OPS_STAT) + +#define GET_NFC_ECC_STATUS() \ + raw_read(REG_NFC_ECC_STATUS_RESULT); + +/*! + * Set INT to 0, Set 1 to specific operation bit, rest to 0 in LAUNCH_NFC + * Register for Specific operation + */ +#define NFC_CMD 0x1 +#define NFC_ADDR 0x2 +#define NFC_INPUT 0x4 +#define NFC_OUTPUT 0x8 +#define NFC_ID 0x10 +#define NFC_STATUS 0x20 + +/* Bit Definitions */ +#define NFC_OPS_STAT (1 << 15) +#define NFC_SP_EN (1 << 2) +#define NFC_ECC_EN (1 << 3) +#define NFC_INT_MSK (1 << 4) +#define NFC_BIG (1 << 5) +#define NFC_RST (1 << 6) +#define NFC_CE (1 << 7) +#define NFC_ONE_CYCLE (1 << 8) +#define NFC_BLS_LOCKED 0 +#define NFC_BLS_LOCKED_DEFAULT 1 +#define NFC_BLS_UNLCOKED 2 +#define NFC_WPC_LOCK_TIGHT 1 +#define NFC_WPC_LOCK (1 << 1) +#define NFC_WPC_UNLOCK (1 << 2) +#define NFC_FLASH_ADDR_SHIFT 0 +#define NFC_UNLOCK_END_ADDR_SHIFT 0 + +#define NFC_ECC_MODE_4 (1<<0) +#define NFC_ECC_MODE_8 (~(1<<0)) +#define NFC_SPAS_16 8 +#define NFC_SPAS_64 32 +#define NFC_SPAS_128 64 +#define NFC_SPAS_218 109 + +/* NFC Register Mapping */ +#define REG_NFC_OPS_STAT NFC_CONFIG2 +#define REG_NFC_INTRRUPT NFC_CONFIG1 +#define REG_NFC_FLASH_ADDR NFC_FLASH_ADDR +#define REG_NFC_FLASH_CMD NFC_FLASH_CMD +#define REG_NFC_OPS NFC_CONFIG2 +#define REG_NFC_SET_RBA NFC_BUF_ADDR +#define REG_NFC_ECC_EN NFC_CONFIG1 +#define REG_NFC_ECC_STATUS_RESULT NFC_ECC_STATUS_RESULT +#define REG_NFC_CE NFC_CONFIG1 +#define REG_NFC_SP_EN NFC_CONFIG1 +#define REG_NFC_BLS NFC_CONFIG +#define REG_NFC_WPC NFC_WRPROT +#define REG_START_BLKADDR NFC_UNLOCKSTART_BLKADDR +#define REG_END_BLKADDR NFC_UNLOCKEND_BLKADDR +#define REG_NFC_RST NFC_CONFIG1 +#define REG_NFC_ECC_MODE NFC_CONFIG1 +#define REG_NFC_SPAS NFC_SPAS + + +/* NFC V1/V2 Specific MACRO functions definitions */ + +#define raw_write(v, a) __raw_writew(v, a) +#define raw_read(a) __raw_readw(a) + +#define NFC_SET_BLS(val) val + +#define UNLOCK_ADDR(start_addr, end_addr) \ +{ \ + raw_write(start_addr, REG_START_BLKADDR); \ + raw_write(end_addr, REG_END_BLKADDR); \ +} + +#define NFC_SET_NFC_ACTIVE_CS(val) +#define NFC_SET_WPC(val) val + +/* NULL Definitions */ +#define ACK_OPS +#define NFC_SET_RBA(val) raw_write(val, REG_NFC_SET_RBA); + +#define READ_PAGE() send_read_page(0) +#define PROG_PAGE() send_prog_page(0) +#define CHECK_NFC_RB 1 + +#endif /* __MXC_NAND_H__ */ diff --git a/include/asm-arm/arch-mx28/mx28.h b/include/asm-arm/arch-mx28/mx28.h new file mode 100644 index 0000000000..bb39779d52 --- /dev/null +++ b/include/asm-arm/arch-mx28/mx28.h @@ -0,0 +1,131 @@ +/* + * Copyright (C) 2008 Embedded Alley Solutions Inc. + * + * (C) Copyright 2009-2010 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#ifndef __MX28_H +#define __MX28_H + +#ifndef __ASSEMBLER__ +enum mxc_clock { + MXC_ARM_CLK = 0, + MXC_AHB_CLK, + MXC_IPG_CLK, + MXC_GPMI_CLK, +}; + +unsigned int mxc_get_clock(enum mxc_clock clk); +void enet_board_init(void); + +extern int mxs_reset_block(volatile void *addr); +#endif + +/* + * Most of i.MX28 SoC registers are associated with four addresses + * used for different operations - read/write, set, clear and toggle bits. + * + * Some of registers do not implement such feature and, thus, should be + * accessed/manipulated via single address in common way. + */ +#define REG_RD(base, reg) \ + (*(volatile unsigned int *)((base) + (reg))) +#define REG_WR(base, reg, value) \ + ((*(volatile unsigned int *)((base) + (reg))) = (value)) +#define REG_SET(base, reg, value) \ + ((*(volatile unsigned int *)((base) + (reg ## _SET))) = (value)) +#define REG_CLR(base, reg, value) \ + ((*(volatile unsigned int *)((base) + (reg ## _CLR))) = (value)) +#define REG_TOG(base, reg, value) \ + ((*(volatile unsigned int *)((base) + (reg ## _TOG))) = (value)) + +#define REG_RD_ADDR(addr) \ + (*(volatile unsigned int *)((addr))) +#define REG_WR_ADDR(addr, value) \ + ((*(volatile unsigned int *)((addr))) = (value)) +#define REG_SET_ADDR(addr, value) \ + ((*(volatile unsigned int *)((addr) + 0x4)) = (value)) +#define REG_CLR_ADDR(addr, value) \ + ((*(volatile unsigned int *)((addr) + 0x8)) = (value)) +#define REG_TOG_ADDR(addr, value) \ + ((*(volatile unsigned int *)((addr) + 0xc)) = (value)) + +/* + * Register base address + */ +#define REGS_ICOL_BASE 0x80000000 +#define REGS_HSADC_BASE 0x80002000 +#define REGS_APBH_BASE 0x80004000 +#define REGS_PERFMON_BASE 0x80006000 +#define REGS_BCH_BASE 0x8000A000 +#define REGS_GPMI_BASE 0x8000C000 +#define REGS_SSP0_BASE 0x80010000 +#define REGS_SSP1_BASE 0x80012000 +#define REGS_SSP2_BASE 0x80014000 +#define REGS_SSP3_BASE 0x80016000 +#define REGS_PINCTRL_BASE 0x80018000 +#define REGS_DIGCTL_BASE 0x8001C000 +#define REGS_ETM_BASE 0x80022000 +#define REGS_APBX_BASE 0x80024000 +#define REGS_DCP_BASE 0x80028000 +#define REGS_PXP_BASE 0x8002A000 +#define REGS_OCOTP_BASE 0x8002C000 +#define REGS_AXI_AHB0_BASE 0x8002E000 +#define REGS_LCDIF_BASE 0x80030000 +#define REGS_CAN0_BASE 0x80032000 +#define REGS_CAN1_BASE 0x80034000 +#define REGS_SIMDBG_BASE 0x8003C000 +#define REGS_SIMGPMISEL_BASE 0x8003C200 +#define REGS_SIMSSPSEL_BASE 0x8003C300 +#define REGS_SIMMEMSEL_BASE 0x8003C400 +#define REGS_GPIOMON_BASE 0x8003C500 +#define REGS_SIMENET_BASE 0x8003C700 +#define REGS_ARMJTAG_BASE 0x8003C800 +#define REGS_CLKCTRL_BASE 0x80040000 +#define REGS_SAIF0_BASE 0x80042000 +#define REGS_POWER_BASE 0x80044000 +#define REGS_SAIF1_BASE 0x80046000 +#define REGS_LRADC_BASE 0x80050000 +#define REGS_SPDIF_BASE 0x80054000 +#define REGS_RTC_BASE 0x80056000 +#define REGS_I2C0_BASE 0x80058000 +#define REGS_I2C1_BASE 0x8005A000 +#define REGS_PWM_BASE 0x80064000 +#define REGS_TIMROT_BASE 0x80068000 +#define REGS_UARTAPP0_BASE 0x8006A000 +#define REGS_UARTAPP1_BASE 0x8006C000 +#define REGS_UARTAPP2_BASE 0x8006E000 +#define REGS_UARTAPP3_BASE 0x80070000 +#define REGS_UARTAPP4_BASE 0x80072000 +#define REGS_UARTDBG_BASE 0x80074000 +#define REGS_USBPHY0_BASE 0x8007C000 +#define REGS_USBPHY1_BASE 0x8007E000 +#define REGS_USBCTRL0_BASE 0x80080000 +#define REGS_USBCTRL1_BASE 0x80090000 +#define REGS_DFLPT_BASE 0x800C0000 +#define REGS_DRAM_BASE 0x800E0000 +#define REGS_ENET_BASE 0x800F0000 + +#define BCH_BASE_ADDR REGS_BCH_BASE +#define GPMI_BASE_ADDR REGS_GPMI_BASE +#define APBHDMA_BASE_ADDR REGS_APBH_BASE +#define CLKCTRL_BASE_ADDR REGS_CLKCTRL_BASE + +#define MXS_SET_ADDR 0x04 +#define MXS_CLR_ADDR 0x08 +#define MXS_TOG_ADDR 0x0c + +#endif /* __MX28_H */ diff --git a/include/asm-arm/arch-mx28/mxs_gpmi-bch-regs.h b/include/asm-arm/arch-mx28/mxs_gpmi-bch-regs.h new file mode 100644 index 0000000000..7ee695a009 --- /dev/null +++ b/include/asm-arm/arch-mx28/mxs_gpmi-bch-regs.h @@ -0,0 +1,310 @@ +/* + * Freescale GPMI NFC NAND Flash Driver + * + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Xml Revision: 2.5 + * Template revision: 26195 + */ + +#ifndef __GPMI_NFC_BCH_REGS_H +#define __GPMI_NFC_BCH_REGS_H + +#define HW_BCH_CTRL 0x000 +#define HW_BCH_CTRL_SET 0x004 +#define HW_BCH_CTRL_CLR 0x008 +#define HW_BCH_CTRL_TOG 0x00c + +#define BM_BCH_CTRL_SFTRST (1 << 31) +#define BM_BCH_CTRL_CLKGATE (1 << 30) +#define BM_BCH_CTRL_DEBUGSYNDROME (1 << 22) +#define BP_BCH_CTRL_M2M_LAYOUT 18 +#define BM_BCH_CTRL_M2M_LAYOUT (1 << BP_BCH_CTRL_M2M_LAYOUT) +#define BF_BCH_CTRL_M2M_LAYOUT(v) (((v) << BP_BCH_CTRL_M2M_LAYOUT) & BM_BCH_CTRL_M2M_LAYOUT) +#define BM_BCH_CTRL_M2M_ENCODE (1 << 17) +#define BM_BCH_CTRL_M2M_ENABLE (1 << 16) +#define BM_BCH_CTRL_DEBUG_STALL_IRQ_EN (1 << 10) +#define BM_BCH_CTRL_COMPLETE_IRQ_EN (1 << 8) +#define BM_BCH_CTRL_BM_ERROR_IRQ (1 << 3) +#define BM_BCH_CTRL_DEBUG_STALL_IRQ (1 << 2) +#define BM_BCH_CTRL_COMPLETE_IRQ (1 << 0) + +#define HW_BCH_STATUS0 0x010 + +#define BP_BCH_STATUS0_HANDLE 20 +#define BM_BCH_STATUS0_HANDLE (0xFFF << BP_BCH_STATUS0_HANDLE) +#define BF_BCH_STATUS0_HANDLE(v) (((v) << BP_BCH_STATUS0_HANDLE) & BM_BCH_STATUS0_HANDLE) +#define BP_BCH_STATUS0_COMPLETED_CE 16 +#define BM_BCH_STATUS0_COMPLETED_CE (0x000F << BP_BCH_STATUS0_COMPLETED_CE) +#define BF_BCH_STATUS0_COMPLETED_CE(v) (((v) << BP_BCH_STATUS0_COMPLETED_CE) & BM_BCH_STATUS0_COMPLETED_CE) +#define BP_BCH_STATUS0_STATUS_BLK0 8 +#define BM_BCH_STATUS0_STATUS_BLK0 (0xFF << BP_BCH_STATUS0_STATUS_BLK0) +#define BF_BCH_STATUS0_STATUS_BLK0(v) (((v) << BP_BCH_STATUS0_STATUS_BLK0) & BM_BCH_STATUS0_STATUS_BLK0) +#define BV_BCH_STATUS0_STATUS_BLK0__ZERO 0x00 +#define BV_BCH_STATUS0_STATUS_BLK0__ERROR1 0x01 +#define BV_BCH_STATUS0_STATUS_BLK0__ERROR2 0x02 +#define BV_BCH_STATUS0_STATUS_BLK0__ERROR3 0x03 +#define BV_BCH_STATUS0_STATUS_BLK0__ERROR4 0x04 +#define BV_BCH_STATUS0_STATUS_BLK0__UNCORRECTABLE 0xFE +#define BV_BCH_STATUS0_STATUS_BLK0__ERASED 0xFF +#define BM_BCH_STATUS0_ALLONES (1 << 4) +#define BM_BCH_STATUS0_CORRECTED (1 << 3) +#define BM_BCH_STATUS0_UNCORRECTABLE (1 << 2) + +#define HW_BCH_MODE 0x020 + +#define BP_BCH_MODE_ERASE_THRESHOLD 0 +#define BM_BCH_MODE_ERASE_THRESHOLD (0xFF << BP_BCH_MODE_ERASE_THRESHOLD) +#define BF_BCH_MODE_ERASE_THRESHOLD(v) (((v) << 0) & BM_BCH_MODE_ERASE_THRESHOLD) + +#define HW_BCH_ENCODEPTR 0x030 + +#define BP_BCH_ENCODEPTR_ADDR 0 +#define BM_BCH_ENCODEPTR_ADDR 0xFFFFFFFF +#define BF_BCH_ENCODEPTR_ADDR(v) (v) + +#define HW_BCH_DATAPTR 0x040 + +#define BP_BCH_DATAPTR_ADDR 0 +#define BM_BCH_DATAPTR_ADDR 0xFFFFFFFF +#define BF_BCH_DATAPTR_ADDR(v) (v) + +#define HW_BCH_METAPTR 0x050 + +#define BP_BCH_METAPTR_ADDR 0 +#define BM_BCH_METAPTR_ADDR 0xFFFFFFFF +#define BF_BCH_METAPTR_ADDR(v) (v) + +#define HW_BCH_LAYOUTSELECT 0x070 + +#define BP_BCH_LAYOUTSELECT_CS15_SELECT 30 +#define BM_BCH_LAYOUTSELECT_CS15_SELECT (0x3 << BP_BCH_LAYOUTSELECT_CS15_SELECT) +#define BF_BCH_LAYOUTSELECT_CS15_SELECT(v) (((v) << BP_BCH_LAYOUTSELECT_CS15_SELECT) & \ + BM_BCH_LAYOUTSELECT_CS15_SELECT) +#define BP_BCH_LAYOUTSELECT_CS14_SELECT 28 +#define BM_BCH_LAYOUTSELECT_CS14_SELECT (0x3 << BP_BCH_LAYOUTSELECT_CS14_SELECT) +#define BF_BCH_LAYOUTSELECT_CS14_SELECT(v) (((v) << BP_BCH_LAYOUTSELECT_CS14_SELECT) & \ + BM_BCH_LAYOUTSELECT_CS14_SELECT) +#define BP_BCH_LAYOUTSELECT_CS13_SELECT 26 +#define BM_BCH_LAYOUTSELECT_CS13_SELECT (0x3 << BP_BCH_LAYOUTSELECT_CS13_SELECT) +#define BF_BCH_LAYOUTSELECT_CS13_SELECT(v) (((v) << BP_BCH_LAYOUTSELECT_CS13_SELECT) & \ + BM_BCH_LAYOUTSELECT_CS13_SELECT) +#define BP_BCH_LAYOUTSELECT_CS12_SELECT 24 +#define BM_BCH_LAYOUTSELECT_CS12_SELECT (0x3 << BP_BCH_LAYOUTSELECT_CS12_SELECT) +#define BF_BCH_LAYOUTSELECT_CS12_SELECT(v) (((v) << BP_BCH_LAYOUTSELECT_CS12_SELECT) & \ + BM_BCH_LAYOUTSELECT_CS12_SELECT) +#define BP_BCH_LAYOUTSELECT_CS11_SELECT 22 +#define BM_BCH_LAYOUTSELECT_CS11_SELECT (0x3 << BP_BCH_LAYOUTSELECT_CS11_SELECT) +#define BF_BCH_LAYOUTSELECT_CS11_SELECT(v) (((v) << BP_BCH_LAYOUTSELECT_CS11_SELECT) & \ + BM_BCH_LAYOUTSELECT_CS11_SELECT) +#define BP_BCH_LAYOUTSELECT_CS10_SELECT 20 +#define BM_BCH_LAYOUTSELECT_CS10_SELECT (0x3 << BP_BCH_LAYOUTSELECT_CS10_SELECT) +#define BF_BCH_LAYOUTSELECT_CS10_SELECT(v) (((v) << BP_BCH_LAYOUTSELECT_CS10_SELECT) & \ + BM_BCH_LAYOUTSELECT_CS10_SELECT) +#define BP_BCH_LAYOUTSELECT_CS9_SELECT 18 +#define BM_BCH_LAYOUTSELECT_CS9_SELECT 0x000C0000 +#define BF_BCH_LAYOUTSELECT_CS9_SELECT(v) (((v) << 18) & \ + BM_BCH_LAYOUTSELECT_CS9_SELECT) +#define BP_BCH_LAYOUTSELECT_CS8_SELECT 16 +#define BM_BCH_LAYOUTSELECT_CS8_SELECT 0x00030000 +#define BF_BCH_LAYOUTSELECT_CS8_SELECT(v) (((v) << 16) & \ + BM_BCH_LAYOUTSELECT_CS8_SELECT) +#define BP_BCH_LAYOUTSELECT_CS7_SELECT 14 +#define BM_BCH_LAYOUTSELECT_CS7_SELECT 0x0000C000 +#define BF_BCH_LAYOUTSELECT_CS7_SELECT(v) (((v) << 14) & \ + BM_BCH_LAYOUTSELECT_CS7_SELECT) +#define BP_BCH_LAYOUTSELECT_CS6_SELECT 12 +#define BM_BCH_LAYOUTSELECT_CS6_SELECT 0x00003000 +#define BF_BCH_LAYOUTSELECT_CS6_SELECT(v) (((v) << 12) & \ + BM_BCH_LAYOUTSELECT_CS6_SELECT) +#define BP_BCH_LAYOUTSELECT_CS5_SELECT 10 +#define BM_BCH_LAYOUTSELECT_CS5_SELECT 0x00000C00 +#define BF_BCH_LAYOUTSELECT_CS5_SELECT(v) (((v) << 10) & \ + BM_BCH_LAYOUTSELECT_CS5_SELECT) +#define BP_BCH_LAYOUTSELECT_CS4_SELECT 8 +#define BM_BCH_LAYOUTSELECT_CS4_SELECT 0x00000300 +#define BF_BCH_LAYOUTSELECT_CS4_SELECT(v) (((v) << 8) & \ + BM_BCH_LAYOUTSELECT_CS4_SELECT) +#define BP_BCH_LAYOUTSELECT_CS3_SELECT 6 +#define BM_BCH_LAYOUTSELECT_CS3_SELECT 0x000000C0 +#define BF_BCH_LAYOUTSELECT_CS3_SELECT(v) (((v) << 6) & \ + BM_BCH_LAYOUTSELECT_CS3_SELECT) +#define BP_BCH_LAYOUTSELECT_CS2_SELECT 4 +#define BM_BCH_LAYOUTSELECT_CS2_SELECT 0x00000030 +#define BF_BCH_LAYOUTSELECT_CS2_SELECT(v) (((v) << 4) & \ + BM_BCH_LAYOUTSELECT_CS2_SELECT) +#define BP_BCH_LAYOUTSELECT_CS1_SELECT 2 +#define BM_BCH_LAYOUTSELECT_CS1_SELECT 0x0000000C +#define BF_BCH_LAYOUTSELECT_CS1_SELECT(v) (((v) << 2) & \ + BM_BCH_LAYOUTSELECT_CS1_SELECT) +#define BP_BCH_LAYOUTSELECT_CS0_SELECT 0 +#define BM_BCH_LAYOUTSELECT_CS0_SELECT 0x00000003 +#define BF_BCH_LAYOUTSELECT_CS0_SELECT(v) (((v) << 0) & \ + BM_BCH_LAYOUTSELECT_CS0_SELECT) + +#define HW_BCH_FLASH0LAYOUT0 0x080 + +#define BP_BCH_FLASH0LAYOUT0_NBLOCKS 24 +#define BM_BCH_FLASH0LAYOUT0_NBLOCKS (0xFF << BP_BCH_FLASH0LAYOUT0_NBLOCKS) +#define BF_BCH_FLASH0LAYOUT0_NBLOCKS(v) (((v) << BP_BCH_FLASH0LAYOUT0_NBLOCKS) & \ + BM_BCH_FLASH0LAYOUT0_NBLOCKS) +#define BP_BCH_FLASH0LAYOUT0_META_SIZE 16 +#define BM_BCH_FLASH0LAYOUT0_META_SIZE (0xFF << BP_BCH_FLASH0LAYOUT0_META_SIZE) +#define BF_BCH_FLASH0LAYOUT0_META_SIZE(v) (((v) << BP_BCH_FLASH0LAYOUT0_META_SIZE) & \ + BM_BCH_FLASH0LAYOUT0_META_SIZE) +#define BP_BCH_FLASH0LAYOUT0_ECC0 12 +#define BM_BCH_FLASH0LAYOUT0_ECC0 (0xF << BP_BCH_FLASH0LAYOUT0_ECC0) +#define BF_BCH_FLASH0LAYOUT0_ECC0(v) (((v) << BP_BCH_FLASH0LAYOUT0_ECC0) & \ + BM_BCH_FLASH0LAYOUT0_ECC0) +#define BV_BCH_FLASH0LAYOUT0_ECC0__NONE 0x0 +#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC2 0x1 +#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC4 0x2 +#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC6 0x3 +#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC8 0x4 +#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC10 0x5 +#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC12 0x6 +#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC14 0x7 +#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC16 0x8 +#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC18 0x9 +#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC20 0xA +#define BP_BCH_FLASH0LAYOUT0_DATA0_SIZE 0 +#define BM_BCH_FLASH0LAYOUT0_DATA0_SIZE (0xFFF << BP_BCH_FLASH0LAYOUT0_DATA0_SIZE) +#define BF_BCH_FLASH0LAYOUT0_DATA0_SIZE(v) (((v) << BP_BCH_FLASH0LAYOUT0_DATA0_SIZE) & \ + BM_BCH_FLASH0LAYOUT0_DATA0_SIZE) + +#define HW_BCH_FLASH0LAYOUT1 0x090 + +#define BP_BCH_FLASH0LAYOUT1_PAGE_SIZE 16 +#define BM_BCH_FLASH0LAYOUT1_PAGE_SIZE (0xFFFF << BP_BCH_FLASH0LAYOUT1_PAGE_SIZE) +#define BF_BCH_FLASH0LAYOUT1_PAGE_SIZE(v) (((v) << BP_BCH_FLASH0LAYOUT1_PAGE_SIZE) & \ + BM_BCH_FLASH0LAYOUT1_PAGE_SIZE) +#define BP_BCH_FLASH0LAYOUT1_ECCN 12 +#define BM_BCH_FLASH0LAYOUT1_ECCN (0xF << BP_BCH_FLASH0LAYOUT1_ECCN) +#define BF_BCH_FLASH0LAYOUT1_ECCN(v) (((v) << BP_BCH_FLASH0LAYOUT1_ECCN) & \ + BM_BCH_FLASH0LAYOUT1_ECCN) +#define BV_BCH_FLASH0LAYOUT1_ECCN__NONE 0x0 +#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC2 0x1 +#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC4 0x2 +#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC6 0x3 +#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC8 0x4 +#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC10 0x5 +#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC12 0x6 +#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC14 0x7 +#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC16 0x8 +#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC18 0x9 +#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC20 0xA +#define BP_BCH_FLASH0LAYOUT1_DATAN_SIZE 0 +#define BM_BCH_FLASH0LAYOUT1_DATAN_SIZE (0xFFF << BP_BCH_FLASH0LAYOUT1_DATAN_SIZE) +#define BF_BCH_FLASH0LAYOUT1_DATAN_SIZE(v) (((v) << BP_BCH_FLASH0LAYOUT1_DATAN_SIZE) & \ + BM_BCH_FLASH0LAYOUT1_DATAN_SIZE) + +#define HW_BCH_FLASH1LAYOUT0 0x0a0 + +#define HW_BCH_FLASH1LAYOUT1 0x0b0 + +#define HW_BCH_FLASH2LAYOUT0 0x0c0 + +#define HW_BCH_FLASH2LAYOUT1 0x0d0 + +#define HW_BCH_FLASH3LAYOUT0 0x0e0 + +#define HW_BCH_FLASH3LAYOUT1 0x0f0 + +#if 0 +#define HW_BCH_DEBUG0 0x100 +#define HW_BCH_DEBUG0_SET 0x104 +#define HW_BCH_DEBUG0_CLR 0x108 +#define HW_BCH_DEBUG0_TOG 0x10c + +#define BM_BCH_DEBUG0_ROM_BIST_ENABLE (1 << 26) +#define BM_BCH_DEBUG0_ROM_BIST_COMPLETE (1 << 25) +#define BP_BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL 16 +#define BM_BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL (0x1FF << BP_BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL) +#define BF_BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL(v) (((v) << BP_BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL) & \ + BM_BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL) +#define BV_BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL__NORMAL 0x0 +#define BV_BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL__TEST_MODE 0x1 +#define BM_BCH_DEBUG0_KES_DEBUG_SHIFT_SYND (1 << 15) +#define BM_BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG (1 << 14) +#define BV_BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG__DATA 0x1 +#define BV_BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG__AUX 0x1 +#define BM_BCH_DEBUG0_KES_DEBUG_MODE4K (1 << 13) +#define BV_BCH_DEBUG0_KES_DEBUG_MODE4K__4k 0x1 +#define BV_BCH_DEBUG0_KES_DEBUG_MODE4K__2k 0x1 +#define BM_BCH_DEBUG0_KES_DEBUG_KICK 0x00001000 +#define BM_BCH_DEBUG0_KES_STANDALONE 0x00000800 +#define BV_BCH_DEBUG0_KES_STANDALONE__NORMAL 0x0 +#define BV_BCH_DEBUG0_KES_STANDALONE__TEST_MODE 0x1 +#define BM_BCH_DEBUG0_KES_DEBUG_STEP 0x00000400 +#define BM_BCH_DEBUG0_KES_DEBUG_STALL 0x00000200 +#define BV_BCH_DEBUG0_KES_DEBUG_STALL__NORMAL 0x0 +#define BV_BCH_DEBUG0_KES_DEBUG_STALL__WAIT 0x1 +#define BM_BCH_DEBUG0_BM_KES_TEST_BYPASS 0x00000100 +#define BV_BCH_DEBUG0_BM_KES_TEST_BYPASS__NORMAL 0x0 +#define BV_BCH_DEBUG0_BM_KES_TEST_BYPASS__TEST_MODE 0x1 +#define BP_BCH_DEBUG0_DEBUG_REG_SELECT 0 +#define BM_BCH_DEBUG0_DEBUG_REG_SELECT 0x0000003F +#define BF_BCH_DEBUG0_DEBUG_REG_SELECT(v) (((v) << BP_BCH_DEBUG0_DEBUG_REG_SELECT) & \ + BM_BCH_DEBUG0_DEBUG_REG_SELECT) + +#define HW_BCH_DBGKESREAD 0x110 + +#define BP_BCH_DBGKESREAD_VALUES 0 +#define BM_BCH_DBGKESREAD_VALUES 0xFFFFFFFF +#define BF_BCH_DBGKESREAD_VALUES(v) (v) + +#define HW_BCH_DBGCSFEREAD 0x120 + +#define BP_BCH_DBGCSFEREAD_VALUES 0 +#define BM_BCH_DBGCSFEREAD_VALUES 0xFFFFFFFF +#define BF_BCH_DBGCSFEREAD_VALUES(v) (v) + +#define HW_BCH_DBGSYNDGENREAD 0x130 + +#define BP_BCH_DBGSYNDGENREAD_VALUES 0 +#define BM_BCH_DBGSYNDGENREAD_VALUES 0xFFFFFFFF +#define BF_BCH_DBGSYNDGENREAD_VALUES(v) (v) + +#define HW_BCH_DBGAHBMREAD 0x140 + +#define BP_BCH_DBGAHBMREAD_VALUES 0 +#define BM_BCH_DBGAHBMREAD_VALUES 0xFFFFFFFF +#define BF_BCH_DBGAHBMREAD_VALUES(v) (v) + +#define HW_BCH_BLOCKNAME 0x150 + +#define BP_BCH_BLOCKNAME_NAME 0 +#define BM_BCH_BLOCKNAME_NAME 0xFFFFFFFF +#define BF_BCH_BLOCKNAME_NAME(v) (v) +#endif + +#define HW_BCH_VERSION 0x160 + +#define BP_BCH_VERSION_MAJOR 24 +#define BM_BCH_VERSION_MAJOR (0xFF << BP_BCH_VERSION_MAJOR) +#define BF_BCH_VERSION_MAJOR(v) (((v) << BP_BCH_VERSION_MAJOR) & \ + BM_BCH_VERSION_MAJOR) +#define BP_BCH_VERSION_MINOR 16 +#define BM_BCH_VERSION_MINOR (0xFF << BP_BCH_VERSION_MINOR) +#define BF_BCH_VERSION_MINOR(v) (((v) << BP_BCH_VERSION_MINOR) & \ + BM_BCH_VERSION_MINOR) +#define BP_BCH_VERSION_STEP 0 +#define BM_BCH_VERSION_STEP (0xFFFF << BP_BCH_VERSION_STEP) +#define BF_BCH_VERSION_STEP(v) (((v) << BP_BCH_VERSION_STEP) & \ + BM_BCH_VERSION_STEP) + +#endif diff --git a/include/asm-arm/arch-mx28/mxs_gpmi-regs.h b/include/asm-arm/arch-mx28/mxs_gpmi-regs.h new file mode 100644 index 0000000000..b24c2fdac1 --- /dev/null +++ b/include/asm-arm/arch-mx28/mxs_gpmi-regs.h @@ -0,0 +1,456 @@ +/* + * Freescale GPMI NFC NAND Flash Driver + * + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Xml Revision: 2.2 + * Template revision: 26195 + */ + +#ifndef __GPMI_NFC_GPMI_REGS_H +#define __GPMI_NFC_GPMI_REGS_H + +/*============================================================================*/ + +#define HW_GPMI_CTRL0 0x00000000 +#define HW_GPMI_CTRL0_SET 0x00000004 +#define HW_GPMI_CTRL0_CLR 0x00000008 +#define HW_GPMI_CTRL0_TOG 0x0000000c + +#define BM_GPMI_CTRL0_SFTRST (1 << 31) +#define BV_GPMI_CTRL0_SFTRST__RUN 0x0 +#define BV_GPMI_CTRL0_SFTRST__RESET 0x1 +#define BM_GPMI_CTRL0_CLKGATE (1 << 30) +#define BV_GPMI_CTRL0_CLKGATE__RUN 0x0 +#define BV_GPMI_CTRL0_CLKGATE__NO_CLKS 0x1 +#define BM_GPMI_CTRL0_RUN (1 << 29) +#define BV_GPMI_CTRL0_RUN__IDLE 0x0 +#define BV_GPMI_CTRL0_RUN__BUSY 0x1 +#define BM_GPMI_CTRL0_DEV_IRQ_EN (1 << 28) +/* V0 */ +#define BM_GPMI_CTRL0_TIMEOUT_IRQ_EN (1 << 27) +/* V1 */ +#define BM_GPMI_CTRL0_LOCK_CS_V1 (1 << 27) + +#define BM_GPMI_CTRL0_UDMA (1 << 26) +#define BP_GPMI_CTRL0_COMMAND_MODE 24 +#define BM_GPMI_CTRL0_COMMAND_MODE (0x3 << BP_GPMI_CTRL0_COMMAND_MODE) +#define BF_GPMI_CTRL0_COMMAND_MODE(v) \ + (((v) << 24) & BM_GPMI_CTRL0_COMMAND_MODE) +#define BV_GPMI_CTRL0_COMMAND_MODE__WRITE 0x0 +#define BV_GPMI_CTRL0_COMMAND_MODE__READ 0x1 +#define BV_GPMI_CTRL0_COMMAND_MODE__READ_AND_COMPARE 0x2 +#define BV_GPMI_CTRL0_COMMAND_MODE__WAIT_FOR_READY 0x3 +#define BP_GPMI_CTRL0_WORD_LENGTH 23 +#define BM_GPMI_CTRL0_WORD_LENGTH (1 << BP_GPMI_CTRL0_WORD_LENGTH) +#define BV_GPMI_CTRL0_WORD_LENGTH__16_BIT (0x0 << BP_GPMI_CTRL0_WORD_LENGTH) +#define BV_GPMI_CTRL0_WORD_LENGTH__8_BIT (0x1 << BP_GPMI_CTRL0_WORD_LENGTH__8_BIT) +#define BP_GPMI_CTRL0_CS 20 +/* V0 */ +#define BM_GPMI_CTRL0_LOCK_CS (1 << 22) +#define BM_GPMI_CTRL0_CS (0x3 << BP_GPMI_CTRL0_CS) +#define BF_GPMI_CTRL0_CS(v) (((v) << BP_GPMI_CTRL0_CS) & BM_GPMI_CTRL0_CS) +/* V1 */ +#define BM_GPMI_CTRL0_CS_V1 (0x7 << BP_GPMI_CTRL0_CS) +#define BF_GPMI_CTRL0_CS_V1(v) (((v) << BP_GPMI_CTRL0_CS) & BM_GPMI_CTRL0_CS_V1) + +#define BP_GPMI_CTRL0_ADDRESS 17 +#define BM_GPMI_CTRL0_ADDRESS (0x7 << BP_GPMI_CTRL0_ADDRESS) +#define BF_GPMI_CTRL0_ADDRESS(v) (((v) << 17) & BM_GPMI_CTRL0_ADDRESS) +#define BV_GPMI_CTRL0_ADDRESS__NAND_DATA 0x0 +#define BV_GPMI_CTRL0_ADDRESS__NAND_CLE 0x1 +#define BV_GPMI_CTRL0_ADDRESS__NAND_ALE 0x2 +#define BM_GPMI_CTRL0_ADDRESS_INCREMENT (1 << 16) +#define BP_GPMI_CTRL0_XFER_COUNT 0 +#define BM_GPMI_CTRL0_XFER_COUNT (0xFFFF << BP_GPMI_CTRL0_XFER_COUNT) +#define BF_GPMI_CTRL0_XFER_COUNT(v) \ + (((v) << 0) & BM_GPMI_CTRL0_XFER_COUNT) + +/*============================================================================*/ + +#define HW_GPMI_COMPARE 0x00000010 + +#define BP_GPMI_COMPARE_MASK 16 +#define BM_GPMI_COMPARE_MASK (0xFFFF << BP_GPMI_COMPARE_MASK) +#define BF_GPMI_COMPARE_MASK(v) (((v) << 16) & BM_GPMI_COMPARE_MASK) +#define BP_GPMI_COMPARE_REFERENCE 0 +#define BM_GPMI_COMPARE_REFERENCE (0xFFFF << BP_GPMI_COMPARE_REFERENCE) +#define BF_GPMI_COMPARE_REFERENCE(v) (((v) << 0) & BM_GPMI_COMPARE_REFERENCE) + +/*============================================================================*/ + +#define HW_GPMI_ECCCTRL 0x00000020 +#define HW_GPMI_ECCCTRL_SET 0x00000024 +#define HW_GPMI_ECCCTRL_CLR 0x00000028 +#define HW_GPMI_ECCCTRL_TOG 0x0000002c + +#define BP_GPMI_ECCCTRL_HANDLE 16 +#define BM_GPMI_ECCCTRL_HANDLE (0xFFFF << BP_GPMI_ECCCTRL_HANDLE) +#define BF_GPMI_ECCCTRL_HANDLE(v) (((v) << BP_GPMI_ECCCTRL_HANDLE) & BM_GPMI_ECCCTRL_HANDLE) +#define BP_GPMI_ECCCTRL_ECC_CMD 13 +#define BM_GPMI_ECCCTRL_ECC_CMD (3 << BP_GPMI_ECCCTRL_ECC_CMD) +#define BF_GPMI_ECCCTRL_ECC_CMD(v) (((v) << BP_GPMI_ECCCTRL_ECC_CMD) & BM_GPMI_ECCCTRL_ECC_CMD) +/* V0 */ +#define BV_GPMI_ECCCTRL_ECC_CMD__DECODE_4_BIT 0x0 +#define BV_GPMI_ECCCTRL_ECC_CMD__ENCODE_4_BIT 0x1 +#define BV_GPMI_ECCCTRL_ECC_CMD__DECODE_8_BIT 0x2 +#define BV_GPMI_ECCCTRL_ECC_CMD__ENCODE_8_BIT 0x3 +#define BV_GPMI_ECCCTRL_ECC_CMD__BCH_DECODE 0x0 +#define BV_GPMI_ECCCTRL_ECC_CMD__BCH_ENCODE 0x1 +/* V1 */ +#define BV_GPMI_ECCCTRL_ECC_CMD__DECODE 0x0 +#define BV_GPMI_ECCCTRL_ECC_CMD__ENCODE 0x1 + +#define BM_GPMI_ECCCTRL_ENABLE_ECC (1 << 12) +#define BP_GPMI_ECCCTRL_BUFFER_MASK 0 +#define BM_GPMI_ECCCTRL_BUFFER_MASK (0x1FF << BP_GPMI_ECCCTRL_BUFFER_MASK) +#define BF_GPMI_ECCCTRL_BUFFER_MASK(v) (((v) << 0) & BM_GPMI_ECCCTRL_BUFFER_MASK) +#define BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_AUXONLY 0x100 +#define BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_PAGE 0x1FF +/* V0 */ +#define BV_GPMI_ECCCTRL_BUFFER_MASK__AUXILIARY 0x100 +#define BV_GPMI_ECCCTRL_BUFFER_MASK__BUFFER7 0x080 +#define BV_GPMI_ECCCTRL_BUFFER_MASK__BUFFER6 0x040 +#define BV_GPMI_ECCCTRL_BUFFER_MASK__BUFFER5 0x020 +#define BV_GPMI_ECCCTRL_BUFFER_MASK__BUFFER4 0x010 +#define BV_GPMI_ECCCTRL_BUFFER_MASK__BUFFER3 0x008 +#define BV_GPMI_ECCCTRL_BUFFER_MASK__BUFFER2 0x004 +#define BV_GPMI_ECCCTRL_BUFFER_MASK__BUFFER1 0x002 +#define BV_GPMI_ECCCTRL_BUFFER_MASK__BUFFER0 0x001 + +/*============================================================================*/ + +#define HW_GPMI_ECCCOUNT 0x00000030 + +#define BP_GPMI_ECCCOUNT_COUNT 0 +#define BM_GPMI_ECCCOUNT_COUNT 0x0000FFFF +#define BF_GPMI_ECCCOUNT_COUNT(v) (((v) << 0) & BM_GPMI_ECCCOUNT_COUNT) + +/*============================================================================*/ + +#define HW_GPMI_PAYLOAD 0x00000040 + +#define BP_GPMI_PAYLOAD_ADDRESS 2 +#define BM_GPMI_PAYLOAD_ADDRESS 0xFFFFFFFC +#define BF_GPMI_PAYLOAD_ADDRESS(v) (((v) << 2) & BM_GPMI_PAYLOAD_ADDRESS) + +/*============================================================================*/ + +#define HW_GPMI_AUXILIARY 0x00000050 + +#define BP_GPMI_AUXILIARY_ADDRESS 2 +#define BM_GPMI_AUXILIARY_ADDRESS 0xFFFFFFFC +#define BF_GPMI_AUXILIARY_ADDRESS(v) (((v) << 2) & BM_GPMI_AUXILIARY_ADDRESS) + +/*============================================================================*/ + +#define HW_GPMI_CTRL1 0x00000060 +#define HW_GPMI_CTRL1_SET 0x00000064 +#define HW_GPMI_CTRL1_CLR 0x00000068 +#define HW_GPMI_CTRL1_TOG 0x0000006c + +/* V0 */ +#define BM_GPMI_CTRL1_CE3_SEL (1 << 23) +#define BM_GPMI_CTRL1_CE2_SEL (1 << 22) +#define BM_GPMI_CTRL1_CE1_SEL (1 << 21) +#define BM_GPMI_CTRL1_CE0_SEL (1 << 20) +/* V1 */ +#define BM_GPMI_CTRL1_DECOUPLE_CS (1 << 24) +#define BP_GPMI_CTRL1_WRN_DLY_SEL 22 +#define BM_GPMI_CTRL1_WRN_DLY_SEL (3 << BP_GPMI_CTRL1_WRN_DLY_SEL) +#define BF_GPMI_CTRL1_WRN_DLY_SEL(v) (((v) << BP_GPMI_CTRL1_WRN_DLY_SEL) & BM_GPMI_CTRL1_WRN_DLY_SEL) +#define BM_GPMI_CTRL1_TIMEOUT_IRQ_EN (1 << 20) + +#define BM_GPMI_CTRL1_GANGED_RDYBUSY (1 << 19) +/* V0 */ +#define BP_GPMI_CTRL1_RDN_DELAY 12 +#define BM_GPMI_CTRL1_RDN_DELAY (0xf << BP_GPMI_CTRL1_RDN_DELAY) + +#define BM_GPMI_CTRL1_BCH_MODE (1 << 18) +#define BP_GPMI_CTRL1_DLL_ENABLE 17 +#define BM_GPMI_CTRL1_DLL_ENABLE (1 << BP_GPMI_CTRL1_DLL_ENABLE) +#define BP_GPMI_CTRL1_HALF_PERIOD 16 +#define BM_GPMI_CTRL1_HALF_PERIOD (1 << BP_GPMI_CTRL1_HALF_PERIOD) +#define BP_GPMI_CTRL1_RDN_DELAY 12 +#define BM_GPMI_CTRL1_RDN_DELAY (0xf << BP_GPMI_CTRL1_RDN_DELAY) +#define BF_GPMI_CTRL1_RDN_DELAY(v) (((v) << 12) & BM_GPMI_CTRL1_RDN_DELAY) +#define BM_GPMI_CTRL1_DMA2ECC_MODE (1 << 11) +#define BM_GPMI_CTRL1_DEV_IRQ (1 << 10) +#define BM_GPMI_CTRL1_TIMEOUT_IRQ (1 << 9) +#define BM_GPMI_CTRL1_BURST_EN (1 << 8) +/* V0 */ +#define BM_GPMI_CTRL1_ABORT_WAIT_FOR_READY3 (1 << 7) +#define BM_GPMI_CTRL1_ABORT_WAIT_FOR_READY2 (1 << 6) +#define BM_GPMI_CTRL1_ABORT_WAIT_FOR_READY1 (1 << 5) +#define BM_GPMI_CTRL1_ABORT_WAIT_FOR_READY0 (1 << 4) +/* V1 */ +#define BM_GPMI_CTRL1_ABORT_WAIT_REQUEST (1 << 7) +#define BP_GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL 4 +#define BM_GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL (0x7 << BP_GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL) +#define BF_GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL(v) \ + (((v) << BP_GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL) & BM_GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL) + +#define BM_GPMI_CTRL1_DEV_RESET (1 << 3) +#define BM_GPMI_CTRL1_ATA_IRQRDY_POLARITY (1 << 2) +#define BV_GPMI_CTRL1_ATA_IRQRDY_POLARITY__ACTIVELOW 0x0 +#define BV_GPMI_CTRL1_ATA_IRQRDY_POLARITY__ACTIVEHIGH 0x1 +#define BM_GPMI_CTRL1_CAMERA_MODE (1 << 1) +#define BP_GPMI_CTRL1_GPMI_MODE 0 +#define BM_GPMI_CTRL1_GPMI_MODE (0x1 << BP_GPMI_CTRL1_GPMI_MODE) +#define BV_GPMI_CTRL1_GPMI_MODE__NAND (0x0 << BP_GPMI_CTRL1_GPMI_MODE) +#define BV_GPMI_CTRL1_GPMI_MODE__ATA (0x1 << BP_GPMI_CTRL1_GPMI_MODE) + +/*============================================================================*/ + +#define HW_GPMI_TIMING0 0x00000070 + +#define BP_GPMI_TIMING0_ADDRESS_SETUP 16 +#define BM_GPMI_TIMING0_ADDRESS_SETUP 0x00FF0000 +#define BF_GPMI_TIMING0_ADDRESS_SETUP(v) \ + (((v) << 16) & BM_GPMI_TIMING0_ADDRESS_SETUP) +#define BP_GPMI_TIMING0_DATA_HOLD 8 +#define BM_GPMI_TIMING0_DATA_HOLD 0x0000FF00 +#define BF_GPMI_TIMING0_DATA_HOLD(v) \ + (((v) << 8) & BM_GPMI_TIMING0_DATA_HOLD) +#define BP_GPMI_TIMING0_DATA_SETUP 0 +#define BM_GPMI_TIMING0_DATA_SETUP 0x000000FF +#define BF_GPMI_TIMING0_DATA_SETUP(v) \ + (((v) << 0) & BM_GPMI_TIMING0_DATA_SETUP) + +/*============================================================================*/ + +#define HW_GPMI_TIMING1 0x00000080 + +#define BP_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT 16 +#define BM_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT 0xFFFF0000 +#define BF_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT(v) \ + (((v) << 16) & BM_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT) + +/*============================================================================*/ + +#define HW_GPMI_TIMING2 0x00000090 + +#define BP_GPMI_TIMING2_UDMA_TRP 24 +#define BM_GPMI_TIMING2_UDMA_TRP 0xFF000000 +#define BF_GPMI_TIMING2_UDMA_TRP(v) \ + (((v) << 24) & BM_GPMI_TIMING2_UDMA_TRP) +#define BP_GPMI_TIMING2_UDMA_ENV 16 +#define BM_GPMI_TIMING2_UDMA_ENV 0x00FF0000 +#define BF_GPMI_TIMING2_UDMA_ENV(v) \ + (((v) << 16) & BM_GPMI_TIMING2_UDMA_ENV) +#define BP_GPMI_TIMING2_UDMA_HOLD 8 +#define BM_GPMI_TIMING2_UDMA_HOLD 0x0000FF00 +#define BF_GPMI_TIMING2_UDMA_HOLD(v) \ + (((v) << 8) & BM_GPMI_TIMING2_UDMA_HOLD) +#define BP_GPMI_TIMING2_UDMA_SETUP 0 +#define BM_GPMI_TIMING2_UDMA_SETUP 0x000000FF +#define BF_GPMI_TIMING2_UDMA_SETUP(v) \ + (((v) << 0) & BM_GPMI_TIMING2_UDMA_SETUP) + +/*============================================================================*/ + +#define HW_GPMI_DATA 0x000000a0 +#define HW_GPMI_STAT 0x000000b0 + +/* V0 */ +#define BM_GPMI_STAT_PRESENT (1 << 31) +#define BP_GPMI_STAT_RDY_TIMEOUT 8 +#define BM_GPMI_STAT_RDY_TIMEOUT (0xf << BP_GPMI_STAT_RDY_TIMEOUT) +#define BF_GPMI_STAT_RDY_TIMEOUT(v) \ + (((v) << BP_GPMI_STAT_RDY_TIMEOUT) & BM_GPMI_STAT_RDY_TIMEOUT) +#define BM_GPMI_STAT_ATA_IRQ (1 << 7) +#define BM_GPMI_STAT_INVALID_BUFFER_MASK (1 << 6) +#define BM_GPMI_STAT_FIFO_EMPTY (1 << 5) +#define BM_GPMI_STAT_FIFO_FULL (1 << 4) +#define BM_GPMI_STAT_DEV3_ERROR (1 << 3) +#define BM_GPMI_STAT_DEV2_ERROR (1 << 2) +#define BM_GPMI_STAT_DEV1_ERROR (1 << 1) +#define BM_GPMI_STAT_DEERROR (1 << 0) +/* V1 */ +#define BP_GPMI_STAT_READY_BUSY 24 +#define BM_GPMI_STAT_READY_BUSY (0xFF << BP_GPMI_STAT_READY_BUSY) +#define BF_GPMI_STAT_READY_BUSY(v) \ + (((v) << BP_GPMI_STAT_READY_BUSY) & BM_GPMI_STAT_READY_BUSY) +#define BP_GPMI_STAT_RDY_TIMEOUT_V1 16 +#define BM_GPMI_STAT_RDY_TIMEOUT_V1 (0xFF << BP_GPMI_STAT_RDY_TIMEOUT_V1) +#define BF_GPMI_STAT_RDY_TIMEOUT_V1(v) (((v) << BM_GPMI_STAT_RDY_TIMEOUT_V1) & BM_GPMI_STAT_RDY_TIMEOUT_V1) +#define BM_GPMI_STAT_DEV7_ERROR (1 << 15) +#define BM_GPMI_STAT_DEV6_ERROR (1 << 14) +#define BM_GPMI_STAT_DEV5_ERROR (1 << 13) +#define BM_GPMI_STAT_DEV4_ERROR (1 << 12) +#define BM_GPMI_STAT_DEV3_ERROR_V1 (1 << 11) +#define BM_GPMI_STAT_DEV2_ERROR_V1 (1 << 10) +#define BM_GPMI_STAT_DEERROR_V1 (1 << 9) +#define BM_GPMI_STAT_DEV0_ERROR (1 << 5) +#define BM_GPMI_STAT_ATA_IRQ_V1 (1 << 4) +#define BM_GPMI_STAT_INVALID_BUFFER_MASK_V1 (1 << 3) +#define BM_GPMI_STAT_FIFO_EMPTY_V1 (1 << 2) +#define BM_GPMI_STAT_FIFO_FULL_V1 (1 << 1) +#define BM_GPMI_STAT_PRESENT_V1 (1 << 0) + +/*============================================================================*/ + +#define HW_GPMI_DEBUG 0x000000c0 + +/* V0 */ +#define BM_GPMI_DEBUG_READY3 (1 << 31) +#define BM_GPMI_DEBUG_READY2 (1 << 30) +#define BM_GPMI_DEBUG_READY1 (1 << 29) +#define BM_GPMI_DEBUG_READY0 (1 << 28) +#define BM_GPMI_DEBUG_WAIT_FOR_READY_END3 (1 << 27) +#define BM_GPMI_DEBUG_WAIT_FOR_READY_END2 (1 << 26) +#define BM_GPMI_DEBUG_WAIT_FOR_READY_END1 (1 << 25) +#define BM_GPMI_DEBUG_WAIT_FOR_READY_END0 (1 << 24) +#define BM_GPMI_DEBUG_SENSE3 (1 << 23) +#define BM_GPMI_DEBUG_SENSE2 (1 << 22) +#define BM_GPMI_DEBUG_SENSE1 (1 << 21) +#define BM_GPMI_DEBUG_SENSE0 (1 << 20) +#define BM_GPMI_DEBUG_DMAREQ3 (1 << 19) +#define BM_GPMI_DEBUG_DMAREQ2 (1 << 18) +#define BM_GPMI_DEBUG_DMAREQ1 (1 << 17) +#define BM_GPMI_DEBUG_DMAREQ0 (1 << 16) +#define BP_GPMI_DEBUG_CMD_END (1 << 12) +#define BM_GPMI_DEBUG_CMD_END (0xF << BP_GPMI_DEBUG_CMD_END) +#define BF_GPMI_DEBUG_CMD_END(v) \ + (((v) << BP_GPMI_DEBUG_CMD_END) & BM_GPMI_DEBUG_CMD_END) +#define BP_GPMI_DEBUG_UDMA_STATE 8 +#define BM_GPMI_DEBUG_UDMA_STATE (0xf << BP_GPMI_DEBUG_UDMA_STATE) +#define BF_GPMI_DEBUG_UDMA_STATE(v) \ + (((v) << BP_GPMI_DEBUG_UDMA_STATE) & BM_GPMI_DEBUG_UDMA_STATE) +#define BM_GPMI_DEBUG_BUSY (1 << 7) +#define BP_GPMI_DEBUG_PIN_STATE 4 +#define BM_GPMI_DEBUG_PIN_STATE (0x7 << BP_GPMI_DEBUG_PIN_STATE) +#define BF_GPMI_DEBUG_PIN_STATE(v) \ + (((v) << BP_GPMI_DEBUG_PIN_STATE) & BM_GPMI_DEBUG_PIN_STATE) +#define BV_GPMI_DEBUG_PIN_STATE__PSM_IDLE 0x0 +#define BV_GPMI_DEBUG_PIN_STATE__PSM_BYTCNT 0x1 +#define BV_GPMI_DEBUG_PIN_STATE__PSM_ADDR 0x2 +#define BV_GPMI_DEBUG_PIN_STATE__PSM_STALL 0x3 +#define BV_GPMI_DEBUG_PIN_STATE__PSM_STROBE 0x4 +#define BV_GPMI_DEBUG_PIN_STATE__PSM_ATARDY 0x5 +#define BV_GPMI_DEBUG_PIN_STATE__PSM_DHOLD 0x6 +#define BV_GPMI_DEBUG_PIN_STATE__PSM_DONE 0x7 +#define BP_GPMI_DEBUG_MAIN_STATE 0 +#define BM_GPMI_DEBUG_MAIN_STATE (0xF << BP_GPMI_DEBUG_MAIN_STATE) +#define BF_GPMI_DEBUG_MAIN_STATE(v) \ + (((v) << BP_GPMI_DEBUG_MAIN_STATE) & BM_GPMI_DEBUG_MAIN_STATE) +#define BV_GPMI_DEBUG_MAIN_STATE__MSM_IDLE 0x0 +#define BV_GPMI_DEBUG_MAIN_STATE__MSM_BYTCNT 0x1 +#define BV_GPMI_DEBUG_MAIN_STATE__MSM_WAITFE 0x2 +#define BV_GPMI_DEBUG_MAIN_STATE__MSM_WAITFR 0x3 +#define BV_GPMI_DEBUG_MAIN_STATE__MSM_DMAREQ 0x4 +#define BV_GPMI_DEBUG_MAIN_STATE__MSM_DMAACK 0x5 +#define BV_GPMI_DEBUG_MAIN_STATE__MSM_WAITFF 0x6 +#define BV_GPMI_DEBUG_MAIN_STATE__MSM_LDFIFO 0x7 +#define BV_GPMI_DEBUG_MAIN_STATE__MSM_LDDMAR 0x8 +#define BV_GPMI_DEBUG_MAIN_STATE__MSM_RDCMP 0x9 +#define BV_GPMI_DEBUG_MAIN_STATE__MSM_DONE 0xA +/* V1 */ +#define BP_GPMI_DEBUG_WAIT_FOR_READY_END 24 +#define BM_GPMI_DEBUG_WAIT_FOR_READY_END (0xFF << BP_GPMI_DEBUG_WAIT_FOR_READY_END) +#define BF_GPMI_DEBUG_WAIT_FOR_READY_END(v) \ + (((v) << BP_GPMI_DEBUG_WAIT_FOR_READY_END) & BM_GPMI_DEBUG_WAIT_FOR_READY_END) +#define BP_GPMI_DEBUG_DMA_SENSE 16 +#define BM_GPMI_DEBUG_DMA_SENSE (0xFF << BP_GPMI_DEBUG_DMA_SENSE) +#define BF_GPMI_DEBUG_DMA_SENSE(v) \ + (((v) << BP_GPMI_DEBUG_DMA_SENSE) & BM_GPMI_DEBUG_DMA_SENSE) +#define BP_GPMI_DEBUG_DMAREQ 8 +#define BM_GPMI_DEBUG_DMAREQ (0xFF << BP_GPMI_DEBUG_DMAREQ) +#define BF_GPMI_DEBUG_DMAREQ(v) \ + (((v) << BP_GPMI_DEBUG_DMAREQ) & BM_GPMI_DEBUG_DMAREQ) +#define BP_GPMI_DEBUG_CMD_END_V1 0 +#define BM_GPMI_DEBUG_CMD_END_V1 (0xFF << BP_GPMI_DEBUG_CMD_END) +#define BF_GPMI_DEBUG_CMD_END_V1(v) \ + (((v) << BP_GPMI_DEBUG_CMD_END) & BM_GPMI_DEBUG_CMD_END) + +/*============================================================================*/ + +#define HW_GPMI_VERSION 0x000000d0 + +#define BP_GPMI_VERSION_MAJOR 24 +#define BM_GPMI_VERSION_MAJOR (0xFF << BP_GPMI_VERSION_MAJOR) +#define BF_GPMI_VERSION_MAJOR(v) (((v) << BP_GPMI_VERSION_MAJOR) & BM_GPMI_VERSION_MAJOR) +#define BP_GPMI_VERSION_MINOR 16 +#define BM_GPMI_VERSION_MINOR (0xFF << BP_GPMI_VERSION_MINOR) +#define BF_GPMI_VERSION_MINOR(v) (((v) << BP_GPMI_VERSION_MINOR) & BM_GPMI_VERSION_MINOR) +#define BP_GPMI_VERSION_STEP 0 +#define BM_GPMI_VERSION_STEP (0xFFFF << BP_GPMI_VERSION_STEP) +#define BF_GPMI_VERSION_STEP(v) (((v) << BP_GPMI_VERSION_STEP) & BM_GPMI_VERSION_STEP) + +/*============================================================================*/ + +#define HW_GPMI_DEBUG2 0x000000e0 + +/* V1 */ +#define BP_GPMI_DEBUG2_UDMA_STATE 24 +#define BM_GPMI_DEBUG2_UDMA_STATE (0xF << BP_GPMI_DEBUG2_UDMA_STATE) +#define BF_GPMI_DEBUG2_UDMA_STATE(v) \ + (((v) << BP_GPMI_DEBUG2_UDMA_STATE) & BM_GPMI_DEBUG2_UDMA_STATE) +#define BM_GPMI_DEBUG2_BUSY (1 << 23) +#define BP_GPMI_DEBUG2_PIN_STATE 20 +#define BM_GPMI_DEBUG2_PIN_STATE (0x7 << BP_GPMI_DEBUG2_PIN_STATE) +#define BF_GPMI_DEBUG2_PIN_STATE(v) \ + (((v) << BP_GPMI_DEBUG2_PIN_STATE) & BM_GPMI_DEBUG2_PIN_STATE) +#define BV_GPMI_DEBUG2_PIN_STATE__PSM_IDLE 0x0 +#define BV_GPMI_DEBUG2_PIN_STATE__PSM_BYTCNT 0x1 +#define BV_GPMI_DEBUG2_PIN_STATE__PSM_ADDR 0x2 +#define BV_GPMI_DEBUG2_PIN_STATE__PSM_STALL 0x3 +#define BV_GPMI_DEBUG2_PIN_STATE__PSM_STROBE 0x4 +#define BV_GPMI_DEBUG2_PIN_STATE__PSM_ATARDY 0x5 +#define BV_GPMI_DEBUG2_PIN_STATE__PSM_DHOLD 0x6 +#define BV_GPMI_DEBUG2_PIN_STATE__PSM_DONE 0x7 +#define BP_GPMI_DEBUG2_MAIN_STATE 16 +#define BM_GPMI_DEBUG2_MAIN_STATE (0xF << BP_GPMI_DEBUG2_MAIN_STATE) +#define BF_GPMI_DEBUG2_MAIN_STATE(v) \ + (((v) << BP_GPMI_DEBUG2_MAIN_STATE) & BM_GPMI_DEBUG2_MAIN_STATE) +#define BV_GPMI_DEBUG2_MAIN_STATE__MSM_IDLE 0x0 +#define BV_GPMI_DEBUG2_MAIN_STATE__MSM_BYTCNT 0x1 +#define BV_GPMI_DEBUG2_MAIN_STATE__MSM_WAITFE 0x2 +#define BV_GPMI_DEBUG2_MAIN_STATE__MSM_WAITFR 0x3 +#define BV_GPMI_DEBUG2_MAIN_STATE__MSM_DMAREQ 0x4 +#define BV_GPMI_DEBUG2_MAIN_STATE__MSM_DMAACK 0x5 +#define BV_GPMI_DEBUG2_MAIN_STATE__MSM_WAITFF 0x6 +#define BV_GPMI_DEBUG2_MAIN_STATE__MSM_LDFIFO 0x7 +#define BV_GPMI_DEBUG2_MAIN_STATE__MSM_LDDMAR 0x8 +#define BV_GPMI_DEBUG2_MAIN_STATE__MSM_RDCMP 0x9 +#define BV_GPMI_DEBUG2_MAIN_STATE__MSM_DONE 0xA +#define BP_GPMI_DEBUG2_SYND2GPMI_BE 12 +#define BM_GPMI_DEBUG2_SYND2GPMI_BE (0xF << BP_GPMI_DEBUG2_SYND2GPMI_BE) +#define BF_GPMI_DEBUG2_SYND2GPMI_BE(v) (((v) << BP_GPMI_DEBUG2_SYND2GPMI_BE) & BM_GPMI_DEBUG2_SYND2GPMI_BE) +#define BM_GPMI_DEBUG2_GPMI2SYND_VALID (1 << 11) +#define BM_GPMI_DEBUG2_GPMI2SYND_READY (1 << 10) +#define BM_GPMI_DEBUG2_SYND2GPMI_VALID (1 << 9) +#define BM_GPMI_DEBUG2_SYND2GPMI_READY (1 << 8) +#define BM_GPMI_DEBUG2_VIEW_DELAYED_RDN (1 << 7) +#define BM_GPMI_DEBUG2_UPDATE_WINDOW (1 << 6) +#define BP_GPMI_DEBUG2_RDN_TAP 0 +#define BM_GPMI_DEBUG2_RDN_TAP (0x3F << BP_GPMI_DEBUG2_RDN_TAP) +#define BF_GPMI_DEBUG2_RDN_TAP(v) (((v) << BP_GPMI_DEBUG2_RDN_TAP) & BM_GPMI_DEBUG2_RDN_TAP) + +/*============================================================================*/ + +#define HW_GPMI_DEBUG3 0x000000f0 + +#define BP_GPMI_DEBUG3_APB_WORD_CNTR 16 +#define BM_GPMI_DEBUG3_APB_WORD_CNTR (0xFFFF << BP_GPMI_DEBUG3_APB_WORD_CNTR) +#define BF_GPMI_DEBUG3_APB_WORD_CNTR(v) (((v) << )BP_GPMI_DEBUG3_APB_WORD_CNTR & BM_GPMI_DEBUG3_APB_WORD_CNTR) +#define BP_GPMI_DEBUG3_DEV_WORD_CNTR 0 +#define BM_GPMI_DEBUG3_DEV_WORD_CNTR (0xFFFF << BP_GPMI_DEBUG3_DEV_WORD_CNTR) +#define BF_GPMI_DEBUG3_DEV_WORD_CNTR(v) (((v) << BP_GPMI_DEBUG3_DEV_WORD_CNTR) & BM_GPMI_DEBUG3_DEV_WORD_CNTR) + +/*============================================================================*/ +#endif diff --git a/include/asm-arm/arch-mx28/pinctrl.h b/include/asm-arm/arch-mx28/pinctrl.h new file mode 100644 index 0000000000..ae48e821cc --- /dev/null +++ b/include/asm-arm/arch-mx28/pinctrl.h @@ -0,0 +1,222 @@ +/* + * + * (C) Copyright 2009-2010 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#ifndef __PINCTRL_H +#define __PINCTRL_H + +#define PIN_BITS 5 +#define PINS_PER_BANK (1 << PIN_BITS) +#define PINID_2_BANK(id) ((id) >> PIN_BITS) +#define PINID_2_PIN(id) ((id) & (PINS_PER_BANK - 1)) +#define PINID_ENCODE(bank, pin) (((bank) << PIN_BITS) + (pin)) + +/* + * Each pin may be routed up to four different HW interfaces + * including GPIO + */ +enum pin_fun { + PIN_FUN1 = 0, + PIN_FUN2, + PIN_FUN3, + PIN_GPIO +}; + +/* + * Each pin may have different output drive strength in range from + * 4mA to 20mA. The most common case is 4, 8 and 12 mA strengths. + */ +enum pad_strength { + PAD_4MA = 0, + PAD_8MA, + PAD_12MA, + PAD_RESV +}; + +/* + * Each pin can be programmed for 1.8V or 3.3V + */ +enum pad_voltage { + PAD_1V8 = 0, + PAD_3V3 +}; + +/* + * Structure to define a group of pins and their parameters + */ +struct pin_desc { + u32 id; + enum pin_fun fun; + enum pad_strength strength; + enum pad_voltage voltage; + u32 pullup:1; +}; + +struct pin_group { + struct pin_desc *pins; + int nr_pins; +}; + +extern void pin_gpio_direction(u32 id, u32 output); +extern u32 pin_gpio_get(u32 id); +extern void pin_gpio_set(u32 id, u32 val); +extern void pin_set_type(u32 id, enum pin_fun cfg); +extern void pin_set_strength(u32 id, enum pad_strength strength); +extern void pin_set_voltage(u32 id, enum pad_voltage volt); +extern void pin_set_pullup(u32 id, u32 pullup); +extern void pin_set_group(struct pin_group *pin_group); + +/* + * Definitions of all i.MX28 pins + */ +/* Bank 0 */ +#define PINID_GPMI_D00 PINID_ENCODE(0, 0) +#define PINID_GPMI_D01 PINID_ENCODE(0, 1) +#define PINID_GPMI_D02 PINID_ENCODE(0, 2) +#define PINID_GPMI_D03 PINID_ENCODE(0, 3) +#define PINID_GPMI_D04 PINID_ENCODE(0, 4) +#define PINID_GPMI_D05 PINID_ENCODE(0, 5) +#define PINID_GPMI_D06 PINID_ENCODE(0, 6) +#define PINID_GPMI_D07 PINID_ENCODE(0, 7) +#define PINID_GPMI_CE0N PINID_ENCODE(0, 16) +#define PINID_GPMI_CE1N PINID_ENCODE(0, 17) +#define PINID_GPMI_CE2N PINID_ENCODE(0, 18) +#define PINID_GPMI_CE3N PINID_ENCODE(0, 19) +#define PINID_GPMI_RDY0 PINID_ENCODE(0, 20) +#define PINID_GPMI_RDY1 PINID_ENCODE(0, 21) +#define PINID_GPMI_RDY2 PINID_ENCODE(0, 22) +#define PINID_GPMI_RDY3 PINID_ENCODE(0, 23) +#define PINID_GPMI_RDN PINID_ENCODE(0, 24) +#define PINID_GPMI_WRN PINID_ENCODE(0, 25) +#define PINID_GPMI_ALE PINID_ENCODE(0, 26) +#define PINID_GPMI_CLE PINID_ENCODE(0, 27) +#define PINID_GPMI_RESETN PINID_ENCODE(0, 28) + +/* Bank 1 */ +#define PINID_LCD_D00 PINID_ENCODE(1, 0) +#define PINID_LCD_D01 PINID_ENCODE(1, 1) +#define PINID_LCD_D02 PINID_ENCODE(1, 2) +#define PINID_LCD_D03 PINID_ENCODE(1, 3) +#define PINID_LCD_D04 PINID_ENCODE(1, 4) +#define PINID_LCD_D05 PINID_ENCODE(1, 5) +#define PINID_LCD_D06 PINID_ENCODE(1, 6) +#define PINID_LCD_D07 PINID_ENCODE(1, 7) +#define PINID_LCD_D08 PINID_ENCODE(1, 8) +#define PINID_LCD_D09 PINID_ENCODE(1, 9) +#define PINID_LCD_D10 PINID_ENCODE(1, 10) +#define PINID_LCD_D11 PINID_ENCODE(1, 11) +#define PINID_LCD_D12 PINID_ENCODE(1, 12) +#define PINID_LCD_D13 PINID_ENCODE(1, 13) +#define PINID_LCD_D14 PINID_ENCODE(1, 14) +#define PINID_LCD_D15 PINID_ENCODE(1, 15) +#define PINID_LCD_D16 PINID_ENCODE(1, 16) +#define PINID_LCD_D17 PINID_ENCODE(1, 17) +#define PINID_LCD_D18 PINID_ENCODE(1, 18) +#define PINID_LCD_D19 PINID_ENCODE(1, 19) +#define PINID_LCD_D20 PINID_ENCODE(1, 20) +#define PINID_LCD_D21 PINID_ENCODE(1, 21) +#define PINID_LCD_D22 PINID_ENCODE(1, 22) +#define PINID_LCD_D23 PINID_ENCODE(1, 23) +#define PINID_LCD_RD_E PINID_ENCODE(1, 24) +#define PINID_LCD_WR_RWN PINID_ENCODE(1, 25) +#define PINID_LCD_RS PINID_ENCODE(1, 26) +#define PINID_LCD_CS PINID_ENCODE(1, 27) +#define PINID_LCD_VSYNC PINID_ENCODE(1, 28) +#define PINID_LCD_HSYNC PINID_ENCODE(1, 29) +#define PINID_LCD_DOTCK PINID_ENCODE(1, 30) +#define PINID_LCD_ENABLE PINID_ENCODE(1, 31) + +/* Bank 2 */ +#define PINID_SSP0_DATA0 PINID_ENCODE(2, 0) +#define PINID_SSP0_DATA1 PINID_ENCODE(2, 1) +#define PINID_SSP0_DATA2 PINID_ENCODE(2, 2) +#define PINID_SSP0_DATA3 PINID_ENCODE(2, 3) +#define PINID_SSP0_DATA4 PINID_ENCODE(2, 4) +#define PINID_SSP0_DATA5 PINID_ENCODE(2, 5) +#define PINID_SSP0_DATA6 PINID_ENCODE(2, 6) +#define PINID_SSP0_DATA7 PINID_ENCODE(2, 7) +#define PINID_SSP0_CMD PINID_ENCODE(2, 8) +#define PINID_SSP0_DETECT PINID_ENCODE(2, 9) +#define PINID_SSP0_SCK PINID_ENCODE(2, 10) +#define PINID_SSP1_SCK PINID_ENCODE(2, 12) +#define PINID_SSP1_CMD PINID_ENCODE(2, 13) +#define PINID_SSP1_DATA0 PINID_ENCODE(2, 14) +#define PINID_SSP1_DATA3 PINID_ENCODE(2, 15) +#define PINID_SSP2_SCK PINID_ENCODE(2, 16) +#define PINID_SSP2_MOSI PINID_ENCODE(2, 17) +#define PINID_SSP2_MISO PINID_ENCODE(2, 18) +#define PINID_SSP2_SS0 PINID_ENCODE(2, 19) +#define PINID_SSP2_SS1 PINID_ENCODE(2, 20) +#define PINID_SSP2_SS2 PINID_ENCODE(2, 21) +#define PINID_SSP3_SCK PINID_ENCODE(2, 24) +#define PINID_SSP3_MOSI PINID_ENCODE(2, 25) +#define PINID_SSP3_MISO PINID_ENCODE(2, 26) +#define PINID_SSP3_SS0 PINID_ENCODE(2, 27) + +/* Bank 3 */ +#define PINID_AUART0_RX PINID_ENCODE(3, 0) +#define PINID_AUART0_TX PINID_ENCODE(3, 1) +#define PINID_AUART0_CTS PINID_ENCODE(3, 2) +#define PINID_AUART0_RTS PINID_ENCODE(3, 3) +#define PINID_AUART1_RX PINID_ENCODE(3, 4) +#define PINID_AUART1_TX PINID_ENCODE(3, 5) +#define PINID_AUART1_CTS PINID_ENCODE(3, 6) +#define PINID_AUART1_RTS PINID_ENCODE(3, 7) +#define PINID_AUART2_RX PINID_ENCODE(3, 8) +#define PINID_AUART2_TX PINID_ENCODE(3, 9) +#define PINID_AUART2_CTS PINID_ENCODE(3, 10) +#define PINID_AUART2_RTS PINID_ENCODE(3, 11) +#define PINID_AUART3_RX PINID_ENCODE(3, 12) +#define PINID_AUART3_TX PINID_ENCODE(3, 13) +#define PINID_AUART3_CTS PINID_ENCODE(3, 14) +#define PINID_AUART3_RTS PINID_ENCODE(3, 15) +#define PINID_PWM0 PINID_ENCODE(3, 16) +#define PINID_PWM1 PINID_ENCODE(3, 17) +#define PINID_PWM2 PINID_ENCODE(3, 18) +#define PINID_SAIF0_MCLK PINID_ENCODE(3, 20) +#define PINID_SAIF0_LRCLK PINID_ENCODE(3, 21) +#define PINID_SAIF0_BITCLK PINID_ENCODE(3, 22) +#define PINID_SAIF0_SDATA0 PINID_ENCODE(3, 23) +#define PINID_I2C0_SCL PINID_ENCODE(3, 24) +#define PINID_I2C0_SDA PINID_ENCODE(3, 25) +#define PINID_SAIF1_SDATA0 PINID_ENCODE(3, 26) +#define PINID_SPDIF PINID_ENCODE(3, 27) +#define PINID_PWM3 PINID_ENCODE(3, 28) +#define PINID_PWM4 PINID_ENCODE(3, 29) +#define PINID_LCD_RESET PINID_ENCODE(3, 30) + +/* Bank 4 */ +#define PINID_ENET0_MDC PINID_ENCODE(4, 0) +#define PINID_ENET0_MDIO PINID_ENCODE(4, 1) +#define PINID_ENET0_RX_EN PINID_ENCODE(4, 2) +#define PINID_ENET0_RXD0 PINID_ENCODE(4, 3) +#define PINID_ENET0_RXD1 PINID_ENCODE(4, 4) +#define PINID_ENET0_TX_CLK PINID_ENCODE(4, 5) +#define PINID_ENET0_TX_EN PINID_ENCODE(4, 6) +#define PINID_ENET0_TXD0 PINID_ENCODE(4, 7) +#define PINID_ENET0_TXD1 PINID_ENCODE(4, 8) +#define PINID_ENET0_RXD2 PINID_ENCODE(4, 9) +#define PINID_ENET0_RXD3 PINID_ENCODE(4, 10) +#define PINID_ENET0_TXD2 PINID_ENCODE(4, 11) +#define PINID_ENET0_TXD3 PINID_ENCODE(4, 12) +#define PINID_ENET0_RX_CLK PINID_ENCODE(4, 13) +#define PINID_ENET0_COL PINID_ENCODE(4, 14) +#define PINID_ENET0_CRS PINID_ENCODE(4, 15) +#define PINID_ENET_CLK PINID_ENCODE(4, 16) +#define PINID_JTAG_RTCK PINID_ENCODE(4, 20) + +#endif diff --git a/include/asm-arm/arch-mx28/regs-clkctrl.h b/include/asm-arm/arch-mx28/regs-clkctrl.h new file mode 100644 index 0000000000..8fae8854eb --- /dev/null +++ b/include/asm-arm/arch-mx28/regs-clkctrl.h @@ -0,0 +1,635 @@ +/* + * Freescale CLKCTRL Register Definitions + * + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * This file is created by xml file. Don't Edit it. + * + * Xml Revision: 1.48 + * Template revision: 26195 + */ + +#ifndef __ARCH_ARM___CLKCTRL_H +#define __ARCH_ARM___CLKCTRL_H + + +#define HW_CLKCTRL_PLL0CTRL0 (0x00000000) +#define HW_CLKCTRL_PLL0CTRL0_SET (0x00000004) +#define HW_CLKCTRL_PLL0CTRL0_CLR (0x00000008) +#define HW_CLKCTRL_PLL0CTRL0_TOG (0x0000000c) + +#define BP_CLKCTRL_PLL0CTRL0_RSRVD6 30 +#define BM_CLKCTRL_PLL0CTRL0_RSRVD6 0xC0000000 +#define BF_CLKCTRL_PLL0CTRL0_RSRVD6(v) \ + (((v) << 30) & BM_CLKCTRL_PLL0CTRL0_RSRVD6) +#define BP_CLKCTRL_PLL0CTRL0_LFR_SEL 28 +#define BM_CLKCTRL_PLL0CTRL0_LFR_SEL 0x30000000 +#define BF_CLKCTRL_PLL0CTRL0_LFR_SEL(v) \ + (((v) << 28) & BM_CLKCTRL_PLL0CTRL0_LFR_SEL) +#define BV_CLKCTRL_PLL0CTRL0_LFR_SEL__DEFAULT 0x0 +#define BV_CLKCTRL_PLL0CTRL0_LFR_SEL__TIMES_2 0x1 +#define BV_CLKCTRL_PLL0CTRL0_LFR_SEL__TIMES_05 0x2 +#define BV_CLKCTRL_PLL0CTRL0_LFR_SEL__UNDEFINED 0x3 +#define BP_CLKCTRL_PLL0CTRL0_RSRVD5 26 +#define BM_CLKCTRL_PLL0CTRL0_RSRVD5 0x0C000000 +#define BF_CLKCTRL_PLL0CTRL0_RSRVD5(v) \ + (((v) << 26) & BM_CLKCTRL_PLL0CTRL0_RSRVD5) +#define BP_CLKCTRL_PLL0CTRL0_CP_SEL 24 +#define BM_CLKCTRL_PLL0CTRL0_CP_SEL 0x03000000 +#define BF_CLKCTRL_PLL0CTRL0_CP_SEL(v) \ + (((v) << 24) & BM_CLKCTRL_PLL0CTRL0_CP_SEL) +#define BV_CLKCTRL_PLL0CTRL0_CP_SEL__DEFAULT 0x0 +#define BV_CLKCTRL_PLL0CTRL0_CP_SEL__TIMES_2 0x1 +#define BV_CLKCTRL_PLL0CTRL0_CP_SEL__TIMES_05 0x2 +#define BV_CLKCTRL_PLL0CTRL0_CP_SEL__UNDEFINED 0x3 +#define BP_CLKCTRL_PLL0CTRL0_RSRVD4 22 +#define BM_CLKCTRL_PLL0CTRL0_RSRVD4 0x00C00000 +#define BF_CLKCTRL_PLL0CTRL0_RSRVD4(v) \ + (((v) << 22) & BM_CLKCTRL_PLL0CTRL0_RSRVD4) +#define BP_CLKCTRL_PLL0CTRL0_DIV_SEL 20 +#define BM_CLKCTRL_PLL0CTRL0_DIV_SEL 0x00300000 +#define BF_CLKCTRL_PLL0CTRL0_DIV_SEL(v) \ + (((v) << 20) & BM_CLKCTRL_PLL0CTRL0_DIV_SEL) +#define BV_CLKCTRL_PLL0CTRL0_DIV_SEL__DEFAULT 0x0 +#define BV_CLKCTRL_PLL0CTRL0_DIV_SEL__LOWER 0x1 +#define BV_CLKCTRL_PLL0CTRL0_DIV_SEL__LOWEST 0x2 +#define BV_CLKCTRL_PLL0CTRL0_DIV_SEL__UNDEFINED 0x3 +#define BM_CLKCTRL_PLL0CTRL0_RSRVD3 0x00080000 +#define BM_CLKCTRL_PLL0CTRL0_EN_USB_CLKS 0x00040000 +#define BM_CLKCTRL_PLL0CTRL0_POWER 0x00020000 +#define BP_CLKCTRL_PLL0CTRL0_RSRVD1 0 +#define BM_CLKCTRL_PLL0CTRL0_RSRVD1 0x0001FFFF +#define BF_CLKCTRL_PLL0CTRL0_RSRVD1(v) \ + (((v) << 0) & BM_CLKCTRL_PLL0CTRL0_RSRVD1) + +#define HW_CLKCTRL_PLL0CTRL1 (0x00000010) + +#define BM_CLKCTRL_PLL0CTRL1_LOCK 0x80000000 +#define BM_CLKCTRL_PLL0CTRL1_FORCE_LOCK 0x40000000 +#define BP_CLKCTRL_PLL0CTRL1_RSRVD1 16 +#define BM_CLKCTRL_PLL0CTRL1_RSRVD1 0x3FFF0000 +#define BF_CLKCTRL_PLL0CTRL1_RSRVD1(v) \ + (((v) << 16) & BM_CLKCTRL_PLL0CTRL1_RSRVD1) +#define BP_CLKCTRL_PLL0CTRL1_LOCK_COUNT 0 +#define BM_CLKCTRL_PLL0CTRL1_LOCK_COUNT 0x0000FFFF +#define BF_CLKCTRL_PLL0CTRL1_LOCK_COUNT(v) \ + (((v) << 0) & BM_CLKCTRL_PLL0CTRL1_LOCK_COUNT) + +#define HW_CLKCTRL_PLL1CTRL0 (0x00000020) +#define HW_CLKCTRL_PLL1CTRL0_SET (0x00000024) +#define HW_CLKCTRL_PLL1CTRL0_CLR (0x00000028) +#define HW_CLKCTRL_PLL1CTRL0_TOG (0x0000002c) + +#define BM_CLKCTRL_PLL1CTRL0_CLKGATEEMI 0x80000000 +#define BM_CLKCTRL_PLL1CTRL0_RSRVD6 0x40000000 +#define BP_CLKCTRL_PLL1CTRL0_LFR_SEL 28 +#define BM_CLKCTRL_PLL1CTRL0_LFR_SEL 0x30000000 +#define BF_CLKCTRL_PLL1CTRL0_LFR_SEL(v) \ + (((v) << 28) & BM_CLKCTRL_PLL1CTRL0_LFR_SEL) +#define BV_CLKCTRL_PLL1CTRL0_LFR_SEL__DEFAULT 0x0 +#define BV_CLKCTRL_PLL1CTRL0_LFR_SEL__TIMES_2 0x1 +#define BV_CLKCTRL_PLL1CTRL0_LFR_SEL__TIMES_05 0x2 +#define BV_CLKCTRL_PLL1CTRL0_LFR_SEL__UNDEFINED 0x3 +#define BP_CLKCTRL_PLL1CTRL0_RSRVD5 26 +#define BM_CLKCTRL_PLL1CTRL0_RSRVD5 0x0C000000 +#define BF_CLKCTRL_PLL1CTRL0_RSRVD5(v) \ + (((v) << 26) & BM_CLKCTRL_PLL1CTRL0_RSRVD5) +#define BP_CLKCTRL_PLL1CTRL0_CP_SEL 24 +#define BM_CLKCTRL_PLL1CTRL0_CP_SEL 0x03000000 +#define BF_CLKCTRL_PLL1CTRL0_CP_SEL(v) \ + (((v) << 24) & BM_CLKCTRL_PLL1CTRL0_CP_SEL) +#define BV_CLKCTRL_PLL1CTRL0_CP_SEL__DEFAULT 0x0 +#define BV_CLKCTRL_PLL1CTRL0_CP_SEL__TIMES_2 0x1 +#define BV_CLKCTRL_PLL1CTRL0_CP_SEL__TIMES_05 0x2 +#define BV_CLKCTRL_PLL1CTRL0_CP_SEL__UNDEFINED 0x3 +#define BP_CLKCTRL_PLL1CTRL0_RSRVD4 22 +#define BM_CLKCTRL_PLL1CTRL0_RSRVD4 0x00C00000 +#define BF_CLKCTRL_PLL1CTRL0_RSRVD4(v) \ + (((v) << 22) & BM_CLKCTRL_PLL1CTRL0_RSRVD4) +#define BP_CLKCTRL_PLL1CTRL0_DIV_SEL 20 +#define BM_CLKCTRL_PLL1CTRL0_DIV_SEL 0x00300000 +#define BF_CLKCTRL_PLL1CTRL0_DIV_SEL(v) \ + (((v) << 20) & BM_CLKCTRL_PLL1CTRL0_DIV_SEL) +#define BV_CLKCTRL_PLL1CTRL0_DIV_SEL__DEFAULT 0x0 +#define BV_CLKCTRL_PLL1CTRL0_DIV_SEL__LOWER 0x1 +#define BV_CLKCTRL_PLL1CTRL0_DIV_SEL__LOWEST 0x2 +#define BV_CLKCTRL_PLL1CTRL0_DIV_SEL__UNDEFINED 0x3 +#define BM_CLKCTRL_PLL1CTRL0_RSRVD3 0x00080000 +#define BM_CLKCTRL_PLL1CTRL0_EN_USB_CLKS 0x00040000 +#define BM_CLKCTRL_PLL1CTRL0_POWER 0x00020000 +#define BP_CLKCTRL_PLL1CTRL0_RSRVD1 0 +#define BM_CLKCTRL_PLL1CTRL0_RSRVD1 0x0001FFFF +#define BF_CLKCTRL_PLL1CTRL0_RSRVD1(v) \ + (((v) << 0) & BM_CLKCTRL_PLL1CTRL0_RSRVD1) + +#define HW_CLKCTRL_PLL1CTRL1 (0x00000030) + +#define BM_CLKCTRL_PLL1CTRL1_LOCK 0x80000000 +#define BM_CLKCTRL_PLL1CTRL1_FORCE_LOCK 0x40000000 +#define BP_CLKCTRL_PLL1CTRL1_RSRVD1 16 +#define BM_CLKCTRL_PLL1CTRL1_RSRVD1 0x3FFF0000 +#define BF_CLKCTRL_PLL1CTRL1_RSRVD1(v) \ + (((v) << 16) & BM_CLKCTRL_PLL1CTRL1_RSRVD1) +#define BP_CLKCTRL_PLL1CTRL1_LOCK_COUNT 0 +#define BM_CLKCTRL_PLL1CTRL1_LOCK_COUNT 0x0000FFFF +#define BF_CLKCTRL_PLL1CTRL1_LOCK_COUNT(v) \ + (((v) << 0) & BM_CLKCTRL_PLL1CTRL1_LOCK_COUNT) + +#define HW_CLKCTRL_PLL2CTRL0 (0x00000040) +#define HW_CLKCTRL_PLL2CTRL0_SET (0x00000044) +#define HW_CLKCTRL_PLL2CTRL0_CLR (0x00000048) +#define HW_CLKCTRL_PLL2CTRL0_TOG (0x0000004c) + +#define BM_CLKCTRL_PLL2CTRL0_CLKGATE 0x80000000 +#define BM_CLKCTRL_PLL2CTRL0_RSRVD3 0x40000000 +#define BP_CLKCTRL_PLL2CTRL0_LFR_SEL 28 +#define BM_CLKCTRL_PLL2CTRL0_LFR_SEL 0x30000000 +#define BF_CLKCTRL_PLL2CTRL0_LFR_SEL(v) \ + (((v) << 28) & BM_CLKCTRL_PLL2CTRL0_LFR_SEL) +#define BM_CLKCTRL_PLL2CTRL0_RSRVD2 0x08000000 +#define BM_CLKCTRL_PLL2CTRL0_HOLD_RING_OFF_B 0x04000000 +#define BP_CLKCTRL_PLL2CTRL0_CP_SEL 24 +#define BM_CLKCTRL_PLL2CTRL0_CP_SEL 0x03000000 +#define BF_CLKCTRL_PLL2CTRL0_CP_SEL(v) \ + (((v) << 24) & BM_CLKCTRL_PLL2CTRL0_CP_SEL) +#define BM_CLKCTRL_PLL2CTRL0_POWER 0x00800000 +#define BP_CLKCTRL_PLL2CTRL0_RSRVD1 0 +#define BM_CLKCTRL_PLL2CTRL0_RSRVD1 0x007FFFFF +#define BF_CLKCTRL_PLL2CTRL0_RSRVD1(v) \ + (((v) << 0) & BM_CLKCTRL_PLL2CTRL0_RSRVD1) + +#define HW_CLKCTRL_CPU (0x00000050) +#define HW_CLKCTRL_CPU_SET (0x00000054) +#define HW_CLKCTRL_CPU_CLR (0x00000058) +#define HW_CLKCTRL_CPU_TOG (0x0000005c) + +#define BP_CLKCTRL_CPU_RSRVD5 30 +#define BM_CLKCTRL_CPU_RSRVD5 0xC0000000 +#define BF_CLKCTRL_CPU_RSRVD5(v) \ + (((v) << 30) & BM_CLKCTRL_CPU_RSRVD5) +#define BM_CLKCTRL_CPU_BUSY_REF_XTAL 0x20000000 +#define BM_CLKCTRL_CPU_BUSY_REF_CPU 0x10000000 +#define BM_CLKCTRL_CPU_RSRVD4 0x08000000 +#define BM_CLKCTRL_CPU_DIV_XTAL_FRAC_EN 0x04000000 +#define BP_CLKCTRL_CPU_DIV_XTAL 16 +#define BM_CLKCTRL_CPU_DIV_XTAL 0x03FF0000 +#define BF_CLKCTRL_CPU_DIV_XTAL(v) \ + (((v) << 16) & BM_CLKCTRL_CPU_DIV_XTAL) +#define BP_CLKCTRL_CPU_RSRVD3 13 +#define BM_CLKCTRL_CPU_RSRVD3 0x0000E000 +#define BF_CLKCTRL_CPU_RSRVD3(v) \ + (((v) << 13) & BM_CLKCTRL_CPU_RSRVD3) +#define BM_CLKCTRL_CPU_INTERRUPT_WAIT 0x00001000 +#define BM_CLKCTRL_CPU_RSRVD2 0x00000800 +#define BM_CLKCTRL_CPU_DIV_CPU_FRAC_EN 0x00000400 +#define BP_CLKCTRL_CPU_RSRVD1 6 +#define BM_CLKCTRL_CPU_RSRVD1 0x000003C0 +#define BF_CLKCTRL_CPU_RSRVD1(v) \ + (((v) << 6) & BM_CLKCTRL_CPU_RSRVD1) +#define BP_CLKCTRL_CPU_DIV_CPU 0 +#define BM_CLKCTRL_CPU_DIV_CPU 0x0000003F +#define BF_CLKCTRL_CPU_DIV_CPU(v) \ + (((v) << 0) & BM_CLKCTRL_CPU_DIV_CPU) + +#define HW_CLKCTRL_HBUS (0x00000060) +#define HW_CLKCTRL_HBUS_SET (0x00000064) +#define HW_CLKCTRL_HBUS_CLR (0x00000068) +#define HW_CLKCTRL_HBUS_TOG (0x0000006c) + +#define BM_CLKCTRL_HBUS_ASM_BUSY 0x80000000 +#define BM_CLKCTRL_HBUS_DCP_AS_ENABLE 0x40000000 +#define BM_CLKCTRL_HBUS_PXP_AS_ENABLE 0x20000000 +#define BM_CLKCTRL_HBUS_RSRVD2 0x10000000 +#define BM_CLKCTRL_HBUS_ASM_EMIPORT_AS_ENABLE 0x08000000 +#define BM_CLKCTRL_HBUS_APBHDMA_AS_ENABLE 0x04000000 +#define BM_CLKCTRL_HBUS_APBXDMA_AS_ENABLE 0x02000000 +#define BM_CLKCTRL_HBUS_TRAFFIC_JAM_AS_ENABLE 0x01000000 +#define BM_CLKCTRL_HBUS_TRAFFIC_AS_ENABLE 0x00800000 +#define BM_CLKCTRL_HBUS_CPU_DATA_AS_ENABLE 0x00400000 +#define BM_CLKCTRL_HBUS_CPU_INSTR_AS_ENABLE 0x00200000 +#define BM_CLKCTRL_HBUS_ASM_ENABLE 0x00100000 +#define BM_CLKCTRL_HBUS_AUTO_CLEAR_DIV_ENABLE 0x00080000 +#define BP_CLKCTRL_HBUS_SLOW_DIV 16 +#define BM_CLKCTRL_HBUS_SLOW_DIV 0x00070000 +#define BF_CLKCTRL_HBUS_SLOW_DIV(v) \ + (((v) << 16) & BM_CLKCTRL_HBUS_SLOW_DIV) +#define BV_CLKCTRL_HBUS_SLOW_DIV__BY1 0x0 +#define BV_CLKCTRL_HBUS_SLOW_DIV__BY2 0x1 +#define BV_CLKCTRL_HBUS_SLOW_DIV__BY4 0x2 +#define BV_CLKCTRL_HBUS_SLOW_DIV__BY8 0x3 +#define BV_CLKCTRL_HBUS_SLOW_DIV__BY16 0x4 +#define BV_CLKCTRL_HBUS_SLOW_DIV__BY32 0x5 +#define BP_CLKCTRL_HBUS_RSRVD1 6 +#define BM_CLKCTRL_HBUS_RSRVD1 0x0000FFC0 +#define BF_CLKCTRL_HBUS_RSRVD1(v) \ + (((v) << 6) & BM_CLKCTRL_HBUS_RSRVD1) +#define BM_CLKCTRL_HBUS_DIV_FRAC_EN 0x00000020 +#define BP_CLKCTRL_HBUS_DIV 0 +#define BM_CLKCTRL_HBUS_DIV 0x0000001F +#define BF_CLKCTRL_HBUS_DIV(v) \ + (((v) << 0) & BM_CLKCTRL_HBUS_DIV) + +#define HW_CLKCTRL_XBUS (0x00000070) + +#define BM_CLKCTRL_XBUS_BUSY 0x80000000 +#define BP_CLKCTRL_XBUS_RSRVD1 12 +#define BM_CLKCTRL_XBUS_RSRVD1 0x7FFFF000 +#define BF_CLKCTRL_XBUS_RSRVD1(v) \ + (((v) << 12) & BM_CLKCTRL_XBUS_RSRVD1) +#define BM_CLKCTRL_XBUS_AUTO_CLEAR_DIV_ENABLE 0x00000800 +#define BM_CLKCTRL_XBUS_DIV_FRAC_EN 0x00000400 +#define BP_CLKCTRL_XBUS_DIV 0 +#define BM_CLKCTRL_XBUS_DIV 0x000003FF +#define BF_CLKCTRL_XBUS_DIV(v) \ + (((v) << 0) & BM_CLKCTRL_XBUS_DIV) + +#define HW_CLKCTRL_XTAL (0x00000080) +#define HW_CLKCTRL_XTAL_SET (0x00000084) +#define HW_CLKCTRL_XTAL_CLR (0x00000088) +#define HW_CLKCTRL_XTAL_TOG (0x0000008c) + +#define BM_CLKCTRL_XTAL_UART_CLK_GATE 0x80000000 +#define BM_CLKCTRL_XTAL_RSRVD3 0x40000000 +#define BM_CLKCTRL_XTAL_PWM_CLK24M_GATE 0x20000000 +#define BP_CLKCTRL_XTAL_RSRVD2 27 +#define BM_CLKCTRL_XTAL_RSRVD2 0x18000000 +#define BF_CLKCTRL_XTAL_RSRVD2(v) \ + (((v) << 27) & BM_CLKCTRL_XTAL_RSRVD2) +#define BM_CLKCTRL_XTAL_TIMROT_CLK32K_GATE 0x04000000 +#define BP_CLKCTRL_XTAL_RSRVD1 2 +#define BM_CLKCTRL_XTAL_RSRVD1 0x03FFFFFC +#define BF_CLKCTRL_XTAL_RSRVD1(v) \ + (((v) << 2) & BM_CLKCTRL_XTAL_RSRVD1) +#define BP_CLKCTRL_XTAL_DIV_UART 0 +#define BM_CLKCTRL_XTAL_DIV_UART 0x00000003 +#define BF_CLKCTRL_XTAL_DIV_UART(v) \ + (((v) << 0) & BM_CLKCTRL_XTAL_DIV_UART) + +#define HW_CLKCTRL_SSP0 (0x00000090) + +#define BM_CLKCTRL_SSP0_CLKGATE 0x80000000 +#define BM_CLKCTRL_SSP0_RSRVD2 0x40000000 +#define BM_CLKCTRL_SSP0_BUSY 0x20000000 +#define BP_CLKCTRL_SSP0_RSRVD1 10 +#define BM_CLKCTRL_SSP0_RSRVD1 0x1FFFFC00 +#define BF_CLKCTRL_SSP0_RSRVD1(v) \ + (((v) << 10) & BM_CLKCTRL_SSP0_RSRVD1) +#define BM_CLKCTRL_SSP0_DIV_FRAC_EN 0x00000200 +#define BP_CLKCTRL_SSP0_DIV 0 +#define BM_CLKCTRL_SSP0_DIV 0x000001FF +#define BF_CLKCTRL_SSP0_DIV(v) \ + (((v) << 0) & BM_CLKCTRL_SSP0_DIV) + +#define HW_CLKCTRL_SSP1 (0x000000a0) + +#define BM_CLKCTRL_SSP1_CLKGATE 0x80000000 +#define BM_CLKCTRL_SSP1_RSRVD2 0x40000000 +#define BM_CLKCTRL_SSP1_BUSY 0x20000000 +#define BP_CLKCTRL_SSP1_RSRVD1 10 +#define BM_CLKCTRL_SSP1_RSRVD1 0x1FFFFC00 +#define BF_CLKCTRL_SSP1_RSRVD1(v) \ + (((v) << 10) & BM_CLKCTRL_SSP1_RSRVD1) +#define BM_CLKCTRL_SSP1_DIV_FRAC_EN 0x00000200 +#define BP_CLKCTRL_SSP1_DIV 0 +#define BM_CLKCTRL_SSP1_DIV 0x000001FF +#define BF_CLKCTRL_SSP1_DIV(v) \ + (((v) << 0) & BM_CLKCTRL_SSP1_DIV) + +#define HW_CLKCTRL_SSP2 (0x000000b0) + +#define BM_CLKCTRL_SSP2_CLKGATE 0x80000000 +#define BM_CLKCTRL_SSP2_RSRVD2 0x40000000 +#define BM_CLKCTRL_SSP2_BUSY 0x20000000 +#define BP_CLKCTRL_SSP2_RSRVD1 10 +#define BM_CLKCTRL_SSP2_RSRVD1 0x1FFFFC00 +#define BF_CLKCTRL_SSP2_RSRVD1(v) \ + (((v) << 10) & BM_CLKCTRL_SSP2_RSRVD1) +#define BM_CLKCTRL_SSP2_DIV_FRAC_EN 0x00000200 +#define BP_CLKCTRL_SSP2_DIV 0 +#define BM_CLKCTRL_SSP2_DIV 0x000001FF +#define BF_CLKCTRL_SSP2_DIV(v) \ + (((v) << 0) & BM_CLKCTRL_SSP2_DIV) + +#define HW_CLKCTRL_SSP3 (0x000000c0) + +#define BM_CLKCTRL_SSP3_CLKGATE 0x80000000 +#define BM_CLKCTRL_SSP3_RSRVD2 0x40000000 +#define BM_CLKCTRL_SSP3_BUSY 0x20000000 +#define BP_CLKCTRL_SSP3_RSRVD1 10 +#define BM_CLKCTRL_SSP3_RSRVD1 0x1FFFFC00 +#define BF_CLKCTRL_SSP3_RSRVD1(v) \ + (((v) << 10) & BM_CLKCTRL_SSP3_RSRVD1) +#define BM_CLKCTRL_SSP3_DIV_FRAC_EN 0x00000200 +#define BP_CLKCTRL_SSP3_DIV 0 +#define BM_CLKCTRL_SSP3_DIV 0x000001FF +#define BF_CLKCTRL_SSP3_DIV(v) \ + (((v) << 0) & BM_CLKCTRL_SSP3_DIV) + +#define HW_CLKCTRL_GPMI (0x000000d0) + +#define BM_CLKCTRL_GPMI_CLKGATE 0x80000000 +#define BM_CLKCTRL_GPMI_RSRVD2 0x40000000 +#define BM_CLKCTRL_GPMI_BUSY 0x20000000 +#define BP_CLKCTRL_GPMI_RSRVD1 11 +#define BM_CLKCTRL_GPMI_RSRVD1 0x1FFFF800 +#define BF_CLKCTRL_GPMI_RSRVD1(v) \ + (((v) << 11) & BM_CLKCTRL_GPMI_RSRVD1) +#define BM_CLKCTRL_GPMI_DIV_FRAC_EN 0x00000400 +#define BP_CLKCTRL_GPMI_DIV 0 +#define BM_CLKCTRL_GPMI_DIV 0x000003FF +#define BF_CLKCTRL_GPMI_DIV(v) \ + (((v) << 0) & BM_CLKCTRL_GPMI_DIV) + +#define HW_CLKCTRL_SPDIF (0x000000e0) + +#define BM_CLKCTRL_SPDIF_CLKGATE 0x80000000 +#define BP_CLKCTRL_SPDIF_RSRVD 0 +#define BM_CLKCTRL_SPDIF_RSRVD 0x7FFFFFFF +#define BF_CLKCTRL_SPDIF_RSRVD(v) \ + (((v) << 0) & BM_CLKCTRL_SPDIF_RSRVD) + +#define HW_CLKCTRL_EMI (0x000000f0) + +#define BM_CLKCTRL_EMI_CLKGATE 0x80000000 +#define BM_CLKCTRL_EMI_SYNC_MODE_EN 0x40000000 +#define BM_CLKCTRL_EMI_BUSY_REF_XTAL 0x20000000 +#define BM_CLKCTRL_EMI_BUSY_REF_EMI 0x10000000 +#define BM_CLKCTRL_EMI_BUSY_REF_CPU 0x08000000 +#define BM_CLKCTRL_EMI_BUSY_SYNC_MODE 0x04000000 +#define BP_CLKCTRL_EMI_RSRVD3 18 +#define BM_CLKCTRL_EMI_RSRVD3 0x03FC0000 +#define BF_CLKCTRL_EMI_RSRVD3(v) \ + (((v) << 18) & BM_CLKCTRL_EMI_RSRVD3) +#define BM_CLKCTRL_EMI_BUSY_DCC_RESYNC 0x00020000 +#define BM_CLKCTRL_EMI_DCC_RESYNC_ENABLE 0x00010000 +#define BP_CLKCTRL_EMI_RSRVD2 12 +#define BM_CLKCTRL_EMI_RSRVD2 0x0000F000 +#define BF_CLKCTRL_EMI_RSRVD2(v) \ + (((v) << 12) & BM_CLKCTRL_EMI_RSRVD2) +#define BP_CLKCTRL_EMI_DIV_XTAL 8 +#define BM_CLKCTRL_EMI_DIV_XTAL 0x00000F00 +#define BF_CLKCTRL_EMI_DIV_XTAL(v) \ + (((v) << 8) & BM_CLKCTRL_EMI_DIV_XTAL) +#define BP_CLKCTRL_EMI_RSRVD1 6 +#define BM_CLKCTRL_EMI_RSRVD1 0x000000C0 +#define BF_CLKCTRL_EMI_RSRVD1(v) \ + (((v) << 6) & BM_CLKCTRL_EMI_RSRVD1) +#define BP_CLKCTRL_EMI_DIV_EMI 0 +#define BM_CLKCTRL_EMI_DIV_EMI 0x0000003F +#define BF_CLKCTRL_EMI_DIV_EMI(v) \ + (((v) << 0) & BM_CLKCTRL_EMI_DIV_EMI) + +#define HW_CLKCTRL_SAIF0 (0x00000100) + +#define BM_CLKCTRL_SAIF0_CLKGATE 0x80000000 +#define BM_CLKCTRL_SAIF0_RSRVD2 0x40000000 +#define BM_CLKCTRL_SAIF0_BUSY 0x20000000 +#define BP_CLKCTRL_SAIF0_RSRVD1 17 +#define BM_CLKCTRL_SAIF0_RSRVD1 0x1FFE0000 +#define BF_CLKCTRL_SAIF0_RSRVD1(v) \ + (((v) << 17) & BM_CLKCTRL_SAIF0_RSRVD1) +#define BM_CLKCTRL_SAIF0_DIV_FRAC_EN 0x00010000 +#define BP_CLKCTRL_SAIF0_DIV 0 +#define BM_CLKCTRL_SAIF0_DIV 0x0000FFFF +#define BF_CLKCTRL_SAIF0_DIV(v) \ + (((v) << 0) & BM_CLKCTRL_SAIF0_DIV) + +#define HW_CLKCTRL_SAIF1 (0x00000110) + +#define BM_CLKCTRL_SAIF1_CLKGATE 0x80000000 +#define BM_CLKCTRL_SAIF1_RSRVD2 0x40000000 +#define BM_CLKCTRL_SAIF1_BUSY 0x20000000 +#define BP_CLKCTRL_SAIF1_RSRVD1 17 +#define BM_CLKCTRL_SAIF1_RSRVD1 0x1FFE0000 +#define BF_CLKCTRL_SAIF1_RSRVD1(v) \ + (((v) << 17) & BM_CLKCTRL_SAIF1_RSRVD1) +#define BM_CLKCTRL_SAIF1_DIV_FRAC_EN 0x00010000 +#define BP_CLKCTRL_SAIF1_DIV 0 +#define BM_CLKCTRL_SAIF1_DIV 0x0000FFFF +#define BF_CLKCTRL_SAIF1_DIV(v) \ + (((v) << 0) & BM_CLKCTRL_SAIF1_DIV) + +#define HW_CLKCTRL_DIS_LCDIF (0x00000120) + +#define BM_CLKCTRL_DIS_LCDIF_CLKGATE 0x80000000 +#define BM_CLKCTRL_DIS_LCDIF_RSRVD2 0x40000000 +#define BM_CLKCTRL_DIS_LCDIF_BUSY 0x20000000 +#define BP_CLKCTRL_DIS_LCDIF_RSRVD1 14 +#define BM_CLKCTRL_DIS_LCDIF_RSRVD1 0x1FFFC000 +#define BF_CLKCTRL_DIS_LCDIF_RSRVD1(v) \ + (((v) << 14) & BM_CLKCTRL_DIS_LCDIF_RSRVD1) +#define BM_CLKCTRL_DIS_LCDIF_DIV_FRAC_EN 0x00002000 +#define BP_CLKCTRL_DIS_LCDIF_DIV 0 +#define BM_CLKCTRL_DIS_LCDIF_DIV 0x00001FFF +#define BF_CLKCTRL_DIS_LCDIF_DIV(v) \ + (((v) << 0) & BM_CLKCTRL_DIS_LCDIF_DIV) + +#define HW_CLKCTRL_ETM (0x00000130) + +#define BM_CLKCTRL_ETM_CLKGATE 0x80000000 +#define BM_CLKCTRL_ETM_RSRVD2 0x40000000 +#define BM_CLKCTRL_ETM_BUSY 0x20000000 +#define BP_CLKCTRL_ETM_RSRVD1 8 +#define BM_CLKCTRL_ETM_RSRVD1 0x1FFFFF00 +#define BF_CLKCTRL_ETM_RSRVD1(v) \ + (((v) << 8) & BM_CLKCTRL_ETM_RSRVD1) +#define BM_CLKCTRL_ETM_DIV_FRAC_EN 0x00000080 +#define BP_CLKCTRL_ETM_DIV 0 +#define BM_CLKCTRL_ETM_DIV 0x0000007F +#define BF_CLKCTRL_ETM_DIV(v) \ + (((v) << 0) & BM_CLKCTRL_ETM_DIV) + +#define HW_CLKCTRL_ENET (0x00000140) + +#define BM_CLKCTRL_ENET_SLEEP 0x80000000 +#define BM_CLKCTRL_ENET_DISABLE 0x40000000 +#define BM_CLKCTRL_ENET_STATUS 0x20000000 +#define BM_CLKCTRL_ENET_RSRVD1 0x10000000 +#define BM_CLKCTRL_ENET_BUSY_TIME 0x08000000 +#define BP_CLKCTRL_ENET_DIV_TIME 21 +#define BM_CLKCTRL_ENET_DIV_TIME 0x07E00000 +#define BF_CLKCTRL_ENET_DIV_TIME(v) \ + (((v) << 21) & BM_CLKCTRL_ENET_DIV_TIME) +#define BP_CLKCTRL_ENET_TIME_SEL 19 +#define BM_CLKCTRL_ENET_TIME_SEL 0x00180000 +#define BF_CLKCTRL_ENET_TIME_SEL(v) \ + (((v) << 19) & BM_CLKCTRL_ENET_TIME_SEL) +#define BV_CLKCTRL_ENET_TIME_SEL__XTAL 0x0 +#define BV_CLKCTRL_ENET_TIME_SEL__PLL 0x1 +#define BV_CLKCTRL_ENET_TIME_SEL__RMII_CLK 0x2 +#define BV_CLKCTRL_ENET_TIME_SEL__UNDEFINED 0x3 +#define BM_CLKCTRL_ENET_CLK_OUT_EN 0x00040000 +#define BM_CLKCTRL_ENET_RESET_BY_SW_CHIP 0x00020000 +#define BM_CLKCTRL_ENET_RESET_BY_SW 0x00010000 +#define BP_CLKCTRL_ENET_RSRVD0 0 +#define BM_CLKCTRL_ENET_RSRVD0 0x0000FFFF +#define BF_CLKCTRL_ENET_RSRVD0(v) \ + (((v) << 0) & BM_CLKCTRL_ENET_RSRVD0) + +#define HW_CLKCTRL_HSADC (0x00000150) + +#define BM_CLKCTRL_HSADC_RSRVD2 0x80000000 +#define BM_CLKCTRL_HSADC_RESETB 0x40000000 +#define BP_CLKCTRL_HSADC_FREQDIV 28 +#define BM_CLKCTRL_HSADC_FREQDIV 0x30000000 +#define BF_CLKCTRL_HSADC_FREQDIV(v) \ + (((v) << 28) & BM_CLKCTRL_HSADC_FREQDIV) +#define BP_CLKCTRL_HSADC_RSRVD1 0 +#define BM_CLKCTRL_HSADC_RSRVD1 0x0FFFFFFF +#define BF_CLKCTRL_HSADC_RSRVD1(v) \ + (((v) << 0) & BM_CLKCTRL_HSADC_RSRVD1) + +#define HW_CLKCTRL_FLEXCAN (0x00000160) + +#define BM_CLKCTRL_FLEXCAN_RSRVD2 0x80000000 +#define BM_CLKCTRL_FLEXCAN_STOP_CAN0 0x40000000 +#define BM_CLKCTRL_FLEXCAN_CAN0_STATUS 0x20000000 +#define BM_CLKCTRL_FLEXCAN_STOP_CAN1 0x10000000 +#define BM_CLKCTRL_FLEXCAN_CAN1_STATUS 0x08000000 +#define BP_CLKCTRL_FLEXCAN_RSRVD1 0 +#define BM_CLKCTRL_FLEXCAN_RSRVD1 0x07FFFFFF +#define BF_CLKCTRL_FLEXCAN_RSRVD1(v) \ + (((v) << 0) & BM_CLKCTRL_FLEXCAN_RSRVD1) + +#define HW_CLKCTRL_FRAC0 (0x000001b0) +#define HW_CLKCTRL_FRAC0_SET (0x000001b4) +#define HW_CLKCTRL_FRAC0_CLR (0x000001b8) +#define HW_CLKCTRL_FRAC0_TOG (0x000001bc) + +#define BM_CLKCTRL_FRAC0_CLKGATEIO0 0x80000000 +#define BM_CLKCTRL_FRAC0_IO0_STABLE 0x40000000 +#define BP_CLKCTRL_FRAC0_IO0FRAC 24 +#define BM_CLKCTRL_FRAC0_IO0FRAC 0x3F000000 +#define BF_CLKCTRL_FRAC0_IO0FRAC(v) \ + (((v) << 24) & BM_CLKCTRL_FRAC0_IO0FRAC) +#define BM_CLKCTRL_FRAC0_CLKGATEIO1 0x00800000 +#define BM_CLKCTRL_FRAC0_IO1_STABLE 0x00400000 +#define BP_CLKCTRL_FRAC0_IO1FRAC 16 +#define BM_CLKCTRL_FRAC0_IO1FRAC 0x003F0000 +#define BF_CLKCTRL_FRAC0_IO1FRAC(v) \ + (((v) << 16) & BM_CLKCTRL_FRAC0_IO1FRAC) +#define BM_CLKCTRL_FRAC0_CLKGATEEMI 0x00008000 +#define BM_CLKCTRL_FRAC0_EMI_STABLE 0x00004000 +#define BP_CLKCTRL_FRAC0_EMIFRAC 8 +#define BM_CLKCTRL_FRAC0_EMIFRAC 0x00003F00 +#define BF_CLKCTRL_FRAC0_EMIFRAC(v) \ + (((v) << 8) & BM_CLKCTRL_FRAC0_EMIFRAC) +#define BM_CLKCTRL_FRAC0_CLKGATECPU 0x00000080 +#define BM_CLKCTRL_FRAC0_CPU_STABLE 0x00000040 +#define BP_CLKCTRL_FRAC0_CPUFRAC 0 +#define BM_CLKCTRL_FRAC0_CPUFRAC 0x0000003F +#define BF_CLKCTRL_FRAC0_CPUFRAC(v) \ + (((v) << 0) & BM_CLKCTRL_FRAC0_CPUFRAC) + +#define HW_CLKCTRL_FRAC1 (0x000001c0) +#define HW_CLKCTRL_FRAC1_SET (0x000001c4) +#define HW_CLKCTRL_FRAC1_CLR (0x000001c8) +#define HW_CLKCTRL_FRAC1_TOG (0x000001cc) + +#define BP_CLKCTRL_FRAC1_RSRVD2 24 +#define BM_CLKCTRL_FRAC1_RSRVD2 0xFF000000 +#define BF_CLKCTRL_FRAC1_RSRVD2(v) \ + (((v) << 24) & BM_CLKCTRL_FRAC1_RSRVD2) +#define BM_CLKCTRL_FRAC1_CLKGATEGPMI 0x00800000 +#define BM_CLKCTRL_FRAC1_GPMI_STABLE 0x00400000 +#define BP_CLKCTRL_FRAC1_GPMIFRAC 16 +#define BM_CLKCTRL_FRAC1_GPMIFRAC 0x003F0000 +#define BF_CLKCTRL_FRAC1_GPMIFRAC(v) \ + (((v) << 16) & BM_CLKCTRL_FRAC1_GPMIFRAC) +#define BM_CLKCTRL_FRAC1_CLKGATEHSADC 0x00008000 +#define BM_CLKCTRL_FRAC1_HSADC_STABLE 0x00004000 +#define BP_CLKCTRL_FRAC1_HSADCFRAC 8 +#define BM_CLKCTRL_FRAC1_HSADCFRAC 0x00003F00 +#define BF_CLKCTRL_FRAC1_HSADCFRAC(v) \ + (((v) << 8) & BM_CLKCTRL_FRAC1_HSADCFRAC) +#define BM_CLKCTRL_FRAC1_CLKGATEPIX 0x00000080 +#define BM_CLKCTRL_FRAC1_PIX_STABLE 0x00000040 +#define BP_CLKCTRL_FRAC1_PIXFRAC 0 +#define BM_CLKCTRL_FRAC1_PIXFRAC 0x0000003F +#define BF_CLKCTRL_FRAC1_PIXFRAC(v) \ + (((v) << 0) & BM_CLKCTRL_FRAC1_PIXFRAC) + +#define HW_CLKCTRL_CLKSEQ (0x000001d0) +#define HW_CLKCTRL_CLKSEQ_SET (0x000001d4) +#define HW_CLKCTRL_CLKSEQ_CLR (0x000001d8) +#define HW_CLKCTRL_CLKSEQ_TOG (0x000001dc) + +#define BP_CLKCTRL_CLKSEQ_RSRVD0 19 +#define BM_CLKCTRL_CLKSEQ_RSRVD0 0xFFF80000 +#define BF_CLKCTRL_CLKSEQ_RSRVD0(v) \ + (((v) << 19) & BM_CLKCTRL_CLKSEQ_RSRVD0) +#define BM_CLKCTRL_CLKSEQ_BYPASS_CPU 0x00040000 +#define BP_CLKCTRL_CLKSEQ_RSRVD1 15 +#define BM_CLKCTRL_CLKSEQ_RSRVD1 0x00038000 +#define BF_CLKCTRL_CLKSEQ_RSRVD1(v) \ + (((v) << 15) & BM_CLKCTRL_CLKSEQ_RSRVD1) +#define BM_CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF 0x00004000 +#define BV_CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF__BYPASS 0x1 +#define BV_CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF__PFD 0x0 +#define BP_CLKCTRL_CLKSEQ_RSRVD2 9 +#define BM_CLKCTRL_CLKSEQ_RSRVD2 0x00003E00 +#define BF_CLKCTRL_CLKSEQ_RSRVD2(v) \ + (((v) << 9) & BM_CLKCTRL_CLKSEQ_RSRVD2) +#define BM_CLKCTRL_CLKSEQ_BYPASS_ETM 0x00000100 +#define BM_CLKCTRL_CLKSEQ_BYPASS_EMI 0x00000080 +#define BM_CLKCTRL_CLKSEQ_BYPASS_SSP3 0x00000040 +#define BM_CLKCTRL_CLKSEQ_BYPASS_SSP2 0x00000020 +#define BM_CLKCTRL_CLKSEQ_BYPASS_SSP1 0x00000010 +#define BM_CLKCTRL_CLKSEQ_BYPASS_SSP0 0x00000008 +#define BM_CLKCTRL_CLKSEQ_BYPASS_GPMI 0x00000004 +#define BM_CLKCTRL_CLKSEQ_BYPASS_SAIF1 0x00000002 +#define BM_CLKCTRL_CLKSEQ_BYPASS_SAIF0 0x00000001 + +#define HW_CLKCTRL_RESET (0x000001e0) + +#define BP_CLKCTRL_RESET_RSRVD 6 +#define BM_CLKCTRL_RESET_RSRVD 0xFFFFFFC0 +#define BF_CLKCTRL_RESET_RSRVD(v) \ + (((v) << 6) & BM_CLKCTRL_RESET_RSRVD) +#define BM_CLKCTRL_RESET_WDOG_POR_DISABLE 0x00000020 +#define BM_CLKCTRL_RESET_EXTERNAL_RESET_ENABLE 0x00000010 +#define BM_CLKCTRL_RESET_THERMAL_RESET_ENABLE 0x00000008 +#define BM_CLKCTRL_RESET_THERMAL_RESET_DEFAULT 0x00000004 +#define BM_CLKCTRL_RESET_CHIP 0x00000002 +#define BM_CLKCTRL_RESET_DIG 0x00000001 + +#define HW_CLKCTRL_STATUS (0x000001f0) + +#define BP_CLKCTRL_STATUS_CPU_LIMIT 30 +#define BM_CLKCTRL_STATUS_CPU_LIMIT 0xC0000000 +#define BF_CLKCTRL_STATUS_CPU_LIMIT(v) \ + (((v) << 30) & BM_CLKCTRL_STATUS_CPU_LIMIT) +#define BP_CLKCTRL_STATUS_RSRVD 0 +#define BM_CLKCTRL_STATUS_RSRVD 0x3FFFFFFF +#define BF_CLKCTRL_STATUS_RSRVD(v) \ + (((v) << 0) & BM_CLKCTRL_STATUS_RSRVD) + +#define HW_CLKCTRL_VERSION (0x00000200) + +#define BP_CLKCTRL_VERSION_MAJOR 24 +#define BM_CLKCTRL_VERSION_MAJOR 0xFF000000 +#define BF_CLKCTRL_VERSION_MAJOR(v) \ + (((v) << 24) & BM_CLKCTRL_VERSION_MAJOR) +#define BP_CLKCTRL_VERSION_MINOR 16 +#define BM_CLKCTRL_VERSION_MINOR 0x00FF0000 +#define BF_CLKCTRL_VERSION_MINOR(v) \ + (((v) << 16) & BM_CLKCTRL_VERSION_MINOR) +#define BP_CLKCTRL_VERSION_STEP 0 +#define BM_CLKCTRL_VERSION_STEP 0x0000FFFF +#define BF_CLKCTRL_VERSION_STEP(v) \ + (((v) << 0) & BM_CLKCTRL_VERSION_STEP) +#endif /* __ARCH_ARM___CLKCTRL_H */ diff --git a/include/asm-arm/arch-mx28/regs-enet.h b/include/asm-arm/arch-mx28/regs-enet.h new file mode 100644 index 0000000000..91aefe1649 --- /dev/null +++ b/include/asm-arm/arch-mx28/regs-enet.h @@ -0,0 +1,3562 @@ +/* + * Freescale ENET Register Definitions + * + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * This file is created by xml file. Don't Edit it. + * + * Xml Revision: 1.32 + * Template revision: 26195 + */ + +#ifndef __ARCH_ARM___ENET_H +#define __ARCH_ARM___ENET_H + + +#define HW_ENET_MAC0_EIR (0x00000000) + +#define BM_ENET_MAC0_EIR_RSRVD0 0x80000000 +#define BM_ENET_MAC0_EIR_BABR 0x40000000 +#define BM_ENET_MAC0_EIR_BABT 0x20000000 +#define BM_ENET_MAC0_EIR_GRA 0x10000000 +#define BM_ENET_MAC0_EIR_TXF 0x08000000 +#define BM_ENET_MAC0_EIR_TXB 0x04000000 +#define BM_ENET_MAC0_EIR_RXF 0x02000000 +#define BM_ENET_MAC0_EIR_RXB 0x01000000 +#define BM_ENET_MAC0_EIR_MII 0x00800000 +#define BM_ENET_MAC0_EIR_EBERR 0x00400000 +#define BM_ENET_MAC0_EIR_LC 0x00200000 +#define BM_ENET_MAC0_EIR_RL 0x00100000 +#define BM_ENET_MAC0_EIR_UN 0x00080000 +#define BM_ENET_MAC0_EIR_PLR 0x00040000 +#define BM_ENET_MAC0_EIR_WAKEUP 0x00020000 +#define BM_ENET_MAC0_EIR_TS_AVAIL 0x00010000 +#define BM_ENET_MAC0_EIR_TS_TIMER 0x00008000 +#define BP_ENET_MAC0_EIR_RSRVD1 0 +#define BM_ENET_MAC0_EIR_RSRVD1 0x00007FFF +#define BF_ENET_MAC0_EIR_RSRVD1(v) \ + (((v) << 0) & BM_ENET_MAC0_EIR_RSRVD1) + +#define HW_ENET_MAC0_EIMR (0x00000004) + +#define BP_ENET_MAC0_EIMR_EIMR 0 +#define BM_ENET_MAC0_EIMR_EIMR 0xFFFFFFFF +#define BF_ENET_MAC0_EIMR_EIMR(v) (v) + +#define HW_ENET_MAC0_RDAR (0x0000000c) + +#define BP_ENET_MAC0_RDAR_RSRVD0 25 +#define BM_ENET_MAC0_RDAR_RSRVD0 0xFE000000 +#define BF_ENET_MAC0_RDAR_RSRVD0(v) \ + (((v) << 25) & BM_ENET_MAC0_RDAR_RSRVD0) +#define BM_ENET_MAC0_RDAR_RDAR 0x01000000 +#define BP_ENET_MAC0_RDAR_RSRVD1 0 +#define BM_ENET_MAC0_RDAR_RSRVD1 0x00FFFFFF +#define BF_ENET_MAC0_RDAR_RSRVD1(v) \ + (((v) << 0) & BM_ENET_MAC0_RDAR_RSRVD1) + +#define HW_ENET_MAC0_TDAR (0x00000010) + +#define BP_ENET_MAC0_TDAR_RSRVD0 25 +#define BM_ENET_MAC0_TDAR_RSRVD0 0xFE000000 +#define BF_ENET_MAC0_TDAR_RSRVD0(v) \ + (((v) << 25) & BM_ENET_MAC0_TDAR_RSRVD0) +#define BM_ENET_MAC0_TDAR_TDAR 0x01000000 +#define BP_ENET_MAC0_TDAR_RSRVD1 0 +#define BM_ENET_MAC0_TDAR_RSRVD1 0x00FFFFFF +#define BF_ENET_MAC0_TDAR_RSRVD1(v) \ + (((v) << 0) & BM_ENET_MAC0_TDAR_RSRVD1) + +#define HW_ENET_MAC0_ECR (0x00000020) + +#define BP_ENET_MAC0_ECR_RSRVD0 7 +#define BM_ENET_MAC0_ECR_RSRVD0 0xFFFFFF80 +#define BF_ENET_MAC0_ECR_RSRVD0(v) \ + (((v) << 7) & BM_ENET_MAC0_ECR_RSRVD0) +#define BM_ENET_MAC0_ECR_DBG_EN 0x00000040 +#define BM_ENET_MAC0_ECR_ETH_SPEED 0x00000020 +#define BM_ENET_MAC0_ECR_ENA_1588 0x00000010 +#define BM_ENET_MAC0_ECR_SLEEP 0x00000008 +#define BM_ENET_MAC0_ECR_MAGIC_ENA 0x00000004 +#define BM_ENET_MAC0_ECR_ETHER_EN 0x00000002 +#define BM_ENET_MAC0_ECR_RESET 0x00000001 + +#define HW_ENET_MAC0_MMFR (0x0000003c) + +#define BP_ENET_MAC0_MMFR_ST 30 +#define BM_ENET_MAC0_MMFR_ST 0xC0000000 +#define BF_ENET_MAC0_MMFR_ST(v) \ + (((v) << 30) & BM_ENET_MAC0_MMFR_ST) +#define BP_ENET_MAC0_MMFR_OP 28 +#define BM_ENET_MAC0_MMFR_OP 0x30000000 +#define BF_ENET_MAC0_MMFR_OP(v) \ + (((v) << 28) & BM_ENET_MAC0_MMFR_OP) +#define BP_ENET_MAC0_MMFR_PA 23 +#define BM_ENET_MAC0_MMFR_PA 0x0F800000 +#define BF_ENET_MAC0_MMFR_PA(v) \ + (((v) << 23) & BM_ENET_MAC0_MMFR_PA) +#define BP_ENET_MAC0_MMFR_RA 18 +#define BM_ENET_MAC0_MMFR_RA 0x007C0000 +#define BF_ENET_MAC0_MMFR_RA(v) \ + (((v) << 18) & BM_ENET_MAC0_MMFR_RA) +#define BP_ENET_MAC0_MMFR_TA 16 +#define BM_ENET_MAC0_MMFR_TA 0x00030000 +#define BF_ENET_MAC0_MMFR_TA(v) \ + (((v) << 16) & BM_ENET_MAC0_MMFR_TA) +#define BP_ENET_MAC0_MMFR_DATA 0 +#define BM_ENET_MAC0_MMFR_DATA 0x0000FFFF +#define BF_ENET_MAC0_MMFR_DATA(v) \ + (((v) << 0) & BM_ENET_MAC0_MMFR_DATA) + +#define HW_ENET_MAC0_MSCR (0x00000040) + +#define BP_ENET_MAC0_MSCR_RSRVD0 11 +#define BM_ENET_MAC0_MSCR_RSRVD0 0xFFFFF800 +#define BF_ENET_MAC0_MSCR_RSRVD0(v) \ + (((v) << 11) & BM_ENET_MAC0_MSCR_RSRVD0) +#define BP_ENET_MAC0_MSCR_HOLDTIME 8 +#define BM_ENET_MAC0_MSCR_HOLDTIME 0x00000700 +#define BF_ENET_MAC0_MSCR_HOLDTIME(v) \ + (((v) << 8) & BM_ENET_MAC0_MSCR_HOLDTIME) +#define BM_ENET_MAC0_MSCR_DIS_PRE 0x00000080 +#define BP_ENET_MAC0_MSCR_MII_SPEED 1 +#define BM_ENET_MAC0_MSCR_MII_SPEED 0x0000007E +#define BF_ENET_MAC0_MSCR_MII_SPEED(v) \ + (((v) << 1) & BM_ENET_MAC0_MSCR_MII_SPEED) +#define BM_ENET_MAC0_MSCR_RSRVD1 0x00000001 + +#define HW_ENET_MAC0_MIBC (0x00000060) + +#define BM_ENET_MAC0_MIBC_MIB_DIS 0x80000000 +#define BM_ENET_MAC0_MIBC_MIB_IDLE 0x40000000 +#define BM_ENET_MAC0_MIBC_MIB_CLEAR 0x20000000 +#define BP_ENET_MAC0_MIBC_RSRVD0 0 +#define BM_ENET_MAC0_MIBC_RSRVD0 0x1FFFFFFF +#define BF_ENET_MAC0_MIBC_RSRVD0(v) \ + (((v) << 0) & BM_ENET_MAC0_MIBC_RSRVD0) + +#define HW_ENET_MAC0_RCR (0x00000080) + +#define BM_ENET_MAC0_RCR_GRS 0x80000000 +#define BM_ENET_MAC0_RCR_NO_LGTH_CHECK 0x40000000 +#define BP_ENET_MAC0_RCR_MAX_FL 16 +#define BM_ENET_MAC0_RCR_MAX_FL 0x3FFF0000 +#define BF_ENET_MAC0_RCR_MAX_FL(v) \ + (((v) << 16) & BM_ENET_MAC0_RCR_MAX_FL) +#define BM_ENET_MAC0_RCR_CNTL_FRM_ENA 0x00008000 +#define BM_ENET_MAC0_RCR_CRC_FWD 0x00004000 +#define BM_ENET_MAC0_RCR_PAUSE_FWD 0x00002000 +#define BM_ENET_MAC0_RCR_PAD_EN 0x00001000 +#define BM_ENET_MAC0_RCR_RMII_ECHO 0x00000800 +#define BM_ENET_MAC0_RCR_RMII_LOOP 0x00000400 +#define BM_ENET_MAC0_RCR_RMII_10T 0x00000200 +#define BM_ENET_MAC0_RCR_RMII_MODE 0x00000100 +#define BM_ENET_MAC0_RCR_SGMII_ENA 0x00000080 +#define BM_ENET_MAC0_RCR_RGMII_ENA 0x00000040 +#define BM_ENET_MAC0_RCR_FCE 0x00000020 +#define BM_ENET_MAC0_RCR_BC_REJ 0x00000010 +#define BM_ENET_MAC0_RCR_PROM 0x00000008 +#define BM_ENET_MAC0_RCR_MII_MODE 0x00000004 +#define BM_ENET_MAC0_RCR_DRT 0x00000002 +#define BM_ENET_MAC0_RCR_LOOP 0x00000001 + +#define HW_ENET_MAC0_TCR (0x000000c0) + +#define BP_ENET_MAC0_TCR_RSRVD0 10 +#define BM_ENET_MAC0_TCR_RSRVD0 0xFFFFFC00 +#define BF_ENET_MAC0_TCR_RSRVD0(v) \ + (((v) << 10) & BM_ENET_MAC0_TCR_RSRVD0) +#define BM_ENET_MAC0_TCR_TX_CRC_FWD 0x00000200 +#define BM_ENET_MAC0_TCR_TX_ADDR_INS 0x00000100 +#define BP_ENET_MAC0_TCR_TX_ADDR_SEL 5 +#define BM_ENET_MAC0_TCR_TX_ADDR_SEL 0x000000E0 +#define BF_ENET_MAC0_TCR_TX_ADDR_SEL(v) \ + (((v) << 5) & BM_ENET_MAC0_TCR_TX_ADDR_SEL) +#define BM_ENET_MAC0_TCR_RFC_PAUSE 0x00000010 +#define BM_ENET_MAC0_TCR_TFC_PAUSE 0x00000008 +#define BM_ENET_MAC0_TCR_FEDN 0x00000004 +#define BM_ENET_MAC0_TCR_HBC 0x00000002 +#define BM_ENET_MAC0_TCR_GTS 0x00000001 + +#define HW_ENET_MAC0_PALR (0x000000e0) + +#define BP_ENET_MAC0_PALR_PADDR1 0 +#define BM_ENET_MAC0_PALR_PADDR1 0xFFFFFFFF +#define BF_ENET_MAC0_PALR_PADDR1(v) (v) + +#define HW_ENET_MAC0_PAUR (0x000000e4) + +#define BP_ENET_MAC0_PAUR_PADDR2 16 +#define BM_ENET_MAC0_PAUR_PADDR2 0xFFFF0000 +#define BF_ENET_MAC0_PAUR_PADDR2(v) \ + (((v) << 16) & BM_ENET_MAC0_PAUR_PADDR2) +#define BP_ENET_MAC0_PAUR_TYPE 0 +#define BM_ENET_MAC0_PAUR_TYPE 0x0000FFFF +#define BF_ENET_MAC0_PAUR_TYPE(v) \ + (((v) << 0) & BM_ENET_MAC0_PAUR_TYPE) + +#define HW_ENET_MAC0_OPD (0x000000e8) + +#define BP_ENET_MAC0_OPD_OPCODE 16 +#define BM_ENET_MAC0_OPD_OPCODE 0xFFFF0000 +#define BF_ENET_MAC0_OPD_OPCODE(v) \ + (((v) << 16) & BM_ENET_MAC0_OPD_OPCODE) +#define BP_ENET_MAC0_OPD_PAUSE_DUR 0 +#define BM_ENET_MAC0_OPD_PAUSE_DUR 0x0000FFFF +#define BF_ENET_MAC0_OPD_PAUSE_DUR(v) \ + (((v) << 0) & BM_ENET_MAC0_OPD_PAUSE_DUR) + +#define HW_ENET_MAC0_IAUR (0x00000114) + +#define BP_ENET_MAC0_IAUR_IADDR1 0 +#define BM_ENET_MAC0_IAUR_IADDR1 0xFFFFFFFF +#define BF_ENET_MAC0_IAUR_IADDR1(v) (v) + +#define HW_ENET_MAC0_IALR (0x00000118) + +#define BP_ENET_MAC0_IALR_IADDR2 0 +#define BM_ENET_MAC0_IALR_IADDR2 0xFFFFFFFF +#define BF_ENET_MAC0_IALR_IADDR2(v) (v) + +#define HW_ENET_MAC0_GAUR (0x0000011c) + +#define BP_ENET_MAC0_GAUR_GADDR1 0 +#define BM_ENET_MAC0_GAUR_GADDR1 0xFFFFFFFF +#define BF_ENET_MAC0_GAUR_GADDR1(v) (v) + +#define HW_ENET_MAC0_GALR (0x00000120) + +#define BP_ENET_MAC0_GALR_GADDR2 0 +#define BM_ENET_MAC0_GALR_GADDR2 0xFFFFFFFF +#define BF_ENET_MAC0_GALR_GADDR2(v) (v) + +#define HW_ENET_MAC0_TFW_SFCR (0x00000140) + +#define BP_ENET_MAC0_TFW_SFCR_RSRVD0 9 +#define BM_ENET_MAC0_TFW_SFCR_RSRVD0 0xFFFFFE00 +#define BF_ENET_MAC0_TFW_SFCR_RSRVD0(v) \ + (((v) << 9) & BM_ENET_MAC0_TFW_SFCR_RSRVD0) +#define BM_ENET_MAC0_TFW_SFCR_STR_FWD 0x00000100 +#define BP_ENET_MAC0_TFW_SFCR_RSRVD1 6 +#define BM_ENET_MAC0_TFW_SFCR_RSRVD1 0x000000C0 +#define BF_ENET_MAC0_TFW_SFCR_RSRVD1(v) \ + (((v) << 6) & BM_ENET_MAC0_TFW_SFCR_RSRVD1) +#define BP_ENET_MAC0_TFW_SFCR_TFWR 0 +#define BM_ENET_MAC0_TFW_SFCR_TFWR 0x0000003F +#define BF_ENET_MAC0_TFW_SFCR_TFWR(v) \ + (((v) << 0) & BM_ENET_MAC0_TFW_SFCR_TFWR) + +#define HW_ENET_MAC0_FRBR (0x00000148) + +#define BP_ENET_MAC0_FRBR_RSRVD0 10 +#define BM_ENET_MAC0_FRBR_RSRVD0 0xFFFFFC00 +#define BF_ENET_MAC0_FRBR_RSRVD0(v) \ + (((v) << 10) & BM_ENET_MAC0_FRBR_RSRVD0) +#define BP_ENET_MAC0_FRBR_R_BOUND 2 +#define BM_ENET_MAC0_FRBR_R_BOUND 0x000003FC +#define BF_ENET_MAC0_FRBR_R_BOUND(v) \ + (((v) << 2) & BM_ENET_MAC0_FRBR_R_BOUND) +#define BP_ENET_MAC0_FRBR_RSRVD1 0 +#define BM_ENET_MAC0_FRBR_RSRVD1 0x00000003 +#define BF_ENET_MAC0_FRBR_RSRVD1(v) \ + (((v) << 0) & BM_ENET_MAC0_FRBR_RSRVD1) + +#define HW_ENET_MAC0_FRSR (0x0000014c) + +#define BP_ENET_MAC0_FRSR_RSRVD0 11 +#define BM_ENET_MAC0_FRSR_RSRVD0 0xFFFFF800 +#define BF_ENET_MAC0_FRSR_RSRVD0(v) \ + (((v) << 11) & BM_ENET_MAC0_FRSR_RSRVD0) +#define BM_ENET_MAC0_FRSR_RSRVD1 0x00000400 +#define BP_ENET_MAC0_FRSR_R_FSTART 2 +#define BM_ENET_MAC0_FRSR_R_FSTART 0x000003FC +#define BF_ENET_MAC0_FRSR_R_FSTART(v) \ + (((v) << 2) & BM_ENET_MAC0_FRSR_R_FSTART) +#define BP_ENET_MAC0_FRSR_RSRVD2 0 +#define BM_ENET_MAC0_FRSR_RSRVD2 0x00000003 +#define BF_ENET_MAC0_FRSR_RSRVD2(v) \ + (((v) << 0) & BM_ENET_MAC0_FRSR_RSRVD2) + +#define HW_ENET_MAC0_ERDSR (0x0000017c) + +#define BP_ENET_MAC0_ERDSR_R_DES_START 2 +#define BM_ENET_MAC0_ERDSR_R_DES_START 0xFFFFFFFC +#define BF_ENET_MAC0_ERDSR_R_DES_START(v) \ + (((v) << 2) & BM_ENET_MAC0_ERDSR_R_DES_START) +#define BP_ENET_MAC0_ERDSR_RSRVD0 0 +#define BM_ENET_MAC0_ERDSR_RSRVD0 0x00000003 +#define BF_ENET_MAC0_ERDSR_RSRVD0(v) \ + (((v) << 0) & BM_ENET_MAC0_ERDSR_RSRVD0) + +#define HW_ENET_MAC0_ETDSR (0x00000180) + +#define BP_ENET_MAC0_ETDSR_X_DES_START 2 +#define BM_ENET_MAC0_ETDSR_X_DES_START 0xFFFFFFFC +#define BF_ENET_MAC0_ETDSR_X_DES_START(v) \ + (((v) << 2) & BM_ENET_MAC0_ETDSR_X_DES_START) +#define BP_ENET_MAC0_ETDSR_RSRVD0 0 +#define BM_ENET_MAC0_ETDSR_RSRVD0 0x00000003 +#define BF_ENET_MAC0_ETDSR_RSRVD0(v) \ + (((v) << 0) & BM_ENET_MAC0_ETDSR_RSRVD0) + +#define HW_ENET_MAC0_EMRBR (0x00000184) + +#define BP_ENET_MAC0_EMRBR_RSRVD0 11 +#define BM_ENET_MAC0_EMRBR_RSRVD0 0xFFFFF800 +#define BF_ENET_MAC0_EMRBR_RSRVD0(v) \ + (((v) << 11) & BM_ENET_MAC0_EMRBR_RSRVD0) +#define BP_ENET_MAC0_EMRBR_R_BUF_SIZE 4 +#define BM_ENET_MAC0_EMRBR_R_BUF_SIZE 0x000007F0 +#define BF_ENET_MAC0_EMRBR_R_BUF_SIZE(v) \ + (((v) << 4) & BM_ENET_MAC0_EMRBR_R_BUF_SIZE) +#define BP_ENET_MAC0_EMRBR_RSRVD1 0 +#define BM_ENET_MAC0_EMRBR_RSRVD1 0x0000000F +#define BF_ENET_MAC0_EMRBR_RSRVD1(v) \ + (((v) << 0) & BM_ENET_MAC0_EMRBR_RSRVD1) + +#define HW_ENET_MAC0_RX_SECTION_FULL (0x0000018c) + +#define BP_ENET_MAC0_RX_SECTION_FULL_RSRVD0 8 +#define BM_ENET_MAC0_RX_SECTION_FULL_RSRVD0 0xFFFFFF00 +#define BF_ENET_MAC0_RX_SECTION_FULL_RSRVD0(v) \ + (((v) << 8) & BM_ENET_MAC0_RX_SECTION_FULL_RSRVD0) +#define BP_ENET_MAC0_RX_SECTION_FULL_RX_SECTION_FULL 0 +#define BM_ENET_MAC0_RX_SECTION_FULL_RX_SECTION_FULL 0x000000FF +#define BF_ENET_MAC0_RX_SECTION_FULL_RX_SECTION_FULL(v) \ + (((v) << 0) & BM_ENET_MAC0_RX_SECTION_FULL_RX_SECTION_FULL) + +#define HW_ENET_MAC0_RX_SECTION_EMPTY (0x00000190) + +#define BP_ENET_MAC0_RX_SECTION_EMPTY_RSRVD0 8 +#define BM_ENET_MAC0_RX_SECTION_EMPTY_RSRVD0 0xFFFFFF00 +#define BF_ENET_MAC0_RX_SECTION_EMPTY_RSRVD0(v) \ + (((v) << 8) & BM_ENET_MAC0_RX_SECTION_EMPTY_RSRVD0) +#define BP_ENET_MAC0_RX_SECTION_EMPTY_RX_SECTION_EMPTY 0 +#define BM_ENET_MAC0_RX_SECTION_EMPTY_RX_SECTION_EMPTY 0x000000FF +#define BF_ENET_MAC0_RX_SECTION_EMPTY_RX_SECTION_EMPTY(v) \ + (((v) << 0) & BM_ENET_MAC0_RX_SECTION_EMPTY_RX_SECTION_EMPTY) + +#define HW_ENET_MAC0_RX_ALMOST_EMPTY (0x00000194) + +#define BP_ENET_MAC0_RX_ALMOST_EMPTY_RSRVD0 8 +#define BM_ENET_MAC0_RX_ALMOST_EMPTY_RSRVD0 0xFFFFFF00 +#define BF_ENET_MAC0_RX_ALMOST_EMPTY_RSRVD0(v) \ + (((v) << 8) & BM_ENET_MAC0_RX_ALMOST_EMPTY_RSRVD0) +#define BP_ENET_MAC0_RX_ALMOST_EMPTY_RX_ALMOST_EMPTY 0 +#define BM_ENET_MAC0_RX_ALMOST_EMPTY_RX_ALMOST_EMPTY 0x000000FF +#define BF_ENET_MAC0_RX_ALMOST_EMPTY_RX_ALMOST_EMPTY(v) \ + (((v) << 0) & BM_ENET_MAC0_RX_ALMOST_EMPTY_RX_ALMOST_EMPTY) + +#define HW_ENET_MAC0_RX_ALMOST_FULL (0x00000198) + +#define BP_ENET_MAC0_RX_ALMOST_FULL_RSRVD0 8 +#define BM_ENET_MAC0_RX_ALMOST_FULL_RSRVD0 0xFFFFFF00 +#define BF_ENET_MAC0_RX_ALMOST_FULL_RSRVD0(v) \ + (((v) << 8) & BM_ENET_MAC0_RX_ALMOST_FULL_RSRVD0) +#define BP_ENET_MAC0_RX_ALMOST_FULL_RX_ALMOST_FULL 0 +#define BM_ENET_MAC0_RX_ALMOST_FULL_RX_ALMOST_FULL 0x000000FF +#define BF_ENET_MAC0_RX_ALMOST_FULL_RX_ALMOST_FULL(v) \ + (((v) << 0) & BM_ENET_MAC0_RX_ALMOST_FULL_RX_ALMOST_FULL) + +#define HW_ENET_MAC0_TX_SECTION_EMPTY (0x0000019c) + +#define BP_ENET_MAC0_TX_SECTION_EMPTY_RSRVD0 8 +#define BM_ENET_MAC0_TX_SECTION_EMPTY_RSRVD0 0xFFFFFF00 +#define BF_ENET_MAC0_TX_SECTION_EMPTY_RSRVD0(v) \ + (((v) << 8) & BM_ENET_MAC0_TX_SECTION_EMPTY_RSRVD0) +#define BP_ENET_MAC0_TX_SECTION_EMPTY_TX_SECTION_EMPTY 0 +#define BM_ENET_MAC0_TX_SECTION_EMPTY_TX_SECTION_EMPTY 0x000000FF +#define BF_ENET_MAC0_TX_SECTION_EMPTY_TX_SECTION_EMPTY(v) \ + (((v) << 0) & BM_ENET_MAC0_TX_SECTION_EMPTY_TX_SECTION_EMPTY) + +#define HW_ENET_MAC0_TX_ALMOST_EMPTY (0x000001a0) + +#define BP_ENET_MAC0_TX_ALMOST_EMPTY_RSRVD0 8 +#define BM_ENET_MAC0_TX_ALMOST_EMPTY_RSRVD0 0xFFFFFF00 +#define BF_ENET_MAC0_TX_ALMOST_EMPTY_RSRVD0(v) \ + (((v) << 8) & BM_ENET_MAC0_TX_ALMOST_EMPTY_RSRVD0) +#define BP_ENET_MAC0_TX_ALMOST_EMPTY_TX_ALMOST_EMPTY 0 +#define BM_ENET_MAC0_TX_ALMOST_EMPTY_TX_ALMOST_EMPTY 0x000000FF +#define BF_ENET_MAC0_TX_ALMOST_EMPTY_TX_ALMOST_EMPTY(v) \ + (((v) << 0) & BM_ENET_MAC0_TX_ALMOST_EMPTY_TX_ALMOST_EMPTY) + +#define HW_ENET_MAC0_TX_ALMOST_FULL (0x000001a4) + +#define BP_ENET_MAC0_TX_ALMOST_FULL_RSRVD0 8 +#define BM_ENET_MAC0_TX_ALMOST_FULL_RSRVD0 0xFFFFFF00 +#define BF_ENET_MAC0_TX_ALMOST_FULL_RSRVD0(v) \ + (((v) << 8) & BM_ENET_MAC0_TX_ALMOST_FULL_RSRVD0) +#define BP_ENET_MAC0_TX_ALMOST_FULL_TX_ALMOST_FULL 0 +#define BM_ENET_MAC0_TX_ALMOST_FULL_TX_ALMOST_FULL 0x000000FF +#define BF_ENET_MAC0_TX_ALMOST_FULL_TX_ALMOST_FULL(v) \ + (((v) << 0) & BM_ENET_MAC0_TX_ALMOST_FULL_TX_ALMOST_FULL) + +#define HW_ENET_MAC0_TX_IPG_LENGTH (0x000001a8) + +#define BP_ENET_MAC0_TX_IPG_LENGTH_RSRVD0 5 +#define BM_ENET_MAC0_TX_IPG_LENGTH_RSRVD0 0xFFFFFFE0 +#define BF_ENET_MAC0_TX_IPG_LENGTH_RSRVD0(v) \ + (((v) << 5) & BM_ENET_MAC0_TX_IPG_LENGTH_RSRVD0) +#define BP_ENET_MAC0_TX_IPG_LENGTH_TX_IPG_LENGTH 0 +#define BM_ENET_MAC0_TX_IPG_LENGTH_TX_IPG_LENGTH 0x0000001F +#define BF_ENET_MAC0_TX_IPG_LENGTH_TX_IPG_LENGTH(v) \ + (((v) << 0) & BM_ENET_MAC0_TX_IPG_LENGTH_TX_IPG_LENGTH) + +#define HW_ENET_MAC0_TRUNC_FL (0x000001ac) + +#define BP_ENET_MAC0_TRUNC_FL_RSRVD0 14 +#define BM_ENET_MAC0_TRUNC_FL_RSRVD0 0xFFFFC000 +#define BF_ENET_MAC0_TRUNC_FL_RSRVD0(v) \ + (((v) << 14) & BM_ENET_MAC0_TRUNC_FL_RSRVD0) +#define BP_ENET_MAC0_TRUNC_FL_TRUNC_FL 0 +#define BM_ENET_MAC0_TRUNC_FL_TRUNC_FL 0x00003FFF +#define BF_ENET_MAC0_TRUNC_FL_TRUNC_FL(v) \ + (((v) << 0) & BM_ENET_MAC0_TRUNC_FL_TRUNC_FL) + +#define HW_ENET_MAC0_IPACCTXCONF (0x000001bc) + +#define BP_ENET_MAC0_IPACCTXCONF_RSRVD0 5 +#define BM_ENET_MAC0_IPACCTXCONF_RSRVD0 0xFFFFFFE0 +#define BF_ENET_MAC0_IPACCTXCONF_RSRVD0(v) \ + (((v) << 5) & BM_ENET_MAC0_IPACCTXCONF_RSRVD0) +#define BM_ENET_MAC0_IPACCTXCONF_TX_PROTCHK_INS 0x00000010 +#define BM_ENET_MAC0_IPACCTXCONF_TX_IPCHK_INS 0x00000008 +#define BP_ENET_MAC0_IPACCTXCONF_RSRVD1 1 +#define BM_ENET_MAC0_IPACCTXCONF_RSRVD1 0x00000006 +#define BF_ENET_MAC0_IPACCTXCONF_RSRVD1(v) \ + (((v) << 1) & BM_ENET_MAC0_IPACCTXCONF_RSRVD1) +#define BM_ENET_MAC0_IPACCTXCONF_SHIFT16 0x00000001 + +#define HW_ENET_MAC0_IPACCRXCONF (0x000001c0) + +#define BP_ENET_MAC0_IPACCRXCONF_RSRVD0 8 +#define BM_ENET_MAC0_IPACCRXCONF_RSRVD0 0xFFFFFF00 +#define BF_ENET_MAC0_IPACCRXCONF_RSRVD0(v) \ + (((v) << 8) & BM_ENET_MAC0_IPACCRXCONF_RSRVD0) +#define BM_ENET_MAC0_IPACCRXCONF_SHIFT16 0x00000080 +#define BM_ENET_MAC0_IPACCRXCONF_RX_LINEERR_DISC 0x00000040 +#define BP_ENET_MAC0_IPACCRXCONF_RSRVD1 3 +#define BM_ENET_MAC0_IPACCRXCONF_RSRVD1 0x00000038 +#define BF_ENET_MAC0_IPACCRXCONF_RSRVD1(v) \ + (((v) << 3) & BM_ENET_MAC0_IPACCRXCONF_RSRVD1) +#define BM_ENET_MAC0_IPACCRXCONF_RX_PROTERR_DISCARD 0x00000004 +#define BM_ENET_MAC0_IPACCRXCONF_RX_IPERR_DISCARD 0x00000002 +#define BM_ENET_MAC0_IPACCRXCONF_RX_IP_PAD_REMOVE 0x00000001 + +#define HW_ENET_MAC0_RMON_T_DROP (0x000001fc) + +#define BP_ENET_MAC0_RMON_T_DROP_RMON_T_DROP 0 +#define BM_ENET_MAC0_RMON_T_DROP_RMON_T_DROP 0xFFFFFFFF +#define BF_ENET_MAC0_RMON_T_DROP_RMON_T_DROP(v) (v) + +#define HW_ENET_MAC0_RMON_T_PACKETS (0x00000200) + +#define BP_ENET_MAC0_RMON_T_PACKETS_RMON_T_PACKETS 0 +#define BM_ENET_MAC0_RMON_T_PACKETS_RMON_T_PACKETS 0xFFFFFFFF +#define BF_ENET_MAC0_RMON_T_PACKETS_RMON_T_PACKETS(v) (v) + +#define HW_ENET_MAC0_RMON_T_BC_PKT (0x00000204) + +#define BP_ENET_MAC0_RMON_T_BC_PKT_RMON_T_BC_PKT 0 +#define BM_ENET_MAC0_RMON_T_BC_PKT_RMON_T_BC_PKT 0xFFFFFFFF +#define BF_ENET_MAC0_RMON_T_BC_PKT_RMON_T_BC_PKT(v) (v) + +#define HW_ENET_MAC0_RMON_T_MC_PKT (0x00000208) + +#define BP_ENET_MAC0_RMON_T_MC_PKT_RMON_T_MC_PKT 0 +#define BM_ENET_MAC0_RMON_T_MC_PKT_RMON_T_MC_PKT 0xFFFFFFFF +#define BF_ENET_MAC0_RMON_T_MC_PKT_RMON_T_MC_PKT(v) (v) + +#define HW_ENET_MAC0_RMON_T_CRC_ALIGN (0x0000020c) + +#define BP_ENET_MAC0_RMON_T_CRC_ALIGN_RMON_T_CRC_ALIGN 0 +#define BM_ENET_MAC0_RMON_T_CRC_ALIGN_RMON_T_CRC_ALIGN 0xFFFFFFFF +#define BF_ENET_MAC0_RMON_T_CRC_ALIGN_RMON_T_CRC_ALIGN(v) (v) + +#define HW_ENET_MAC0_RMON_T_UNDERSIZE (0x00000210) + +#define BP_ENET_MAC0_RMON_T_UNDERSIZE_RMON_T_UNDERSIZE 0 +#define BM_ENET_MAC0_RMON_T_UNDERSIZE_RMON_T_UNDERSIZE 0xFFFFFFFF +#define BF_ENET_MAC0_RMON_T_UNDERSIZE_RMON_T_UNDERSIZE(v) (v) + +#define HW_ENET_MAC0_RMON_T_OVERSIZE (0x00000214) + +#define BP_ENET_MAC0_RMON_T_OVERSIZE_RMON_T_OVERSIZE 0 +#define BM_ENET_MAC0_RMON_T_OVERSIZE_RMON_T_OVERSIZE 0xFFFFFFFF +#define BF_ENET_MAC0_RMON_T_OVERSIZE_RMON_T_OVERSIZE(v) (v) + +#define HW_ENET_MAC0_RMON_T_FRAG (0x00000218) + +#define BP_ENET_MAC0_RMON_T_FRAG_RMON_T_FRAG 0 +#define BM_ENET_MAC0_RMON_T_FRAG_RMON_T_FRAG 0xFFFFFFFF +#define BF_ENET_MAC0_RMON_T_FRAG_RMON_T_FRAG(v) (v) + +#define HW_ENET_MAC0_RMON_T_JAB (0x0000021c) + +#define BP_ENET_MAC0_RMON_T_JAB_RMON_T_JAB 0 +#define BM_ENET_MAC0_RMON_T_JAB_RMON_T_JAB 0xFFFFFFFF +#define BF_ENET_MAC0_RMON_T_JAB_RMON_T_JAB(v) (v) + +#define HW_ENET_MAC0_RMON_T_COL (0x00000220) + +#define BP_ENET_MAC0_RMON_T_COL_RMON_T_COL 0 +#define BM_ENET_MAC0_RMON_T_COL_RMON_T_COL 0xFFFFFFFF +#define BF_ENET_MAC0_RMON_T_COL_RMON_T_COL(v) (v) + +#define HW_ENET_MAC0_RMON_T_P64 (0x00000224) + +#define BP_ENET_MAC0_RMON_T_P64_RMON_T_P64 0 +#define BM_ENET_MAC0_RMON_T_P64_RMON_T_P64 0xFFFFFFFF +#define BF_ENET_MAC0_RMON_T_P64_RMON_T_P64(v) (v) + +#define HW_ENET_MAC0_RMON_T_P65TO127N (0x00000228) + +#define BP_ENET_MAC0_RMON_T_P65TO127N_RMON_T_P65TO127N 0 +#define BM_ENET_MAC0_RMON_T_P65TO127N_RMON_T_P65TO127N 0xFFFFFFFF +#define BF_ENET_MAC0_RMON_T_P65TO127N_RMON_T_P65TO127N(v) (v) + +#define HW_ENET_MAC0_RMON_T_P128TO255N (0x0000022c) + +#define BP_ENET_MAC0_RMON_T_P128TO255N_RMON_T_P128TO255N 0 +#define BM_ENET_MAC0_RMON_T_P128TO255N_RMON_T_P128TO255N 0xFFFFFFFF +#define BF_ENET_MAC0_RMON_T_P128TO255N_RMON_T_P128TO255N(v) (v) + +#define HW_ENET_MAC0_RMON_T_P256TO511 (0x00000230) + +#define BP_ENET_MAC0_RMON_T_P256TO511_RMON_T_P256TO511 0 +#define BM_ENET_MAC0_RMON_T_P256TO511_RMON_T_P256TO511 0xFFFFFFFF +#define BF_ENET_MAC0_RMON_T_P256TO511_RMON_T_P256TO511(v) (v) + +#define HW_ENET_MAC0_RMON_T_P512TO1023 (0x00000234) + +#define BP_ENET_MAC0_RMON_T_P512TO1023_RMON_T_P512TO1023 0 +#define BM_ENET_MAC0_RMON_T_P512TO1023_RMON_T_P512TO1023 0xFFFFFFFF +#define BF_ENET_MAC0_RMON_T_P512TO1023_RMON_T_P512TO1023(v) (v) + +#define HW_ENET_MAC0_RMON_T_P1024TO2047 (0x00000238) + +#define BP_ENET_MAC0_RMON_T_P1024TO2047_RMON_T_P1024TO2047 0 +#define BM_ENET_MAC0_RMON_T_P1024TO2047_RMON_T_P1024TO2047 0xFFFFFFFF +#define BF_ENET_MAC0_RMON_T_P1024TO2047_RMON_T_P1024TO2047(v) (v) + +#define HW_ENET_MAC0_RMON_T_P_GTE2048 (0x0000023c) + +#define BP_ENET_MAC0_RMON_T_P_GTE2048_RMON_T_P_GTE2048 0 +#define BM_ENET_MAC0_RMON_T_P_GTE2048_RMON_T_P_GTE2048 0xFFFFFFFF +#define BF_ENET_MAC0_RMON_T_P_GTE2048_RMON_T_P_GTE2048(v) (v) + +#define HW_ENET_MAC0_RMON_T_OCTETS (0x00000240) + +#define BP_ENET_MAC0_RMON_T_OCTETS_RMON_T_OCTETS 0 +#define BM_ENET_MAC0_RMON_T_OCTETS_RMON_T_OCTETS 0xFFFFFFFF +#define BF_ENET_MAC0_RMON_T_OCTETS_RMON_T_OCTETS(v) (v) + +#define HW_ENET_MAC0_IEEE_T_DROP (0x00000244) + +#define BP_ENET_MAC0_IEEE_T_DROP_IEEE_T_DROP 0 +#define BM_ENET_MAC0_IEEE_T_DROP_IEEE_T_DROP 0xFFFFFFFF +#define BF_ENET_MAC0_IEEE_T_DROP_IEEE_T_DROP(v) (v) + +#define HW_ENET_MAC0_IEEE_T_FRAME_OK (0x00000248) + +#define BP_ENET_MAC0_IEEE_T_FRAME_OK_IEEE_T_FRAME_OK 0 +#define BM_ENET_MAC0_IEEE_T_FRAME_OK_IEEE_T_FRAME_OK 0xFFFFFFFF +#define BF_ENET_MAC0_IEEE_T_FRAME_OK_IEEE_T_FRAME_OK(v) (v) + +#define HW_ENET_MAC0_IEEE_T_1COL (0x0000024c) + +#define BP_ENET_MAC0_IEEE_T_1COL_IEEE_T_1COL 0 +#define BM_ENET_MAC0_IEEE_T_1COL_IEEE_T_1COL 0xFFFFFFFF +#define BF_ENET_MAC0_IEEE_T_1COL_IEEE_T_1COL(v) (v) + +#define HW_ENET_MAC0_IEEE_T_MCOL (0x00000250) + +#define BP_ENET_MAC0_IEEE_T_MCOL_IEEE_T_MCOL 0 +#define BM_ENET_MAC0_IEEE_T_MCOL_IEEE_T_MCOL 0xFFFFFFFF +#define BF_ENET_MAC0_IEEE_T_MCOL_IEEE_T_MCOL(v) (v) + +#define HW_ENET_MAC0_IEEE_T_DEF (0x00000254) + +#define BP_ENET_MAC0_IEEE_T_DEF_IEEE_T_DEF 0 +#define BM_ENET_MAC0_IEEE_T_DEF_IEEE_T_DEF 0xFFFFFFFF +#define BF_ENET_MAC0_IEEE_T_DEF_IEEE_T_DEF(v) (v) + +#define HW_ENET_MAC0_IEEE_T_LCOL (0x00000258) + +#define BP_ENET_MAC0_IEEE_T_LCOL_IEEE_T_LCOL 0 +#define BM_ENET_MAC0_IEEE_T_LCOL_IEEE_T_LCOL 0xFFFFFFFF +#define BF_ENET_MAC0_IEEE_T_LCOL_IEEE_T_LCOL(v) (v) + +#define HW_ENET_MAC0_IEEE_T_EXCOL (0x0000025c) + +#define BP_ENET_MAC0_IEEE_T_EXCOL_IEEE_T_EXCOL 0 +#define BM_ENET_MAC0_IEEE_T_EXCOL_IEEE_T_EXCOL 0xFFFFFFFF +#define BF_ENET_MAC0_IEEE_T_EXCOL_IEEE_T_EXCOL(v) (v) + +#define HW_ENET_MAC0_IEEE_T_MACERR (0x00000260) + +#define BP_ENET_MAC0_IEEE_T_MACERR_IEEE_T_MACERR 0 +#define BM_ENET_MAC0_IEEE_T_MACERR_IEEE_T_MACERR 0xFFFFFFFF +#define BF_ENET_MAC0_IEEE_T_MACERR_IEEE_T_MACERR(v) (v) + +#define HW_ENET_MAC0_IEEE_T_CSERR (0x00000264) + +#define BP_ENET_MAC0_IEEE_T_CSERR_IEEE_T_CSERR 0 +#define BM_ENET_MAC0_IEEE_T_CSERR_IEEE_T_CSERR 0xFFFFFFFF +#define BF_ENET_MAC0_IEEE_T_CSERR_IEEE_T_CSERR(v) (v) + +#define HW_ENET_MAC0_IEEE_T_SQE (0x00000268) + +#define BP_ENET_MAC0_IEEE_T_SQE_IEEE_T_SQE 0 +#define BM_ENET_MAC0_IEEE_T_SQE_IEEE_T_SQE 0xFFFFFFFF +#define BF_ENET_MAC0_IEEE_T_SQE_IEEE_T_SQE(v) (v) + +#define HW_ENET_MAC0_IEEE_T_FDXFC (0x0000026c) + +#define BP_ENET_MAC0_IEEE_T_FDXFC_IEEE_T_FDXFC 0 +#define BM_ENET_MAC0_IEEE_T_FDXFC_IEEE_T_FDXFC 0xFFFFFFFF +#define BF_ENET_MAC0_IEEE_T_FDXFC_IEEE_T_FDXFC(v) (v) + +#define HW_ENET_MAC0_IEEE_T_OCTETS_OK (0x00000270) + +#define BP_ENET_MAC0_IEEE_T_OCTETS_OK_IEEE_T_OCTETS_OK 0 +#define BM_ENET_MAC0_IEEE_T_OCTETS_OK_IEEE_T_OCTETS_OK 0xFFFFFFFF +#define BF_ENET_MAC0_IEEE_T_OCTETS_OK_IEEE_T_OCTETS_OK(v) (v) + +#define HW_ENET_MAC0_RMON_R_PACKETS (0x00000280) + +#define BP_ENET_MAC0_RMON_R_PACKETS_RMON_R_PACKETS 0 +#define BM_ENET_MAC0_RMON_R_PACKETS_RMON_R_PACKETS 0xFFFFFFFF +#define BF_ENET_MAC0_RMON_R_PACKETS_RMON_R_PACKETS(v) (v) + +#define HW_ENET_MAC0_RMON_R_BC_PKT (0x00000284) + +#define BP_ENET_MAC0_RMON_R_BC_PKT_RMON_R_BC_PKT 0 +#define BM_ENET_MAC0_RMON_R_BC_PKT_RMON_R_BC_PKT 0xFFFFFFFF +#define BF_ENET_MAC0_RMON_R_BC_PKT_RMON_R_BC_PKT(v) (v) + +#define HW_ENET_MAC0_RMON_R_MC_PKT (0x00000288) + +#define BP_ENET_MAC0_RMON_R_MC_PKT_RMON_R_MC_PKT 0 +#define BM_ENET_MAC0_RMON_R_MC_PKT_RMON_R_MC_PKT 0xFFFFFFFF +#define BF_ENET_MAC0_RMON_R_MC_PKT_RMON_R_MC_PKT(v) (v) + +#define HW_ENET_MAC0_RMON_R_CRC_ALIGN (0x0000028c) + +#define BP_ENET_MAC0_RMON_R_CRC_ALIGN_RMON_R_CRC_ALIGN 0 +#define BM_ENET_MAC0_RMON_R_CRC_ALIGN_RMON_R_CRC_ALIGN 0xFFFFFFFF +#define BF_ENET_MAC0_RMON_R_CRC_ALIGN_RMON_R_CRC_ALIGN(v) (v) + +#define HW_ENET_MAC0_RMON_R_UNDERSIZE (0x00000290) + +#define BP_ENET_MAC0_RMON_R_UNDERSIZE_RMON_R_UNDERSIZE 0 +#define BM_ENET_MAC0_RMON_R_UNDERSIZE_RMON_R_UNDERSIZE 0xFFFFFFFF +#define BF_ENET_MAC0_RMON_R_UNDERSIZE_RMON_R_UNDERSIZE(v) (v) + +#define HW_ENET_MAC0_RMON_R_OVERSIZE (0x00000294) + +#define BP_ENET_MAC0_RMON_R_OVERSIZE_RMON_R_OVERSIZE 0 +#define BM_ENET_MAC0_RMON_R_OVERSIZE_RMON_R_OVERSIZE 0xFFFFFFFF +#define BF_ENET_MAC0_RMON_R_OVERSIZE_RMON_R_OVERSIZE(v) (v) + +#define HW_ENET_MAC0_RMON_R_FRAG (0x00000298) + +#define BP_ENET_MAC0_RMON_R_FRAG_RMON_R_FRAG 0 +#define BM_ENET_MAC0_RMON_R_FRAG_RMON_R_FRAG 0xFFFFFFFF +#define BF_ENET_MAC0_RMON_R_FRAG_RMON_R_FRAG(v) (v) + +#define HW_ENET_MAC0_RMON_R_JAB (0x0000029c) + +#define BP_ENET_MAC0_RMON_R_JAB_RMON_R_JAB 0 +#define BM_ENET_MAC0_RMON_R_JAB_RMON_R_JAB 0xFFFFFFFF +#define BF_ENET_MAC0_RMON_R_JAB_RMON_R_JAB(v) (v) + +#define HW_ENET_MAC0_RMON_R_P64 (0x000002a4) + +#define BP_ENET_MAC0_RMON_R_P64_RMON_R_P64 0 +#define BM_ENET_MAC0_RMON_R_P64_RMON_R_P64 0xFFFFFFFF +#define BF_ENET_MAC0_RMON_R_P64_RMON_R_P64(v) (v) + +#define HW_ENET_MAC0_RMON_R_P65TO127 (0x000002a8) + +#define BP_ENET_MAC0_RMON_R_P65TO127_RMON_R_P65TO127 0 +#define BM_ENET_MAC0_RMON_R_P65TO127_RMON_R_P65TO127 0xFFFFFFFF +#define BF_ENET_MAC0_RMON_R_P65TO127_RMON_R_P65TO127(v) (v) + +#define HW_ENET_MAC0_RMON_R_P128TO255 (0x000002ac) + +#define BP_ENET_MAC0_RMON_R_P128TO255_RMON_R_P128TO255 0 +#define BM_ENET_MAC0_RMON_R_P128TO255_RMON_R_P128TO255 0xFFFFFFFF +#define BF_ENET_MAC0_RMON_R_P128TO255_RMON_R_P128TO255(v) (v) + +#define HW_ENET_MAC0_RMON_R_P256TO511 (0x000002b0) + +#define BP_ENET_MAC0_RMON_R_P256TO511_RMON_R_P256TO511 0 +#define BM_ENET_MAC0_RMON_R_P256TO511_RMON_R_P256TO511 0xFFFFFFFF +#define BF_ENET_MAC0_RMON_R_P256TO511_RMON_R_P256TO511(v) (v) + +#define HW_ENET_MAC0_RMON_R_P512TO1023 (0x000002b4) + +#define BP_ENET_MAC0_RMON_R_P512TO1023_RMON_R_P512TO1023 0 +#define BM_ENET_MAC0_RMON_R_P512TO1023_RMON_R_P512TO1023 0xFFFFFFFF +#define BF_ENET_MAC0_RMON_R_P512TO1023_RMON_R_P512TO1023(v) (v) + +#define HW_ENET_MAC0_RMON_R_P1024TO2047 (0x000002b8) + +#define BP_ENET_MAC0_RMON_R_P1024TO2047_RMON_R_P1024TO2047 0 +#define BM_ENET_MAC0_RMON_R_P1024TO2047_RMON_R_P1024TO2047 0xFFFFFFFF +#define BF_ENET_MAC0_RMON_R_P1024TO2047_RMON_R_P1024TO2047(v) (v) + +#define HW_ENET_MAC0_RMON_R_P_GTE2048 (0x000002bc) + +#define BP_ENET_MAC0_RMON_R_P_GTE2048_RMON_R_P_GTE2048 0 +#define BM_ENET_MAC0_RMON_R_P_GTE2048_RMON_R_P_GTE2048 0xFFFFFFFF +#define BF_ENET_MAC0_RMON_R_P_GTE2048_RMON_R_P_GTE2048(v) (v) + +#define HW_ENET_MAC0_RMON_R_OCTETS (0x000002c0) + +#define BP_ENET_MAC0_RMON_R_OCTETS_RMON_R_OCTETS 0 +#define BM_ENET_MAC0_RMON_R_OCTETS_RMON_R_OCTETS 0xFFFFFFFF +#define BF_ENET_MAC0_RMON_R_OCTETS_RMON_R_OCTETS(v) (v) + +#define HW_ENET_MAC0_IEEE_R_DROP (0x000002c4) + +#define BP_ENET_MAC0_IEEE_R_DROP_IEEE_R_DROP 0 +#define BM_ENET_MAC0_IEEE_R_DROP_IEEE_R_DROP 0xFFFFFFFF +#define BF_ENET_MAC0_IEEE_R_DROP_IEEE_R_DROP(v) (v) + +#define HW_ENET_MAC0_IEEE_R_FRAME_OK (0x000002c8) + +#define BP_ENET_MAC0_IEEE_R_FRAME_OK_IEEE_R_FRAME_OK 0 +#define BM_ENET_MAC0_IEEE_R_FRAME_OK_IEEE_R_FRAME_OK 0xFFFFFFFF +#define BF_ENET_MAC0_IEEE_R_FRAME_OK_IEEE_R_FRAME_OK(v) (v) + +#define HW_ENET_MAC0_IEEE_R_CRC (0x000002cc) + +#define BP_ENET_MAC0_IEEE_R_CRC_IEEE_R_CRC 0 +#define BM_ENET_MAC0_IEEE_R_CRC_IEEE_R_CRC 0xFFFFFFFF +#define BF_ENET_MAC0_IEEE_R_CRC_IEEE_R_CRC(v) (v) + +#define HW_ENET_MAC0_IEEE_R_ALIGN (0x000002d0) + +#define BP_ENET_MAC0_IEEE_R_ALIGN_IEEE_R_ALIGN 0 +#define BM_ENET_MAC0_IEEE_R_ALIGN_IEEE_R_ALIGN 0xFFFFFFFF +#define BF_ENET_MAC0_IEEE_R_ALIGN_IEEE_R_ALIGN(v) (v) + +#define HW_ENET_MAC0_IEEE_R_MACERR (0x000002d4) + +#define BP_ENET_MAC0_IEEE_R_MACERR_IEEE_R_MACERR 0 +#define BM_ENET_MAC0_IEEE_R_MACERR_IEEE_R_MACERR 0xFFFFFFFF +#define BF_ENET_MAC0_IEEE_R_MACERR_IEEE_R_MACERR(v) (v) + +#define HW_ENET_MAC0_IEEE_R_FDXFC (0x000002d8) + +#define BP_ENET_MAC0_IEEE_R_FDXFC_IEEE_R_FDXFC 0 +#define BM_ENET_MAC0_IEEE_R_FDXFC_IEEE_R_FDXFC 0xFFFFFFFF +#define BF_ENET_MAC0_IEEE_R_FDXFC_IEEE_R_FDXFC(v) (v) + +#define HW_ENET_MAC0_IEEE_R_OCTETS_OK (0x000002dc) + +#define BP_ENET_MAC0_IEEE_R_OCTETS_OK_IEEE_R_OCTETS_OK 0 +#define BM_ENET_MAC0_IEEE_R_OCTETS_OK_IEEE_R_OCTETS_OK 0xFFFFFFFF +#define BF_ENET_MAC0_IEEE_R_OCTETS_OK_IEEE_R_OCTETS_OK(v) (v) + +#define HW_ENET_MAC0_ATIME_CTRL (0x000003fc) + +#define BP_ENET_MAC0_ATIME_CTRL_RSRVD0 14 +#define BM_ENET_MAC0_ATIME_CTRL_RSRVD0 0xFFFFC000 +#define BF_ENET_MAC0_ATIME_CTRL_RSRVD0(v) \ + (((v) << 14) & BM_ENET_MAC0_ATIME_CTRL_RSRVD0) +#define BM_ENET_MAC0_ATIME_CTRL_FRC_SLAVE 0x00002000 +#define BM_ENET_MAC0_ATIME_CTRL_RSRVD1 0x00001000 +#define BM_ENET_MAC0_ATIME_CTRL_CAPTURE 0x00000800 +#define BM_ENET_MAC0_ATIME_CTRL_RSRVD2 0x00000400 +#define BM_ENET_MAC0_ATIME_CTRL_RESTART 0x00000200 +#define BM_ENET_MAC0_ATIME_CTRL_RSRVD3 0x00000100 +#define BM_ENET_MAC0_ATIME_CTRL_PIN_PERIOD_ENA 0x00000080 +#define BM_ENET_MAC0_ATIME_CTRL_RSRVD4 0x00000040 +#define BM_ENET_MAC0_ATIME_CTRL_EVT_PERIOD_RST 0x00000020 +#define BM_ENET_MAC0_ATIME_CTRL_EVT_PERIOD_ENA 0x00000010 +#define BM_ENET_MAC0_ATIME_CTRL_EVT_OFFSET_RST 0x00000008 +#define BM_ENET_MAC0_ATIME_CTRL_EVT_OFFSET_ENA 0x00000004 +#define BM_ENET_MAC0_ATIME_CTRL_ONE_SHOT 0x00000002 +#define BM_ENET_MAC0_ATIME_CTRL_ENABLE 0x00000001 + +#define HW_ENET_MAC0_ATIME (0x00000400) + +#define BP_ENET_MAC0_ATIME_ATIME 0 +#define BM_ENET_MAC0_ATIME_ATIME 0xFFFFFFFF +#define BF_ENET_MAC0_ATIME_ATIME(v) (v) + +#define HW_ENET_MAC0_ATIME_EVT_OFFSET (0x00000404) + +#define BP_ENET_MAC0_ATIME_EVT_OFFSET_ATIME_EVT_OFFSET 0 +#define BM_ENET_MAC0_ATIME_EVT_OFFSET_ATIME_EVT_OFFSET 0xFFFFFFFF +#define BF_ENET_MAC0_ATIME_EVT_OFFSET_ATIME_EVT_OFFSET(v) (v) + +#define HW_ENET_MAC0_ATIME_EVT_PERIOD (0x00000408) + +#define BP_ENET_MAC0_ATIME_EVT_PERIOD_ATIME_EVT_PERIOD 0 +#define BM_ENET_MAC0_ATIME_EVT_PERIOD_ATIME_EVT_PERIOD 0xFFFFFFFF +#define BF_ENET_MAC0_ATIME_EVT_PERIOD_ATIME_EVT_PERIOD(v) (v) + +#define HW_ENET_MAC0_ATIME_CORR (0x0000040c) + +#define BM_ENET_MAC0_ATIME_CORR_RSRVD0 0x80000000 +#define BP_ENET_MAC0_ATIME_CORR_ATIME_CORR 0 +#define BM_ENET_MAC0_ATIME_CORR_ATIME_CORR 0x7FFFFFFF +#define BF_ENET_MAC0_ATIME_CORR_ATIME_CORR(v) \ + (((v) << 0) & BM_ENET_MAC0_ATIME_CORR_ATIME_CORR) + +#define HW_ENET_MAC0_ATIME_INC (0x00000410) + +#define BP_ENET_MAC0_ATIME_INC_RSRVD0 15 +#define BM_ENET_MAC0_ATIME_INC_RSRVD0 0xFFFF8000 +#define BF_ENET_MAC0_ATIME_INC_RSRVD0(v) \ + (((v) << 15) & BM_ENET_MAC0_ATIME_INC_RSRVD0) +#define BP_ENET_MAC0_ATIME_INC_ATIME_INC_CORR 8 +#define BM_ENET_MAC0_ATIME_INC_ATIME_INC_CORR 0x00007F00 +#define BF_ENET_MAC0_ATIME_INC_ATIME_INC_CORR(v) \ + (((v) << 8) & BM_ENET_MAC0_ATIME_INC_ATIME_INC_CORR) +#define BM_ENET_MAC0_ATIME_INC_RSRVD1 0x00000080 +#define BP_ENET_MAC0_ATIME_INC_ATIME_INC 0 +#define BM_ENET_MAC0_ATIME_INC_ATIME_INC 0x0000007F +#define BF_ENET_MAC0_ATIME_INC_ATIME_INC(v) \ + (((v) << 0) & BM_ENET_MAC0_ATIME_INC_ATIME_INC) + +#define HW_ENET_MAC0_TS_TIMESTAMP (0x00000414) + +#define BP_ENET_MAC0_TS_TIMESTAMP_TS_TIMESTAMP 0 +#define BM_ENET_MAC0_TS_TIMESTAMP_TS_TIMESTAMP 0xFFFFFFFF +#define BF_ENET_MAC0_TS_TIMESTAMP_TS_TIMESTAMP(v) (v) + +#define HW_ENET_MAC0_SMAC_0_0 (0x000004fc) + +#define BP_ENET_MAC0_SMAC_0_0_SMAC_0_0 0 +#define BM_ENET_MAC0_SMAC_0_0_SMAC_0_0 0xFFFFFFFF +#define BF_ENET_MAC0_SMAC_0_0_SMAC_0_0(v) (v) + +#define HW_ENET_MAC0_SMAC_0_1 (0x00000500) + +#define BP_ENET_MAC0_SMAC_0_1_SMAC_0_1 0 +#define BM_ENET_MAC0_SMAC_0_1_SMAC_0_1 0xFFFFFFFF +#define BF_ENET_MAC0_SMAC_0_1_SMAC_0_1(v) (v) + +#define HW_ENET_MAC0_SMAC_1_0 (0x00000504) + +#define BP_ENET_MAC0_SMAC_1_0_SMAC_1_0 0 +#define BM_ENET_MAC0_SMAC_1_0_SMAC_1_0 0xFFFFFFFF +#define BF_ENET_MAC0_SMAC_1_0_SMAC_1_0(v) (v) + +#define HW_ENET_MAC0_SMAC_1_1 (0x00000508) + +#define BP_ENET_MAC0_SMAC_1_1_SMAC_1_1 0 +#define BM_ENET_MAC0_SMAC_1_1_SMAC_1_1 0xFFFFFFFF +#define BF_ENET_MAC0_SMAC_1_1_SMAC_1_1(v) (v) + +#define HW_ENET_MAC0_SMAC_2_0 (0x0000050c) + +#define BP_ENET_MAC0_SMAC_2_0_SMAC_2_0 0 +#define BM_ENET_MAC0_SMAC_2_0_SMAC_2_0 0xFFFFFFFF +#define BF_ENET_MAC0_SMAC_2_0_SMAC_2_0(v) (v) + +#define HW_ENET_MAC0_SMAC_2_1 (0x00000510) + +#define BP_ENET_MAC0_SMAC_2_1_SMAC_2_1 0 +#define BM_ENET_MAC0_SMAC_2_1_SMAC_2_1 0xFFFFFFFF +#define BF_ENET_MAC0_SMAC_2_1_SMAC_2_1(v) (v) + +#define HW_ENET_MAC0_SMAC_3_0 (0x00000514) + +#define BP_ENET_MAC0_SMAC_3_0_SMAC_3_0 0 +#define BM_ENET_MAC0_SMAC_3_0_SMAC_3_0 0xFFFFFFFF +#define BF_ENET_MAC0_SMAC_3_0_SMAC_3_0(v) (v) + +#define HW_ENET_MAC0_SMAC_3_1 (0x00000518) + +#define BP_ENET_MAC0_SMAC_3_1_SMAC_3_1 0 +#define BM_ENET_MAC0_SMAC_3_1_SMAC_3_1 0xFFFFFFFF +#define BF_ENET_MAC0_SMAC_3_1_SMAC_3_1(v) (v) + +#define HW_ENET_MAC0_COMP_REG_0 (0x000005fc) + +#define BP_ENET_MAC0_COMP_REG_0_COMP_REG_0 0 +#define BM_ENET_MAC0_COMP_REG_0_COMP_REG_0 0xFFFFFFFF +#define BF_ENET_MAC0_COMP_REG_0_COMP_REG_0(v) (v) + +#define HW_ENET_MAC0_COMP_REG_1 (0x00000600) + +#define BP_ENET_MAC0_COMP_REG_1_COMP_REG_1 0 +#define BM_ENET_MAC0_COMP_REG_1_COMP_REG_1 0xFFFFFFFF +#define BF_ENET_MAC0_COMP_REG_1_COMP_REG_1(v) (v) + +#define HW_ENET_MAC0_COMP_REG_2 (0x00000604) + +#define BP_ENET_MAC0_COMP_REG_2_COMP_REG_2 0 +#define BM_ENET_MAC0_COMP_REG_2_COMP_REG_2 0xFFFFFFFF +#define BF_ENET_MAC0_COMP_REG_2_COMP_REG_2(v) (v) + +#define HW_ENET_MAC0_COMP_REG_3 (0x00000608) + +#define BP_ENET_MAC0_COMP_REG_3_COMP_REG_3 0 +#define BM_ENET_MAC0_COMP_REG_3_COMP_REG_3 0xFFFFFFFF +#define BF_ENET_MAC0_COMP_REG_3_COMP_REG_3(v) (v) + +#define HW_ENET_MAC0_CAPT_REG_0 (0x0000063c) + +#define BP_ENET_MAC0_CAPT_REG_0_CAPT_REG_0 0 +#define BM_ENET_MAC0_CAPT_REG_0_CAPT_REG_0 0xFFFFFFFF +#define BF_ENET_MAC0_CAPT_REG_0_CAPT_REG_0(v) (v) + +#define HW_ENET_MAC0_CAPT_REG_1 (0x00000640) + +#define BP_ENET_MAC0_CAPT_REG_1_CAPT_REG_1 0 +#define BM_ENET_MAC0_CAPT_REG_1_CAPT_REG_1 0xFFFFFFFF +#define BF_ENET_MAC0_CAPT_REG_1_CAPT_REG_1(v) (v) + +#define HW_ENET_MAC0_CAPT_REG_2 (0x00000644) + +#define BP_ENET_MAC0_CAPT_REG_2_CAPT_REG_2 0 +#define BM_ENET_MAC0_CAPT_REG_2_CAPT_REG_2 0xFFFFFFFF +#define BF_ENET_MAC0_CAPT_REG_2_CAPT_REG_2(v) (v) + +#define HW_ENET_MAC0_CAPT_REG_3 (0x00000648) + +#define BP_ENET_MAC0_CAPT_REG_3_CAPT_REG_3 0 +#define BM_ENET_MAC0_CAPT_REG_3_CAPT_REG_3 0xFFFFFFFF +#define BF_ENET_MAC0_CAPT_REG_3_CAPT_REG_3(v) (v) + +#define HW_ENET_MAC0_CCB_INT (0x0000067c) + +#define BP_ENET_MAC0_CCB_INT_RSRVD0 20 +#define BM_ENET_MAC0_CCB_INT_RSRVD0 0xFFF00000 +#define BF_ENET_MAC0_CCB_INT_RSRVD0(v) \ + (((v) << 20) & BM_ENET_MAC0_CCB_INT_RSRVD0) +#define BM_ENET_MAC0_CCB_INT_COMPARE3 0x00080000 +#define BM_ENET_MAC0_CCB_INT_COMPARE2 0x00040000 +#define BM_ENET_MAC0_CCB_INT_COMPARE1 0x00020000 +#define BM_ENET_MAC0_CCB_INT_COMPARE0 0x00010000 +#define BP_ENET_MAC0_CCB_INT_RSRVD1 4 +#define BM_ENET_MAC0_CCB_INT_RSRVD1 0x0000FFF0 +#define BF_ENET_MAC0_CCB_INT_RSRVD1(v) \ + (((v) << 4) & BM_ENET_MAC0_CCB_INT_RSRVD1) +#define BM_ENET_MAC0_CCB_INT_CAPTURE3 0x00000008 +#define BM_ENET_MAC0_CCB_INT_CAPTURE2 0x00000004 +#define BM_ENET_MAC0_CCB_INT_CAPTURE1 0x00000002 +#define BM_ENET_MAC0_CCB_INT_CAPTURE0 0x00000001 + +#define HW_ENET_MAC0_CCB_INT_MASK (0x00000680) + +#define BP_ENET_MAC0_CCB_INT_MASK_RSRVD0 20 +#define BM_ENET_MAC0_CCB_INT_MASK_RSRVD0 0xFFF00000 +#define BF_ENET_MAC0_CCB_INT_MASK_RSRVD0(v) \ + (((v) << 20) & BM_ENET_MAC0_CCB_INT_MASK_RSRVD0) +#define BM_ENET_MAC0_CCB_INT_MASK_COMPARE3 0x00080000 +#define BM_ENET_MAC0_CCB_INT_MASK_COMPARE2 0x00040000 +#define BM_ENET_MAC0_CCB_INT_MASK_COMPARE1 0x00020000 +#define BM_ENET_MAC0_CCB_INT_MASK_COMPARE0 0x00010000 +#define BP_ENET_MAC0_CCB_INT_MASK_RSRVD1 4 +#define BM_ENET_MAC0_CCB_INT_MASK_RSRVD1 0x0000FFF0 +#define BF_ENET_MAC0_CCB_INT_MASK_RSRVD1(v) \ + (((v) << 4) & BM_ENET_MAC0_CCB_INT_MASK_RSRVD1) +#define BM_ENET_MAC0_CCB_INT_MASK_CAPTURE3 0x00000008 +#define BM_ENET_MAC0_CCB_INT_MASK_CAPTURE2 0x00000004 +#define BM_ENET_MAC0_CCB_INT_MASK_CAPTURE1 0x00000002 +#define BM_ENET_MAC0_CCB_INT_MASK_CAPTURE0 0x00000001 + +#define HW_ENET_MAC1_EIR (0x00004000) + +#define BM_ENET_MAC1_EIR_RSRVD0 0x80000000 +#define BM_ENET_MAC1_EIR_BABR 0x40000000 +#define BM_ENET_MAC1_EIR_BABT 0x20000000 +#define BM_ENET_MAC1_EIR_GRA 0x10000000 +#define BM_ENET_MAC1_EIR_TXF 0x08000000 +#define BM_ENET_MAC1_EIR_TXB 0x04000000 +#define BM_ENET_MAC1_EIR_RXF 0x02000000 +#define BM_ENET_MAC1_EIR_RXB 0x01000000 +#define BM_ENET_MAC1_EIR_MII 0x00800000 +#define BM_ENET_MAC1_EIR_EBERR 0x00400000 +#define BM_ENET_MAC1_EIR_LC 0x00200000 +#define BM_ENET_MAC1_EIR_RL 0x00100000 +#define BM_ENET_MAC1_EIR_UN 0x00080000 +#define BM_ENET_MAC1_EIR_PLR 0x00040000 +#define BM_ENET_MAC1_EIR_WAKEUP 0x00020000 +#define BM_ENET_MAC1_EIR_TS_AVAIL 0x00010000 +#define BM_ENET_MAC1_EIR_TS_TIMER 0x00008000 +#define BP_ENET_MAC1_EIR_RSRVD1 0 +#define BM_ENET_MAC1_EIR_RSRVD1 0x00007FFF +#define BF_ENET_MAC1_EIR_RSRVD1(v) \ + (((v) << 0) & BM_ENET_MAC1_EIR_RSRVD1) + +#define HW_ENET_MAC1_EIMR (0x00004004) + +#define BP_ENET_MAC1_EIMR_EIMR 0 +#define BM_ENET_MAC1_EIMR_EIMR 0xFFFFFFFF +#define BF_ENET_MAC1_EIMR_EIMR(v) (v) + +#define HW_ENET_MAC1_RDAR (0x0000400c) + +#define BP_ENET_MAC1_RDAR_RSRVD0 25 +#define BM_ENET_MAC1_RDAR_RSRVD0 0xFE000000 +#define BF_ENET_MAC1_RDAR_RSRVD0(v) \ + (((v) << 25) & BM_ENET_MAC1_RDAR_RSRVD0) +#define BM_ENET_MAC1_RDAR_RDAR 0x01000000 +#define BP_ENET_MAC1_RDAR_RSRVD1 0 +#define BM_ENET_MAC1_RDAR_RSRVD1 0x00FFFFFF +#define BF_ENET_MAC1_RDAR_RSRVD1(v) \ + (((v) << 0) & BM_ENET_MAC1_RDAR_RSRVD1) + +#define HW_ENET_MAC1_TDAR (0x00004010) + +#define BP_ENET_MAC1_TDAR_RSRVD0 25 +#define BM_ENET_MAC1_TDAR_RSRVD0 0xFE000000 +#define BF_ENET_MAC1_TDAR_RSRVD0(v) \ + (((v) << 25) & BM_ENET_MAC1_TDAR_RSRVD0) +#define BM_ENET_MAC1_TDAR_TDAR 0x01000000 +#define BP_ENET_MAC1_TDAR_RSRVD1 0 +#define BM_ENET_MAC1_TDAR_RSRVD1 0x00FFFFFF +#define BF_ENET_MAC1_TDAR_RSRVD1(v) \ + (((v) << 0) & BM_ENET_MAC1_TDAR_RSRVD1) + +#define HW_ENET_MAC1_ECR (0x00004020) + +#define BP_ENET_MAC1_ECR_RSRVD0 7 +#define BM_ENET_MAC1_ECR_RSRVD0 0xFFFFFF80 +#define BF_ENET_MAC1_ECR_RSRVD0(v) \ + (((v) << 7) & BM_ENET_MAC1_ECR_RSRVD0) +#define BM_ENET_MAC1_ECR_DBG_EN 0x00000040 +#define BM_ENET_MAC1_ECR_ETH_SPEED 0x00000020 +#define BM_ENET_MAC1_ECR_ENA_1588 0x00000010 +#define BM_ENET_MAC1_ECR_SLEEP 0x00000008 +#define BM_ENET_MAC1_ECR_MAGIC_ENA 0x00000004 +#define BM_ENET_MAC1_ECR_ETHER_EN 0x00000002 +#define BM_ENET_MAC1_ECR_RESET 0x00000001 + +#define HW_ENET_MAC1_MMFR (0x0000403c) + +#define BP_ENET_MAC1_MMFR_ST 30 +#define BM_ENET_MAC1_MMFR_ST 0xC0000000 +#define BF_ENET_MAC1_MMFR_ST(v) \ + (((v) << 30) & BM_ENET_MAC1_MMFR_ST) +#define BP_ENET_MAC1_MMFR_OP 28 +#define BM_ENET_MAC1_MMFR_OP 0x30000000 +#define BF_ENET_MAC1_MMFR_OP(v) \ + (((v) << 28) & BM_ENET_MAC1_MMFR_OP) +#define BP_ENET_MAC1_MMFR_PA 23 +#define BM_ENET_MAC1_MMFR_PA 0x0F800000 +#define BF_ENET_MAC1_MMFR_PA(v) \ + (((v) << 23) & BM_ENET_MAC1_MMFR_PA) +#define BP_ENET_MAC1_MMFR_RA 18 +#define BM_ENET_MAC1_MMFR_RA 0x007C0000 +#define BF_ENET_MAC1_MMFR_RA(v) \ + (((v) << 18) & BM_ENET_MAC1_MMFR_RA) +#define BP_ENET_MAC1_MMFR_TA 16 +#define BM_ENET_MAC1_MMFR_TA 0x00030000 +#define BF_ENET_MAC1_MMFR_TA(v) \ + (((v) << 16) & BM_ENET_MAC1_MMFR_TA) +#define BP_ENET_MAC1_MMFR_DATA 0 +#define BM_ENET_MAC1_MMFR_DATA 0x0000FFFF +#define BF_ENET_MAC1_MMFR_DATA(v) \ + (((v) << 0) & BM_ENET_MAC1_MMFR_DATA) + +#define HW_ENET_MAC1_MSCR (0x00004040) + +#define BP_ENET_MAC1_MSCR_RSRVD0 11 +#define BM_ENET_MAC1_MSCR_RSRVD0 0xFFFFF800 +#define BF_ENET_MAC1_MSCR_RSRVD0(v) \ + (((v) << 11) & BM_ENET_MAC1_MSCR_RSRVD0) +#define BP_ENET_MAC1_MSCR_HOLDTIME 8 +#define BM_ENET_MAC1_MSCR_HOLDTIME 0x00000700 +#define BF_ENET_MAC1_MSCR_HOLDTIME(v) \ + (((v) << 8) & BM_ENET_MAC1_MSCR_HOLDTIME) +#define BM_ENET_MAC1_MSCR_DIS_PRE 0x00000080 +#define BP_ENET_MAC1_MSCR_MII_SPEED 1 +#define BM_ENET_MAC1_MSCR_MII_SPEED 0x0000007E +#define BF_ENET_MAC1_MSCR_MII_SPEED(v) \ + (((v) << 1) & BM_ENET_MAC1_MSCR_MII_SPEED) +#define BM_ENET_MAC1_MSCR_RSRVD1 0x00000001 + +#define HW_ENET_MAC1_MIBC (0x00004060) + +#define BM_ENET_MAC1_MIBC_MIB_DIS 0x80000000 +#define BM_ENET_MAC1_MIBC_MIB_IDLE 0x40000000 +#define BM_ENET_MAC1_MIBC_MIB_CLEAR 0x20000000 +#define BP_ENET_MAC1_MIBC_RSRVD0 0 +#define BM_ENET_MAC1_MIBC_RSRVD0 0x1FFFFFFF +#define BF_ENET_MAC1_MIBC_RSRVD0(v) \ + (((v) << 0) & BM_ENET_MAC1_MIBC_RSRVD0) + +#define HW_ENET_MAC1_RCR (0x00004080) + +#define BM_ENET_MAC1_RCR_GRS 0x80000000 +#define BM_ENET_MAC1_RCR_NO_LGTH_CHECK 0x40000000 +#define BP_ENET_MAC1_RCR_MAX_FL 16 +#define BM_ENET_MAC1_RCR_MAX_FL 0x3FFF0000 +#define BF_ENET_MAC1_RCR_MAX_FL(v) \ + (((v) << 16) & BM_ENET_MAC1_RCR_MAX_FL) +#define BM_ENET_MAC1_RCR_CNTL_FRM_ENA 0x00008000 +#define BM_ENET_MAC1_RCR_CRC_FWD 0x00004000 +#define BM_ENET_MAC1_RCR_PAUSE_FWD 0x00002000 +#define BM_ENET_MAC1_RCR_PAD_EN 0x00001000 +#define BM_ENET_MAC1_RCR_RMII_ECHO 0x00000800 +#define BM_ENET_MAC1_RCR_RMII_LOOP 0x00000400 +#define BM_ENET_MAC1_RCR_RMII_10T 0x00000200 +#define BM_ENET_MAC1_RCR_RMII_MODE 0x00000100 +#define BM_ENET_MAC1_RCR_SGMII_ENA 0x00000080 +#define BM_ENET_MAC1_RCR_RGMII_ENA 0x00000040 +#define BM_ENET_MAC1_RCR_FCE 0x00000020 +#define BM_ENET_MAC1_RCR_BC_REJ 0x00000010 +#define BM_ENET_MAC1_RCR_PROM 0x00000008 +#define BM_ENET_MAC1_RCR_MII_MODE 0x00000004 +#define BM_ENET_MAC1_RCR_DRT 0x00000002 +#define BM_ENET_MAC1_RCR_LOOP 0x00000001 + +#define HW_ENET_MAC1_TCR (0x000040c0) + +#define BP_ENET_MAC1_TCR_RSRVD0 10 +#define BM_ENET_MAC1_TCR_RSRVD0 0xFFFFFC00 +#define BF_ENET_MAC1_TCR_RSRVD0(v) \ + (((v) << 10) & BM_ENET_MAC1_TCR_RSRVD0) +#define BM_ENET_MAC1_TCR_TX_CRC_FWD 0x00000200 +#define BM_ENET_MAC1_TCR_TX_ADDR_INS 0x00000100 +#define BP_ENET_MAC1_TCR_TX_ADDR_SEL 5 +#define BM_ENET_MAC1_TCR_TX_ADDR_SEL 0x000000E0 +#define BF_ENET_MAC1_TCR_TX_ADDR_SEL(v) \ + (((v) << 5) & BM_ENET_MAC1_TCR_TX_ADDR_SEL) +#define BM_ENET_MAC1_TCR_RFC_PAUSE 0x00000010 +#define BM_ENET_MAC1_TCR_TFC_PAUSE 0x00000008 +#define BM_ENET_MAC1_TCR_FEDN 0x00000004 +#define BM_ENET_MAC1_TCR_HBC 0x00000002 +#define BM_ENET_MAC1_TCR_GTS 0x00000001 + +#define HW_ENET_MAC1_PALR (0x000040e0) + +#define BP_ENET_MAC1_PALR_PADDR1 0 +#define BM_ENET_MAC1_PALR_PADDR1 0xFFFFFFFF +#define BF_ENET_MAC1_PALR_PADDR1(v) (v) + +#define HW_ENET_MAC1_PAUR (0x000040e4) + +#define BP_ENET_MAC1_PAUR_PADDR2 16 +#define BM_ENET_MAC1_PAUR_PADDR2 0xFFFF0000 +#define BF_ENET_MAC1_PAUR_PADDR2(v) \ + (((v) << 16) & BM_ENET_MAC1_PAUR_PADDR2) +#define BP_ENET_MAC1_PAUR_TYPE 0 +#define BM_ENET_MAC1_PAUR_TYPE 0x0000FFFF +#define BF_ENET_MAC1_PAUR_TYPE(v) \ + (((v) << 0) & BM_ENET_MAC1_PAUR_TYPE) + +#define HW_ENET_MAC1_OPD (0x000040e8) + +#define BP_ENET_MAC1_OPD_OPCODE 16 +#define BM_ENET_MAC1_OPD_OPCODE 0xFFFF0000 +#define BF_ENET_MAC1_OPD_OPCODE(v) \ + (((v) << 16) & BM_ENET_MAC1_OPD_OPCODE) +#define BP_ENET_MAC1_OPD_PAUSE_DUR 0 +#define BM_ENET_MAC1_OPD_PAUSE_DUR 0x0000FFFF +#define BF_ENET_MAC1_OPD_PAUSE_DUR(v) \ + (((v) << 0) & BM_ENET_MAC1_OPD_PAUSE_DUR) + +#define HW_ENET_MAC1_IAUR (0x00004114) + +#define BP_ENET_MAC1_IAUR_IADDR1 0 +#define BM_ENET_MAC1_IAUR_IADDR1 0xFFFFFFFF +#define BF_ENET_MAC1_IAUR_IADDR1(v) (v) + +#define HW_ENET_MAC1_IALR (0x00004118) + +#define BP_ENET_MAC1_IALR_IADDR2 0 +#define BM_ENET_MAC1_IALR_IADDR2 0xFFFFFFFF +#define BF_ENET_MAC1_IALR_IADDR2(v) (v) + +#define HW_ENET_MAC1_GAUR (0x0000411c) + +#define BP_ENET_MAC1_GAUR_GADDR1 0 +#define BM_ENET_MAC1_GAUR_GADDR1 0xFFFFFFFF +#define BF_ENET_MAC1_GAUR_GADDR1(v) (v) + +#define HW_ENET_MAC1_GALR (0x00004120) + +#define BP_ENET_MAC1_GALR_GADDR2 0 +#define BM_ENET_MAC1_GALR_GADDR2 0xFFFFFFFF +#define BF_ENET_MAC1_GALR_GADDR2(v) (v) + +#define HW_ENET_MAC1_TFW_SFCR (0x00004140) + +#define BP_ENET_MAC1_TFW_SFCR_RSRVD0 9 +#define BM_ENET_MAC1_TFW_SFCR_RSRVD0 0xFFFFFE00 +#define BF_ENET_MAC1_TFW_SFCR_RSRVD0(v) \ + (((v) << 9) & BM_ENET_MAC1_TFW_SFCR_RSRVD0) +#define BM_ENET_MAC1_TFW_SFCR_STR_FWD 0x00000100 +#define BP_ENET_MAC1_TFW_SFCR_RSRVD1 6 +#define BM_ENET_MAC1_TFW_SFCR_RSRVD1 0x000000C0 +#define BF_ENET_MAC1_TFW_SFCR_RSRVD1(v) \ + (((v) << 6) & BM_ENET_MAC1_TFW_SFCR_RSRVD1) +#define BP_ENET_MAC1_TFW_SFCR_TFWR 0 +#define BM_ENET_MAC1_TFW_SFCR_TFWR 0x0000003F +#define BF_ENET_MAC1_TFW_SFCR_TFWR(v) \ + (((v) << 0) & BM_ENET_MAC1_TFW_SFCR_TFWR) + +#define HW_ENET_MAC1_FRBR (0x00004148) + +#define BP_ENET_MAC1_FRBR_RSRVD0 10 +#define BM_ENET_MAC1_FRBR_RSRVD0 0xFFFFFC00 +#define BF_ENET_MAC1_FRBR_RSRVD0(v) \ + (((v) << 10) & BM_ENET_MAC1_FRBR_RSRVD0) +#define BP_ENET_MAC1_FRBR_R_BOUND 2 +#define BM_ENET_MAC1_FRBR_R_BOUND 0x000003FC +#define BF_ENET_MAC1_FRBR_R_BOUND(v) \ + (((v) << 2) & BM_ENET_MAC1_FRBR_R_BOUND) +#define BP_ENET_MAC1_FRBR_RSRVD1 0 +#define BM_ENET_MAC1_FRBR_RSRVD1 0x00000003 +#define BF_ENET_MAC1_FRBR_RSRVD1(v) \ + (((v) << 0) & BM_ENET_MAC1_FRBR_RSRVD1) + +#define HW_ENET_MAC1_FRSR (0x0000414c) + +#define BP_ENET_MAC1_FRSR_RSRVD0 11 +#define BM_ENET_MAC1_FRSR_RSRVD0 0xFFFFF800 +#define BF_ENET_MAC1_FRSR_RSRVD0(v) \ + (((v) << 11) & BM_ENET_MAC1_FRSR_RSRVD0) +#define BM_ENET_MAC1_FRSR_RSRVD1 0x00000400 +#define BP_ENET_MAC1_FRSR_R_FSTART 2 +#define BM_ENET_MAC1_FRSR_R_FSTART 0x000003FC +#define BF_ENET_MAC1_FRSR_R_FSTART(v) \ + (((v) << 2) & BM_ENET_MAC1_FRSR_R_FSTART) +#define BP_ENET_MAC1_FRSR_RSRVD2 0 +#define BM_ENET_MAC1_FRSR_RSRVD2 0x00000003 +#define BF_ENET_MAC1_FRSR_RSRVD2(v) \ + (((v) << 0) & BM_ENET_MAC1_FRSR_RSRVD2) + +#define HW_ENET_MAC1_ERDSR (0x0000417c) + +#define BP_ENET_MAC1_ERDSR_R_DES_START 2 +#define BM_ENET_MAC1_ERDSR_R_DES_START 0xFFFFFFFC +#define BF_ENET_MAC1_ERDSR_R_DES_START(v) \ + (((v) << 2) & BM_ENET_MAC1_ERDSR_R_DES_START) +#define BP_ENET_MAC1_ERDSR_RSRVD0 0 +#define BM_ENET_MAC1_ERDSR_RSRVD0 0x00000003 +#define BF_ENET_MAC1_ERDSR_RSRVD0(v) \ + (((v) << 0) & BM_ENET_MAC1_ERDSR_RSRVD0) + +#define HW_ENET_MAC1_ETDSR (0x00004180) + +#define BP_ENET_MAC1_ETDSR_X_DES_START 2 +#define BM_ENET_MAC1_ETDSR_X_DES_START 0xFFFFFFFC +#define BF_ENET_MAC1_ETDSR_X_DES_START(v) \ + (((v) << 2) & BM_ENET_MAC1_ETDSR_X_DES_START) +#define BP_ENET_MAC1_ETDSR_RSRVD0 0 +#define BM_ENET_MAC1_ETDSR_RSRVD0 0x00000003 +#define BF_ENET_MAC1_ETDSR_RSRVD0(v) \ + (((v) << 0) & BM_ENET_MAC1_ETDSR_RSRVD0) + +#define HW_ENET_MAC1_EMRBR (0x00004184) + +#define BP_ENET_MAC1_EMRBR_RSRVD0 11 +#define BM_ENET_MAC1_EMRBR_RSRVD0 0xFFFFF800 +#define BF_ENET_MAC1_EMRBR_RSRVD0(v) \ + (((v) << 11) & BM_ENET_MAC1_EMRBR_RSRVD0) +#define BP_ENET_MAC1_EMRBR_R_BUF_SIZE 4 +#define BM_ENET_MAC1_EMRBR_R_BUF_SIZE 0x000007F0 +#define BF_ENET_MAC1_EMRBR_R_BUF_SIZE(v) \ + (((v) << 4) & BM_ENET_MAC1_EMRBR_R_BUF_SIZE) +#define BP_ENET_MAC1_EMRBR_RSRVD1 0 +#define BM_ENET_MAC1_EMRBR_RSRVD1 0x0000000F +#define BF_ENET_MAC1_EMRBR_RSRVD1(v) \ + (((v) << 0) & BM_ENET_MAC1_EMRBR_RSRVD1) + +#define HW_ENET_MAC1_RX_SECTION_FULL (0x0000418c) + +#define BP_ENET_MAC1_RX_SECTION_FULL_RSRVD0 8 +#define BM_ENET_MAC1_RX_SECTION_FULL_RSRVD0 0xFFFFFF00 +#define BF_ENET_MAC1_RX_SECTION_FULL_RSRVD0(v) \ + (((v) << 8) & BM_ENET_MAC1_RX_SECTION_FULL_RSRVD0) +#define BP_ENET_MAC1_RX_SECTION_FULL_RX_SECTION_FULL 0 +#define BM_ENET_MAC1_RX_SECTION_FULL_RX_SECTION_FULL 0x000000FF +#define BF_ENET_MAC1_RX_SECTION_FULL_RX_SECTION_FULL(v) \ + (((v) << 0) & BM_ENET_MAC1_RX_SECTION_FULL_RX_SECTION_FULL) + +#define HW_ENET_MAC1_RX_SECTION_EMPTY (0x00004190) + +#define BP_ENET_MAC1_RX_SECTION_EMPTY_RSRVD0 8 +#define BM_ENET_MAC1_RX_SECTION_EMPTY_RSRVD0 0xFFFFFF00 +#define BF_ENET_MAC1_RX_SECTION_EMPTY_RSRVD0(v) \ + (((v) << 8) & BM_ENET_MAC1_RX_SECTION_EMPTY_RSRVD0) +#define BP_ENET_MAC1_RX_SECTION_EMPTY_RX_SECTION_EMPTY 0 +#define BM_ENET_MAC1_RX_SECTION_EMPTY_RX_SECTION_EMPTY 0x000000FF +#define BF_ENET_MAC1_RX_SECTION_EMPTY_RX_SECTION_EMPTY(v) \ + (((v) << 0) & BM_ENET_MAC1_RX_SECTION_EMPTY_RX_SECTION_EMPTY) + +#define HW_ENET_MAC1_RX_ALMOST_EMPTY (0x00004194) + +#define BP_ENET_MAC1_RX_ALMOST_EMPTY_RSRVD0 8 +#define BM_ENET_MAC1_RX_ALMOST_EMPTY_RSRVD0 0xFFFFFF00 +#define BF_ENET_MAC1_RX_ALMOST_EMPTY_RSRVD0(v) \ + (((v) << 8) & BM_ENET_MAC1_RX_ALMOST_EMPTY_RSRVD0) +#define BP_ENET_MAC1_RX_ALMOST_EMPTY_RX_ALMOST_EMPTY 0 +#define BM_ENET_MAC1_RX_ALMOST_EMPTY_RX_ALMOST_EMPTY 0x000000FF +#define BF_ENET_MAC1_RX_ALMOST_EMPTY_RX_ALMOST_EMPTY(v) \ + (((v) << 0) & BM_ENET_MAC1_RX_ALMOST_EMPTY_RX_ALMOST_EMPTY) + +#define HW_ENET_MAC1_RX_ALMOST_FULL (0x00004198) + +#define BP_ENET_MAC1_RX_ALMOST_FULL_RSRVD0 8 +#define BM_ENET_MAC1_RX_ALMOST_FULL_RSRVD0 0xFFFFFF00 +#define BF_ENET_MAC1_RX_ALMOST_FULL_RSRVD0(v) \ + (((v) << 8) & BM_ENET_MAC1_RX_ALMOST_FULL_RSRVD0) +#define BP_ENET_MAC1_RX_ALMOST_FULL_RX_ALMOST_FULL 0 +#define BM_ENET_MAC1_RX_ALMOST_FULL_RX_ALMOST_FULL 0x000000FF +#define BF_ENET_MAC1_RX_ALMOST_FULL_RX_ALMOST_FULL(v) \ + (((v) << 0) & BM_ENET_MAC1_RX_ALMOST_FULL_RX_ALMOST_FULL) + +#define HW_ENET_MAC1_TX_SECTION_EMPTY (0x0000419c) + +#define BP_ENET_MAC1_TX_SECTION_EMPTY_RSRVD0 8 +#define BM_ENET_MAC1_TX_SECTION_EMPTY_RSRVD0 0xFFFFFF00 +#define BF_ENET_MAC1_TX_SECTION_EMPTY_RSRVD0(v) \ + (((v) << 8) & BM_ENET_MAC1_TX_SECTION_EMPTY_RSRVD0) +#define BP_ENET_MAC1_TX_SECTION_EMPTY_TX_SECTION_EMPTY 0 +#define BM_ENET_MAC1_TX_SECTION_EMPTY_TX_SECTION_EMPTY 0x000000FF +#define BF_ENET_MAC1_TX_SECTION_EMPTY_TX_SECTION_EMPTY(v) \ + (((v) << 0) & BM_ENET_MAC1_TX_SECTION_EMPTY_TX_SECTION_EMPTY) + +#define HW_ENET_MAC1_TX_ALMOST_EMPTY (0x000041a0) + +#define BP_ENET_MAC1_TX_ALMOST_EMPTY_RSRVD0 8 +#define BM_ENET_MAC1_TX_ALMOST_EMPTY_RSRVD0 0xFFFFFF00 +#define BF_ENET_MAC1_TX_ALMOST_EMPTY_RSRVD0(v) \ + (((v) << 8) & BM_ENET_MAC1_TX_ALMOST_EMPTY_RSRVD0) +#define BP_ENET_MAC1_TX_ALMOST_EMPTY_TX_ALMOST_EMPTY 0 +#define BM_ENET_MAC1_TX_ALMOST_EMPTY_TX_ALMOST_EMPTY 0x000000FF +#define BF_ENET_MAC1_TX_ALMOST_EMPTY_TX_ALMOST_EMPTY(v) \ + (((v) << 0) & BM_ENET_MAC1_TX_ALMOST_EMPTY_TX_ALMOST_EMPTY) + +#define HW_ENET_MAC1_TX_ALMOST_FULL (0x000041a4) + +#define BP_ENET_MAC1_TX_ALMOST_FULL_RSRVD0 8 +#define BM_ENET_MAC1_TX_ALMOST_FULL_RSRVD0 0xFFFFFF00 +#define BF_ENET_MAC1_TX_ALMOST_FULL_RSRVD0(v) \ + (((v) << 8) & BM_ENET_MAC1_TX_ALMOST_FULL_RSRVD0) +#define BP_ENET_MAC1_TX_ALMOST_FULL_TX_ALMOST_FULL 0 +#define BM_ENET_MAC1_TX_ALMOST_FULL_TX_ALMOST_FULL 0x000000FF +#define BF_ENET_MAC1_TX_ALMOST_FULL_TX_ALMOST_FULL(v) \ + (((v) << 0) & BM_ENET_MAC1_TX_ALMOST_FULL_TX_ALMOST_FULL) + +#define HW_ENET_MAC1_TX_IPG_LENGTH (0x000041a8) + +#define BP_ENET_MAC1_TX_IPG_LENGTH_RSRVD0 5 +#define BM_ENET_MAC1_TX_IPG_LENGTH_RSRVD0 0xFFFFFFE0 +#define BF_ENET_MAC1_TX_IPG_LENGTH_RSRVD0(v) \ + (((v) << 5) & BM_ENET_MAC1_TX_IPG_LENGTH_RSRVD0) +#define BP_ENET_MAC1_TX_IPG_LENGTH_TX_IPG_LENGTH 0 +#define BM_ENET_MAC1_TX_IPG_LENGTH_TX_IPG_LENGTH 0x0000001F +#define BF_ENET_MAC1_TX_IPG_LENGTH_TX_IPG_LENGTH(v) \ + (((v) << 0) & BM_ENET_MAC1_TX_IPG_LENGTH_TX_IPG_LENGTH) + +#define HW_ENET_MAC1_TRUNC_FL (0x000041ac) + +#define BP_ENET_MAC1_TRUNC_FL_RSRVD0 14 +#define BM_ENET_MAC1_TRUNC_FL_RSRVD0 0xFFFFC000 +#define BF_ENET_MAC1_TRUNC_FL_RSRVD0(v) \ + (((v) << 14) & BM_ENET_MAC1_TRUNC_FL_RSRVD0) +#define BP_ENET_MAC1_TRUNC_FL_TRUNC_FL 0 +#define BM_ENET_MAC1_TRUNC_FL_TRUNC_FL 0x00003FFF +#define BF_ENET_MAC1_TRUNC_FL_TRUNC_FL(v) \ + (((v) << 0) & BM_ENET_MAC1_TRUNC_FL_TRUNC_FL) + +#define HW_ENET_MAC1_IPACCTXCONF (0x000041bc) + +#define BP_ENET_MAC1_IPACCTXCONF_RSRVD0 5 +#define BM_ENET_MAC1_IPACCTXCONF_RSRVD0 0xFFFFFFE0 +#define BF_ENET_MAC1_IPACCTXCONF_RSRVD0(v) \ + (((v) << 5) & BM_ENET_MAC1_IPACCTXCONF_RSRVD0) +#define BM_ENET_MAC1_IPACCTXCONF_TX_PROTCHK_INS 0x00000010 +#define BM_ENET_MAC1_IPACCTXCONF_TX_IPCHK_INS 0x00000008 +#define BP_ENET_MAC1_IPACCTXCONF_RSRVD1 1 +#define BM_ENET_MAC1_IPACCTXCONF_RSRVD1 0x00000006 +#define BF_ENET_MAC1_IPACCTXCONF_RSRVD1(v) \ + (((v) << 1) & BM_ENET_MAC1_IPACCTXCONF_RSRVD1) +#define BM_ENET_MAC1_IPACCTXCONF_SHIFT16 0x00000001 + +#define HW_ENET_MAC1_IPACCRXCONF (0x000041c0) + +#define BP_ENET_MAC1_IPACCRXCONF_RSRVD0 8 +#define BM_ENET_MAC1_IPACCRXCONF_RSRVD0 0xFFFFFF00 +#define BF_ENET_MAC1_IPACCRXCONF_RSRVD0(v) \ + (((v) << 8) & BM_ENET_MAC1_IPACCRXCONF_RSRVD0) +#define BM_ENET_MAC1_IPACCRXCONF_SHIFT16 0x00000080 +#define BM_ENET_MAC1_IPACCRXCONF_RX_LINEERR_DISC 0x00000040 +#define BP_ENET_MAC1_IPACCRXCONF_RSRVD1 3 +#define BM_ENET_MAC1_IPACCRXCONF_RSRVD1 0x00000038 +#define BF_ENET_MAC1_IPACCRXCONF_RSRVD1(v) \ + (((v) << 3) & BM_ENET_MAC1_IPACCRXCONF_RSRVD1) +#define BM_ENET_MAC1_IPACCRXCONF_RX_PROTERR_DISCARD 0x00000004 +#define BM_ENET_MAC1_IPACCRXCONF_RX_IPERR_DISCARD 0x00000002 +#define BM_ENET_MAC1_IPACCRXCONF_RX_IP_PAD_REMOVE 0x00000001 + +#define HW_ENET_MAC1_RMON_T_DROP (0x000041fc) + +#define BP_ENET_MAC1_RMON_T_DROP_RMON_T_DROP 0 +#define BM_ENET_MAC1_RMON_T_DROP_RMON_T_DROP 0xFFFFFFFF +#define BF_ENET_MAC1_RMON_T_DROP_RMON_T_DROP(v) (v) + +#define HW_ENET_MAC1_RMON_T_PACKETS (0x00004200) + +#define BP_ENET_MAC1_RMON_T_PACKETS_RMON_T_PACKETS 0 +#define BM_ENET_MAC1_RMON_T_PACKETS_RMON_T_PACKETS 0xFFFFFFFF +#define BF_ENET_MAC1_RMON_T_PACKETS_RMON_T_PACKETS(v) (v) + +#define HW_ENET_MAC1_RMON_T_BC_PKT (0x00004204) + +#define BP_ENET_MAC1_RMON_T_BC_PKT_RMON_T_BC_PKT 0 +#define BM_ENET_MAC1_RMON_T_BC_PKT_RMON_T_BC_PKT 0xFFFFFFFF +#define BF_ENET_MAC1_RMON_T_BC_PKT_RMON_T_BC_PKT(v) (v) + +#define HW_ENET_MAC1_RMON_T_MC_PKT (0x00004208) + +#define BP_ENET_MAC1_RMON_T_MC_PKT_RMON_T_MC_PKT 0 +#define BM_ENET_MAC1_RMON_T_MC_PKT_RMON_T_MC_PKT 0xFFFFFFFF +#define BF_ENET_MAC1_RMON_T_MC_PKT_RMON_T_MC_PKT(v) (v) + +#define HW_ENET_MAC1_RMON_T_CRC_ALIGN (0x0000420c) + +#define BP_ENET_MAC1_RMON_T_CRC_ALIGN_RMON_T_CRC_ALIGN 0 +#define BM_ENET_MAC1_RMON_T_CRC_ALIGN_RMON_T_CRC_ALIGN 0xFFFFFFFF +#define BF_ENET_MAC1_RMON_T_CRC_ALIGN_RMON_T_CRC_ALIGN(v) (v) + +#define HW_ENET_MAC1_RMON_T_UNDERSIZE (0x00004210) + +#define BP_ENET_MAC1_RMON_T_UNDERSIZE_RMON_T_UNDERSIZE 0 +#define BM_ENET_MAC1_RMON_T_UNDERSIZE_RMON_T_UNDERSIZE 0xFFFFFFFF +#define BF_ENET_MAC1_RMON_T_UNDERSIZE_RMON_T_UNDERSIZE(v) (v) + +#define HW_ENET_MAC1_RMON_T_OVERSIZE (0x00004214) + +#define BP_ENET_MAC1_RMON_T_OVERSIZE_RMON_T_OVERSIZE 0 +#define BM_ENET_MAC1_RMON_T_OVERSIZE_RMON_T_OVERSIZE 0xFFFFFFFF +#define BF_ENET_MAC1_RMON_T_OVERSIZE_RMON_T_OVERSIZE(v) (v) + +#define HW_ENET_MAC1_RMON_T_FRAG (0x00004218) + +#define BP_ENET_MAC1_RMON_T_FRAG_RMON_T_FRAG 0 +#define BM_ENET_MAC1_RMON_T_FRAG_RMON_T_FRAG 0xFFFFFFFF +#define BF_ENET_MAC1_RMON_T_FRAG_RMON_T_FRAG(v) (v) + +#define HW_ENET_MAC1_RMON_T_JAB (0x0000421c) + +#define BP_ENET_MAC1_RMON_T_JAB_RMON_T_JAB 0 +#define BM_ENET_MAC1_RMON_T_JAB_RMON_T_JAB 0xFFFFFFFF +#define BF_ENET_MAC1_RMON_T_JAB_RMON_T_JAB(v) (v) + +#define HW_ENET_MAC1_RMON_T_COL (0x00004220) + +#define BP_ENET_MAC1_RMON_T_COL_RMON_T_COL 0 +#define BM_ENET_MAC1_RMON_T_COL_RMON_T_COL 0xFFFFFFFF +#define BF_ENET_MAC1_RMON_T_COL_RMON_T_COL(v) (v) + +#define HW_ENET_MAC1_RMON_T_P64 (0x00004224) + +#define BP_ENET_MAC1_RMON_T_P64_RMON_T_P64 0 +#define BM_ENET_MAC1_RMON_T_P64_RMON_T_P64 0xFFFFFFFF +#define BF_ENET_MAC1_RMON_T_P64_RMON_T_P64(v) (v) + +#define HW_ENET_MAC1_RMON_T_P65TO127N (0x00004228) + +#define BP_ENET_MAC1_RMON_T_P65TO127N_RMON_T_P65TO127N 0 +#define BM_ENET_MAC1_RMON_T_P65TO127N_RMON_T_P65TO127N 0xFFFFFFFF +#define BF_ENET_MAC1_RMON_T_P65TO127N_RMON_T_P65TO127N(v) (v) + +#define HW_ENET_MAC1_RMON_T_P128TO255N (0x0000422c) + +#define BP_ENET_MAC1_RMON_T_P128TO255N_RMON_T_P128TO255N 0 +#define BM_ENET_MAC1_RMON_T_P128TO255N_RMON_T_P128TO255N 0xFFFFFFFF +#define BF_ENET_MAC1_RMON_T_P128TO255N_RMON_T_P128TO255N(v) (v) + +#define HW_ENET_MAC1_RMON_T_P256TO511 (0x00004230) + +#define BP_ENET_MAC1_RMON_T_P256TO511_RMON_T_P256TO511 0 +#define BM_ENET_MAC1_RMON_T_P256TO511_RMON_T_P256TO511 0xFFFFFFFF +#define BF_ENET_MAC1_RMON_T_P256TO511_RMON_T_P256TO511(v) (v) + +#define HW_ENET_MAC1_RMON_T_P512TO1023 (0x00004234) + +#define BP_ENET_MAC1_RMON_T_P512TO1023_RMON_T_P512TO1023 0 +#define BM_ENET_MAC1_RMON_T_P512TO1023_RMON_T_P512TO1023 0xFFFFFFFF +#define BF_ENET_MAC1_RMON_T_P512TO1023_RMON_T_P512TO1023(v) (v) + +#define HW_ENET_MAC1_RMON_T_P1024TO2047 (0x00004238) + +#define BP_ENET_MAC1_RMON_T_P1024TO2047_RMON_T_P1024TO2047 0 +#define BM_ENET_MAC1_RMON_T_P1024TO2047_RMON_T_P1024TO2047 0xFFFFFFFF +#define BF_ENET_MAC1_RMON_T_P1024TO2047_RMON_T_P1024TO2047(v) (v) + +#define HW_ENET_MAC1_RMON_T_P_GTE2048 (0x0000423c) + +#define BP_ENET_MAC1_RMON_T_P_GTE2048_RMON_T_P_GTE2048 0 +#define BM_ENET_MAC1_RMON_T_P_GTE2048_RMON_T_P_GTE2048 0xFFFFFFFF +#define BF_ENET_MAC1_RMON_T_P_GTE2048_RMON_T_P_GTE2048(v) (v) + +#define HW_ENET_MAC1_RMON_T_OCTETS (0x00004240) + +#define BP_ENET_MAC1_RMON_T_OCTETS_RMON_T_OCTETS 0 +#define BM_ENET_MAC1_RMON_T_OCTETS_RMON_T_OCTETS 0xFFFFFFFF +#define BF_ENET_MAC1_RMON_T_OCTETS_RMON_T_OCTETS(v) (v) + +#define HW_ENET_MAC1_IEEE_T_DROP (0x00004244) + +#define BP_ENET_MAC1_IEEE_T_DROP_IEEE_T_DROP 0 +#define BM_ENET_MAC1_IEEE_T_DROP_IEEE_T_DROP 0xFFFFFFFF +#define BF_ENET_MAC1_IEEE_T_DROP_IEEE_T_DROP(v) (v) + +#define HW_ENET_MAC1_IEEE_T_FRAME_OK (0x00004248) + +#define BP_ENET_MAC1_IEEE_T_FRAME_OK_IEEE_T_FRAME_OK 0 +#define BM_ENET_MAC1_IEEE_T_FRAME_OK_IEEE_T_FRAME_OK 0xFFFFFFFF +#define BF_ENET_MAC1_IEEE_T_FRAME_OK_IEEE_T_FRAME_OK(v) (v) + +#define HW_ENET_MAC1_IEEE_T_1COL (0x0000424c) + +#define BP_ENET_MAC1_IEEE_T_1COL_IEEE_T_1COL 0 +#define BM_ENET_MAC1_IEEE_T_1COL_IEEE_T_1COL 0xFFFFFFFF +#define BF_ENET_MAC1_IEEE_T_1COL_IEEE_T_1COL(v) (v) + +#define HW_ENET_MAC1_IEEE_T_MCOL (0x00004250) + +#define BP_ENET_MAC1_IEEE_T_MCOL_IEEE_T_MCOL 0 +#define BM_ENET_MAC1_IEEE_T_MCOL_IEEE_T_MCOL 0xFFFFFFFF +#define BF_ENET_MAC1_IEEE_T_MCOL_IEEE_T_MCOL(v) (v) + +#define HW_ENET_MAC1_IEEE_T_DEF (0x00004254) + +#define BP_ENET_MAC1_IEEE_T_DEF_IEEE_T_DEF 0 +#define BM_ENET_MAC1_IEEE_T_DEF_IEEE_T_DEF 0xFFFFFFFF +#define BF_ENET_MAC1_IEEE_T_DEF_IEEE_T_DEF(v) (v) + +#define HW_ENET_MAC1_IEEE_T_LCOL (0x00004258) + +#define BP_ENET_MAC1_IEEE_T_LCOL_IEEE_T_LCOL 0 +#define BM_ENET_MAC1_IEEE_T_LCOL_IEEE_T_LCOL 0xFFFFFFFF +#define BF_ENET_MAC1_IEEE_T_LCOL_IEEE_T_LCOL(v) (v) + +#define HW_ENET_MAC1_IEEE_T_EXCOL (0x0000425c) + +#define BP_ENET_MAC1_IEEE_T_EXCOL_IEEE_T_EXCOL 0 +#define BM_ENET_MAC1_IEEE_T_EXCOL_IEEE_T_EXCOL 0xFFFFFFFF +#define BF_ENET_MAC1_IEEE_T_EXCOL_IEEE_T_EXCOL(v) (v) + +#define HW_ENET_MAC1_IEEE_T_MACERR (0x00004260) + +#define BP_ENET_MAC1_IEEE_T_MACERR_IEEE_T_MACERR 0 +#define BM_ENET_MAC1_IEEE_T_MACERR_IEEE_T_MACERR 0xFFFFFFFF +#define BF_ENET_MAC1_IEEE_T_MACERR_IEEE_T_MACERR(v) (v) + +#define HW_ENET_MAC1_IEEE_T_CSERR (0x00004264) + +#define BP_ENET_MAC1_IEEE_T_CSERR_IEEE_T_CSERR 0 +#define BM_ENET_MAC1_IEEE_T_CSERR_IEEE_T_CSERR 0xFFFFFFFF +#define BF_ENET_MAC1_IEEE_T_CSERR_IEEE_T_CSERR(v) (v) + +#define HW_ENET_MAC1_IEEE_T_SQE (0x00004268) + +#define BP_ENET_MAC1_IEEE_T_SQE_IEEE_T_SQE 0 +#define BM_ENET_MAC1_IEEE_T_SQE_IEEE_T_SQE 0xFFFFFFFF +#define BF_ENET_MAC1_IEEE_T_SQE_IEEE_T_SQE(v) (v) + +#define HW_ENET_MAC1_IEEE_T_FDXFC (0x0000426c) + +#define BP_ENET_MAC1_IEEE_T_FDXFC_IEEE_T_FDXFC 0 +#define BM_ENET_MAC1_IEEE_T_FDXFC_IEEE_T_FDXFC 0xFFFFFFFF +#define BF_ENET_MAC1_IEEE_T_FDXFC_IEEE_T_FDXFC(v) (v) + +#define HW_ENET_MAC1_IEEE_T_OCTETS_OK (0x00004270) + +#define BP_ENET_MAC1_IEEE_T_OCTETS_OK_IEEE_T_OCTETS_OK 0 +#define BM_ENET_MAC1_IEEE_T_OCTETS_OK_IEEE_T_OCTETS_OK 0xFFFFFFFF +#define BF_ENET_MAC1_IEEE_T_OCTETS_OK_IEEE_T_OCTETS_OK(v) (v) + +#define HW_ENET_MAC1_RMON_R_PACKETS (0x00004280) + +#define BP_ENET_MAC1_RMON_R_PACKETS_RMON_R_PACKETS 0 +#define BM_ENET_MAC1_RMON_R_PACKETS_RMON_R_PACKETS 0xFFFFFFFF +#define BF_ENET_MAC1_RMON_R_PACKETS_RMON_R_PACKETS(v) (v) + +#define HW_ENET_MAC1_RMON_R_BC_PKT (0x00004284) + +#define BP_ENET_MAC1_RMON_R_BC_PKT_RMON_R_BC_PKT 0 +#define BM_ENET_MAC1_RMON_R_BC_PKT_RMON_R_BC_PKT 0xFFFFFFFF +#define BF_ENET_MAC1_RMON_R_BC_PKT_RMON_R_BC_PKT(v) (v) + +#define HW_ENET_MAC1_RMON_R_MC_PKT (0x00004288) + +#define BP_ENET_MAC1_RMON_R_MC_PKT_RMON_R_MC_PKT 0 +#define BM_ENET_MAC1_RMON_R_MC_PKT_RMON_R_MC_PKT 0xFFFFFFFF +#define BF_ENET_MAC1_RMON_R_MC_PKT_RMON_R_MC_PKT(v) (v) + +#define HW_ENET_MAC1_RMON_R_CRC_ALIGN (0x0000428c) + +#define BP_ENET_MAC1_RMON_R_CRC_ALIGN_RMON_R_CRC_ALIGN 0 +#define BM_ENET_MAC1_RMON_R_CRC_ALIGN_RMON_R_CRC_ALIGN 0xFFFFFFFF +#define BF_ENET_MAC1_RMON_R_CRC_ALIGN_RMON_R_CRC_ALIGN(v) (v) + +#define HW_ENET_MAC1_RMON_R_UNDERSIZE (0x00004290) + +#define BP_ENET_MAC1_RMON_R_UNDERSIZE_RMON_R_UNDERSIZE 0 +#define BM_ENET_MAC1_RMON_R_UNDERSIZE_RMON_R_UNDERSIZE 0xFFFFFFFF +#define BF_ENET_MAC1_RMON_R_UNDERSIZE_RMON_R_UNDERSIZE(v) (v) + +#define HW_ENET_MAC1_RMON_R_OVERSIZE (0x00004294) + +#define BP_ENET_MAC1_RMON_R_OVERSIZE_RMON_R_OVERSIZE 0 +#define BM_ENET_MAC1_RMON_R_OVERSIZE_RMON_R_OVERSIZE 0xFFFFFFFF +#define BF_ENET_MAC1_RMON_R_OVERSIZE_RMON_R_OVERSIZE(v) (v) + +#define HW_ENET_MAC1_RMON_R_FRAG (0x00004298) + +#define BP_ENET_MAC1_RMON_R_FRAG_RMON_R_FRAG 0 +#define BM_ENET_MAC1_RMON_R_FRAG_RMON_R_FRAG 0xFFFFFFFF +#define BF_ENET_MAC1_RMON_R_FRAG_RMON_R_FRAG(v) (v) + +#define HW_ENET_MAC1_RMON_R_JAB (0x0000429c) + +#define BP_ENET_MAC1_RMON_R_JAB_RMON_R_JAB 0 +#define BM_ENET_MAC1_RMON_R_JAB_RMON_R_JAB 0xFFFFFFFF +#define BF_ENET_MAC1_RMON_R_JAB_RMON_R_JAB(v) (v) + +#define HW_ENET_MAC1_RMON_R_P64 (0x000042a4) + +#define BP_ENET_MAC1_RMON_R_P64_RMON_R_P64 0 +#define BM_ENET_MAC1_RMON_R_P64_RMON_R_P64 0xFFFFFFFF +#define BF_ENET_MAC1_RMON_R_P64_RMON_R_P64(v) (v) + +#define HW_ENET_MAC1_RMON_R_P65TO127 (0x000042a8) + +#define BP_ENET_MAC1_RMON_R_P65TO127_RMON_R_P65TO127 0 +#define BM_ENET_MAC1_RMON_R_P65TO127_RMON_R_P65TO127 0xFFFFFFFF +#define BF_ENET_MAC1_RMON_R_P65TO127_RMON_R_P65TO127(v) (v) + +#define HW_ENET_MAC1_RMON_R_P128TO255 (0x000042ac) + +#define BP_ENET_MAC1_RMON_R_P128TO255_RMON_R_P128TO255 0 +#define BM_ENET_MAC1_RMON_R_P128TO255_RMON_R_P128TO255 0xFFFFFFFF +#define BF_ENET_MAC1_RMON_R_P128TO255_RMON_R_P128TO255(v) (v) + +#define HW_ENET_MAC1_RMON_R_P256TO511 (0x000042b0) + +#define BP_ENET_MAC1_RMON_R_P256TO511_RMON_R_P256TO511 0 +#define BM_ENET_MAC1_RMON_R_P256TO511_RMON_R_P256TO511 0xFFFFFFFF +#define BF_ENET_MAC1_RMON_R_P256TO511_RMON_R_P256TO511(v) (v) + +#define HW_ENET_MAC1_RMON_R_P512TO1023 (0x000042b4) + +#define BP_ENET_MAC1_RMON_R_P512TO1023_RMON_R_P512TO1023 0 +#define BM_ENET_MAC1_RMON_R_P512TO1023_RMON_R_P512TO1023 0xFFFFFFFF +#define BF_ENET_MAC1_RMON_R_P512TO1023_RMON_R_P512TO1023(v) (v) + +#define HW_ENET_MAC1_RMON_R_P1024TO2047 (0x000042b8) + +#define BP_ENET_MAC1_RMON_R_P1024TO2047_RMON_R_P1024TO2047 0 +#define BM_ENET_MAC1_RMON_R_P1024TO2047_RMON_R_P1024TO2047 0xFFFFFFFF +#define BF_ENET_MAC1_RMON_R_P1024TO2047_RMON_R_P1024TO2047(v) (v) + +#define HW_ENET_MAC1_RMON_R_P_GTE2048 (0x000042bc) + +#define BP_ENET_MAC1_RMON_R_P_GTE2048_RMON_R_P_GTE2048 0 +#define BM_ENET_MAC1_RMON_R_P_GTE2048_RMON_R_P_GTE2048 0xFFFFFFFF +#define BF_ENET_MAC1_RMON_R_P_GTE2048_RMON_R_P_GTE2048(v) (v) + +#define HW_ENET_MAC1_RMON_R_OCTETS (0x000042c0) + +#define BP_ENET_MAC1_RMON_R_OCTETS_RMON_R_OCTETS 0 +#define BM_ENET_MAC1_RMON_R_OCTETS_RMON_R_OCTETS 0xFFFFFFFF +#define BF_ENET_MAC1_RMON_R_OCTETS_RMON_R_OCTETS(v) (v) + +#define HW_ENET_MAC1_IEEE_R_DROP (0x000042c4) + +#define BP_ENET_MAC1_IEEE_R_DROP_IEEE_R_DROP 0 +#define BM_ENET_MAC1_IEEE_R_DROP_IEEE_R_DROP 0xFFFFFFFF +#define BF_ENET_MAC1_IEEE_R_DROP_IEEE_R_DROP(v) (v) + +#define HW_ENET_MAC1_IEEE_R_FRAME_OK (0x000042c8) + +#define BP_ENET_MAC1_IEEE_R_FRAME_OK_IEEE_R_FRAME_OK 0 +#define BM_ENET_MAC1_IEEE_R_FRAME_OK_IEEE_R_FRAME_OK 0xFFFFFFFF +#define BF_ENET_MAC1_IEEE_R_FRAME_OK_IEEE_R_FRAME_OK(v) (v) + +#define HW_ENET_MAC1_IEEE_R_CRC (0x000042cc) + +#define BP_ENET_MAC1_IEEE_R_CRC_IEEE_R_CRC 0 +#define BM_ENET_MAC1_IEEE_R_CRC_IEEE_R_CRC 0xFFFFFFFF +#define BF_ENET_MAC1_IEEE_R_CRC_IEEE_R_CRC(v) (v) + +#define HW_ENET_MAC1_IEEE_R_ALIGN (0x000042d0) + +#define BP_ENET_MAC1_IEEE_R_ALIGN_IEEE_R_ALIGN 0 +#define BM_ENET_MAC1_IEEE_R_ALIGN_IEEE_R_ALIGN 0xFFFFFFFF +#define BF_ENET_MAC1_IEEE_R_ALIGN_IEEE_R_ALIGN(v) (v) + +#define HW_ENET_MAC1_IEEE_R_MACERR (0x000042d4) + +#define BP_ENET_MAC1_IEEE_R_MACERR_IEEE_R_MACERR 0 +#define BM_ENET_MAC1_IEEE_R_MACERR_IEEE_R_MACERR 0xFFFFFFFF +#define BF_ENET_MAC1_IEEE_R_MACERR_IEEE_R_MACERR(v) (v) + +#define HW_ENET_MAC1_IEEE_R_FDXFC (0x000042d8) + +#define BP_ENET_MAC1_IEEE_R_FDXFC_IEEE_R_FDXFC 0 +#define BM_ENET_MAC1_IEEE_R_FDXFC_IEEE_R_FDXFC 0xFFFFFFFF +#define BF_ENET_MAC1_IEEE_R_FDXFC_IEEE_R_FDXFC(v) (v) + +#define HW_ENET_MAC1_IEEE_R_OCTETS_OK (0x000042dc) + +#define BP_ENET_MAC1_IEEE_R_OCTETS_OK_IEEE_R_OCTETS_OK 0 +#define BM_ENET_MAC1_IEEE_R_OCTETS_OK_IEEE_R_OCTETS_OK 0xFFFFFFFF +#define BF_ENET_MAC1_IEEE_R_OCTETS_OK_IEEE_R_OCTETS_OK(v) (v) + +#define HW_ENET_MAC1_ATIME_CTRL (0x000043fc) + +#define BP_ENET_MAC1_ATIME_CTRL_RSRVD0 14 +#define BM_ENET_MAC1_ATIME_CTRL_RSRVD0 0xFFFFC000 +#define BF_ENET_MAC1_ATIME_CTRL_RSRVD0(v) \ + (((v) << 14) & BM_ENET_MAC1_ATIME_CTRL_RSRVD0) +#define BM_ENET_MAC1_ATIME_CTRL_FRC_SLAVE 0x00002000 +#define BM_ENET_MAC1_ATIME_CTRL_RSRVD1 0x00001000 +#define BM_ENET_MAC1_ATIME_CTRL_CAPTURE 0x00000800 +#define BM_ENET_MAC1_ATIME_CTRL_RSRVD2 0x00000400 +#define BM_ENET_MAC1_ATIME_CTRL_RESTART 0x00000200 +#define BM_ENET_MAC1_ATIME_CTRL_RSRVD3 0x00000100 +#define BM_ENET_MAC1_ATIME_CTRL_PIN_PERIOD_ENA 0x00000080 +#define BM_ENET_MAC1_ATIME_CTRL_RSRVD4 0x00000040 +#define BM_ENET_MAC1_ATIME_CTRL_EVT_PERIOD_RST 0x00000020 +#define BM_ENET_MAC1_ATIME_CTRL_EVT_PERIOD_ENA 0x00000010 +#define BM_ENET_MAC1_ATIME_CTRL_EVT_OFFSET_RST 0x00000008 +#define BM_ENET_MAC1_ATIME_CTRL_EVT_OFFSET_ENA 0x00000004 +#define BM_ENET_MAC1_ATIME_CTRL_ONE_SHOT 0x00000002 +#define BM_ENET_MAC1_ATIME_CTRL_ENABLE 0x00000001 + +#define HW_ENET_MAC1_ATIME (0x00004400) + +#define BP_ENET_MAC1_ATIME_ATIME 0 +#define BM_ENET_MAC1_ATIME_ATIME 0xFFFFFFFF +#define BF_ENET_MAC1_ATIME_ATIME(v) (v) + +#define HW_ENET_MAC1_ATIME_EVT_OFFSET (0x00004404) + +#define BP_ENET_MAC1_ATIME_EVT_OFFSET_ATIME_EVT_OFFSET 0 +#define BM_ENET_MAC1_ATIME_EVT_OFFSET_ATIME_EVT_OFFSET 0xFFFFFFFF +#define BF_ENET_MAC1_ATIME_EVT_OFFSET_ATIME_EVT_OFFSET(v) (v) + +#define HW_ENET_MAC1_ATIME_EVT_PERIOD (0x00004408) + +#define BP_ENET_MAC1_ATIME_EVT_PERIOD_ATIME_EVT_PERIOD 0 +#define BM_ENET_MAC1_ATIME_EVT_PERIOD_ATIME_EVT_PERIOD 0xFFFFFFFF +#define BF_ENET_MAC1_ATIME_EVT_PERIOD_ATIME_EVT_PERIOD(v) (v) + +#define HW_ENET_MAC1_ATIME_CORR (0x0000440c) + +#define BM_ENET_MAC1_ATIME_CORR_RSRVD0 0x80000000 +#define BP_ENET_MAC1_ATIME_CORR_ATIME_CORR 0 +#define BM_ENET_MAC1_ATIME_CORR_ATIME_CORR 0x7FFFFFFF +#define BF_ENET_MAC1_ATIME_CORR_ATIME_CORR(v) \ + (((v) << 0) & BM_ENET_MAC1_ATIME_CORR_ATIME_CORR) + +#define HW_ENET_MAC1_ATIME_INC (0x00004410) + +#define BP_ENET_MAC1_ATIME_INC_RSRVD0 15 +#define BM_ENET_MAC1_ATIME_INC_RSRVD0 0xFFFF8000 +#define BF_ENET_MAC1_ATIME_INC_RSRVD0(v) \ + (((v) << 15) & BM_ENET_MAC1_ATIME_INC_RSRVD0) +#define BP_ENET_MAC1_ATIME_INC_ATIME_INC_CORR 8 +#define BM_ENET_MAC1_ATIME_INC_ATIME_INC_CORR 0x00007F00 +#define BF_ENET_MAC1_ATIME_INC_ATIME_INC_CORR(v) \ + (((v) << 8) & BM_ENET_MAC1_ATIME_INC_ATIME_INC_CORR) +#define BM_ENET_MAC1_ATIME_INC_RSRVD1 0x00000080 +#define BP_ENET_MAC1_ATIME_INC_ATIME_INC 0 +#define BM_ENET_MAC1_ATIME_INC_ATIME_INC 0x0000007F +#define BF_ENET_MAC1_ATIME_INC_ATIME_INC(v) \ + (((v) << 0) & BM_ENET_MAC1_ATIME_INC_ATIME_INC) + +#define HW_ENET_MAC1_TS_TIMESTAMP (0x00004414) + +#define BP_ENET_MAC1_TS_TIMESTAMP_TS_TIMESTAMP 0 +#define BM_ENET_MAC1_TS_TIMESTAMP_TS_TIMESTAMP 0xFFFFFFFF +#define BF_ENET_MAC1_TS_TIMESTAMP_TS_TIMESTAMP(v) (v) + +#define HW_ENET_MAC1_SMAC_0_0 (0x000044fc) + +#define BP_ENET_MAC1_SMAC_0_0_SMAC_0_0 0 +#define BM_ENET_MAC1_SMAC_0_0_SMAC_0_0 0xFFFFFFFF +#define BF_ENET_MAC1_SMAC_0_0_SMAC_0_0(v) (v) + +#define HW_ENET_MAC1_SMAC_0_1 (0x00004500) + +#define BP_ENET_MAC1_SMAC_0_1_SMAC_0_1 0 +#define BM_ENET_MAC1_SMAC_0_1_SMAC_0_1 0xFFFFFFFF +#define BF_ENET_MAC1_SMAC_0_1_SMAC_0_1(v) (v) + +#define HW_ENET_MAC1_SMAC_1_0 (0x00004504) + +#define BP_ENET_MAC1_SMAC_1_0_SMAC_1_0 0 +#define BM_ENET_MAC1_SMAC_1_0_SMAC_1_0 0xFFFFFFFF +#define BF_ENET_MAC1_SMAC_1_0_SMAC_1_0(v) (v) + +#define HW_ENET_MAC1_SMAC_1_1 (0x00004508) + +#define BP_ENET_MAC1_SMAC_1_1_SMAC_1_1 0 +#define BM_ENET_MAC1_SMAC_1_1_SMAC_1_1 0xFFFFFFFF +#define BF_ENET_MAC1_SMAC_1_1_SMAC_1_1(v) (v) + +#define HW_ENET_MAC1_SMAC_2_0 (0x0000450c) + +#define BP_ENET_MAC1_SMAC_2_0_SMAC_2_0 0 +#define BM_ENET_MAC1_SMAC_2_0_SMAC_2_0 0xFFFFFFFF +#define BF_ENET_MAC1_SMAC_2_0_SMAC_2_0(v) (v) + +#define HW_ENET_MAC1_SMAC_2_1 (0x00004510) + +#define BP_ENET_MAC1_SMAC_2_1_SMAC_2_1 0 +#define BM_ENET_MAC1_SMAC_2_1_SMAC_2_1 0xFFFFFFFF +#define BF_ENET_MAC1_SMAC_2_1_SMAC_2_1(v) (v) + +#define HW_ENET_MAC1_SMAC_3_0 (0x00004514) + +#define BP_ENET_MAC1_SMAC_3_0_SMAC_3_0 0 +#define BM_ENET_MAC1_SMAC_3_0_SMAC_3_0 0xFFFFFFFF +#define BF_ENET_MAC1_SMAC_3_0_SMAC_3_0(v) (v) + +#define HW_ENET_MAC1_SMAC_3_1 (0x00004518) + +#define BP_ENET_MAC1_SMAC_3_1_SMAC_3_1 0 +#define BM_ENET_MAC1_SMAC_3_1_SMAC_3_1 0xFFFFFFFF +#define BF_ENET_MAC1_SMAC_3_1_SMAC_3_1(v) (v) + +#define HW_ENET_MAC1_COMP_REG_0 (0x000045fc) + +#define BP_ENET_MAC1_COMP_REG_0_COMP_REG_0 0 +#define BM_ENET_MAC1_COMP_REG_0_COMP_REG_0 0xFFFFFFFF +#define BF_ENET_MAC1_COMP_REG_0_COMP_REG_0(v) (v) + +#define HW_ENET_MAC1_COMP_REG_1 (0x00004600) + +#define BP_ENET_MAC1_COMP_REG_1_COMP_REG_1 0 +#define BM_ENET_MAC1_COMP_REG_1_COMP_REG_1 0xFFFFFFFF +#define BF_ENET_MAC1_COMP_REG_1_COMP_REG_1(v) (v) + +#define HW_ENET_MAC1_COMP_REG_2 (0x00004604) + +#define BP_ENET_MAC1_COMP_REG_2_COMP_REG_2 0 +#define BM_ENET_MAC1_COMP_REG_2_COMP_REG_2 0xFFFFFFFF +#define BF_ENET_MAC1_COMP_REG_2_COMP_REG_2(v) (v) + +#define HW_ENET_MAC1_COMP_REG_3 (0x00004608) + +#define BP_ENET_MAC1_COMP_REG_3_COMP_REG_3 0 +#define BM_ENET_MAC1_COMP_REG_3_COMP_REG_3 0xFFFFFFFF +#define BF_ENET_MAC1_COMP_REG_3_COMP_REG_3(v) (v) + +#define HW_ENET_MAC1_CAPT_REG_0 (0x0000463c) + +#define BP_ENET_MAC1_CAPT_REG_0_CAPT_REG_0 0 +#define BM_ENET_MAC1_CAPT_REG_0_CAPT_REG_0 0xFFFFFFFF +#define BF_ENET_MAC1_CAPT_REG_0_CAPT_REG_0(v) (v) + +#define HW_ENET_MAC1_CAPT_REG_1 (0x00004640) + +#define BP_ENET_MAC1_CAPT_REG_1_CAPT_REG_1 0 +#define BM_ENET_MAC1_CAPT_REG_1_CAPT_REG_1 0xFFFFFFFF +#define BF_ENET_MAC1_CAPT_REG_1_CAPT_REG_1(v) (v) + +#define HW_ENET_MAC1_CAPT_REG_2 (0x00004644) + +#define BP_ENET_MAC1_CAPT_REG_2_CAPT_REG_2 0 +#define BM_ENET_MAC1_CAPT_REG_2_CAPT_REG_2 0xFFFFFFFF +#define BF_ENET_MAC1_CAPT_REG_2_CAPT_REG_2(v) (v) + +#define HW_ENET_MAC1_CAPT_REG_3 (0x00004648) + +#define BP_ENET_MAC1_CAPT_REG_3_CAPT_REG_3 0 +#define BM_ENET_MAC1_CAPT_REG_3_CAPT_REG_3 0xFFFFFFFF +#define BF_ENET_MAC1_CAPT_REG_3_CAPT_REG_3(v) (v) + +#define HW_ENET_MAC1_CCB_INT (0x0000467c) + +#define BP_ENET_MAC1_CCB_INT_RSRVD0 20 +#define BM_ENET_MAC1_CCB_INT_RSRVD0 0xFFF00000 +#define BF_ENET_MAC1_CCB_INT_RSRVD0(v) \ + (((v) << 20) & BM_ENET_MAC1_CCB_INT_RSRVD0) +#define BM_ENET_MAC1_CCB_INT_COMPARE3 0x00080000 +#define BM_ENET_MAC1_CCB_INT_COMPARE2 0x00040000 +#define BM_ENET_MAC1_CCB_INT_COMPARE1 0x00020000 +#define BM_ENET_MAC1_CCB_INT_COMPARE0 0x00010000 +#define BP_ENET_MAC1_CCB_INT_RSRVD1 4 +#define BM_ENET_MAC1_CCB_INT_RSRVD1 0x0000FFF0 +#define BF_ENET_MAC1_CCB_INT_RSRVD1(v) \ + (((v) << 4) & BM_ENET_MAC1_CCB_INT_RSRVD1) +#define BM_ENET_MAC1_CCB_INT_CAPTURE3 0x00000008 +#define BM_ENET_MAC1_CCB_INT_CAPTURE2 0x00000004 +#define BM_ENET_MAC1_CCB_INT_CAPTURE1 0x00000002 +#define BM_ENET_MAC1_CCB_INT_CAPTURE0 0x00000001 + +#define HW_ENET_MAC1_CCB_INT_MASK (0x00004680) + +#define BP_ENET_MAC1_CCB_INT_MASK_RSRVD0 20 +#define BM_ENET_MAC1_CCB_INT_MASK_RSRVD0 0xFFF00000 +#define BF_ENET_MAC1_CCB_INT_MASK_RSRVD0(v) \ + (((v) << 20) & BM_ENET_MAC1_CCB_INT_MASK_RSRVD0) +#define BM_ENET_MAC1_CCB_INT_MASK_COMPARE3 0x00080000 +#define BM_ENET_MAC1_CCB_INT_MASK_COMPARE2 0x00040000 +#define BM_ENET_MAC1_CCB_INT_MASK_COMPARE1 0x00020000 +#define BM_ENET_MAC1_CCB_INT_MASK_COMPARE0 0x00010000 +#define BP_ENET_MAC1_CCB_INT_MASK_RSRVD1 4 +#define BM_ENET_MAC1_CCB_INT_MASK_RSRVD1 0x0000FFF0 +#define BF_ENET_MAC1_CCB_INT_MASK_RSRVD1(v) \ + (((v) << 4) & BM_ENET_MAC1_CCB_INT_MASK_RSRVD1) +#define BM_ENET_MAC1_CCB_INT_MASK_CAPTURE3 0x00000008 +#define BM_ENET_MAC1_CCB_INT_MASK_CAPTURE2 0x00000004 +#define BM_ENET_MAC1_CCB_INT_MASK_CAPTURE1 0x00000002 +#define BM_ENET_MAC1_CCB_INT_MASK_CAPTURE0 0x00000001 + +#define HW_ENET_SWI_REVISION (0x00007ffc) + +#define BP_ENET_SWI_REVISION_CUSTOMER_REVISION 16 +#define BM_ENET_SWI_REVISION_CUSTOMER_REVISION 0xFFFF0000 +#define BF_ENET_SWI_REVISION_CUSTOMER_REVISION(v) \ + (((v) << 16) & BM_ENET_SWI_REVISION_CUSTOMER_REVISION) +#define BP_ENET_SWI_REVISION_CORE_REVISION 0 +#define BM_ENET_SWI_REVISION_CORE_REVISION 0x0000FFFF +#define BF_ENET_SWI_REVISION_CORE_REVISION(v) \ + (((v) << 0) & BM_ENET_SWI_REVISION_CORE_REVISION) + +#define HW_ENET_SWI_SCRATCH (0x00008000) + +#define BP_ENET_SWI_SCRATCH_COMPARE0 0 +#define BM_ENET_SWI_SCRATCH_COMPARE0 0xFFFFFFFF +#define BF_ENET_SWI_SCRATCH_COMPARE0(v) (v) + +#define HW_ENET_SWI_PORT_ENA (0x00008004) + +#define BP_ENET_SWI_PORT_ENA_RSRVD1 19 +#define BM_ENET_SWI_PORT_ENA_RSRVD1 0xFFF80000 +#define BF_ENET_SWI_PORT_ENA_RSRVD1(v) \ + (((v) << 19) & BM_ENET_SWI_PORT_ENA_RSRVD1) +#define BM_ENET_SWI_PORT_ENA_ENA_RECEIVE_2 0x00040000 +#define BM_ENET_SWI_PORT_ENA_ENA_RECEIVE_1 0x00020000 +#define BM_ENET_SWI_PORT_ENA_ENA_RECEIVE_0 0x00010000 +#define BP_ENET_SWI_PORT_ENA_RSRVD0 3 +#define BM_ENET_SWI_PORT_ENA_RSRVD0 0x0000FFF8 +#define BF_ENET_SWI_PORT_ENA_RSRVD0(v) \ + (((v) << 3) & BM_ENET_SWI_PORT_ENA_RSRVD0) +#define BM_ENET_SWI_PORT_ENA_ENA_TRANSMIT_2 0x00000004 +#define BM_ENET_SWI_PORT_ENA_ENA_TRANSMIT_1 0x00000002 +#define BM_ENET_SWI_PORT_ENA_ENA_TRANSMIT_0 0x00000001 + +#define HW_ENET_SWI_VLAN_VERIFY (0x0000800c) + +#define BP_ENET_SWI_VLAN_VERIFY_RSRVD1 19 +#define BM_ENET_SWI_VLAN_VERIFY_RSRVD1 0xFFF80000 +#define BF_ENET_SWI_VLAN_VERIFY_RSRVD1(v) \ + (((v) << 19) & BM_ENET_SWI_VLAN_VERIFY_RSRVD1) +#define BM_ENET_SWI_VLAN_VERIFY_DISCARD_P2 0x00040000 +#define BM_ENET_SWI_VLAN_VERIFY_DISCARD_P1 0x00020000 +#define BM_ENET_SWI_VLAN_VERIFY_DISCARD_P0 0x00010000 +#define BP_ENET_SWI_VLAN_VERIFY_RSRVD0 3 +#define BM_ENET_SWI_VLAN_VERIFY_RSRVD0 0x0000FFF8 +#define BF_ENET_SWI_VLAN_VERIFY_RSRVD0(v) \ + (((v) << 3) & BM_ENET_SWI_VLAN_VERIFY_RSRVD0) +#define BM_ENET_SWI_VLAN_VERIFY_VLAN_VERIFY_2 0x00000004 +#define BM_ENET_SWI_VLAN_VERIFY_VLAN_VERIFY_1 0x00000002 +#define BM_ENET_SWI_VLAN_VERIFY_VLAN_VERIFY_0 0x00000001 + +#define HW_ENET_SWI_BCAST_DEFAULT_MASK (0x00008010) + +#define BP_ENET_SWI_BCAST_DEFAULT_MASK_RSRVD0 3 +#define BM_ENET_SWI_BCAST_DEFAULT_MASK_RSRVD0 0xFFFFFFF8 +#define BF_ENET_SWI_BCAST_DEFAULT_MASK_RSRVD0(v) \ + (((v) << 3) & BM_ENET_SWI_BCAST_DEFAULT_MASK_RSRVD0) +#define BM_ENET_SWI_BCAST_DEFAULT_MASK_BCAST_DEFAULT_MASK_2 0x00000004 +#define BM_ENET_SWI_BCAST_DEFAULT_MASK_BCAST_DEFAULT_MASK_1 0x00000002 +#define BM_ENET_SWI_BCAST_DEFAULT_MASK_BCAST_DEFAULT_MASK_0 0x00000001 + +#define HW_ENET_SWI_MCAST_DEFAULT_MASK (0x00008014) + +#define BP_ENET_SWI_MCAST_DEFAULT_MASK_RSRVD0 3 +#define BM_ENET_SWI_MCAST_DEFAULT_MASK_RSRVD0 0xFFFFFFF8 +#define BF_ENET_SWI_MCAST_DEFAULT_MASK_RSRVD0(v) \ + (((v) << 3) & BM_ENET_SWI_MCAST_DEFAULT_MASK_RSRVD0) +#define BM_ENET_SWI_MCAST_DEFAULT_MASK_MCAST_DEFAULT_MASK_2 0x00000004 +#define BM_ENET_SWI_MCAST_DEFAULT_MASK_MCAST_DEFAULT_MASK_1 0x00000002 +#define BM_ENET_SWI_MCAST_DEFAULT_MASK_MCAST_DEFAULT_MASK_0 0x00000001 + +#define HW_ENET_SWI_INPUT_LEARN_BLOCK (0x00008018) + +#define BP_ENET_SWI_INPUT_LEARN_BLOCK_RSRVD1 19 +#define BM_ENET_SWI_INPUT_LEARN_BLOCK_RSRVD1 0xFFF80000 +#define BF_ENET_SWI_INPUT_LEARN_BLOCK_RSRVD1(v) \ + (((v) << 19) & BM_ENET_SWI_INPUT_LEARN_BLOCK_RSRVD1) +#define BM_ENET_SWI_INPUT_LEARN_BLOCK_LEARNING_DIS_P2 0x00040000 +#define BM_ENET_SWI_INPUT_LEARN_BLOCK_LEARNING_DI_P1 0x00020000 +#define BM_ENET_SWI_INPUT_LEARN_BLOCK_LEARNING_DI_P0 0x00010000 +#define BP_ENET_SWI_INPUT_LEARN_BLOCK_RSRVD0 3 +#define BM_ENET_SWI_INPUT_LEARN_BLOCK_RSRVD0 0x0000FFF8 +#define BF_ENET_SWI_INPUT_LEARN_BLOCK_RSRVD0(v) \ + (((v) << 3) & BM_ENET_SWI_INPUT_LEARN_BLOCK_RSRVD0) +#define BM_ENET_SWI_INPUT_LEARN_BLOCK_BLOCKING_ENA_P2 0x00000004 +#define BM_ENET_SWI_INPUT_LEARN_BLOCK_BLOCKING_ENA_P1 0x00000002 +#define BM_ENET_SWI_INPUT_LEARN_BLOCK_BLOCKING_ENA_P0 0x00000001 + +#define HW_ENET_SWI_MGMT_CONFIG (0x0000801c) + +#define BP_ENET_SWI_MGMT_CONFIG_RSRVD2 19 +#define BM_ENET_SWI_MGMT_CONFIG_RSRVD2 0xFFF80000 +#define BF_ENET_SWI_MGMT_CONFIG_RSRVD2(v) \ + (((v) << 19) & BM_ENET_SWI_MGMT_CONFIG_RSRVD2) +#define BP_ENET_SWI_MGMT_CONFIG_PORTMASK 16 +#define BM_ENET_SWI_MGMT_CONFIG_PORTMASK 0x00070000 +#define BF_ENET_SWI_MGMT_CONFIG_PORTMASK(v) \ + (((v) << 16) & BM_ENET_SWI_MGMT_CONFIG_PORTMASK) +#define BP_ENET_SWI_MGMT_CONFIG_PRIORITY 13 +#define BM_ENET_SWI_MGMT_CONFIG_PRIORITY 0x0000E000 +#define BF_ENET_SWI_MGMT_CONFIG_PRIORITY(v) \ + (((v) << 13) & BM_ENET_SWI_MGMT_CONFIG_PRIORITY) +#define BP_ENET_SWI_MGMT_CONFIG_RSRVD1 8 +#define BM_ENET_SWI_MGMT_CONFIG_RSRVD1 0x00001F00 +#define BF_ENET_SWI_MGMT_CONFIG_RSRVD1(v) \ + (((v) << 8) & BM_ENET_SWI_MGMT_CONFIG_RSRVD1) +#define BM_ENET_SWI_MGMT_CONFIG_DISCARD 0x00000080 +#define BM_ENET_SWI_MGMT_CONFIG_ENABLE 0x00000040 +#define BM_ENET_SWI_MGMT_CONFIG_MESSAGE_TRANSMITTED 0x00000020 +#define BM_ENET_SWI_MGMT_CONFIG_RSRVD0 0x00000010 +#define BP_ENET_SWI_MGMT_CONFIG_PORT 0 +#define BM_ENET_SWI_MGMT_CONFIG_PORT 0x0000000F +#define BF_ENET_SWI_MGMT_CONFIG_PORT(v) \ + (((v) << 0) & BM_ENET_SWI_MGMT_CONFIG_PORT) + +#define HW_ENET_SWI_MODE_CONFIG (0x00008020) + +#define BM_ENET_SWI_MODE_CONFIG_STATSRESET 0x80000000 +#define BP_ENET_SWI_MODE_CONFIG_RSRVD1 10 +#define BM_ENET_SWI_MODE_CONFIG_RSRVD1 0x7FFFFC00 +#define BF_ENET_SWI_MODE_CONFIG_RSRVD1(v) \ + (((v) << 10) & BM_ENET_SWI_MODE_CONFIG_RSRVD1) +#define BM_ENET_SWI_MODE_CONFIG_P0BUF_CUT_THROUGH 0x00000200 +#define BM_ENET_SWI_MODE_CONFIG_CRC_TRANSPARENT 0x00000100 +#define BM_ENET_SWI_MODE_CONFIG_STOP_EN 0x00000080 +#define BP_ENET_SWI_MODE_CONFIG_RSRVD0 2 +#define BM_ENET_SWI_MODE_CONFIG_RSRVD0 0x0000007C +#define BF_ENET_SWI_MODE_CONFIG_RSRVD0(v) \ + (((v) << 2) & BM_ENET_SWI_MODE_CONFIG_RSRVD0) +#define BM_ENET_SWI_MODE_CONFIG_SWITCH_EN 0x00000002 +#define BM_ENET_SWI_MODE_CONFIG_SWITCH_RESET 0x00000001 + +#define HW_ENET_SWI_VLAN_IN_MODE (0x00008024) + +#define BP_ENET_SWI_VLAN_IN_MODE_RSRVD0 6 +#define BM_ENET_SWI_VLAN_IN_MODE_RSRVD0 0xFFFFFFC0 +#define BF_ENET_SWI_VLAN_IN_MODE_RSRVD0(v) \ + (((v) << 6) & BM_ENET_SWI_VLAN_IN_MODE_RSRVD0) +#define BP_ENET_SWI_VLAN_IN_MODE_VLAN_IN_MODE_2 4 +#define BM_ENET_SWI_VLAN_IN_MODE_VLAN_IN_MODE_2 0x00000030 +#define BF_ENET_SWI_VLAN_IN_MODE_VLAN_IN_MODE_2(v) \ + (((v) << 4) & BM_ENET_SWI_VLAN_IN_MODE_VLAN_IN_MODE_2) +#define BP_ENET_SWI_VLAN_IN_MODE_VLAN_IN_MODE_1 2 +#define BM_ENET_SWI_VLAN_IN_MODE_VLAN_IN_MODE_1 0x0000000C +#define BF_ENET_SWI_VLAN_IN_MODE_VLAN_IN_MODE_1(v) \ + (((v) << 2) & BM_ENET_SWI_VLAN_IN_MODE_VLAN_IN_MODE_1) +#define BP_ENET_SWI_VLAN_IN_MODE_VLAN_IN_MODE_0 0 +#define BM_ENET_SWI_VLAN_IN_MODE_VLAN_IN_MODE_0 0x00000003 +#define BF_ENET_SWI_VLAN_IN_MODE_VLAN_IN_MODE_0(v) \ + (((v) << 0) & BM_ENET_SWI_VLAN_IN_MODE_VLAN_IN_MODE_0) + +#define HW_ENET_SWI_VLAN_OUT_MODE (0x00008028) + +#define BP_ENET_SWI_VLAN_OUT_MODE_RSRVD0 6 +#define BM_ENET_SWI_VLAN_OUT_MODE_RSRVD0 0xFFFFFFC0 +#define BF_ENET_SWI_VLAN_OUT_MODE_RSRVD0(v) \ + (((v) << 6) & BM_ENET_SWI_VLAN_OUT_MODE_RSRVD0) +#define BP_ENET_SWI_VLAN_OUT_MODE_VLAN_OUT_MODE_2 4 +#define BM_ENET_SWI_VLAN_OUT_MODE_VLAN_OUT_MODE_2 0x00000030 +#define BF_ENET_SWI_VLAN_OUT_MODE_VLAN_OUT_MODE_2(v) \ + (((v) << 4) & BM_ENET_SWI_VLAN_OUT_MODE_VLAN_OUT_MODE_2) +#define BP_ENET_SWI_VLAN_OUT_MODE_VLAN_OUT_MODE_1 2 +#define BM_ENET_SWI_VLAN_OUT_MODE_VLAN_OUT_MODE_1 0x0000000C +#define BF_ENET_SWI_VLAN_OUT_MODE_VLAN_OUT_MODE_1(v) \ + (((v) << 2) & BM_ENET_SWI_VLAN_OUT_MODE_VLAN_OUT_MODE_1) +#define BP_ENET_SWI_VLAN_OUT_MODE_VLAN_OUT_MODE_0 0 +#define BM_ENET_SWI_VLAN_OUT_MODE_VLAN_OUT_MODE_0 0x00000003 +#define BF_ENET_SWI_VLAN_OUT_MODE_VLAN_OUT_MODE_0(v) \ + (((v) << 0) & BM_ENET_SWI_VLAN_OUT_MODE_VLAN_OUT_MODE_0) + +#define HW_ENET_SWI_VLAN_IN_MODE_ENA (0x0000802c) + +#define BP_ENET_SWI_VLAN_IN_MODE_ENA_RSRVD0 3 +#define BM_ENET_SWI_VLAN_IN_MODE_ENA_RSRVD0 0xFFFFFFF8 +#define BF_ENET_SWI_VLAN_IN_MODE_ENA_RSRVD0(v) \ + (((v) << 3) & BM_ENET_SWI_VLAN_IN_MODE_ENA_RSRVD0) +#define BM_ENET_SWI_VLAN_IN_MODE_ENA_VLAN_IN_MODE_ENA_2 0x00000004 +#define BM_ENET_SWI_VLAN_IN_MODE_ENA_VLAN_IN_MODE_ENA_1 0x00000002 +#define BM_ENET_SWI_VLAN_IN_MODE_ENA_VLAN_IN_MODE_ENA_0 0x00000001 + +#define HW_ENET_SWI_VLAN_TAG_ID (0x00008030) + +#define BP_ENET_SWI_VLAN_TAG_ID_RSRVD0 16 +#define BM_ENET_SWI_VLAN_TAG_ID_RSRVD0 0xFFFF0000 +#define BF_ENET_SWI_VLAN_TAG_ID_RSRVD0(v) \ + (((v) << 16) & BM_ENET_SWI_VLAN_TAG_ID_RSRVD0) +#define BP_ENET_SWI_VLAN_TAG_ID_SWI_VLAN_TAG_ID 0 +#define BM_ENET_SWI_VLAN_TAG_ID_SWI_VLAN_TAG_ID 0x0000FFFF +#define BF_ENET_SWI_VLAN_TAG_ID_SWI_VLAN_TAG_ID(v) \ + (((v) << 0) & BM_ENET_SWI_VLAN_TAG_ID_SWI_VLAN_TAG_ID) + +#define HW_ENET_SWI_MIRROR_CONTROL (0x0000803c) + +#define BP_ENET_SWI_MIRROR_CONTROL_RSRVD0 11 +#define BM_ENET_SWI_MIRROR_CONTROL_RSRVD0 0xFFFFF800 +#define BF_ENET_SWI_MIRROR_CONTROL_RSRVD0(v) \ + (((v) << 11) & BM_ENET_SWI_MIRROR_CONTROL_RSRVD0) +#define BM_ENET_SWI_MIRROR_CONTROL_EG_DA_MATCH 0x00000400 +#define BM_ENET_SWI_MIRROR_CONTROL_EG_SA_MATCH 0x00000200 +#define BM_ENET_SWI_MIRROR_CONTROL_ING_DA_MATCH 0x00000100 +#define BM_ENET_SWI_MIRROR_CONTROL_ING_SA_MATCH 0x00000080 +#define BM_ENET_SWI_MIRROR_CONTROL_EG_MAP_ENABLE 0x00000040 +#define BM_ENET_SWI_MIRROR_CONTROL_ING_MAP_ENABLE 0x00000020 +#define BM_ENET_SWI_MIRROR_CONTROL_MIRROR_ENABLE 0x00000010 +#define BP_ENET_SWI_MIRROR_CONTROL_PORTX 0 +#define BM_ENET_SWI_MIRROR_CONTROL_PORTX 0x0000000F +#define BF_ENET_SWI_MIRROR_CONTROL_PORTX(v) \ + (((v) << 0) & BM_ENET_SWI_MIRROR_CONTROL_PORTX) + +#define HW_ENET_SWI_MIRROR_EG_MAP (0x00008040) + +#define BP_ENET_SWI_MIRROR_EG_MAP_RSRVD0 3 +#define BM_ENET_SWI_MIRROR_EG_MAP_RSRVD0 0xFFFFFFF8 +#define BF_ENET_SWI_MIRROR_EG_MAP_RSRVD0(v) \ + (((v) << 3) & BM_ENET_SWI_MIRROR_EG_MAP_RSRVD0) +#define BM_ENET_SWI_MIRROR_EG_MAP_MIRROR_EG_MAP_2 0x00000004 +#define BM_ENET_SWI_MIRROR_EG_MAP_MIRROR_EG_MAP_1 0x00000002 +#define BM_ENET_SWI_MIRROR_EG_MAP_MIRROR_EG_MAP_0 0x00000001 + +#define HW_ENET_SWI_MIRROR_ING_MAP (0x00008044) + +#define BP_ENET_SWI_MIRROR_ING_MAP_RSRVD0 3 +#define BM_ENET_SWI_MIRROR_ING_MAP_RSRVD0 0xFFFFFFF8 +#define BF_ENET_SWI_MIRROR_ING_MAP_RSRVD0(v) \ + (((v) << 3) & BM_ENET_SWI_MIRROR_ING_MAP_RSRVD0) +#define BM_ENET_SWI_MIRROR_ING_MAP_MIRROR_ING_MAP_2 0x00000004 +#define BM_ENET_SWI_MIRROR_ING_MAP_MIRROR_ING_MAP_1 0x00000002 +#define BM_ENET_SWI_MIRROR_ING_MAP_MIRROR_ING_MAP_0 0x00000001 + +#define HW_ENET_SWI_MIRROR_ISRC_0 (0x00008048) + +#define BP_ENET_SWI_MIRROR_ISRC_0_MIRROR_ISRC_0 0 +#define BM_ENET_SWI_MIRROR_ISRC_0_MIRROR_ISRC_0 0xFFFFFFFF +#define BF_ENET_SWI_MIRROR_ISRC_0_MIRROR_ISRC_0(v) (v) + +#define HW_ENET_SWI_MIRROR_ISRC_1 (0x0000804c) + +#define BP_ENET_SWI_MIRROR_ISRC_1_RSRVD0 16 +#define BM_ENET_SWI_MIRROR_ISRC_1_RSRVD0 0xFFFF0000 +#define BF_ENET_SWI_MIRROR_ISRC_1_RSRVD0(v) \ + (((v) << 16) & BM_ENET_SWI_MIRROR_ISRC_1_RSRVD0) +#define BP_ENET_SWI_MIRROR_ISRC_1_MIRROR_ISRC_1 0 +#define BM_ENET_SWI_MIRROR_ISRC_1_MIRROR_ISRC_1 0x0000FFFF +#define BF_ENET_SWI_MIRROR_ISRC_1_MIRROR_ISRC_1(v) \ + (((v) << 0) & BM_ENET_SWI_MIRROR_ISRC_1_MIRROR_ISRC_1) + +#define HW_ENET_SWI_MIRROR_IDST_0 (0x00008050) + +#define BP_ENET_SWI_MIRROR_IDST_0_MIRROR_IDST_0 0 +#define BM_ENET_SWI_MIRROR_IDST_0_MIRROR_IDST_0 0xFFFFFFFF +#define BF_ENET_SWI_MIRROR_IDST_0_MIRROR_IDST_0(v) (v) + +#define HW_ENET_SWI_MIRROR_IDST_1 (0x00008054) + +#define BP_ENET_SWI_MIRROR_IDST_1_RSRVD0 16 +#define BM_ENET_SWI_MIRROR_IDST_1_RSRVD0 0xFFFF0000 +#define BF_ENET_SWI_MIRROR_IDST_1_RSRVD0(v) \ + (((v) << 16) & BM_ENET_SWI_MIRROR_IDST_1_RSRVD0) +#define BP_ENET_SWI_MIRROR_IDST_1_MIRROR_IDST_1 0 +#define BM_ENET_SWI_MIRROR_IDST_1_MIRROR_IDST_1 0x0000FFFF +#define BF_ENET_SWI_MIRROR_IDST_1_MIRROR_IDST_1(v) \ + (((v) << 0) & BM_ENET_SWI_MIRROR_IDST_1_MIRROR_IDST_1) + +#define HW_ENET_SWI_MIRROR_ESRC_0 (0x00008058) + +#define BP_ENET_SWI_MIRROR_ESRC_0_MIRROR_ESRC_0 0 +#define BM_ENET_SWI_MIRROR_ESRC_0_MIRROR_ESRC_0 0xFFFFFFFF +#define BF_ENET_SWI_MIRROR_ESRC_0_MIRROR_ESRC_0(v) (v) + +#define HW_ENET_SWI_MIRROR_ESRC_1 (0x0000805c) + +#define BP_ENET_SWI_MIRROR_ESRC_1_RSRVD0 16 +#define BM_ENET_SWI_MIRROR_ESRC_1_RSRVD0 0xFFFF0000 +#define BF_ENET_SWI_MIRROR_ESRC_1_RSRVD0(v) \ + (((v) << 16) & BM_ENET_SWI_MIRROR_ESRC_1_RSRVD0) +#define BP_ENET_SWI_MIRROR_ESRC_1_MIRROR_ESRC_1 0 +#define BM_ENET_SWI_MIRROR_ESRC_1_MIRROR_ESRC_1 0x0000FFFF +#define BF_ENET_SWI_MIRROR_ESRC_1_MIRROR_ESRC_1(v) \ + (((v) << 0) & BM_ENET_SWI_MIRROR_ESRC_1_MIRROR_ESRC_1) + +#define HW_ENET_SWI_MIRROR_EDST_0 (0x00008060) + +#define BP_ENET_SWI_MIRROR_EDST_0_MIRROR_ESRC_0 0 +#define BM_ENET_SWI_MIRROR_EDST_0_MIRROR_ESRC_0 0xFFFFFFFF +#define BF_ENET_SWI_MIRROR_EDST_0_MIRROR_ESRC_0(v) (v) + +#define HW_ENET_SWI_MIRROR_EDST_1 (0x00008064) + +#define BP_ENET_SWI_MIRROR_EDST_1_RSRVD0 16 +#define BM_ENET_SWI_MIRROR_EDST_1_RSRVD0 0xFFFF0000 +#define BF_ENET_SWI_MIRROR_EDST_1_RSRVD0(v) \ + (((v) << 16) & BM_ENET_SWI_MIRROR_EDST_1_RSRVD0) +#define BP_ENET_SWI_MIRROR_EDST_1_MIRROR_ESRC_1 0 +#define BM_ENET_SWI_MIRROR_EDST_1_MIRROR_ESRC_1 0x0000FFFF +#define BF_ENET_SWI_MIRROR_EDST_1_MIRROR_ESRC_1(v) \ + (((v) << 0) & BM_ENET_SWI_MIRROR_EDST_1_MIRROR_ESRC_1) + +#define HW_ENET_SWI_MIRROR_CNT (0x00008068) + +#define BP_ENET_SWI_MIRROR_CNT_RSRVD0 8 +#define BM_ENET_SWI_MIRROR_CNT_RSRVD0 0xFFFFFF00 +#define BF_ENET_SWI_MIRROR_CNT_RSRVD0(v) \ + (((v) << 8) & BM_ENET_SWI_MIRROR_CNT_RSRVD0) +#define BP_ENET_SWI_MIRROR_CNT_MIRROR_CNT 0 +#define BM_ENET_SWI_MIRROR_CNT_MIRROR_CNT 0x000000FF +#define BF_ENET_SWI_MIRROR_CNT_MIRROR_CNT(v) \ + (((v) << 0) & BM_ENET_SWI_MIRROR_CNT_MIRROR_CNT) + +#define HW_ENET_SWI_OQMGR_STATUS (0x0000807c) + +#define BP_ENET_SWI_OQMGR_STATUS_RSRVD2 24 +#define BM_ENET_SWI_OQMGR_STATUS_RSRVD2 0xFF000000 +#define BF_ENET_SWI_OQMGR_STATUS_RSRVD2(v) \ + (((v) << 24) & BM_ENET_SWI_OQMGR_STATUS_RSRVD2) +#define BP_ENET_SWI_OQMGR_STATUS_CELLS_AVAILABLE 16 +#define BM_ENET_SWI_OQMGR_STATUS_CELLS_AVAILABLE 0x00FF0000 +#define BF_ENET_SWI_OQMGR_STATUS_CELLS_AVAILABLE(v) \ + (((v) << 16) & BM_ENET_SWI_OQMGR_STATUS_CELLS_AVAILABLE) +#define BP_ENET_SWI_OQMGR_STATUS_RSRVD1 7 +#define BM_ENET_SWI_OQMGR_STATUS_RSRVD1 0x0000FF80 +#define BF_ENET_SWI_OQMGR_STATUS_RSRVD1(v) \ + (((v) << 7) & BM_ENET_SWI_OQMGR_STATUS_RSRVD1) +#define BM_ENET_SWI_OQMGR_STATUS_DEQUEUE_GRANT 0x00000040 +#define BP_ENET_SWI_OQMGR_STATUS_RSRVD0 4 +#define BM_ENET_SWI_OQMGR_STATUS_RSRVD0 0x00000030 +#define BF_ENET_SWI_OQMGR_STATUS_RSRVD0(v) \ + (((v) << 4) & BM_ENET_SWI_OQMGR_STATUS_RSRVD0) +#define BM_ENET_SWI_OQMGR_STATUS_MEM_FULL_LATCH 0x00000008 +#define BM_ENET_SWI_OQMGR_STATUS_MEM_FULL 0x00000004 +#define BM_ENET_SWI_OQMGR_STATUS_NO_CELL_LATCH 0x00000002 +#define BM_ENET_SWI_OQMGR_STATUS_BUSY_INITIALIZING 0x00000001 + +#define HW_ENET_SWI_QMGR_MINCELLS (0x00008080) + +#define BP_ENET_SWI_QMGR_MINCELLS_RSRVD0 8 +#define BM_ENET_SWI_QMGR_MINCELLS_RSRVD0 0xFFFFFF00 +#define BF_ENET_SWI_QMGR_MINCELLS_RSRVD0(v) \ + (((v) << 8) & BM_ENET_SWI_QMGR_MINCELLS_RSRVD0) +#define BP_ENET_SWI_QMGR_MINCELLS_QMGR_MINCELLS 0 +#define BM_ENET_SWI_QMGR_MINCELLS_QMGR_MINCELLS 0x000000FF +#define BF_ENET_SWI_QMGR_MINCELLS_QMGR_MINCELLS(v) \ + (((v) << 0) & BM_ENET_SWI_QMGR_MINCELLS_QMGR_MINCELLS) + +#define HW_ENET_SWI_QMGR_ST_MINCELLS (0x00008084) + +#define BP_ENET_SWI_QMGR_ST_MINCELLS_QMGR_ST_MINCELLS 0 +#define BM_ENET_SWI_QMGR_ST_MINCELLS_QMGR_ST_MINCELLS 0xFFFFFFFF +#define BF_ENET_SWI_QMGR_ST_MINCELLS_QMGR_ST_MINCELLS(v) (v) + +#define HW_ENET_SWI_QMGR_CONGEST_STAT (0x00008088) + +#define BP_ENET_SWI_QMGR_CONGEST_STAT_RSRVD0 3 +#define BM_ENET_SWI_QMGR_CONGEST_STAT_RSRVD0 0xFFFFFFF8 +#define BF_ENET_SWI_QMGR_CONGEST_STAT_RSRVD0(v) \ + (((v) << 3) & BM_ENET_SWI_QMGR_CONGEST_STAT_RSRVD0) +#define BM_ENET_SWI_QMGR_CONGEST_STAT_QMGR_CONGEST_STAT_2 0x00000004 +#define BM_ENET_SWI_QMGR_CONGEST_STAT_QMGR_CONGEST_STAT_1 0x00000002 +#define BM_ENET_SWI_QMGR_CONGEST_STAT_QMGR_CONGEST_STAT_0 0x00000001 + +#define HW_ENET_SWI_QMGR_IFACE_STAT (0x0000808c) + +#define BP_ENET_SWI_QMGR_IFACE_STAT_RSRVD1 19 +#define BM_ENET_SWI_QMGR_IFACE_STAT_RSRVD1 0xFFF80000 +#define BF_ENET_SWI_QMGR_IFACE_STAT_RSRVD1(v) \ + (((v) << 19) & BM_ENET_SWI_QMGR_IFACE_STAT_RSRVD1) +#define BM_ENET_SWI_QMGR_IFACE_STAT_INPUT_2 0x00040000 +#define BM_ENET_SWI_QMGR_IFACE_STAT_INPUT_1 0x00020000 +#define BM_ENET_SWI_QMGR_IFACE_STAT_INPUT_0 0x00010000 +#define BP_ENET_SWI_QMGR_IFACE_STAT_RSRVD0 3 +#define BM_ENET_SWI_QMGR_IFACE_STAT_RSRVD0 0x0000FFF8 +#define BF_ENET_SWI_QMGR_IFACE_STAT_RSRVD0(v) \ + (((v) << 3) & BM_ENET_SWI_QMGR_IFACE_STAT_RSRVD0) +#define BM_ENET_SWI_QMGR_IFACE_STAT_OUTPUT_2 0x00000004 +#define BM_ENET_SWI_QMGR_IFACE_STAT_OUTPUT_1 0x00000002 +#define BM_ENET_SWI_QMGR_IFACE_STAT_OUTPUT_0 0x00000001 + +#define HW_ENET_SWI_QM_WEIGHTS (0x00008090) + +#define BP_ENET_SWI_QM_WEIGHTS_RSRVD3 29 +#define BM_ENET_SWI_QM_WEIGHTS_RSRVD3 0xE0000000 +#define BF_ENET_SWI_QM_WEIGHTS_RSRVD3(v) \ + (((v) << 29) & BM_ENET_SWI_QM_WEIGHTS_RSRVD3) +#define BP_ENET_SWI_QM_WEIGHTS_QUEUE_3 24 +#define BM_ENET_SWI_QM_WEIGHTS_QUEUE_3 0x1F000000 +#define BF_ENET_SWI_QM_WEIGHTS_QUEUE_3(v) \ + (((v) << 24) & BM_ENET_SWI_QM_WEIGHTS_QUEUE_3) +#define BP_ENET_SWI_QM_WEIGHTS_RSRVD2 21 +#define BM_ENET_SWI_QM_WEIGHTS_RSRVD2 0x00E00000 +#define BF_ENET_SWI_QM_WEIGHTS_RSRVD2(v) \ + (((v) << 21) & BM_ENET_SWI_QM_WEIGHTS_RSRVD2) +#define BP_ENET_SWI_QM_WEIGHTS_QUEUE_2 16 +#define BM_ENET_SWI_QM_WEIGHTS_QUEUE_2 0x001F0000 +#define BF_ENET_SWI_QM_WEIGHTS_QUEUE_2(v) \ + (((v) << 16) & BM_ENET_SWI_QM_WEIGHTS_QUEUE_2) +#define BP_ENET_SWI_QM_WEIGHTS_RSRVD1 13 +#define BM_ENET_SWI_QM_WEIGHTS_RSRVD1 0x0000E000 +#define BF_ENET_SWI_QM_WEIGHTS_RSRVD1(v) \ + (((v) << 13) & BM_ENET_SWI_QM_WEIGHTS_RSRVD1) +#define BP_ENET_SWI_QM_WEIGHTS_QUEUE_1 8 +#define BM_ENET_SWI_QM_WEIGHTS_QUEUE_1 0x00001F00 +#define BF_ENET_SWI_QM_WEIGHTS_QUEUE_1(v) \ + (((v) << 8) & BM_ENET_SWI_QM_WEIGHTS_QUEUE_1) +#define BP_ENET_SWI_QM_WEIGHTS_RSRVD0 5 +#define BM_ENET_SWI_QM_WEIGHTS_RSRVD0 0x000000E0 +#define BF_ENET_SWI_QM_WEIGHTS_RSRVD0(v) \ + (((v) << 5) & BM_ENET_SWI_QM_WEIGHTS_RSRVD0) +#define BP_ENET_SWI_QM_WEIGHTS_QUEUE_0 0 +#define BM_ENET_SWI_QM_WEIGHTS_QUEUE_0 0x0000001F +#define BF_ENET_SWI_QM_WEIGHTS_QUEUE_0(v) \ + (((v) << 0) & BM_ENET_SWI_QM_WEIGHTS_QUEUE_0) + +#define HW_ENET_SWI_QMGR_MINCELLSP0 (0x00008098) + +#define BP_ENET_SWI_QMGR_MINCELLSP0_RSRVD0 8 +#define BM_ENET_SWI_QMGR_MINCELLSP0_RSRVD0 0xFFFFFF00 +#define BF_ENET_SWI_QMGR_MINCELLSP0_RSRVD0(v) \ + (((v) << 8) & BM_ENET_SWI_QMGR_MINCELLSP0_RSRVD0) +#define BP_ENET_SWI_QMGR_MINCELLSP0_QMGR_MINCELLSP0 0 +#define BM_ENET_SWI_QMGR_MINCELLSP0_QMGR_MINCELLSP0 0x000000FF +#define BF_ENET_SWI_QMGR_MINCELLSP0_QMGR_MINCELLSP0(v) \ + (((v) << 0) & BM_ENET_SWI_QMGR_MINCELLSP0_QMGR_MINCELLSP0) + +#define HW_ENET_SWI_FORCE_FWD_P0 (0x000080b8) + +#define BP_ENET_SWI_FORCE_FWD_P0_RSRVD1 4 +#define BM_ENET_SWI_FORCE_FWD_P0_RSRVD1 0xFFFFFFF0 +#define BF_ENET_SWI_FORCE_FWD_P0_RSRVD1(v) \ + (((v) << 4) & BM_ENET_SWI_FORCE_FWD_P0_RSRVD1) +#define BP_ENET_SWI_FORCE_FWD_P0_FORCE_DESTINATION 2 +#define BM_ENET_SWI_FORCE_FWD_P0_FORCE_DESTINATION 0x0000000C +#define BF_ENET_SWI_FORCE_FWD_P0_FORCE_DESTINATION(v) \ + (((v) << 2) & BM_ENET_SWI_FORCE_FWD_P0_FORCE_DESTINATION) +#define BM_ENET_SWI_FORCE_FWD_P0_RSRVD0 0x00000002 +#define BM_ENET_SWI_FORCE_FWD_P0_FORCE_ENABLE 0x00000001 + +#define HW_ENET_SWI_PORTSNOOP1 (0x000080bc) + +#define BP_ENET_SWI_PORTSNOOP1_DESTINATION_PORT 16 +#define BM_ENET_SWI_PORTSNOOP1_DESTINATION_PORT 0xFFFF0000 +#define BF_ENET_SWI_PORTSNOOP1_DESTINATION_PORT(v) \ + (((v) << 16) & BM_ENET_SWI_PORTSNOOP1_DESTINATION_PORT) +#define BP_ENET_SWI_PORTSNOOP1_RSRVD0 5 +#define BM_ENET_SWI_PORTSNOOP1_RSRVD0 0x0000FFE0 +#define BF_ENET_SWI_PORTSNOOP1_RSRVD0(v) \ + (((v) << 5) & BM_ENET_SWI_PORTSNOOP1_RSRVD0) +#define BM_ENET_SWI_PORTSNOOP1_COMPARE_SOURCE 0x00000010 +#define BM_ENET_SWI_PORTSNOOP1_COMPARE_DEST 0x00000008 +#define BP_ENET_SWI_PORTSNOOP1_MODE 1 +#define BM_ENET_SWI_PORTSNOOP1_MODE 0x00000006 +#define BF_ENET_SWI_PORTSNOOP1_MODE(v) \ + (((v) << 1) & BM_ENET_SWI_PORTSNOOP1_MODE) +#define BM_ENET_SWI_PORTSNOOP1_ENABLE 0x00000001 + +#define HW_ENET_SWI_PORTSNOOP2 (0x000080c0) + +#define BP_ENET_SWI_PORTSNOOP2_DESTINATION_PORT 16 +#define BM_ENET_SWI_PORTSNOOP2_DESTINATION_PORT 0xFFFF0000 +#define BF_ENET_SWI_PORTSNOOP2_DESTINATION_PORT(v) \ + (((v) << 16) & BM_ENET_SWI_PORTSNOOP2_DESTINATION_PORT) +#define BP_ENET_SWI_PORTSNOOP2_RSRVD0 5 +#define BM_ENET_SWI_PORTSNOOP2_RSRVD0 0x0000FFE0 +#define BF_ENET_SWI_PORTSNOOP2_RSRVD0(v) \ + (((v) << 5) & BM_ENET_SWI_PORTSNOOP2_RSRVD0) +#define BM_ENET_SWI_PORTSNOOP2_COMPARE_SOURCE 0x00000010 +#define BM_ENET_SWI_PORTSNOOP2_COMPARE_DEST 0x00000008 +#define BP_ENET_SWI_PORTSNOOP2_MODE 1 +#define BM_ENET_SWI_PORTSNOOP2_MODE 0x00000006 +#define BF_ENET_SWI_PORTSNOOP2_MODE(v) \ + (((v) << 1) & BM_ENET_SWI_PORTSNOOP2_MODE) +#define BM_ENET_SWI_PORTSNOOP2_ENABLE 0x00000001 + +#define HW_ENET_SWI_PORTSNOOP3 (0x000080c4) + +#define BP_ENET_SWI_PORTSNOOP3_DESTINATION_PORT 16 +#define BM_ENET_SWI_PORTSNOOP3_DESTINATION_PORT 0xFFFF0000 +#define BF_ENET_SWI_PORTSNOOP3_DESTINATION_PORT(v) \ + (((v) << 16) & BM_ENET_SWI_PORTSNOOP3_DESTINATION_PORT) +#define BP_ENET_SWI_PORTSNOOP3_RSRVD0 5 +#define BM_ENET_SWI_PORTSNOOP3_RSRVD0 0x0000FFE0 +#define BF_ENET_SWI_PORTSNOOP3_RSRVD0(v) \ + (((v) << 5) & BM_ENET_SWI_PORTSNOOP3_RSRVD0) +#define BM_ENET_SWI_PORTSNOOP3_COMPARE_SOURCE 0x00000010 +#define BM_ENET_SWI_PORTSNOOP3_COMPARE_DEST 0x00000008 +#define BP_ENET_SWI_PORTSNOOP3_MODE 1 +#define BM_ENET_SWI_PORTSNOOP3_MODE 0x00000006 +#define BF_ENET_SWI_PORTSNOOP3_MODE(v) \ + (((v) << 1) & BM_ENET_SWI_PORTSNOOP3_MODE) +#define BM_ENET_SWI_PORTSNOOP3_ENABLE 0x00000001 + +#define HW_ENET_SWI_PORTSNOOP4 (0x000080c8) + +#define BP_ENET_SWI_PORTSNOOP4_DESTINATION_PORT 16 +#define BM_ENET_SWI_PORTSNOOP4_DESTINATION_PORT 0xFFFF0000 +#define BF_ENET_SWI_PORTSNOOP4_DESTINATION_PORT(v) \ + (((v) << 16) & BM_ENET_SWI_PORTSNOOP4_DESTINATION_PORT) +#define BP_ENET_SWI_PORTSNOOP4_RSRVD0 5 +#define BM_ENET_SWI_PORTSNOOP4_RSRVD0 0x0000FFE0 +#define BF_ENET_SWI_PORTSNOOP4_RSRVD0(v) \ + (((v) << 5) & BM_ENET_SWI_PORTSNOOP4_RSRVD0) +#define BM_ENET_SWI_PORTSNOOP4_COMPARE_SOURCE 0x00000010 +#define BM_ENET_SWI_PORTSNOOP4_COMPARE_DEST 0x00000008 +#define BP_ENET_SWI_PORTSNOOP4_MODE 1 +#define BM_ENET_SWI_PORTSNOOP4_MODE 0x00000006 +#define BF_ENET_SWI_PORTSNOOP4_MODE(v) \ + (((v) << 1) & BM_ENET_SWI_PORTSNOOP4_MODE) +#define BM_ENET_SWI_PORTSNOOP4_ENABLE 0x00000001 + +#define HW_ENET_SWI_PORTSNOOP5 (0x000080cc) + +#define BP_ENET_SWI_PORTSNOOP5_DESTINATION_PORT 16 +#define BM_ENET_SWI_PORTSNOOP5_DESTINATION_PORT 0xFFFF0000 +#define BF_ENET_SWI_PORTSNOOP5_DESTINATION_PORT(v) \ + (((v) << 16) & BM_ENET_SWI_PORTSNOOP5_DESTINATION_PORT) +#define BP_ENET_SWI_PORTSNOOP5_RSRVD0 5 +#define BM_ENET_SWI_PORTSNOOP5_RSRVD0 0x0000FFE0 +#define BF_ENET_SWI_PORTSNOOP5_RSRVD0(v) \ + (((v) << 5) & BM_ENET_SWI_PORTSNOOP5_RSRVD0) +#define BM_ENET_SWI_PORTSNOOP5_COMPARE_SOURCE 0x00000010 +#define BM_ENET_SWI_PORTSNOOP5_COMPARE_DEST 0x00000008 +#define BP_ENET_SWI_PORTSNOOP5_MODE 1 +#define BM_ENET_SWI_PORTSNOOP5_MODE 0x00000006 +#define BF_ENET_SWI_PORTSNOOP5_MODE(v) \ + (((v) << 1) & BM_ENET_SWI_PORTSNOOP5_MODE) +#define BM_ENET_SWI_PORTSNOOP5_ENABLE 0x00000001 + +#define HW_ENET_SWI_PORTSNOOP6 (0x000080d0) + +#define BP_ENET_SWI_PORTSNOOP6_DESTINATION_PORT 16 +#define BM_ENET_SWI_PORTSNOOP6_DESTINATION_PORT 0xFFFF0000 +#define BF_ENET_SWI_PORTSNOOP6_DESTINATION_PORT(v) \ + (((v) << 16) & BM_ENET_SWI_PORTSNOOP6_DESTINATION_PORT) +#define BP_ENET_SWI_PORTSNOOP6_RSRVD0 5 +#define BM_ENET_SWI_PORTSNOOP6_RSRVD0 0x0000FFE0 +#define BF_ENET_SWI_PORTSNOOP6_RSRVD0(v) \ + (((v) << 5) & BM_ENET_SWI_PORTSNOOP6_RSRVD0) +#define BM_ENET_SWI_PORTSNOOP6_COMPARE_SOURCE 0x00000010 +#define BM_ENET_SWI_PORTSNOOP6_COMPARE_DEST 0x00000008 +#define BP_ENET_SWI_PORTSNOOP6_MODE 1 +#define BM_ENET_SWI_PORTSNOOP6_MODE 0x00000006 +#define BF_ENET_SWI_PORTSNOOP6_MODE(v) \ + (((v) << 1) & BM_ENET_SWI_PORTSNOOP6_MODE) +#define BM_ENET_SWI_PORTSNOOP6_ENABLE 0x00000001 + +#define HW_ENET_SWI_PORTSNOOP7 (0x000080d4) + +#define BP_ENET_SWI_PORTSNOOP7_DESTINATION_PORT 16 +#define BM_ENET_SWI_PORTSNOOP7_DESTINATION_PORT 0xFFFF0000 +#define BF_ENET_SWI_PORTSNOOP7_DESTINATION_PORT(v) \ + (((v) << 16) & BM_ENET_SWI_PORTSNOOP7_DESTINATION_PORT) +#define BP_ENET_SWI_PORTSNOOP7_RSRVD0 5 +#define BM_ENET_SWI_PORTSNOOP7_RSRVD0 0x0000FFE0 +#define BF_ENET_SWI_PORTSNOOP7_RSRVD0(v) \ + (((v) << 5) & BM_ENET_SWI_PORTSNOOP7_RSRVD0) +#define BM_ENET_SWI_PORTSNOOP7_COMPARE_SOURCE 0x00000010 +#define BM_ENET_SWI_PORTSNOOP7_COMPARE_DEST 0x00000008 +#define BP_ENET_SWI_PORTSNOOP7_MODE 1 +#define BM_ENET_SWI_PORTSNOOP7_MODE 0x00000006 +#define BF_ENET_SWI_PORTSNOOP7_MODE(v) \ + (((v) << 1) & BM_ENET_SWI_PORTSNOOP7_MODE) +#define BM_ENET_SWI_PORTSNOOP7_ENABLE 0x00000001 + +#define HW_ENET_SWI_PORTSNOOP8 (0x000080d8) + +#define BP_ENET_SWI_PORTSNOOP8_DESTINATION_PORT 16 +#define BM_ENET_SWI_PORTSNOOP8_DESTINATION_PORT 0xFFFF0000 +#define BF_ENET_SWI_PORTSNOOP8_DESTINATION_PORT(v) \ + (((v) << 16) & BM_ENET_SWI_PORTSNOOP8_DESTINATION_PORT) +#define BP_ENET_SWI_PORTSNOOP8_RSRVD0 5 +#define BM_ENET_SWI_PORTSNOOP8_RSRVD0 0x0000FFE0 +#define BF_ENET_SWI_PORTSNOOP8_RSRVD0(v) \ + (((v) << 5) & BM_ENET_SWI_PORTSNOOP8_RSRVD0) +#define BM_ENET_SWI_PORTSNOOP8_COMPARE_SOURCE 0x00000010 +#define BM_ENET_SWI_PORTSNOOP8_COMPARE_DEST 0x00000008 +#define BP_ENET_SWI_PORTSNOOP8_MODE 1 +#define BM_ENET_SWI_PORTSNOOP8_MODE 0x00000006 +#define BF_ENET_SWI_PORTSNOOP8_MODE(v) \ + (((v) << 1) & BM_ENET_SWI_PORTSNOOP8_MODE) +#define BM_ENET_SWI_PORTSNOOP8_ENABLE 0x00000001 + +#define HW_ENET_SWI_IPSNOOP1 (0x000080dc) + +#define BP_ENET_SWI_IPSNOOP1_RSRVD1 16 +#define BM_ENET_SWI_IPSNOOP1_RSRVD1 0xFFFF0000 +#define BF_ENET_SWI_IPSNOOP1_RSRVD1(v) \ + (((v) << 16) & BM_ENET_SWI_IPSNOOP1_RSRVD1) +#define BP_ENET_SWI_IPSNOOP1_PROTOCOL 8 +#define BM_ENET_SWI_IPSNOOP1_PROTOCOL 0x0000FF00 +#define BF_ENET_SWI_IPSNOOP1_PROTOCOL(v) \ + (((v) << 8) & BM_ENET_SWI_IPSNOOP1_PROTOCOL) +#define BP_ENET_SWI_IPSNOOP1_RSRVD0 3 +#define BM_ENET_SWI_IPSNOOP1_RSRVD0 0x000000F8 +#define BF_ENET_SWI_IPSNOOP1_RSRVD0(v) \ + (((v) << 3) & BM_ENET_SWI_IPSNOOP1_RSRVD0) +#define BP_ENET_SWI_IPSNOOP1_MODE 1 +#define BM_ENET_SWI_IPSNOOP1_MODE 0x00000006 +#define BF_ENET_SWI_IPSNOOP1_MODE(v) \ + (((v) << 1) & BM_ENET_SWI_IPSNOOP1_MODE) +#define BM_ENET_SWI_IPSNOOP1_ENABLE 0x00000001 + +#define HW_ENET_SWI_IPSNOOP2 (0x000080e0) + +#define BP_ENET_SWI_IPSNOOP2_RSRVD1 16 +#define BM_ENET_SWI_IPSNOOP2_RSRVD1 0xFFFF0000 +#define BF_ENET_SWI_IPSNOOP2_RSRVD1(v) \ + (((v) << 16) & BM_ENET_SWI_IPSNOOP2_RSRVD1) +#define BP_ENET_SWI_IPSNOOP2_PROTOCOL 8 +#define BM_ENET_SWI_IPSNOOP2_PROTOCOL 0x0000FF00 +#define BF_ENET_SWI_IPSNOOP2_PROTOCOL(v) \ + (((v) << 8) & BM_ENET_SWI_IPSNOOP2_PROTOCOL) +#define BP_ENET_SWI_IPSNOOP2_RSRVD0 3 +#define BM_ENET_SWI_IPSNOOP2_RSRVD0 0x000000F8 +#define BF_ENET_SWI_IPSNOOP2_RSRVD0(v) \ + (((v) << 3) & BM_ENET_SWI_IPSNOOP2_RSRVD0) +#define BP_ENET_SWI_IPSNOOP2_MODE 1 +#define BM_ENET_SWI_IPSNOOP2_MODE 0x00000006 +#define BF_ENET_SWI_IPSNOOP2_MODE(v) \ + (((v) << 1) & BM_ENET_SWI_IPSNOOP2_MODE) +#define BM_ENET_SWI_IPSNOOP2_ENABLE 0x00000001 + +#define HW_ENET_SWI_IPSNOOP3 (0x000080e4) + +#define BP_ENET_SWI_IPSNOOP3_RSRVD1 16 +#define BM_ENET_SWI_IPSNOOP3_RSRVD1 0xFFFF0000 +#define BF_ENET_SWI_IPSNOOP3_RSRVD1(v) \ + (((v) << 16) & BM_ENET_SWI_IPSNOOP3_RSRVD1) +#define BP_ENET_SWI_IPSNOOP3_PROTOCOL 8 +#define BM_ENET_SWI_IPSNOOP3_PROTOCOL 0x0000FF00 +#define BF_ENET_SWI_IPSNOOP3_PROTOCOL(v) \ + (((v) << 8) & BM_ENET_SWI_IPSNOOP3_PROTOCOL) +#define BP_ENET_SWI_IPSNOOP3_RSRVD0 3 +#define BM_ENET_SWI_IPSNOOP3_RSRVD0 0x000000F8 +#define BF_ENET_SWI_IPSNOOP3_RSRVD0(v) \ + (((v) << 3) & BM_ENET_SWI_IPSNOOP3_RSRVD0) +#define BP_ENET_SWI_IPSNOOP3_MODE 1 +#define BM_ENET_SWI_IPSNOOP3_MODE 0x00000006 +#define BF_ENET_SWI_IPSNOOP3_MODE(v) \ + (((v) << 1) & BM_ENET_SWI_IPSNOOP3_MODE) +#define BM_ENET_SWI_IPSNOOP3_ENABLE 0x00000001 + +#define HW_ENET_SWI_IPSNOOP4 (0x000080e8) + +#define BP_ENET_SWI_IPSNOOP4_RSRVD1 16 +#define BM_ENET_SWI_IPSNOOP4_RSRVD1 0xFFFF0000 +#define BF_ENET_SWI_IPSNOOP4_RSRVD1(v) \ + (((v) << 16) & BM_ENET_SWI_IPSNOOP4_RSRVD1) +#define BP_ENET_SWI_IPSNOOP4_PROTOCOL 8 +#define BM_ENET_SWI_IPSNOOP4_PROTOCOL 0x0000FF00 +#define BF_ENET_SWI_IPSNOOP4_PROTOCOL(v) \ + (((v) << 8) & BM_ENET_SWI_IPSNOOP4_PROTOCOL) +#define BP_ENET_SWI_IPSNOOP4_RSRVD0 3 +#define BM_ENET_SWI_IPSNOOP4_RSRVD0 0x000000F8 +#define BF_ENET_SWI_IPSNOOP4_RSRVD0(v) \ + (((v) << 3) & BM_ENET_SWI_IPSNOOP4_RSRVD0) +#define BP_ENET_SWI_IPSNOOP4_MODE 1 +#define BM_ENET_SWI_IPSNOOP4_MODE 0x00000006 +#define BF_ENET_SWI_IPSNOOP4_MODE(v) \ + (((v) << 1) & BM_ENET_SWI_IPSNOOP4_MODE) +#define BM_ENET_SWI_IPSNOOP4_ENABLE 0x00000001 + +#define HW_ENET_SWI_IPSNOOP5 (0x000080ec) + +#define BP_ENET_SWI_IPSNOOP5_RSRVD1 16 +#define BM_ENET_SWI_IPSNOOP5_RSRVD1 0xFFFF0000 +#define BF_ENET_SWI_IPSNOOP5_RSRVD1(v) \ + (((v) << 16) & BM_ENET_SWI_IPSNOOP5_RSRVD1) +#define BP_ENET_SWI_IPSNOOP5_PROTOCOL 8 +#define BM_ENET_SWI_IPSNOOP5_PROTOCOL 0x0000FF00 +#define BF_ENET_SWI_IPSNOOP5_PROTOCOL(v) \ + (((v) << 8) & BM_ENET_SWI_IPSNOOP5_PROTOCOL) +#define BP_ENET_SWI_IPSNOOP5_RSRVD0 3 +#define BM_ENET_SWI_IPSNOOP5_RSRVD0 0x000000F8 +#define BF_ENET_SWI_IPSNOOP5_RSRVD0(v) \ + (((v) << 3) & BM_ENET_SWI_IPSNOOP5_RSRVD0) +#define BP_ENET_SWI_IPSNOOP5_MODE 1 +#define BM_ENET_SWI_IPSNOOP5_MODE 0x00000006 +#define BF_ENET_SWI_IPSNOOP5_MODE(v) \ + (((v) << 1) & BM_ENET_SWI_IPSNOOP5_MODE) +#define BM_ENET_SWI_IPSNOOP5_ENABLE 0x00000001 + +#define HW_ENET_SWI_IPSNOOP6 (0x000080f0) + +#define BP_ENET_SWI_IPSNOOP6_RSRVD1 16 +#define BM_ENET_SWI_IPSNOOP6_RSRVD1 0xFFFF0000 +#define BF_ENET_SWI_IPSNOOP6_RSRVD1(v) \ + (((v) << 16) & BM_ENET_SWI_IPSNOOP6_RSRVD1) +#define BP_ENET_SWI_IPSNOOP6_PROTOCOL 8 +#define BM_ENET_SWI_IPSNOOP6_PROTOCOL 0x0000FF00 +#define BF_ENET_SWI_IPSNOOP6_PROTOCOL(v) \ + (((v) << 8) & BM_ENET_SWI_IPSNOOP6_PROTOCOL) +#define BP_ENET_SWI_IPSNOOP6_RSRVD0 3 +#define BM_ENET_SWI_IPSNOOP6_RSRVD0 0x000000F8 +#define BF_ENET_SWI_IPSNOOP6_RSRVD0(v) \ + (((v) << 3) & BM_ENET_SWI_IPSNOOP6_RSRVD0) +#define BP_ENET_SWI_IPSNOOP6_MODE 1 +#define BM_ENET_SWI_IPSNOOP6_MODE 0x00000006 +#define BF_ENET_SWI_IPSNOOP6_MODE(v) \ + (((v) << 1) & BM_ENET_SWI_IPSNOOP6_MODE) +#define BM_ENET_SWI_IPSNOOP6_ENABLE 0x00000001 + +#define HW_ENET_SWI_IPSNOOP7 (0x000080f4) + +#define BP_ENET_SWI_IPSNOOP7_RSRVD1 16 +#define BM_ENET_SWI_IPSNOOP7_RSRVD1 0xFFFF0000 +#define BF_ENET_SWI_IPSNOOP7_RSRVD1(v) \ + (((v) << 16) & BM_ENET_SWI_IPSNOOP7_RSRVD1) +#define BP_ENET_SWI_IPSNOOP7_PROTOCOL 8 +#define BM_ENET_SWI_IPSNOOP7_PROTOCOL 0x0000FF00 +#define BF_ENET_SWI_IPSNOOP7_PROTOCOL(v) \ + (((v) << 8) & BM_ENET_SWI_IPSNOOP7_PROTOCOL) +#define BP_ENET_SWI_IPSNOOP7_RSRVD0 3 +#define BM_ENET_SWI_IPSNOOP7_RSRVD0 0x000000F8 +#define BF_ENET_SWI_IPSNOOP7_RSRVD0(v) \ + (((v) << 3) & BM_ENET_SWI_IPSNOOP7_RSRVD0) +#define BP_ENET_SWI_IPSNOOP7_MODE 1 +#define BM_ENET_SWI_IPSNOOP7_MODE 0x00000006 +#define BF_ENET_SWI_IPSNOOP7_MODE(v) \ + (((v) << 1) & BM_ENET_SWI_IPSNOOP7_MODE) +#define BM_ENET_SWI_IPSNOOP7_ENABLE 0x00000001 + +#define HW_ENET_SWI_IPSNOOP8 (0x000080f8) + +#define BP_ENET_SWI_IPSNOOP8_RSRVD1 16 +#define BM_ENET_SWI_IPSNOOP8_RSRVD1 0xFFFF0000 +#define BF_ENET_SWI_IPSNOOP8_RSRVD1(v) \ + (((v) << 16) & BM_ENET_SWI_IPSNOOP8_RSRVD1) +#define BP_ENET_SWI_IPSNOOP8_PROTOCOL 8 +#define BM_ENET_SWI_IPSNOOP8_PROTOCOL 0x0000FF00 +#define BF_ENET_SWI_IPSNOOP8_PROTOCOL(v) \ + (((v) << 8) & BM_ENET_SWI_IPSNOOP8_PROTOCOL) +#define BP_ENET_SWI_IPSNOOP8_RSRVD0 3 +#define BM_ENET_SWI_IPSNOOP8_RSRVD0 0x000000F8 +#define BF_ENET_SWI_IPSNOOP8_RSRVD0(v) \ + (((v) << 3) & BM_ENET_SWI_IPSNOOP8_RSRVD0) +#define BP_ENET_SWI_IPSNOOP8_MODE 1 +#define BM_ENET_SWI_IPSNOOP8_MODE 0x00000006 +#define BF_ENET_SWI_IPSNOOP8_MODE(v) \ + (((v) << 1) & BM_ENET_SWI_IPSNOOP8_MODE) +#define BM_ENET_SWI_IPSNOOP8_ENABLE 0x00000001 + +#define HW_ENET_SWI_VLAN_PRIORITY0 (0x000080fc) + +#define BP_ENET_SWI_VLAN_PRIORITY0_RSRVD0 24 +#define BM_ENET_SWI_VLAN_PRIORITY0_RSRVD0 0xFF000000 +#define BF_ENET_SWI_VLAN_PRIORITY0_RSRVD0(v) \ + (((v) << 24) & BM_ENET_SWI_VLAN_PRIORITY0_RSRVD0) +#define BP_ENET_SWI_VLAN_PRIORITY0_P7 21 +#define BM_ENET_SWI_VLAN_PRIORITY0_P7 0x00E00000 +#define BF_ENET_SWI_VLAN_PRIORITY0_P7(v) \ + (((v) << 21) & BM_ENET_SWI_VLAN_PRIORITY0_P7) +#define BP_ENET_SWI_VLAN_PRIORITY0_P6 18 +#define BM_ENET_SWI_VLAN_PRIORITY0_P6 0x001C0000 +#define BF_ENET_SWI_VLAN_PRIORITY0_P6(v) \ + (((v) << 18) & BM_ENET_SWI_VLAN_PRIORITY0_P6) +#define BP_ENET_SWI_VLAN_PRIORITY0_P5 15 +#define BM_ENET_SWI_VLAN_PRIORITY0_P5 0x00038000 +#define BF_ENET_SWI_VLAN_PRIORITY0_P5(v) \ + (((v) << 15) & BM_ENET_SWI_VLAN_PRIORITY0_P5) +#define BP_ENET_SWI_VLAN_PRIORITY0_P4 12 +#define BM_ENET_SWI_VLAN_PRIORITY0_P4 0x00007000 +#define BF_ENET_SWI_VLAN_PRIORITY0_P4(v) \ + (((v) << 12) & BM_ENET_SWI_VLAN_PRIORITY0_P4) +#define BP_ENET_SWI_VLAN_PRIORITY0_P3 9 +#define BM_ENET_SWI_VLAN_PRIORITY0_P3 0x00000E00 +#define BF_ENET_SWI_VLAN_PRIORITY0_P3(v) \ + (((v) << 9) & BM_ENET_SWI_VLAN_PRIORITY0_P3) +#define BP_ENET_SWI_VLAN_PRIORITY0_P2 6 +#define BM_ENET_SWI_VLAN_PRIORITY0_P2 0x000001C0 +#define BF_ENET_SWI_VLAN_PRIORITY0_P2(v) \ + (((v) << 6) & BM_ENET_SWI_VLAN_PRIORITY0_P2) +#define BP_ENET_SWI_VLAN_PRIORITY0_P1 3 +#define BM_ENET_SWI_VLAN_PRIORITY0_P1 0x00000038 +#define BF_ENET_SWI_VLAN_PRIORITY0_P1(v) \ + (((v) << 3) & BM_ENET_SWI_VLAN_PRIORITY0_P1) +#define BP_ENET_SWI_VLAN_PRIORITY0_P0 0 +#define BM_ENET_SWI_VLAN_PRIORITY0_P0 0x00000007 +#define BF_ENET_SWI_VLAN_PRIORITY0_P0(v) \ + (((v) << 0) & BM_ENET_SWI_VLAN_PRIORITY0_P0) + +#define HW_ENET_SWI_VLAN_PRIORITY1 (0x00008100) + +#define BP_ENET_SWI_VLAN_PRIORITY1_RSRVD0 24 +#define BM_ENET_SWI_VLAN_PRIORITY1_RSRVD0 0xFF000000 +#define BF_ENET_SWI_VLAN_PRIORITY1_RSRVD0(v) \ + (((v) << 24) & BM_ENET_SWI_VLAN_PRIORITY1_RSRVD0) +#define BP_ENET_SWI_VLAN_PRIORITY1_P7 21 +#define BM_ENET_SWI_VLAN_PRIORITY1_P7 0x00E00000 +#define BF_ENET_SWI_VLAN_PRIORITY1_P7(v) \ + (((v) << 21) & BM_ENET_SWI_VLAN_PRIORITY1_P7) +#define BP_ENET_SWI_VLAN_PRIORITY1_P6 18 +#define BM_ENET_SWI_VLAN_PRIORITY1_P6 0x001C0000 +#define BF_ENET_SWI_VLAN_PRIORITY1_P6(v) \ + (((v) << 18) & BM_ENET_SWI_VLAN_PRIORITY1_P6) +#define BP_ENET_SWI_VLAN_PRIORITY1_P5 15 +#define BM_ENET_SWI_VLAN_PRIORITY1_P5 0x00038000 +#define BF_ENET_SWI_VLAN_PRIORITY1_P5(v) \ + (((v) << 15) & BM_ENET_SWI_VLAN_PRIORITY1_P5) +#define BP_ENET_SWI_VLAN_PRIORITY1_P4 12 +#define BM_ENET_SWI_VLAN_PRIORITY1_P4 0x00007000 +#define BF_ENET_SWI_VLAN_PRIORITY1_P4(v) \ + (((v) << 12) & BM_ENET_SWI_VLAN_PRIORITY1_P4) +#define BP_ENET_SWI_VLAN_PRIORITY1_P3 9 +#define BM_ENET_SWI_VLAN_PRIORITY1_P3 0x00000E00 +#define BF_ENET_SWI_VLAN_PRIORITY1_P3(v) \ + (((v) << 9) & BM_ENET_SWI_VLAN_PRIORITY1_P3) +#define BP_ENET_SWI_VLAN_PRIORITY1_P2 6 +#define BM_ENET_SWI_VLAN_PRIORITY1_P2 0x000001C0 +#define BF_ENET_SWI_VLAN_PRIORITY1_P2(v) \ + (((v) << 6) & BM_ENET_SWI_VLAN_PRIORITY1_P2) +#define BP_ENET_SWI_VLAN_PRIORITY1_P1 3 +#define BM_ENET_SWI_VLAN_PRIORITY1_P1 0x00000038 +#define BF_ENET_SWI_VLAN_PRIORITY1_P1(v) \ + (((v) << 3) & BM_ENET_SWI_VLAN_PRIORITY1_P1) +#define BP_ENET_SWI_VLAN_PRIORITY1_P0 0 +#define BM_ENET_SWI_VLAN_PRIORITY1_P0 0x00000007 +#define BF_ENET_SWI_VLAN_PRIORITY1_P0(v) \ + (((v) << 0) & BM_ENET_SWI_VLAN_PRIORITY1_P0) + +#define HW_ENET_SWI_VLAN_PRIORITY2 (0x00008104) + +#define BP_ENET_SWI_VLAN_PRIORITY2_RSRVD0 24 +#define BM_ENET_SWI_VLAN_PRIORITY2_RSRVD0 0xFF000000 +#define BF_ENET_SWI_VLAN_PRIORITY2_RSRVD0(v) \ + (((v) << 24) & BM_ENET_SWI_VLAN_PRIORITY2_RSRVD0) +#define BP_ENET_SWI_VLAN_PRIORITY2_P7 21 +#define BM_ENET_SWI_VLAN_PRIORITY2_P7 0x00E00000 +#define BF_ENET_SWI_VLAN_PRIORITY2_P7(v) \ + (((v) << 21) & BM_ENET_SWI_VLAN_PRIORITY2_P7) +#define BP_ENET_SWI_VLAN_PRIORITY2_P6 18 +#define BM_ENET_SWI_VLAN_PRIORITY2_P6 0x001C0000 +#define BF_ENET_SWI_VLAN_PRIORITY2_P6(v) \ + (((v) << 18) & BM_ENET_SWI_VLAN_PRIORITY2_P6) +#define BP_ENET_SWI_VLAN_PRIORITY2_P5 15 +#define BM_ENET_SWI_VLAN_PRIORITY2_P5 0x00038000 +#define BF_ENET_SWI_VLAN_PRIORITY2_P5(v) \ + (((v) << 15) & BM_ENET_SWI_VLAN_PRIORITY2_P5) +#define BP_ENET_SWI_VLAN_PRIORITY2_P4 12 +#define BM_ENET_SWI_VLAN_PRIORITY2_P4 0x00007000 +#define BF_ENET_SWI_VLAN_PRIORITY2_P4(v) \ + (((v) << 12) & BM_ENET_SWI_VLAN_PRIORITY2_P4) +#define BP_ENET_SWI_VLAN_PRIORITY2_P3 9 +#define BM_ENET_SWI_VLAN_PRIORITY2_P3 0x00000E00 +#define BF_ENET_SWI_VLAN_PRIORITY2_P3(v) \ + (((v) << 9) & BM_ENET_SWI_VLAN_PRIORITY2_P3) +#define BP_ENET_SWI_VLAN_PRIORITY2_P2 6 +#define BM_ENET_SWI_VLAN_PRIORITY2_P2 0x000001C0 +#define BF_ENET_SWI_VLAN_PRIORITY2_P2(v) \ + (((v) << 6) & BM_ENET_SWI_VLAN_PRIORITY2_P2) +#define BP_ENET_SWI_VLAN_PRIORITY2_P1 3 +#define BM_ENET_SWI_VLAN_PRIORITY2_P1 0x00000038 +#define BF_ENET_SWI_VLAN_PRIORITY2_P1(v) \ + (((v) << 3) & BM_ENET_SWI_VLAN_PRIORITY2_P1) +#define BP_ENET_SWI_VLAN_PRIORITY2_P0 0 +#define BM_ENET_SWI_VLAN_PRIORITY2_P0 0x00000007 +#define BF_ENET_SWI_VLAN_PRIORITY2_P0(v) \ + (((v) << 0) & BM_ENET_SWI_VLAN_PRIORITY2_P0) + +#define HW_ENET_SWI_IP_PRIORITY (0x0000813c) + +#define BM_ENET_SWI_IP_PRIORITY_READ 0x80000000 +#define BP_ENET_SWI_IP_PRIORITY_RSRVD0 15 +#define BM_ENET_SWI_IP_PRIORITY_RSRVD0 0x7FFF8000 +#define BF_ENET_SWI_IP_PRIORITY_RSRVD0(v) \ + (((v) << 15) & BM_ENET_SWI_IP_PRIORITY_RSRVD0) +#define BP_ENET_SWI_IP_PRIORITY_PRIORITY_PORT2 13 +#define BM_ENET_SWI_IP_PRIORITY_PRIORITY_PORT2 0x00006000 +#define BF_ENET_SWI_IP_PRIORITY_PRIORITY_PORT2(v) \ + (((v) << 13) & BM_ENET_SWI_IP_PRIORITY_PRIORITY_PORT2) +#define BP_ENET_SWI_IP_PRIORITY_PRIORITY_PORT1 11 +#define BM_ENET_SWI_IP_PRIORITY_PRIORITY_PORT1 0x00001800 +#define BF_ENET_SWI_IP_PRIORITY_PRIORITY_PORT1(v) \ + (((v) << 11) & BM_ENET_SWI_IP_PRIORITY_PRIORITY_PORT1) +#define BP_ENET_SWI_IP_PRIORITY_PRIORITY_PORT0 9 +#define BM_ENET_SWI_IP_PRIORITY_PRIORITY_PORT0 0x00000600 +#define BF_ENET_SWI_IP_PRIORITY_PRIORITY_PORT0(v) \ + (((v) << 9) & BM_ENET_SWI_IP_PRIORITY_PRIORITY_PORT0) +#define BM_ENET_SWI_IP_PRIORITY_IPV4_SELECT 0x00000100 +#define BP_ENET_SWI_IP_PRIORITY_ADDRESS 0 +#define BM_ENET_SWI_IP_PRIORITY_ADDRESS 0x000000FF +#define BF_ENET_SWI_IP_PRIORITY_ADDRESS(v) \ + (((v) << 0) & BM_ENET_SWI_IP_PRIORITY_ADDRESS) + +#define HW_ENET_SWI_PRIORITY_CFG0 (0x0000817c) + +#define BP_ENET_SWI_PRIORITY_CFG0_RSRVD1 7 +#define BM_ENET_SWI_PRIORITY_CFG0_RSRVD1 0xFFFFFF80 +#define BF_ENET_SWI_PRIORITY_CFG0_RSRVD1(v) \ + (((v) << 7) & BM_ENET_SWI_PRIORITY_CFG0_RSRVD1) +#define BP_ENET_SWI_PRIORITY_CFG0_DEFAULT_PRIORITY 4 +#define BM_ENET_SWI_PRIORITY_CFG0_DEFAULT_PRIORITY 0x00000070 +#define BF_ENET_SWI_PRIORITY_CFG0_DEFAULT_PRIORITY(v) \ + (((v) << 4) & BM_ENET_SWI_PRIORITY_CFG0_DEFAULT_PRIORITY) +#define BM_ENET_SWI_PRIORITY_CFG0_RSRVD0 0x00000008 +#define BM_ENET_SWI_PRIORITY_CFG0_MAC_EN 0x00000004 +#define BM_ENET_SWI_PRIORITY_CFG0_IP_EN 0x00000002 +#define BM_ENET_SWI_PRIORITY_CFG0_VLAN_EN 0x00000001 + +#define HW_ENET_SWI_PRIORITY_CFG1 (0x00008180) + +#define BP_ENET_SWI_PRIORITY_CFG1_RSRVD1 7 +#define BM_ENET_SWI_PRIORITY_CFG1_RSRVD1 0xFFFFFF80 +#define BF_ENET_SWI_PRIORITY_CFG1_RSRVD1(v) \ + (((v) << 7) & BM_ENET_SWI_PRIORITY_CFG1_RSRVD1) +#define BP_ENET_SWI_PRIORITY_CFG1_DEFAULT_PRIORITY 4 +#define BM_ENET_SWI_PRIORITY_CFG1_DEFAULT_PRIORITY 0x00000070 +#define BF_ENET_SWI_PRIORITY_CFG1_DEFAULT_PRIORITY(v) \ + (((v) << 4) & BM_ENET_SWI_PRIORITY_CFG1_DEFAULT_PRIORITY) +#define BM_ENET_SWI_PRIORITY_CFG1_RSRVD0 0x00000008 +#define BM_ENET_SWI_PRIORITY_CFG1_MAC_EN 0x00000004 +#define BM_ENET_SWI_PRIORITY_CFG1_IP_EN 0x00000002 +#define BM_ENET_SWI_PRIORITY_CFG1_VLAN_EN 0x00000001 + +#define HW_ENET_SWI_PRIORITY_CFG2 (0x00008184) + +#define BP_ENET_SWI_PRIORITY_CFG2_RSRVD1 7 +#define BM_ENET_SWI_PRIORITY_CFG2_RSRVD1 0xFFFFFF80 +#define BF_ENET_SWI_PRIORITY_CFG2_RSRVD1(v) \ + (((v) << 7) & BM_ENET_SWI_PRIORITY_CFG2_RSRVD1) +#define BP_ENET_SWI_PRIORITY_CFG2_DEFAULT_PRIORITY 4 +#define BM_ENET_SWI_PRIORITY_CFG2_DEFAULT_PRIORITY 0x00000070 +#define BF_ENET_SWI_PRIORITY_CFG2_DEFAULT_PRIORITY(v) \ + (((v) << 4) & BM_ENET_SWI_PRIORITY_CFG2_DEFAULT_PRIORITY) +#define BM_ENET_SWI_PRIORITY_CFG2_RSRVD0 0x00000008 +#define BM_ENET_SWI_PRIORITY_CFG2_MAC_EN 0x00000004 +#define BM_ENET_SWI_PRIORITY_CFG2_IP_EN 0x00000002 +#define BM_ENET_SWI_PRIORITY_CFG2_VLAN_EN 0x00000001 + +#define HW_ENET_SWI_SYSTEM_TAGINFO0 (0x000081fc) + +#define BP_ENET_SWI_SYSTEM_TAGINFO0_RSRVD0 16 +#define BM_ENET_SWI_SYSTEM_TAGINFO0_RSRVD0 0xFFFF0000 +#define BF_ENET_SWI_SYSTEM_TAGINFO0_RSRVD0(v) \ + (((v) << 16) & BM_ENET_SWI_SYSTEM_TAGINFO0_RSRVD0) +#define BP_ENET_SWI_SYSTEM_TAGINFO0_SYSTEM_TAGINFO0 0 +#define BM_ENET_SWI_SYSTEM_TAGINFO0_SYSTEM_TAGINFO0 0x0000FFFF +#define BF_ENET_SWI_SYSTEM_TAGINFO0_SYSTEM_TAGINFO0(v) \ + (((v) << 0) & BM_ENET_SWI_SYSTEM_TAGINFO0_SYSTEM_TAGINFO0) + +#define HW_ENET_SWI_SYSTEM_TAGINFO1 (0x00008200) + +#define BP_ENET_SWI_SYSTEM_TAGINFO1_RSRVD0 16 +#define BM_ENET_SWI_SYSTEM_TAGINFO1_RSRVD0 0xFFFF0000 +#define BF_ENET_SWI_SYSTEM_TAGINFO1_RSRVD0(v) \ + (((v) << 16) & BM_ENET_SWI_SYSTEM_TAGINFO1_RSRVD0) +#define BP_ENET_SWI_SYSTEM_TAGINFO1_SYSTEM_TAGINFO0 0 +#define BM_ENET_SWI_SYSTEM_TAGINFO1_SYSTEM_TAGINFO0 0x0000FFFF +#define BF_ENET_SWI_SYSTEM_TAGINFO1_SYSTEM_TAGINFO0(v) \ + (((v) << 0) & BM_ENET_SWI_SYSTEM_TAGINFO1_SYSTEM_TAGINFO0) + +#define HW_ENET_SWI_SYSTEM_TAGINFO2 (0x00008204) + +#define BP_ENET_SWI_SYSTEM_TAGINFO2_RSRVD0 16 +#define BM_ENET_SWI_SYSTEM_TAGINFO2_RSRVD0 0xFFFF0000 +#define BF_ENET_SWI_SYSTEM_TAGINFO2_RSRVD0(v) \ + (((v) << 16) & BM_ENET_SWI_SYSTEM_TAGINFO2_RSRVD0) +#define BP_ENET_SWI_SYSTEM_TAGINFO2_SYSTEM_TAGINFO0 0 +#define BM_ENET_SWI_SYSTEM_TAGINFO2_SYSTEM_TAGINFO0 0x0000FFFF +#define BF_ENET_SWI_SYSTEM_TAGINFO2_SYSTEM_TAGINFO0(v) \ + (((v) << 0) & BM_ENET_SWI_SYSTEM_TAGINFO2_SYSTEM_TAGINFO0) + +#define HW_ENET_SWI_VLAN_RES_TABLE_0 (0x0000827c) + +#define BP_ENET_SWI_VLAN_RES_TABLE_0_RSRVD0 15 +#define BM_ENET_SWI_VLAN_RES_TABLE_0_RSRVD0 0xFFFF8000 +#define BF_ENET_SWI_VLAN_RES_TABLE_0_RSRVD0(v) \ + (((v) << 15) & BM_ENET_SWI_VLAN_RES_TABLE_0_RSRVD0) +#define BP_ENET_SWI_VLAN_RES_TABLE_0_VLAN_ID_0 3 +#define BM_ENET_SWI_VLAN_RES_TABLE_0_VLAN_ID_0 0x00007FF8 +#define BF_ENET_SWI_VLAN_RES_TABLE_0_VLAN_ID_0(v) \ + (((v) << 3) & BM_ENET_SWI_VLAN_RES_TABLE_0_VLAN_ID_0) +#define BM_ENET_SWI_VLAN_RES_TABLE_0_PORT_2 0x00000004 +#define BM_ENET_SWI_VLAN_RES_TABLE_0_PORT_1 0x00000002 +#define BM_ENET_SWI_VLAN_RES_TABLE_0_PORT_0 0x00000001 + +#define HW_ENET_SWI_VLAN_RES_TABLE_1 (0x00008280) + +#define BP_ENET_SWI_VLAN_RES_TABLE_1_RSRVD0 15 +#define BM_ENET_SWI_VLAN_RES_TABLE_1_RSRVD0 0xFFFF8000 +#define BF_ENET_SWI_VLAN_RES_TABLE_1_RSRVD0(v) \ + (((v) << 15) & BM_ENET_SWI_VLAN_RES_TABLE_1_RSRVD0) +#define BP_ENET_SWI_VLAN_RES_TABLE_1_VLAN_ID_1 3 +#define BM_ENET_SWI_VLAN_RES_TABLE_1_VLAN_ID_1 0x00007FF8 +#define BF_ENET_SWI_VLAN_RES_TABLE_1_VLAN_ID_1(v) \ + (((v) << 3) & BM_ENET_SWI_VLAN_RES_TABLE_1_VLAN_ID_1) +#define BM_ENET_SWI_VLAN_RES_TABLE_1_PORT_2 0x00000004 +#define BM_ENET_SWI_VLAN_RES_TABLE_1_PORT_1 0x00000002 +#define BM_ENET_SWI_VLAN_RES_TABLE_1_PORT_0 0x00000001 + +#define HW_ENET_SWI_VLAN_RES_TABLE_2 (0x00008284) + +#define BP_ENET_SWI_VLAN_RES_TABLE_2_RSRVD0 15 +#define BM_ENET_SWI_VLAN_RES_TABLE_2_RSRVD0 0xFFFF8000 +#define BF_ENET_SWI_VLAN_RES_TABLE_2_RSRVD0(v) \ + (((v) << 15) & BM_ENET_SWI_VLAN_RES_TABLE_2_RSRVD0) +#define BP_ENET_SWI_VLAN_RES_TABLE_2_VLAN_ID_2 3 +#define BM_ENET_SWI_VLAN_RES_TABLE_2_VLAN_ID_2 0x00007FF8 +#define BF_ENET_SWI_VLAN_RES_TABLE_2_VLAN_ID_2(v) \ + (((v) << 3) & BM_ENET_SWI_VLAN_RES_TABLE_2_VLAN_ID_2) +#define BM_ENET_SWI_VLAN_RES_TABLE_2_PORT_2 0x00000004 +#define BM_ENET_SWI_VLAN_RES_TABLE_2_PORT_1 0x00000002 +#define BM_ENET_SWI_VLAN_RES_TABLE_2_PORT_0 0x00000001 + +#define HW_ENET_SWI_VLAN_RES_TABLE_3 (0x00008288) + +#define BP_ENET_SWI_VLAN_RES_TABLE_3_RSRVD0 15 +#define BM_ENET_SWI_VLAN_RES_TABLE_3_RSRVD0 0xFFFF8000 +#define BF_ENET_SWI_VLAN_RES_TABLE_3_RSRVD0(v) \ + (((v) << 15) & BM_ENET_SWI_VLAN_RES_TABLE_3_RSRVD0) +#define BP_ENET_SWI_VLAN_RES_TABLE_3_VLAN_ID_3 3 +#define BM_ENET_SWI_VLAN_RES_TABLE_3_VLAN_ID_3 0x00007FF8 +#define BF_ENET_SWI_VLAN_RES_TABLE_3_VLAN_ID_3(v) \ + (((v) << 3) & BM_ENET_SWI_VLAN_RES_TABLE_3_VLAN_ID_3) +#define BM_ENET_SWI_VLAN_RES_TABLE_3_PORT_2 0x00000004 +#define BM_ENET_SWI_VLAN_RES_TABLE_3_PORT_1 0x00000002 +#define BM_ENET_SWI_VLAN_RES_TABLE_3_PORT_0 0x00000001 + +#define HW_ENET_SWI_VLAN_RES_TABLE_4 (0x0000828c) + +#define BP_ENET_SWI_VLAN_RES_TABLE_4_RSRVD0 15 +#define BM_ENET_SWI_VLAN_RES_TABLE_4_RSRVD0 0xFFFF8000 +#define BF_ENET_SWI_VLAN_RES_TABLE_4_RSRVD0(v) \ + (((v) << 15) & BM_ENET_SWI_VLAN_RES_TABLE_4_RSRVD0) +#define BP_ENET_SWI_VLAN_RES_TABLE_4_VLAN_ID_4 3 +#define BM_ENET_SWI_VLAN_RES_TABLE_4_VLAN_ID_4 0x00007FF8 +#define BF_ENET_SWI_VLAN_RES_TABLE_4_VLAN_ID_4(v) \ + (((v) << 3) & BM_ENET_SWI_VLAN_RES_TABLE_4_VLAN_ID_4) +#define BM_ENET_SWI_VLAN_RES_TABLE_4_PORT_2 0x00000004 +#define BM_ENET_SWI_VLAN_RES_TABLE_4_PORT_1 0x00000002 +#define BM_ENET_SWI_VLAN_RES_TABLE_4_PORT_0 0x00000001 + +#define HW_ENET_SWI_VLAN_RES_TABLE_5 (0x00008290) + +#define BP_ENET_SWI_VLAN_RES_TABLE_5_RSRVD0 15 +#define BM_ENET_SWI_VLAN_RES_TABLE_5_RSRVD0 0xFFFF8000 +#define BF_ENET_SWI_VLAN_RES_TABLE_5_RSRVD0(v) \ + (((v) << 15) & BM_ENET_SWI_VLAN_RES_TABLE_5_RSRVD0) +#define BP_ENET_SWI_VLAN_RES_TABLE_5_VLAN_ID_5 3 +#define BM_ENET_SWI_VLAN_RES_TABLE_5_VLAN_ID_5 0x00007FF8 +#define BF_ENET_SWI_VLAN_RES_TABLE_5_VLAN_ID_5(v) \ + (((v) << 3) & BM_ENET_SWI_VLAN_RES_TABLE_5_VLAN_ID_5) +#define BM_ENET_SWI_VLAN_RES_TABLE_5_PORT_2 0x00000004 +#define BM_ENET_SWI_VLAN_RES_TABLE_5_PORT_1 0x00000002 +#define BM_ENET_SWI_VLAN_RES_TABLE_5_PORT_0 0x00000001 + +#define HW_ENET_SWI_VLAN_RES_TABLE_6 (0x00008294) + +#define BP_ENET_SWI_VLAN_RES_TABLE_6_RSRVD0 15 +#define BM_ENET_SWI_VLAN_RES_TABLE_6_RSRVD0 0xFFFF8000 +#define BF_ENET_SWI_VLAN_RES_TABLE_6_RSRVD0(v) \ + (((v) << 15) & BM_ENET_SWI_VLAN_RES_TABLE_6_RSRVD0) +#define BP_ENET_SWI_VLAN_RES_TABLE_6_VLAN_ID_6 3 +#define BM_ENET_SWI_VLAN_RES_TABLE_6_VLAN_ID_6 0x00007FF8 +#define BF_ENET_SWI_VLAN_RES_TABLE_6_VLAN_ID_6(v) \ + (((v) << 3) & BM_ENET_SWI_VLAN_RES_TABLE_6_VLAN_ID_6) +#define BM_ENET_SWI_VLAN_RES_TABLE_6_PORT_2 0x00000004 +#define BM_ENET_SWI_VLAN_RES_TABLE_6_PORT_1 0x00000002 +#define BM_ENET_SWI_VLAN_RES_TABLE_6_PORT_0 0x00000001 + +#define HW_ENET_SWI_VLAN_RES_TABLE_7 (0x00008298) + +#define BP_ENET_SWI_VLAN_RES_TABLE_7_RSRVD0 15 +#define BM_ENET_SWI_VLAN_RES_TABLE_7_RSRVD0 0xFFFF8000 +#define BF_ENET_SWI_VLAN_RES_TABLE_7_RSRVD0(v) \ + (((v) << 15) & BM_ENET_SWI_VLAN_RES_TABLE_7_RSRVD0) +#define BP_ENET_SWI_VLAN_RES_TABLE_7_VLAN_ID_7 3 +#define BM_ENET_SWI_VLAN_RES_TABLE_7_VLAN_ID_7 0x00007FF8 +#define BF_ENET_SWI_VLAN_RES_TABLE_7_VLAN_ID_7(v) \ + (((v) << 3) & BM_ENET_SWI_VLAN_RES_TABLE_7_VLAN_ID_7) +#define BM_ENET_SWI_VLAN_RES_TABLE_7_PORT_2 0x00000004 +#define BM_ENET_SWI_VLAN_RES_TABLE_7_PORT_1 0x00000002 +#define BM_ENET_SWI_VLAN_RES_TABLE_7_PORT_0 0x00000001 + +#define HW_ENET_SWI_VLAN_RES_TABLE_8 (0x0000829c) + +#define BP_ENET_SWI_VLAN_RES_TABLE_8_RSRVD0 15 +#define BM_ENET_SWI_VLAN_RES_TABLE_8_RSRVD0 0xFFFF8000 +#define BF_ENET_SWI_VLAN_RES_TABLE_8_RSRVD0(v) \ + (((v) << 15) & BM_ENET_SWI_VLAN_RES_TABLE_8_RSRVD0) +#define BP_ENET_SWI_VLAN_RES_TABLE_8_VLAN_ID_8 3 +#define BM_ENET_SWI_VLAN_RES_TABLE_8_VLAN_ID_8 0x00007FF8 +#define BF_ENET_SWI_VLAN_RES_TABLE_8_VLAN_ID_8(v) \ + (((v) << 3) & BM_ENET_SWI_VLAN_RES_TABLE_8_VLAN_ID_8) +#define BM_ENET_SWI_VLAN_RES_TABLE_8_PORT_2 0x00000004 +#define BM_ENET_SWI_VLAN_RES_TABLE_8_PORT_1 0x00000002 +#define BM_ENET_SWI_VLAN_RES_TABLE_8_PORT_0 0x00000001 + +#define HW_ENET_SWI_VLAN_RES_TABLE_9 (0x000082a0) + +#define BP_ENET_SWI_VLAN_RES_TABLE_9_RSRVD0 15 +#define BM_ENET_SWI_VLAN_RES_TABLE_9_RSRVD0 0xFFFF8000 +#define BF_ENET_SWI_VLAN_RES_TABLE_9_RSRVD0(v) \ + (((v) << 15) & BM_ENET_SWI_VLAN_RES_TABLE_9_RSRVD0) +#define BP_ENET_SWI_VLAN_RES_TABLE_9_VLAN_ID_9 3 +#define BM_ENET_SWI_VLAN_RES_TABLE_9_VLAN_ID_9 0x00007FF8 +#define BF_ENET_SWI_VLAN_RES_TABLE_9_VLAN_ID_9(v) \ + (((v) << 3) & BM_ENET_SWI_VLAN_RES_TABLE_9_VLAN_ID_9) +#define BM_ENET_SWI_VLAN_RES_TABLE_9_PORT_2 0x00000004 +#define BM_ENET_SWI_VLAN_RES_TABLE_9_PORT_1 0x00000002 +#define BM_ENET_SWI_VLAN_RES_TABLE_9_PORT_0 0x00000001 + +#define HW_ENET_SWI_VLAN_RES_TABLE_10 (0x000082a4) + +#define BP_ENET_SWI_VLAN_RES_TABLE_10_RSRVD0 15 +#define BM_ENET_SWI_VLAN_RES_TABLE_10_RSRVD0 0xFFFF8000 +#define BF_ENET_SWI_VLAN_RES_TABLE_10_RSRVD0(v) \ + (((v) << 15) & BM_ENET_SWI_VLAN_RES_TABLE_10_RSRVD0) +#define BP_ENET_SWI_VLAN_RES_TABLE_10_VLAN_ID_10 3 +#define BM_ENET_SWI_VLAN_RES_TABLE_10_VLAN_ID_10 0x00007FF8 +#define BF_ENET_SWI_VLAN_RES_TABLE_10_VLAN_ID_10(v) \ + (((v) << 3) & BM_ENET_SWI_VLAN_RES_TABLE_10_VLAN_ID_10) +#define BM_ENET_SWI_VLAN_RES_TABLE_10_PORT_2 0x00000004 +#define BM_ENET_SWI_VLAN_RES_TABLE_10_PORT_1 0x00000002 +#define BM_ENET_SWI_VLAN_RES_TABLE_10_PORT_0 0x00000001 + +#define HW_ENET_SWI_VLAN_RES_TABLE_11 (0x000082a8) + +#define BP_ENET_SWI_VLAN_RES_TABLE_11_RSRVD0 15 +#define BM_ENET_SWI_VLAN_RES_TABLE_11_RSRVD0 0xFFFF8000 +#define BF_ENET_SWI_VLAN_RES_TABLE_11_RSRVD0(v) \ + (((v) << 15) & BM_ENET_SWI_VLAN_RES_TABLE_11_RSRVD0) +#define BP_ENET_SWI_VLAN_RES_TABLE_11_VLAN_ID_11 3 +#define BM_ENET_SWI_VLAN_RES_TABLE_11_VLAN_ID_11 0x00007FF8 +#define BF_ENET_SWI_VLAN_RES_TABLE_11_VLAN_ID_11(v) \ + (((v) << 3) & BM_ENET_SWI_VLAN_RES_TABLE_11_VLAN_ID_11) +#define BM_ENET_SWI_VLAN_RES_TABLE_11_PORT_2 0x00000004 +#define BM_ENET_SWI_VLAN_RES_TABLE_11_PORT_1 0x00000002 +#define BM_ENET_SWI_VLAN_RES_TABLE_11_PORT_0 0x00000001 + +#define HW_ENET_SWI_VLAN_RES_TABLE_12 (0x000082ac) + +#define BP_ENET_SWI_VLAN_RES_TABLE_12_RSRVD0 15 +#define BM_ENET_SWI_VLAN_RES_TABLE_12_RSRVD0 0xFFFF8000 +#define BF_ENET_SWI_VLAN_RES_TABLE_12_RSRVD0(v) \ + (((v) << 15) & BM_ENET_SWI_VLAN_RES_TABLE_12_RSRVD0) +#define BP_ENET_SWI_VLAN_RES_TABLE_12_VLAN_ID_12 3 +#define BM_ENET_SWI_VLAN_RES_TABLE_12_VLAN_ID_12 0x00007FF8 +#define BF_ENET_SWI_VLAN_RES_TABLE_12_VLAN_ID_12(v) \ + (((v) << 3) & BM_ENET_SWI_VLAN_RES_TABLE_12_VLAN_ID_12) +#define BM_ENET_SWI_VLAN_RES_TABLE_12_PORT_2 0x00000004 +#define BM_ENET_SWI_VLAN_RES_TABLE_12_PORT_1 0x00000002 +#define BM_ENET_SWI_VLAN_RES_TABLE_12_PORT_0 0x00000001 + +#define HW_ENET_SWI_VLAN_RES_TABLE_13 (0x000082b0) + +#define BP_ENET_SWI_VLAN_RES_TABLE_13_RSRVD0 15 +#define BM_ENET_SWI_VLAN_RES_TABLE_13_RSRVD0 0xFFFF8000 +#define BF_ENET_SWI_VLAN_RES_TABLE_13_RSRVD0(v) \ + (((v) << 15) & BM_ENET_SWI_VLAN_RES_TABLE_13_RSRVD0) +#define BP_ENET_SWI_VLAN_RES_TABLE_13_VLAN_ID_13 3 +#define BM_ENET_SWI_VLAN_RES_TABLE_13_VLAN_ID_13 0x00007FF8 +#define BF_ENET_SWI_VLAN_RES_TABLE_13_VLAN_ID_13(v) \ + (((v) << 3) & BM_ENET_SWI_VLAN_RES_TABLE_13_VLAN_ID_13) +#define BM_ENET_SWI_VLAN_RES_TABLE_13_PORT_2 0x00000004 +#define BM_ENET_SWI_VLAN_RES_TABLE_13_PORT_1 0x00000002 +#define BM_ENET_SWI_VLAN_RES_TABLE_13_PORT_0 0x00000001 + +#define HW_ENET_SWI_VLAN_RES_TABLE_14 (0x000082b4) + +#define BP_ENET_SWI_VLAN_RES_TABLE_14_RSRVD0 15 +#define BM_ENET_SWI_VLAN_RES_TABLE_14_RSRVD0 0xFFFF8000 +#define BF_ENET_SWI_VLAN_RES_TABLE_14_RSRVD0(v) \ + (((v) << 15) & BM_ENET_SWI_VLAN_RES_TABLE_14_RSRVD0) +#define BP_ENET_SWI_VLAN_RES_TABLE_14_VLAN_ID_14 3 +#define BM_ENET_SWI_VLAN_RES_TABLE_14_VLAN_ID_14 0x00007FF8 +#define BF_ENET_SWI_VLAN_RES_TABLE_14_VLAN_ID_14(v) \ + (((v) << 3) & BM_ENET_SWI_VLAN_RES_TABLE_14_VLAN_ID_14) +#define BM_ENET_SWI_VLAN_RES_TABLE_14_PORT_2 0x00000004 +#define BM_ENET_SWI_VLAN_RES_TABLE_14_PORT_1 0x00000002 +#define BM_ENET_SWI_VLAN_RES_TABLE_14_PORT_0 0x00000001 + +#define HW_ENET_SWI_VLAN_RES_TABLE_15 (0x000082b8) + +#define BP_ENET_SWI_VLAN_RES_TABLE_15_RSRVD0 15 +#define BM_ENET_SWI_VLAN_RES_TABLE_15_RSRVD0 0xFFFF8000 +#define BF_ENET_SWI_VLAN_RES_TABLE_15_RSRVD0(v) \ + (((v) << 15) & BM_ENET_SWI_VLAN_RES_TABLE_15_RSRVD0) +#define BP_ENET_SWI_VLAN_RES_TABLE_15_VLAN_ID_15 3 +#define BM_ENET_SWI_VLAN_RES_TABLE_15_VLAN_ID_15 0x00007FF8 +#define BF_ENET_SWI_VLAN_RES_TABLE_15_VLAN_ID_15(v) \ + (((v) << 3) & BM_ENET_SWI_VLAN_RES_TABLE_15_VLAN_ID_15) +#define BM_ENET_SWI_VLAN_RES_TABLE_15_PORT_2 0x00000004 +#define BM_ENET_SWI_VLAN_RES_TABLE_15_PORT_1 0x00000002 +#define BM_ENET_SWI_VLAN_RES_TABLE_15_PORT_0 0x00000001 + +#define HW_ENET_SWI_VLAN_RES_TABLE_16 (0x000082bc) + +#define BP_ENET_SWI_VLAN_RES_TABLE_16_RSRVD0 15 +#define BM_ENET_SWI_VLAN_RES_TABLE_16_RSRVD0 0xFFFF8000 +#define BF_ENET_SWI_VLAN_RES_TABLE_16_RSRVD0(v) \ + (((v) << 15) & BM_ENET_SWI_VLAN_RES_TABLE_16_RSRVD0) +#define BP_ENET_SWI_VLAN_RES_TABLE_16_VLAN_ID_16 3 +#define BM_ENET_SWI_VLAN_RES_TABLE_16_VLAN_ID_16 0x00007FF8 +#define BF_ENET_SWI_VLAN_RES_TABLE_16_VLAN_ID_16(v) \ + (((v) << 3) & BM_ENET_SWI_VLAN_RES_TABLE_16_VLAN_ID_16) +#define BM_ENET_SWI_VLAN_RES_TABLE_16_PORT_2 0x00000004 +#define BM_ENET_SWI_VLAN_RES_TABLE_16_PORT_1 0x00000002 +#define BM_ENET_SWI_VLAN_RES_TABLE_16_PORT_0 0x00000001 + +#define HW_ENET_SWI_VLAN_RES_TABLE_17 (0x000082c0) + +#define BP_ENET_SWI_VLAN_RES_TABLE_17_RSRVD0 15 +#define BM_ENET_SWI_VLAN_RES_TABLE_17_RSRVD0 0xFFFF8000 +#define BF_ENET_SWI_VLAN_RES_TABLE_17_RSRVD0(v) \ + (((v) << 15) & BM_ENET_SWI_VLAN_RES_TABLE_17_RSRVD0) +#define BP_ENET_SWI_VLAN_RES_TABLE_17_VLAN_ID_17 3 +#define BM_ENET_SWI_VLAN_RES_TABLE_17_VLAN_ID_17 0x00007FF8 +#define BF_ENET_SWI_VLAN_RES_TABLE_17_VLAN_ID_17(v) \ + (((v) << 3) & BM_ENET_SWI_VLAN_RES_TABLE_17_VLAN_ID_17) +#define BM_ENET_SWI_VLAN_RES_TABLE_17_PORT_2 0x00000004 +#define BM_ENET_SWI_VLAN_RES_TABLE_17_PORT_1 0x00000002 +#define BM_ENET_SWI_VLAN_RES_TABLE_17_PORT_0 0x00000001 + +#define HW_ENET_SWI_VLAN_RES_TABLE_18 (0x000082c4) + +#define BP_ENET_SWI_VLAN_RES_TABLE_18_RSRVD0 15 +#define BM_ENET_SWI_VLAN_RES_TABLE_18_RSRVD0 0xFFFF8000 +#define BF_ENET_SWI_VLAN_RES_TABLE_18_RSRVD0(v) \ + (((v) << 15) & BM_ENET_SWI_VLAN_RES_TABLE_18_RSRVD0) +#define BP_ENET_SWI_VLAN_RES_TABLE_18_VLAN_ID_18 3 +#define BM_ENET_SWI_VLAN_RES_TABLE_18_VLAN_ID_18 0x00007FF8 +#define BF_ENET_SWI_VLAN_RES_TABLE_18_VLAN_ID_18(v) \ + (((v) << 3) & BM_ENET_SWI_VLAN_RES_TABLE_18_VLAN_ID_18) +#define BM_ENET_SWI_VLAN_RES_TABLE_18_PORT_2 0x00000004 +#define BM_ENET_SWI_VLAN_RES_TABLE_18_PORT_1 0x00000002 +#define BM_ENET_SWI_VLAN_RES_TABLE_18_PORT_0 0x00000001 + +#define HW_ENET_SWI_VLAN_RES_TABLE_19 (0x000082c8) + +#define BP_ENET_SWI_VLAN_RES_TABLE_19_RSRVD0 15 +#define BM_ENET_SWI_VLAN_RES_TABLE_19_RSRVD0 0xFFFF8000 +#define BF_ENET_SWI_VLAN_RES_TABLE_19_RSRVD0(v) \ + (((v) << 15) & BM_ENET_SWI_VLAN_RES_TABLE_19_RSRVD0) +#define BP_ENET_SWI_VLAN_RES_TABLE_19_VLAN_ID_19 3 +#define BM_ENET_SWI_VLAN_RES_TABLE_19_VLAN_ID_19 0x00007FF8 +#define BF_ENET_SWI_VLAN_RES_TABLE_19_VLAN_ID_19(v) \ + (((v) << 3) & BM_ENET_SWI_VLAN_RES_TABLE_19_VLAN_ID_19) +#define BM_ENET_SWI_VLAN_RES_TABLE_19_PORT_2 0x00000004 +#define BM_ENET_SWI_VLAN_RES_TABLE_19_PORT_1 0x00000002 +#define BM_ENET_SWI_VLAN_RES_TABLE_19_PORT_0 0x00000001 + +#define HW_ENET_SWI_VLAN_RES_TABLE_20 (0x000082cc) + +#define BP_ENET_SWI_VLAN_RES_TABLE_20_RSRVD0 15 +#define BM_ENET_SWI_VLAN_RES_TABLE_20_RSRVD0 0xFFFF8000 +#define BF_ENET_SWI_VLAN_RES_TABLE_20_RSRVD0(v) \ + (((v) << 15) & BM_ENET_SWI_VLAN_RES_TABLE_20_RSRVD0) +#define BP_ENET_SWI_VLAN_RES_TABLE_20_VLAN_ID_20 3 +#define BM_ENET_SWI_VLAN_RES_TABLE_20_VLAN_ID_20 0x00007FF8 +#define BF_ENET_SWI_VLAN_RES_TABLE_20_VLAN_ID_20(v) \ + (((v) << 3) & BM_ENET_SWI_VLAN_RES_TABLE_20_VLAN_ID_20) +#define BM_ENET_SWI_VLAN_RES_TABLE_20_PORT_2 0x00000004 +#define BM_ENET_SWI_VLAN_RES_TABLE_20_PORT_1 0x00000002 +#define BM_ENET_SWI_VLAN_RES_TABLE_20_PORT_0 0x00000001 + +#define HW_ENET_SWI_VLAN_RES_TABLE_21 (0x000082d0) + +#define BP_ENET_SWI_VLAN_RES_TABLE_21_RSRVD0 15 +#define BM_ENET_SWI_VLAN_RES_TABLE_21_RSRVD0 0xFFFF8000 +#define BF_ENET_SWI_VLAN_RES_TABLE_21_RSRVD0(v) \ + (((v) << 15) & BM_ENET_SWI_VLAN_RES_TABLE_21_RSRVD0) +#define BP_ENET_SWI_VLAN_RES_TABLE_21_VLAN_ID_21 3 +#define BM_ENET_SWI_VLAN_RES_TABLE_21_VLAN_ID_21 0x00007FF8 +#define BF_ENET_SWI_VLAN_RES_TABLE_21_VLAN_ID_21(v) \ + (((v) << 3) & BM_ENET_SWI_VLAN_RES_TABLE_21_VLAN_ID_21) +#define BM_ENET_SWI_VLAN_RES_TABLE_21_PORT_2 0x00000004 +#define BM_ENET_SWI_VLAN_RES_TABLE_21_PORT_1 0x00000002 +#define BM_ENET_SWI_VLAN_RES_TABLE_21_PORT_0 0x00000001 + +#define HW_ENET_SWI_VLAN_RES_TABLE_22 (0x000082d4) + +#define BP_ENET_SWI_VLAN_RES_TABLE_22_RSRVD0 15 +#define BM_ENET_SWI_VLAN_RES_TABLE_22_RSRVD0 0xFFFF8000 +#define BF_ENET_SWI_VLAN_RES_TABLE_22_RSRVD0(v) \ + (((v) << 15) & BM_ENET_SWI_VLAN_RES_TABLE_22_RSRVD0) +#define BP_ENET_SWI_VLAN_RES_TABLE_22_VLAN_ID_22 3 +#define BM_ENET_SWI_VLAN_RES_TABLE_22_VLAN_ID_22 0x00007FF8 +#define BF_ENET_SWI_VLAN_RES_TABLE_22_VLAN_ID_22(v) \ + (((v) << 3) & BM_ENET_SWI_VLAN_RES_TABLE_22_VLAN_ID_22) +#define BM_ENET_SWI_VLAN_RES_TABLE_22_PORT_2 0x00000004 +#define BM_ENET_SWI_VLAN_RES_TABLE_22_PORT_1 0x00000002 +#define BM_ENET_SWI_VLAN_RES_TABLE_22_PORT_0 0x00000001 + +#define HW_ENET_SWI_VLAN_RES_TABLE_23 (0x000082d8) + +#define BP_ENET_SWI_VLAN_RES_TABLE_23_RSRVD0 15 +#define BM_ENET_SWI_VLAN_RES_TABLE_23_RSRVD0 0xFFFF8000 +#define BF_ENET_SWI_VLAN_RES_TABLE_23_RSRVD0(v) \ + (((v) << 15) & BM_ENET_SWI_VLAN_RES_TABLE_23_RSRVD0) +#define BP_ENET_SWI_VLAN_RES_TABLE_23_VLAN_ID_23 3 +#define BM_ENET_SWI_VLAN_RES_TABLE_23_VLAN_ID_23 0x00007FF8 +#define BF_ENET_SWI_VLAN_RES_TABLE_23_VLAN_ID_23(v) \ + (((v) << 3) & BM_ENET_SWI_VLAN_RES_TABLE_23_VLAN_ID_23) +#define BM_ENET_SWI_VLAN_RES_TABLE_23_PORT_2 0x00000004 +#define BM_ENET_SWI_VLAN_RES_TABLE_23_PORT_1 0x00000002 +#define BM_ENET_SWI_VLAN_RES_TABLE_23_PORT_0 0x00000001 + +#define HW_ENET_SWI_VLAN_RES_TABLE_24 (0x000082dc) + +#define BP_ENET_SWI_VLAN_RES_TABLE_24_RSRVD0 15 +#define BM_ENET_SWI_VLAN_RES_TABLE_24_RSRVD0 0xFFFF8000 +#define BF_ENET_SWI_VLAN_RES_TABLE_24_RSRVD0(v) \ + (((v) << 15) & BM_ENET_SWI_VLAN_RES_TABLE_24_RSRVD0) +#define BP_ENET_SWI_VLAN_RES_TABLE_24_VLAN_ID_24 3 +#define BM_ENET_SWI_VLAN_RES_TABLE_24_VLAN_ID_24 0x00007FF8 +#define BF_ENET_SWI_VLAN_RES_TABLE_24_VLAN_ID_24(v) \ + (((v) << 3) & BM_ENET_SWI_VLAN_RES_TABLE_24_VLAN_ID_24) +#define BM_ENET_SWI_VLAN_RES_TABLE_24_PORT_2 0x00000004 +#define BM_ENET_SWI_VLAN_RES_TABLE_24_PORT_1 0x00000002 +#define BM_ENET_SWI_VLAN_RES_TABLE_24_PORT_0 0x00000001 + +#define HW_ENET_SWI_VLAN_RES_TABLE_25 (0x000082e0) + +#define BP_ENET_SWI_VLAN_RES_TABLE_25_RSRVD0 15 +#define BM_ENET_SWI_VLAN_RES_TABLE_25_RSRVD0 0xFFFF8000 +#define BF_ENET_SWI_VLAN_RES_TABLE_25_RSRVD0(v) \ + (((v) << 15) & BM_ENET_SWI_VLAN_RES_TABLE_25_RSRVD0) +#define BP_ENET_SWI_VLAN_RES_TABLE_25_VLAN_ID_25 3 +#define BM_ENET_SWI_VLAN_RES_TABLE_25_VLAN_ID_25 0x00007FF8 +#define BF_ENET_SWI_VLAN_RES_TABLE_25_VLAN_ID_25(v) \ + (((v) << 3) & BM_ENET_SWI_VLAN_RES_TABLE_25_VLAN_ID_25) +#define BM_ENET_SWI_VLAN_RES_TABLE_25_PORT_2 0x00000004 +#define BM_ENET_SWI_VLAN_RES_TABLE_25_PORT_1 0x00000002 +#define BM_ENET_SWI_VLAN_RES_TABLE_25_PORT_0 0x00000001 + +#define HW_ENET_SWI_VLAN_RES_TABLE_26 (0x000082e4) + +#define BP_ENET_SWI_VLAN_RES_TABLE_26_RSRVD0 15 +#define BM_ENET_SWI_VLAN_RES_TABLE_26_RSRVD0 0xFFFF8000 +#define BF_ENET_SWI_VLAN_RES_TABLE_26_RSRVD0(v) \ + (((v) << 15) & BM_ENET_SWI_VLAN_RES_TABLE_26_RSRVD0) +#define BP_ENET_SWI_VLAN_RES_TABLE_26_VLAN_ID_26 3 +#define BM_ENET_SWI_VLAN_RES_TABLE_26_VLAN_ID_26 0x00007FF8 +#define BF_ENET_SWI_VLAN_RES_TABLE_26_VLAN_ID_26(v) \ + (((v) << 3) & BM_ENET_SWI_VLAN_RES_TABLE_26_VLAN_ID_26) +#define BM_ENET_SWI_VLAN_RES_TABLE_26_PORT_2 0x00000004 +#define BM_ENET_SWI_VLAN_RES_TABLE_26_PORT_1 0x00000002 +#define BM_ENET_SWI_VLAN_RES_TABLE_26_PORT_0 0x00000001 + +#define HW_ENET_SWI_VLAN_RES_TABLE_27 (0x000082e8) + +#define BP_ENET_SWI_VLAN_RES_TABLE_27_RSRVD0 15 +#define BM_ENET_SWI_VLAN_RES_TABLE_27_RSRVD0 0xFFFF8000 +#define BF_ENET_SWI_VLAN_RES_TABLE_27_RSRVD0(v) \ + (((v) << 15) & BM_ENET_SWI_VLAN_RES_TABLE_27_RSRVD0) +#define BP_ENET_SWI_VLAN_RES_TABLE_27_VLAN_ID_27 3 +#define BM_ENET_SWI_VLAN_RES_TABLE_27_VLAN_ID_27 0x00007FF8 +#define BF_ENET_SWI_VLAN_RES_TABLE_27_VLAN_ID_27(v) \ + (((v) << 3) & BM_ENET_SWI_VLAN_RES_TABLE_27_VLAN_ID_27) +#define BM_ENET_SWI_VLAN_RES_TABLE_27_PORT_2 0x00000004 +#define BM_ENET_SWI_VLAN_RES_TABLE_27_PORT_1 0x00000002 +#define BM_ENET_SWI_VLAN_RES_TABLE_27_PORT_0 0x00000001 + +#define HW_ENET_SWI_VLAN_RES_TABLE_28 (0x000082ec) + +#define BP_ENET_SWI_VLAN_RES_TABLE_28_RSRVD0 15 +#define BM_ENET_SWI_VLAN_RES_TABLE_28_RSRVD0 0xFFFF8000 +#define BF_ENET_SWI_VLAN_RES_TABLE_28_RSRVD0(v) \ + (((v) << 15) & BM_ENET_SWI_VLAN_RES_TABLE_28_RSRVD0) +#define BP_ENET_SWI_VLAN_RES_TABLE_28_VLAN_ID_28 3 +#define BM_ENET_SWI_VLAN_RES_TABLE_28_VLAN_ID_28 0x00007FF8 +#define BF_ENET_SWI_VLAN_RES_TABLE_28_VLAN_ID_28(v) \ + (((v) << 3) & BM_ENET_SWI_VLAN_RES_TABLE_28_VLAN_ID_28) +#define BM_ENET_SWI_VLAN_RES_TABLE_28_PORT_2 0x00000004 +#define BM_ENET_SWI_VLAN_RES_TABLE_28_PORT_1 0x00000002 +#define BM_ENET_SWI_VLAN_RES_TABLE_28_PORT_0 0x00000001 + +#define HW_ENET_SWI_VLAN_RES_TABLE_29 (0x000082f0) + +#define BP_ENET_SWI_VLAN_RES_TABLE_29_RSRVD0 15 +#define BM_ENET_SWI_VLAN_RES_TABLE_29_RSRVD0 0xFFFF8000 +#define BF_ENET_SWI_VLAN_RES_TABLE_29_RSRVD0(v) \ + (((v) << 15) & BM_ENET_SWI_VLAN_RES_TABLE_29_RSRVD0) +#define BP_ENET_SWI_VLAN_RES_TABLE_29_VLAN_ID_29 3 +#define BM_ENET_SWI_VLAN_RES_TABLE_29_VLAN_ID_29 0x00007FF8 +#define BF_ENET_SWI_VLAN_RES_TABLE_29_VLAN_ID_29(v) \ + (((v) << 3) & BM_ENET_SWI_VLAN_RES_TABLE_29_VLAN_ID_29) +#define BM_ENET_SWI_VLAN_RES_TABLE_29_PORT_2 0x00000004 +#define BM_ENET_SWI_VLAN_RES_TABLE_29_PORT_1 0x00000002 +#define BM_ENET_SWI_VLAN_RES_TABLE_29_PORT_0 0x00000001 + +#define HW_ENET_SWI_VLAN_RES_TABLE_30 (0x000082f4) + +#define BP_ENET_SWI_VLAN_RES_TABLE_30_RSRVD0 15 +#define BM_ENET_SWI_VLAN_RES_TABLE_30_RSRVD0 0xFFFF8000 +#define BF_ENET_SWI_VLAN_RES_TABLE_30_RSRVD0(v) \ + (((v) << 15) & BM_ENET_SWI_VLAN_RES_TABLE_30_RSRVD0) +#define BP_ENET_SWI_VLAN_RES_TABLE_30_VLAN_ID_30 3 +#define BM_ENET_SWI_VLAN_RES_TABLE_30_VLAN_ID_30 0x00007FF8 +#define BF_ENET_SWI_VLAN_RES_TABLE_30_VLAN_ID_30(v) \ + (((v) << 3) & BM_ENET_SWI_VLAN_RES_TABLE_30_VLAN_ID_30) +#define BM_ENET_SWI_VLAN_RES_TABLE_30_PORT_2 0x00000004 +#define BM_ENET_SWI_VLAN_RES_TABLE_30_PORT_1 0x00000002 +#define BM_ENET_SWI_VLAN_RES_TABLE_30_PORT_0 0x00000001 + +#define HW_ENET_SWI_VLAN_RES_TABLE_31 (0x000082f8) + +#define BP_ENET_SWI_VLAN_RES_TABLE_31_RSRVD0 15 +#define BM_ENET_SWI_VLAN_RES_TABLE_31_RSRVD0 0xFFFF8000 +#define BF_ENET_SWI_VLAN_RES_TABLE_31_RSRVD0(v) \ + (((v) << 15) & BM_ENET_SWI_VLAN_RES_TABLE_31_RSRVD0) +#define BP_ENET_SWI_VLAN_RES_TABLE_31_VLAN_ID_31 3 +#define BM_ENET_SWI_VLAN_RES_TABLE_31_VLAN_ID_31 0x00007FF8 +#define BF_ENET_SWI_VLAN_RES_TABLE_31_VLAN_ID_31(v) \ + (((v) << 3) & BM_ENET_SWI_VLAN_RES_TABLE_31_VLAN_ID_31) +#define BM_ENET_SWI_VLAN_RES_TABLE_31_PORT_2 0x00000004 +#define BM_ENET_SWI_VLAN_RES_TABLE_31_PORT_1 0x00000002 +#define BM_ENET_SWI_VLAN_RES_TABLE_31_PORT_0 0x00000001 + +#define HW_ENET_SWI_TOTAL_DISC (0x000082fc) + +#define BP_ENET_SWI_TOTAL_DISC_TOTAL_DISC 0 +#define BM_ENET_SWI_TOTAL_DISC_TOTAL_DISC 0xFFFFFFFF +#define BF_ENET_SWI_TOTAL_DISC_TOTAL_DISC(v) (v) + +#define HW_ENET_SWI_TOTAL_BYT_DISC (0x00008300) + +#define BP_ENET_SWI_TOTAL_BYT_DISC_TOTAL_BYT_DISC 0 +#define BM_ENET_SWI_TOTAL_BYT_DISC_TOTAL_BYT_DISC 0xFFFFFFFF +#define BF_ENET_SWI_TOTAL_BYT_DISC_TOTAL_BYT_DISC(v) (v) + +#define HW_ENET_SWI_TOTAL_FRM (0x00008304) + +#define BP_ENET_SWI_TOTAL_FRM_TOTAL_FRM 0 +#define BM_ENET_SWI_TOTAL_FRM_TOTAL_FRM 0xFFFFFFFF +#define BF_ENET_SWI_TOTAL_FRM_TOTAL_FRM(v) (v) + +#define HW_ENET_SWI_TOTAL_BYT_FRM (0x00008308) + +#define BP_ENET_SWI_TOTAL_BYT_FRM_TOTAL_BYT_FRM 0 +#define BM_ENET_SWI_TOTAL_BYT_FRM_TOTAL_BYT_FRM 0xFFFFFFFF +#define BF_ENET_SWI_TOTAL_BYT_FRM_TOTAL_BYT_FRM(v) (v) + +#define HW_ENET_SWI_ODISC0 (0x0000830c) + +#define BP_ENET_SWI_ODISC0_ODISC0 0 +#define BM_ENET_SWI_ODISC0_ODISC0 0xFFFFFFFF +#define BF_ENET_SWI_ODISC0_ODISC0(v) (v) + +#define HW_ENET_SWI_IDISC_VLAN0 (0x00008310) + +#define BP_ENET_SWI_IDISC_VLAN0_IDISC_VLAN0 0 +#define BM_ENET_SWI_IDISC_VLAN0_IDISC_VLAN0 0xFFFFFFFF +#define BF_ENET_SWI_IDISC_VLAN0_IDISC_VLAN0(v) (v) + +#define HW_ENET_SWI_IDISC_UNTAGGED0 (0x00008314) + +#define BP_ENET_SWI_IDISC_UNTAGGED0_IDISC_UNTAGGED0 0 +#define BM_ENET_SWI_IDISC_UNTAGGED0_IDISC_UNTAGGED0 0xFFFFFFFF +#define BF_ENET_SWI_IDISC_UNTAGGED0_IDISC_UNTAGGED0(v) (v) + +#define HW_ENET_SWI_IDISC_BLOCKED0 (0x00008318) + +#define BP_ENET_SWI_IDISC_BLOCKED0_IDISC_BLOCKED0 0 +#define BM_ENET_SWI_IDISC_BLOCKED0_IDISC_BLOCKED0 0xFFFFFFFF +#define BF_ENET_SWI_IDISC_BLOCKED0_IDISC_BLOCKED0(v) (v) + +#define HW_ENET_SWI_ODISC1 (0x0000831c) + +#define BP_ENET_SWI_ODISC1_ODISC1 0 +#define BM_ENET_SWI_ODISC1_ODISC1 0xFFFFFFFF +#define BF_ENET_SWI_ODISC1_ODISC1(v) (v) + +#define HW_ENET_SWI_IDISC_VLAN1 (0x00008320) + +#define BP_ENET_SWI_IDISC_VLAN1_IDISC_VLAN1 0 +#define BM_ENET_SWI_IDISC_VLAN1_IDISC_VLAN1 0xFFFFFFFF +#define BF_ENET_SWI_IDISC_VLAN1_IDISC_VLAN1(v) (v) + +#define HW_ENET_SWI_IDISC_UNTAGGED1 (0x00008324) + +#define BP_ENET_SWI_IDISC_UNTAGGED1_IDISC_UNTAGGED1 0 +#define BM_ENET_SWI_IDISC_UNTAGGED1_IDISC_UNTAGGED1 0xFFFFFFFF +#define BF_ENET_SWI_IDISC_UNTAGGED1_IDISC_UNTAGGED1(v) (v) + +#define HW_ENET_SWI_IDISC_BLOCKED1 (0x00008328) + +#define BP_ENET_SWI_IDISC_BLOCKED1_IDISC_BLOCKED1 0 +#define BM_ENET_SWI_IDISC_BLOCKED1_IDISC_BLOCKED1 0xFFFFFFFF +#define BF_ENET_SWI_IDISC_BLOCKED1_IDISC_BLOCKED1(v) (v) + +#define HW_ENET_SWI_ODISC2 (0x0000832c) + +#define BP_ENET_SWI_ODISC2_ODISC2 0 +#define BM_ENET_SWI_ODISC2_ODISC2 0xFFFFFFFF +#define BF_ENET_SWI_ODISC2_ODISC2(v) (v) + +#define HW_ENET_SWI_IDISC_VLAN2 (0x00008330) + +#define BP_ENET_SWI_IDISC_VLAN2_IDISC_VLAN2 0 +#define BM_ENET_SWI_IDISC_VLAN2_IDISC_VLAN2 0xFFFFFFFF +#define BF_ENET_SWI_IDISC_VLAN2_IDISC_VLAN2(v) (v) + +#define HW_ENET_SWI_IDISC_UNTAGGED2 (0x00008334) + +#define BP_ENET_SWI_IDISC_UNTAGGED2_IDISC_UNTAGGED2 0 +#define BM_ENET_SWI_IDISC_UNTAGGED2_IDISC_UNTAGGED2 0xFFFFFFFF +#define BF_ENET_SWI_IDISC_UNTAGGED2_IDISC_UNTAGGED2(v) (v) + +#define HW_ENET_SWI_IDISC_BLOCKED2 (0x00008338) + +#define BP_ENET_SWI_IDISC_BLOCKED2_IDISC_BLOCKED2 0 +#define BM_ENET_SWI_IDISC_BLOCKED2_IDISC_BLOCKED2 0xFFFFFFFF +#define BF_ENET_SWI_IDISC_BLOCKED2_IDISC_BLOCKED2(v) (v) + +#define HW_ENET_SWI_EIR (0x000083fc) + +#define BP_ENET_SWI_EIR_RSRVD0 10 +#define BM_ENET_SWI_EIR_RSRVD0 0xFFFFFC00 +#define BF_ENET_SWI_EIR_RSRVD0(v) \ + (((v) << 10) & BM_ENET_SWI_EIR_RSRVD0) +#define BM_ENET_SWI_EIR_LRN 0x00000200 +#define BM_ENET_SWI_EIR_OD2 0x00000100 +#define BM_ENET_SWI_EIR_OD1 0x00000080 +#define BM_ENET_SWI_EIR_OD0 0x00000040 +#define BM_ENET_SWI_EIR_QM 0x00000020 +#define BM_ENET_SWI_EIR_TXF 0x00000010 +#define BM_ENET_SWI_EIR_TXB 0x00000008 +#define BM_ENET_SWI_EIR_RXF 0x00000004 +#define BM_ENET_SWI_EIR_RXB 0x00000002 +#define BM_ENET_SWI_EIR_EBERR 0x00000001 + +#define HW_ENET_SWI_EIMR (0x00008400) + +#define BP_ENET_SWI_EIMR_RSRVD0 10 +#define BM_ENET_SWI_EIMR_RSRVD0 0xFFFFFC00 +#define BF_ENET_SWI_EIMR_RSRVD0(v) \ + (((v) << 10) & BM_ENET_SWI_EIMR_RSRVD0) +#define BM_ENET_SWI_EIMR_LRN 0x00000200 +#define BM_ENET_SWI_EIMR_OD2 0x00000100 +#define BM_ENET_SWI_EIMR_OD1 0x00000080 +#define BM_ENET_SWI_EIMR_OD0 0x00000040 +#define BM_ENET_SWI_EIMR_QM 0x00000020 +#define BM_ENET_SWI_EIMR_TXF 0x00000010 +#define BM_ENET_SWI_EIMR_TXB 0x00000008 +#define BM_ENET_SWI_EIMR_RXF 0x00000004 +#define BM_ENET_SWI_EIMR_RXB 0x00000002 +#define BM_ENET_SWI_EIMR_EBERR 0x00000001 + +#define HW_ENET_SWI_ERDSR (0x00008404) + +#define BP_ENET_SWI_ERDSR_ERDSR 2 +#define BM_ENET_SWI_ERDSR_ERDSR 0xFFFFFFFC +#define BF_ENET_SWI_ERDSR_ERDSR(v) \ + (((v) << 2) & BM_ENET_SWI_ERDSR_ERDSR) +#define BP_ENET_SWI_ERDSR_RSRVD0 0 +#define BM_ENET_SWI_ERDSR_RSRVD0 0x00000003 +#define BF_ENET_SWI_ERDSR_RSRVD0(v) \ + (((v) << 0) & BM_ENET_SWI_ERDSR_RSRVD0) + +#define HW_ENET_SWI_ETDSR (0x00008408) + +#define BP_ENET_SWI_ETDSR_ETDSR 2 +#define BM_ENET_SWI_ETDSR_ETDSR 0xFFFFFFFC +#define BF_ENET_SWI_ETDSR_ETDSR(v) \ + (((v) << 2) & BM_ENET_SWI_ETDSR_ETDSR) +#define BP_ENET_SWI_ETDSR_RSRVD0 0 +#define BM_ENET_SWI_ETDSR_RSRVD0 0x00000003 +#define BF_ENET_SWI_ETDSR_RSRVD0(v) \ + (((v) << 0) & BM_ENET_SWI_ETDSR_RSRVD0) + +#define HW_ENET_SWI_EMRBR (0x0000840c) + +#define BP_ENET_SWI_EMRBR_RSRVD1 14 +#define BM_ENET_SWI_EMRBR_RSRVD1 0xFFFFC000 +#define BF_ENET_SWI_EMRBR_RSRVD1(v) \ + (((v) << 14) & BM_ENET_SWI_EMRBR_RSRVD1) +#define BP_ENET_SWI_EMRBR_EMRBR 4 +#define BM_ENET_SWI_EMRBR_EMRBR 0x00003FF0 +#define BF_ENET_SWI_EMRBR_EMRBR(v) \ + (((v) << 4) & BM_ENET_SWI_EMRBR_EMRBR) +#define BP_ENET_SWI_EMRBR_RSRVD0 0 +#define BM_ENET_SWI_EMRBR_RSRVD0 0x0000000F +#define BF_ENET_SWI_EMRBR_RSRVD0(v) \ + (((v) << 0) & BM_ENET_SWI_EMRBR_RSRVD0) + +#define HW_ENET_SWI_RDAR (0x00008410) + +#define BP_ENET_SWI_RDAR_RDAR 0 +#define BM_ENET_SWI_RDAR_RDAR 0xFFFFFFFF +#define BF_ENET_SWI_RDAR_RDAR(v) (v) + +#define HW_ENET_SWI_TDAR (0x00008414) + +#define BP_ENET_SWI_TDAR_TDAR 0 +#define BM_ENET_SWI_TDAR_TDAR 0xFFFFFFFF +#define BF_ENET_SWI_TDAR_TDAR(v) (v) + +#define HW_ENET_SWI_LRN_REC_0 (0x000084fc) + +#define BP_ENET_SWI_LRN_REC_0_LRN_REC_0 0 +#define BM_ENET_SWI_LRN_REC_0_LRN_REC_0 0xFFFFFFFF +#define BF_ENET_SWI_LRN_REC_0_LRN_REC_0(v) (v) + +#define HW_ENET_SWI_LRN_REC_1 (0x00008500) + +#define BP_ENET_SWI_LRN_REC_1_RSRVD0 26 +#define BM_ENET_SWI_LRN_REC_1_RSRVD0 0xFC000000 +#define BF_ENET_SWI_LRN_REC_1_RSRVD0(v) \ + (((v) << 26) & BM_ENET_SWI_LRN_REC_1_RSRVD0) +#define BP_ENET_SWI_LRN_REC_1_SW_PORT 24 +#define BM_ENET_SWI_LRN_REC_1_SW_PORT 0x03000000 +#define BF_ENET_SWI_LRN_REC_1_SW_PORT(v) \ + (((v) << 24) & BM_ENET_SWI_LRN_REC_1_SW_PORT) +#define BP_ENET_SWI_LRN_REC_1_HASH 16 +#define BM_ENET_SWI_LRN_REC_1_HASH 0x00FF0000 +#define BF_ENET_SWI_LRN_REC_1_HASH(v) \ + (((v) << 16) & BM_ENET_SWI_LRN_REC_1_HASH) +#define BP_ENET_SWI_LRN_REC_1_MAC_ADDR1 0 +#define BM_ENET_SWI_LRN_REC_1_MAC_ADDR1 0x0000FFFF +#define BF_ENET_SWI_LRN_REC_1_MAC_ADDR1(v) \ + (((v) << 0) & BM_ENET_SWI_LRN_REC_1_MAC_ADDR1) + +#define HW_ENET_SWI_LRN_STATUS (0x00008504) + +#define BP_ENET_SWI_LRN_STATUS_RSRVD0 1 +#define BM_ENET_SWI_LRN_STATUS_RSRVD0 0xFFFFFFFE +#define BF_ENET_SWI_LRN_STATUS_RSRVD0(v) \ + (((v) << 1) & BM_ENET_SWI_LRN_STATUS_RSRVD0) +#define BM_ENET_SWI_LRN_STATUS_LRN_STATUS 0x00000001 + +#define HW_ENET_SWI_LOOKUP_MEMORY_START (0x0000bffc) + +#define BP_ENET_SWI_LOOKUP_MEMORY_START_MEMORY_DATA 0 +#define BM_ENET_SWI_LOOKUP_MEMORY_START_MEMORY_DATA 0xFFFFFFFF +#define BF_ENET_SWI_LOOKUP_MEMORY_START_MEMORY_DATA(v) (v) + +#define HW_ENET_SWI_LOOKUP_MEMORY_END (0x0000fff8) + +#define BP_ENET_SWI_LOOKUP_MEMORY_END_MEMORY_DATA 0 +#define BM_ENET_SWI_LOOKUP_MEMORY_END_MEMORY_DATA 0xFFFFFFFF +#define BF_ENET_SWI_LOOKUP_MEMORY_END_MEMORY_DATA(v) (v) +#endif /* __ARCH_ARM___ENET_H */ diff --git a/include/asm-arm/arch-mx28/regs-ocotp.h b/include/asm-arm/arch-mx28/regs-ocotp.h new file mode 100644 index 0000000000..7907250116 --- /dev/null +++ b/include/asm-arm/arch-mx28/regs-ocotp.h @@ -0,0 +1,239 @@ +/* + * Freescale OCOTP Register Definitions + * + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * This file is created by xml file. Don't Edit it. + * + * Xml Revision: 1.21 + * Template revision: 26195 + */ + +#ifndef __ARCH_ARM___OCOTP_H +#define __ARCH_ARM___OCOTP_H + + +#define HW_OCOTP_CTRL (0x00000000) +#define HW_OCOTP_CTRL_SET (0x00000004) +#define HW_OCOTP_CTRL_CLR (0x00000008) +#define HW_OCOTP_CTRL_TOG (0x0000000c) + +#define BP_OCOTP_CTRL_WR_UNLOCK 16 +#define BM_OCOTP_CTRL_WR_UNLOCK 0xFFFF0000 +#define BF_OCOTP_CTRL_WR_UNLOCK(v) \ + (((v) << 16) & BM_OCOTP_CTRL_WR_UNLOCK) +#define BV_OCOTP_CTRL_WR_UNLOCK__KEY 0x3E77 +#define BP_OCOTP_CTRL_RSRVD2 14 +#define BM_OCOTP_CTRL_RSRVD2 0x0000C000 +#define BF_OCOTP_CTRL_RSRVD2(v) \ + (((v) << 14) & BM_OCOTP_CTRL_RSRVD2) +#define BM_OCOTP_CTRL_RELOAD_SHADOWS 0x00002000 +#define BM_OCOTP_CTRL_RD_BANK_OPEN 0x00001000 +#define BP_OCOTP_CTRL_RSRVD1 10 +#define BM_OCOTP_CTRL_RSRVD1 0x00000C00 +#define BF_OCOTP_CTRL_RSRVD1(v) \ + (((v) << 10) & BM_OCOTP_CTRL_RSRVD1) +#define BM_OCOTP_CTRL_ERROR 0x00000200 +#define BM_OCOTP_CTRL_BUSY 0x00000100 +#define BP_OCOTP_CTRL_RSRVD0 6 +#define BM_OCOTP_CTRL_RSRVD0 0x000000C0 +#define BF_OCOTP_CTRL_RSRVD0(v) \ + (((v) << 6) & BM_OCOTP_CTRL_RSRVD0) +#define BP_OCOTP_CTRL_ADDR 0 +#define BM_OCOTP_CTRL_ADDR 0x0000003F +#define BF_OCOTP_CTRL_ADDR(v) \ + (((v) << 0) & BM_OCOTP_CTRL_ADDR) + +#define HW_OCOTP_DATA (0x00000010) + +#define BP_OCOTP_DATA_DATA 0 +#define BM_OCOTP_DATA_DATA 0xFFFFFFFF +#define BF_OCOTP_DATA_DATA(v) (v) + +/* + * multi-register-define name HW_OCOTP_CUSTn + * base 0x00000020 + * count 4 + * offset 0x10 + */ +#define HW_OCOTP_CUSTn(n) (0x00000020 + (n) * 0x10) +#define BP_OCOTP_CUSTn_BITS 0 +#define BM_OCOTP_CUSTn_BITS 0xFFFFFFFF +#define BF_OCOTP_CUSTn_BITS(v) (v) + +/* + * multi-register-define name HW_OCOTP_CRYPTOn + * base 0x00000060 + * count 4 + * offset 0x10 + */ +#define HW_OCOTP_CRYPTOn(n) (0x00000060 + (n) * 0x10) +#define BP_OCOTP_CRYPTOn_BITS 0 +#define BM_OCOTP_CRYPTOn_BITS 0xFFFFFFFF +#define BF_OCOTP_CRYPTOn_BITS(v) (v) + +/* + * multi-register-define name HW_OCOTP_HWCAPn + * base 0x000000A0 + * count 6 + * offset 0x10 + */ +#define HW_OCOTP_HWCAPn(n) (0x000000a0 + (n) * 0x10) +#define BP_OCOTP_HWCAPn_BITS 0 +#define BM_OCOTP_HWCAPn_BITS 0xFFFFFFFF +#define BF_OCOTP_HWCAPn_BITS(v) (v) + +#define HW_OCOTP_SWCAP (0x00000100) + +#define BP_OCOTP_SWCAP_BITS 0 +#define BM_OCOTP_SWCAP_BITS 0xFFFFFFFF +#define BF_OCOTP_SWCAP_BITS(v) (v) + +#define HW_OCOTP_CUSTCAP (0x00000110) + +#define BP_OCOTP_CUSTCAP_RSRVD1 3 +#define BM_OCOTP_CUSTCAP_RSRVD1 0xFFFFFFF8 +#define BF_OCOTP_CUSTCAP_RSRVD1(v) \ + (((v) << 3) & BM_OCOTP_CUSTCAP_RSRVD1) +#define BM_OCOTP_CUSTCAP_RTC_XTAL_32768_PRESENT 0x00000004 +#define BM_OCOTP_CUSTCAP_RTC_XTAL_32000_PRESENT 0x00000002 +#define BM_OCOTP_CUSTCAP_RSRVD0 0x00000001 + +#define HW_OCOTP_LOCK (0x00000120) + +#define BM_OCOTP_LOCK_ROM7 0x80000000 +#define BM_OCOTP_LOCK_ROM6 0x40000000 +#define BM_OCOTP_LOCK_ROM5 0x20000000 +#define BM_OCOTP_LOCK_ROM4 0x10000000 +#define BM_OCOTP_LOCK_ROM3 0x08000000 +#define BM_OCOTP_LOCK_ROM2 0x04000000 +#define BM_OCOTP_LOCK_ROM1 0x02000000 +#define BM_OCOTP_LOCK_ROM0 0x01000000 +#define BM_OCOTP_LOCK_HWSW_SHADOW_ALT 0x00800000 +#define BM_OCOTP_LOCK_CRYPTODCP_ALT 0x00400000 +#define BM_OCOTP_LOCK_CRYPTOKEY_ALT 0x00200000 +#define BM_OCOTP_LOCK_PIN 0x00100000 +#define BM_OCOTP_LOCK_OPS 0x00080000 +#define BM_OCOTP_LOCK_UN2 0x00040000 +#define BM_OCOTP_LOCK_UN1 0x00020000 +#define BM_OCOTP_LOCK_UN0 0x00010000 +#define BM_OCOTP_LOCK_SRK 0x00008000 +#define BP_OCOTP_LOCK_UNALLOCATED 12 +#define BM_OCOTP_LOCK_UNALLOCATED 0x00007000 +#define BF_OCOTP_LOCK_UNALLOCATED(v) \ + (((v) << 12) & BM_OCOTP_LOCK_UNALLOCATED) +#define BM_OCOTP_LOCK_SRK_SHADOW 0x00000800 +#define BM_OCOTP_LOCK_ROM_SHADOW 0x00000400 +#define BM_OCOTP_LOCK_CUSTCAP 0x00000200 +#define BM_OCOTP_LOCK_HWSW 0x00000100 +#define BM_OCOTP_LOCK_CUSTCAP_SHADOW 0x00000080 +#define BM_OCOTP_LOCK_HWSW_SHADOW 0x00000040 +#define BM_OCOTP_LOCK_CRYPTODCP 0x00000020 +#define BM_OCOTP_LOCK_CRYPTOKEY 0x00000010 +#define BM_OCOTP_LOCK_CUST3 0x00000008 +#define BM_OCOTP_LOCK_CUST2 0x00000004 +#define BM_OCOTP_LOCK_CUST1 0x00000002 +#define BM_OCOTP_LOCK_CUST0 0x00000001 + +/* + * multi-register-define name HW_OCOTP_OPSn + * base 0x00000130 + * count 4 + * offset 0x10 + */ +#define HW_OCOTP_OPSn(n) (0x00000130 + (n) * 0x10) +#define BP_OCOTP_OPSn_BITS 0 +#define BM_OCOTP_OPSn_BITS 0xFFFFFFFF +#define BF_OCOTP_OPSn_BITS(v) (v) + +/* + * multi-register-define name HW_OCOTP_UNn + * base 0x00000170 + * count 3 + * offset 0x10 + */ +#define HW_OCOTP_UNn(n) (0x00000170 + (n) * 0x10) +#define BP_OCOTP_UNn_BITS 0 +#define BM_OCOTP_UNn_BITS 0xFFFFFFFF +#define BF_OCOTP_UNn_BITS(v) (v) + +/* + * multi-register-define name HW_OCOTP_ROMn + * base 0x000001A0 + * count 8 + * offset 0x10 + */ +#define HW_OCOTP_ROMn(n) (0x000001a0 + (n) * 0x10) +#define BP_OCOTP_ROMn_BOOT_MODE 24 +#define BM_OCOTP_ROMn_BOOT_MODE 0xFF000000 +#define BF_OCOTP_ROMn_BOOT_MODE(v) \ + (((v) << 24) & BM_OCOTP_ROMn_BOOT_MODE) +#define BP_OCOTP_ROMn_SD_MMC_MODE 22 +#define BM_OCOTP_ROMn_SD_MMC_MODE 0x00C00000 +#define BF_OCOTP_ROMn_SD_MMC_MODE(v) \ + (((v) << 22) & BM_OCOTP_ROMn_SD_MMC_MODE) +#define BP_OCOTP_ROMn_SD_POWER_GATE_GPIO 20 +#define BM_OCOTP_ROMn_SD_POWER_GATE_GPIO 0x00300000 +#define BF_OCOTP_ROMn_SD_POWER_GATE_GPIO(v) \ + (((v) << 20) & BM_OCOTP_ROMn_SD_POWER_GATE_GPIO) +#define BP_OCOTP_ROMn_SD_POWER_UP_DELAY 14 +#define BM_OCOTP_ROMn_SD_POWER_UP_DELAY 0x000FC000 +#define BF_OCOTP_ROMn_SD_POWER_UP_DELAY(v) \ + (((v) << 14) & BM_OCOTP_ROMn_SD_POWER_UP_DELAY) +#define BP_OCOTP_ROMn_SD_BUS_WIDTH 12 +#define BM_OCOTP_ROMn_SD_BUS_WIDTH 0x00003000 +#define BF_OCOTP_ROMn_SD_BUS_WIDTH(v) \ + (((v) << 12) & BM_OCOTP_ROMn_SD_BUS_WIDTH) +#define BP_OCOTP_ROMn_SSP_SCK_INDEX 8 +#define BM_OCOTP_ROMn_SSP_SCK_INDEX 0x00000F00 +#define BF_OCOTP_ROMn_SSP_SCK_INDEX(v) \ + (((v) << 8) & BM_OCOTP_ROMn_SSP_SCK_INDEX) +#define BM_OCOTP_ROMn_EMMC_USE_DDR 0x00000080 +#define BM_OCOTP_ROMn_DISABLE_SPI_NOR_FAST_READ 0x00000040 +#define BM_OCOTP_ROMn_ENABLE_USB_BOOT_SERIAL_NUM 0x00000020 +#define BM_OCOTP_ROMn_ENABLE_UNENCRYPTED_BOOT 0x00000010 +#define BM_OCOTP_ROMn_SD_MBR_BOOT 0x00000008 +#define BM_OCOTP_ROMn_RSRVD2 0x00000004 +#define BM_OCOTP_ROMn_RSRVD1 0x00000002 +#define BM_OCOTP_ROMn_RSRVD0 0x00000001 + +/* + * multi-register-define name HW_OCOTP_SRKn + * base 0x00000220 + * count 8 + * offset 0x10 + */ +#define HW_OCOTP_SRKn(n) (0x00000220 + (n) * 0x10) +#define BP_OCOTP_SRKn_BITS 0 +#define BM_OCOTP_SRKn_BITS 0xFFFFFFFF +#define BF_OCOTP_SRKn_BITS(v) (v) + +#define HW_OCOTP_VERSION (0x000002a0) + +#define BP_OCOTP_VERSION_MAJOR 24 +#define BM_OCOTP_VERSION_MAJOR 0xFF000000 +#define BF_OCOTP_VERSION_MAJOR(v) \ + (((v) << 24) & BM_OCOTP_VERSION_MAJOR) +#define BP_OCOTP_VERSION_MINOR 16 +#define BM_OCOTP_VERSION_MINOR 0x00FF0000 +#define BF_OCOTP_VERSION_MINOR(v) \ + (((v) << 16) & BM_OCOTP_VERSION_MINOR) +#define BP_OCOTP_VERSION_STEP 0 +#define BM_OCOTP_VERSION_STEP 0x0000FFFF +#define BF_OCOTP_VERSION_STEP(v) \ + (((v) << 0) & BM_OCOTP_VERSION_STEP) +#endif /* __ARCH_ARM___OCOTP_H */ diff --git a/include/asm-arm/arch-mx28/regs-pinctrl.h b/include/asm-arm/arch-mx28/regs-pinctrl.h new file mode 100644 index 0000000000..c0b9e8df3c --- /dev/null +++ b/include/asm-arm/arch-mx28/regs-pinctrl.h @@ -0,0 +1,2674 @@ +/* + * Freescale PINCTRL Register Definitions + * + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * This file is created by xml file. Don't Edit it. + * + * Xml Revision: 1.19 + * Template revision: 26195 + */ + +#ifndef __ARCH_ARM___PINCTRL_H +#define __ARCH_ARM___PINCTRL_H + + +#define HW_PINCTRL_CTRL 0x00000000 +#define HW_PINCTRL_CTRL_SET 0x00000004 +#define HW_PINCTRL_CTRL_CLR 0x00000008 +#define HW_PINCTRL_CTRL_TOG 0x0000000c + +#define BM_PINCTRL_CTRL_SFTRST 0x80000000 +#define BM_PINCTRL_CTRL_CLKGATE 0x40000000 +#define BP_PINCTRL_CTRL_RSRVD2 25 +#define BM_PINCTRL_CTRL_RSRVD2 0x3E000000 +#define BF_PINCTRL_CTRL_RSRVD2(v) \ + (((v) << 25) & BM_PINCTRL_CTRL_RSRVD2) +#define BM_PINCTRL_CTRL_PRESENT4 0x01000000 +#define BM_PINCTRL_CTRL_PRESENT3 0x00800000 +#define BM_PINCTRL_CTRL_PRESENT2 0x00400000 +#define BM_PINCTRL_CTRL_PRESENT1 0x00200000 +#define BM_PINCTRL_CTRL_PRESENT0 0x00100000 +#define BP_PINCTRL_CTRL_RSRVD1 5 +#define BM_PINCTRL_CTRL_RSRVD1 0x000FFFE0 +#define BF_PINCTRL_CTRL_RSRVD1(v) \ + (((v) << 5) & BM_PINCTRL_CTRL_RSRVD1) +#define BM_PINCTRL_CTRL_IRQOUT4 0x00000010 +#define BM_PINCTRL_CTRL_IRQOUT3 0x00000008 +#define BM_PINCTRL_CTRL_IRQOUT2 0x00000004 +#define BM_PINCTRL_CTRL_IRQOUT1 0x00000002 +#define BM_PINCTRL_CTRL_IRQOUT0 0x00000001 + +#define HW_PINCTRL_MUXSEL0 0x00000100 +#define HW_PINCTRL_MUXSEL0_SET 0x00000104 +#define HW_PINCTRL_MUXSEL0_CLR 0x00000108 +#define HW_PINCTRL_MUXSEL0_TOG 0x0000010c + +#define BP_PINCTRL_MUXSEL0_RSRVD0 16 +#define BM_PINCTRL_MUXSEL0_RSRVD0 0xFFFF0000 +#define BF_PINCTRL_MUXSEL0_RSRVD0(v) \ + (((v) << 16) & BM_PINCTRL_MUXSEL0_RSRVD0) +#define BP_PINCTRL_MUXSEL0_BANK0_PIN07 14 +#define BM_PINCTRL_MUXSEL0_BANK0_PIN07 0x0000C000 +#define BF_PINCTRL_MUXSEL0_BANK0_PIN07(v) \ + (((v) << 14) & BM_PINCTRL_MUXSEL0_BANK0_PIN07) +#define BP_PINCTRL_MUXSEL0_BANK0_PIN06 12 +#define BM_PINCTRL_MUXSEL0_BANK0_PIN06 0x00003000 +#define BF_PINCTRL_MUXSEL0_BANK0_PIN06(v) \ + (((v) << 12) & BM_PINCTRL_MUXSEL0_BANK0_PIN06) +#define BP_PINCTRL_MUXSEL0_BANK0_PIN05 10 +#define BM_PINCTRL_MUXSEL0_BANK0_PIN05 0x00000C00 +#define BF_PINCTRL_MUXSEL0_BANK0_PIN05(v) \ + (((v) << 10) & BM_PINCTRL_MUXSEL0_BANK0_PIN05) +#define BP_PINCTRL_MUXSEL0_BANK0_PIN04 8 +#define BM_PINCTRL_MUXSEL0_BANK0_PIN04 0x00000300 +#define BF_PINCTRL_MUXSEL0_BANK0_PIN04(v) \ + (((v) << 8) & BM_PINCTRL_MUXSEL0_BANK0_PIN04) +#define BP_PINCTRL_MUXSEL0_BANK0_PIN03 6 +#define BM_PINCTRL_MUXSEL0_BANK0_PIN03 0x000000C0 +#define BF_PINCTRL_MUXSEL0_BANK0_PIN03(v) \ + (((v) << 6) & BM_PINCTRL_MUXSEL0_BANK0_PIN03) +#define BP_PINCTRL_MUXSEL0_BANK0_PIN02 4 +#define BM_PINCTRL_MUXSEL0_BANK0_PIN02 0x00000030 +#define BF_PINCTRL_MUXSEL0_BANK0_PIN02(v) \ + (((v) << 4) & BM_PINCTRL_MUXSEL0_BANK0_PIN02) +#define BP_PINCTRL_MUXSEL0_BANK0_PIN01 2 +#define BM_PINCTRL_MUXSEL0_BANK0_PIN01 0x0000000C +#define BF_PINCTRL_MUXSEL0_BANK0_PIN01(v) \ + (((v) << 2) & BM_PINCTRL_MUXSEL0_BANK0_PIN01) +#define BP_PINCTRL_MUXSEL0_BANK0_PIN00 0 +#define BM_PINCTRL_MUXSEL0_BANK0_PIN00 0x00000003 +#define BF_PINCTRL_MUXSEL0_BANK0_PIN00(v) \ + (((v) << 0) & BM_PINCTRL_MUXSEL0_BANK0_PIN00) + +#define HW_PINCTRL_MUXSEL1 0x00000110 +#define HW_PINCTRL_MUXSEL1_SET 0x00000114 +#define HW_PINCTRL_MUXSEL1_CLR 0x00000118 +#define HW_PINCTRL_MUXSEL1_TOG 0x0000011c + +#define BP_PINCTRL_MUXSEL1_RSRVD0 26 +#define BM_PINCTRL_MUXSEL1_RSRVD0 0xFC000000 +#define BF_PINCTRL_MUXSEL1_RSRVD0(v) \ + (((v) << 26) & BM_PINCTRL_MUXSEL1_RSRVD0) +#define BP_PINCTRL_MUXSEL1_BANK0_PIN28 24 +#define BM_PINCTRL_MUXSEL1_BANK0_PIN28 0x03000000 +#define BF_PINCTRL_MUXSEL1_BANK0_PIN28(v) \ + (((v) << 24) & BM_PINCTRL_MUXSEL1_BANK0_PIN28) +#define BP_PINCTRL_MUXSEL1_BANK0_PIN27 22 +#define BM_PINCTRL_MUXSEL1_BANK0_PIN27 0x00C00000 +#define BF_PINCTRL_MUXSEL1_BANK0_PIN27(v) \ + (((v) << 22) & BM_PINCTRL_MUXSEL1_BANK0_PIN27) +#define BP_PINCTRL_MUXSEL1_BANK0_PIN26 20 +#define BM_PINCTRL_MUXSEL1_BANK0_PIN26 0x00300000 +#define BF_PINCTRL_MUXSEL1_BANK0_PIN26(v) \ + (((v) << 20) & BM_PINCTRL_MUXSEL1_BANK0_PIN26) +#define BP_PINCTRL_MUXSEL1_BANK0_PIN25 18 +#define BM_PINCTRL_MUXSEL1_BANK0_PIN25 0x000C0000 +#define BF_PINCTRL_MUXSEL1_BANK0_PIN25(v) \ + (((v) << 18) & BM_PINCTRL_MUXSEL1_BANK0_PIN25) +#define BP_PINCTRL_MUXSEL1_BANK0_PIN24 16 +#define BM_PINCTRL_MUXSEL1_BANK0_PIN24 0x00030000 +#define BF_PINCTRL_MUXSEL1_BANK0_PIN24(v) \ + (((v) << 16) & BM_PINCTRL_MUXSEL1_BANK0_PIN24) +#define BP_PINCTRL_MUXSEL1_BANK0_PIN23 14 +#define BM_PINCTRL_MUXSEL1_BANK0_PIN23 0x0000C000 +#define BF_PINCTRL_MUXSEL1_BANK0_PIN23(v) \ + (((v) << 14) & BM_PINCTRL_MUXSEL1_BANK0_PIN23) +#define BP_PINCTRL_MUXSEL1_BANK0_PIN22 12 +#define BM_PINCTRL_MUXSEL1_BANK0_PIN22 0x00003000 +#define BF_PINCTRL_MUXSEL1_BANK0_PIN22(v) \ + (((v) << 12) & BM_PINCTRL_MUXSEL1_BANK0_PIN22) +#define BP_PINCTRL_MUXSEL1_BANK0_PIN21 10 +#define BM_PINCTRL_MUXSEL1_BANK0_PIN21 0x00000C00 +#define BF_PINCTRL_MUXSEL1_BANK0_PIN21(v) \ + (((v) << 10) & BM_PINCTRL_MUXSEL1_BANK0_PIN21) +#define BP_PINCTRL_MUXSEL1_BANK0_PIN20 8 +#define BM_PINCTRL_MUXSEL1_BANK0_PIN20 0x00000300 +#define BF_PINCTRL_MUXSEL1_BANK0_PIN20(v) \ + (((v) << 8) & BM_PINCTRL_MUXSEL1_BANK0_PIN20) +#define BP_PINCTRL_MUXSEL1_BANK0_PIN19 6 +#define BM_PINCTRL_MUXSEL1_BANK0_PIN19 0x000000C0 +#define BF_PINCTRL_MUXSEL1_BANK0_PIN19(v) \ + (((v) << 6) & BM_PINCTRL_MUXSEL1_BANK0_PIN19) +#define BP_PINCTRL_MUXSEL1_BANK0_PIN18 4 +#define BM_PINCTRL_MUXSEL1_BANK0_PIN18 0x00000030 +#define BF_PINCTRL_MUXSEL1_BANK0_PIN18(v) \ + (((v) << 4) & BM_PINCTRL_MUXSEL1_BANK0_PIN18) +#define BP_PINCTRL_MUXSEL1_BANK0_PIN17 2 +#define BM_PINCTRL_MUXSEL1_BANK0_PIN17 0x0000000C +#define BF_PINCTRL_MUXSEL1_BANK0_PIN17(v) \ + (((v) << 2) & BM_PINCTRL_MUXSEL1_BANK0_PIN17) +#define BP_PINCTRL_MUXSEL1_BANK0_PIN16 0 +#define BM_PINCTRL_MUXSEL1_BANK0_PIN16 0x00000003 +#define BF_PINCTRL_MUXSEL1_BANK0_PIN16(v) \ + (((v) << 0) & BM_PINCTRL_MUXSEL1_BANK0_PIN16) + +#define HW_PINCTRL_MUXSEL2 0x00000120 +#define HW_PINCTRL_MUXSEL2_SET 0x00000124 +#define HW_PINCTRL_MUXSEL2_CLR 0x00000128 +#define HW_PINCTRL_MUXSEL2_TOG 0x0000012c + +#define BP_PINCTRL_MUXSEL2_BANK1_PIN15 30 +#define BM_PINCTRL_MUXSEL2_BANK1_PIN15 0xC0000000 +#define BF_PINCTRL_MUXSEL2_BANK1_PIN15(v) \ + (((v) << 30) & BM_PINCTRL_MUXSEL2_BANK1_PIN15) +#define BP_PINCTRL_MUXSEL2_BANK1_PIN14 28 +#define BM_PINCTRL_MUXSEL2_BANK1_PIN14 0x30000000 +#define BF_PINCTRL_MUXSEL2_BANK1_PIN14(v) \ + (((v) << 28) & BM_PINCTRL_MUXSEL2_BANK1_PIN14) +#define BP_PINCTRL_MUXSEL2_BANK1_PIN13 26 +#define BM_PINCTRL_MUXSEL2_BANK1_PIN13 0x0C000000 +#define BF_PINCTRL_MUXSEL2_BANK1_PIN13(v) \ + (((v) << 26) & BM_PINCTRL_MUXSEL2_BANK1_PIN13) +#define BP_PINCTRL_MUXSEL2_BANK1_PIN12 24 +#define BM_PINCTRL_MUXSEL2_BANK1_PIN12 0x03000000 +#define BF_PINCTRL_MUXSEL2_BANK1_PIN12(v) \ + (((v) << 24) & BM_PINCTRL_MUXSEL2_BANK1_PIN12) +#define BP_PINCTRL_MUXSEL2_BANK1_PIN11 22 +#define BM_PINCTRL_MUXSEL2_BANK1_PIN11 0x00C00000 +#define BF_PINCTRL_MUXSEL2_BANK1_PIN11(v) \ + (((v) << 22) & BM_PINCTRL_MUXSEL2_BANK1_PIN11) +#define BP_PINCTRL_MUXSEL2_BANK1_PIN10 20 +#define BM_PINCTRL_MUXSEL2_BANK1_PIN10 0x00300000 +#define BF_PINCTRL_MUXSEL2_BANK1_PIN10(v) \ + (((v) << 20) & BM_PINCTRL_MUXSEL2_BANK1_PIN10) +#define BP_PINCTRL_MUXSEL2_BANK1_PIN09 18 +#define BM_PINCTRL_MUXSEL2_BANK1_PIN09 0x000C0000 +#define BF_PINCTRL_MUXSEL2_BANK1_PIN09(v) \ + (((v) << 18) & BM_PINCTRL_MUXSEL2_BANK1_PIN09) +#define BP_PINCTRL_MUXSEL2_BANK1_PIN08 16 +#define BM_PINCTRL_MUXSEL2_BANK1_PIN08 0x00030000 +#define BF_PINCTRL_MUXSEL2_BANK1_PIN08(v) \ + (((v) << 16) & BM_PINCTRL_MUXSEL2_BANK1_PIN08) +#define BP_PINCTRL_MUXSEL2_BANK1_PIN07 14 +#define BM_PINCTRL_MUXSEL2_BANK1_PIN07 0x0000C000 +#define BF_PINCTRL_MUXSEL2_BANK1_PIN07(v) \ + (((v) << 14) & BM_PINCTRL_MUXSEL2_BANK1_PIN07) +#define BP_PINCTRL_MUXSEL2_BANK1_PIN06 12 +#define BM_PINCTRL_MUXSEL2_BANK1_PIN06 0x00003000 +#define BF_PINCTRL_MUXSEL2_BANK1_PIN06(v) \ + (((v) << 12) & BM_PINCTRL_MUXSEL2_BANK1_PIN06) +#define BP_PINCTRL_MUXSEL2_BANK1_PIN05 10 +#define BM_PINCTRL_MUXSEL2_BANK1_PIN05 0x00000C00 +#define BF_PINCTRL_MUXSEL2_BANK1_PIN05(v) \ + (((v) << 10) & BM_PINCTRL_MUXSEL2_BANK1_PIN05) +#define BP_PINCTRL_MUXSEL2_BANK1_PIN04 8 +#define BM_PINCTRL_MUXSEL2_BANK1_PIN04 0x00000300 +#define BF_PINCTRL_MUXSEL2_BANK1_PIN04(v) \ + (((v) << 8) & BM_PINCTRL_MUXSEL2_BANK1_PIN04) +#define BP_PINCTRL_MUXSEL2_BANK1_PIN03 6 +#define BM_PINCTRL_MUXSEL2_BANK1_PIN03 0x000000C0 +#define BF_PINCTRL_MUXSEL2_BANK1_PIN03(v) \ + (((v) << 6) & BM_PINCTRL_MUXSEL2_BANK1_PIN03) +#define BP_PINCTRL_MUXSEL2_BANK1_PIN02 4 +#define BM_PINCTRL_MUXSEL2_BANK1_PIN02 0x00000030 +#define BF_PINCTRL_MUXSEL2_BANK1_PIN02(v) \ + (((v) << 4) & BM_PINCTRL_MUXSEL2_BANK1_PIN02) +#define BP_PINCTRL_MUXSEL2_BANK1_PIN01 2 +#define BM_PINCTRL_MUXSEL2_BANK1_PIN01 0x0000000C +#define BF_PINCTRL_MUXSEL2_BANK1_PIN01(v) \ + (((v) << 2) & BM_PINCTRL_MUXSEL2_BANK1_PIN01) +#define BP_PINCTRL_MUXSEL2_BANK1_PIN00 0 +#define BM_PINCTRL_MUXSEL2_BANK1_PIN00 0x00000003 +#define BF_PINCTRL_MUXSEL2_BANK1_PIN00(v) \ + (((v) << 0) & BM_PINCTRL_MUXSEL2_BANK1_PIN00) + +#define HW_PINCTRL_MUXSEL3 0x00000130 +#define HW_PINCTRL_MUXSEL3_SET 0x00000134 +#define HW_PINCTRL_MUXSEL3_CLR 0x00000138 +#define HW_PINCTRL_MUXSEL3_TOG 0x0000013c + +#define BP_PINCTRL_MUXSEL3_BANK1_PIN31 30 +#define BM_PINCTRL_MUXSEL3_BANK1_PIN31 0xC0000000 +#define BF_PINCTRL_MUXSEL3_BANK1_PIN31(v) \ + (((v) << 30) & BM_PINCTRL_MUXSEL3_BANK1_PIN31) +#define BP_PINCTRL_MUXSEL3_BANK1_PIN30 28 +#define BM_PINCTRL_MUXSEL3_BANK1_PIN30 0x30000000 +#define BF_PINCTRL_MUXSEL3_BANK1_PIN30(v) \ + (((v) << 28) & BM_PINCTRL_MUXSEL3_BANK1_PIN30) +#define BP_PINCTRL_MUXSEL3_BANK1_PIN29 26 +#define BM_PINCTRL_MUXSEL3_BANK1_PIN29 0x0C000000 +#define BF_PINCTRL_MUXSEL3_BANK1_PIN29(v) \ + (((v) << 26) & BM_PINCTRL_MUXSEL3_BANK1_PIN29) +#define BP_PINCTRL_MUXSEL3_BANK1_PIN28 24 +#define BM_PINCTRL_MUXSEL3_BANK1_PIN28 0x03000000 +#define BF_PINCTRL_MUXSEL3_BANK1_PIN28(v) \ + (((v) << 24) & BM_PINCTRL_MUXSEL3_BANK1_PIN28) +#define BP_PINCTRL_MUXSEL3_BANK1_PIN27 22 +#define BM_PINCTRL_MUXSEL3_BANK1_PIN27 0x00C00000 +#define BF_PINCTRL_MUXSEL3_BANK1_PIN27(v) \ + (((v) << 22) & BM_PINCTRL_MUXSEL3_BANK1_PIN27) +#define BP_PINCTRL_MUXSEL3_BANK1_PIN26 20 +#define BM_PINCTRL_MUXSEL3_BANK1_PIN26 0x00300000 +#define BF_PINCTRL_MUXSEL3_BANK1_PIN26(v) \ + (((v) << 20) & BM_PINCTRL_MUXSEL3_BANK1_PIN26) +#define BP_PINCTRL_MUXSEL3_BANK1_PIN25 18 +#define BM_PINCTRL_MUXSEL3_BANK1_PIN25 0x000C0000 +#define BF_PINCTRL_MUXSEL3_BANK1_PIN25(v) \ + (((v) << 18) & BM_PINCTRL_MUXSEL3_BANK1_PIN25) +#define BP_PINCTRL_MUXSEL3_BANK1_PIN24 16 +#define BM_PINCTRL_MUXSEL3_BANK1_PIN24 0x00030000 +#define BF_PINCTRL_MUXSEL3_BANK1_PIN24(v) \ + (((v) << 16) & BM_PINCTRL_MUXSEL3_BANK1_PIN24) +#define BP_PINCTRL_MUXSEL3_BANK1_PIN23 14 +#define BM_PINCTRL_MUXSEL3_BANK1_PIN23 0x0000C000 +#define BF_PINCTRL_MUXSEL3_BANK1_PIN23(v) \ + (((v) << 14) & BM_PINCTRL_MUXSEL3_BANK1_PIN23) +#define BP_PINCTRL_MUXSEL3_BANK1_PIN22 12 +#define BM_PINCTRL_MUXSEL3_BANK1_PIN22 0x00003000 +#define BF_PINCTRL_MUXSEL3_BANK1_PIN22(v) \ + (((v) << 12) & BM_PINCTRL_MUXSEL3_BANK1_PIN22) +#define BP_PINCTRL_MUXSEL3_BANK1_PIN21 10 +#define BM_PINCTRL_MUXSEL3_BANK1_PIN21 0x00000C00 +#define BF_PINCTRL_MUXSEL3_BANK1_PIN21(v) \ + (((v) << 10) & BM_PINCTRL_MUXSEL3_BANK1_PIN21) +#define BP_PINCTRL_MUXSEL3_BANK1_PIN20 8 +#define BM_PINCTRL_MUXSEL3_BANK1_PIN20 0x00000300 +#define BF_PINCTRL_MUXSEL3_BANK1_PIN20(v) \ + (((v) << 8) & BM_PINCTRL_MUXSEL3_BANK1_PIN20) +#define BP_PINCTRL_MUXSEL3_BANK1_PIN19 6 +#define BM_PINCTRL_MUXSEL3_BANK1_PIN19 0x000000C0 +#define BF_PINCTRL_MUXSEL3_BANK1_PIN19(v) \ + (((v) << 6) & BM_PINCTRL_MUXSEL3_BANK1_PIN19) +#define BP_PINCTRL_MUXSEL3_BANK1_PIN18 4 +#define BM_PINCTRL_MUXSEL3_BANK1_PIN18 0x00000030 +#define BF_PINCTRL_MUXSEL3_BANK1_PIN18(v) \ + (((v) << 4) & BM_PINCTRL_MUXSEL3_BANK1_PIN18) +#define BP_PINCTRL_MUXSEL3_BANK1_PIN17 2 +#define BM_PINCTRL_MUXSEL3_BANK1_PIN17 0x0000000C +#define BF_PINCTRL_MUXSEL3_BANK1_PIN17(v) \ + (((v) << 2) & BM_PINCTRL_MUXSEL3_BANK1_PIN17) +#define BP_PINCTRL_MUXSEL3_BANK1_PIN16 0 +#define BM_PINCTRL_MUXSEL3_BANK1_PIN16 0x00000003 +#define BF_PINCTRL_MUXSEL3_BANK1_PIN16(v) \ + (((v) << 0) & BM_PINCTRL_MUXSEL3_BANK1_PIN16) + +#define HW_PINCTRL_MUXSEL4 0x00000140 +#define HW_PINCTRL_MUXSEL4_SET 0x00000144 +#define HW_PINCTRL_MUXSEL4_CLR 0x00000148 +#define HW_PINCTRL_MUXSEL4_TOG 0x0000014c + +#define BP_PINCTRL_MUXSEL4_BANK2_PIN15 30 +#define BM_PINCTRL_MUXSEL4_BANK2_PIN15 0xC0000000 +#define BF_PINCTRL_MUXSEL4_BANK2_PIN15(v) \ + (((v) << 30) & BM_PINCTRL_MUXSEL4_BANK2_PIN15) +#define BP_PINCTRL_MUXSEL4_BANK2_PIN14 28 +#define BM_PINCTRL_MUXSEL4_BANK2_PIN14 0x30000000 +#define BF_PINCTRL_MUXSEL4_BANK2_PIN14(v) \ + (((v) << 28) & BM_PINCTRL_MUXSEL4_BANK2_PIN14) +#define BP_PINCTRL_MUXSEL4_BANK2_PIN13 26 +#define BM_PINCTRL_MUXSEL4_BANK2_PIN13 0x0C000000 +#define BF_PINCTRL_MUXSEL4_BANK2_PIN13(v) \ + (((v) << 26) & BM_PINCTRL_MUXSEL4_BANK2_PIN13) +#define BP_PINCTRL_MUXSEL4_BANK2_PIN12 24 +#define BM_PINCTRL_MUXSEL4_BANK2_PIN12 0x03000000 +#define BF_PINCTRL_MUXSEL4_BANK2_PIN12(v) \ + (((v) << 24) & BM_PINCTRL_MUXSEL4_BANK2_PIN12) +#define BP_PINCTRL_MUXSEL4_RSRVD0 22 +#define BM_PINCTRL_MUXSEL4_RSRVD0 0x00C00000 +#define BF_PINCTRL_MUXSEL4_RSRVD0(v) \ + (((v) << 22) & BM_PINCTRL_MUXSEL4_RSRVD0) +#define BP_PINCTRL_MUXSEL4_BANK2_PIN10 20 +#define BM_PINCTRL_MUXSEL4_BANK2_PIN10 0x00300000 +#define BF_PINCTRL_MUXSEL4_BANK2_PIN10(v) \ + (((v) << 20) & BM_PINCTRL_MUXSEL4_BANK2_PIN10) +#define BP_PINCTRL_MUXSEL4_BANK2_PIN09 18 +#define BM_PINCTRL_MUXSEL4_BANK2_PIN09 0x000C0000 +#define BF_PINCTRL_MUXSEL4_BANK2_PIN09(v) \ + (((v) << 18) & BM_PINCTRL_MUXSEL4_BANK2_PIN09) +#define BP_PINCTRL_MUXSEL4_BANK2_PIN08 16 +#define BM_PINCTRL_MUXSEL4_BANK2_PIN08 0x00030000 +#define BF_PINCTRL_MUXSEL4_BANK2_PIN08(v) \ + (((v) << 16) & BM_PINCTRL_MUXSEL4_BANK2_PIN08) +#define BP_PINCTRL_MUXSEL4_BANK2_PIN07 14 +#define BM_PINCTRL_MUXSEL4_BANK2_PIN07 0x0000C000 +#define BF_PINCTRL_MUXSEL4_BANK2_PIN07(v) \ + (((v) << 14) & BM_PINCTRL_MUXSEL4_BANK2_PIN07) +#define BP_PINCTRL_MUXSEL4_BANK2_PIN06 12 +#define BM_PINCTRL_MUXSEL4_BANK2_PIN06 0x00003000 +#define BF_PINCTRL_MUXSEL4_BANK2_PIN06(v) \ + (((v) << 12) & BM_PINCTRL_MUXSEL4_BANK2_PIN06) +#define BP_PINCTRL_MUXSEL4_BANK2_PIN05 10 +#define BM_PINCTRL_MUXSEL4_BANK2_PIN05 0x00000C00 +#define BF_PINCTRL_MUXSEL4_BANK2_PIN05(v) \ + (((v) << 10) & BM_PINCTRL_MUXSEL4_BANK2_PIN05) +#define BP_PINCTRL_MUXSEL4_BANK2_PIN04 8 +#define BM_PINCTRL_MUXSEL4_BANK2_PIN04 0x00000300 +#define BF_PINCTRL_MUXSEL4_BANK2_PIN04(v) \ + (((v) << 8) & BM_PINCTRL_MUXSEL4_BANK2_PIN04) +#define BP_PINCTRL_MUXSEL4_BANK2_PIN03 6 +#define BM_PINCTRL_MUXSEL4_BANK2_PIN03 0x000000C0 +#define BF_PINCTRL_MUXSEL4_BANK2_PIN03(v) \ + (((v) << 6) & BM_PINCTRL_MUXSEL4_BANK2_PIN03) +#define BP_PINCTRL_MUXSEL4_BANK2_PIN02 4 +#define BM_PINCTRL_MUXSEL4_BANK2_PIN02 0x00000030 +#define BF_PINCTRL_MUXSEL4_BANK2_PIN02(v) \ + (((v) << 4) & BM_PINCTRL_MUXSEL4_BANK2_PIN02) +#define BP_PINCTRL_MUXSEL4_BANK2_PIN01 2 +#define BM_PINCTRL_MUXSEL4_BANK2_PIN01 0x0000000C +#define BF_PINCTRL_MUXSEL4_BANK2_PIN01(v) \ + (((v) << 2) & BM_PINCTRL_MUXSEL4_BANK2_PIN01) +#define BP_PINCTRL_MUXSEL4_BANK2_PIN00 0 +#define BM_PINCTRL_MUXSEL4_BANK2_PIN00 0x00000003 +#define BF_PINCTRL_MUXSEL4_BANK2_PIN00(v) \ + (((v) << 0) & BM_PINCTRL_MUXSEL4_BANK2_PIN00) + +#define HW_PINCTRL_MUXSEL5 0x00000150 +#define HW_PINCTRL_MUXSEL5_SET 0x00000154 +#define HW_PINCTRL_MUXSEL5_CLR 0x00000158 +#define HW_PINCTRL_MUXSEL5_TOG 0x0000015c + +#define BP_PINCTRL_MUXSEL5_RSRVD1 24 +#define BM_PINCTRL_MUXSEL5_RSRVD1 0xFF000000 +#define BF_PINCTRL_MUXSEL5_RSRVD1(v) \ + (((v) << 24) & BM_PINCTRL_MUXSEL5_RSRVD1) +#define BP_PINCTRL_MUXSEL5_BANK2_PIN27 22 +#define BM_PINCTRL_MUXSEL5_BANK2_PIN27 0x00C00000 +#define BF_PINCTRL_MUXSEL5_BANK2_PIN27(v) \ + (((v) << 22) & BM_PINCTRL_MUXSEL5_BANK2_PIN27) +#define BP_PINCTRL_MUXSEL5_BANK2_PIN26 20 +#define BM_PINCTRL_MUXSEL5_BANK2_PIN26 0x00300000 +#define BF_PINCTRL_MUXSEL5_BANK2_PIN26(v) \ + (((v) << 20) & BM_PINCTRL_MUXSEL5_BANK2_PIN26) +#define BP_PINCTRL_MUXSEL5_BANK2_PIN25 18 +#define BM_PINCTRL_MUXSEL5_BANK2_PIN25 0x000C0000 +#define BF_PINCTRL_MUXSEL5_BANK2_PIN25(v) \ + (((v) << 18) & BM_PINCTRL_MUXSEL5_BANK2_PIN25) +#define BP_PINCTRL_MUXSEL5_BANK2_PIN24 16 +#define BM_PINCTRL_MUXSEL5_BANK2_PIN24 0x00030000 +#define BF_PINCTRL_MUXSEL5_BANK2_PIN24(v) \ + (((v) << 16) & BM_PINCTRL_MUXSEL5_BANK2_PIN24) +#define BP_PINCTRL_MUXSEL5_RSRVD0 12 +#define BM_PINCTRL_MUXSEL5_RSRVD0 0x0000F000 +#define BF_PINCTRL_MUXSEL5_RSRVD0(v) \ + (((v) << 12) & BM_PINCTRL_MUXSEL5_RSRVD0) +#define BP_PINCTRL_MUXSEL5_BANK2_PIN21 10 +#define BM_PINCTRL_MUXSEL5_BANK2_PIN21 0x00000C00 +#define BF_PINCTRL_MUXSEL5_BANK2_PIN21(v) \ + (((v) << 10) & BM_PINCTRL_MUXSEL5_BANK2_PIN21) +#define BP_PINCTRL_MUXSEL5_BANK2_PIN20 8 +#define BM_PINCTRL_MUXSEL5_BANK2_PIN20 0x00000300 +#define BF_PINCTRL_MUXSEL5_BANK2_PIN20(v) \ + (((v) << 8) & BM_PINCTRL_MUXSEL5_BANK2_PIN20) +#define BP_PINCTRL_MUXSEL5_BANK2_PIN19 6 +#define BM_PINCTRL_MUXSEL5_BANK2_PIN19 0x000000C0 +#define BF_PINCTRL_MUXSEL5_BANK2_PIN19(v) \ + (((v) << 6) & BM_PINCTRL_MUXSEL5_BANK2_PIN19) +#define BP_PINCTRL_MUXSEL5_BANK2_PIN18 4 +#define BM_PINCTRL_MUXSEL5_BANK2_PIN18 0x00000030 +#define BF_PINCTRL_MUXSEL5_BANK2_PIN18(v) \ + (((v) << 4) & BM_PINCTRL_MUXSEL5_BANK2_PIN18) +#define BP_PINCTRL_MUXSEL5_BANK2_PIN17 2 +#define BM_PINCTRL_MUXSEL5_BANK2_PIN17 0x0000000C +#define BF_PINCTRL_MUXSEL5_BANK2_PIN17(v) \ + (((v) << 2) & BM_PINCTRL_MUXSEL5_BANK2_PIN17) +#define BP_PINCTRL_MUXSEL5_BANK2_PIN16 0 +#define BM_PINCTRL_MUXSEL5_BANK2_PIN16 0x00000003 +#define BF_PINCTRL_MUXSEL5_BANK2_PIN16(v) \ + (((v) << 0) & BM_PINCTRL_MUXSEL5_BANK2_PIN16) + +#define HW_PINCTRL_MUXSEL6 0x00000160 +#define HW_PINCTRL_MUXSEL6_SET 0x00000164 +#define HW_PINCTRL_MUXSEL6_CLR 0x00000168 +#define HW_PINCTRL_MUXSEL6_TOG 0x0000016c + +#define BP_PINCTRL_MUXSEL6_BANK3_PIN15 30 +#define BM_PINCTRL_MUXSEL6_BANK3_PIN15 0xC0000000 +#define BF_PINCTRL_MUXSEL6_BANK3_PIN15(v) \ + (((v) << 30) & BM_PINCTRL_MUXSEL6_BANK3_PIN15) +#define BP_PINCTRL_MUXSEL6_BANK3_PIN14 28 +#define BM_PINCTRL_MUXSEL6_BANK3_PIN14 0x30000000 +#define BF_PINCTRL_MUXSEL6_BANK3_PIN14(v) \ + (((v) << 28) & BM_PINCTRL_MUXSEL6_BANK3_PIN14) +#define BP_PINCTRL_MUXSEL6_BANK3_PIN13 26 +#define BM_PINCTRL_MUXSEL6_BANK3_PIN13 0x0C000000 +#define BF_PINCTRL_MUXSEL6_BANK3_PIN13(v) \ + (((v) << 26) & BM_PINCTRL_MUXSEL6_BANK3_PIN13) +#define BP_PINCTRL_MUXSEL6_BANK3_PIN12 24 +#define BM_PINCTRL_MUXSEL6_BANK3_PIN12 0x03000000 +#define BF_PINCTRL_MUXSEL6_BANK3_PIN12(v) \ + (((v) << 24) & BM_PINCTRL_MUXSEL6_BANK3_PIN12) +#define BP_PINCTRL_MUXSEL6_BANK3_PIN11 22 +#define BM_PINCTRL_MUXSEL6_BANK3_PIN11 0x00C00000 +#define BF_PINCTRL_MUXSEL6_BANK3_PIN11(v) \ + (((v) << 22) & BM_PINCTRL_MUXSEL6_BANK3_PIN11) +#define BP_PINCTRL_MUXSEL6_BANK3_PIN10 20 +#define BM_PINCTRL_MUXSEL6_BANK3_PIN10 0x00300000 +#define BF_PINCTRL_MUXSEL6_BANK3_PIN10(v) \ + (((v) << 20) & BM_PINCTRL_MUXSEL6_BANK3_PIN10) +#define BP_PINCTRL_MUXSEL6_BANK3_PIN09 18 +#define BM_PINCTRL_MUXSEL6_BANK3_PIN09 0x000C0000 +#define BF_PINCTRL_MUXSEL6_BANK3_PIN09(v) \ + (((v) << 18) & BM_PINCTRL_MUXSEL6_BANK3_PIN09) +#define BP_PINCTRL_MUXSEL6_BANK3_PIN08 16 +#define BM_PINCTRL_MUXSEL6_BANK3_PIN08 0x00030000 +#define BF_PINCTRL_MUXSEL6_BANK3_PIN08(v) \ + (((v) << 16) & BM_PINCTRL_MUXSEL6_BANK3_PIN08) +#define BP_PINCTRL_MUXSEL6_BANK3_PIN07 14 +#define BM_PINCTRL_MUXSEL6_BANK3_PIN07 0x0000C000 +#define BF_PINCTRL_MUXSEL6_BANK3_PIN07(v) \ + (((v) << 14) & BM_PINCTRL_MUXSEL6_BANK3_PIN07) +#define BP_PINCTRL_MUXSEL6_BANK3_PIN06 12 +#define BM_PINCTRL_MUXSEL6_BANK3_PIN06 0x00003000 +#define BF_PINCTRL_MUXSEL6_BANK3_PIN06(v) \ + (((v) << 12) & BM_PINCTRL_MUXSEL6_BANK3_PIN06) +#define BP_PINCTRL_MUXSEL6_BANK3_PIN05 10 +#define BM_PINCTRL_MUXSEL6_BANK3_PIN05 0x00000C00 +#define BF_PINCTRL_MUXSEL6_BANK3_PIN05(v) \ + (((v) << 10) & BM_PINCTRL_MUXSEL6_BANK3_PIN05) +#define BP_PINCTRL_MUXSEL6_BANK3_PIN04 8 +#define BM_PINCTRL_MUXSEL6_BANK3_PIN04 0x00000300 +#define BF_PINCTRL_MUXSEL6_BANK3_PIN04(v) \ + (((v) << 8) & BM_PINCTRL_MUXSEL6_BANK3_PIN04) +#define BP_PINCTRL_MUXSEL6_BANK3_PIN03 6 +#define BM_PINCTRL_MUXSEL6_BANK3_PIN03 0x000000C0 +#define BF_PINCTRL_MUXSEL6_BANK3_PIN03(v) \ + (((v) << 6) & BM_PINCTRL_MUXSEL6_BANK3_PIN03) +#define BP_PINCTRL_MUXSEL6_BANK3_PIN02 4 +#define BM_PINCTRL_MUXSEL6_BANK3_PIN02 0x00000030 +#define BF_PINCTRL_MUXSEL6_BANK3_PIN02(v) \ + (((v) << 4) & BM_PINCTRL_MUXSEL6_BANK3_PIN02) +#define BP_PINCTRL_MUXSEL6_BANK3_PIN01 2 +#define BM_PINCTRL_MUXSEL6_BANK3_PIN01 0x0000000C +#define BF_PINCTRL_MUXSEL6_BANK3_PIN01(v) \ + (((v) << 2) & BM_PINCTRL_MUXSEL6_BANK3_PIN01) +#define BP_PINCTRL_MUXSEL6_BANK3_PIN00 0 +#define BM_PINCTRL_MUXSEL6_BANK3_PIN00 0x00000003 +#define BF_PINCTRL_MUXSEL6_BANK3_PIN00(v) \ + (((v) << 0) & BM_PINCTRL_MUXSEL6_BANK3_PIN00) + +#define HW_PINCTRL_MUXSEL7 0x00000170 +#define HW_PINCTRL_MUXSEL7_SET 0x00000174 +#define HW_PINCTRL_MUXSEL7_CLR 0x00000178 +#define HW_PINCTRL_MUXSEL7_TOG 0x0000017c + +#define BP_PINCTRL_MUXSEL7_RSRVD1 30 +#define BM_PINCTRL_MUXSEL7_RSRVD1 0xC0000000 +#define BF_PINCTRL_MUXSEL7_RSRVD1(v) \ + (((v) << 30) & BM_PINCTRL_MUXSEL7_RSRVD1) +#define BP_PINCTRL_MUXSEL7_BANK3_PIN30 28 +#define BM_PINCTRL_MUXSEL7_BANK3_PIN30 0x30000000 +#define BF_PINCTRL_MUXSEL7_BANK3_PIN30(v) \ + (((v) << 28) & BM_PINCTRL_MUXSEL7_BANK3_PIN30) +#define BP_PINCTRL_MUXSEL7_BANK3_PIN29 26 +#define BM_PINCTRL_MUXSEL7_BANK3_PIN29 0x0C000000 +#define BF_PINCTRL_MUXSEL7_BANK3_PIN29(v) \ + (((v) << 26) & BM_PINCTRL_MUXSEL7_BANK3_PIN29) +#define BP_PINCTRL_MUXSEL7_BANK3_PIN28 24 +#define BM_PINCTRL_MUXSEL7_BANK3_PIN28 0x03000000 +#define BF_PINCTRL_MUXSEL7_BANK3_PIN28(v) \ + (((v) << 24) & BM_PINCTRL_MUXSEL7_BANK3_PIN28) +#define BP_PINCTRL_MUXSEL7_BANK3_PIN27 22 +#define BM_PINCTRL_MUXSEL7_BANK3_PIN27 0x00C00000 +#define BF_PINCTRL_MUXSEL7_BANK3_PIN27(v) \ + (((v) << 22) & BM_PINCTRL_MUXSEL7_BANK3_PIN27) +#define BP_PINCTRL_MUXSEL7_BANK3_PIN26 20 +#define BM_PINCTRL_MUXSEL7_BANK3_PIN26 0x00300000 +#define BF_PINCTRL_MUXSEL7_BANK3_PIN26(v) \ + (((v) << 20) & BM_PINCTRL_MUXSEL7_BANK3_PIN26) +#define BP_PINCTRL_MUXSEL7_BANK3_PIN25 18 +#define BM_PINCTRL_MUXSEL7_BANK3_PIN25 0x000C0000 +#define BF_PINCTRL_MUXSEL7_BANK3_PIN25(v) \ + (((v) << 18) & BM_PINCTRL_MUXSEL7_BANK3_PIN25) +#define BP_PINCTRL_MUXSEL7_BANK3_PIN24 16 +#define BM_PINCTRL_MUXSEL7_BANK3_PIN24 0x00030000 +#define BF_PINCTRL_MUXSEL7_BANK3_PIN24(v) \ + (((v) << 16) & BM_PINCTRL_MUXSEL7_BANK3_PIN24) +#define BP_PINCTRL_MUXSEL7_BANK3_PIN23 14 +#define BM_PINCTRL_MUXSEL7_BANK3_PIN23 0x0000C000 +#define BF_PINCTRL_MUXSEL7_BANK3_PIN23(v) \ + (((v) << 14) & BM_PINCTRL_MUXSEL7_BANK3_PIN23) +#define BP_PINCTRL_MUXSEL7_BANK3_PIN22 12 +#define BM_PINCTRL_MUXSEL7_BANK3_PIN22 0x00003000 +#define BF_PINCTRL_MUXSEL7_BANK3_PIN22(v) \ + (((v) << 12) & BM_PINCTRL_MUXSEL7_BANK3_PIN22) +#define BP_PINCTRL_MUXSEL7_BANK3_PIN21 10 +#define BM_PINCTRL_MUXSEL7_BANK3_PIN21 0x00000C00 +#define BF_PINCTRL_MUXSEL7_BANK3_PIN21(v) \ + (((v) << 10) & BM_PINCTRL_MUXSEL7_BANK3_PIN21) +#define BP_PINCTRL_MUXSEL7_BANK3_PIN20 8 +#define BM_PINCTRL_MUXSEL7_BANK3_PIN20 0x00000300 +#define BF_PINCTRL_MUXSEL7_BANK3_PIN20(v) \ + (((v) << 8) & BM_PINCTRL_MUXSEL7_BANK3_PIN20) +#define BP_PINCTRL_MUXSEL7_RSRVD0 6 +#define BM_PINCTRL_MUXSEL7_RSRVD0 0x000000C0 +#define BF_PINCTRL_MUXSEL7_RSRVD0(v) \ + (((v) << 6) & BM_PINCTRL_MUXSEL7_RSRVD0) +#define BP_PINCTRL_MUXSEL7_BANK3_PIN18 4 +#define BM_PINCTRL_MUXSEL7_BANK3_PIN18 0x00000030 +#define BF_PINCTRL_MUXSEL7_BANK3_PIN18(v) \ + (((v) << 4) & BM_PINCTRL_MUXSEL7_BANK3_PIN18) +#define BP_PINCTRL_MUXSEL7_BANK3_PIN17 2 +#define BM_PINCTRL_MUXSEL7_BANK3_PIN17 0x0000000C +#define BF_PINCTRL_MUXSEL7_BANK3_PIN17(v) \ + (((v) << 2) & BM_PINCTRL_MUXSEL7_BANK3_PIN17) +#define BP_PINCTRL_MUXSEL7_BANK3_PIN16 0 +#define BM_PINCTRL_MUXSEL7_BANK3_PIN16 0x00000003 +#define BF_PINCTRL_MUXSEL7_BANK3_PIN16(v) \ + (((v) << 0) & BM_PINCTRL_MUXSEL7_BANK3_PIN16) + +#define HW_PINCTRL_MUXSEL8 0x00000180 +#define HW_PINCTRL_MUXSEL8_SET 0x00000184 +#define HW_PINCTRL_MUXSEL8_CLR 0x00000188 +#define HW_PINCTRL_MUXSEL8_TOG 0x0000018c + +#define BP_PINCTRL_MUXSEL8_BANK4_PIN15 30 +#define BM_PINCTRL_MUXSEL8_BANK4_PIN15 0xC0000000 +#define BF_PINCTRL_MUXSEL8_BANK4_PIN15(v) \ + (((v) << 30) & BM_PINCTRL_MUXSEL8_BANK4_PIN15) +#define BP_PINCTRL_MUXSEL8_BANK4_PIN14 28 +#define BM_PINCTRL_MUXSEL8_BANK4_PIN14 0x30000000 +#define BF_PINCTRL_MUXSEL8_BANK4_PIN14(v) \ + (((v) << 28) & BM_PINCTRL_MUXSEL8_BANK4_PIN14) +#define BP_PINCTRL_MUXSEL8_BANK4_PIN13 26 +#define BM_PINCTRL_MUXSEL8_BANK4_PIN13 0x0C000000 +#define BF_PINCTRL_MUXSEL8_BANK4_PIN13(v) \ + (((v) << 26) & BM_PINCTRL_MUXSEL8_BANK4_PIN13) +#define BP_PINCTRL_MUXSEL8_BANK4_PIN12 24 +#define BM_PINCTRL_MUXSEL8_BANK4_PIN12 0x03000000 +#define BF_PINCTRL_MUXSEL8_BANK4_PIN12(v) \ + (((v) << 24) & BM_PINCTRL_MUXSEL8_BANK4_PIN12) +#define BP_PINCTRL_MUXSEL8_BANK4_PIN11 22 +#define BM_PINCTRL_MUXSEL8_BANK4_PIN11 0x00C00000 +#define BF_PINCTRL_MUXSEL8_BANK4_PIN11(v) \ + (((v) << 22) & BM_PINCTRL_MUXSEL8_BANK4_PIN11) +#define BP_PINCTRL_MUXSEL8_BANK4_PIN10 20 +#define BM_PINCTRL_MUXSEL8_BANK4_PIN10 0x00300000 +#define BF_PINCTRL_MUXSEL8_BANK4_PIN10(v) \ + (((v) << 20) & BM_PINCTRL_MUXSEL8_BANK4_PIN10) +#define BP_PINCTRL_MUXSEL8_BANK4_PIN09 18 +#define BM_PINCTRL_MUXSEL8_BANK4_PIN09 0x000C0000 +#define BF_PINCTRL_MUXSEL8_BANK4_PIN09(v) \ + (((v) << 18) & BM_PINCTRL_MUXSEL8_BANK4_PIN09) +#define BP_PINCTRL_MUXSEL8_BANK4_PIN08 16 +#define BM_PINCTRL_MUXSEL8_BANK4_PIN08 0x00030000 +#define BF_PINCTRL_MUXSEL8_BANK4_PIN08(v) \ + (((v) << 16) & BM_PINCTRL_MUXSEL8_BANK4_PIN08) +#define BP_PINCTRL_MUXSEL8_BANK4_PIN07 14 +#define BM_PINCTRL_MUXSEL8_BANK4_PIN07 0x0000C000 +#define BF_PINCTRL_MUXSEL8_BANK4_PIN07(v) \ + (((v) << 14) & BM_PINCTRL_MUXSEL8_BANK4_PIN07) +#define BP_PINCTRL_MUXSEL8_BANK4_PIN06 12 +#define BM_PINCTRL_MUXSEL8_BANK4_PIN06 0x00003000 +#define BF_PINCTRL_MUXSEL8_BANK4_PIN06(v) \ + (((v) << 12) & BM_PINCTRL_MUXSEL8_BANK4_PIN06) +#define BP_PINCTRL_MUXSEL8_BANK4_PIN05 10 +#define BM_PINCTRL_MUXSEL8_BANK4_PIN05 0x00000C00 +#define BF_PINCTRL_MUXSEL8_BANK4_PIN05(v) \ + (((v) << 10) & BM_PINCTRL_MUXSEL8_BANK4_PIN05) +#define BP_PINCTRL_MUXSEL8_BANK4_PIN04 8 +#define BM_PINCTRL_MUXSEL8_BANK4_PIN04 0x00000300 +#define BF_PINCTRL_MUXSEL8_BANK4_PIN04(v) \ + (((v) << 8) & BM_PINCTRL_MUXSEL8_BANK4_PIN04) +#define BP_PINCTRL_MUXSEL8_BANK4_PIN03 6 +#define BM_PINCTRL_MUXSEL8_BANK4_PIN03 0x000000C0 +#define BF_PINCTRL_MUXSEL8_BANK4_PIN03(v) \ + (((v) << 6) & BM_PINCTRL_MUXSEL8_BANK4_PIN03) +#define BP_PINCTRL_MUXSEL8_BANK4_PIN02 4 +#define BM_PINCTRL_MUXSEL8_BANK4_PIN02 0x00000030 +#define BF_PINCTRL_MUXSEL8_BANK4_PIN02(v) \ + (((v) << 4) & BM_PINCTRL_MUXSEL8_BANK4_PIN02) +#define BP_PINCTRL_MUXSEL8_BANK4_PIN01 2 +#define BM_PINCTRL_MUXSEL8_BANK4_PIN01 0x0000000C +#define BF_PINCTRL_MUXSEL8_BANK4_PIN01(v) \ + (((v) << 2) & BM_PINCTRL_MUXSEL8_BANK4_PIN01) +#define BP_PINCTRL_MUXSEL8_BANK4_PIN00 0 +#define BM_PINCTRL_MUXSEL8_BANK4_PIN00 0x00000003 +#define BF_PINCTRL_MUXSEL8_BANK4_PIN00(v) \ + (((v) << 0) & BM_PINCTRL_MUXSEL8_BANK4_PIN00) + +#define HW_PINCTRL_MUXSEL9 0x00000190 +#define HW_PINCTRL_MUXSEL9_SET 0x00000194 +#define HW_PINCTRL_MUXSEL9_CLR 0x00000198 +#define HW_PINCTRL_MUXSEL9_TOG 0x0000019c + +#define BP_PINCTRL_MUXSEL9_RSRVD1 10 +#define BM_PINCTRL_MUXSEL9_RSRVD1 0xFFFFFC00 +#define BF_PINCTRL_MUXSEL9_RSRVD1(v) \ + (((v) << 10) & BM_PINCTRL_MUXSEL9_RSRVD1) +#define BP_PINCTRL_MUXSEL9_BANK4_PIN20 8 +#define BM_PINCTRL_MUXSEL9_BANK4_PIN20 0x00000300 +#define BF_PINCTRL_MUXSEL9_BANK4_PIN20(v) \ + (((v) << 8) & BM_PINCTRL_MUXSEL9_BANK4_PIN20) +#define BP_PINCTRL_MUXSEL9_RSRVD0 2 +#define BM_PINCTRL_MUXSEL9_RSRVD0 0x000000FC +#define BF_PINCTRL_MUXSEL9_RSRVD0(v) \ + (((v) << 2) & BM_PINCTRL_MUXSEL9_RSRVD0) +#define BP_PINCTRL_MUXSEL9_BANK4_PIN16 0 +#define BM_PINCTRL_MUXSEL9_BANK4_PIN16 0x00000003 +#define BF_PINCTRL_MUXSEL9_BANK4_PIN16(v) \ + (((v) << 0) & BM_PINCTRL_MUXSEL9_BANK4_PIN16) + +#define HW_PINCTRL_MUXSEL10 0x000001a0 +#define HW_PINCTRL_MUXSEL10_SET 0x000001a4 +#define HW_PINCTRL_MUXSEL10_CLR 0x000001a8 +#define HW_PINCTRL_MUXSEL10_TOG 0x000001ac + +#define BP_PINCTRL_MUXSEL10_BANK5_PIN15 30 +#define BM_PINCTRL_MUXSEL10_BANK5_PIN15 0xC0000000 +#define BF_PINCTRL_MUXSEL10_BANK5_PIN15(v) \ + (((v) << 30) & BM_PINCTRL_MUXSEL10_BANK5_PIN15) +#define BP_PINCTRL_MUXSEL10_BANK5_PIN14 28 +#define BM_PINCTRL_MUXSEL10_BANK5_PIN14 0x30000000 +#define BF_PINCTRL_MUXSEL10_BANK5_PIN14(v) \ + (((v) << 28) & BM_PINCTRL_MUXSEL10_BANK5_PIN14) +#define BP_PINCTRL_MUXSEL10_BANK5_PIN13 26 +#define BM_PINCTRL_MUXSEL10_BANK5_PIN13 0x0C000000 +#define BF_PINCTRL_MUXSEL10_BANK5_PIN13(v) \ + (((v) << 26) & BM_PINCTRL_MUXSEL10_BANK5_PIN13) +#define BP_PINCTRL_MUXSEL10_BANK5_PIN12 24 +#define BM_PINCTRL_MUXSEL10_BANK5_PIN12 0x03000000 +#define BF_PINCTRL_MUXSEL10_BANK5_PIN12(v) \ + (((v) << 24) & BM_PINCTRL_MUXSEL10_BANK5_PIN12) +#define BP_PINCTRL_MUXSEL10_BANK5_PIN11 22 +#define BM_PINCTRL_MUXSEL10_BANK5_PIN11 0x00C00000 +#define BF_PINCTRL_MUXSEL10_BANK5_PIN11(v) \ + (((v) << 22) & BM_PINCTRL_MUXSEL10_BANK5_PIN11) +#define BP_PINCTRL_MUXSEL10_BANK5_PIN10 20 +#define BM_PINCTRL_MUXSEL10_BANK5_PIN10 0x00300000 +#define BF_PINCTRL_MUXSEL10_BANK5_PIN10(v) \ + (((v) << 20) & BM_PINCTRL_MUXSEL10_BANK5_PIN10) +#define BP_PINCTRL_MUXSEL10_BANK5_PIN09 18 +#define BM_PINCTRL_MUXSEL10_BANK5_PIN09 0x000C0000 +#define BF_PINCTRL_MUXSEL10_BANK5_PIN09(v) \ + (((v) << 18) & BM_PINCTRL_MUXSEL10_BANK5_PIN09) +#define BP_PINCTRL_MUXSEL10_BANK5_PIN08 16 +#define BM_PINCTRL_MUXSEL10_BANK5_PIN08 0x00030000 +#define BF_PINCTRL_MUXSEL10_BANK5_PIN08(v) \ + (((v) << 16) & BM_PINCTRL_MUXSEL10_BANK5_PIN08) +#define BP_PINCTRL_MUXSEL10_BANK5_PIN07 14 +#define BM_PINCTRL_MUXSEL10_BANK5_PIN07 0x0000C000 +#define BF_PINCTRL_MUXSEL10_BANK5_PIN07(v) \ + (((v) << 14) & BM_PINCTRL_MUXSEL10_BANK5_PIN07) +#define BP_PINCTRL_MUXSEL10_BANK5_PIN06 12 +#define BM_PINCTRL_MUXSEL10_BANK5_PIN06 0x00003000 +#define BF_PINCTRL_MUXSEL10_BANK5_PIN06(v) \ + (((v) << 12) & BM_PINCTRL_MUXSEL10_BANK5_PIN06) +#define BP_PINCTRL_MUXSEL10_BANK5_PIN05 10 +#define BM_PINCTRL_MUXSEL10_BANK5_PIN05 0x00000C00 +#define BF_PINCTRL_MUXSEL10_BANK5_PIN05(v) \ + (((v) << 10) & BM_PINCTRL_MUXSEL10_BANK5_PIN05) +#define BP_PINCTRL_MUXSEL10_BANK5_PIN04 8 +#define BM_PINCTRL_MUXSEL10_BANK5_PIN04 0x00000300 +#define BF_PINCTRL_MUXSEL10_BANK5_PIN04(v) \ + (((v) << 8) & BM_PINCTRL_MUXSEL10_BANK5_PIN04) +#define BP_PINCTRL_MUXSEL10_BANK5_PIN03 6 +#define BM_PINCTRL_MUXSEL10_BANK5_PIN03 0x000000C0 +#define BF_PINCTRL_MUXSEL10_BANK5_PIN03(v) \ + (((v) << 6) & BM_PINCTRL_MUXSEL10_BANK5_PIN03) +#define BP_PINCTRL_MUXSEL10_BANK5_PIN02 4 +#define BM_PINCTRL_MUXSEL10_BANK5_PIN02 0x00000030 +#define BF_PINCTRL_MUXSEL10_BANK5_PIN02(v) \ + (((v) << 4) & BM_PINCTRL_MUXSEL10_BANK5_PIN02) +#define BP_PINCTRL_MUXSEL10_BANK5_PIN01 2 +#define BM_PINCTRL_MUXSEL10_BANK5_PIN01 0x0000000C +#define BF_PINCTRL_MUXSEL10_BANK5_PIN01(v) \ + (((v) << 2) & BM_PINCTRL_MUXSEL10_BANK5_PIN01) +#define BP_PINCTRL_MUXSEL10_BANK5_PIN00 0 +#define BM_PINCTRL_MUXSEL10_BANK5_PIN00 0x00000003 +#define BF_PINCTRL_MUXSEL10_BANK5_PIN00(v) \ + (((v) << 0) & BM_PINCTRL_MUXSEL10_BANK5_PIN00) + +#define HW_PINCTRL_MUXSEL11 0x000001b0 +#define HW_PINCTRL_MUXSEL11_SET 0x000001b4 +#define HW_PINCTRL_MUXSEL11_CLR 0x000001b8 +#define HW_PINCTRL_MUXSEL11_TOG 0x000001bc + +#define BP_PINCTRL_MUXSEL11_RSRVD1 22 +#define BM_PINCTRL_MUXSEL11_RSRVD1 0xFFC00000 +#define BF_PINCTRL_MUXSEL11_RSRVD1(v) \ + (((v) << 22) & BM_PINCTRL_MUXSEL11_RSRVD1) +#define BP_PINCTRL_MUXSEL11_BANK5_PIN26 20 +#define BM_PINCTRL_MUXSEL11_BANK5_PIN26 0x00300000 +#define BF_PINCTRL_MUXSEL11_BANK5_PIN26(v) \ + (((v) << 20) & BM_PINCTRL_MUXSEL11_BANK5_PIN26) +#define BP_PINCTRL_MUXSEL11_RSRVD0 16 +#define BM_PINCTRL_MUXSEL11_RSRVD0 0x000F0000 +#define BF_PINCTRL_MUXSEL11_RSRVD0(v) \ + (((v) << 16) & BM_PINCTRL_MUXSEL11_RSRVD0) +#define BP_PINCTRL_MUXSEL11_BANK5_PIN23 14 +#define BM_PINCTRL_MUXSEL11_BANK5_PIN23 0x0000C000 +#define BF_PINCTRL_MUXSEL11_BANK5_PIN23(v) \ + (((v) << 14) & BM_PINCTRL_MUXSEL11_BANK5_PIN23) +#define BP_PINCTRL_MUXSEL11_BANK5_PIN22 12 +#define BM_PINCTRL_MUXSEL11_BANK5_PIN22 0x00003000 +#define BF_PINCTRL_MUXSEL11_BANK5_PIN22(v) \ + (((v) << 12) & BM_PINCTRL_MUXSEL11_BANK5_PIN22) +#define BP_PINCTRL_MUXSEL11_BANK5_PIN21 10 +#define BM_PINCTRL_MUXSEL11_BANK5_PIN21 0x00000C00 +#define BF_PINCTRL_MUXSEL11_BANK5_PIN21(v) \ + (((v) << 10) & BM_PINCTRL_MUXSEL11_BANK5_PIN21) +#define BP_PINCTRL_MUXSEL11_BANK5_PIN20 8 +#define BM_PINCTRL_MUXSEL11_BANK5_PIN20 0x00000300 +#define BF_PINCTRL_MUXSEL11_BANK5_PIN20(v) \ + (((v) << 8) & BM_PINCTRL_MUXSEL11_BANK5_PIN20) +#define BP_PINCTRL_MUXSEL11_BANK5_PIN19 6 +#define BM_PINCTRL_MUXSEL11_BANK5_PIN19 0x000000C0 +#define BF_PINCTRL_MUXSEL11_BANK5_PIN19(v) \ + (((v) << 6) & BM_PINCTRL_MUXSEL11_BANK5_PIN19) +#define BP_PINCTRL_MUXSEL11_BANK5_PIN18 4 +#define BM_PINCTRL_MUXSEL11_BANK5_PIN18 0x00000030 +#define BF_PINCTRL_MUXSEL11_BANK5_PIN18(v) \ + (((v) << 4) & BM_PINCTRL_MUXSEL11_BANK5_PIN18) +#define BP_PINCTRL_MUXSEL11_BANK5_PIN17 2 +#define BM_PINCTRL_MUXSEL11_BANK5_PIN17 0x0000000C +#define BF_PINCTRL_MUXSEL11_BANK5_PIN17(v) \ + (((v) << 2) & BM_PINCTRL_MUXSEL11_BANK5_PIN17) +#define BP_PINCTRL_MUXSEL11_BANK5_PIN16 0 +#define BM_PINCTRL_MUXSEL11_BANK5_PIN16 0x00000003 +#define BF_PINCTRL_MUXSEL11_BANK5_PIN16(v) \ + (((v) << 0) & BM_PINCTRL_MUXSEL11_BANK5_PIN16) + +#define HW_PINCTRL_MUXSEL12 0x000001c0 +#define HW_PINCTRL_MUXSEL12_SET 0x000001c4 +#define HW_PINCTRL_MUXSEL12_CLR 0x000001c8 +#define HW_PINCTRL_MUXSEL12_TOG 0x000001cc + +#define BP_PINCTRL_MUXSEL12_RSRVD0 30 +#define BM_PINCTRL_MUXSEL12_RSRVD0 0xC0000000 +#define BF_PINCTRL_MUXSEL12_RSRVD0(v) \ + (((v) << 30) & BM_PINCTRL_MUXSEL12_RSRVD0) +#define BP_PINCTRL_MUXSEL12_BANK6_PIN14 28 +#define BM_PINCTRL_MUXSEL12_BANK6_PIN14 0x30000000 +#define BF_PINCTRL_MUXSEL12_BANK6_PIN14(v) \ + (((v) << 28) & BM_PINCTRL_MUXSEL12_BANK6_PIN14) +#define BP_PINCTRL_MUXSEL12_BANK6_PIN13 26 +#define BM_PINCTRL_MUXSEL12_BANK6_PIN13 0x0C000000 +#define BF_PINCTRL_MUXSEL12_BANK6_PIN13(v) \ + (((v) << 26) & BM_PINCTRL_MUXSEL12_BANK6_PIN13) +#define BP_PINCTRL_MUXSEL12_BANK6_PIN12 24 +#define BM_PINCTRL_MUXSEL12_BANK6_PIN12 0x03000000 +#define BF_PINCTRL_MUXSEL12_BANK6_PIN12(v) \ + (((v) << 24) & BM_PINCTRL_MUXSEL12_BANK6_PIN12) +#define BP_PINCTRL_MUXSEL12_BANK6_PIN11 22 +#define BM_PINCTRL_MUXSEL12_BANK6_PIN11 0x00C00000 +#define BF_PINCTRL_MUXSEL12_BANK6_PIN11(v) \ + (((v) << 22) & BM_PINCTRL_MUXSEL12_BANK6_PIN11) +#define BP_PINCTRL_MUXSEL12_BANK6_PIN10 20 +#define BM_PINCTRL_MUXSEL12_BANK6_PIN10 0x00300000 +#define BF_PINCTRL_MUXSEL12_BANK6_PIN10(v) \ + (((v) << 20) & BM_PINCTRL_MUXSEL12_BANK6_PIN10) +#define BP_PINCTRL_MUXSEL12_BANK6_PIN09 18 +#define BM_PINCTRL_MUXSEL12_BANK6_PIN09 0x000C0000 +#define BF_PINCTRL_MUXSEL12_BANK6_PIN09(v) \ + (((v) << 18) & BM_PINCTRL_MUXSEL12_BANK6_PIN09) +#define BP_PINCTRL_MUXSEL12_BANK6_PIN08 16 +#define BM_PINCTRL_MUXSEL12_BANK6_PIN08 0x00030000 +#define BF_PINCTRL_MUXSEL12_BANK6_PIN08(v) \ + (((v) << 16) & BM_PINCTRL_MUXSEL12_BANK6_PIN08) +#define BP_PINCTRL_MUXSEL12_BANK6_PIN07 14 +#define BM_PINCTRL_MUXSEL12_BANK6_PIN07 0x0000C000 +#define BF_PINCTRL_MUXSEL12_BANK6_PIN07(v) \ + (((v) << 14) & BM_PINCTRL_MUXSEL12_BANK6_PIN07) +#define BP_PINCTRL_MUXSEL12_BANK6_PIN06 12 +#define BM_PINCTRL_MUXSEL12_BANK6_PIN06 0x00003000 +#define BF_PINCTRL_MUXSEL12_BANK6_PIN06(v) \ + (((v) << 12) & BM_PINCTRL_MUXSEL12_BANK6_PIN06) +#define BP_PINCTRL_MUXSEL12_BANK6_PIN05 10 +#define BM_PINCTRL_MUXSEL12_BANK6_PIN05 0x00000C00 +#define BF_PINCTRL_MUXSEL12_BANK6_PIN05(v) \ + (((v) << 10) & BM_PINCTRL_MUXSEL12_BANK6_PIN05) +#define BP_PINCTRL_MUXSEL12_BANK6_PIN04 8 +#define BM_PINCTRL_MUXSEL12_BANK6_PIN04 0x00000300 +#define BF_PINCTRL_MUXSEL12_BANK6_PIN04(v) \ + (((v) << 8) & BM_PINCTRL_MUXSEL12_BANK6_PIN04) +#define BP_PINCTRL_MUXSEL12_BANK6_PIN03 6 +#define BM_PINCTRL_MUXSEL12_BANK6_PIN03 0x000000C0 +#define BF_PINCTRL_MUXSEL12_BANK6_PIN03(v) \ + (((v) << 6) & BM_PINCTRL_MUXSEL12_BANK6_PIN03) +#define BP_PINCTRL_MUXSEL12_BANK6_PIN02 4 +#define BM_PINCTRL_MUXSEL12_BANK6_PIN02 0x00000030 +#define BF_PINCTRL_MUXSEL12_BANK6_PIN02(v) \ + (((v) << 4) & BM_PINCTRL_MUXSEL12_BANK6_PIN02) +#define BP_PINCTRL_MUXSEL12_BANK6_PIN01 2 +#define BM_PINCTRL_MUXSEL12_BANK6_PIN01 0x0000000C +#define BF_PINCTRL_MUXSEL12_BANK6_PIN01(v) \ + (((v) << 2) & BM_PINCTRL_MUXSEL12_BANK6_PIN01) +#define BP_PINCTRL_MUXSEL12_BANK6_PIN00 0 +#define BM_PINCTRL_MUXSEL12_BANK6_PIN00 0x00000003 +#define BF_PINCTRL_MUXSEL12_BANK6_PIN00(v) \ + (((v) << 0) & BM_PINCTRL_MUXSEL12_BANK6_PIN00) + +#define HW_PINCTRL_MUXSEL13 0x000001d0 +#define HW_PINCTRL_MUXSEL13_SET 0x000001d4 +#define HW_PINCTRL_MUXSEL13_CLR 0x000001d8 +#define HW_PINCTRL_MUXSEL13_TOG 0x000001dc + +#define BP_PINCTRL_MUXSEL13_RSRVD0 18 +#define BM_PINCTRL_MUXSEL13_RSRVD0 0xFFFC0000 +#define BF_PINCTRL_MUXSEL13_RSRVD0(v) \ + (((v) << 18) & BM_PINCTRL_MUXSEL13_RSRVD0) +#define BP_PINCTRL_MUXSEL13_BANK6_PIN24 16 +#define BM_PINCTRL_MUXSEL13_BANK6_PIN24 0x00030000 +#define BF_PINCTRL_MUXSEL13_BANK6_PIN24(v) \ + (((v) << 16) & BM_PINCTRL_MUXSEL13_BANK6_PIN24) +#define BP_PINCTRL_MUXSEL13_BANK6_PIN23 14 +#define BM_PINCTRL_MUXSEL13_BANK6_PIN23 0x0000C000 +#define BF_PINCTRL_MUXSEL13_BANK6_PIN23(v) \ + (((v) << 14) & BM_PINCTRL_MUXSEL13_BANK6_PIN23) +#define BP_PINCTRL_MUXSEL13_BANK6_PIN22 12 +#define BM_PINCTRL_MUXSEL13_BANK6_PIN22 0x00003000 +#define BF_PINCTRL_MUXSEL13_BANK6_PIN22(v) \ + (((v) << 12) & BM_PINCTRL_MUXSEL13_BANK6_PIN22) +#define BP_PINCTRL_MUXSEL13_BANK6_PIN21 10 +#define BM_PINCTRL_MUXSEL13_BANK6_PIN21 0x00000C00 +#define BF_PINCTRL_MUXSEL13_BANK6_PIN21(v) \ + (((v) << 10) & BM_PINCTRL_MUXSEL13_BANK6_PIN21) +#define BP_PINCTRL_MUXSEL13_BANK6_PIN20 8 +#define BM_PINCTRL_MUXSEL13_BANK6_PIN20 0x00000300 +#define BF_PINCTRL_MUXSEL13_BANK6_PIN20(v) \ + (((v) << 8) & BM_PINCTRL_MUXSEL13_BANK6_PIN20) +#define BP_PINCTRL_MUXSEL13_BANK6_PIN19 6 +#define BM_PINCTRL_MUXSEL13_BANK6_PIN19 0x000000C0 +#define BF_PINCTRL_MUXSEL13_BANK6_PIN19(v) \ + (((v) << 6) & BM_PINCTRL_MUXSEL13_BANK6_PIN19) +#define BP_PINCTRL_MUXSEL13_BANK6_PIN18 4 +#define BM_PINCTRL_MUXSEL13_BANK6_PIN18 0x00000030 +#define BF_PINCTRL_MUXSEL13_BANK6_PIN18(v) \ + (((v) << 4) & BM_PINCTRL_MUXSEL13_BANK6_PIN18) +#define BP_PINCTRL_MUXSEL13_BANK6_PIN17 2 +#define BM_PINCTRL_MUXSEL13_BANK6_PIN17 0x0000000C +#define BF_PINCTRL_MUXSEL13_BANK6_PIN17(v) \ + (((v) << 2) & BM_PINCTRL_MUXSEL13_BANK6_PIN17) +#define BP_PINCTRL_MUXSEL13_BANK6_PIN16 0 +#define BM_PINCTRL_MUXSEL13_BANK6_PIN16 0x00000003 +#define BF_PINCTRL_MUXSEL13_BANK6_PIN16(v) \ + (((v) << 0) & BM_PINCTRL_MUXSEL13_BANK6_PIN16) + +#define HW_PINCTRL_DRIVE0 0x00000300 +#define HW_PINCTRL_DRIVE0_SET 0x00000304 +#define HW_PINCTRL_DRIVE0_CLR 0x00000308 +#define HW_PINCTRL_DRIVE0_TOG 0x0000030c + +#define BM_PINCTRL_DRIVE0_RSRVD7 0x80000000 +#define BM_PINCTRL_DRIVE0_BANK0_PIN07_V 0x40000000 +#define BP_PINCTRL_DRIVE0_BANK0_PIN07_MA 28 +#define BM_PINCTRL_DRIVE0_BANK0_PIN07_MA 0x30000000 +#define BF_PINCTRL_DRIVE0_BANK0_PIN07_MA(v) \ + (((v) << 28) & BM_PINCTRL_DRIVE0_BANK0_PIN07_MA) +#define BM_PINCTRL_DRIVE0_RSRVD6 0x08000000 +#define BM_PINCTRL_DRIVE0_BANK0_PIN06_V 0x04000000 +#define BP_PINCTRL_DRIVE0_BANK0_PIN06_MA 24 +#define BM_PINCTRL_DRIVE0_BANK0_PIN06_MA 0x03000000 +#define BF_PINCTRL_DRIVE0_BANK0_PIN06_MA(v) \ + (((v) << 24) & BM_PINCTRL_DRIVE0_BANK0_PIN06_MA) +#define BM_PINCTRL_DRIVE0_RSRVD5 0x00800000 +#define BM_PINCTRL_DRIVE0_BANK0_PIN05_V 0x00400000 +#define BP_PINCTRL_DRIVE0_BANK0_PIN05_MA 20 +#define BM_PINCTRL_DRIVE0_BANK0_PIN05_MA 0x00300000 +#define BF_PINCTRL_DRIVE0_BANK0_PIN05_MA(v) \ + (((v) << 20) & BM_PINCTRL_DRIVE0_BANK0_PIN05_MA) +#define BM_PINCTRL_DRIVE0_RSRVD4 0x00080000 +#define BM_PINCTRL_DRIVE0_BANK0_PIN04_V 0x00040000 +#define BP_PINCTRL_DRIVE0_BANK0_PIN04_MA 16 +#define BM_PINCTRL_DRIVE0_BANK0_PIN04_MA 0x00030000 +#define BF_PINCTRL_DRIVE0_BANK0_PIN04_MA(v) \ + (((v) << 16) & BM_PINCTRL_DRIVE0_BANK0_PIN04_MA) +#define BM_PINCTRL_DRIVE0_RSRVD3 0x00008000 +#define BM_PINCTRL_DRIVE0_BANK0_PIN03_V 0x00004000 +#define BP_PINCTRL_DRIVE0_BANK0_PIN03_MA 12 +#define BM_PINCTRL_DRIVE0_BANK0_PIN03_MA 0x00003000 +#define BF_PINCTRL_DRIVE0_BANK0_PIN03_MA(v) \ + (((v) << 12) & BM_PINCTRL_DRIVE0_BANK0_PIN03_MA) +#define BM_PINCTRL_DRIVE0_RSRVD2 0x00000800 +#define BM_PINCTRL_DRIVE0_BANK0_PIN02_V 0x00000400 +#define BP_PINCTRL_DRIVE0_BANK0_PIN02_MA 8 +#define BM_PINCTRL_DRIVE0_BANK0_PIN02_MA 0x00000300 +#define BF_PINCTRL_DRIVE0_BANK0_PIN02_MA(v) \ + (((v) << 8) & BM_PINCTRL_DRIVE0_BANK0_PIN02_MA) +#define BM_PINCTRL_DRIVE0_RSRVD1 0x00000080 +#define BM_PINCTRL_DRIVE0_BANK0_PIN01_V 0x00000040 +#define BP_PINCTRL_DRIVE0_BANK0_PIN01_MA 4 +#define BM_PINCTRL_DRIVE0_BANK0_PIN01_MA 0x00000030 +#define BF_PINCTRL_DRIVE0_BANK0_PIN01_MA(v) \ + (((v) << 4) & BM_PINCTRL_DRIVE0_BANK0_PIN01_MA) +#define BM_PINCTRL_DRIVE0_RSRVD0 0x00000008 +#define BM_PINCTRL_DRIVE0_BANK0_PIN00_V 0x00000004 +#define BP_PINCTRL_DRIVE0_BANK0_PIN00_MA 0 +#define BM_PINCTRL_DRIVE0_BANK0_PIN00_MA 0x00000003 +#define BF_PINCTRL_DRIVE0_BANK0_PIN00_MA(v) \ + (((v) << 0) & BM_PINCTRL_DRIVE0_BANK0_PIN00_MA) + +#define HW_PINCTRL_DRIVE1 0x00000310 +#define HW_PINCTRL_DRIVE1_SET 0x00000314 +#define HW_PINCTRL_DRIVE1_CLR 0x00000318 +#define HW_PINCTRL_DRIVE1_TOG 0x0000031c + +#define BP_PINCTRL_DRIVE1_RSRVD0 0 +#define BM_PINCTRL_DRIVE1_RSRVD0 0xFFFFFFFF +#define BF_PINCTRL_DRIVE1_RSRVD0(v) (v) + +#define HW_PINCTRL_DRIVE2 0x00000320 +#define HW_PINCTRL_DRIVE2_SET 0x00000324 +#define HW_PINCTRL_DRIVE2_CLR 0x00000328 +#define HW_PINCTRL_DRIVE2_TOG 0x0000032c + +#define BM_PINCTRL_DRIVE2_RSRVD7 0x80000000 +#define BM_PINCTRL_DRIVE2_BANK0_PIN23_V 0x40000000 +#define BP_PINCTRL_DRIVE2_BANK0_PIN23_MA 28 +#define BM_PINCTRL_DRIVE2_BANK0_PIN23_MA 0x30000000 +#define BF_PINCTRL_DRIVE2_BANK0_PIN23_MA(v) \ + (((v) << 28) & BM_PINCTRL_DRIVE2_BANK0_PIN23_MA) +#define BM_PINCTRL_DRIVE2_RSRVD6 0x08000000 +#define BM_PINCTRL_DRIVE2_BANK0_PIN22_V 0x04000000 +#define BP_PINCTRL_DRIVE2_BANK0_PIN22_MA 24 +#define BM_PINCTRL_DRIVE2_BANK0_PIN22_MA 0x03000000 +#define BF_PINCTRL_DRIVE2_BANK0_PIN22_MA(v) \ + (((v) << 24) & BM_PINCTRL_DRIVE2_BANK0_PIN22_MA) +#define BM_PINCTRL_DRIVE2_RSRVD5 0x00800000 +#define BM_PINCTRL_DRIVE2_BANK0_PIN21_V 0x00400000 +#define BP_PINCTRL_DRIVE2_BANK0_PIN21_MA 20 +#define BM_PINCTRL_DRIVE2_BANK0_PIN21_MA 0x00300000 +#define BF_PINCTRL_DRIVE2_BANK0_PIN21_MA(v) \ + (((v) << 20) & BM_PINCTRL_DRIVE2_BANK0_PIN21_MA) +#define BM_PINCTRL_DRIVE2_RSRVD4 0x00080000 +#define BM_PINCTRL_DRIVE2_BANK0_PIN20_V 0x00040000 +#define BP_PINCTRL_DRIVE2_BANK0_PIN20_MA 16 +#define BM_PINCTRL_DRIVE2_BANK0_PIN20_MA 0x00030000 +#define BF_PINCTRL_DRIVE2_BANK0_PIN20_MA(v) \ + (((v) << 16) & BM_PINCTRL_DRIVE2_BANK0_PIN20_MA) +#define BM_PINCTRL_DRIVE2_RSRVD3 0x00008000 +#define BM_PINCTRL_DRIVE2_BANK0_PIN19_V 0x00004000 +#define BP_PINCTRL_DRIVE2_BANK0_PIN19_MA 12 +#define BM_PINCTRL_DRIVE2_BANK0_PIN19_MA 0x00003000 +#define BF_PINCTRL_DRIVE2_BANK0_PIN19_MA(v) \ + (((v) << 12) & BM_PINCTRL_DRIVE2_BANK0_PIN19_MA) +#define BM_PINCTRL_DRIVE2_RSRVD2 0x00000800 +#define BM_PINCTRL_DRIVE2_BANK0_PIN18_V 0x00000400 +#define BP_PINCTRL_DRIVE2_BANK0_PIN18_MA 8 +#define BM_PINCTRL_DRIVE2_BANK0_PIN18_MA 0x00000300 +#define BF_PINCTRL_DRIVE2_BANK0_PIN18_MA(v) \ + (((v) << 8) & BM_PINCTRL_DRIVE2_BANK0_PIN18_MA) +#define BM_PINCTRL_DRIVE2_RSRVD1 0x00000080 +#define BM_PINCTRL_DRIVE2_BANK0_PIN17_V 0x00000040 +#define BP_PINCTRL_DRIVE2_BANK0_PIN17_MA 4 +#define BM_PINCTRL_DRIVE2_BANK0_PIN17_MA 0x00000030 +#define BF_PINCTRL_DRIVE2_BANK0_PIN17_MA(v) \ + (((v) << 4) & BM_PINCTRL_DRIVE2_BANK0_PIN17_MA) +#define BM_PINCTRL_DRIVE2_RSRVD0 0x00000008 +#define BM_PINCTRL_DRIVE2_BANK0_PIN16_V 0x00000004 +#define BP_PINCTRL_DRIVE2_BANK0_PIN16_MA 0 +#define BM_PINCTRL_DRIVE2_BANK0_PIN16_MA 0x00000003 +#define BF_PINCTRL_DRIVE2_BANK0_PIN16_MA(v) \ + (((v) << 0) & BM_PINCTRL_DRIVE2_BANK0_PIN16_MA) + +#define HW_PINCTRL_DRIVE3 0x00000330 +#define HW_PINCTRL_DRIVE3_SET 0x00000334 +#define HW_PINCTRL_DRIVE3_CLR 0x00000338 +#define HW_PINCTRL_DRIVE3_TOG 0x0000033c + +#define BP_PINCTRL_DRIVE3_RSRVD5 20 +#define BM_PINCTRL_DRIVE3_RSRVD5 0xFFF00000 +#define BF_PINCTRL_DRIVE3_RSRVD5(v) \ + (((v) << 20) & BM_PINCTRL_DRIVE3_RSRVD5) +#define BM_PINCTRL_DRIVE3_RSRVD4 0x00080000 +#define BM_PINCTRL_DRIVE3_BANK0_PIN28_V 0x00040000 +#define BP_PINCTRL_DRIVE3_BANK0_PIN28_MA 16 +#define BM_PINCTRL_DRIVE3_BANK0_PIN28_MA 0x00030000 +#define BF_PINCTRL_DRIVE3_BANK0_PIN28_MA(v) \ + (((v) << 16) & BM_PINCTRL_DRIVE3_BANK0_PIN28_MA) +#define BM_PINCTRL_DRIVE3_RSRVD3 0x00008000 +#define BM_PINCTRL_DRIVE3_BANK0_PIN27_V 0x00004000 +#define BP_PINCTRL_DRIVE3_BANK0_PIN27_MA 12 +#define BM_PINCTRL_DRIVE3_BANK0_PIN27_MA 0x00003000 +#define BF_PINCTRL_DRIVE3_BANK0_PIN27_MA(v) \ + (((v) << 12) & BM_PINCTRL_DRIVE3_BANK0_PIN27_MA) +#define BM_PINCTRL_DRIVE3_RSRVD2 0x00000800 +#define BM_PINCTRL_DRIVE3_BANK0_PIN26_V 0x00000400 +#define BP_PINCTRL_DRIVE3_BANK0_PIN26_MA 8 +#define BM_PINCTRL_DRIVE3_BANK0_PIN26_MA 0x00000300 +#define BF_PINCTRL_DRIVE3_BANK0_PIN26_MA(v) \ + (((v) << 8) & BM_PINCTRL_DRIVE3_BANK0_PIN26_MA) +#define BM_PINCTRL_DRIVE3_RSRVD1 0x00000080 +#define BM_PINCTRL_DRIVE3_BANK0_PIN25_V 0x00000040 +#define BP_PINCTRL_DRIVE3_BANK0_PIN25_MA 4 +#define BM_PINCTRL_DRIVE3_BANK0_PIN25_MA 0x00000030 +#define BF_PINCTRL_DRIVE3_BANK0_PIN25_MA(v) \ + (((v) << 4) & BM_PINCTRL_DRIVE3_BANK0_PIN25_MA) +#define BM_PINCTRL_DRIVE3_RSRVD0 0x00000008 +#define BM_PINCTRL_DRIVE3_BANK0_PIN24_V 0x00000004 +#define BP_PINCTRL_DRIVE3_BANK0_PIN24_MA 0 +#define BM_PINCTRL_DRIVE3_BANK0_PIN24_MA 0x00000003 +#define BF_PINCTRL_DRIVE3_BANK0_PIN24_MA(v) \ + (((v) << 0) & BM_PINCTRL_DRIVE3_BANK0_PIN24_MA) + +#define HW_PINCTRL_DRIVE4 0x00000340 +#define HW_PINCTRL_DRIVE4_SET 0x00000344 +#define HW_PINCTRL_DRIVE4_CLR 0x00000348 +#define HW_PINCTRL_DRIVE4_TOG 0x0000034c + +#define BM_PINCTRL_DRIVE4_RSRVD7 0x80000000 +#define BM_PINCTRL_DRIVE4_BANK1_PIN07_V 0x40000000 +#define BP_PINCTRL_DRIVE4_BANK1_PIN07_MA 28 +#define BM_PINCTRL_DRIVE4_BANK1_PIN07_MA 0x30000000 +#define BF_PINCTRL_DRIVE4_BANK1_PIN07_MA(v) \ + (((v) << 28) & BM_PINCTRL_DRIVE4_BANK1_PIN07_MA) +#define BM_PINCTRL_DRIVE4_RSRVD6 0x08000000 +#define BM_PINCTRL_DRIVE4_BANK1_PIN06_V 0x04000000 +#define BP_PINCTRL_DRIVE4_BANK1_PIN06_MA 24 +#define BM_PINCTRL_DRIVE4_BANK1_PIN06_MA 0x03000000 +#define BF_PINCTRL_DRIVE4_BANK1_PIN06_MA(v) \ + (((v) << 24) & BM_PINCTRL_DRIVE4_BANK1_PIN06_MA) +#define BM_PINCTRL_DRIVE4_RSRVD5 0x00800000 +#define BM_PINCTRL_DRIVE4_BANK1_PIN05_V 0x00400000 +#define BP_PINCTRL_DRIVE4_BANK1_PIN05_MA 20 +#define BM_PINCTRL_DRIVE4_BANK1_PIN05_MA 0x00300000 +#define BF_PINCTRL_DRIVE4_BANK1_PIN05_MA(v) \ + (((v) << 20) & BM_PINCTRL_DRIVE4_BANK1_PIN05_MA) +#define BM_PINCTRL_DRIVE4_RSRVD4 0x00080000 +#define BM_PINCTRL_DRIVE4_BANK1_PIN04_V 0x00040000 +#define BP_PINCTRL_DRIVE4_BANK1_PIN04_MA 16 +#define BM_PINCTRL_DRIVE4_BANK1_PIN04_MA 0x00030000 +#define BF_PINCTRL_DRIVE4_BANK1_PIN04_MA(v) \ + (((v) << 16) & BM_PINCTRL_DRIVE4_BANK1_PIN04_MA) +#define BM_PINCTRL_DRIVE4_RSRVD3 0x00008000 +#define BM_PINCTRL_DRIVE4_BANK1_PIN03_V 0x00004000 +#define BP_PINCTRL_DRIVE4_BANK1_PIN03_MA 12 +#define BM_PINCTRL_DRIVE4_BANK1_PIN03_MA 0x00003000 +#define BF_PINCTRL_DRIVE4_BANK1_PIN03_MA(v) \ + (((v) << 12) & BM_PINCTRL_DRIVE4_BANK1_PIN03_MA) +#define BM_PINCTRL_DRIVE4_RSRVD2 0x00000800 +#define BM_PINCTRL_DRIVE4_BANK1_PIN02_V 0x00000400 +#define BP_PINCTRL_DRIVE4_BANK1_PIN02_MA 8 +#define BM_PINCTRL_DRIVE4_BANK1_PIN02_MA 0x00000300 +#define BF_PINCTRL_DRIVE4_BANK1_PIN02_MA(v) \ + (((v) << 8) & BM_PINCTRL_DRIVE4_BANK1_PIN02_MA) +#define BM_PINCTRL_DRIVE4_RSRVD1 0x00000080 +#define BM_PINCTRL_DRIVE4_BANK1_PIN01_V 0x00000040 +#define BP_PINCTRL_DRIVE4_BANK1_PIN01_MA 4 +#define BM_PINCTRL_DRIVE4_BANK1_PIN01_MA 0x00000030 +#define BF_PINCTRL_DRIVE4_BANK1_PIN01_MA(v) \ + (((v) << 4) & BM_PINCTRL_DRIVE4_BANK1_PIN01_MA) +#define BM_PINCTRL_DRIVE4_RSRVD0 0x00000008 +#define BM_PINCTRL_DRIVE4_BANK1_PIN00_V 0x00000004 +#define BP_PINCTRL_DRIVE4_BANK1_PIN00_MA 0 +#define BM_PINCTRL_DRIVE4_BANK1_PIN00_MA 0x00000003 +#define BF_PINCTRL_DRIVE4_BANK1_PIN00_MA(v) \ + (((v) << 0) & BM_PINCTRL_DRIVE4_BANK1_PIN00_MA) + +#define HW_PINCTRL_DRIVE5 0x00000350 +#define HW_PINCTRL_DRIVE5_SET 0x00000354 +#define HW_PINCTRL_DRIVE5_CLR 0x00000358 +#define HW_PINCTRL_DRIVE5_TOG 0x0000035c + +#define BM_PINCTRL_DRIVE5_RSRVD7 0x80000000 +#define BM_PINCTRL_DRIVE5_BANK1_PIN15_V 0x40000000 +#define BP_PINCTRL_DRIVE5_BANK1_PIN15_MA 28 +#define BM_PINCTRL_DRIVE5_BANK1_PIN15_MA 0x30000000 +#define BF_PINCTRL_DRIVE5_BANK1_PIN15_MA(v) \ + (((v) << 28) & BM_PINCTRL_DRIVE5_BANK1_PIN15_MA) +#define BM_PINCTRL_DRIVE5_RSRVD6 0x08000000 +#define BM_PINCTRL_DRIVE5_BANK1_PIN14_V 0x04000000 +#define BP_PINCTRL_DRIVE5_BANK1_PIN14_MA 24 +#define BM_PINCTRL_DRIVE5_BANK1_PIN14_MA 0x03000000 +#define BF_PINCTRL_DRIVE5_BANK1_PIN14_MA(v) \ + (((v) << 24) & BM_PINCTRL_DRIVE5_BANK1_PIN14_MA) +#define BM_PINCTRL_DRIVE5_RSRVD5 0x00800000 +#define BM_PINCTRL_DRIVE5_BANK1_PIN13_V 0x00400000 +#define BP_PINCTRL_DRIVE5_BANK1_PIN13_MA 20 +#define BM_PINCTRL_DRIVE5_BANK1_PIN13_MA 0x00300000 +#define BF_PINCTRL_DRIVE5_BANK1_PIN13_MA(v) \ + (((v) << 20) & BM_PINCTRL_DRIVE5_BANK1_PIN13_MA) +#define BM_PINCTRL_DRIVE5_RSRVD4 0x00080000 +#define BM_PINCTRL_DRIVE5_BANK1_PIN12_V 0x00040000 +#define BP_PINCTRL_DRIVE5_BANK1_PIN12_MA 16 +#define BM_PINCTRL_DRIVE5_BANK1_PIN12_MA 0x00030000 +#define BF_PINCTRL_DRIVE5_BANK1_PIN12_MA(v) \ + (((v) << 16) & BM_PINCTRL_DRIVE5_BANK1_PIN12_MA) +#define BM_PINCTRL_DRIVE5_RSRVD3 0x00008000 +#define BM_PINCTRL_DRIVE5_BANK1_PIN11_V 0x00004000 +#define BP_PINCTRL_DRIVE5_BANK1_PIN11_MA 12 +#define BM_PINCTRL_DRIVE5_BANK1_PIN11_MA 0x00003000 +#define BF_PINCTRL_DRIVE5_BANK1_PIN11_MA(v) \ + (((v) << 12) & BM_PINCTRL_DRIVE5_BANK1_PIN11_MA) +#define BM_PINCTRL_DRIVE5_RSRVD2 0x00000800 +#define BM_PINCTRL_DRIVE5_BANK1_PIN10_V 0x00000400 +#define BP_PINCTRL_DRIVE5_BANK1_PIN10_MA 8 +#define BM_PINCTRL_DRIVE5_BANK1_PIN10_MA 0x00000300 +#define BF_PINCTRL_DRIVE5_BANK1_PIN10_MA(v) \ + (((v) << 8) & BM_PINCTRL_DRIVE5_BANK1_PIN10_MA) +#define BM_PINCTRL_DRIVE5_RSRVD1 0x00000080 +#define BM_PINCTRL_DRIVE5_BANK1_PIN09_V 0x00000040 +#define BP_PINCTRL_DRIVE5_BANK1_PIN09_MA 4 +#define BM_PINCTRL_DRIVE5_BANK1_PIN09_MA 0x00000030 +#define BF_PINCTRL_DRIVE5_BANK1_PIN09_MA(v) \ + (((v) << 4) & BM_PINCTRL_DRIVE5_BANK1_PIN09_MA) +#define BM_PINCTRL_DRIVE5_RSRVD0 0x00000008 +#define BM_PINCTRL_DRIVE5_BANK1_PIN08_V 0x00000004 +#define BP_PINCTRL_DRIVE5_BANK1_PIN08_MA 0 +#define BM_PINCTRL_DRIVE5_BANK1_PIN08_MA 0x00000003 +#define BF_PINCTRL_DRIVE5_BANK1_PIN08_MA(v) \ + (((v) << 0) & BM_PINCTRL_DRIVE5_BANK1_PIN08_MA) + +#define HW_PINCTRL_DRIVE6 0x00000360 +#define HW_PINCTRL_DRIVE6_SET 0x00000364 +#define HW_PINCTRL_DRIVE6_CLR 0x00000368 +#define HW_PINCTRL_DRIVE6_TOG 0x0000036c + +#define BM_PINCTRL_DRIVE6_RSRVD7 0x80000000 +#define BM_PINCTRL_DRIVE6_BANK1_PIN23_V 0x40000000 +#define BP_PINCTRL_DRIVE6_BANK1_PIN23_MA 28 +#define BM_PINCTRL_DRIVE6_BANK1_PIN23_MA 0x30000000 +#define BF_PINCTRL_DRIVE6_BANK1_PIN23_MA(v) \ + (((v) << 28) & BM_PINCTRL_DRIVE6_BANK1_PIN23_MA) +#define BM_PINCTRL_DRIVE6_RSRVD6 0x08000000 +#define BM_PINCTRL_DRIVE6_BANK1_PIN22_V 0x04000000 +#define BP_PINCTRL_DRIVE6_BANK1_PIN22_MA 24 +#define BM_PINCTRL_DRIVE6_BANK1_PIN22_MA 0x03000000 +#define BF_PINCTRL_DRIVE6_BANK1_PIN22_MA(v) \ + (((v) << 24) & BM_PINCTRL_DRIVE6_BANK1_PIN22_MA) +#define BM_PINCTRL_DRIVE6_RSRVD5 0x00800000 +#define BM_PINCTRL_DRIVE6_BANK1_PIN21_V 0x00400000 +#define BP_PINCTRL_DRIVE6_BANK1_PIN21_MA 20 +#define BM_PINCTRL_DRIVE6_BANK1_PIN21_MA 0x00300000 +#define BF_PINCTRL_DRIVE6_BANK1_PIN21_MA(v) \ + (((v) << 20) & BM_PINCTRL_DRIVE6_BANK1_PIN21_MA) +#define BM_PINCTRL_DRIVE6_RSRVD4 0x00080000 +#define BM_PINCTRL_DRIVE6_BANK1_PIN20_V 0x00040000 +#define BP_PINCTRL_DRIVE6_BANK1_PIN20_MA 16 +#define BM_PINCTRL_DRIVE6_BANK1_PIN20_MA 0x00030000 +#define BF_PINCTRL_DRIVE6_BANK1_PIN20_MA(v) \ + (((v) << 16) & BM_PINCTRL_DRIVE6_BANK1_PIN20_MA) +#define BM_PINCTRL_DRIVE6_RSRVD3 0x00008000 +#define BM_PINCTRL_DRIVE6_BANK1_PIN19_V 0x00004000 +#define BP_PINCTRL_DRIVE6_BANK1_PIN19_MA 12 +#define BM_PINCTRL_DRIVE6_BANK1_PIN19_MA 0x00003000 +#define BF_PINCTRL_DRIVE6_BANK1_PIN19_MA(v) \ + (((v) << 12) & BM_PINCTRL_DRIVE6_BANK1_PIN19_MA) +#define BM_PINCTRL_DRIVE6_RSRVD2 0x00000800 +#define BM_PINCTRL_DRIVE6_BANK1_PIN18_V 0x00000400 +#define BP_PINCTRL_DRIVE6_BANK1_PIN18_MA 8 +#define BM_PINCTRL_DRIVE6_BANK1_PIN18_MA 0x00000300 +#define BF_PINCTRL_DRIVE6_BANK1_PIN18_MA(v) \ + (((v) << 8) & BM_PINCTRL_DRIVE6_BANK1_PIN18_MA) +#define BM_PINCTRL_DRIVE6_RSRVD1 0x00000080 +#define BM_PINCTRL_DRIVE6_BANK1_PIN17_V 0x00000040 +#define BP_PINCTRL_DRIVE6_BANK1_PIN17_MA 4 +#define BM_PINCTRL_DRIVE6_BANK1_PIN17_MA 0x00000030 +#define BF_PINCTRL_DRIVE6_BANK1_PIN17_MA(v) \ + (((v) << 4) & BM_PINCTRL_DRIVE6_BANK1_PIN17_MA) +#define BM_PINCTRL_DRIVE6_RSRVD0 0x00000008 +#define BM_PINCTRL_DRIVE6_BANK1_PIN16_V 0x00000004 +#define BP_PINCTRL_DRIVE6_BANK1_PIN16_MA 0 +#define BM_PINCTRL_DRIVE6_BANK1_PIN16_MA 0x00000003 +#define BF_PINCTRL_DRIVE6_BANK1_PIN16_MA(v) \ + (((v) << 0) & BM_PINCTRL_DRIVE6_BANK1_PIN16_MA) + +#define HW_PINCTRL_DRIVE7 0x00000370 +#define HW_PINCTRL_DRIVE7_SET 0x00000374 +#define HW_PINCTRL_DRIVE7_CLR 0x00000378 +#define HW_PINCTRL_DRIVE7_TOG 0x0000037c + +#define BM_PINCTRL_DRIVE7_RSRVD7 0x80000000 +#define BM_PINCTRL_DRIVE7_BANK1_PIN31_V 0x40000000 +#define BP_PINCTRL_DRIVE7_BANK1_PIN31_MA 28 +#define BM_PINCTRL_DRIVE7_BANK1_PIN31_MA 0x30000000 +#define BF_PINCTRL_DRIVE7_BANK1_PIN31_MA(v) \ + (((v) << 28) & BM_PINCTRL_DRIVE7_BANK1_PIN31_MA) +#define BM_PINCTRL_DRIVE7_RSRVD6 0x08000000 +#define BM_PINCTRL_DRIVE7_BANK1_PIN30_V 0x04000000 +#define BP_PINCTRL_DRIVE7_BANK1_PIN30_MA 24 +#define BM_PINCTRL_DRIVE7_BANK1_PIN30_MA 0x03000000 +#define BF_PINCTRL_DRIVE7_BANK1_PIN30_MA(v) \ + (((v) << 24) & BM_PINCTRL_DRIVE7_BANK1_PIN30_MA) +#define BM_PINCTRL_DRIVE7_RSRVD5 0x00800000 +#define BM_PINCTRL_DRIVE7_BANK1_PIN29_V 0x00400000 +#define BP_PINCTRL_DRIVE7_BANK1_PIN29_MA 20 +#define BM_PINCTRL_DRIVE7_BANK1_PIN29_MA 0x00300000 +#define BF_PINCTRL_DRIVE7_BANK1_PIN29_MA(v) \ + (((v) << 20) & BM_PINCTRL_DRIVE7_BANK1_PIN29_MA) +#define BM_PINCTRL_DRIVE7_RSRVD4 0x00080000 +#define BM_PINCTRL_DRIVE7_BANK1_PIN28_V 0x00040000 +#define BP_PINCTRL_DRIVE7_BANK1_PIN28_MA 16 +#define BM_PINCTRL_DRIVE7_BANK1_PIN28_MA 0x00030000 +#define BF_PINCTRL_DRIVE7_BANK1_PIN28_MA(v) \ + (((v) << 16) & BM_PINCTRL_DRIVE7_BANK1_PIN28_MA) +#define BM_PINCTRL_DRIVE7_RSRVD3 0x00008000 +#define BM_PINCTRL_DRIVE7_BANK1_PIN27_V 0x00004000 +#define BP_PINCTRL_DRIVE7_BANK1_PIN27_MA 12 +#define BM_PINCTRL_DRIVE7_BANK1_PIN27_MA 0x00003000 +#define BF_PINCTRL_DRIVE7_BANK1_PIN27_MA(v) \ + (((v) << 12) & BM_PINCTRL_DRIVE7_BANK1_PIN27_MA) +#define BM_PINCTRL_DRIVE7_RSRVD2 0x00000800 +#define BM_PINCTRL_DRIVE7_BANK1_PIN26_V 0x00000400 +#define BP_PINCTRL_DRIVE7_BANK1_PIN26_MA 8 +#define BM_PINCTRL_DRIVE7_BANK1_PIN26_MA 0x00000300 +#define BF_PINCTRL_DRIVE7_BANK1_PIN26_MA(v) \ + (((v) << 8) & BM_PINCTRL_DRIVE7_BANK1_PIN26_MA) +#define BM_PINCTRL_DRIVE7_RSRVD1 0x00000080 +#define BM_PINCTRL_DRIVE7_BANK1_PIN25_V 0x00000040 +#define BP_PINCTRL_DRIVE7_BANK1_PIN25_MA 4 +#define BM_PINCTRL_DRIVE7_BANK1_PIN25_MA 0x00000030 +#define BF_PINCTRL_DRIVE7_BANK1_PIN25_MA(v) \ + (((v) << 4) & BM_PINCTRL_DRIVE7_BANK1_PIN25_MA) +#define BM_PINCTRL_DRIVE7_RSRVD0 0x00000008 +#define BM_PINCTRL_DRIVE7_BANK1_PIN24_V 0x00000004 +#define BP_PINCTRL_DRIVE7_BANK1_PIN24_MA 0 +#define BM_PINCTRL_DRIVE7_BANK1_PIN24_MA 0x00000003 +#define BF_PINCTRL_DRIVE7_BANK1_PIN24_MA(v) \ + (((v) << 0) & BM_PINCTRL_DRIVE7_BANK1_PIN24_MA) + +#define HW_PINCTRL_DRIVE8 0x00000380 +#define HW_PINCTRL_DRIVE8_SET 0x00000384 +#define HW_PINCTRL_DRIVE8_CLR 0x00000388 +#define HW_PINCTRL_DRIVE8_TOG 0x0000038c + +#define BM_PINCTRL_DRIVE8_RSRVD7 0x80000000 +#define BM_PINCTRL_DRIVE8_BANK2_PIN07_V 0x40000000 +#define BP_PINCTRL_DRIVE8_BANK2_PIN07_MA 28 +#define BM_PINCTRL_DRIVE8_BANK2_PIN07_MA 0x30000000 +#define BF_PINCTRL_DRIVE8_BANK2_PIN07_MA(v) \ + (((v) << 28) & BM_PINCTRL_DRIVE8_BANK2_PIN07_MA) +#define BM_PINCTRL_DRIVE8_RSRVD6 0x08000000 +#define BM_PINCTRL_DRIVE8_BANK2_PIN06_V 0x04000000 +#define BP_PINCTRL_DRIVE8_BANK2_PIN06_MA 24 +#define BM_PINCTRL_DRIVE8_BANK2_PIN06_MA 0x03000000 +#define BF_PINCTRL_DRIVE8_BANK2_PIN06_MA(v) \ + (((v) << 24) & BM_PINCTRL_DRIVE8_BANK2_PIN06_MA) +#define BM_PINCTRL_DRIVE8_RSRVD5 0x00800000 +#define BM_PINCTRL_DRIVE8_BANK2_PIN05_V 0x00400000 +#define BP_PINCTRL_DRIVE8_BANK2_PIN05_MA 20 +#define BM_PINCTRL_DRIVE8_BANK2_PIN05_MA 0x00300000 +#define BF_PINCTRL_DRIVE8_BANK2_PIN05_MA(v) \ + (((v) << 20) & BM_PINCTRL_DRIVE8_BANK2_PIN05_MA) +#define BM_PINCTRL_DRIVE8_RSRVD4 0x00080000 +#define BM_PINCTRL_DRIVE8_BANK2_PIN04_V 0x00040000 +#define BP_PINCTRL_DRIVE8_BANK2_PIN04_MA 16 +#define BM_PINCTRL_DRIVE8_BANK2_PIN04_MA 0x00030000 +#define BF_PINCTRL_DRIVE8_BANK2_PIN04_MA(v) \ + (((v) << 16) & BM_PINCTRL_DRIVE8_BANK2_PIN04_MA) +#define BM_PINCTRL_DRIVE8_RSRVD3 0x00008000 +#define BM_PINCTRL_DRIVE8_BANK2_PIN03_V 0x00004000 +#define BP_PINCTRL_DRIVE8_BANK2_PIN03_MA 12 +#define BM_PINCTRL_DRIVE8_BANK2_PIN03_MA 0x00003000 +#define BF_PINCTRL_DRIVE8_BANK2_PIN03_MA(v) \ + (((v) << 12) & BM_PINCTRL_DRIVE8_BANK2_PIN03_MA) +#define BM_PINCTRL_DRIVE8_RSRVD2 0x00000800 +#define BM_PINCTRL_DRIVE8_BANK2_PIN02_V 0x00000400 +#define BP_PINCTRL_DRIVE8_BANK2_PIN02_MA 8 +#define BM_PINCTRL_DRIVE8_BANK2_PIN02_MA 0x00000300 +#define BF_PINCTRL_DRIVE8_BANK2_PIN02_MA(v) \ + (((v) << 8) & BM_PINCTRL_DRIVE8_BANK2_PIN02_MA) +#define BM_PINCTRL_DRIVE8_RSRVD1 0x00000080 +#define BM_PINCTRL_DRIVE8_BANK2_PIN01_V 0x00000040 +#define BP_PINCTRL_DRIVE8_BANK2_PIN01_MA 4 +#define BM_PINCTRL_DRIVE8_BANK2_PIN01_MA 0x00000030 +#define BF_PINCTRL_DRIVE8_BANK2_PIN01_MA(v) \ + (((v) << 4) & BM_PINCTRL_DRIVE8_BANK2_PIN01_MA) +#define BM_PINCTRL_DRIVE8_RSRVD0 0x00000008 +#define BM_PINCTRL_DRIVE8_BANK2_PIN00_V 0x00000004 +#define BP_PINCTRL_DRIVE8_BANK2_PIN00_MA 0 +#define BM_PINCTRL_DRIVE8_BANK2_PIN00_MA 0x00000003 +#define BF_PINCTRL_DRIVE8_BANK2_PIN00_MA(v) \ + (((v) << 0) & BM_PINCTRL_DRIVE8_BANK2_PIN00_MA) + +#define HW_PINCTRL_DRIVE9 0x00000390 +#define HW_PINCTRL_DRIVE9_SET 0x00000394 +#define HW_PINCTRL_DRIVE9_CLR 0x00000398 +#define HW_PINCTRL_DRIVE9_TOG 0x0000039c + +#define BM_PINCTRL_DRIVE9_RSRVD7 0x80000000 +#define BM_PINCTRL_DRIVE9_BANK2_PIN15_V 0x40000000 +#define BP_PINCTRL_DRIVE9_BANK2_PIN15_MA 28 +#define BM_PINCTRL_DRIVE9_BANK2_PIN15_MA 0x30000000 +#define BF_PINCTRL_DRIVE9_BANK2_PIN15_MA(v) \ + (((v) << 28) & BM_PINCTRL_DRIVE9_BANK2_PIN15_MA) +#define BM_PINCTRL_DRIVE9_RSRVD6 0x08000000 +#define BM_PINCTRL_DRIVE9_BANK2_PIN14_V 0x04000000 +#define BP_PINCTRL_DRIVE9_BANK2_PIN14_MA 24 +#define BM_PINCTRL_DRIVE9_BANK2_PIN14_MA 0x03000000 +#define BF_PINCTRL_DRIVE9_BANK2_PIN14_MA(v) \ + (((v) << 24) & BM_PINCTRL_DRIVE9_BANK2_PIN14_MA) +#define BM_PINCTRL_DRIVE9_RSRVD5 0x00800000 +#define BM_PINCTRL_DRIVE9_BANK2_PIN13_V 0x00400000 +#define BP_PINCTRL_DRIVE9_BANK2_PIN13_MA 20 +#define BM_PINCTRL_DRIVE9_BANK2_PIN13_MA 0x00300000 +#define BF_PINCTRL_DRIVE9_BANK2_PIN13_MA(v) \ + (((v) << 20) & BM_PINCTRL_DRIVE9_BANK2_PIN13_MA) +#define BM_PINCTRL_DRIVE9_RSRVD4 0x00080000 +#define BM_PINCTRL_DRIVE9_BANK2_PIN12_V 0x00040000 +#define BP_PINCTRL_DRIVE9_BANK2_PIN12_MA 16 +#define BM_PINCTRL_DRIVE9_BANK2_PIN12_MA 0x00030000 +#define BF_PINCTRL_DRIVE9_BANK2_PIN12_MA(v) \ + (((v) << 16) & BM_PINCTRL_DRIVE9_BANK2_PIN12_MA) +#define BP_PINCTRL_DRIVE9_RSRVD3 12 +#define BM_PINCTRL_DRIVE9_RSRVD3 0x0000F000 +#define BF_PINCTRL_DRIVE9_RSRVD3(v) \ + (((v) << 12) & BM_PINCTRL_DRIVE9_RSRVD3) +#define BM_PINCTRL_DRIVE9_RSRVD2 0x00000800 +#define BM_PINCTRL_DRIVE9_BANK2_PIN10_V 0x00000400 +#define BP_PINCTRL_DRIVE9_BANK2_PIN10_MA 8 +#define BM_PINCTRL_DRIVE9_BANK2_PIN10_MA 0x00000300 +#define BF_PINCTRL_DRIVE9_BANK2_PIN10_MA(v) \ + (((v) << 8) & BM_PINCTRL_DRIVE9_BANK2_PIN10_MA) +#define BM_PINCTRL_DRIVE9_RSRVD1 0x00000080 +#define BM_PINCTRL_DRIVE9_BANK2_PIN09_V 0x00000040 +#define BP_PINCTRL_DRIVE9_BANK2_PIN09_MA 4 +#define BM_PINCTRL_DRIVE9_BANK2_PIN09_MA 0x00000030 +#define BF_PINCTRL_DRIVE9_BANK2_PIN09_MA(v) \ + (((v) << 4) & BM_PINCTRL_DRIVE9_BANK2_PIN09_MA) +#define BM_PINCTRL_DRIVE9_RSRVD0 0x00000008 +#define BM_PINCTRL_DRIVE9_BANK2_PIN08_V 0x00000004 +#define BP_PINCTRL_DRIVE9_BANK2_PIN08_MA 0 +#define BM_PINCTRL_DRIVE9_BANK2_PIN08_MA 0x00000003 +#define BF_PINCTRL_DRIVE9_BANK2_PIN08_MA(v) \ + (((v) << 0) & BM_PINCTRL_DRIVE9_BANK2_PIN08_MA) + +#define HW_PINCTRL_DRIVE10 0x000003a0 +#define HW_PINCTRL_DRIVE10_SET 0x000003a4 +#define HW_PINCTRL_DRIVE10_CLR 0x000003a8 +#define HW_PINCTRL_DRIVE10_TOG 0x000003ac + +#define BP_PINCTRL_DRIVE10_RSRVD6 24 +#define BM_PINCTRL_DRIVE10_RSRVD6 0xFF000000 +#define BF_PINCTRL_DRIVE10_RSRVD6(v) \ + (((v) << 24) & BM_PINCTRL_DRIVE10_RSRVD6) +#define BM_PINCTRL_DRIVE10_RSRVD5 0x00800000 +#define BM_PINCTRL_DRIVE10_BANK2_PIN21_V 0x00400000 +#define BP_PINCTRL_DRIVE10_BANK2_PIN21_MA 20 +#define BM_PINCTRL_DRIVE10_BANK2_PIN21_MA 0x00300000 +#define BF_PINCTRL_DRIVE10_BANK2_PIN21_MA(v) \ + (((v) << 20) & BM_PINCTRL_DRIVE10_BANK2_PIN21_MA) +#define BM_PINCTRL_DRIVE10_RSRVD4 0x00080000 +#define BM_PINCTRL_DRIVE10_BANK2_PIN20_V 0x00040000 +#define BP_PINCTRL_DRIVE10_BANK2_PIN20_MA 16 +#define BM_PINCTRL_DRIVE10_BANK2_PIN20_MA 0x00030000 +#define BF_PINCTRL_DRIVE10_BANK2_PIN20_MA(v) \ + (((v) << 16) & BM_PINCTRL_DRIVE10_BANK2_PIN20_MA) +#define BM_PINCTRL_DRIVE10_RSRVD3 0x00008000 +#define BM_PINCTRL_DRIVE10_BANK2_PIN19_V 0x00004000 +#define BP_PINCTRL_DRIVE10_BANK2_PIN19_MA 12 +#define BM_PINCTRL_DRIVE10_BANK2_PIN19_MA 0x00003000 +#define BF_PINCTRL_DRIVE10_BANK2_PIN19_MA(v) \ + (((v) << 12) & BM_PINCTRL_DRIVE10_BANK2_PIN19_MA) +#define BM_PINCTRL_DRIVE10_RSRVD2 0x00000800 +#define BM_PINCTRL_DRIVE10_BANK2_PIN18_V 0x00000400 +#define BP_PINCTRL_DRIVE10_BANK2_PIN18_MA 8 +#define BM_PINCTRL_DRIVE10_BANK2_PIN18_MA 0x00000300 +#define BF_PINCTRL_DRIVE10_BANK2_PIN18_MA(v) \ + (((v) << 8) & BM_PINCTRL_DRIVE10_BANK2_PIN18_MA) +#define BM_PINCTRL_DRIVE10_RSRVD1 0x00000080 +#define BM_PINCTRL_DRIVE10_BANK2_PIN17_V 0x00000040 +#define BP_PINCTRL_DRIVE10_BANK2_PIN17_MA 4 +#define BM_PINCTRL_DRIVE10_BANK2_PIN17_MA 0x00000030 +#define BF_PINCTRL_DRIVE10_BANK2_PIN17_MA(v) \ + (((v) << 4) & BM_PINCTRL_DRIVE10_BANK2_PIN17_MA) +#define BM_PINCTRL_DRIVE10_RSRVD0 0x00000008 +#define BM_PINCTRL_DRIVE10_BANK2_PIN16_V 0x00000004 +#define BP_PINCTRL_DRIVE10_BANK2_PIN16_MA 0 +#define BM_PINCTRL_DRIVE10_BANK2_PIN16_MA 0x00000003 +#define BF_PINCTRL_DRIVE10_BANK2_PIN16_MA(v) \ + (((v) << 0) & BM_PINCTRL_DRIVE10_BANK2_PIN16_MA) + +#define HW_PINCTRL_DRIVE11 0x000003b0 +#define HW_PINCTRL_DRIVE11_SET 0x000003b4 +#define HW_PINCTRL_DRIVE11_CLR 0x000003b8 +#define HW_PINCTRL_DRIVE11_TOG 0x000003bc + +#define BP_PINCTRL_DRIVE11_RSRVD4 16 +#define BM_PINCTRL_DRIVE11_RSRVD4 0xFFFF0000 +#define BF_PINCTRL_DRIVE11_RSRVD4(v) \ + (((v) << 16) & BM_PINCTRL_DRIVE11_RSRVD4) +#define BM_PINCTRL_DRIVE11_RSRVD3 0x00008000 +#define BM_PINCTRL_DRIVE11_BANK2_PIN27_V 0x00004000 +#define BP_PINCTRL_DRIVE11_BANK2_PIN27_MA 12 +#define BM_PINCTRL_DRIVE11_BANK2_PIN27_MA 0x00003000 +#define BF_PINCTRL_DRIVE11_BANK2_PIN27_MA(v) \ + (((v) << 12) & BM_PINCTRL_DRIVE11_BANK2_PIN27_MA) +#define BM_PINCTRL_DRIVE11_RSRVD2 0x00000800 +#define BM_PINCTRL_DRIVE11_BANK2_PIN26_V 0x00000400 +#define BP_PINCTRL_DRIVE11_BANK2_PIN26_MA 8 +#define BM_PINCTRL_DRIVE11_BANK2_PIN26_MA 0x00000300 +#define BF_PINCTRL_DRIVE11_BANK2_PIN26_MA(v) \ + (((v) << 8) & BM_PINCTRL_DRIVE11_BANK2_PIN26_MA) +#define BM_PINCTRL_DRIVE11_RSRVD1 0x00000080 +#define BM_PINCTRL_DRIVE11_BANK2_PIN25_V 0x00000040 +#define BP_PINCTRL_DRIVE11_BANK2_PIN25_MA 4 +#define BM_PINCTRL_DRIVE11_BANK2_PIN25_MA 0x00000030 +#define BF_PINCTRL_DRIVE11_BANK2_PIN25_MA(v) \ + (((v) << 4) & BM_PINCTRL_DRIVE11_BANK2_PIN25_MA) +#define BM_PINCTRL_DRIVE11_RSRVD0 0x00000008 +#define BM_PINCTRL_DRIVE11_BANK2_PIN24_V 0x00000004 +#define BP_PINCTRL_DRIVE11_BANK2_PIN24_MA 0 +#define BM_PINCTRL_DRIVE11_BANK2_PIN24_MA 0x00000003 +#define BF_PINCTRL_DRIVE11_BANK2_PIN24_MA(v) \ + (((v) << 0) & BM_PINCTRL_DRIVE11_BANK2_PIN24_MA) + +#define HW_PINCTRL_DRIVE12 0x000003c0 +#define HW_PINCTRL_DRIVE12_SET 0x000003c4 +#define HW_PINCTRL_DRIVE12_CLR 0x000003c8 +#define HW_PINCTRL_DRIVE12_TOG 0x000003cc + +#define BM_PINCTRL_DRIVE12_RSRVD7 0x80000000 +#define BM_PINCTRL_DRIVE12_BANK3_PIN07_V 0x40000000 +#define BP_PINCTRL_DRIVE12_BANK3_PIN07_MA 28 +#define BM_PINCTRL_DRIVE12_BANK3_PIN07_MA 0x30000000 +#define BF_PINCTRL_DRIVE12_BANK3_PIN07_MA(v) \ + (((v) << 28) & BM_PINCTRL_DRIVE12_BANK3_PIN07_MA) +#define BM_PINCTRL_DRIVE12_RSRVD6 0x08000000 +#define BM_PINCTRL_DRIVE12_BANK3_PIN06_V 0x04000000 +#define BP_PINCTRL_DRIVE12_BANK3_PIN06_MA 24 +#define BM_PINCTRL_DRIVE12_BANK3_PIN06_MA 0x03000000 +#define BF_PINCTRL_DRIVE12_BANK3_PIN06_MA(v) \ + (((v) << 24) & BM_PINCTRL_DRIVE12_BANK3_PIN06_MA) +#define BM_PINCTRL_DRIVE12_RSRVD5 0x00800000 +#define BM_PINCTRL_DRIVE12_BANK3_PIN05_V 0x00400000 +#define BP_PINCTRL_DRIVE12_BANK3_PIN05_MA 20 +#define BM_PINCTRL_DRIVE12_BANK3_PIN05_MA 0x00300000 +#define BF_PINCTRL_DRIVE12_BANK3_PIN05_MA(v) \ + (((v) << 20) & BM_PINCTRL_DRIVE12_BANK3_PIN05_MA) +#define BM_PINCTRL_DRIVE12_RSRVD4 0x00080000 +#define BM_PINCTRL_DRIVE12_BANK3_PIN04_V 0x00040000 +#define BP_PINCTRL_DRIVE12_BANK3_PIN04_MA 16 +#define BM_PINCTRL_DRIVE12_BANK3_PIN04_MA 0x00030000 +#define BF_PINCTRL_DRIVE12_BANK3_PIN04_MA(v) \ + (((v) << 16) & BM_PINCTRL_DRIVE12_BANK3_PIN04_MA) +#define BM_PINCTRL_DRIVE12_RSRVD3 0x00008000 +#define BM_PINCTRL_DRIVE12_BANK3_PIN03_V 0x00004000 +#define BP_PINCTRL_DRIVE12_BANK3_PIN03_MA 12 +#define BM_PINCTRL_DRIVE12_BANK3_PIN03_MA 0x00003000 +#define BF_PINCTRL_DRIVE12_BANK3_PIN03_MA(v) \ + (((v) << 12) & BM_PINCTRL_DRIVE12_BANK3_PIN03_MA) +#define BM_PINCTRL_DRIVE12_RSRVD2 0x00000800 +#define BM_PINCTRL_DRIVE12_BANK3_PIN02_V 0x00000400 +#define BP_PINCTRL_DRIVE12_BANK3_PIN02_MA 8 +#define BM_PINCTRL_DRIVE12_BANK3_PIN02_MA 0x00000300 +#define BF_PINCTRL_DRIVE12_BANK3_PIN02_MA(v) \ + (((v) << 8) & BM_PINCTRL_DRIVE12_BANK3_PIN02_MA) +#define BM_PINCTRL_DRIVE12_RSRVD1 0x00000080 +#define BM_PINCTRL_DRIVE12_BANK3_PIN01_V 0x00000040 +#define BP_PINCTRL_DRIVE12_BANK3_PIN01_MA 4 +#define BM_PINCTRL_DRIVE12_BANK3_PIN01_MA 0x00000030 +#define BF_PINCTRL_DRIVE12_BANK3_PIN01_MA(v) \ + (((v) << 4) & BM_PINCTRL_DRIVE12_BANK3_PIN01_MA) +#define BM_PINCTRL_DRIVE12_RSRVD0 0x00000008 +#define BM_PINCTRL_DRIVE12_BANK3_PIN00_V 0x00000004 +#define BP_PINCTRL_DRIVE12_BANK3_PIN00_MA 0 +#define BM_PINCTRL_DRIVE12_BANK3_PIN00_MA 0x00000003 +#define BF_PINCTRL_DRIVE12_BANK3_PIN00_MA(v) \ + (((v) << 0) & BM_PINCTRL_DRIVE12_BANK3_PIN00_MA) + +#define HW_PINCTRL_DRIVE13 0x000003d0 +#define HW_PINCTRL_DRIVE13_SET 0x000003d4 +#define HW_PINCTRL_DRIVE13_CLR 0x000003d8 +#define HW_PINCTRL_DRIVE13_TOG 0x000003dc + +#define BM_PINCTRL_DRIVE13_RSRVD7 0x80000000 +#define BM_PINCTRL_DRIVE13_BANK3_PIN15_V 0x40000000 +#define BP_PINCTRL_DRIVE13_BANK3_PIN15_MA 28 +#define BM_PINCTRL_DRIVE13_BANK3_PIN15_MA 0x30000000 +#define BF_PINCTRL_DRIVE13_BANK3_PIN15_MA(v) \ + (((v) << 28) & BM_PINCTRL_DRIVE13_BANK3_PIN15_MA) +#define BM_PINCTRL_DRIVE13_RSRVD6 0x08000000 +#define BM_PINCTRL_DRIVE13_BANK3_PIN14_V 0x04000000 +#define BP_PINCTRL_DRIVE13_BANK3_PIN14_MA 24 +#define BM_PINCTRL_DRIVE13_BANK3_PIN14_MA 0x03000000 +#define BF_PINCTRL_DRIVE13_BANK3_PIN14_MA(v) \ + (((v) << 24) & BM_PINCTRL_DRIVE13_BANK3_PIN14_MA) +#define BM_PINCTRL_DRIVE13_RSRVD5 0x00800000 +#define BM_PINCTRL_DRIVE13_BANK3_PIN13_V 0x00400000 +#define BP_PINCTRL_DRIVE13_BANK3_PIN13_MA 20 +#define BM_PINCTRL_DRIVE13_BANK3_PIN13_MA 0x00300000 +#define BF_PINCTRL_DRIVE13_BANK3_PIN13_MA(v) \ + (((v) << 20) & BM_PINCTRL_DRIVE13_BANK3_PIN13_MA) +#define BM_PINCTRL_DRIVE13_RSRVD4 0x00080000 +#define BM_PINCTRL_DRIVE13_BANK3_PIN12_V 0x00040000 +#define BP_PINCTRL_DRIVE13_BANK3_PIN12_MA 16 +#define BM_PINCTRL_DRIVE13_BANK3_PIN12_MA 0x00030000 +#define BF_PINCTRL_DRIVE13_BANK3_PIN12_MA(v) \ + (((v) << 16) & BM_PINCTRL_DRIVE13_BANK3_PIN12_MA) +#define BM_PINCTRL_DRIVE13_RSRVD3 0x00008000 +#define BM_PINCTRL_DRIVE13_BANK3_PIN11_V 0x00004000 +#define BP_PINCTRL_DRIVE13_BANK3_PIN11_MA 12 +#define BM_PINCTRL_DRIVE13_BANK3_PIN11_MA 0x00003000 +#define BF_PINCTRL_DRIVE13_BANK3_PIN11_MA(v) \ + (((v) << 12) & BM_PINCTRL_DRIVE13_BANK3_PIN11_MA) +#define BM_PINCTRL_DRIVE13_RSRVD2 0x00000800 +#define BM_PINCTRL_DRIVE13_BANK3_PIN10_V 0x00000400 +#define BP_PINCTRL_DRIVE13_BANK3_PIN10_MA 8 +#define BM_PINCTRL_DRIVE13_BANK3_PIN10_MA 0x00000300 +#define BF_PINCTRL_DRIVE13_BANK3_PIN10_MA(v) \ + (((v) << 8) & BM_PINCTRL_DRIVE13_BANK3_PIN10_MA) +#define BM_PINCTRL_DRIVE13_RSRVD1 0x00000080 +#define BM_PINCTRL_DRIVE13_BANK3_PIN09_V 0x00000040 +#define BP_PINCTRL_DRIVE13_BANK3_PIN09_MA 4 +#define BM_PINCTRL_DRIVE13_BANK3_PIN09_MA 0x00000030 +#define BF_PINCTRL_DRIVE13_BANK3_PIN09_MA(v) \ + (((v) << 4) & BM_PINCTRL_DRIVE13_BANK3_PIN09_MA) +#define BM_PINCTRL_DRIVE13_RSRVD0 0x00000008 +#define BM_PINCTRL_DRIVE13_BANK3_PIN08_V 0x00000004 +#define BP_PINCTRL_DRIVE13_BANK3_PIN08_MA 0 +#define BM_PINCTRL_DRIVE13_BANK3_PIN08_MA 0x00000003 +#define BF_PINCTRL_DRIVE13_BANK3_PIN08_MA(v) \ + (((v) << 0) & BM_PINCTRL_DRIVE13_BANK3_PIN08_MA) + +#define HW_PINCTRL_DRIVE14 0x000003e0 +#define HW_PINCTRL_DRIVE14_SET 0x000003e4 +#define HW_PINCTRL_DRIVE14_CLR 0x000003e8 +#define HW_PINCTRL_DRIVE14_TOG 0x000003ec + +#define BM_PINCTRL_DRIVE14_RSRVD7 0x80000000 +#define BM_PINCTRL_DRIVE14_BANK3_PIN23_V 0x40000000 +#define BP_PINCTRL_DRIVE14_BANK3_PIN23_MA 28 +#define BM_PINCTRL_DRIVE14_BANK3_PIN23_MA 0x30000000 +#define BF_PINCTRL_DRIVE14_BANK3_PIN23_MA(v) \ + (((v) << 28) & BM_PINCTRL_DRIVE14_BANK3_PIN23_MA) +#define BM_PINCTRL_DRIVE14_RSRVD6 0x08000000 +#define BM_PINCTRL_DRIVE14_BANK3_PIN22_V 0x04000000 +#define BP_PINCTRL_DRIVE14_BANK3_PIN22_MA 24 +#define BM_PINCTRL_DRIVE14_BANK3_PIN22_MA 0x03000000 +#define BF_PINCTRL_DRIVE14_BANK3_PIN22_MA(v) \ + (((v) << 24) & BM_PINCTRL_DRIVE14_BANK3_PIN22_MA) +#define BM_PINCTRL_DRIVE14_RSRVD5 0x00800000 +#define BM_PINCTRL_DRIVE14_BANK3_PIN21_V 0x00400000 +#define BP_PINCTRL_DRIVE14_BANK3_PIN21_MA 20 +#define BM_PINCTRL_DRIVE14_BANK3_PIN21_MA 0x00300000 +#define BF_PINCTRL_DRIVE14_BANK3_PIN21_MA(v) \ + (((v) << 20) & BM_PINCTRL_DRIVE14_BANK3_PIN21_MA) +#define BM_PINCTRL_DRIVE14_RSRVD4 0x00080000 +#define BM_PINCTRL_DRIVE14_BANK3_PIN20_V 0x00040000 +#define BP_PINCTRL_DRIVE14_BANK3_PIN20_MA 16 +#define BM_PINCTRL_DRIVE14_BANK3_PIN20_MA 0x00030000 +#define BF_PINCTRL_DRIVE14_BANK3_PIN20_MA(v) \ + (((v) << 16) & BM_PINCTRL_DRIVE14_BANK3_PIN20_MA) +#define BP_PINCTRL_DRIVE14_RSRVD3 12 +#define BM_PINCTRL_DRIVE14_RSRVD3 0x0000F000 +#define BF_PINCTRL_DRIVE14_RSRVD3(v) \ + (((v) << 12) & BM_PINCTRL_DRIVE14_RSRVD3) +#define BM_PINCTRL_DRIVE14_RSRVD2 0x00000800 +#define BM_PINCTRL_DRIVE14_BANK3_PIN18_V 0x00000400 +#define BP_PINCTRL_DRIVE14_BANK3_PIN18_MA 8 +#define BM_PINCTRL_DRIVE14_BANK3_PIN18_MA 0x00000300 +#define BF_PINCTRL_DRIVE14_BANK3_PIN18_MA(v) \ + (((v) << 8) & BM_PINCTRL_DRIVE14_BANK3_PIN18_MA) +#define BM_PINCTRL_DRIVE14_RSRVD1 0x00000080 +#define BM_PINCTRL_DRIVE14_BANK3_PIN17_V 0x00000040 +#define BP_PINCTRL_DRIVE14_BANK3_PIN17_MA 4 +#define BM_PINCTRL_DRIVE14_BANK3_PIN17_MA 0x00000030 +#define BF_PINCTRL_DRIVE14_BANK3_PIN17_MA(v) \ + (((v) << 4) & BM_PINCTRL_DRIVE14_BANK3_PIN17_MA) +#define BM_PINCTRL_DRIVE14_RSRVD0 0x00000008 +#define BM_PINCTRL_DRIVE14_BANK3_PIN16_V 0x00000004 +#define BP_PINCTRL_DRIVE14_BANK3_PIN16_MA 0 +#define BM_PINCTRL_DRIVE14_BANK3_PIN16_MA 0x00000003 +#define BF_PINCTRL_DRIVE14_BANK3_PIN16_MA(v) \ + (((v) << 0) & BM_PINCTRL_DRIVE14_BANK3_PIN16_MA) + +#define HW_PINCTRL_DRIVE15 0x000003f0 +#define HW_PINCTRL_DRIVE15_SET 0x000003f4 +#define HW_PINCTRL_DRIVE15_CLR 0x000003f8 +#define HW_PINCTRL_DRIVE15_TOG 0x000003fc + +#define BP_PINCTRL_DRIVE15_RSRVD7 28 +#define BM_PINCTRL_DRIVE15_RSRVD7 0xF0000000 +#define BF_PINCTRL_DRIVE15_RSRVD7(v) \ + (((v) << 28) & BM_PINCTRL_DRIVE15_RSRVD7) +#define BM_PINCTRL_DRIVE15_RSRVD6 0x08000000 +#define BM_PINCTRL_DRIVE15_BANK3_PIN30_V 0x04000000 +#define BP_PINCTRL_DRIVE15_BANK3_PIN30_MA 24 +#define BM_PINCTRL_DRIVE15_BANK3_PIN30_MA 0x03000000 +#define BF_PINCTRL_DRIVE15_BANK3_PIN30_MA(v) \ + (((v) << 24) & BM_PINCTRL_DRIVE15_BANK3_PIN30_MA) +#define BM_PINCTRL_DRIVE15_RSRVD5 0x00800000 +#define BM_PINCTRL_DRIVE15_BANK3_PIN29_V 0x00400000 +#define BP_PINCTRL_DRIVE15_BANK3_PIN29_MA 20 +#define BM_PINCTRL_DRIVE15_BANK3_PIN29_MA 0x00300000 +#define BF_PINCTRL_DRIVE15_BANK3_PIN29_MA(v) \ + (((v) << 20) & BM_PINCTRL_DRIVE15_BANK3_PIN29_MA) +#define BM_PINCTRL_DRIVE15_RSRVD4 0x00080000 +#define BM_PINCTRL_DRIVE15_BANK3_PIN28_V 0x00040000 +#define BP_PINCTRL_DRIVE15_BANK3_PIN28_MA 16 +#define BM_PINCTRL_DRIVE15_BANK3_PIN28_MA 0x00030000 +#define BF_PINCTRL_DRIVE15_BANK3_PIN28_MA(v) \ + (((v) << 16) & BM_PINCTRL_DRIVE15_BANK3_PIN28_MA) +#define BM_PINCTRL_DRIVE15_RSRVD3 0x00008000 +#define BM_PINCTRL_DRIVE15_BANK3_PIN27_V 0x00004000 +#define BP_PINCTRL_DRIVE15_BANK3_PIN27_MA 12 +#define BM_PINCTRL_DRIVE15_BANK3_PIN27_MA 0x00003000 +#define BF_PINCTRL_DRIVE15_BANK3_PIN27_MA(v) \ + (((v) << 12) & BM_PINCTRL_DRIVE15_BANK3_PIN27_MA) +#define BM_PINCTRL_DRIVE15_RSRVD2 0x00000800 +#define BM_PINCTRL_DRIVE15_BANK3_PIN26_V 0x00000400 +#define BP_PINCTRL_DRIVE15_BANK3_PIN26_MA 8 +#define BM_PINCTRL_DRIVE15_BANK3_PIN26_MA 0x00000300 +#define BF_PINCTRL_DRIVE15_BANK3_PIN26_MA(v) \ + (((v) << 8) & BM_PINCTRL_DRIVE15_BANK3_PIN26_MA) +#define BM_PINCTRL_DRIVE15_RSRVD1 0x00000080 +#define BM_PINCTRL_DRIVE15_BANK3_PIN25_V 0x00000040 +#define BP_PINCTRL_DRIVE15_BANK3_PIN25_MA 4 +#define BM_PINCTRL_DRIVE15_BANK3_PIN25_MA 0x00000030 +#define BF_PINCTRL_DRIVE15_BANK3_PIN25_MA(v) \ + (((v) << 4) & BM_PINCTRL_DRIVE15_BANK3_PIN25_MA) +#define BM_PINCTRL_DRIVE15_RSRVD0 0x00000008 +#define BM_PINCTRL_DRIVE15_BANK3_PIN24_V 0x00000004 +#define BP_PINCTRL_DRIVE15_BANK3_PIN24_MA 0 +#define BM_PINCTRL_DRIVE15_BANK3_PIN24_MA 0x00000003 +#define BF_PINCTRL_DRIVE15_BANK3_PIN24_MA(v) \ + (((v) << 0) & BM_PINCTRL_DRIVE15_BANK3_PIN24_MA) + +#define HW_PINCTRL_DRIVE16 0x00000400 +#define HW_PINCTRL_DRIVE16_SET 0x00000404 +#define HW_PINCTRL_DRIVE16_CLR 0x00000408 +#define HW_PINCTRL_DRIVE16_TOG 0x0000040c + +#define BM_PINCTRL_DRIVE16_RSRVD7 0x80000000 +#define BM_PINCTRL_DRIVE16_BANK4_PIN07_V 0x40000000 +#define BP_PINCTRL_DRIVE16_BANK4_PIN07_MA 28 +#define BM_PINCTRL_DRIVE16_BANK4_PIN07_MA 0x30000000 +#define BF_PINCTRL_DRIVE16_BANK4_PIN07_MA(v) \ + (((v) << 28) & BM_PINCTRL_DRIVE16_BANK4_PIN07_MA) +#define BM_PINCTRL_DRIVE16_RSRVD6 0x08000000 +#define BM_PINCTRL_DRIVE16_BANK4_PIN06_V 0x04000000 +#define BP_PINCTRL_DRIVE16_BANK4_PIN06_MA 24 +#define BM_PINCTRL_DRIVE16_BANK4_PIN06_MA 0x03000000 +#define BF_PINCTRL_DRIVE16_BANK4_PIN06_MA(v) \ + (((v) << 24) & BM_PINCTRL_DRIVE16_BANK4_PIN06_MA) +#define BM_PINCTRL_DRIVE16_RSRVD5 0x00800000 +#define BM_PINCTRL_DRIVE16_BANK4_PIN05_V 0x00400000 +#define BP_PINCTRL_DRIVE16_BANK4_PIN05_MA 20 +#define BM_PINCTRL_DRIVE16_BANK4_PIN05_MA 0x00300000 +#define BF_PINCTRL_DRIVE16_BANK4_PIN05_MA(v) \ + (((v) << 20) & BM_PINCTRL_DRIVE16_BANK4_PIN05_MA) +#define BM_PINCTRL_DRIVE16_RSRVD4 0x00080000 +#define BM_PINCTRL_DRIVE16_BANK4_PIN04_V 0x00040000 +#define BP_PINCTRL_DRIVE16_BANK4_PIN04_MA 16 +#define BM_PINCTRL_DRIVE16_BANK4_PIN04_MA 0x00030000 +#define BF_PINCTRL_DRIVE16_BANK4_PIN04_MA(v) \ + (((v) << 16) & BM_PINCTRL_DRIVE16_BANK4_PIN04_MA) +#define BM_PINCTRL_DRIVE16_RSRVD3 0x00008000 +#define BM_PINCTRL_DRIVE16_BANK4_PIN03_V 0x00004000 +#define BP_PINCTRL_DRIVE16_BANK4_PIN03_MA 12 +#define BM_PINCTRL_DRIVE16_BANK4_PIN03_MA 0x00003000 +#define BF_PINCTRL_DRIVE16_BANK4_PIN03_MA(v) \ + (((v) << 12) & BM_PINCTRL_DRIVE16_BANK4_PIN03_MA) +#define BM_PINCTRL_DRIVE16_RSRVD2 0x00000800 +#define BM_PINCTRL_DRIVE16_BANK4_PIN02_V 0x00000400 +#define BP_PINCTRL_DRIVE16_BANK4_PIN02_MA 8 +#define BM_PINCTRL_DRIVE16_BANK4_PIN02_MA 0x00000300 +#define BF_PINCTRL_DRIVE16_BANK4_PIN02_MA(v) \ + (((v) << 8) & BM_PINCTRL_DRIVE16_BANK4_PIN02_MA) +#define BM_PINCTRL_DRIVE16_RSRVD1 0x00000080 +#define BM_PINCTRL_DRIVE16_BANK4_PIN01_V 0x00000040 +#define BP_PINCTRL_DRIVE16_BANK4_PIN01_MA 4 +#define BM_PINCTRL_DRIVE16_BANK4_PIN01_MA 0x00000030 +#define BF_PINCTRL_DRIVE16_BANK4_PIN01_MA(v) \ + (((v) << 4) & BM_PINCTRL_DRIVE16_BANK4_PIN01_MA) +#define BM_PINCTRL_DRIVE16_RSRVD0 0x00000008 +#define BM_PINCTRL_DRIVE16_BANK4_PIN00_V 0x00000004 +#define BP_PINCTRL_DRIVE16_BANK4_PIN00_MA 0 +#define BM_PINCTRL_DRIVE16_BANK4_PIN00_MA 0x00000003 +#define BF_PINCTRL_DRIVE16_BANK4_PIN00_MA(v) \ + (((v) << 0) & BM_PINCTRL_DRIVE16_BANK4_PIN00_MA) + +#define HW_PINCTRL_DRIVE17 0x00000410 +#define HW_PINCTRL_DRIVE17_SET 0x00000414 +#define HW_PINCTRL_DRIVE17_CLR 0x00000418 +#define HW_PINCTRL_DRIVE17_TOG 0x0000041c + +#define BM_PINCTRL_DRIVE17_RSRVD7 0x80000000 +#define BM_PINCTRL_DRIVE17_BANK4_PIN15_V 0x40000000 +#define BP_PINCTRL_DRIVE17_BANK4_PIN15_MA 28 +#define BM_PINCTRL_DRIVE17_BANK4_PIN15_MA 0x30000000 +#define BF_PINCTRL_DRIVE17_BANK4_PIN15_MA(v) \ + (((v) << 28) & BM_PINCTRL_DRIVE17_BANK4_PIN15_MA) +#define BM_PINCTRL_DRIVE17_RSRVD6 0x08000000 +#define BM_PINCTRL_DRIVE17_BANK4_PIN14_V 0x04000000 +#define BP_PINCTRL_DRIVE17_BANK4_PIN14_MA 24 +#define BM_PINCTRL_DRIVE17_BANK4_PIN14_MA 0x03000000 +#define BF_PINCTRL_DRIVE17_BANK4_PIN14_MA(v) \ + (((v) << 24) & BM_PINCTRL_DRIVE17_BANK4_PIN14_MA) +#define BM_PINCTRL_DRIVE17_RSRVD5 0x00800000 +#define BM_PINCTRL_DRIVE17_BANK4_PIN13_V 0x00400000 +#define BP_PINCTRL_DRIVE17_BANK4_PIN13_MA 20 +#define BM_PINCTRL_DRIVE17_BANK4_PIN13_MA 0x00300000 +#define BF_PINCTRL_DRIVE17_BANK4_PIN13_MA(v) \ + (((v) << 20) & BM_PINCTRL_DRIVE17_BANK4_PIN13_MA) +#define BM_PINCTRL_DRIVE17_RSRVD4 0x00080000 +#define BM_PINCTRL_DRIVE17_BANK4_PIN12_V 0x00040000 +#define BP_PINCTRL_DRIVE17_BANK4_PIN12_MA 16 +#define BM_PINCTRL_DRIVE17_BANK4_PIN12_MA 0x00030000 +#define BF_PINCTRL_DRIVE17_BANK4_PIN12_MA(v) \ + (((v) << 16) & BM_PINCTRL_DRIVE17_BANK4_PIN12_MA) +#define BM_PINCTRL_DRIVE17_RSRVD3 0x00008000 +#define BM_PINCTRL_DRIVE17_BANK4_PIN11_V 0x00004000 +#define BP_PINCTRL_DRIVE17_BANK4_PIN11_MA 12 +#define BM_PINCTRL_DRIVE17_BANK4_PIN11_MA 0x00003000 +#define BF_PINCTRL_DRIVE17_BANK4_PIN11_MA(v) \ + (((v) << 12) & BM_PINCTRL_DRIVE17_BANK4_PIN11_MA) +#define BM_PINCTRL_DRIVE17_RSRVD2 0x00000800 +#define BM_PINCTRL_DRIVE17_BANK4_PIN10_V 0x00000400 +#define BP_PINCTRL_DRIVE17_BANK4_PIN10_MA 8 +#define BM_PINCTRL_DRIVE17_BANK4_PIN10_MA 0x00000300 +#define BF_PINCTRL_DRIVE17_BANK4_PIN10_MA(v) \ + (((v) << 8) & BM_PINCTRL_DRIVE17_BANK4_PIN10_MA) +#define BM_PINCTRL_DRIVE17_RSRVD1 0x00000080 +#define BM_PINCTRL_DRIVE17_BANK4_PIN09_V 0x00000040 +#define BP_PINCTRL_DRIVE17_BANK4_PIN09_MA 4 +#define BM_PINCTRL_DRIVE17_BANK4_PIN09_MA 0x00000030 +#define BF_PINCTRL_DRIVE17_BANK4_PIN09_MA(v) \ + (((v) << 4) & BM_PINCTRL_DRIVE17_BANK4_PIN09_MA) +#define BM_PINCTRL_DRIVE17_RSRVD0 0x00000008 +#define BM_PINCTRL_DRIVE17_BANK4_PIN08_V 0x00000004 +#define BP_PINCTRL_DRIVE17_BANK4_PIN08_MA 0 +#define BM_PINCTRL_DRIVE17_BANK4_PIN08_MA 0x00000003 +#define BF_PINCTRL_DRIVE17_BANK4_PIN08_MA(v) \ + (((v) << 0) & BM_PINCTRL_DRIVE17_BANK4_PIN08_MA) + +#define HW_PINCTRL_DRIVE18 0x00000420 +#define HW_PINCTRL_DRIVE18_SET 0x00000424 +#define HW_PINCTRL_DRIVE18_CLR 0x00000428 +#define HW_PINCTRL_DRIVE18_TOG 0x0000042c + +#define BP_PINCTRL_DRIVE18_RSRVD3 20 +#define BM_PINCTRL_DRIVE18_RSRVD3 0xFFF00000 +#define BF_PINCTRL_DRIVE18_RSRVD3(v) \ + (((v) << 20) & BM_PINCTRL_DRIVE18_RSRVD3) +#define BM_PINCTRL_DRIVE18_RSRVD2 0x00080000 +#define BM_PINCTRL_DRIVE18_BANK4_PIN20_V 0x00040000 +#define BP_PINCTRL_DRIVE18_BANK4_PIN20_MA 16 +#define BM_PINCTRL_DRIVE18_BANK4_PIN20_MA 0x00030000 +#define BF_PINCTRL_DRIVE18_BANK4_PIN20_MA(v) \ + (((v) << 16) & BM_PINCTRL_DRIVE18_BANK4_PIN20_MA) +#define BP_PINCTRL_DRIVE18_RSRVD1 4 +#define BM_PINCTRL_DRIVE18_RSRVD1 0x0000FFF0 +#define BF_PINCTRL_DRIVE18_RSRVD1(v) \ + (((v) << 4) & BM_PINCTRL_DRIVE18_RSRVD1) +#define BM_PINCTRL_DRIVE18_RSRVD0 0x00000008 +#define BM_PINCTRL_DRIVE18_BANK4_PIN16_V 0x00000004 +#define BP_PINCTRL_DRIVE18_BANK4_PIN16_MA 0 +#define BM_PINCTRL_DRIVE18_BANK4_PIN16_MA 0x00000003 +#define BF_PINCTRL_DRIVE18_BANK4_PIN16_MA(v) \ + (((v) << 0) & BM_PINCTRL_DRIVE18_BANK4_PIN16_MA) + +#define HW_PINCTRL_DRIVE19 0x00000430 +#define HW_PINCTRL_DRIVE19_SET 0x00000434 +#define HW_PINCTRL_DRIVE19_CLR 0x00000438 +#define HW_PINCTRL_DRIVE19_TOG 0x0000043c + +#define BP_PINCTRL_DRIVE19_RSRVD0 0 +#define BM_PINCTRL_DRIVE19_RSRVD0 0xFFFFFFFF +#define BF_PINCTRL_DRIVE19_RSRVD0(v) (v) + +#define HW_PINCTRL_PULL0 0x00000600 +#define HW_PINCTRL_PULL0_SET 0x00000604 +#define HW_PINCTRL_PULL0_CLR 0x00000608 +#define HW_PINCTRL_PULL0_TOG 0x0000060c + +#define BP_PINCTRL_PULL0_RSRVD1 29 +#define BM_PINCTRL_PULL0_RSRVD1 0xE0000000 +#define BF_PINCTRL_PULL0_RSRVD1(v) \ + (((v) << 29) & BM_PINCTRL_PULL0_RSRVD1) +#define BM_PINCTRL_PULL0_BANK0_PIN28 0x10000000 +#define BM_PINCTRL_PULL0_BANK0_PIN27 0x08000000 +#define BM_PINCTRL_PULL0_BANK0_PIN26 0x04000000 +#define BM_PINCTRL_PULL0_BANK0_PIN25 0x02000000 +#define BM_PINCTRL_PULL0_BANK0_PIN24 0x01000000 +#define BM_PINCTRL_PULL0_BANK0_PIN23 0x00800000 +#define BM_PINCTRL_PULL0_BANK0_PIN22 0x00400000 +#define BM_PINCTRL_PULL0_BANK0_PIN21 0x00200000 +#define BM_PINCTRL_PULL0_BANK0_PIN20 0x00100000 +#define BM_PINCTRL_PULL0_BANK0_PIN19 0x00080000 +#define BM_PINCTRL_PULL0_BANK0_PIN18 0x00040000 +#define BM_PINCTRL_PULL0_BANK0_PIN17 0x00020000 +#define BM_PINCTRL_PULL0_BANK0_PIN16 0x00010000 +#define BP_PINCTRL_PULL0_RSRVD0 8 +#define BM_PINCTRL_PULL0_RSRVD0 0x0000FF00 +#define BF_PINCTRL_PULL0_RSRVD0(v) \ + (((v) << 8) & BM_PINCTRL_PULL0_RSRVD0) +#define BM_PINCTRL_PULL0_BANK0_PIN07 0x00000080 +#define BM_PINCTRL_PULL0_BANK0_PIN06 0x00000040 +#define BM_PINCTRL_PULL0_BANK0_PIN05 0x00000020 +#define BM_PINCTRL_PULL0_BANK0_PIN04 0x00000010 +#define BM_PINCTRL_PULL0_BANK0_PIN03 0x00000008 +#define BM_PINCTRL_PULL0_BANK0_PIN02 0x00000004 +#define BM_PINCTRL_PULL0_BANK0_PIN01 0x00000002 +#define BM_PINCTRL_PULL0_BANK0_PIN00 0x00000001 + +#define HW_PINCTRL_PULL1 0x00000610 +#define HW_PINCTRL_PULL1_SET 0x00000614 +#define HW_PINCTRL_PULL1_CLR 0x00000618 +#define HW_PINCTRL_PULL1_TOG 0x0000061c + +#define BM_PINCTRL_PULL1_BANK1_PIN31 0x80000000 +#define BM_PINCTRL_PULL1_BANK1_PIN30 0x40000000 +#define BM_PINCTRL_PULL1_BANK1_PIN29 0x20000000 +#define BM_PINCTRL_PULL1_BANK1_PIN28 0x10000000 +#define BM_PINCTRL_PULL1_BANK1_PIN27 0x08000000 +#define BM_PINCTRL_PULL1_BANK1_PIN26 0x04000000 +#define BM_PINCTRL_PULL1_BANK1_PIN25 0x02000000 +#define BM_PINCTRL_PULL1_BANK1_PIN24 0x01000000 +#define BM_PINCTRL_PULL1_BANK1_PIN23 0x00800000 +#define BM_PINCTRL_PULL1_BANK1_PIN22 0x00400000 +#define BM_PINCTRL_PULL1_BANK1_PIN21 0x00200000 +#define BM_PINCTRL_PULL1_BANK1_PIN20 0x00100000 +#define BM_PINCTRL_PULL1_BANK1_PIN19 0x00080000 +#define BM_PINCTRL_PULL1_BANK1_PIN18 0x00040000 +#define BM_PINCTRL_PULL1_BANK1_PIN17 0x00020000 +#define BM_PINCTRL_PULL1_BANK1_PIN16 0x00010000 +#define BM_PINCTRL_PULL1_BANK1_PIN15 0x00008000 +#define BM_PINCTRL_PULL1_BANK1_PIN14 0x00004000 +#define BM_PINCTRL_PULL1_BANK1_PIN13 0x00002000 +#define BM_PINCTRL_PULL1_BANK1_PIN12 0x00001000 +#define BM_PINCTRL_PULL1_BANK1_PIN11 0x00000800 +#define BM_PINCTRL_PULL1_BANK1_PIN10 0x00000400 +#define BM_PINCTRL_PULL1_BANK1_PIN09 0x00000200 +#define BM_PINCTRL_PULL1_BANK1_PIN08 0x00000100 +#define BM_PINCTRL_PULL1_BANK1_PIN07 0x00000080 +#define BM_PINCTRL_PULL1_BANK1_PIN06 0x00000040 +#define BM_PINCTRL_PULL1_BANK1_PIN05 0x00000020 +#define BM_PINCTRL_PULL1_BANK1_PIN04 0x00000010 +#define BM_PINCTRL_PULL1_BANK1_PIN03 0x00000008 +#define BM_PINCTRL_PULL1_BANK1_PIN02 0x00000004 +#define BM_PINCTRL_PULL1_BANK1_PIN01 0x00000002 +#define BM_PINCTRL_PULL1_BANK1_PIN00 0x00000001 + +#define HW_PINCTRL_PULL2 0x00000620 +#define HW_PINCTRL_PULL2_SET 0x00000624 +#define HW_PINCTRL_PULL2_CLR 0x00000628 +#define HW_PINCTRL_PULL2_TOG 0x0000062c + +#define BP_PINCTRL_PULL2_RSRVD2 28 +#define BM_PINCTRL_PULL2_RSRVD2 0xF0000000 +#define BF_PINCTRL_PULL2_RSRVD2(v) \ + (((v) << 28) & BM_PINCTRL_PULL2_RSRVD2) +#define BM_PINCTRL_PULL2_BANK2_PIN27 0x08000000 +#define BM_PINCTRL_PULL2_BANK2_PIN26 0x04000000 +#define BM_PINCTRL_PULL2_BANK2_PIN25 0x02000000 +#define BM_PINCTRL_PULL2_BANK2_PIN24 0x01000000 +#define BP_PINCTRL_PULL2_RSRVD1 22 +#define BM_PINCTRL_PULL2_RSRVD1 0x00C00000 +#define BF_PINCTRL_PULL2_RSRVD1(v) \ + (((v) << 22) & BM_PINCTRL_PULL2_RSRVD1) +#define BM_PINCTRL_PULL2_BANK2_PIN21 0x00200000 +#define BM_PINCTRL_PULL2_BANK2_PIN20 0x00100000 +#define BM_PINCTRL_PULL2_BANK2_PIN19 0x00080000 +#define BM_PINCTRL_PULL2_BANK2_PIN18 0x00040000 +#define BM_PINCTRL_PULL2_BANK2_PIN17 0x00020000 +#define BM_PINCTRL_PULL2_BANK2_PIN16 0x00010000 +#define BM_PINCTRL_PULL2_BANK2_PIN15 0x00008000 +#define BM_PINCTRL_PULL2_BANK2_PIN14 0x00004000 +#define BM_PINCTRL_PULL2_BANK2_PIN13 0x00002000 +#define BM_PINCTRL_PULL2_BANK2_PIN12 0x00001000 +#define BM_PINCTRL_PULL2_RSRVD0 0x00000800 +#define BM_PINCTRL_PULL2_BANK2_PIN10 0x00000400 +#define BM_PINCTRL_PULL2_BANK2_PIN09 0x00000200 +#define BM_PINCTRL_PULL2_BANK2_PIN08 0x00000100 +#define BM_PINCTRL_PULL2_BANK2_PIN07 0x00000080 +#define BM_PINCTRL_PULL2_BANK2_PIN06 0x00000040 +#define BM_PINCTRL_PULL2_BANK2_PIN05 0x00000020 +#define BM_PINCTRL_PULL2_BANK2_PIN04 0x00000010 +#define BM_PINCTRL_PULL2_BANK2_PIN03 0x00000008 +#define BM_PINCTRL_PULL2_BANK2_PIN02 0x00000004 +#define BM_PINCTRL_PULL2_BANK2_PIN01 0x00000002 +#define BM_PINCTRL_PULL2_BANK2_PIN00 0x00000001 + +#define HW_PINCTRL_PULL3 0x00000630 +#define HW_PINCTRL_PULL3_SET 0x00000634 +#define HW_PINCTRL_PULL3_CLR 0x00000638 +#define HW_PINCTRL_PULL3_TOG 0x0000063c + +#define BM_PINCTRL_PULL3_RSRVD1 0x80000000 +#define BM_PINCTRL_PULL3_BANK3_PIN30 0x40000000 +#define BM_PINCTRL_PULL3_BANK3_PIN29 0x20000000 +#define BM_PINCTRL_PULL3_BANK3_PIN28 0x10000000 +#define BM_PINCTRL_PULL3_BANK3_PIN27 0x08000000 +#define BM_PINCTRL_PULL3_BANK3_PIN26 0x04000000 +#define BM_PINCTRL_PULL3_BANK3_PIN25 0x02000000 +#define BM_PINCTRL_PULL3_BANK3_PIN24 0x01000000 +#define BM_PINCTRL_PULL3_BANK3_PIN23 0x00800000 +#define BM_PINCTRL_PULL3_BANK3_PIN22 0x00400000 +#define BM_PINCTRL_PULL3_BANK3_PIN21 0x00200000 +#define BM_PINCTRL_PULL3_BANK3_PIN20 0x00100000 +#define BM_PINCTRL_PULL3_RSRVD0 0x00080000 +#define BM_PINCTRL_PULL3_BANK3_PIN18 0x00040000 +#define BM_PINCTRL_PULL3_BANK3_PIN17 0x00020000 +#define BM_PINCTRL_PULL3_BANK3_PIN16 0x00010000 +#define BM_PINCTRL_PULL3_BANK3_PIN15 0x00008000 +#define BM_PINCTRL_PULL3_BANK3_PIN14 0x00004000 +#define BM_PINCTRL_PULL3_BANK3_PIN13 0x00002000 +#define BM_PINCTRL_PULL3_BANK3_PIN12 0x00001000 +#define BM_PINCTRL_PULL3_BANK3_PIN11 0x00000800 +#define BM_PINCTRL_PULL3_BANK3_PIN10 0x00000400 +#define BM_PINCTRL_PULL3_BANK3_PIN09 0x00000200 +#define BM_PINCTRL_PULL3_BANK3_PIN08 0x00000100 +#define BM_PINCTRL_PULL3_BANK3_PIN07 0x00000080 +#define BM_PINCTRL_PULL3_BANK3_PIN06 0x00000040 +#define BM_PINCTRL_PULL3_BANK3_PIN05 0x00000020 +#define BM_PINCTRL_PULL3_BANK3_PIN04 0x00000010 +#define BM_PINCTRL_PULL3_BANK3_PIN03 0x00000008 +#define BM_PINCTRL_PULL3_BANK3_PIN02 0x00000004 +#define BM_PINCTRL_PULL3_BANK3_PIN01 0x00000002 +#define BM_PINCTRL_PULL3_BANK3_PIN00 0x00000001 + +#define HW_PINCTRL_PULL4 0x00000640 +#define HW_PINCTRL_PULL4_SET 0x00000644 +#define HW_PINCTRL_PULL4_CLR 0x00000648 +#define HW_PINCTRL_PULL4_TOG 0x0000064c + +#define BP_PINCTRL_PULL4_RSRVD1 21 +#define BM_PINCTRL_PULL4_RSRVD1 0xFFE00000 +#define BF_PINCTRL_PULL4_RSRVD1(v) \ + (((v) << 21) & BM_PINCTRL_PULL4_RSRVD1) +#define BM_PINCTRL_PULL4_BANK4_PIN20 0x00100000 +#define BP_PINCTRL_PULL4_RSRVD0 17 +#define BM_PINCTRL_PULL4_RSRVD0 0x000E0000 +#define BF_PINCTRL_PULL4_RSRVD0(v) \ + (((v) << 17) & BM_PINCTRL_PULL4_RSRVD0) +#define BM_PINCTRL_PULL4_BANK4_PIN16 0x00010000 +#define BM_PINCTRL_PULL4_BANK4_PIN15 0x00008000 +#define BM_PINCTRL_PULL4_BANK4_PIN14 0x00004000 +#define BM_PINCTRL_PULL4_BANK4_PIN13 0x00002000 +#define BM_PINCTRL_PULL4_BANK4_PIN12 0x00001000 +#define BM_PINCTRL_PULL4_BANK4_PIN11 0x00000800 +#define BM_PINCTRL_PULL4_BANK4_PIN10 0x00000400 +#define BM_PINCTRL_PULL4_BANK4_PIN09 0x00000200 +#define BM_PINCTRL_PULL4_BANK4_PIN08 0x00000100 +#define BM_PINCTRL_PULL4_BANK4_PIN07 0x00000080 +#define BM_PINCTRL_PULL4_BANK4_PIN06 0x00000040 +#define BM_PINCTRL_PULL4_BANK4_PIN05 0x00000020 +#define BM_PINCTRL_PULL4_BANK4_PIN04 0x00000010 +#define BM_PINCTRL_PULL4_BANK4_PIN03 0x00000008 +#define BM_PINCTRL_PULL4_BANK4_PIN02 0x00000004 +#define BM_PINCTRL_PULL4_BANK4_PIN01 0x00000002 +#define BM_PINCTRL_PULL4_BANK4_PIN00 0x00000001 + +#define HW_PINCTRL_PULL5 0x00000650 +#define HW_PINCTRL_PULL5_SET 0x00000654 +#define HW_PINCTRL_PULL5_CLR 0x00000658 +#define HW_PINCTRL_PULL5_TOG 0x0000065c + +#define BP_PINCTRL_PULL5_RSRVD1 27 +#define BM_PINCTRL_PULL5_RSRVD1 0xF8000000 +#define BF_PINCTRL_PULL5_RSRVD1(v) \ + (((v) << 27) & BM_PINCTRL_PULL5_RSRVD1) +#define BM_PINCTRL_PULL5_BANK5_PIN26 0x04000000 +#define BP_PINCTRL_PULL5_RSRVD0 24 +#define BM_PINCTRL_PULL5_RSRVD0 0x03000000 +#define BF_PINCTRL_PULL5_RSRVD0(v) \ + (((v) << 24) & BM_PINCTRL_PULL5_RSRVD0) +#define BM_PINCTRL_PULL5_BANK5_PIN23 0x00800000 +#define BM_PINCTRL_PULL5_BANK5_PIN22 0x00400000 +#define BM_PINCTRL_PULL5_BANK5_PIN21 0x00200000 +#define BM_PINCTRL_PULL5_BANK5_PIN20 0x00100000 +#define BM_PINCTRL_PULL5_BANK5_PIN19 0x00080000 +#define BM_PINCTRL_PULL5_BANK5_PIN18 0x00040000 +#define BM_PINCTRL_PULL5_BANK5_PIN17 0x00020000 +#define BM_PINCTRL_PULL5_BANK5_PIN16 0x00010000 +#define BM_PINCTRL_PULL5_BANK5_PIN15 0x00008000 +#define BM_PINCTRL_PULL5_BANK5_PIN14 0x00004000 +#define BM_PINCTRL_PULL5_BANK5_PIN13 0x00002000 +#define BM_PINCTRL_PULL5_BANK5_PIN12 0x00001000 +#define BM_PINCTRL_PULL5_BANK5_PIN11 0x00000800 +#define BM_PINCTRL_PULL5_BANK5_PIN10 0x00000400 +#define BM_PINCTRL_PULL5_BANK5_PIN09 0x00000200 +#define BM_PINCTRL_PULL5_BANK5_PIN08 0x00000100 +#define BM_PINCTRL_PULL5_BANK5_PIN07 0x00000080 +#define BM_PINCTRL_PULL5_BANK5_PIN06 0x00000040 +#define BM_PINCTRL_PULL5_BANK5_PIN05 0x00000020 +#define BM_PINCTRL_PULL5_BANK5_PIN04 0x00000010 +#define BM_PINCTRL_PULL5_BANK5_PIN03 0x00000008 +#define BM_PINCTRL_PULL5_BANK5_PIN02 0x00000004 +#define BM_PINCTRL_PULL5_BANK5_PIN01 0x00000002 +#define BM_PINCTRL_PULL5_BANK5_PIN00 0x00000001 + +#define HW_PINCTRL_PULL6 0x00000660 +#define HW_PINCTRL_PULL6_SET 0x00000664 +#define HW_PINCTRL_PULL6_CLR 0x00000668 +#define HW_PINCTRL_PULL6_TOG 0x0000066c + +#define BP_PINCTRL_PULL6_RSRVD1 25 +#define BM_PINCTRL_PULL6_RSRVD1 0xFE000000 +#define BF_PINCTRL_PULL6_RSRVD1(v) \ + (((v) << 25) & BM_PINCTRL_PULL6_RSRVD1) +#define BM_PINCTRL_PULL6_BANK6_PIN24 0x01000000 +#define BM_PINCTRL_PULL6_BANK6_PIN23 0x00800000 +#define BM_PINCTRL_PULL6_BANK6_PIN22 0x00400000 +#define BM_PINCTRL_PULL6_BANK6_PIN21 0x00200000 +#define BM_PINCTRL_PULL6_BANK6_PIN20 0x00100000 +#define BM_PINCTRL_PULL6_BANK6_PIN19 0x00080000 +#define BM_PINCTRL_PULL6_BANK6_PIN18 0x00040000 +#define BM_PINCTRL_PULL6_BANK6_PIN17 0x00020000 +#define BM_PINCTRL_PULL6_BANK6_PIN16 0x00010000 +#define BM_PINCTRL_PULL6_RSRVD0 0x00008000 +#define BM_PINCTRL_PULL6_BANK6_PIN14 0x00004000 +#define BM_PINCTRL_PULL6_BANK6_PIN13 0x00002000 +#define BM_PINCTRL_PULL6_BANK6_PIN12 0x00001000 +#define BM_PINCTRL_PULL6_BANK6_PIN11 0x00000800 +#define BM_PINCTRL_PULL6_BANK6_PIN10 0x00000400 +#define BM_PINCTRL_PULL6_BANK6_PIN09 0x00000200 +#define BM_PINCTRL_PULL6_BANK6_PIN08 0x00000100 +#define BM_PINCTRL_PULL6_BANK6_PIN07 0x00000080 +#define BM_PINCTRL_PULL6_BANK6_PIN06 0x00000040 +#define BM_PINCTRL_PULL6_BANK6_PIN05 0x00000020 +#define BM_PINCTRL_PULL6_BANK6_PIN04 0x00000010 +#define BM_PINCTRL_PULL6_BANK6_PIN03 0x00000008 +#define BM_PINCTRL_PULL6_BANK6_PIN02 0x00000004 +#define BM_PINCTRL_PULL6_BANK6_PIN01 0x00000002 +#define BM_PINCTRL_PULL6_BANK6_PIN00 0x00000001 + +#define HW_PINCTRL_DOUT0 0x00000700 +#define HW_PINCTRL_DOUT0_SET 0x00000704 +#define HW_PINCTRL_DOUT0_CLR 0x00000708 +#define HW_PINCTRL_DOUT0_TOG 0x0000070c + +#define BP_PINCTRL_DOUT0_RSRVD1 29 +#define BM_PINCTRL_DOUT0_RSRVD1 0xE0000000 +#define BF_PINCTRL_DOUT0_RSRVD1(v) \ + (((v) << 29) & BM_PINCTRL_DOUT0_RSRVD1) +#define BP_PINCTRL_DOUT0_DOUT 0 +#define BM_PINCTRL_DOUT0_DOUT 0x1FFFFFFF +#define BF_PINCTRL_DOUT0_DOUT(v) \ + (((v) << 0) & BM_PINCTRL_DOUT0_DOUT) + +#define HW_PINCTRL_DOUT1 0x00000710 +#define HW_PINCTRL_DOUT1_SET 0x00000714 +#define HW_PINCTRL_DOUT1_CLR 0x00000718 +#define HW_PINCTRL_DOUT1_TOG 0x0000071c + +#define BP_PINCTRL_DOUT1_DOUT 0 +#define BM_PINCTRL_DOUT1_DOUT 0xFFFFFFFF +#define BF_PINCTRL_DOUT1_DOUT(v) (v) + +#define HW_PINCTRL_DOUT2 0x00000720 +#define HW_PINCTRL_DOUT2_SET 0x00000724 +#define HW_PINCTRL_DOUT2_CLR 0x00000728 +#define HW_PINCTRL_DOUT2_TOG 0x0000072c + +#define BP_PINCTRL_DOUT2_RSRVD1 28 +#define BM_PINCTRL_DOUT2_RSRVD1 0xF0000000 +#define BF_PINCTRL_DOUT2_RSRVD1(v) \ + (((v) << 28) & BM_PINCTRL_DOUT2_RSRVD1) +#define BP_PINCTRL_DOUT2_DOUT 0 +#define BM_PINCTRL_DOUT2_DOUT 0x0FFFFFFF +#define BF_PINCTRL_DOUT2_DOUT(v) \ + (((v) << 0) & BM_PINCTRL_DOUT2_DOUT) + +#define HW_PINCTRL_DOUT3 0x00000730 +#define HW_PINCTRL_DOUT3_SET 0x00000734 +#define HW_PINCTRL_DOUT3_CLR 0x00000738 +#define HW_PINCTRL_DOUT3_TOG 0x0000073c + +#define BM_PINCTRL_DOUT3_RSRVD1 0x80000000 +#define BP_PINCTRL_DOUT3_DOUT 0 +#define BM_PINCTRL_DOUT3_DOUT 0x7FFFFFFF +#define BF_PINCTRL_DOUT3_DOUT(v) \ + (((v) << 0) & BM_PINCTRL_DOUT3_DOUT) + +#define HW_PINCTRL_DOUT4 0x00000740 +#define HW_PINCTRL_DOUT4_SET 0x00000744 +#define HW_PINCTRL_DOUT4_CLR 0x00000748 +#define HW_PINCTRL_DOUT4_TOG 0x0000074c + +#define BP_PINCTRL_DOUT4_RSRVD1 21 +#define BM_PINCTRL_DOUT4_RSRVD1 0xFFE00000 +#define BF_PINCTRL_DOUT4_RSRVD1(v) \ + (((v) << 21) & BM_PINCTRL_DOUT4_RSRVD1) +#define BP_PINCTRL_DOUT4_DOUT 0 +#define BM_PINCTRL_DOUT4_DOUT 0x001FFFFF +#define BF_PINCTRL_DOUT4_DOUT(v) \ + (((v) << 0) & BM_PINCTRL_DOUT4_DOUT) + +#define HW_PINCTRL_DIN0 0x00000900 +#define HW_PINCTRL_DIN0_SET 0x00000904 +#define HW_PINCTRL_DIN0_CLR 0x00000908 +#define HW_PINCTRL_DIN0_TOG 0x0000090c + +#define BP_PINCTRL_DIN0_RSRVD1 29 +#define BM_PINCTRL_DIN0_RSRVD1 0xE0000000 +#define BF_PINCTRL_DIN0_RSRVD1(v) \ + (((v) << 29) & BM_PINCTRL_DIN0_RSRVD1) +#define BP_PINCTRL_DIN0_DIN 0 +#define BM_PINCTRL_DIN0_DIN 0x1FFFFFFF +#define BF_PINCTRL_DIN0_DIN(v) \ + (((v) << 0) & BM_PINCTRL_DIN0_DIN) + +#define HW_PINCTRL_DIN1 0x00000910 +#define HW_PINCTRL_DIN1_SET 0x00000914 +#define HW_PINCTRL_DIN1_CLR 0x00000918 +#define HW_PINCTRL_DIN1_TOG 0x0000091c + +#define BP_PINCTRL_DIN1_DIN 0 +#define BM_PINCTRL_DIN1_DIN 0xFFFFFFFF +#define BF_PINCTRL_DIN1_DIN(v) (v) + +#define HW_PINCTRL_DIN2 0x00000920 +#define HW_PINCTRL_DIN2_SET 0x00000924 +#define HW_PINCTRL_DIN2_CLR 0x00000928 +#define HW_PINCTRL_DIN2_TOG 0x0000092c + +#define BP_PINCTRL_DIN2_RSRVD1 28 +#define BM_PINCTRL_DIN2_RSRVD1 0xF0000000 +#define BF_PINCTRL_DIN2_RSRVD1(v) \ + (((v) << 28) & BM_PINCTRL_DIN2_RSRVD1) +#define BP_PINCTRL_DIN2_DIN 0 +#define BM_PINCTRL_DIN2_DIN 0x0FFFFFFF +#define BF_PINCTRL_DIN2_DIN(v) \ + (((v) << 0) & BM_PINCTRL_DIN2_DIN) + +#define HW_PINCTRL_DIN3 0x00000930 +#define HW_PINCTRL_DIN3_SET 0x00000934 +#define HW_PINCTRL_DIN3_CLR 0x00000938 +#define HW_PINCTRL_DIN3_TOG 0x0000093c + +#define BM_PINCTRL_DIN3_RSRVD1 0x80000000 +#define BP_PINCTRL_DIN3_DIN 0 +#define BM_PINCTRL_DIN3_DIN 0x7FFFFFFF +#define BF_PINCTRL_DIN3_DIN(v) \ + (((v) << 0) & BM_PINCTRL_DIN3_DIN) + +#define HW_PINCTRL_DIN4 0x00000940 +#define HW_PINCTRL_DIN4_SET 0x00000944 +#define HW_PINCTRL_DIN4_CLR 0x00000948 +#define HW_PINCTRL_DIN4_TOG 0x0000094c + +#define BP_PINCTRL_DIN4_RSRVD1 21 +#define BM_PINCTRL_DIN4_RSRVD1 0xFFE00000 +#define BF_PINCTRL_DIN4_RSRVD1(v) \ + (((v) << 21) & BM_PINCTRL_DIN4_RSRVD1) +#define BP_PINCTRL_DIN4_DIN 0 +#define BM_PINCTRL_DIN4_DIN 0x001FFFFF +#define BF_PINCTRL_DIN4_DIN(v) \ + (((v) << 0) & BM_PINCTRL_DIN4_DIN) + +#define HW_PINCTRL_DOE0 0x00000b00 +#define HW_PINCTRL_DOE0_SET 0x00000b04 +#define HW_PINCTRL_DOE0_CLR 0x00000b08 +#define HW_PINCTRL_DOE0_TOG 0x00000b0c + +#define BP_PINCTRL_DOE0_RSRVD1 29 +#define BM_PINCTRL_DOE0_RSRVD1 0xE0000000 +#define BF_PINCTRL_DOE0_RSRVD1(v) \ + (((v) << 29) & BM_PINCTRL_DOE0_RSRVD1) +#define BP_PINCTRL_DOE0_DOE 0 +#define BM_PINCTRL_DOE0_DOE 0x1FFFFFFF +#define BF_PINCTRL_DOE0_DOE(v) \ + (((v) << 0) & BM_PINCTRL_DOE0_DOE) + +#define HW_PINCTRL_DOE1 0x00000b10 +#define HW_PINCTRL_DOE1_SET 0x00000b14 +#define HW_PINCTRL_DOE1_CLR 0x00000b18 +#define HW_PINCTRL_DOE1_TOG 0x00000b1c + +#define BP_PINCTRL_DOE1_DOE 0 +#define BM_PINCTRL_DOE1_DOE 0xFFFFFFFF +#define BF_PINCTRL_DOE1_DOE(v) (v) + +#define HW_PINCTRL_DOE2 0x00000b20 +#define HW_PINCTRL_DOE2_SET 0x00000b24 +#define HW_PINCTRL_DOE2_CLR 0x00000b28 +#define HW_PINCTRL_DOE2_TOG 0x00000b2c + +#define BP_PINCTRL_DOE2_RSRVD1 28 +#define BM_PINCTRL_DOE2_RSRVD1 0xF0000000 +#define BF_PINCTRL_DOE2_RSRVD1(v) \ + (((v) << 28) & BM_PINCTRL_DOE2_RSRVD1) +#define BP_PINCTRL_DOE2_DOE 0 +#define BM_PINCTRL_DOE2_DOE 0x0FFFFFFF +#define BF_PINCTRL_DOE2_DOE(v) \ + (((v) << 0) & BM_PINCTRL_DOE2_DOE) + +#define HW_PINCTRL_DOE3 0x00000b30 +#define HW_PINCTRL_DOE3_SET 0x00000b34 +#define HW_PINCTRL_DOE3_CLR 0x00000b38 +#define HW_PINCTRL_DOE3_TOG 0x00000b3c + +#define BM_PINCTRL_DOE3_RSRVD1 0x80000000 +#define BP_PINCTRL_DOE3_DOE 0 +#define BM_PINCTRL_DOE3_DOE 0x7FFFFFFF +#define BF_PINCTRL_DOE3_DOE(v) \ + (((v) << 0) & BM_PINCTRL_DOE3_DOE) + +#define HW_PINCTRL_DOE4 0x00000b40 +#define HW_PINCTRL_DOE4_SET 0x00000b44 +#define HW_PINCTRL_DOE4_CLR 0x00000b48 +#define HW_PINCTRL_DOE4_TOG 0x00000b4c + +#define BP_PINCTRL_DOE4_RSRVD1 21 +#define BM_PINCTRL_DOE4_RSRVD1 0xFFE00000 +#define BF_PINCTRL_DOE4_RSRVD1(v) \ + (((v) << 21) & BM_PINCTRL_DOE4_RSRVD1) +#define BP_PINCTRL_DOE4_DOE 0 +#define BM_PINCTRL_DOE4_DOE 0x001FFFFF +#define BF_PINCTRL_DOE4_DOE(v) \ + (((v) << 0) & BM_PINCTRL_DOE4_DOE) + +#define HW_PINCTRL_PIN2IRQ0 0x00001000 +#define HW_PINCTRL_PIN2IRQ0_SET 0x00001004 +#define HW_PINCTRL_PIN2IRQ0_CLR 0x00001008 +#define HW_PINCTRL_PIN2IRQ0_TOG 0x0000100c + +#define BP_PINCTRL_PIN2IRQ0_RSRVD1 29 +#define BM_PINCTRL_PIN2IRQ0_RSRVD1 0xE0000000 +#define BF_PINCTRL_PIN2IRQ0_RSRVD1(v) \ + (((v) << 29) & BM_PINCTRL_PIN2IRQ0_RSRVD1) +#define BP_PINCTRL_PIN2IRQ0_PIN2IRQ 0 +#define BM_PINCTRL_PIN2IRQ0_PIN2IRQ 0x1FFFFFFF +#define BF_PINCTRL_PIN2IRQ0_PIN2IRQ(v) \ + (((v) << 0) & BM_PINCTRL_PIN2IRQ0_PIN2IRQ) + +#define HW_PINCTRL_PIN2IRQ1 0x00001010 +#define HW_PINCTRL_PIN2IRQ1_SET 0x00001014 +#define HW_PINCTRL_PIN2IRQ1_CLR 0x00001018 +#define HW_PINCTRL_PIN2IRQ1_TOG 0x0000101c + +#define BP_PINCTRL_PIN2IRQ1_PIN2IRQ 0 +#define BM_PINCTRL_PIN2IRQ1_PIN2IRQ 0xFFFFFFFF +#define BF_PINCTRL_PIN2IRQ1_PIN2IRQ(v) (v) + +#define HW_PINCTRL_PIN2IRQ2 0x00001020 +#define HW_PINCTRL_PIN2IRQ2_SET 0x00001024 +#define HW_PINCTRL_PIN2IRQ2_CLR 0x00001028 +#define HW_PINCTRL_PIN2IRQ2_TOG 0x0000102c + +#define BP_PINCTRL_PIN2IRQ2_RSRVD1 28 +#define BM_PINCTRL_PIN2IRQ2_RSRVD1 0xF0000000 +#define BF_PINCTRL_PIN2IRQ2_RSRVD1(v) \ + (((v) << 28) & BM_PINCTRL_PIN2IRQ2_RSRVD1) +#define BP_PINCTRL_PIN2IRQ2_PIN2IRQ 0 +#define BM_PINCTRL_PIN2IRQ2_PIN2IRQ 0x0FFFFFFF +#define BF_PINCTRL_PIN2IRQ2_PIN2IRQ(v) \ + (((v) << 0) & BM_PINCTRL_PIN2IRQ2_PIN2IRQ) + +#define HW_PINCTRL_PIN2IRQ3 0x00001030 +#define HW_PINCTRL_PIN2IRQ3_SET 0x00001034 +#define HW_PINCTRL_PIN2IRQ3_CLR 0x00001038 +#define HW_PINCTRL_PIN2IRQ3_TOG 0x0000103c + +#define BM_PINCTRL_PIN2IRQ3_RSRVD1 0x80000000 +#define BP_PINCTRL_PIN2IRQ3_PIN2IRQ 0 +#define BM_PINCTRL_PIN2IRQ3_PIN2IRQ 0x7FFFFFFF +#define BF_PINCTRL_PIN2IRQ3_PIN2IRQ(v) \ + (((v) << 0) & BM_PINCTRL_PIN2IRQ3_PIN2IRQ) + +#define HW_PINCTRL_PIN2IRQ4 0x00001040 +#define HW_PINCTRL_PIN2IRQ4_SET 0x00001044 +#define HW_PINCTRL_PIN2IRQ4_CLR 0x00001048 +#define HW_PINCTRL_PIN2IRQ4_TOG 0x0000104c + +#define BP_PINCTRL_PIN2IRQ4_RSRVD1 21 +#define BM_PINCTRL_PIN2IRQ4_RSRVD1 0xFFE00000 +#define BF_PINCTRL_PIN2IRQ4_RSRVD1(v) \ + (((v) << 21) & BM_PINCTRL_PIN2IRQ4_RSRVD1) +#define BP_PINCTRL_PIN2IRQ4_PIN2IRQ 0 +#define BM_PINCTRL_PIN2IRQ4_PIN2IRQ 0x001FFFFF +#define BF_PINCTRL_PIN2IRQ4_PIN2IRQ(v) \ + (((v) << 0) & BM_PINCTRL_PIN2IRQ4_PIN2IRQ) + +#define HW_PINCTRL_IRQEN0 0x00001100 +#define HW_PINCTRL_IRQEN0_SET 0x00001104 +#define HW_PINCTRL_IRQEN0_CLR 0x00001108 +#define HW_PINCTRL_IRQEN0_TOG 0x0000110c + +#define BP_PINCTRL_IRQEN0_RSRVD1 29 +#define BM_PINCTRL_IRQEN0_RSRVD1 0xE0000000 +#define BF_PINCTRL_IRQEN0_RSRVD1(v) \ + (((v) << 29) & BM_PINCTRL_IRQEN0_RSRVD1) +#define BP_PINCTRL_IRQEN0_IRQEN 0 +#define BM_PINCTRL_IRQEN0_IRQEN 0x1FFFFFFF +#define BF_PINCTRL_IRQEN0_IRQEN(v) \ + (((v) << 0) & BM_PINCTRL_IRQEN0_IRQEN) + +#define HW_PINCTRL_IRQEN1 0x00001110 +#define HW_PINCTRL_IRQEN1_SET 0x00001114 +#define HW_PINCTRL_IRQEN1_CLR 0x00001118 +#define HW_PINCTRL_IRQEN1_TOG 0x0000111c + +#define BP_PINCTRL_IRQEN1_IRQEN 0 +#define BM_PINCTRL_IRQEN1_IRQEN 0xFFFFFFFF +#define BF_PINCTRL_IRQEN1_IRQEN(v) (v) + +#define HW_PINCTRL_IRQEN2 0x00001120 +#define HW_PINCTRL_IRQEN2_SET 0x00001124 +#define HW_PINCTRL_IRQEN2_CLR 0x00001128 +#define HW_PINCTRL_IRQEN2_TOG 0x0000112c + +#define BP_PINCTRL_IRQEN2_RSRVD1 28 +#define BM_PINCTRL_IRQEN2_RSRVD1 0xF0000000 +#define BF_PINCTRL_IRQEN2_RSRVD1(v) \ + (((v) << 28) & BM_PINCTRL_IRQEN2_RSRVD1) +#define BP_PINCTRL_IRQEN2_IRQEN 0 +#define BM_PINCTRL_IRQEN2_IRQEN 0x0FFFFFFF +#define BF_PINCTRL_IRQEN2_IRQEN(v) \ + (((v) << 0) & BM_PINCTRL_IRQEN2_IRQEN) + +#define HW_PINCTRL_IRQEN3 0x00001130 +#define HW_PINCTRL_IRQEN3_SET 0x00001134 +#define HW_PINCTRL_IRQEN3_CLR 0x00001138 +#define HW_PINCTRL_IRQEN3_TOG 0x0000113c + +#define BM_PINCTRL_IRQEN3_RSRVD1 0x80000000 +#define BP_PINCTRL_IRQEN3_IRQEN 0 +#define BM_PINCTRL_IRQEN3_IRQEN 0x7FFFFFFF +#define BF_PINCTRL_IRQEN3_IRQEN(v) \ + (((v) << 0) & BM_PINCTRL_IRQEN3_IRQEN) + +#define HW_PINCTRL_IRQEN4 0x00001140 +#define HW_PINCTRL_IRQEN4_SET 0x00001144 +#define HW_PINCTRL_IRQEN4_CLR 0x00001148 +#define HW_PINCTRL_IRQEN4_TOG 0x0000114c + +#define BP_PINCTRL_IRQEN4_RSRVD1 21 +#define BM_PINCTRL_IRQEN4_RSRVD1 0xFFE00000 +#define BF_PINCTRL_IRQEN4_RSRVD1(v) \ + (((v) << 21) & BM_PINCTRL_IRQEN4_RSRVD1) +#define BP_PINCTRL_IRQEN4_IRQEN 0 +#define BM_PINCTRL_IRQEN4_IRQEN 0x001FFFFF +#define BF_PINCTRL_IRQEN4_IRQEN(v) \ + (((v) << 0) & BM_PINCTRL_IRQEN4_IRQEN) + +#define HW_PINCTRL_IRQLEVEL0 0x00001200 +#define HW_PINCTRL_IRQLEVEL0_SET 0x00001204 +#define HW_PINCTRL_IRQLEVEL0_CLR 0x00001208 +#define HW_PINCTRL_IRQLEVEL0_TOG 0x0000120c + +#define BP_PINCTRL_IRQLEVEL0_RSRVD1 29 +#define BM_PINCTRL_IRQLEVEL0_RSRVD1 0xE0000000 +#define BF_PINCTRL_IRQLEVEL0_RSRVD1(v) \ + (((v) << 29) & BM_PINCTRL_IRQLEVEL0_RSRVD1) +#define BP_PINCTRL_IRQLEVEL0_IRQLEVEL 0 +#define BM_PINCTRL_IRQLEVEL0_IRQLEVEL 0x1FFFFFFF +#define BF_PINCTRL_IRQLEVEL0_IRQLEVEL(v) \ + (((v) << 0) & BM_PINCTRL_IRQLEVEL0_IRQLEVEL) + +#define HW_PINCTRL_IRQLEVEL1 0x00001210 +#define HW_PINCTRL_IRQLEVEL1_SET 0x00001214 +#define HW_PINCTRL_IRQLEVEL1_CLR 0x00001218 +#define HW_PINCTRL_IRQLEVEL1_TOG 0x0000121c + +#define BP_PINCTRL_IRQLEVEL1_IRQLEVEL 0 +#define BM_PINCTRL_IRQLEVEL1_IRQLEVEL 0xFFFFFFFF +#define BF_PINCTRL_IRQLEVEL1_IRQLEVEL(v) (v) + +#define HW_PINCTRL_IRQLEVEL2 0x00001220 +#define HW_PINCTRL_IRQLEVEL2_SET 0x00001224 +#define HW_PINCTRL_IRQLEVEL2_CLR 0x00001228 +#define HW_PINCTRL_IRQLEVEL2_TOG 0x0000122c + +#define BP_PINCTRL_IRQLEVEL2_RSRVD1 28 +#define BM_PINCTRL_IRQLEVEL2_RSRVD1 0xF0000000 +#define BF_PINCTRL_IRQLEVEL2_RSRVD1(v) \ + (((v) << 28) & BM_PINCTRL_IRQLEVEL2_RSRVD1) +#define BP_PINCTRL_IRQLEVEL2_IRQLEVEL 0 +#define BM_PINCTRL_IRQLEVEL2_IRQLEVEL 0x0FFFFFFF +#define BF_PINCTRL_IRQLEVEL2_IRQLEVEL(v) \ + (((v) << 0) & BM_PINCTRL_IRQLEVEL2_IRQLEVEL) + +#define HW_PINCTRL_IRQLEVEL3 0x00001230 +#define HW_PINCTRL_IRQLEVEL3_SET 0x00001234 +#define HW_PINCTRL_IRQLEVEL3_CLR 0x00001238 +#define HW_PINCTRL_IRQLEVEL3_TOG 0x0000123c + +#define BM_PINCTRL_IRQLEVEL3_RSRVD1 0x80000000 +#define BP_PINCTRL_IRQLEVEL3_IRQLEVEL 0 +#define BM_PINCTRL_IRQLEVEL3_IRQLEVEL 0x7FFFFFFF +#define BF_PINCTRL_IRQLEVEL3_IRQLEVEL(v) \ + (((v) << 0) & BM_PINCTRL_IRQLEVEL3_IRQLEVEL) + +#define HW_PINCTRL_IRQLEVEL4 0x00001240 +#define HW_PINCTRL_IRQLEVEL4_SET 0x00001244 +#define HW_PINCTRL_IRQLEVEL4_CLR 0x00001248 +#define HW_PINCTRL_IRQLEVEL4_TOG 0x0000124c + +#define BP_PINCTRL_IRQLEVEL4_RSRVD1 21 +#define BM_PINCTRL_IRQLEVEL4_RSRVD1 0xFFE00000 +#define BF_PINCTRL_IRQLEVEL4_RSRVD1(v) \ + (((v) << 21) & BM_PINCTRL_IRQLEVEL4_RSRVD1) +#define BP_PINCTRL_IRQLEVEL4_IRQLEVEL 0 +#define BM_PINCTRL_IRQLEVEL4_IRQLEVEL 0x001FFFFF +#define BF_PINCTRL_IRQLEVEL4_IRQLEVEL(v) \ + (((v) << 0) & BM_PINCTRL_IRQLEVEL4_IRQLEVEL) + +#define HW_PINCTRL_IRQPOL0 0x00001300 +#define HW_PINCTRL_IRQPOL0_SET 0x00001304 +#define HW_PINCTRL_IRQPOL0_CLR 0x00001308 +#define HW_PINCTRL_IRQPOL0_TOG 0x0000130c + +#define BP_PINCTRL_IRQPOL0_RSRVD1 29 +#define BM_PINCTRL_IRQPOL0_RSRVD1 0xE0000000 +#define BF_PINCTRL_IRQPOL0_RSRVD1(v) \ + (((v) << 29) & BM_PINCTRL_IRQPOL0_RSRVD1) +#define BP_PINCTRL_IRQPOL0_IRQPOL 0 +#define BM_PINCTRL_IRQPOL0_IRQPOL 0x1FFFFFFF +#define BF_PINCTRL_IRQPOL0_IRQPOL(v) \ + (((v) << 0) & BM_PINCTRL_IRQPOL0_IRQPOL) + +#define HW_PINCTRL_IRQPOL1 0x00001310 +#define HW_PINCTRL_IRQPOL1_SET 0x00001314 +#define HW_PINCTRL_IRQPOL1_CLR 0x00001318 +#define HW_PINCTRL_IRQPOL1_TOG 0x0000131c + +#define BP_PINCTRL_IRQPOL1_IRQPOL 0 +#define BM_PINCTRL_IRQPOL1_IRQPOL 0xFFFFFFFF +#define BF_PINCTRL_IRQPOL1_IRQPOL(v) (v) + +#define HW_PINCTRL_IRQPOL2 0x00001320 +#define HW_PINCTRL_IRQPOL2_SET 0x00001324 +#define HW_PINCTRL_IRQPOL2_CLR 0x00001328 +#define HW_PINCTRL_IRQPOL2_TOG 0x0000132c + +#define BP_PINCTRL_IRQPOL2_RSRVD1 28 +#define BM_PINCTRL_IRQPOL2_RSRVD1 0xF0000000 +#define BF_PINCTRL_IRQPOL2_RSRVD1(v) \ + (((v) << 28) & BM_PINCTRL_IRQPOL2_RSRVD1) +#define BP_PINCTRL_IRQPOL2_IRQPOL 0 +#define BM_PINCTRL_IRQPOL2_IRQPOL 0x0FFFFFFF +#define BF_PINCTRL_IRQPOL2_IRQPOL(v) \ + (((v) << 0) & BM_PINCTRL_IRQPOL2_IRQPOL) + +#define HW_PINCTRL_IRQPOL3 0x00001330 +#define HW_PINCTRL_IRQPOL3_SET 0x00001334 +#define HW_PINCTRL_IRQPOL3_CLR 0x00001338 +#define HW_PINCTRL_IRQPOL3_TOG 0x0000133c + +#define BM_PINCTRL_IRQPOL3_RSRVD1 0x80000000 +#define BP_PINCTRL_IRQPOL3_IRQPOL 0 +#define BM_PINCTRL_IRQPOL3_IRQPOL 0x7FFFFFFF +#define BF_PINCTRL_IRQPOL3_IRQPOL(v) \ + (((v) << 0) & BM_PINCTRL_IRQPOL3_IRQPOL) + +#define HW_PINCTRL_IRQPOL4 0x00001340 +#define HW_PINCTRL_IRQPOL4_SET 0x00001344 +#define HW_PINCTRL_IRQPOL4_CLR 0x00001348 +#define HW_PINCTRL_IRQPOL4_TOG 0x0000134c + +#define BP_PINCTRL_IRQPOL4_RSRVD1 21 +#define BM_PINCTRL_IRQPOL4_RSRVD1 0xFFE00000 +#define BF_PINCTRL_IRQPOL4_RSRVD1(v) \ + (((v) << 21) & BM_PINCTRL_IRQPOL4_RSRVD1) +#define BP_PINCTRL_IRQPOL4_IRQPOL 0 +#define BM_PINCTRL_IRQPOL4_IRQPOL 0x001FFFFF +#define BF_PINCTRL_IRQPOL4_IRQPOL(v) \ + (((v) << 0) & BM_PINCTRL_IRQPOL4_IRQPOL) + +#define HW_PINCTRL_IRQSTAT0 0x00001400 +#define HW_PINCTRL_IRQSTAT0_SET 0x00001404 +#define HW_PINCTRL_IRQSTAT0_CLR 0x00001408 +#define HW_PINCTRL_IRQSTAT0_TOG 0x0000140c + +#define BP_PINCTRL_IRQSTAT0_RSRVD1 29 +#define BM_PINCTRL_IRQSTAT0_RSRVD1 0xE0000000 +#define BF_PINCTRL_IRQSTAT0_RSRVD1(v) \ + (((v) << 29) & BM_PINCTRL_IRQSTAT0_RSRVD1) +#define BP_PINCTRL_IRQSTAT0_IRQSTAT 0 +#define BM_PINCTRL_IRQSTAT0_IRQSTAT 0x1FFFFFFF +#define BF_PINCTRL_IRQSTAT0_IRQSTAT(v) \ + (((v) << 0) & BM_PINCTRL_IRQSTAT0_IRQSTAT) + +#define HW_PINCTRL_IRQSTAT1 0x00001410 +#define HW_PINCTRL_IRQSTAT1_SET 0x00001414 +#define HW_PINCTRL_IRQSTAT1_CLR 0x00001418 +#define HW_PINCTRL_IRQSTAT1_TOG 0x0000141c + +#define BP_PINCTRL_IRQSTAT1_IRQSTAT 0 +#define BM_PINCTRL_IRQSTAT1_IRQSTAT 0xFFFFFFFF +#define BF_PINCTRL_IRQSTAT1_IRQSTAT(v) (v) + +#define HW_PINCTRL_IRQSTAT2 0x00001420 +#define HW_PINCTRL_IRQSTAT2_SET 0x00001424 +#define HW_PINCTRL_IRQSTAT2_CLR 0x00001428 +#define HW_PINCTRL_IRQSTAT2_TOG 0x0000142c + +#define BP_PINCTRL_IRQSTAT2_RSRVD1 28 +#define BM_PINCTRL_IRQSTAT2_RSRVD1 0xF0000000 +#define BF_PINCTRL_IRQSTAT2_RSRVD1(v) \ + (((v) << 28) & BM_PINCTRL_IRQSTAT2_RSRVD1) +#define BP_PINCTRL_IRQSTAT2_IRQSTAT 0 +#define BM_PINCTRL_IRQSTAT2_IRQSTAT 0x0FFFFFFF +#define BF_PINCTRL_IRQSTAT2_IRQSTAT(v) \ + (((v) << 0) & BM_PINCTRL_IRQSTAT2_IRQSTAT) + +#define HW_PINCTRL_IRQSTAT3 0x00001430 +#define HW_PINCTRL_IRQSTAT3_SET 0x00001434 +#define HW_PINCTRL_IRQSTAT3_CLR 0x00001438 +#define HW_PINCTRL_IRQSTAT3_TOG 0x0000143c + +#define BM_PINCTRL_IRQSTAT3_RSRVD1 0x80000000 +#define BP_PINCTRL_IRQSTAT3_IRQSTAT 0 +#define BM_PINCTRL_IRQSTAT3_IRQSTAT 0x7FFFFFFF +#define BF_PINCTRL_IRQSTAT3_IRQSTAT(v) \ + (((v) << 0) & BM_PINCTRL_IRQSTAT3_IRQSTAT) + +#define HW_PINCTRL_IRQSTAT4 0x00001440 +#define HW_PINCTRL_IRQSTAT4_SET 0x00001444 +#define HW_PINCTRL_IRQSTAT4_CLR 0x00001448 +#define HW_PINCTRL_IRQSTAT4_TOG 0x0000144c + +#define BP_PINCTRL_IRQSTAT4_RSRVD1 21 +#define BM_PINCTRL_IRQSTAT4_RSRVD1 0xFFE00000 +#define BF_PINCTRL_IRQSTAT4_RSRVD1(v) \ + (((v) << 21) & BM_PINCTRL_IRQSTAT4_RSRVD1) +#define BP_PINCTRL_IRQSTAT4_IRQSTAT 0 +#define BM_PINCTRL_IRQSTAT4_IRQSTAT 0x001FFFFF +#define BF_PINCTRL_IRQSTAT4_IRQSTAT(v) \ + (((v) << 0) & BM_PINCTRL_IRQSTAT4_IRQSTAT) + +#define HW_PINCTRL_EMI_ODT_CTRL 0x00001a40 +#define HW_PINCTRL_EMI_ODT_CTRL_SET 0x00001a44 +#define HW_PINCTRL_EMI_ODT_CTRL_CLR 0x00001a48 +#define HW_PINCTRL_EMI_ODT_CTRL_TOG 0x00001a4c + +#define BP_PINCTRL_EMI_ODT_CTRL_RSRVD1 28 +#define BM_PINCTRL_EMI_ODT_CTRL_RSRVD1 0xF0000000 +#define BF_PINCTRL_EMI_ODT_CTRL_RSRVD1(v) \ + (((v) << 28) & BM_PINCTRL_EMI_ODT_CTRL_RSRVD1) +#define BP_PINCTRL_EMI_ODT_CTRL_ADDRESS_CALIB 26 +#define BM_PINCTRL_EMI_ODT_CTRL_ADDRESS_CALIB 0x0C000000 +#define BF_PINCTRL_EMI_ODT_CTRL_ADDRESS_CALIB(v) \ + (((v) << 26) & BM_PINCTRL_EMI_ODT_CTRL_ADDRESS_CALIB) +#define BP_PINCTRL_EMI_ODT_CTRL_ADDRESS_TLOAD 24 +#define BM_PINCTRL_EMI_ODT_CTRL_ADDRESS_TLOAD 0x03000000 +#define BF_PINCTRL_EMI_ODT_CTRL_ADDRESS_TLOAD(v) \ + (((v) << 24) & BM_PINCTRL_EMI_ODT_CTRL_ADDRESS_TLOAD) +#define BP_PINCTRL_EMI_ODT_CTRL_CONTROL_CALIB 22 +#define BM_PINCTRL_EMI_ODT_CTRL_CONTROL_CALIB 0x00C00000 +#define BF_PINCTRL_EMI_ODT_CTRL_CONTROL_CALIB(v) \ + (((v) << 22) & BM_PINCTRL_EMI_ODT_CTRL_CONTROL_CALIB) +#define BP_PINCTRL_EMI_ODT_CTRL_CONTROL_TLOAD 20 +#define BM_PINCTRL_EMI_ODT_CTRL_CONTROL_TLOAD 0x00300000 +#define BF_PINCTRL_EMI_ODT_CTRL_CONTROL_TLOAD(v) \ + (((v) << 20) & BM_PINCTRL_EMI_ODT_CTRL_CONTROL_TLOAD) +#define BP_PINCTRL_EMI_ODT_CTRL_DUALPAD_CALIB 18 +#define BM_PINCTRL_EMI_ODT_CTRL_DUALPAD_CALIB 0x000C0000 +#define BF_PINCTRL_EMI_ODT_CTRL_DUALPAD_CALIB(v) \ + (((v) << 18) & BM_PINCTRL_EMI_ODT_CTRL_DUALPAD_CALIB) +#define BP_PINCTRL_EMI_ODT_CTRL_DUALPAD_TLOAD 16 +#define BM_PINCTRL_EMI_ODT_CTRL_DUALPAD_TLOAD 0x00030000 +#define BF_PINCTRL_EMI_ODT_CTRL_DUALPAD_TLOAD(v) \ + (((v) << 16) & BM_PINCTRL_EMI_ODT_CTRL_DUALPAD_TLOAD) +#define BP_PINCTRL_EMI_ODT_CTRL_SLICE3_CALIB 14 +#define BM_PINCTRL_EMI_ODT_CTRL_SLICE3_CALIB 0x0000C000 +#define BF_PINCTRL_EMI_ODT_CTRL_SLICE3_CALIB(v) \ + (((v) << 14) & BM_PINCTRL_EMI_ODT_CTRL_SLICE3_CALIB) +#define BP_PINCTRL_EMI_ODT_CTRL_SLICE3_TLOAD 12 +#define BM_PINCTRL_EMI_ODT_CTRL_SLICE3_TLOAD 0x00003000 +#define BF_PINCTRL_EMI_ODT_CTRL_SLICE3_TLOAD(v) \ + (((v) << 12) & BM_PINCTRL_EMI_ODT_CTRL_SLICE3_TLOAD) +#define BP_PINCTRL_EMI_ODT_CTRL_SLICE2_CALIB 10 +#define BM_PINCTRL_EMI_ODT_CTRL_SLICE2_CALIB 0x00000C00 +#define BF_PINCTRL_EMI_ODT_CTRL_SLICE2_CALIB(v) \ + (((v) << 10) & BM_PINCTRL_EMI_ODT_CTRL_SLICE2_CALIB) +#define BP_PINCTRL_EMI_ODT_CTRL_SLICE2_TLOAD 8 +#define BM_PINCTRL_EMI_ODT_CTRL_SLICE2_TLOAD 0x00000300 +#define BF_PINCTRL_EMI_ODT_CTRL_SLICE2_TLOAD(v) \ + (((v) << 8) & BM_PINCTRL_EMI_ODT_CTRL_SLICE2_TLOAD) +#define BP_PINCTRL_EMI_ODT_CTRL_SLICE1_CALIB 6 +#define BM_PINCTRL_EMI_ODT_CTRL_SLICE1_CALIB 0x000000C0 +#define BF_PINCTRL_EMI_ODT_CTRL_SLICE1_CALIB(v) \ + (((v) << 6) & BM_PINCTRL_EMI_ODT_CTRL_SLICE1_CALIB) +#define BP_PINCTRL_EMI_ODT_CTRL_SLICE1_TLOAD 4 +#define BM_PINCTRL_EMI_ODT_CTRL_SLICE1_TLOAD 0x00000030 +#define BF_PINCTRL_EMI_ODT_CTRL_SLICE1_TLOAD(v) \ + (((v) << 4) & BM_PINCTRL_EMI_ODT_CTRL_SLICE1_TLOAD) +#define BP_PINCTRL_EMI_ODT_CTRL_SLICE0_CALIB 2 +#define BM_PINCTRL_EMI_ODT_CTRL_SLICE0_CALIB 0x0000000C +#define BF_PINCTRL_EMI_ODT_CTRL_SLICE0_CALIB(v) \ + (((v) << 2) & BM_PINCTRL_EMI_ODT_CTRL_SLICE0_CALIB) +#define BP_PINCTRL_EMI_ODT_CTRL_SLICE0_TLOAD 0 +#define BM_PINCTRL_EMI_ODT_CTRL_SLICE0_TLOAD 0x00000003 +#define BF_PINCTRL_EMI_ODT_CTRL_SLICE0_TLOAD(v) \ + (((v) << 0) & BM_PINCTRL_EMI_ODT_CTRL_SLICE0_TLOAD) + +#define HW_PINCTRL_EMI_DS_CTRL 0x00001b80 +#define HW_PINCTRL_EMI_DS_CTRL_SET 0x00001b84 +#define HW_PINCTRL_EMI_DS_CTRL_CLR 0x00001b88 +#define HW_PINCTRL_EMI_DS_CTRL_TOG 0x00001b8c + +#define BP_PINCTRL_EMI_DS_CTRL_RSRVD1 18 +#define BM_PINCTRL_EMI_DS_CTRL_RSRVD1 0xFFFC0000 +#define BF_PINCTRL_EMI_DS_CTRL_RSRVD1(v) \ + (((v) << 18) & BM_PINCTRL_EMI_DS_CTRL_RSRVD1) +#define BP_PINCTRL_EMI_DS_CTRL_DDR_MODE 16 +#define BM_PINCTRL_EMI_DS_CTRL_DDR_MODE 0x00030000 +#define BF_PINCTRL_EMI_DS_CTRL_DDR_MODE(v) \ + (((v) << 16) & BM_PINCTRL_EMI_DS_CTRL_DDR_MODE) +#define BV_PINCTRL_EMI_DS_CTRL_DDR_MODE__mDDR 00 +#define BV_PINCTRL_EMI_DS_CTRL_DDR_MODE__GPIO 01 +#define BV_PINCTRL_EMI_DS_CTRL_DDR_MODE__LVDDR2 10 +#define BV_PINCTRL_EMI_DS_CTRL_DDR_MODE__DDR2 11 +#define BP_PINCTRL_EMI_DS_CTRL_RSRVD0 14 +#define BM_PINCTRL_EMI_DS_CTRL_RSRVD0 0x0000C000 +#define BF_PINCTRL_EMI_DS_CTRL_RSRVD0(v) \ + (((v) << 14) & BM_PINCTRL_EMI_DS_CTRL_RSRVD0) +#define BP_PINCTRL_EMI_DS_CTRL_ADDRESS_MA 12 +#define BM_PINCTRL_EMI_DS_CTRL_ADDRESS_MA 0x00003000 +#define BF_PINCTRL_EMI_DS_CTRL_ADDRESS_MA(v) \ + (((v) << 12) & BM_PINCTRL_EMI_DS_CTRL_ADDRESS_MA) +#define BP_PINCTRL_EMI_DS_CTRL_CONTROL_MA 10 +#define BM_PINCTRL_EMI_DS_CTRL_CONTROL_MA 0x00000C00 +#define BF_PINCTRL_EMI_DS_CTRL_CONTROL_MA(v) \ + (((v) << 10) & BM_PINCTRL_EMI_DS_CTRL_CONTROL_MA) +#define BP_PINCTRL_EMI_DS_CTRL_DUALPAD_MA 8 +#define BM_PINCTRL_EMI_DS_CTRL_DUALPAD_MA 0x00000300 +#define BF_PINCTRL_EMI_DS_CTRL_DUALPAD_MA(v) \ + (((v) << 8) & BM_PINCTRL_EMI_DS_CTRL_DUALPAD_MA) +#define BP_PINCTRL_EMI_DS_CTRL_SLICE3_MA 6 +#define BM_PINCTRL_EMI_DS_CTRL_SLICE3_MA 0x000000C0 +#define BF_PINCTRL_EMI_DS_CTRL_SLICE3_MA(v) \ + (((v) << 6) & BM_PINCTRL_EMI_DS_CTRL_SLICE3_MA) +#define BP_PINCTRL_EMI_DS_CTRL_SLICE2_MA 4 +#define BM_PINCTRL_EMI_DS_CTRL_SLICE2_MA 0x00000030 +#define BF_PINCTRL_EMI_DS_CTRL_SLICE2_MA(v) \ + (((v) << 4) & BM_PINCTRL_EMI_DS_CTRL_SLICE2_MA) +#define BP_PINCTRL_EMI_DS_CTRL_SLICE1_MA 2 +#define BM_PINCTRL_EMI_DS_CTRL_SLICE1_MA 0x0000000C +#define BF_PINCTRL_EMI_DS_CTRL_SLICE1_MA(v) \ + (((v) << 2) & BM_PINCTRL_EMI_DS_CTRL_SLICE1_MA) +#define BP_PINCTRL_EMI_DS_CTRL_SLICE0_MA 0 +#define BM_PINCTRL_EMI_DS_CTRL_SLICE0_MA 0x00000003 +#define BF_PINCTRL_EMI_DS_CTRL_SLICE0_MA(v) \ + (((v) << 0) & BM_PINCTRL_EMI_DS_CTRL_SLICE0_MA) +#endif /* __ARCH_ARM___PINCTRL_H */ diff --git a/include/asm-arm/arch-mx28/regs-ssp.h b/include/asm-arm/arch-mx28/regs-ssp.h new file mode 100644 index 0000000000..96ee211777 --- /dev/null +++ b/include/asm-arm/arch-mx28/regs-ssp.h @@ -0,0 +1,471 @@ +/* + * Freescale SSP Register Definitions + * + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * This file is created by xml file. Don't Edit it. + * + * Xml Revision: 4.0 + * Template revision: 26195 + */ + +#ifndef __ARCH_ARM___SSP_H +#define __ARCH_ARM___SSP_H + + +#define HW_SSP_CTRL0 (0x00000000) +#define HW_SSP_CTRL0_SET (0x00000004) +#define HW_SSP_CTRL0_CLR (0x00000008) +#define HW_SSP_CTRL0_TOG (0x0000000c) + +#define BM_SSP_CTRL0_SFTRST 0x80000000 +#define BM_SSP_CTRL0_CLKGATE 0x40000000 +#define BM_SSP_CTRL0_RUN 0x20000000 +#define BM_SSP_CTRL0_SDIO_IRQ_CHECK 0x10000000 +#define BM_SSP_CTRL0_LOCK_CS 0x08000000 +#define BM_SSP_CTRL0_IGNORE_CRC 0x04000000 +#define BM_SSP_CTRL0_READ 0x02000000 +#define BM_SSP_CTRL0_DATA_XFER 0x01000000 +#define BP_SSP_CTRL0_BUS_WIDTH 22 +#define BM_SSP_CTRL0_BUS_WIDTH 0x00C00000 +#define BF_SSP_CTRL0_BUS_WIDTH(v) \ + (((v) << 22) & BM_SSP_CTRL0_BUS_WIDTH) +#define BV_SSP_CTRL0_BUS_WIDTH__ONE_BIT 0x0 +#define BV_SSP_CTRL0_BUS_WIDTH__FOUR_BIT 0x1 +#define BV_SSP_CTRL0_BUS_WIDTH__EIGHT_BIT 0x2 +#define BM_SSP_CTRL0_WAIT_FOR_IRQ 0x00200000 +#define BM_SSP_CTRL0_WAIT_FOR_CMD 0x00100000 +#define BM_SSP_CTRL0_LONG_RESP 0x00080000 +#define BM_SSP_CTRL0_CHECK_RESP 0x00040000 +#define BM_SSP_CTRL0_GET_RESP 0x00020000 +#define BM_SSP_CTRL0_ENABLE 0x00010000 +#define BP_SSP_CTRL0_RSVD0 0 +#define BM_SSP_CTRL0_RSVD0 0x0000FFFF +#define BF_SSP_CTRL0_RSVD0(v) \ + (((v) << 0) & BM_SSP_CTRL0_RSVD0) + +#define HW_SSP_CMD0 (0x00000010) +#define HW_SSP_CMD0_SET (0x00000014) +#define HW_SSP_CMD0_CLR (0x00000018) +#define HW_SSP_CMD0_TOG (0x0000001c) + +#define BP_SSP_CMD0_RSVD0 27 +#define BM_SSP_CMD0_RSVD0 0xF8000000 +#define BF_SSP_CMD0_RSVD0(v) \ + (((v) << 27) & BM_SSP_CMD0_RSVD0) +#define BM_SSP_CMD0_SOFT_TERMINATE 0x04000000 +#define BM_SSP_CMD0_DBL_DATA_RATE_EN 0x02000000 +#define BM_SSP_CMD0_PRIM_BOOT_OP_EN 0x01000000 +#define BM_SSP_CMD0_BOOT_ACK_EN 0x00800000 +#define BM_SSP_CMD0_SLOW_CLKING_EN 0x00400000 +#define BM_SSP_CMD0_CONT_CLKING_EN 0x00200000 +#define BM_SSP_CMD0_APPEND_8CYC 0x00100000 +#define BP_SSP_CMD0_RSVD1 8 +#define BM_SSP_CMD0_RSVD1 0x000FFF00 +#define BF_SSP_CMD0_RSVD1(v) \ + (((v) << 8) & BM_SSP_CMD0_RSVD1) +#define BP_SSP_CMD0_CMD 0 +#define BM_SSP_CMD0_CMD 0x000000FF +#define BF_SSP_CMD0_CMD(v) \ + (((v) << 0) & BM_SSP_CMD0_CMD) +#define BV_SSP_CMD0_CMD__MMC_GO_IDLE_STATE 0x00 +#define BV_SSP_CMD0_CMD__MMC_SEND_OP_COND 0x01 +#define BV_SSP_CMD0_CMD__MMC_ALL_SEND_CID 0x02 +#define BV_SSP_CMD0_CMD__MMC_SET_RELATIVE_ADDR 0x03 +#define BV_SSP_CMD0_CMD__MMC_SET_DSR 0x04 +#define BV_SSP_CMD0_CMD__MMC_RESERVED_5 0x05 +#define BV_SSP_CMD0_CMD__MMC_SWITCH 0x06 +#define BV_SSP_CMD0_CMD__MMC_SELECT_DESELECT_CARD 0x07 +#define BV_SSP_CMD0_CMD__MMC_SEND_EXT_CSD 0x08 +#define BV_SSP_CMD0_CMD__MMC_SEND_CSD 0x09 +#define BV_SSP_CMD0_CMD__MMC_SEND_CID 0x0A +#define BV_SSP_CMD0_CMD__MMC_READ_DAT_UNTIL_STOP 0x0B +#define BV_SSP_CMD0_CMD__MMC_STOP_TRANSMISSION 0x0C +#define BV_SSP_CMD0_CMD__MMC_SEND_STATUS 0x0D +#define BV_SSP_CMD0_CMD__MMC_BUSTEST_R 0x0E +#define BV_SSP_CMD0_CMD__MMC_GO_INACTIVE_STATE 0x0F +#define BV_SSP_CMD0_CMD__MMC_SET_BLOCKLEN 0x10 +#define BV_SSP_CMD0_CMD__MMC_READ_SINGLE_BLOCK 0x11 +#define BV_SSP_CMD0_CMD__MMC_READ_MULTIPLE_BLOCK 0x12 +#define BV_SSP_CMD0_CMD__MMC_BUSTEST_W 0x13 +#define BV_SSP_CMD0_CMD__MMC_WRITE_DAT_UNTIL_STOP 0x14 +#define BV_SSP_CMD0_CMD__MMC_SET_BLOCK_COUNT 0x17 +#define BV_SSP_CMD0_CMD__MMC_WRITE_BLOCK 0x18 +#define BV_SSP_CMD0_CMD__MMC_WRITE_MULTIPLE_BLOCK 0x19 +#define BV_SSP_CMD0_CMD__MMC_PROGRAM_CID 0x1A +#define BV_SSP_CMD0_CMD__MMC_PROGRAM_CSD 0x1B +#define BV_SSP_CMD0_CMD__MMC_SET_WRITE_PROT 0x1C +#define BV_SSP_CMD0_CMD__MMC_CLR_WRITE_PROT 0x1D +#define BV_SSP_CMD0_CMD__MMC_SEND_WRITE_PROT 0x1E +#define BV_SSP_CMD0_CMD__MMC_ERASE_GROUP_START 0x23 +#define BV_SSP_CMD0_CMD__MMC_ERASE_GROUP_END 0x24 +#define BV_SSP_CMD0_CMD__MMC_ERASE 0x26 +#define BV_SSP_CMD0_CMD__MMC_FAST_IO 0x27 +#define BV_SSP_CMD0_CMD__MMC_GO_IRQ_STATE 0x28 +#define BV_SSP_CMD0_CMD__MMC_LOCK_UNLOCK 0x2A +#define BV_SSP_CMD0_CMD__MMC_APP_CMD 0x37 +#define BV_SSP_CMD0_CMD__MMC_GEN_CMD 0x38 +#define BV_SSP_CMD0_CMD__SD_GO_IDLE_STATE 0x00 +#define BV_SSP_CMD0_CMD__SD_ALL_SEND_CID 0x02 +#define BV_SSP_CMD0_CMD__SD_SEND_RELATIVE_ADDR 0x03 +#define BV_SSP_CMD0_CMD__SD_SET_DSR 0x04 +#define BV_SSP_CMD0_CMD__SD_IO_SEND_OP_COND 0x05 +#define BV_SSP_CMD0_CMD__SD_SELECT_DESELECT_CARD 0x07 +#define BV_SSP_CMD0_CMD__SD_SEND_CSD 0x09 +#define BV_SSP_CMD0_CMD__SD_SEND_CID 0x0A +#define BV_SSP_CMD0_CMD__SD_STOP_TRANSMISSION 0x0C +#define BV_SSP_CMD0_CMD__SD_SEND_STATUS 0x0D +#define BV_SSP_CMD0_CMD__SD_GO_INACTIVE_STATE 0x0F +#define BV_SSP_CMD0_CMD__SD_SET_BLOCKLEN 0x10 +#define BV_SSP_CMD0_CMD__SD_READ_SINGLE_BLOCK 0x11 +#define BV_SSP_CMD0_CMD__SD_READ_MULTIPLE_BLOCK 0x12 +#define BV_SSP_CMD0_CMD__SD_WRITE_BLOCK 0x18 +#define BV_SSP_CMD0_CMD__SD_WRITE_MULTIPLE_BLOCK 0x19 +#define BV_SSP_CMD0_CMD__SD_PROGRAM_CSD 0x1B +#define BV_SSP_CMD0_CMD__SD_SET_WRITE_PROT 0x1C +#define BV_SSP_CMD0_CMD__SD_CLR_WRITE_PROT 0x1D +#define BV_SSP_CMD0_CMD__SD_SEND_WRITE_PROT 0x1E +#define BV_SSP_CMD0_CMD__SD_ERASE_WR_BLK_START 0x20 +#define BV_SSP_CMD0_CMD__SD_ERASE_WR_BLK_END 0x21 +#define BV_SSP_CMD0_CMD__SD_ERASE_GROUP_START 0x23 +#define BV_SSP_CMD0_CMD__SD_ERASE_GROUP_END 0x24 +#define BV_SSP_CMD0_CMD__SD_ERASE 0x26 +#define BV_SSP_CMD0_CMD__SD_LOCK_UNLOCK 0x2A +#define BV_SSP_CMD0_CMD__SD_IO_RW_DIRECT 0x34 +#define BV_SSP_CMD0_CMD__SD_IO_RW_EXTENDED 0x35 +#define BV_SSP_CMD0_CMD__SD_APP_CMD 0x37 +#define BV_SSP_CMD0_CMD__SD_GEN_CMD 0x38 + +#define HW_SSP_CMD1 (0x00000020) + +#define BP_SSP_CMD1_CMD_ARG 0 +#define BM_SSP_CMD1_CMD_ARG 0xFFFFFFFF +#define BF_SSP_CMD1_CMD_ARG(v) (v) + +#define HW_SSP_XFER_SIZE (0x00000030) + +#define BP_SSP_XFER_SIZE_XFER_COUNT 0 +#define BM_SSP_XFER_SIZE_XFER_COUNT 0xFFFFFFFF +#define BF_SSP_XFER_SIZE_XFER_COUNT(v) (v) + +#define HW_SSP_BLOCK_SIZE (0x00000040) + +#define BP_SSP_BLOCK_SIZE_RSVD0 28 +#define BM_SSP_BLOCK_SIZE_RSVD0 0xF0000000 +#define BF_SSP_BLOCK_SIZE_RSVD0(v) \ + (((v) << 28) & BM_SSP_BLOCK_SIZE_RSVD0) +#define BP_SSP_BLOCK_SIZE_BLOCK_COUNT 4 +#define BM_SSP_BLOCK_SIZE_BLOCK_COUNT 0x0FFFFFF0 +#define BF_SSP_BLOCK_SIZE_BLOCK_COUNT(v) \ + (((v) << 4) & BM_SSP_BLOCK_SIZE_BLOCK_COUNT) +#define BP_SSP_BLOCK_SIZE_BLOCK_SIZE 0 +#define BM_SSP_BLOCK_SIZE_BLOCK_SIZE 0x0000000F +#define BF_SSP_BLOCK_SIZE_BLOCK_SIZE(v) \ + (((v) << 0) & BM_SSP_BLOCK_SIZE_BLOCK_SIZE) + +#define HW_SSP_COMPREF (0x00000050) + +#define BP_SSP_COMPREF_REFERENCE 0 +#define BM_SSP_COMPREF_REFERENCE 0xFFFFFFFF +#define BF_SSP_COMPREF_REFERENCE(v) (v) + +#define HW_SSP_COMPMASK (0x00000060) + +#define BP_SSP_COMPMASK_MASK 0 +#define BM_SSP_COMPMASK_MASK 0xFFFFFFFF +#define BF_SSP_COMPMASK_MASK(v) (v) + +#define HW_SSP_TIMING (0x00000070) + +#define BP_SSP_TIMING_TIMEOUT 16 +#define BM_SSP_TIMING_TIMEOUT 0xFFFF0000 +#define BF_SSP_TIMING_TIMEOUT(v) \ + (((v) << 16) & BM_SSP_TIMING_TIMEOUT) +#define BP_SSP_TIMING_CLOCK_DIVIDE 8 +#define BM_SSP_TIMING_CLOCK_DIVIDE 0x0000FF00 +#define BF_SSP_TIMING_CLOCK_DIVIDE(v) \ + (((v) << 8) & BM_SSP_TIMING_CLOCK_DIVIDE) +#define BP_SSP_TIMING_CLOCK_RATE 0 +#define BM_SSP_TIMING_CLOCK_RATE 0x000000FF +#define BF_SSP_TIMING_CLOCK_RATE(v) \ + (((v) << 0) & BM_SSP_TIMING_CLOCK_RATE) + +#define HW_SSP_CTRL1 (0x00000080) +#define HW_SSP_CTRL1_SET (0x00000084) +#define HW_SSP_CTRL1_CLR (0x00000088) +#define HW_SSP_CTRL1_TOG (0x0000008c) + +#define BM_SSP_CTRL1_SDIO_IRQ 0x80000000 +#define BM_SSP_CTRL1_SDIO_IRQ_EN 0x40000000 +#define BM_SSP_CTRL1_RESP_ERR_IRQ 0x20000000 +#define BM_SSP_CTRL1_RESP_ERR_IRQ_EN 0x10000000 +#define BM_SSP_CTRL1_RESP_TIMEOUT_IRQ 0x08000000 +#define BM_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN 0x04000000 +#define BM_SSP_CTRL1_DATA_TIMEOUT_IRQ 0x02000000 +#define BM_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN 0x01000000 +#define BM_SSP_CTRL1_DATA_CRC_IRQ 0x00800000 +#define BM_SSP_CTRL1_DATA_CRC_IRQ_EN 0x00400000 +#define BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ 0x00200000 +#define BM_SSP_CTRL1_FIFO_UNDERRUN_EN 0x00100000 +#define BM_SSP_CTRL1_CEATA_CCS_ERR_IRQ 0x00080000 +#define BM_SSP_CTRL1_CEATA_CCS_ERR_IRQ_EN 0x00040000 +#define BM_SSP_CTRL1_RECV_TIMEOUT_IRQ 0x00020000 +#define BM_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN 0x00010000 +#define BM_SSP_CTRL1_FIFO_OVERRUN_IRQ 0x00008000 +#define BM_SSP_CTRL1_FIFO_OVERRUN_IRQ_EN 0x00004000 +#define BM_SSP_CTRL1_DMA_ENABLE 0x00002000 +#define BM_SSP_CTRL1_CEATA_CCS_ERR_EN 0x00001000 +#define BM_SSP_CTRL1_SLAVE_OUT_DISABLE 0x00000800 +#define BM_SSP_CTRL1_PHASE 0x00000400 +#define BM_SSP_CTRL1_POLARITY 0x00000200 +#define BM_SSP_CTRL1_SLAVE_MODE 0x00000100 +#define BP_SSP_CTRL1_WORD_LENGTH 4 +#define BM_SSP_CTRL1_WORD_LENGTH 0x000000F0 +#define BF_SSP_CTRL1_WORD_LENGTH(v) \ + (((v) << 4) & BM_SSP_CTRL1_WORD_LENGTH) +#define BV_SSP_CTRL1_WORD_LENGTH__RESERVED0 0x0 +#define BV_SSP_CTRL1_WORD_LENGTH__RESERVED1 0x1 +#define BV_SSP_CTRL1_WORD_LENGTH__RESERVED2 0x2 +#define BV_SSP_CTRL1_WORD_LENGTH__FOUR_BITS 0x3 +#define BV_SSP_CTRL1_WORD_LENGTH__EIGHT_BITS 0x7 +#define BV_SSP_CTRL1_WORD_LENGTH__SIXTEEN_BITS 0xF +#define BP_SSP_CTRL1_SSP_MODE 0 +#define BM_SSP_CTRL1_SSP_MODE 0x0000000F +#define BF_SSP_CTRL1_SSP_MODE(v) \ + (((v) << 0) & BM_SSP_CTRL1_SSP_MODE) +#define BV_SSP_CTRL1_SSP_MODE__SPI 0x0 +#define BV_SSP_CTRL1_SSP_MODE__SSI 0x1 +#define BV_SSP_CTRL1_SSP_MODE__SD_MMC 0x3 +#define BV_SSP_CTRL1_SSP_MODE__MS 0x4 + +#define HW_SSP_DATA (0x00000090) + +#define BP_SSP_DATA_DATA 0 +#define BM_SSP_DATA_DATA 0xFFFFFFFF +#define BF_SSP_DATA_DATA(v) (v) + +#define HW_SSP_SDRESP0 (0x000000a0) + +#define BP_SSP_SDRESP0_RESP0 0 +#define BM_SSP_SDRESP0_RESP0 0xFFFFFFFF +#define BF_SSP_SDRESP0_RESP0(v) (v) + +#define HW_SSP_SDRESP1 (0x000000b0) + +#define BP_SSP_SDRESP1_RESP1 0 +#define BM_SSP_SDRESP1_RESP1 0xFFFFFFFF +#define BF_SSP_SDRESP1_RESP1(v) (v) + +#define HW_SSP_SDRESP2 (0x000000c0) + +#define BP_SSP_SDRESP2_RESP2 0 +#define BM_SSP_SDRESP2_RESP2 0xFFFFFFFF +#define BF_SSP_SDRESP2_RESP2(v) (v) + +#define HW_SSP_SDRESP3 (0x000000d0) + +#define BP_SSP_SDRESP3_RESP3 0 +#define BM_SSP_SDRESP3_RESP3 0xFFFFFFFF +#define BF_SSP_SDRESP3_RESP3(v) (v) + +#define HW_SSP_DDR_CTRL (0x000000e0) + +#define BP_SSP_DDR_CTRL_DMA_BURST_TYPE 30 +#define BM_SSP_DDR_CTRL_DMA_BURST_TYPE 0xC0000000 +#define BF_SSP_DDR_CTRL_DMA_BURST_TYPE(v) \ + (((v) << 30) & BM_SSP_DDR_CTRL_DMA_BURST_TYPE) +#define BP_SSP_DDR_CTRL_RSVD0 2 +#define BM_SSP_DDR_CTRL_RSVD0 0x3FFFFFFC +#define BF_SSP_DDR_CTRL_RSVD0(v) \ + (((v) << 2) & BM_SSP_DDR_CTRL_RSVD0) +#define BM_SSP_DDR_CTRL_NIBBLE_POS 0x00000002 +#define BM_SSP_DDR_CTRL_TXCLK_DELAY_TYPE 0x00000001 + +#define HW_SSP_DLL_CTRL (0x000000f0) + +#define BP_SSP_DLL_CTRL_REF_UPDATE_INT 28 +#define BM_SSP_DLL_CTRL_REF_UPDATE_INT 0xF0000000 +#define BF_SSP_DLL_CTRL_REF_UPDATE_INT(v) \ + (((v) << 28) & BM_SSP_DLL_CTRL_REF_UPDATE_INT) +#define BP_SSP_DLL_CTRL_SLV_UPDATE_INT 20 +#define BM_SSP_DLL_CTRL_SLV_UPDATE_INT 0x0FF00000 +#define BF_SSP_DLL_CTRL_SLV_UPDATE_INT(v) \ + (((v) << 20) & BM_SSP_DLL_CTRL_SLV_UPDATE_INT) +#define BP_SSP_DLL_CTRL_RSVD1 16 +#define BM_SSP_DLL_CTRL_RSVD1 0x000F0000 +#define BF_SSP_DLL_CTRL_RSVD1(v) \ + (((v) << 16) & BM_SSP_DLL_CTRL_RSVD1) +#define BP_SSP_DLL_CTRL_SLV_OVERRIDE_VAL 10 +#define BM_SSP_DLL_CTRL_SLV_OVERRIDE_VAL 0x0000FC00 +#define BF_SSP_DLL_CTRL_SLV_OVERRIDE_VAL(v) \ + (((v) << 10) & BM_SSP_DLL_CTRL_SLV_OVERRIDE_VAL) +#define BM_SSP_DLL_CTRL_SLV_OVERRIDE 0x00000200 +#define BM_SSP_DLL_CTRL_RSVD0 0x00000100 +#define BM_SSP_DLL_CTRL_GATE_UPDATE 0x00000080 +#define BP_SSP_DLL_CTRL_SLV_DLY_TARGET 3 +#define BM_SSP_DLL_CTRL_SLV_DLY_TARGET 0x00000078 +#define BF_SSP_DLL_CTRL_SLV_DLY_TARGET(v) \ + (((v) << 3) & BM_SSP_DLL_CTRL_SLV_DLY_TARGET) +#define BM_SSP_DLL_CTRL_SLV_FORCE_UPD 0x00000004 +#define BM_SSP_DLL_CTRL_RESET 0x00000002 +#define BM_SSP_DLL_CTRL_ENABLE 0x00000001 + +#define HW_SSP_STATUS (0x00000100) + +#define BM_SSP_STATUS_PRESENT 0x80000000 +#define BM_SSP_STATUS_MS_PRESENT 0x40000000 +#define BM_SSP_STATUS_SD_PRESENT 0x20000000 +#define BM_SSP_STATUS_CARD_DETECT 0x10000000 +#define BP_SSP_STATUS_RSVD3 23 +#define BM_SSP_STATUS_RSVD3 0x0F800000 +#define BF_SSP_STATUS_RSVD3(v) \ + (((v) << 23) & BM_SSP_STATUS_RSVD3) +#define BM_SSP_STATUS_DMABURST 0x00400000 +#define BM_SSP_STATUS_DMASENSE 0x00200000 +#define BM_SSP_STATUS_DMATERM 0x00100000 +#define BM_SSP_STATUS_DMAREQ 0x00080000 +#define BM_SSP_STATUS_DMAEND 0x00040000 +#define BM_SSP_STATUS_SDIO_IRQ 0x00020000 +#define BM_SSP_STATUS_RESP_CRC_ERR 0x00010000 +#define BM_SSP_STATUS_RESP_ERR 0x00008000 +#define BM_SSP_STATUS_RESP_TIMEOUT 0x00004000 +#define BM_SSP_STATUS_DATA_CRC_ERR 0x00002000 +#define BM_SSP_STATUS_TIMEOUT 0x00001000 +#define BM_SSP_STATUS_RECV_TIMEOUT_STAT 0x00000800 +#define BM_SSP_STATUS_CEATA_CCS_ERR 0x00000400 +#define BM_SSP_STATUS_FIFO_OVRFLW 0x00000200 +#define BM_SSP_STATUS_FIFO_FULL 0x00000100 +#define BP_SSP_STATUS_RSVD1 6 +#define BM_SSP_STATUS_RSVD1 0x000000C0 +#define BF_SSP_STATUS_RSVD1(v) \ + (((v) << 6) & BM_SSP_STATUS_RSVD1) +#define BM_SSP_STATUS_FIFO_EMPTY 0x00000020 +#define BM_SSP_STATUS_FIFO_UNDRFLW 0x00000010 +#define BM_SSP_STATUS_CMD_BUSY 0x00000008 +#define BM_SSP_STATUS_DATA_BUSY 0x00000004 +#define BM_SSP_STATUS_RSVD0 0x00000002 +#define BM_SSP_STATUS_BUSY 0x00000001 + +#define HW_SSP_DLL_STS (0x00000110) + +#define BP_SSP_DLL_STS_RSVD0 14 +#define BM_SSP_DLL_STS_RSVD0 0xFFFFC000 +#define BF_SSP_DLL_STS_RSVD0(v) \ + (((v) << 14) & BM_SSP_DLL_STS_RSVD0) +#define BP_SSP_DLL_STS_REF_SEL 8 +#define BM_SSP_DLL_STS_REF_SEL 0x00003F00 +#define BF_SSP_DLL_STS_REF_SEL(v) \ + (((v) << 8) & BM_SSP_DLL_STS_REF_SEL) +#define BP_SSP_DLL_STS_SLV_SEL 2 +#define BM_SSP_DLL_STS_SLV_SEL 0x000000FC +#define BF_SSP_DLL_STS_SLV_SEL(v) \ + (((v) << 2) & BM_SSP_DLL_STS_SLV_SEL) +#define BM_SSP_DLL_STS_REF_LOCK 0x00000002 +#define BM_SSP_DLL_STS_SLV_LOCK 0x00000001 + +#define HW_SSP_DEBUG (0x00000120) + +#define BP_SSP_DEBUG_DATACRC_ERR 28 +#define BM_SSP_DEBUG_DATACRC_ERR 0xF0000000 +#define BF_SSP_DEBUG_DATACRC_ERR(v) \ + (((v) << 28) & BM_SSP_DEBUG_DATACRC_ERR) +#define BM_SSP_DEBUG_DATA_STALL 0x08000000 +#define BP_SSP_DEBUG_DAT_SM 24 +#define BM_SSP_DEBUG_DAT_SM 0x07000000 +#define BF_SSP_DEBUG_DAT_SM(v) \ + (((v) << 24) & BM_SSP_DEBUG_DAT_SM) +#define BV_SSP_DEBUG_DAT_SM__DSM_IDLE 0x0 +#define BV_SSP_DEBUG_DAT_SM__DSM_WORD 0x2 +#define BV_SSP_DEBUG_DAT_SM__DSM_CRC1 0x3 +#define BV_SSP_DEBUG_DAT_SM__DSM_CRC2 0x4 +#define BV_SSP_DEBUG_DAT_SM__DSM_END 0x5 +#define BP_SSP_DEBUG_MSTK_SM 20 +#define BM_SSP_DEBUG_MSTK_SM 0x00F00000 +#define BF_SSP_DEBUG_MSTK_SM(v) \ + (((v) << 20) & BM_SSP_DEBUG_MSTK_SM) +#define BV_SSP_DEBUG_MSTK_SM__MSTK_IDLE 0x0 +#define BV_SSP_DEBUG_MSTK_SM__MSTK_CKON 0x1 +#define BV_SSP_DEBUG_MSTK_SM__MSTK_BS1 0x2 +#define BV_SSP_DEBUG_MSTK_SM__MSTK_TPC 0x3 +#define BV_SSP_DEBUG_MSTK_SM__MSTK_BS2 0x4 +#define BV_SSP_DEBUG_MSTK_SM__MSTK_HDSHK 0x5 +#define BV_SSP_DEBUG_MSTK_SM__MSTK_BS3 0x6 +#define BV_SSP_DEBUG_MSTK_SM__MSTK_RW 0x7 +#define BV_SSP_DEBUG_MSTK_SM__MSTK_CRC1 0x8 +#define BV_SSP_DEBUG_MSTK_SM__MSTK_CRC2 0x9 +#define BV_SSP_DEBUG_MSTK_SM__MSTK_BS0 0xA +#define BV_SSP_DEBUG_MSTK_SM__MSTK_END1 0xB +#define BV_SSP_DEBUG_MSTK_SM__MSTK_END2W 0xC +#define BV_SSP_DEBUG_MSTK_SM__MSTK_END2R 0xD +#define BV_SSP_DEBUG_MSTK_SM__MSTK_DONE 0xE +#define BM_SSP_DEBUG_CMD_OE 0x00080000 +#define BP_SSP_DEBUG_DMA_SM 16 +#define BM_SSP_DEBUG_DMA_SM 0x00070000 +#define BF_SSP_DEBUG_DMA_SM(v) \ + (((v) << 16) & BM_SSP_DEBUG_DMA_SM) +#define BV_SSP_DEBUG_DMA_SM__DMA_IDLE 0x0 +#define BV_SSP_DEBUG_DMA_SM__DMA_DMAREQ 0x1 +#define BV_SSP_DEBUG_DMA_SM__DMA_DMAACK 0x2 +#define BV_SSP_DEBUG_DMA_SM__DMA_STALL 0x3 +#define BV_SSP_DEBUG_DMA_SM__DMA_BUSY 0x4 +#define BV_SSP_DEBUG_DMA_SM__DMA_DONE 0x5 +#define BV_SSP_DEBUG_DMA_SM__DMA_COUNT 0x6 +#define BP_SSP_DEBUG_MMC_SM 12 +#define BM_SSP_DEBUG_MMC_SM 0x0000F000 +#define BF_SSP_DEBUG_MMC_SM(v) \ + (((v) << 12) & BM_SSP_DEBUG_MMC_SM) +#define BV_SSP_DEBUG_MMC_SM__MMC_IDLE 0x0 +#define BV_SSP_DEBUG_MMC_SM__MMC_CMD 0x1 +#define BV_SSP_DEBUG_MMC_SM__MMC_TRC 0x2 +#define BV_SSP_DEBUG_MMC_SM__MMC_RESP 0x3 +#define BV_SSP_DEBUG_MMC_SM__MMC_RPRX 0x4 +#define BV_SSP_DEBUG_MMC_SM__MMC_TX 0x5 +#define BV_SSP_DEBUG_MMC_SM__MMC_CTOK 0x6 +#define BV_SSP_DEBUG_MMC_SM__MMC_RX 0x7 +#define BV_SSP_DEBUG_MMC_SM__MMC_CCS 0x8 +#define BV_SSP_DEBUG_MMC_SM__MMC_PUP 0x9 +#define BV_SSP_DEBUG_MMC_SM__MMC_WAIT 0xA +#define BP_SSP_DEBUG_CMD_SM 10 +#define BM_SSP_DEBUG_CMD_SM 0x00000C00 +#define BF_SSP_DEBUG_CMD_SM(v) \ + (((v) << 10) & BM_SSP_DEBUG_CMD_SM) +#define BV_SSP_DEBUG_CMD_SM__CSM_IDLE 0x0 +#define BV_SSP_DEBUG_CMD_SM__CSM_INDEX 0x1 +#define BV_SSP_DEBUG_CMD_SM__CSM_ARG 0x2 +#define BV_SSP_DEBUG_CMD_SM__CSM_CRC 0x3 +#define BM_SSP_DEBUG_SSP_CMD 0x00000200 +#define BM_SSP_DEBUG_SSP_RESP 0x00000100 +#define BP_SSP_DEBUG_SSP_RXD 0 +#define BM_SSP_DEBUG_SSP_RXD 0x000000FF +#define BF_SSP_DEBUG_SSP_RXD(v) \ + (((v) << 0) & BM_SSP_DEBUG_SSP_RXD) + +#define HW_SSP_VERSION (0x00000130) + +#define BP_SSP_VERSION_MAJOR 24 +#define BM_SSP_VERSION_MAJOR 0xFF000000 +#define BF_SSP_VERSION_MAJOR(v) \ + (((v) << 24) & BM_SSP_VERSION_MAJOR) +#define BP_SSP_VERSION_MINOR 16 +#define BM_SSP_VERSION_MINOR 0x00FF0000 +#define BF_SSP_VERSION_MINOR(v) \ + (((v) << 16) & BM_SSP_VERSION_MINOR) +#define BP_SSP_VERSION_STEP 0 +#define BM_SSP_VERSION_STEP 0x0000FFFF +#define BF_SSP_VERSION_STEP(v) \ + (((v) << 0) & BM_SSP_VERSION_STEP) +#endif /* __ARCH_ARM___SSP_H */ diff --git a/include/asm-arm/arch-mx28/regs-timrot.h b/include/asm-arm/arch-mx28/regs-timrot.h new file mode 100644 index 0000000000..125b835e19 --- /dev/null +++ b/include/asm-arm/arch-mx28/regs-timrot.h @@ -0,0 +1,293 @@ +/* + * Freescale TIMROT Register Definitions + * + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * This file is created by xml file. Don't Edit it. + * + * Xml Revision: 1.40 + * Template revision: 26195 + */ + +#ifndef __ARCH_ARM___TIMROT_H +#define __ARCH_ARM___TIMROT_H + + +#define HW_TIMROT_ROTCTRL (0x00000000) +#define HW_TIMROT_ROTCTRL_SET (0x00000004) +#define HW_TIMROT_ROTCTRL_CLR (0x00000008) +#define HW_TIMROT_ROTCTRL_TOG (0x0000000c) + +#define BM_TIMROT_ROTCTRL_SFTRST 0x80000000 +#define BM_TIMROT_ROTCTRL_CLKGATE 0x40000000 +#define BM_TIMROT_ROTCTRL_ROTARY_PRESENT 0x20000000 +#define BM_TIMROT_ROTCTRL_TIM3_PRESENT 0x10000000 +#define BM_TIMROT_ROTCTRL_TIM2_PRESENT 0x08000000 +#define BM_TIMROT_ROTCTRL_TIM1_PRESENT 0x04000000 +#define BM_TIMROT_ROTCTRL_TIM0_PRESENT 0x02000000 +#define BP_TIMROT_ROTCTRL_STATE 22 +#define BM_TIMROT_ROTCTRL_STATE 0x01C00000 +#define BF_TIMROT_ROTCTRL_STATE(v) \ + (((v) << 22) & BM_TIMROT_ROTCTRL_STATE) +#define BP_TIMROT_ROTCTRL_DIVIDER 16 +#define BM_TIMROT_ROTCTRL_DIVIDER 0x003F0000 +#define BF_TIMROT_ROTCTRL_DIVIDER(v) \ + (((v) << 16) & BM_TIMROT_ROTCTRL_DIVIDER) +#define BP_TIMROT_ROTCTRL_RSRVD3 13 +#define BM_TIMROT_ROTCTRL_RSRVD3 0x0000E000 +#define BF_TIMROT_ROTCTRL_RSRVD3(v) \ + (((v) << 13) & BM_TIMROT_ROTCTRL_RSRVD3) +#define BM_TIMROT_ROTCTRL_RELATIVE 0x00001000 +#define BP_TIMROT_ROTCTRL_OVERSAMPLE 10 +#define BM_TIMROT_ROTCTRL_OVERSAMPLE 0x00000C00 +#define BF_TIMROT_ROTCTRL_OVERSAMPLE(v) \ + (((v) << 10) & BM_TIMROT_ROTCTRL_OVERSAMPLE) +#define BV_TIMROT_ROTCTRL_OVERSAMPLE__8X 0x0 +#define BV_TIMROT_ROTCTRL_OVERSAMPLE__4X 0x1 +#define BV_TIMROT_ROTCTRL_OVERSAMPLE__2X 0x2 +#define BV_TIMROT_ROTCTRL_OVERSAMPLE__1X 0x3 +#define BM_TIMROT_ROTCTRL_POLARITY_B 0x00000200 +#define BM_TIMROT_ROTCTRL_POLARITY_A 0x00000100 +#define BP_TIMROT_ROTCTRL_SELECT_B 4 +#define BM_TIMROT_ROTCTRL_SELECT_B 0x000000F0 +#define BF_TIMROT_ROTCTRL_SELECT_B(v) \ + (((v) << 4) & BM_TIMROT_ROTCTRL_SELECT_B) +#define BV_TIMROT_ROTCTRL_SELECT_B__NEVER_TICK 0x0 +#define BV_TIMROT_ROTCTRL_SELECT_B__PWM0 0x1 +#define BV_TIMROT_ROTCTRL_SELECT_B__PWM1 0x2 +#define BV_TIMROT_ROTCTRL_SELECT_B__PWM2 0x3 +#define BV_TIMROT_ROTCTRL_SELECT_B__PWM3 0x4 +#define BV_TIMROT_ROTCTRL_SELECT_B__PWM4 0x5 +#define BV_TIMROT_ROTCTRL_SELECT_B__PWM5 0x6 +#define BV_TIMROT_ROTCTRL_SELECT_B__PWM6 0x7 +#define BV_TIMROT_ROTCTRL_SELECT_B__PWM7 0x8 +#define BV_TIMROT_ROTCTRL_SELECT_B__ROTARYA 0x9 +#define BV_TIMROT_ROTCTRL_SELECT_B__ROTARYB 0xA +#define BP_TIMROT_ROTCTRL_SELECT_A 0 +#define BM_TIMROT_ROTCTRL_SELECT_A 0x0000000F +#define BF_TIMROT_ROTCTRL_SELECT_A(v) \ + (((v) << 0) & BM_TIMROT_ROTCTRL_SELECT_A) +#define BV_TIMROT_ROTCTRL_SELECT_A__NEVER_TICK 0x0 +#define BV_TIMROT_ROTCTRL_SELECT_A__PWM0 0x1 +#define BV_TIMROT_ROTCTRL_SELECT_A__PWM1 0x2 +#define BV_TIMROT_ROTCTRL_SELECT_A__PWM2 0x3 +#define BV_TIMROT_ROTCTRL_SELECT_A__PWM3 0x4 +#define BV_TIMROT_ROTCTRL_SELECT_A__PWM4 0x5 +#define BV_TIMROT_ROTCTRL_SELECT_A__PWM5 0x6 +#define BV_TIMROT_ROTCTRL_SELECT_A__PWM6 0x7 +#define BV_TIMROT_ROTCTRL_SELECT_A__PWM7 0x8 +#define BV_TIMROT_ROTCTRL_SELECT_A__ROTARYA 0x9 +#define BV_TIMROT_ROTCTRL_SELECT_A__ROTARYB 0xA + +#define HW_TIMROT_ROTCOUNT (0x00000010) + +#define BP_TIMROT_ROTCOUNT_RSRVD1 16 +#define BM_TIMROT_ROTCOUNT_RSRVD1 0xFFFF0000 +#define BF_TIMROT_ROTCOUNT_RSRVD1(v) \ + (((v) << 16) & BM_TIMROT_ROTCOUNT_RSRVD1) +#define BP_TIMROT_ROTCOUNT_UPDOWN 0 +#define BM_TIMROT_ROTCOUNT_UPDOWN 0x0000FFFF +#define BF_TIMROT_ROTCOUNT_UPDOWN(v) \ + (((v) << 0) & BM_TIMROT_ROTCOUNT_UPDOWN) + +/* + * multi-register-define name HW_TIMROT_TIMCTRLn + * base 0x00000020 + * count 3 + * offset 0x40 + */ +#define HW_TIMROT_TIMCTRLn(n) (0x00000020 + (n) * 0x40) +#define HW_TIMROT_TIMCTRLn_SET(n) (0x00000024 + (n) * 0x40) +#define HW_TIMROT_TIMCTRLn_CLR(n) (0x00000028 + (n) * 0x40) +#define HW_TIMROT_TIMCTRLn_TOG(n) (0x0000002c + (n) * 0x40) +#define BP_TIMROT_TIMCTRLn_RSRVD3 16 +#define BM_TIMROT_TIMCTRLn_RSRVD3 0xFFFF0000 +#define BF_TIMROT_TIMCTRLn_RSRVD3(v) \ + (((v) << 16) & BM_TIMROT_TIMCTRLn_RSRVD3) +#define BM_TIMROT_TIMCTRLn_IRQ 0x00008000 +#define BM_TIMROT_TIMCTRLn_IRQ_EN 0x00004000 +#define BP_TIMROT_TIMCTRLn_RSRVD2 12 +#define BM_TIMROT_TIMCTRLn_RSRVD2 0x00003000 +#define BF_TIMROT_TIMCTRLn_RSRVD2(v) \ + (((v) << 12) & BM_TIMROT_TIMCTRLn_RSRVD2) +#define BM_TIMROT_TIMCTRLn_MATCH_MODE 0x00000800 +#define BP_TIMROT_TIMCTRLn_RSRVD1 9 +#define BM_TIMROT_TIMCTRLn_RSRVD1 0x00000600 +#define BF_TIMROT_TIMCTRLn_RSRVD1(v) \ + (((v) << 9) & BM_TIMROT_TIMCTRLn_RSRVD1) +#define BM_TIMROT_TIMCTRLn_POLARITY 0x00000100 +#define BM_TIMROT_TIMCTRLn_UPDATE 0x00000080 +#define BM_TIMROT_TIMCTRLn_RELOAD 0x00000040 +#define BP_TIMROT_TIMCTRLn_PRESCALE 4 +#define BM_TIMROT_TIMCTRLn_PRESCALE 0x00000030 +#define BF_TIMROT_TIMCTRLn_PRESCALE(v) \ + (((v) << 4) & BM_TIMROT_TIMCTRLn_PRESCALE) +#define BV_TIMROT_TIMCTRLn_PRESCALE__DIV_BY_1 0x0 +#define BV_TIMROT_TIMCTRLn_PRESCALE__DIV_BY_2 0x1 +#define BV_TIMROT_TIMCTRLn_PRESCALE__DIV_BY_4 0x2 +#define BV_TIMROT_TIMCTRLn_PRESCALE__DIV_BY_8 0x3 +#define BP_TIMROT_TIMCTRLn_SELECT 0 +#define BM_TIMROT_TIMCTRLn_SELECT 0x0000000F +#define BF_TIMROT_TIMCTRLn_SELECT(v) \ + (((v) << 0) & BM_TIMROT_TIMCTRLn_SELECT) +#define BV_TIMROT_TIMCTRLn_SELECT__NEVER_TICK 0x0 +#define BV_TIMROT_TIMCTRLn_SELECT__PWM0 0x1 +#define BV_TIMROT_TIMCTRLn_SELECT__PWM1 0x2 +#define BV_TIMROT_TIMCTRLn_SELECT__PWM2 0x3 +#define BV_TIMROT_TIMCTRLn_SELECT__PWM3 0x4 +#define BV_TIMROT_TIMCTRLn_SELECT__PWM4 0x5 +#define BV_TIMROT_TIMCTRLn_SELECT__PWM5 0x6 +#define BV_TIMROT_TIMCTRLn_SELECT__PWM6 0x7 +#define BV_TIMROT_TIMCTRLn_SELECT__PWM7 0x8 +#define BV_TIMROT_TIMCTRLn_SELECT__ROTARYA 0x9 +#define BV_TIMROT_TIMCTRLn_SELECT__ROTARYB 0xA +#define BV_TIMROT_TIMCTRLn_SELECT__32KHZ_XTAL 0xB +#define BV_TIMROT_TIMCTRLn_SELECT__8KHZ_XTAL 0xC +#define BV_TIMROT_TIMCTRLn_SELECT__4KHZ_XTAL 0xD +#define BV_TIMROT_TIMCTRLn_SELECT__1KHZ_XTAL 0xE +#define BV_TIMROT_TIMCTRLn_SELECT__TICK_ALWAYS 0xF + +/* + * multi-register-define name HW_TIMROT_RUNNING_COUNTn + * base 0x00000030 + * count 3 + * offset 0x40 + */ +#define HW_TIMROT_RUNNING_COUNTn(n) (0x00000030 + (n) * 0x40) +#define BP_TIMROT_RUNNING_COUNTn_RUNNING_COUNT 0 +#define BM_TIMROT_RUNNING_COUNTn_RUNNING_COUNT 0xFFFFFFFF +#define BF_TIMROT_RUNNING_COUNTn_RUNNING_COUNT(v) (v) + +/* + * multi-register-define name HW_TIMROT_FIXED_COUNTn + * base 0x00000040 + * count 3 + * offset 0x40 + */ +#define HW_TIMROT_FIXED_COUNTn(n) (0x00000040 + (n) * 0x40) +#define BP_TIMROT_FIXED_COUNTn_FIXED_COUNT 0 +#define BM_TIMROT_FIXED_COUNTn_FIXED_COUNT 0xFFFFFFFF +#define BF_TIMROT_FIXED_COUNTn_FIXED_COUNT(v) (v) + +/* + * multi-register-define name HW_TIMROT_MATCH_COUNTn + * base 0x00000050 + * count 4 + * offset 0x40 + */ +#define HW_TIMROT_MATCH_COUNTn(n) (0x00000050 + (n) * 0x40) +#define BP_TIMROT_MATCH_COUNTn_MATCH_COUNT 0 +#define BM_TIMROT_MATCH_COUNTn_MATCH_COUNT 0xFFFFFFFF +#define BF_TIMROT_MATCH_COUNTn_MATCH_COUNT(v) (v) + +#define HW_TIMROT_TIMCTRL3 (0x000000e0) +#define HW_TIMROT_TIMCTRL3_SET (0x000000e4) +#define HW_TIMROT_TIMCTRL3_CLR (0x000000e8) +#define HW_TIMROT_TIMCTRL3_TOG (0x000000ec) + +#define BP_TIMROT_TIMCTRL3_RSRVD2 20 +#define BM_TIMROT_TIMCTRL3_RSRVD2 0xFFF00000 +#define BF_TIMROT_TIMCTRL3_RSRVD2(v) \ + (((v) << 20) & BM_TIMROT_TIMCTRL3_RSRVD2) +#define BP_TIMROT_TIMCTRL3_TEST_SIGNAL 16 +#define BM_TIMROT_TIMCTRL3_TEST_SIGNAL 0x000F0000 +#define BF_TIMROT_TIMCTRL3_TEST_SIGNAL(v) \ + (((v) << 16) & BM_TIMROT_TIMCTRL3_TEST_SIGNAL) +#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__NEVER_TICK 0x0 +#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM0 0x1 +#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM1 0x2 +#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM2 0x3 +#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM3 0x4 +#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM4 0x5 +#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM5 0x6 +#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM6 0x7 +#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM7 0x8 +#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__ROTARYA 0x9 +#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__ROTARYB 0xA +#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__32KHZ_XTAL 0xB +#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__8KHZ_XTAL 0xC +#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__4KHZ_XTAL 0xD +#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__1KHZ_XTAL 0xE +#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__TICK_ALWAYS 0xF +#define BM_TIMROT_TIMCTRL3_IRQ 0x00008000 +#define BM_TIMROT_TIMCTRL3_IRQ_EN 0x00004000 +#define BP_TIMROT_TIMCTRL3_RSRVD1 12 +#define BM_TIMROT_TIMCTRL3_RSRVD1 0x00003000 +#define BF_TIMROT_TIMCTRL3_RSRVD1(v) \ + (((v) << 12) & BM_TIMROT_TIMCTRL3_RSRVD1) +#define BM_TIMROT_TIMCTRL3_MATCH_MODE 0x00000800 +#define BM_TIMROT_TIMCTRL3_DUTY_VALID 0x00000400 +#define BM_TIMROT_TIMCTRL3_DUTY_CYCLE 0x00000200 +#define BM_TIMROT_TIMCTRL3_POLARITY 0x00000100 +#define BM_TIMROT_TIMCTRL3_UPDATE 0x00000080 +#define BM_TIMROT_TIMCTRL3_RELOAD 0x00000040 +#define BP_TIMROT_TIMCTRL3_PRESCALE 4 +#define BM_TIMROT_TIMCTRL3_PRESCALE 0x00000030 +#define BF_TIMROT_TIMCTRL3_PRESCALE(v) \ + (((v) << 4) & BM_TIMROT_TIMCTRL3_PRESCALE) +#define BV_TIMROT_TIMCTRL3_PRESCALE__DIV_BY_1 0x0 +#define BV_TIMROT_TIMCTRL3_PRESCALE__DIV_BY_2 0x1 +#define BV_TIMROT_TIMCTRL3_PRESCALE__DIV_BY_4 0x2 +#define BV_TIMROT_TIMCTRL3_PRESCALE__DIV_BY_8 0x3 +#define BP_TIMROT_TIMCTRL3_SELECT 0 +#define BM_TIMROT_TIMCTRL3_SELECT 0x0000000F +#define BF_TIMROT_TIMCTRL3_SELECT(v) \ + (((v) << 0) & BM_TIMROT_TIMCTRL3_SELECT) +#define BV_TIMROT_TIMCTRL3_SELECT__NEVER_TICK 0x0 +#define BV_TIMROT_TIMCTRL3_SELECT__PWM0 0x1 +#define BV_TIMROT_TIMCTRL3_SELECT__PWM1 0x2 +#define BV_TIMROT_TIMCTRL3_SELECT__PWM2 0x3 +#define BV_TIMROT_TIMCTRL3_SELECT__PWM3 0x4 +#define BV_TIMROT_TIMCTRL3_SELECT__PWM4 0x5 +#define BV_TIMROT_TIMCTRL3_SELECT__PWM5 0x6 +#define BV_TIMROT_TIMCTRL3_SELECT__PWM6 0x7 +#define BV_TIMROT_TIMCTRL3_SELECT__PWM7 0x8 +#define BV_TIMROT_TIMCTRL3_SELECT__ROTARYA 0x9 +#define BV_TIMROT_TIMCTRL3_SELECT__ROTARYB 0xA +#define BV_TIMROT_TIMCTRL3_SELECT__32KHZ_XTAL 0xB +#define BV_TIMROT_TIMCTRL3_SELECT__8KHZ_XTAL 0xC +#define BV_TIMROT_TIMCTRL3_SELECT__4KHZ_XTAL 0xD +#define BV_TIMROT_TIMCTRL3_SELECT__1KHZ_XTAL 0xE +#define BV_TIMROT_TIMCTRL3_SELECT__TICK_ALWAYS 0xF + +#define HW_TIMROT_RUNNING_COUNT3 (0x000000f0) + +#define BP_TIMROT_RUNNING_COUNT3_LOW_RUNNING_COUNT 0 +#define BM_TIMROT_RUNNING_COUNT3_LOW_RUNNING_COUNT 0xFFFFFFFF +#define BF_TIMROT_RUNNING_COUNT3_LOW_RUNNING_COUNT(v) (v) + +#define HW_TIMROT_FIXED_COUNT3 (0x00000100) + +#define BP_TIMROT_FIXED_COUNT3_HIGH_FIXED_COUNT 0 +#define BM_TIMROT_FIXED_COUNT3_HIGH_FIXED_COUNT 0xFFFFFFFF +#define BF_TIMROT_FIXED_COUNT3_HIGH_FIXED_COUNT(v) (v) + +#define HW_TIMROT_VERSION (0x00000120) + +#define BP_TIMROT_VERSION_MAJOR 24 +#define BM_TIMROT_VERSION_MAJOR 0xFF000000 +#define BF_TIMROT_VERSION_MAJOR(v) \ + (((v) << 24) & BM_TIMROT_VERSION_MAJOR) +#define BP_TIMROT_VERSION_MINOR 16 +#define BM_TIMROT_VERSION_MINOR 0x00FF0000 +#define BF_TIMROT_VERSION_MINOR(v) \ + (((v) << 16) & BM_TIMROT_VERSION_MINOR) +#define BP_TIMROT_VERSION_STEP 0 +#define BM_TIMROT_VERSION_STEP 0x0000FFFF +#define BF_TIMROT_VERSION_STEP(v) \ + (((v) << 0) & BM_TIMROT_VERSION_STEP) +#endif /* __ARCH_ARM___TIMROT_H */ diff --git a/include/asm-arm/arch-mx28/regs-uartdbg.h b/include/asm-arm/arch-mx28/regs-uartdbg.h new file mode 100644 index 0000000000..0b5932c79a --- /dev/null +++ b/include/asm-arm/arch-mx28/regs-uartdbg.h @@ -0,0 +1,301 @@ +/* + * Freescale UARTDBG Register Definitions + * + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * This file is created by xml file. Don't Edit it. + * + * Xml Revision: 1.21 + * Template revision: 26195 + */ + +#ifndef __ARCH_ARM___UARTDBG_H +#define __ARCH_ARM___UARTDBG_H + + +#define HW_UARTDBGDR (0x00000000) + +#define BP_UARTDBGDR_UNAVAILABLE 16 +#define BM_UARTDBGDR_UNAVAILABLE 0xFFFF0000 +#define BF_UARTDBGDR_UNAVAILABLE(v) \ + (((v) << 16) & BM_UARTDBGDR_UNAVAILABLE) +#define BP_UARTDBGDR_RESERVED 12 +#define BM_UARTDBGDR_RESERVED 0x0000F000 +#define BF_UARTDBGDR_RESERVED(v) \ + (((v) << 12) & BM_UARTDBGDR_RESERVED) +#define BM_UARTDBGDR_OE 0x00000800 +#define BM_UARTDBGDR_BE 0x00000400 +#define BM_UARTDBGDR_PE 0x00000200 +#define BM_UARTDBGDR_FE 0x00000100 +#define BP_UARTDBGDR_DATA 0 +#define BM_UARTDBGDR_DATA 0x000000FF +#define BF_UARTDBGDR_DATA(v) \ + (((v) << 0) & BM_UARTDBGDR_DATA) + +#define HW_UARTDBGRSR_ECR (0x00000004) + +#define BP_UARTDBGRSR_ECR_UNAVAILABLE 8 +#define BM_UARTDBGRSR_ECR_UNAVAILABLE 0xFFFFFF00 +#define BF_UARTDBGRSR_ECR_UNAVAILABLE(v) \ + (((v) << 8) & BM_UARTDBGRSR_ECR_UNAVAILABLE) +#define BP_UARTDBGRSR_ECR_EC 4 +#define BM_UARTDBGRSR_ECR_EC 0x000000F0 +#define BF_UARTDBGRSR_ECR_EC(v) \ + (((v) << 4) & BM_UARTDBGRSR_ECR_EC) +#define BM_UARTDBGRSR_ECR_OE 0x00000008 +#define BM_UARTDBGRSR_ECR_BE 0x00000004 +#define BM_UARTDBGRSR_ECR_PE 0x00000002 +#define BM_UARTDBGRSR_ECR_FE 0x00000001 + +#define HW_UARTDBGFR (0x00000018) + +#define BP_UARTDBGFR_UNAVAILABLE 16 +#define BM_UARTDBGFR_UNAVAILABLE 0xFFFF0000 +#define BF_UARTDBGFR_UNAVAILABLE(v) \ + (((v) << 16) & BM_UARTDBGFR_UNAVAILABLE) +#define BP_UARTDBGFR_RESERVED 9 +#define BM_UARTDBGFR_RESERVED 0x0000FE00 +#define BF_UARTDBGFR_RESERVED(v) \ + (((v) << 9) & BM_UARTDBGFR_RESERVED) +#define BM_UARTDBGFR_RI 0x00000100 +#define BM_UARTDBGFR_TXFE 0x00000080 +#define BM_UARTDBGFR_RXFF 0x00000040 +#define BM_UARTDBGFR_TXFF 0x00000020 +#define BM_UARTDBGFR_RXFE 0x00000010 +#define BM_UARTDBGFR_BUSY 0x00000008 +#define BM_UARTDBGFR_DCD 0x00000004 +#define BM_UARTDBGFR_DSR 0x00000002 +#define BM_UARTDBGFR_CTS 0x00000001 + +#define HW_UARTDBGILPR (0x00000020) + +#define BP_UARTDBGILPR_UNAVAILABLE 8 +#define BM_UARTDBGILPR_UNAVAILABLE 0xFFFFFF00 +#define BF_UARTDBGILPR_UNAVAILABLE(v) \ + (((v) << 8) & BM_UARTDBGILPR_UNAVAILABLE) +#define BP_UARTDBGILPR_ILPDVSR 0 +#define BM_UARTDBGILPR_ILPDVSR 0x000000FF +#define BF_UARTDBGILPR_ILPDVSR(v) \ + (((v) << 0) & BM_UARTDBGILPR_ILPDVSR) + +#define HW_UARTDBGIBRD (0x00000024) + +#define BP_UARTDBGIBRD_UNAVAILABLE 16 +#define BM_UARTDBGIBRD_UNAVAILABLE 0xFFFF0000 +#define BF_UARTDBGIBRD_UNAVAILABLE(v) \ + (((v) << 16) & BM_UARTDBGIBRD_UNAVAILABLE) +#define BP_UARTDBGIBRD_BAUD_DIVINT 0 +#define BM_UARTDBGIBRD_BAUD_DIVINT 0x0000FFFF +#define BF_UARTDBGIBRD_BAUD_DIVINT(v) \ + (((v) << 0) & BM_UARTDBGIBRD_BAUD_DIVINT) + +#define HW_UARTDBGFBRD (0x00000028) + +#define BP_UARTDBGFBRD_UNAVAILABLE 8 +#define BM_UARTDBGFBRD_UNAVAILABLE 0xFFFFFF00 +#define BF_UARTDBGFBRD_UNAVAILABLE(v) \ + (((v) << 8) & BM_UARTDBGFBRD_UNAVAILABLE) +#define BP_UARTDBGFBRD_RESERVED 6 +#define BM_UARTDBGFBRD_RESERVED 0x000000C0 +#define BF_UARTDBGFBRD_RESERVED(v) \ + (((v) << 6) & BM_UARTDBGFBRD_RESERVED) +#define BP_UARTDBGFBRD_BAUD_DIVFRAC 0 +#define BM_UARTDBGFBRD_BAUD_DIVFRAC 0x0000003F +#define BF_UARTDBGFBRD_BAUD_DIVFRAC(v) \ + (((v) << 0) & BM_UARTDBGFBRD_BAUD_DIVFRAC) + +#define HW_UARTDBGLCR_H (0x0000002c) + +#define BP_UARTDBGLCR_H_UNAVAILABLE 16 +#define BM_UARTDBGLCR_H_UNAVAILABLE 0xFFFF0000 +#define BF_UARTDBGLCR_H_UNAVAILABLE(v) \ + (((v) << 16) & BM_UARTDBGLCR_H_UNAVAILABLE) +#define BP_UARTDBGLCR_H_RESERVED 8 +#define BM_UARTDBGLCR_H_RESERVED 0x0000FF00 +#define BF_UARTDBGLCR_H_RESERVED(v) \ + (((v) << 8) & BM_UARTDBGLCR_H_RESERVED) +#define BM_UARTDBGLCR_H_SPS 0x00000080 +#define BP_UARTDBGLCR_H_WLEN 5 +#define BM_UARTDBGLCR_H_WLEN 0x00000060 +#define BF_UARTDBGLCR_H_WLEN(v) \ + (((v) << 5) & BM_UARTDBGLCR_H_WLEN) +#define BM_UARTDBGLCR_H_FEN 0x00000010 +#define BM_UARTDBGLCR_H_STP2 0x00000008 +#define BM_UARTDBGLCR_H_EPS 0x00000004 +#define BM_UARTDBGLCR_H_PEN 0x00000002 +#define BM_UARTDBGLCR_H_BRK 0x00000001 + +#define HW_UARTDBGCR (0x00000030) + +#define BP_UARTDBGCR_UNAVAILABLE 16 +#define BM_UARTDBGCR_UNAVAILABLE 0xFFFF0000 +#define BF_UARTDBGCR_UNAVAILABLE(v) \ + (((v) << 16) & BM_UARTDBGCR_UNAVAILABLE) +#define BM_UARTDBGCR_CTSEN 0x00008000 +#define BM_UARTDBGCR_RTSEN 0x00004000 +#define BM_UARTDBGCR_OUT2 0x00002000 +#define BM_UARTDBGCR_OUT1 0x00001000 +#define BM_UARTDBGCR_RTS 0x00000800 +#define BM_UARTDBGCR_DTR 0x00000400 +#define BM_UARTDBGCR_RXE 0x00000200 +#define BM_UARTDBGCR_TXE 0x00000100 +#define BM_UARTDBGCR_LBE 0x00000080 +#define BP_UARTDBGCR_RESERVED 3 +#define BM_UARTDBGCR_RESERVED 0x00000078 +#define BF_UARTDBGCR_RESERVED(v) \ + (((v) << 3) & BM_UARTDBGCR_RESERVED) +#define BM_UARTDBGCR_SIRLP 0x00000004 +#define BM_UARTDBGCR_SIREN 0x00000002 +#define BM_UARTDBGCR_UARTEN 0x00000001 + +#define HW_UARTDBGIFLS (0x00000034) + +#define BP_UARTDBGIFLS_UNAVAILABLE 16 +#define BM_UARTDBGIFLS_UNAVAILABLE 0xFFFF0000 +#define BF_UARTDBGIFLS_UNAVAILABLE(v) \ + (((v) << 16) & BM_UARTDBGIFLS_UNAVAILABLE) +#define BP_UARTDBGIFLS_RESERVED 6 +#define BM_UARTDBGIFLS_RESERVED 0x0000FFC0 +#define BF_UARTDBGIFLS_RESERVED(v) \ + (((v) << 6) & BM_UARTDBGIFLS_RESERVED) +#define BP_UARTDBGIFLS_RXIFLSEL 3 +#define BM_UARTDBGIFLS_RXIFLSEL 0x00000038 +#define BF_UARTDBGIFLS_RXIFLSEL(v) \ + (((v) << 3) & BM_UARTDBGIFLS_RXIFLSEL) +#define BV_UARTDBGIFLS_RXIFLSEL__ONE_EIGHT 0x0 +#define BV_UARTDBGIFLS_RXIFLSEL__ONE_QUARTER 0x1 +#define BV_UARTDBGIFLS_RXIFLSEL__ONE_HALF 0x2 +#define BV_UARTDBGIFLS_RXIFLSEL__THREE_QUARTERS 0x3 +#define BV_UARTDBGIFLS_RXIFLSEL__SEVEN_EIGHTHS 0x4 +#define BV_UARTDBGIFLS_RXIFLSEL__INVALID5 0x5 +#define BV_UARTDBGIFLS_RXIFLSEL__INVALID6 0x6 +#define BV_UARTDBGIFLS_RXIFLSEL__INVALID7 0x7 +#define BP_UARTDBGIFLS_TXIFLSEL 0 +#define BM_UARTDBGIFLS_TXIFLSEL 0x00000007 +#define BF_UARTDBGIFLS_TXIFLSEL(v) \ + (((v) << 0) & BM_UARTDBGIFLS_TXIFLSEL) +#define BV_UARTDBGIFLS_TXIFLSEL__ONE_EIGHT 0x0 +#define BV_UARTDBGIFLS_TXIFLSEL__ONE_QUARTER 0x1 +#define BV_UARTDBGIFLS_TXIFLSEL__ONE_HALF 0x2 +#define BV_UARTDBGIFLS_TXIFLSEL__THREE_QUARTERS 0x3 +#define BV_UARTDBGIFLS_TXIFLSEL__SEVEN_EIGHTHS 0x4 +#define BV_UARTDBGIFLS_TXIFLSEL__INVALID5 0x5 +#define BV_UARTDBGIFLS_TXIFLSEL__INVALID6 0x6 +#define BV_UARTDBGIFLS_TXIFLSEL__INVALID7 0x7 + +#define HW_UARTDBGIMSC (0x00000038) + +#define BP_UARTDBGIMSC_UNAVAILABLE 16 +#define BM_UARTDBGIMSC_UNAVAILABLE 0xFFFF0000 +#define BF_UARTDBGIMSC_UNAVAILABLE(v) \ + (((v) << 16) & BM_UARTDBGIMSC_UNAVAILABLE) +#define BP_UARTDBGIMSC_RESERVED 11 +#define BM_UARTDBGIMSC_RESERVED 0x0000F800 +#define BF_UARTDBGIMSC_RESERVED(v) \ + (((v) << 11) & BM_UARTDBGIMSC_RESERVED) +#define BM_UARTDBGIMSC_OEIM 0x00000400 +#define BM_UARTDBGIMSC_BEIM 0x00000200 +#define BM_UARTDBGIMSC_PEIM 0x00000100 +#define BM_UARTDBGIMSC_FEIM 0x00000080 +#define BM_UARTDBGIMSC_RTIM 0x00000040 +#define BM_UARTDBGIMSC_TXIM 0x00000020 +#define BM_UARTDBGIMSC_RXIM 0x00000010 +#define BM_UARTDBGIMSC_DSRMIM 0x00000008 +#define BM_UARTDBGIMSC_DCDMIM 0x00000004 +#define BM_UARTDBGIMSC_CTSMIM 0x00000002 +#define BM_UARTDBGIMSC_RIMIM 0x00000001 + +#define HW_UARTDBGRIS (0x0000003c) + +#define BP_UARTDBGRIS_UNAVAILABLE 16 +#define BM_UARTDBGRIS_UNAVAILABLE 0xFFFF0000 +#define BF_UARTDBGRIS_UNAVAILABLE(v) \ + (((v) << 16) & BM_UARTDBGRIS_UNAVAILABLE) +#define BP_UARTDBGRIS_RESERVED 11 +#define BM_UARTDBGRIS_RESERVED 0x0000F800 +#define BF_UARTDBGRIS_RESERVED(v) \ + (((v) << 11) & BM_UARTDBGRIS_RESERVED) +#define BM_UARTDBGRIS_OERIS 0x00000400 +#define BM_UARTDBGRIS_BERIS 0x00000200 +#define BM_UARTDBGRIS_PERIS 0x00000100 +#define BM_UARTDBGRIS_FERIS 0x00000080 +#define BM_UARTDBGRIS_RTRIS 0x00000040 +#define BM_UARTDBGRIS_TXRIS 0x00000020 +#define BM_UARTDBGRIS_RXRIS 0x00000010 +#define BM_UARTDBGRIS_DSRRMIS 0x00000008 +#define BM_UARTDBGRIS_DCDRMIS 0x00000004 +#define BM_UARTDBGRIS_CTSRMIS 0x00000002 +#define BM_UARTDBGRIS_RIRMIS 0x00000001 + +#define HW_UARTDBGMIS (0x00000040) + +#define BP_UARTDBGMIS_UNAVAILABLE 16 +#define BM_UARTDBGMIS_UNAVAILABLE 0xFFFF0000 +#define BF_UARTDBGMIS_UNAVAILABLE(v) \ + (((v) << 16) & BM_UARTDBGMIS_UNAVAILABLE) +#define BP_UARTDBGMIS_RESERVED 11 +#define BM_UARTDBGMIS_RESERVED 0x0000F800 +#define BF_UARTDBGMIS_RESERVED(v) \ + (((v) << 11) & BM_UARTDBGMIS_RESERVED) +#define BM_UARTDBGMIS_OEMIS 0x00000400 +#define BM_UARTDBGMIS_BEMIS 0x00000200 +#define BM_UARTDBGMIS_PEMIS 0x00000100 +#define BM_UARTDBGMIS_FEMIS 0x00000080 +#define BM_UARTDBGMIS_RTMIS 0x00000040 +#define BM_UARTDBGMIS_TXMIS 0x00000020 +#define BM_UARTDBGMIS_RXMIS 0x00000010 +#define BM_UARTDBGMIS_DSRMMIS 0x00000008 +#define BM_UARTDBGMIS_DCDMMIS 0x00000004 +#define BM_UARTDBGMIS_CTSMMIS 0x00000002 +#define BM_UARTDBGMIS_RIMMIS 0x00000001 + +#define HW_UARTDBGICR (0x00000044) + +#define BP_UARTDBGICR_UNAVAILABLE 16 +#define BM_UARTDBGICR_UNAVAILABLE 0xFFFF0000 +#define BF_UARTDBGICR_UNAVAILABLE(v) \ + (((v) << 16) & BM_UARTDBGICR_UNAVAILABLE) +#define BP_UARTDBGICR_RESERVED 11 +#define BM_UARTDBGICR_RESERVED 0x0000F800 +#define BF_UARTDBGICR_RESERVED(v) \ + (((v) << 11) & BM_UARTDBGICR_RESERVED) +#define BM_UARTDBGICR_OEIC 0x00000400 +#define BM_UARTDBGICR_BEIC 0x00000200 +#define BM_UARTDBGICR_PEIC 0x00000100 +#define BM_UARTDBGICR_FEIC 0x00000080 +#define BM_UARTDBGICR_RTIC 0x00000040 +#define BM_UARTDBGICR_TXIC 0x00000020 +#define BM_UARTDBGICR_RXIC 0x00000010 +#define BM_UARTDBGICR_DSRMIC 0x00000008 +#define BM_UARTDBGICR_DCDMIC 0x00000004 +#define BM_UARTDBGICR_CTSMIC 0x00000002 +#define BM_UARTDBGICR_RIMIC 0x00000001 + +#define HW_UARTDBGDMACR (0x00000048) + +#define BP_UARTDBGDMACR_UNAVAILABLE 16 +#define BM_UARTDBGDMACR_UNAVAILABLE 0xFFFF0000 +#define BF_UARTDBGDMACR_UNAVAILABLE(v) \ + (((v) << 16) & BM_UARTDBGDMACR_UNAVAILABLE) +#define BP_UARTDBGDMACR_RESERVED 3 +#define BM_UARTDBGDMACR_RESERVED 0x0000FFF8 +#define BF_UARTDBGDMACR_RESERVED(v) \ + (((v) << 3) & BM_UARTDBGDMACR_RESERVED) +#define BM_UARTDBGDMACR_DMAONERR 0x00000004 +#define BM_UARTDBGDMACR_TXDMAE 0x00000002 +#define BM_UARTDBGDMACR_RXDMAE 0x00000001 +#endif /* __ARCH_ARM___UARTDBG_H */ diff --git a/include/asm-arm/arch-mx31/mx31-regs.h b/include/asm-arm/arch-mx31/mx31-regs.h index 51b02a2a26..a683a2e383 100644 --- a/include/asm-arm/arch-mx31/mx31-regs.h +++ b/include/asm-arm/arch-mx31/mx31-regs.h @@ -1,5 +1,6 @@ /* * + * (C) Copyright 2008-2009 Freescale Semiconductor, Inc. * (c) 2007 Pengutronix, Sascha Hauer * * See file CREDITS for list of people who contributed to this @@ -255,4 +256,100 @@ */ #define NFC_BASE_ADDR 0xB8000000 +/* + * Addresses for NFC registers + */ +#define NFC_BUF_SIZE (*((volatile u16 *)(NFC_BASE_ADDR + 0xE00))) +#define NFC_BUF_ADDR (*((volatile u16 *)(NFC_BASE_ADDR + 0xE04))) +#define NFC_FLASH_ADDR (*((volatile u16 *)(NFC_BASE_ADDR + 0xE06))) +#define NFC_FLASH_CMD (*((volatile u16 *)(NFC_BASE_ADDR + 0xE08))) +#define NFC_CONFIG (*((volatile u16 *)(NFC_BASE_ADDR + 0xE0A))) +#define NFC_ECC_STATUS_RESULT (*((volatile u16 *)(NFC_BASE_ADDR + 0xE0C))) +#define NFC_RSLTMAIN_AREA (*((volatile u16 *)(NFC_BASE_ADDR + 0xE0E))) +#define NFC_RSLTSPARE_AREA (*((volatile u16 *)(NFC_BASE_ADDR + 0xE10))) +#define NFC_WRPROT (*((volatile u16 *)(NFC_BASE_ADDR + 0xE12))) +#define NFC_UNLOCKSTART_BLKADDR (*((volatile u16 *)(NFC_BASE_ADDR + 0xE14))) +#define NFC_UNLOCKEND_BLKADDR (*((volatile u16 *)(NFC_BASE_ADDR + 0xE16))) +#define NFC_NF_WRPRST (*((volatile u16 *)(NFC_BASE_ADDR + 0xE18))) +#define NFC_CONFIG1 (*((volatile u16 *)(NFC_BASE_ADDR + 0xE1A))) +#define NFC_CONFIG2 (*((volatile u16 *)(NFC_BASE_ADDR + 0xE1C))) + +#define NFC_BUFSIZE_REG_OFF (0 + 0x00) +#define RAM_BUFFER_ADDRESS_REG_OFF (0 + 0x04) +#define NAND_FLASH_ADD_REG_OFF (0 + 0x06) +#define NAND_FLASH_CMD_REG_OFF (0 + 0x08) +#define NFC_CONFIGURATION_REG_OFF (0 + 0x0A) +#define ECC_STATUS_RESULT_REG_OFF (0 + 0x0C) +#define ECC_RSLT_MAIN_AREA_REG_OFF (0 + 0x0E) +#define ECC_RSLT_SPARE_AREA_REG_OFF (0 + 0x10) +#define NF_WR_PROT_REG_OFF (0 + 0x12) +#define UNLOCK_START_BLK_ADD_REG_OFF (0 + 0x14) +#define UNLOCK_END_BLK_ADD_REG_OFF (0 + 0x16) +#define NAND_FLASH_WR_PR_ST_REG_OFF (0 + 0x18) +#define NAND_FLASH_CONFIG1_REG_OFF (0 + 0x1A) +#define NAND_FLASH_CONFIG2_REG_OFF (0 + 0x1C) +#define RAM_BUFFER_ADDRESS_RBA_3 0x3 +#define NFC_BUFSIZE_1KB 0x0 +#define NFC_BUFSIZE_2KB 0x1 +#define NFC_CONFIGURATION_UNLOCKED 0x2 +#define ECC_STATUS_RESULT_NO_ERR 0x0 +#define ECC_STATUS_RESULT_1BIT_ERR 0x1 +#define ECC_STATUS_RESULT_2BIT_ERR 0x2 +#define NF_WR_PROT_UNLOCK 0x4 +#define NAND_FLASH_CONFIG1_FORCE_CE (1 << 7) +#define NAND_FLASH_CONFIG1_RST (1 << 6) +#define NAND_FLASH_CONFIG1_BIG (1 << 5) +#define NAND_FLASH_CONFIG1_INT_MSK (1 << 4) +#define NAND_FLASH_CONFIG1_ECC_EN (1 << 3) +#define NAND_FLASH_CONFIG1_SP_EN (1 << 2) +#define NAND_FLASH_CONFIG2_INT_DONE (1 << 15) +#define NAND_FLASH_CONFIG2_FDO_PAGE (0 << 3) +#define NAND_FLASH_CONFIG2_FDO_ID (2 << 3) +#define NAND_FLASH_CONFIG2_FDO_STATUS (4 << 3) +#define NAND_FLASH_CONFIG2_FDI_EN (1 << 2) +#define NAND_FLASH_CONFIG2_FADD_EN (1 << 1) +#define NAND_FLASH_CONFIG2_FCMD_EN (1 << 0) +#define FDO_PAGE_SPARE_VAL 0x8 +#define NAND_FLASH_BOOT 0x10000000 +#define MXCFIS_NAND 0x10000000 + +/* + * Addresses for NFC RAM BUFFER Main area 0 + */ +#define MAIN_AREA0 (volatile u16 *)(NFC_BASE_ADDR + 0x000) +#define MAIN_AREA1 (volatile u16 *)(NFC_BASE_ADDR + 0x200) +#define MAIN_AREA2 (volatile u16 *)(NFC_BASE_ADDR + 0x400) +#define MAIN_AREA3 (volatile u16 *)(NFC_BASE_ADDR + 0x600) + +/* + * Addresses for NFC SPARE BUFFER Spare area 0 + */ +#define SPARE_AREA0 (volatile u16 *)(NFC_BASE_ADDR + 0x800) +#define SPARE_AREA1 (volatile u16 *)(NFC_BASE_ADDR + 0x810) +#define SPARE_AREA2 (volatile u16 *)(NFC_BASE_ADDR + 0x820) +#define SPARE_AREA3 (volatile u16 *)(NFC_BASE_ADDR + 0x830) + +#define NFC_CMD 0x1 +#define NFC_ADDR 0x2 +#define NFC_INPUT 0x4 +#define NFC_OUTPUT 0x8 +#define NFC_ID 0x10 +#define NFC_STATUS 0x20 +#define NFC_INT 0x8000 + +#define NFC_SP_EN (1 << 2) +#define NFC_ECC_EN (1 << 3) +#define NFC_INT_MSK (1 << 4) +#define NFC_BIG (1 << 5) +#define NFC_RST (1 << 6) +#define NFC_CE (1 << 7) +#define NFC_ONE_CYCLE (1 << 8) + +/* + * NFMS bit in RCSR register for pagesize of nandflash + */ +#define NFMS (*((volatile u32 *)CCM_RCSR)) +#define NFMS_BIT 30 + #endif /* __ASM_ARCH_MX31_REGS_H */ + diff --git a/include/asm-arm/arch-mx35/iomux.h b/include/asm-arm/arch-mx35/iomux.h new file mode 100644 index 0000000000..0b9f6a9cdf --- /dev/null +++ b/include/asm-arm/arch-mx35/iomux.h @@ -0,0 +1,290 @@ +/* + * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#ifndef __MACH_MX35_IOMUX_H__ +#define __MACH_MX35_IOMUX_H__ + +#include + +/*! + * @file mach-mx35/iomux.h + * + * @brief I/O Muxing control definitions and functions + * + * @ingroup GPIO_MX35 + */ + +/*! + * various IOMUX functions + */ +typedef enum iomux_pin_config { + MUX_CONFIG_FUNC = 0, /*!< used as function */ + MUX_CONFIG_ALT1, /*!< used as alternate function 1 */ + MUX_CONFIG_ALT2, /*!< used as alternate function 2 */ + MUX_CONFIG_ALT3, /*!< used as alternate function 3 */ + MUX_CONFIG_ALT4, /*!< used as alternate function 4 */ + MUX_CONFIG_ALT5, /*!< used as alternate function 5 */ + MUX_CONFIG_ALT6, /*!< used as alternate function 6 */ + MUX_CONFIG_ALT7, /*!< used as alternate function 7 */ + MUX_CONFIG_SION = 0x1 << 4, /*!< used as LOOPBACK:MUX SION bit */ + MUX_CONFIG_GPIO = MUX_CONFIG_ALT5, /*!< used as GPIO */ +} iomux_pin_cfg_t; + +/*! + * various IOMUX pad functions + */ +typedef enum iomux_pad_config { + PAD_CTL_DRV_3_3V = 0x0 << 13, + PAD_CTL_DRV_1_8V = 0x1 << 13, + PAD_CTL_HYS_CMOS = 0x0 << 8, + PAD_CTL_HYS_SCHMITZ = 0x1 << 8, + PAD_CTL_PKE_NONE = 0x0 << 7, + PAD_CTL_PKE_ENABLE = 0x1 << 7, + PAD_CTL_PUE_KEEPER = 0x0 << 6, + PAD_CTL_PUE_PUD = 0x1 << 6, + PAD_CTL_100K_PD = 0x0 << 4, + PAD_CTL_47K_PU = 0x1 << 4, + PAD_CTL_100K_PU = 0x2 << 4, + PAD_CTL_22K_PU = 0x3 << 4, + PAD_CTL_ODE_CMOS = 0x0 << 3, + PAD_CTL_ODE_OpenDrain = 0x1 << 3, + PAD_CTL_DRV_NORMAL = 0x0 << 1, + PAD_CTL_DRV_HIGH = 0x1 << 1, + PAD_CTL_DRV_MAX = 0x2 << 1, + PAD_CTL_SRE_SLOW = 0x0 << 0, + PAD_CTL_SRE_FAST = 0x1 << 0 +} iomux_pad_config_t; + +/*! + * various IOMUX general purpose functions + */ +typedef enum iomux_gp_func { + MUX_SDCTL_CSD0_SEL = 0x1 << 0, + MUX_SDCTL_CSD1_SEL = 0x1 << 1, + MUX_TAMPER_DETECT_EN = 0x1 << 2, +} iomux_gp_func_t; + +/*! + * various IOMUX input select register index + */ +typedef enum iomux_input_select { + MUX_IN_AMX_P5_RXCLK = 0, + MUX_IN_AMX_P5_RXFS, + MUX_IN_AMX_P6_DA, + MUX_IN_AMX_P6_DB, + MUX_IN_AMX_P6_RXCLK, + MUX_IN_AMX_P6_RXFS, + MUX_IN_AMX_P6_TXCLK, + MUX_IN_AMX_P6_TXFS, + MUX_IN_CAN1_CANRX, + MUX_IN_CAN2_CANRX, + MUX_IN_CCM_32K_MUXED, + MUX_IN_CCM_PMIC_RDY, + MUX_IN_CSPI1_SS2_B, + MUX_IN_CSPI1_SS3_B, + MUX_IN_CSPI2_CLK_IN, + MUX_IN_CSPI2_DATAREADY_B, + MUX_IN_CSPI2_MISO, + MUX_IN_CSPI2_MOSI, + MUX_IN_CSPI2_SS0_B, + MUX_IN_CSPI2_SS1_B, + MUX_IN_CSPI2_SS2_B, + MUX_IN_CSPI2_SS3_B, + MUX_IN_EMI_WEIM_DTACK_B, + MUX_IN_ESDHC1_DAT4_IN, + MUX_IN_ESDHC1_DAT5_IN, + MUX_IN_ESDHC1_DAT6_IN, + MUX_IN_ESDHC1_DAT7_IN, + MUX_IN_ESDHC3_CARD_CLK_IN, + MUX_IN_ESDHC3_CMD_IN, + MUX_IN_ESDHC3_DAT0, + MUX_IN_ESDHC3_DAT1, + MUX_IN_ESDHC3_DAT2, + MUX_IN_ESDHC3_DAT3, + MUX_IN_GPIO1_IN_0, + MUX_IN_GPIO1_IN_10, + MUX_IN_GPIO1_IN_11, + MUX_IN_GPIO1_IN_1, + MUX_IN_GPIO1_IN_20, + MUX_IN_GPIO1_IN_21, + MUX_IN_GPIO1_IN_22, + MUX_IN_GPIO1_IN_2, + MUX_IN_GPIO1_IN_3, + MUX_IN_GPIO1_IN_4, + MUX_IN_GPIO1_IN_5, + MUX_IN_GPIO1_IN_6, + MUX_IN_GPIO1_IN_7, + MUX_IN_GPIO1_IN_8, + MUX_IN_GPIO1_IN_9, + MUX_IN_GPIO2_IN_0, + MUX_IN_GPIO2_IN_10, + MUX_IN_GPIO2_IN_11, + MUX_IN_GPIO2_IN_12, + MUX_IN_GPIO2_IN_13, + MUX_IN_GPIO2_IN_14, + MUX_IN_GPIO2_IN_15, + MUX_IN_GPIO2_IN_16, + MUX_IN_GPIO2_IN_17, + MUX_IN_GPIO2_IN_18, + MUX_IN_GPIO2_IN_19, + MUX_IN_GPIO2_IN_20, + MUX_IN_GPIO2_IN_21, + MUX_IN_GPIO2_IN_22, + MUX_IN_GPIO2_IN_23, + MUX_IN_GPIO2_IN_24, + MUX_IN_GPIO2_IN_25, + MUX_IN_GPIO2_IN_26, + MUX_IN_GPIO2_IN_27, + MUX_IN_GPIO2_IN_28, + MUX_IN_GPIO2_IN_29, + MUX_IN_GPIO2_IN_2, + MUX_IN_GPIO2_IN_30, + MUX_IN_GPIO2_IN_31, + MUX_IN_GPIO2_IN_3, + MUX_IN_GPIO2_IN_4, + MUX_IN_GPIO2_IN_5, + MUX_IN_GPIO2_IN_6, + MUX_IN_GPIO2_IN_7, + MUX_IN_GPIO2_IN_8, + MUX_IN_GPIO2_IN_9, + MUX_IN_GPIO3_IN_0, + MUX_IN_GPIO3_IN_10, + MUX_IN_GPIO3_IN_11, + MUX_IN_GPIO3_IN_12, + MUX_IN_GPIO3_IN_13, + MUX_IN_GPIO3_IN_14, + MUX_IN_GPIO3_IN_15, + MUX_IN_GPIO3_IN_4, + MUX_IN_GPIO3_IN_5, + MUX_IN_GPIO3_IN_6, + MUX_IN_GPIO3_IN_7, + MUX_IN_GPIO3_IN_8, + MUX_IN_GPIO3_IN_9, + MUX_IN_I2C3_SCL_IN, + MUX_IN_I2C3_SDA_IN, + MUX_IN_IPU_DISPB_D0_VSYNC, + MUX_IN_IPU_DISPB_D12_VSYNC, + MUX_IN_IPU_DISPB_SD_D, + MUX_IN_IPU_SENSB_DATA_0, + MUX_IN_IPU_SENSB_DATA_1, + MUX_IN_IPU_SENSB_DATA_2, + MUX_IN_IPU_SENSB_DATA_3, + MUX_IN_IPU_SENSB_DATA_4, + MUX_IN_IPU_SENSB_DATA_5, + MUX_IN_IPU_SENSB_DATA_6, + MUX_IN_IPU_SENSB_DATA_7, + MUX_IN_KPP_COL_0, + MUX_IN_KPP_COL_1, + MUX_IN_KPP_COL_2, + MUX_IN_KPP_COL_3, + MUX_IN_KPP_COL_4, + MUX_IN_KPP_COL_5, + MUX_IN_KPP_COL_6, + MUX_IN_KPP_COL_7, + MUX_IN_KPP_ROW_0, + MUX_IN_KPP_ROW_1, + MUX_IN_KPP_ROW_2, + MUX_IN_KPP_ROW_3, + MUX_IN_KPP_ROW_4, + MUX_IN_KPP_ROW_5, + MUX_IN_KPP_ROW_6, + MUX_IN_KPP_ROW_7, + MUX_IN_OWIRE_BATTERY_LINE, + MUX_IN_SPDIF_HCKT_CLK2, + MUX_IN_SPDIF_SPDIF_IN1, + MUX_IN_UART3_UART_RTS_B, + MUX_IN_UART3_UART_RXD_MUX, + MUX_IN_USB_OTG_DATA_0, + MUX_IN_USB_OTG_DATA_1, + MUX_IN_USB_OTG_DATA_2, + MUX_IN_USB_OTG_DATA_3, + MUX_IN_USB_OTG_DATA_4, + MUX_IN_USB_OTG_DATA_5, + MUX_IN_USB_OTG_DATA_6, + MUX_IN_USB_OTG_DATA_7, + MUX_IN_USB_OTG_DIR, + MUX_IN_USB_OTG_NXT, + MUX_IN_USB_UH2_DATA_0, + MUX_IN_USB_UH2_DATA_1, + MUX_IN_USB_UH2_DATA_2, + MUX_IN_USB_UH2_DATA_3, + MUX_IN_USB_UH2_DATA_4, + MUX_IN_USB_UH2_DATA_5, + MUX_IN_USB_UH2_DATA_6, + MUX_IN_USB_UH2_DATA_7, + MUX_IN_USB_UH2_DIR, + MUX_IN_USB_UH2_NXT, + MUX_IN_USB_UH2_USB_OC, +} iomux_input_select_t; + +/*! + * various IOMUX input functions + */ +typedef enum iomux_input_config { + INPUT_CTL_PATH0 = 0x0, + INPUT_CTL_PATH1, + INPUT_CTL_PATH2, + INPUT_CTL_PATH3, + INPUT_CTL_PATH4, + INPUT_CTL_PATH5, + INPUT_CTL_PATH6, + INPUT_CTL_PATH7, +} iomux_input_cfg_t; + +/*! + * Request ownership for an IO pin. This function has to be the first one + * being called before that pin is used. The caller has to check the + * return value to make sure it returns 0. + * + * @param pin a name defined by \b iomux_pin_name_t + * @param cfg an input function as defined in \b #iomux_pin_cfg_t + * + * @return 0 if successful; Non-zero otherwise + */ +int mxc_request_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg); + +/*! + * Release ownership for an IO pin + * + * @param pin a name defined by \b iomux_pin_name_t + * @param cfg an input function as defined in \b #iomux_pin_cfg_t + */ +void mxc_free_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg); + +/*! + * This function enables/disables the general purpose function for a particular + * signal. + * + * @param gp one signal as defined in \b #iomux_gp_func_t + * @param en \b #true to enable; \b #false to disable + */ +void mxc_iomux_set_gpr(iomux_gp_func_t gp, int en); + +/*! + * This function configures the pad value for a IOMUX pin. + * + * @param pin a pin number as defined in \b #iomux_pin_name_t + * @param config the ORed value of elements defined in \b + * #iomux_pad_config_t + */ +void mxc_iomux_set_pad(iomux_pin_name_t pin, u32 config); + +/*! + * This function configures input path. + * + * @param input index of input select register as defined in \b + * #iomux_input_select_t + * @param config the binary value of elements defined in \b + * #iomux_input_cfg_t + */ +void mxc_iomux_set_input(iomux_input_select_t input, u32 config); +#endif diff --git a/include/asm-arm/arch-mx35/mmu.h b/include/asm-arm/arch-mx35/mmu.h new file mode 100644 index 0000000000..1b15dba68d --- /dev/null +++ b/include/asm-arm/arch-mx35/mmu.h @@ -0,0 +1,172 @@ +/* + * Copyright 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#ifndef __ARM_ARCH_MMU_H +#define __ARM_ARCH_MMU_H + +/* + * Translation Table Base Bit Masks + */ +#define ARM_TRANSLATION_TABLE_MASK 0xFFFFC000 + +/* + * Domain Access Control Bit Masks + */ +#define ARM_ACCESS_TYPE_NO_ACCESS(domain_num) (0x0 << (domain_num)*2) +#define ARM_ACCESS_TYPE_CLIENT(domain_num) (0x1 << (domain_num)*2) +#define ARM_ACCESS_TYPE_MANAGER(domain_num) (0x3 << (domain_num)*2) + +struct ARM_MMU_FIRST_LEVEL_FAULT { + unsigned int id:2; + unsigned int sbz:30; +}; + +#define ARM_MMU_FIRST_LEVEL_FAULT_ID 0x0 + +struct ARM_MMU_FIRST_LEVEL_PAGE_TABLE { + unsigned int id:2; + unsigned int imp:2; + unsigned int domain:4; + unsigned int sbz:1; + unsigned int base_address:23; +}; + +#define ARM_MMU_FIRST_LEVEL_PAGE_TABLE_ID 0x1 + +struct ARM_MMU_FIRST_LEVEL_SECTION { + unsigned int id:2; + unsigned int b:1; + unsigned int c:1; + unsigned int imp:1; + unsigned int domain:4; + unsigned int sbz0:1; + unsigned int ap:2; + unsigned int sbz1:8; + unsigned int base_address:12; +}; + +#define ARM_MMU_FIRST_LEVEL_SECTION_ID 0x2 + +struct ARM_MMU_FIRST_LEVEL_RESERVED { + unsigned int id:2; + unsigned int sbz:30; +}; + +#define ARM_MMU_FIRST_LEVEL_RESERVED_ID 0x3 + +#define ARM_MMU_FIRST_LEVEL_DESCRIPTOR_ADDRESS(ttb_base, table_index) \ + (unsigned long *)((unsigned long)(ttb_base) + ((table_index) << 2)) + +#define ARM_FIRST_LEVEL_PAGE_TABLE_SIZE 0x4000 + +#define ARM_MMU_SECTION(ttb_base, actual_base, virtual_base, \ + cacheable, bufferable, perm) \ + { \ + register union ARM_MMU_FIRST_LEVEL_DESCRIPTOR desc; \ + desc.word = 0; \ + desc.section.id = ARM_MMU_FIRST_LEVEL_SECTION_ID; \ + desc.section.domain = 0; \ + desc.section.c = (cacheable); \ + desc.section.b = (bufferable); \ + desc.section.ap = (perm); \ + desc.section.base_address = (actual_base); \ + *ARM_MMU_FIRST_LEVEL_DESCRIPTOR_ADDRESS(ttb_base, (virtual_base)) \ + = desc.word; \ + } + +#define X_ARM_MMU_SECTION(abase, vbase, size, cache, buff, access) \ + { \ + int i; int j = abase; int k = vbase; \ + for (i = size; i > 0 ; i--, j++, k++) \ + ARM_MMU_SECTION(ttb_base, j, k, cache, buff, access); \ + } + +union ARM_MMU_FIRST_LEVEL_DESCRIPTOR { + unsigned long word; + struct ARM_MMU_FIRST_LEVEL_FAULT fault; + struct ARM_MMU_FIRST_LEVEL_PAGE_TABLE page_table; + struct ARM_MMU_FIRST_LEVEL_SECTION section; + struct ARM_MMU_FIRST_LEVEL_RESERVED reserved; +}; + +#define ARM_UNCACHEABLE 0 +#define ARM_CACHEABLE 1 +#define ARM_UNBUFFERABLE 0 +#define ARM_BUFFERABLE 1 + +#define ARM_ACCESS_PERM_NONE_NONE 0 +#define ARM_ACCESS_PERM_RO_NONE 0 +#define ARM_ACCESS_PERM_RO_RO 0 +#define ARM_ACCESS_PERM_RW_NONE 1 +#define ARM_ACCESS_PERM_RW_RO 2 +#define ARM_ACCESS_PERM_RW_RW 3 + +/* + * Initialization for the Domain Access Control Register + */ +#define ARM_ACCESS_DACR_DEFAULT ( \ + ARM_ACCESS_TYPE_MANAGER(0) | \ + ARM_ACCESS_TYPE_NO_ACCESS(1) | \ + ARM_ACCESS_TYPE_NO_ACCESS(2) | \ + ARM_ACCESS_TYPE_NO_ACCESS(3) | \ + ARM_ACCESS_TYPE_NO_ACCESS(4) | \ + ARM_ACCESS_TYPE_NO_ACCESS(5) | \ + ARM_ACCESS_TYPE_NO_ACCESS(6) | \ + ARM_ACCESS_TYPE_NO_ACCESS(7) | \ + ARM_ACCESS_TYPE_NO_ACCESS(8) | \ + ARM_ACCESS_TYPE_NO_ACCESS(9) | \ + ARM_ACCESS_TYPE_NO_ACCESS(10) | \ + ARM_ACCESS_TYPE_NO_ACCESS(11) | \ + ARM_ACCESS_TYPE_NO_ACCESS(12) | \ + ARM_ACCESS_TYPE_NO_ACCESS(13) | \ + ARM_ACCESS_TYPE_NO_ACCESS(14) | \ + ARM_ACCESS_TYPE_NO_ACCESS(15)) + +/* + * Translate the virtual address of ram space to physical address + * It is dependent on the implementation of mmu_init + */ +inline unsigned long iomem_to_phys(unsigned long virt) +{ + if (virt < 0x08000000) + return (unsigned long)(virt | PHYS_SDRAM_1); + + if ((virt & 0xF0000000) == PHYS_SDRAM_1) + return (unsigned long)(virt & (~0x08000000)); + + return (unsigned long)virt; +} + +/* + * Remap the physical address of ram space to uncacheable virtual address space + * It is dependent on the implementation of hal_mmu_init + */ +void __iounmap(void *addr) +{ + return; +} + +void *__ioremap(unsigned long offset, size_t size, unsigned long flags) +{ + if (1 == flags) { + /* 0x88000000~0x87FFFFFF is uncacheable meory + space which is mapped to SDRAM */ + if ((offset & 0xF0000000) == PHYS_SDRAM_1) + return (void *)(offset | 0x08000000); + else + return NULL; + } else + return (void *)offset; +} + +#endif diff --git a/include/asm-arm/arch-mx35/mx35.h b/include/asm-arm/arch-mx35/mx35.h new file mode 100644 index 0000000000..45ddc0f3b4 --- /dev/null +++ b/include/asm-arm/arch-mx35/mx35.h @@ -0,0 +1,297 @@ +/* + * + * (c) 2007 Pengutronix, Sascha Hauer + * + * (C) Copyright 2008-2009 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ASM_ARCH_MX35_H +#define __ASM_ARCH_MX35_H + +#define __REG(x) (*((volatile u32 *)(x))) +#define __REG16(x) (*((volatile u16 *)(x))) +#define __REG8(x) (*((volatile u8 *)(x))) + +#define L2CC_BASE_ADDR 0x30000000 + +/* + * AIPS 1 + */ +#define AIPS1_BASE_ADDR 0x43F00000 +#define AIPS1_CTRL_BASE_ADDR AIPS1_BASE_ADDR +#define MAX_BASE_ADDR 0x43F04000 +#define EVTMON_BASE_ADDR 0x43F08000 +#define CLKCTL_BASE_ADDR 0x43F0C000 +#define I2C_BASE_ADDR 0x43F80000 +#define I2C3_BASE_ADDR 0x43F84000 +#define ATA_BASE_ADDR 0x43F8C000 +#define UART1_BASE_ADDR 0x43F90000 +#define UART2_BASE_ADDR 0x43F94000 +#define I2C2_BASE_ADDR 0x43F98000 +#define CSPI1_BASE_ADDR 0x43FA4000 +#define IOMUXC_BASE_ADDR 0x43FAC000 + +/* + * SPBA + */ +#define SPBA_BASE_ADDR 0x50000000 +#define UART3_BASE_ADDR 0x5000C000 +#define CSPI2_BASE_ADDR 0x50010000 +#define ATA_DMA_BASE_ADDR 0x50020000 +#define FEC_BASE_ADDR 0x50038000 +#define SPBA_CTRL_BASE_ADDR 0x5003C000 + +/* + * AIPS 2 + */ +#define AIPS2_BASE_ADDR 0x53F00000 +#define AIPS2_CTRL_BASE_ADDR AIPS2_BASE_ADDR +#define CCM_BASE_ADDR 0x53F80000 +#define GPT1_BASE_ADDR 0x53F90000 +#define EPIT1_BASE_ADDR 0x53F94000 +#define EPIT2_BASE_ADDR 0x53F98000 +#define GPIO3_BASE_ADDR 0x53FA4000 +#define MMC_SDHC1_BASE_ADDR 0x53FB4000 +#define MMC_SDHC2_BASE_ADDR 0x53FB8000 +#define MMC_SDHC3_BASE_ADDR 0x53FBC000 +#define IPU_CTRL_BASE_ADDR 0x53FC0000 +#define GPIO3_BASE_ADDR 0x53FA4000 +#define GPIO1_BASE_ADDR 0x53FCC000 +#define GPIO2_BASE_ADDR 0x53FD0000 +#define SDMA_BASE_ADDR 0x53FD4000 +#define RTC_BASE_ADDR 0x53FD8000 +#define WDOG_BASE_ADDR 0x53FDC000 +#define PWM_BASE_ADDR 0x53FE0000 +#define RTIC_BASE_ADDR 0x53FEC000 +#define IIM_BASE_ADDR 0x53FF0000 + +/* + * ROMPATCH and AVIC + */ +#define ROMPATCH_BASE_ADDR 0x60000000 +#define AVIC_BASE_ADDR 0x68000000 + +/* + * NAND, SDRAM, WEIM, M3IF, EMI controllers + */ +#define EXT_MEM_CTRL_BASE 0xB8000000 +#define ESDCTL_BASE_ADDR 0xB8001000 +#define WEIM_BASE_ADDR 0xB8002000 +#define WEIM_CTRL_CS0 WEIM_BASE_ADDR +#define WEIM_CTRL_CS1 (WEIM_BASE_ADDR + 0x10) +#define WEIM_CTRL_CS2 (WEIM_BASE_ADDR + 0x20) +#define WEIM_CTRL_CS3 (WEIM_BASE_ADDR + 0x30) +#define WEIM_CTRL_CS4 (WEIM_BASE_ADDR + 0x40) +#define WEIM_CTRL_CS5 (WEIM_BASE_ADDR + 0x50) +#define M3IF_BASE_ADDR 0xB8003000 +#define EMI_BASE_ADDR 0xB8004000 + +#define NFC_BASE_ADDR 0xBB000000 + +/* + * Memory regions and CS + */ +#define IPU_MEM_BASE_ADDR 0x70000000 +#define CSD0_BASE_ADDR 0x80000000 +#define CSD1_BASE_ADDR 0x90000000 +#define CS0_BASE_ADDR 0xA0000000 +#define CS1_BASE_ADDR 0xA8000000 +#define CS2_BASE_ADDR 0xB0000000 +#define CS3_BASE_ADDR 0xB2000000 +#define CS4_BASE_ADDR 0xB4000000 +#define CS5_BASE_ADDR 0xB6000000 + +/* + * IRQ Controller Register Definitions. + */ +#define AVIC_NIMASK 0x04 +#define AVIC_INTTYPEH 0x18 +#define AVIC_INTTYPEL 0x1C + +/* L210 */ +#define L2CC_BASE_ADDR 0x30000000 +#define L2_CACHE_LINE_SIZE 32 +#define L2_CACHE_CTL_REG 0x100 +#define L2_CACHE_AUX_CTL_REG 0x104 +#define L2_CACHE_SYNC_REG 0x730 +#define L2_CACHE_INV_LINE_REG 0x770 +#define L2_CACHE_INV_WAY_REG 0x77C +#define L2_CACHE_CLEAN_LINE_REG 0x7B0 +#define L2_CACHE_CLEAN_INV_LINE_REG 0x7F0 +#define L2_CACHE_DBG_CTL_REG 0xF40 + +/* CCM */ +#define CLKCTL_CCMR 0x00 +#define CLKCTL_PDR0 0x04 +#define CLKCTL_PDR1 0x08 +#define CLKCTL_PDR2 0x0C +#define CLKCTL_PDR3 0x10 +#define CLKCTL_PDR4 0x14 +#define CLKCTL_RCSR 0x18 +#define CLKCTL_MPCTL 0x1C +#define CLKCTL_PPCTL 0x20 +#define CLKCTL_ACMR 0x24 +#define CLKCTL_COSR 0x28 +#define CLKCTL_CGR0 0x2C +#define CLKCTL_CGR1 0x30 +#define CLKCTL_CGR2 0x34 +#define CLKCTL_CGR3 0x38 + +#define CLKMODE_AUTO 0 +#define CLKMODE_CONSUMER 1 + +#define PLL_PD(x) (((x) & 0xf) << 26) +#define PLL_MFD(x) (((x) & 0x3ff) << 16) +#define PLL_MFI(x) (((x) & 0xf) << 10) +#define PLL_MFN(x) (((x) & 0x3ff) << 0) + +#define CSCR_U(x) (WEIM_CTRL_CS#x + 0) +#define CSCR_L(x) (WEIM_CTRL_CS#x + 4) +#define CSCR_A(x) (WEIM_CTRL_CS#x + 8) + +#define IIM_SREV 0x24 +#define ROMPATCH_REV 0x40 + +#define IPU_CONF IPU_CTRL_BASE_ADDR + +#define IPU_CONF_PXL_ENDIAN (1<<8) +#define IPU_CONF_DU_EN (1<<7) +#define IPU_CONF_DI_EN (1<<6) +#define IPU_CONF_ADC_EN (1<<5) +#define IPU_CONF_SDC_EN (1<<4) +#define IPU_CONF_PF_EN (1<<3) +#define IPU_CONF_ROT_EN (1<<2) +#define IPU_CONF_IC_EN (1<<1) +#define IPU_CONF_SCI_EN (1<<0) + +#define GPIO_PORT_NUM 3 +#define GPIO_NUM_PIN 32 + +#define NFC_BUF_SIZE 0x1000 +#define NFC_BUFSIZE_REG_OFF (0 + 0x00) +#define RAM_BUFFER_ADDRESS_REG_OFF (0 + 0x04) +#define NAND_FLASH_ADD_REG_OFF (0 + 0x06) +#define NAND_FLASH_CMD_REG_OFF (0 + 0x08) +#define NFC_CONFIGURATION_REG_OFF (0 + 0x0A) +#define ECC_STATUS_RESULT_REG_OFF (0 + 0x0C) +#define ECC_RSLT_MAIN_AREA_REG_OFF (0 + 0x0E) +#define ECC_RSLT_SPARE_AREA_REG_OFF (0 + 0x10) +#define NF_WR_PROT_REG_OFF (0 + 0x12) +#define NAND_FLASH_WR_PR_ST_REG_OFF (0 + 0x18) +#define NAND_FLASH_CONFIG1_REG_OFF (0 + 0x1A) +#define NAND_FLASH_CONFIG2_REG_OFF (0 + 0x1C) +#define UNLOCK_START_BLK_ADD_REG_OFF (0 + 0x20) +#define UNLOCK_END_BLK_ADD_REG_OFF (0 + 0x22) +#define RAM_BUFFER_ADDRESS_RBA_3 0x3 +#define NFC_BUFSIZE_1KB 0x0 +#define NFC_BUFSIZE_2KB 0x1 +#define NFC_CONFIGURATION_UNLOCKED 0x2 +#define ECC_STATUS_RESULT_NO_ERR 0x0 +#define ECC_STATUS_RESULT_1BIT_ERR 0x1 +#define ECC_STATUS_RESULT_2BIT_ERR 0x2 +#define NF_WR_PROT_UNLOCK 0x4 +#define NAND_FLASH_CONFIG1_FORCE_CE (1 << 7) +#define NAND_FLASH_CONFIG1_RST (1 << 6) +#define NAND_FLASH_CONFIG1_BIG (1 << 5) +#define NAND_FLASH_CONFIG1_INT_MSK (1 << 4) +#define NAND_FLASH_CONFIG1_ECC_EN (1 << 3) +#define NAND_FLASH_CONFIG1_SP_EN (1 << 2) +#define NAND_FLASH_CONFIG2_INT_DONE (1 << 15) +#define NAND_FLASH_CONFIG2_FDO_PAGE (0 << 3) +#define NAND_FLASH_CONFIG2_FDO_ID (2 << 3) +#define NAND_FLASH_CONFIG2_FDO_STATUS (4 << 3) +#define NAND_FLASH_CONFIG2_FDI_EN (1 << 2) +#define NAND_FLASH_CONFIG2_FADD_EN (1 << 1) +#define NAND_FLASH_CONFIG2_FCMD_EN (1 << 0) +#define FDO_PAGE_SPARE_VAL 0x8 +#define NAND_BUF_NUM 8 + +#define CHIP_REV_1_0 0x10 +#define CHIP_REV_2_0 0x20 + +#define BOARD_REV_1_0 0x0 +#define BOARD_REV_2_0 0x1 + +#ifndef __ASSEMBLER__ + + +enum mxc_clock { +MXC_ARM_CLK = 0, +MXC_AHB_CLK, +MXC_IPG_CLK, +MXC_IPG_PERCLK, +MXC_UART_CLK, +MXC_ESDHC_CLK, +MXC_USB_CLK, +}; + +enum plls { + MCU_PLL = CCM_BASE_ADDR + CLKCTL_MPCTL, + PER_PLL = CCM_BASE_ADDR + CLKCTL_PPCTL, +}; + +enum mxc_main_clocks { + CPU_CLK, + AHB_CLK, + IPG_CLK, + IPG_PER_CLK, + NFC_CLK, + USB_CLK, + HSP_CLK, +}; + +enum mxc_peri_clocks { + UART1_BAUD, + UART2_BAUD, + UART3_BAUD, + SSI1_BAUD, + SSI2_BAUD, + CSI_BAUD, + MSHC_CLK, + ESDHC1_CLK, + ESDHC2_CLK, + ESDHC3_CLK, + SPDIF_CLK, + SPI1_CLK, + SPI2_CLK, +}; +/*! + * NFMS bit in RCSR register for pagesize of nandflash + */ +#define NFMS (*((volatile u32 *)(CCM_BASE_ADDR+0x18))) +#define NFMS_BIT 8 +#define NFMS_NF_DWIDTH 14 +#define NFMS_NF_PG_SZ 8 + + +extern unsigned int mxc_get_clock(enum mxc_clock clk); +extern unsigned int get_board_rev(void); +extern int is_soc_rev(int rev); +extern int sdhc_init(void); + +#define fixup_before_linux \ + { \ + volatile unsigned long *l2cc_ctl = (unsigned long *)0x30000100;\ + if (is_soc_rev(CHIP_REV_2_0) < 0) \ + *l2cc_ctl = 1;\ + } +#endif /* __ASSEMBLER__*/ +#endif /* __ASM_ARCH_MX35_H */ diff --git a/include/asm-arm/arch-mx35/mx35_pins.h b/include/asm-arm/arch-mx35/mx35_pins.h new file mode 100644 index 0000000000..be4012b81d --- /dev/null +++ b/include/asm-arm/arch-mx35/mx35_pins.h @@ -0,0 +1,342 @@ +/* + * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#ifndef __ASM_ARCH_MXC_MX35_PINS_H__ +#define __ASM_ARCH_MXC_MX35_PINS_H__ + +/*! + * @file arch-mxc/mx35_pins.h + * + * @brief MX35 I/O Pin List + * + * @ingroup GPIO_MX35 + */ + +#ifndef __ASSEMBLY__ + +/*! + * @name IOMUX/PAD Bit field definitions + */ + +/*! @{ */ + +/*! + * In order to identify pins more effectively, each mux-controlled pin's + * enumerated value is constructed in the following way: + * + * ------------------------------------------------------------------- + * 31-29 | 28 - 24 |23 - 21| 20 - 10| 9 - 0 + * ------------------------------------------------------------------- + * IO_P | IO_I | RSVD | PAD_I | MUX_I + * ------------------------------------------------------------------- + * + * Bit 0 to 7 contains MUX_I used to identify the register + * offset (base is IOMUX_module_base ) defined in the Section + * "sw_pad_ctl & sw_mux_ctl details" of the IC Spec. The similar field + * definitions are used for the pad control register.the MX35_PIN_A0 is + * defined in the enumeration: ( 0x28 << MUX_I) |( 0x368 << PAD_I) + * So the absolute address is: IOMUX_module_base + 0x28. + * The pad control register offset is: 0x368. + */ + +/*! + * Starting bit position within each entry of \b iomux_pins to represent the + * MUX control register offset + */ +#define MUX_I 0 +/*! + * Starting bit position within each entry of \b iomux_pins to represent the + * PAD control register offset + */ +#define PAD_I 10 + +/*! + * Starting bit position within each entry of \b iomux_pins to represent the + * reserved filed + */ +#define RSVD_I 21 + +#define MUX_IO_P 29 +#define MUX_IO_I 24 +#define IOMUX_TO_GPIO(pin) ((((unsigned int)pin >> MUX_IO_P) * \ + GPIO_NUM_PIN) + ((pin >> MUX_IO_I) &\ + ((1 << (MUX_IO_P - MUX_IO_I)) - 1))) +#define IOMUX_TO_IRQ(pin) (MXC_GPIO_INT_BASE + IOMUX_TO_GPIO(pin)) +#define GPIO_TO_PORT(n) (n / GPIO_NUM_PIN) +#define GPIO_TO_INDEX(n) (n % GPIO_NUM_PIN) + +#define NON_GPIO_I 0x7 +#define PIN_TO_MUX_MASK ((1<<(PAD_I - MUX_I)) - 1) +#define PIN_TO_PAD_MASK ((1<<(RSVD_I - PAD_I)) - 1) +#define NON_MUX_I PIN_TO_MUX_MASK + +#define _MXC_BUILD_PIN(gp, gi, mi, pi) \ + (((gp) << MUX_IO_P) | ((gi) << MUX_IO_I) | \ + ((mi) << MUX_I) | ((pi) << PAD_I)) + +#define _MXC_BUILD_GPIO_PIN(gp, gi, mi, pi) \ + _MXC_BUILD_PIN(gp, gi, mi, pi) + +#define _MXC_BUILD_NON_GPIO_PIN(mi, pi) \ + _MXC_BUILD_PIN(NON_GPIO_I, 0, mi, pi) + +#define PIN_TO_IOMUX_MUX(pin) ((pin >> MUX_I) & PIN_TO_MUX_MASK) +#define PIN_TO_IOMUX_PAD(pin) ((pin >> PAD_I) & PIN_TO_PAD_MASK) + +/*! @} End IOMUX/PAD Bit field definitions */ + +/*! + * This enumeration is constructed based on the Section + * "sw_pad_ctl & sw_mux_ctl details" of the MX35 IC Spec. Each enumerated + * value is constructed based on the rules described above. + */ +typedef enum iomux_pins { + MX35_PIN_CAPTURE = _MXC_BUILD_GPIO_PIN(0, 4, 0x4, 0x328), + MX35_PIN_COMPARE = _MXC_BUILD_GPIO_PIN(0, 5, 0x8, 0x32C), + MX35_PIN_WATCHDOG_RST = _MXC_BUILD_GPIO_PIN(0, 6, 0xC, 0x330), + MX35_PIN_GPIO1_0 = _MXC_BUILD_GPIO_PIN(0, 0, 0x10, 0x334), + MX35_PIN_GPIO1_1 = _MXC_BUILD_GPIO_PIN(0, 1, 0x14, 0x338), + MX35_PIN_GPIO2_0 = _MXC_BUILD_GPIO_PIN(1, 0, 0x18, 0x33C), + MX35_PIN_GPIO3_0 = _MXC_BUILD_GPIO_PIN(2, 1, 0x1C, 0x340), + MX35_PIN_CLKO = _MXC_BUILD_GPIO_PIN(0, 8, 0x20, 0x34C), + + MX35_PIN_POWER_FAIL = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x360), + MX35_PIN_VSTBY = _MXC_BUILD_GPIO_PIN(0, 7, 0x24, 0x364), + MX35_PIN_A0 = _MXC_BUILD_NON_GPIO_PIN(0x28, 0x368), + MX35_PIN_A1 = _MXC_BUILD_NON_GPIO_PIN(0x2C, 0x36C), + MX35_PIN_A2 = _MXC_BUILD_NON_GPIO_PIN(0x30, 0x370), + MX35_PIN_A3 = _MXC_BUILD_NON_GPIO_PIN(0x34, 0x374), + MX35_PIN_A4 = _MXC_BUILD_NON_GPIO_PIN(0x38, 0x378), + MX35_PIN_A5 = _MXC_BUILD_NON_GPIO_PIN(0x3C, 0x37C), + MX35_PIN_A6 = _MXC_BUILD_NON_GPIO_PIN(0x40, 0x380), + MX35_PIN_A7 = _MXC_BUILD_NON_GPIO_PIN(0x44, 0x384), + MX35_PIN_A8 = _MXC_BUILD_NON_GPIO_PIN(0x48, 0x388), + MX35_PIN_A9 = _MXC_BUILD_NON_GPIO_PIN(0x4C, 0x38C), + MX35_PIN_A10 = _MXC_BUILD_NON_GPIO_PIN(0x50, 0x390), + MX35_PIN_MA10 = _MXC_BUILD_NON_GPIO_PIN(0x54, 0x394), + MX35_PIN_A11 = _MXC_BUILD_NON_GPIO_PIN(0x58, 0x398), + MX35_PIN_A12 = _MXC_BUILD_NON_GPIO_PIN(0x5C, 0x39C), + MX35_PIN_A13 = _MXC_BUILD_NON_GPIO_PIN(0x60, 0x3A0), + MX35_PIN_A14 = _MXC_BUILD_NON_GPIO_PIN(0x64, 0x3A4), + MX35_PIN_A15 = _MXC_BUILD_NON_GPIO_PIN(0x68, 0x3A8), + MX35_PIN_A16 = _MXC_BUILD_NON_GPIO_PIN(0x6C, 0x3AC), + MX35_PIN_A17 = _MXC_BUILD_NON_GPIO_PIN(0x70, 0x3B0), + MX35_PIN_A18 = _MXC_BUILD_NON_GPIO_PIN(0x74, 0x3B4), + MX35_PIN_A19 = _MXC_BUILD_NON_GPIO_PIN(0x78, 0x3B8), + MX35_PIN_A20 = _MXC_BUILD_NON_GPIO_PIN(0x7C, 0x3BC), + MX35_PIN_A21 = _MXC_BUILD_NON_GPIO_PIN(0x80, 0x3C0), + MX35_PIN_A22 = _MXC_BUILD_NON_GPIO_PIN(0x84, 0x3C4), + MX35_PIN_A23 = _MXC_BUILD_NON_GPIO_PIN(0x88, 0x3C8), + MX35_PIN_A24 = _MXC_BUILD_NON_GPIO_PIN(0x8C, 0x3CC), + MX35_PIN_A25 = _MXC_BUILD_NON_GPIO_PIN(0x90, 0x3D0), + + MX35_PIN_EB0 = _MXC_BUILD_NON_GPIO_PIN(0x94, 0x46C), + MX35_PIN_EB1 = _MXC_BUILD_NON_GPIO_PIN(0x98, 0x470), + MX35_PIN_OE = _MXC_BUILD_NON_GPIO_PIN(0x9C, 0x474), + MX35_PIN_CS0 = _MXC_BUILD_NON_GPIO_PIN(0xA0, 0x478), + MX35_PIN_CS1 = _MXC_BUILD_NON_GPIO_PIN(0xA4, 0x47C), + MX35_PIN_CS2 = _MXC_BUILD_NON_GPIO_PIN(0xA8, 0x480), + MX35_PIN_CS3 = _MXC_BUILD_NON_GPIO_PIN(0xAC, 0x484), + MX35_PIN_CS4 = _MXC_BUILD_GPIO_PIN(0, 20, 0xB0, 0x488), + MX35_PIN_CS5 = _MXC_BUILD_GPIO_PIN(0, 21, 0xB4, 0x48C), + MX35_PIN_NFCE_B = _MXC_BUILD_GPIO_PIN(0, 22, 0xB8, 0x490), + + MX35_PIN_LBA = _MXC_BUILD_NON_GPIO_PIN(0xBC, 0x498), + MX35_PIN_BCLK = _MXC_BUILD_NON_GPIO_PIN(0xC0, 0x49C), + MX35_PIN_RW = _MXC_BUILD_NON_GPIO_PIN(0xC4, 0x4A0), + + MX35_PIN_NFWE_B = _MXC_BUILD_GPIO_PIN(0, 18, 0xC8, 0x4CC), + MX35_PIN_NFRE_B = _MXC_BUILD_GPIO_PIN(0, 19, 0xCC, 0x4D0), + MX35_PIN_NFALE = _MXC_BUILD_GPIO_PIN(0, 20, 0xD0, 0x4D4), + MX35_PIN_NFCLE = _MXC_BUILD_GPIO_PIN(0, 21, 0xD4, 0x4D8), + MX35_PIN_NFWP_B = _MXC_BUILD_GPIO_PIN(0, 22, 0xD8, 0x4DC), + MX35_PIN_NFRB = _MXC_BUILD_GPIO_PIN(0, 23, 0xDC, 0x4E0), + + MX35_PIN_D15 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x4E4), + MX35_PIN_D14 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x4E8), + MX35_PIN_D13 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x4EC), + MX35_PIN_D12 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x4F0), + MX35_PIN_D11 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x4F4), + MX35_PIN_D10 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x4F8), + MX35_PIN_D9 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x4FC), + MX35_PIN_D8 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x500), + MX35_PIN_D7 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x504), + MX35_PIN_D6 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x508), + MX35_PIN_D5 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x50C), + MX35_PIN_D4 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x510), + MX35_PIN_D3 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x514), + MX35_PIN_D2 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x518), + MX35_PIN_D1 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x51C), + MX35_PIN_D0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x520), + + MX35_PIN_CSI_D8 = _MXC_BUILD_GPIO_PIN(0, 20, 0xE0, 0x524), + MX35_PIN_CSI_D9 = _MXC_BUILD_GPIO_PIN(0, 21, 0xE4, 0x528), + MX35_PIN_CSI_D10 = _MXC_BUILD_GPIO_PIN(0, 22, 0xE8, 0x52C), + MX35_PIN_CSI_D11 = _MXC_BUILD_GPIO_PIN(0, 23, 0xEC, 0x530), + MX35_PIN_CSI_D12 = _MXC_BUILD_GPIO_PIN(0, 24, 0xF0, 0x534), + MX35_PIN_CSI_D13 = _MXC_BUILD_GPIO_PIN(0, 25, 0xF4, 0x538), + MX35_PIN_CSI_D14 = _MXC_BUILD_GPIO_PIN(0, 26, 0xF8, 0x53C), + MX35_PIN_CSI_D15 = _MXC_BUILD_GPIO_PIN(0, 27, 0xFC, 0x540), + MX35_PIN_CSI_MCLK = _MXC_BUILD_GPIO_PIN(0, 28, 0x100, 0x544), + MX35_PIN_CSI_VSYNC = _MXC_BUILD_GPIO_PIN(0, 29, 0x104, 0x548), + MX35_PIN_CSI_HSYNC = _MXC_BUILD_GPIO_PIN(0, 30, 0x108, 0x54C), + MX35_PIN_CSI_PIXCLK = _MXC_BUILD_GPIO_PIN(0, 31, 0x10C, 0x550), + + MX35_PIN_I2C1_CLK = _MXC_BUILD_GPIO_PIN(1, 24, 0x110, 0x554), + MX35_PIN_I2C1_DAT = _MXC_BUILD_GPIO_PIN(1, 25, 0x114, 0x558), + MX35_PIN_I2C2_CLK = _MXC_BUILD_GPIO_PIN(1, 26, 0x118, 0x55C), + MX35_PIN_I2C2_DAT = _MXC_BUILD_GPIO_PIN(1, 27, 0x11C, 0x560), + + MX35_PIN_STXD4 = _MXC_BUILD_GPIO_PIN(1, 28, 0x120, 0x564), + MX35_PIN_SRXD4 = _MXC_BUILD_GPIO_PIN(1, 29, 0x124, 0x568), + MX35_PIN_SCK4 = _MXC_BUILD_GPIO_PIN(1, 30, 0x128, 0x56C), + MX35_PIN_STXFS4 = _MXC_BUILD_GPIO_PIN(1, 31, 0x12C, 0x570), + MX35_PIN_STXD5 = _MXC_BUILD_GPIO_PIN(0, 0, 0x130, 0x574), + MX35_PIN_SRXD5 = _MXC_BUILD_GPIO_PIN(0, 1, 0x134, 0x578), + MX35_PIN_SCK5 = _MXC_BUILD_GPIO_PIN(0, 2, 0x138, 0x57C), + MX35_PIN_STXFS5 = _MXC_BUILD_GPIO_PIN(0, 3, 0x13C, 0x580), + + MX35_PIN_SCKR = _MXC_BUILD_GPIO_PIN(0, 4, 0x140, 0x584), + MX35_PIN_FSR = _MXC_BUILD_GPIO_PIN(0, 5, 0x144, 0x588), + MX35_PIN_HCKR = _MXC_BUILD_GPIO_PIN(0, 6, 0x148, 0x58C), + MX35_PIN_SCKT = _MXC_BUILD_GPIO_PIN(0, 7, 0x14C, 0x590), + MX35_PIN_FST = _MXC_BUILD_GPIO_PIN(0, 8, 0x150, 0x594), + MX35_PIN_HCKT = _MXC_BUILD_GPIO_PIN(0, 9, 0x154, 0x598), + MX35_PIN_TX5_RX0 = _MXC_BUILD_GPIO_PIN(0, 10, 0x158, 0x59C), + MX35_PIN_TX4_RX1 = _MXC_BUILD_GPIO_PIN(0, 11, 0x15C, 0x5A0), + MX35_PIN_TX3_RX2 = _MXC_BUILD_GPIO_PIN(0, 12, 0x160, 0x5A4), + MX35_PIN_TX2_RX3 = _MXC_BUILD_GPIO_PIN(0, 13, 0x164, 0x5A8), + MX35_PIN_TX1 = _MXC_BUILD_GPIO_PIN(0, 14, 0x168, 0x5AC), + MX35_PIN_TX0 = _MXC_BUILD_GPIO_PIN(0, 15, 0x16C, 0x5B0), + + MX35_PIN_CSPI1_MOSI = _MXC_BUILD_GPIO_PIN(0, 16, 0x170, 0x5B4), + MX35_PIN_CSPI1_MISO = _MXC_BUILD_GPIO_PIN(0, 17, 0x174, 0x5B8), + MX35_PIN_CSPI1_SS0 = _MXC_BUILD_GPIO_PIN(0, 18, 0x178, 0x5BC), + MX35_PIN_CSPI1_SS1 = _MXC_BUILD_GPIO_PIN(0, 19, 0x17C, 0x5C0), + MX35_PIN_CSPI1_SCLK = _MXC_BUILD_GPIO_PIN(2, 4, 0x180, 0x5C4), + MX35_PIN_CSPI1_SPI_RDY = _MXC_BUILD_GPIO_PIN(2, 5, 0x184, 0x5C8), + + MX35_PIN_RXD1 = _MXC_BUILD_GPIO_PIN(2, 6, 0x188, 0x5CC), + MX35_PIN_TXD1 = _MXC_BUILD_GPIO_PIN(2, 7, 0x18C, 0x5D0), + MX35_PIN_RTS1 = _MXC_BUILD_GPIO_PIN(2, 8, 0x190, 0x5D4), + MX35_PIN_CTS1 = _MXC_BUILD_GPIO_PIN(2, 9, 0x194, 0x5D8), + MX35_PIN_RXD2 = _MXC_BUILD_GPIO_PIN(2, 10, 0x198, 0x5DC), + MX35_PIN_TXD2 = _MXC_BUILD_GPIO_PIN(1, 11, 0x19C, 0x5E0), + MX35_PIN_RTS2 = _MXC_BUILD_GPIO_PIN(1, 12, 0x1A0, 0x5E4), + MX35_PIN_CTS2 = _MXC_BUILD_GPIO_PIN(1, 13, 0x1A4, 0x5E8), + + MX35_PIN_USBOTG_PWR = _MXC_BUILD_GPIO_PIN(2, 14, 0x1A8, 0x60C), + MX35_PIN_USBOTG_OC = _MXC_BUILD_GPIO_PIN(2, 15, 0x1AC, 0x610), + + MX35_PIN_LD0 = _MXC_BUILD_GPIO_PIN(1, 0, 0x1B0, 0x614), + MX35_PIN_LD1 = _MXC_BUILD_GPIO_PIN(1, 1, 0x1B4, 0x618), + MX35_PIN_LD2 = _MXC_BUILD_GPIO_PIN(1, 2, 0x1B8, 0x61C), + MX35_PIN_LD3 = _MXC_BUILD_GPIO_PIN(1, 3, 0x1BC, 0x620), + MX35_PIN_LD4 = _MXC_BUILD_GPIO_PIN(1, 4, 0x1C0, 0x624), + MX35_PIN_LD5 = _MXC_BUILD_GPIO_PIN(1, 5, 0x1C4, 0x628), + MX35_PIN_LD6 = _MXC_BUILD_GPIO_PIN(1, 6, 0x1C8, 0x62C), + MX35_PIN_LD7 = _MXC_BUILD_GPIO_PIN(1, 7, 0x1CC, 0x630), + MX35_PIN_LD8 = _MXC_BUILD_GPIO_PIN(1, 8, 0x1D0, 0x634), + MX35_PIN_LD9 = _MXC_BUILD_GPIO_PIN(1, 9, 0x1D4, 0x638), + MX35_PIN_LD10 = _MXC_BUILD_GPIO_PIN(1, 10, 0x1D8, 0x63C), + MX35_PIN_LD11 = _MXC_BUILD_GPIO_PIN(1, 11, 0x1DC, 0x640), + MX35_PIN_LD12 = _MXC_BUILD_GPIO_PIN(1, 12, 0x1E0, 0x644), + MX35_PIN_LD13 = _MXC_BUILD_GPIO_PIN(1, 13, 0x1E4, 0x648), + MX35_PIN_LD14 = _MXC_BUILD_GPIO_PIN(1, 14, 0x1E8, 0x64C), + MX35_PIN_LD15 = _MXC_BUILD_GPIO_PIN(1, 15, 0x1EC, 0x650), + MX35_PIN_LD16 = _MXC_BUILD_GPIO_PIN(1, 16, 0x1F0, 0x654), + MX35_PIN_LD17 = _MXC_BUILD_GPIO_PIN(1, 17, 0x1F4, 0x658), + MX35_PIN_LD18 = _MXC_BUILD_GPIO_PIN(2, 24, 0x1F8, 0x65C), + MX35_PIN_LD19 = _MXC_BUILD_GPIO_PIN(2, 25, 0x1FC, 0x660), + MX35_PIN_LD20 = _MXC_BUILD_GPIO_PIN(2, 26, 0x200, 0x664), + MX35_PIN_LD21 = _MXC_BUILD_GPIO_PIN(2, 27, 0x204, 0x668), + MX35_PIN_LD22 = _MXC_BUILD_GPIO_PIN(2, 28, 0x208, 0x66C), + MX35_PIN_LD23 = _MXC_BUILD_GPIO_PIN(2, 29, 0x20C, 0x670), + + MX35_PIN_D3_HSYNC = _MXC_BUILD_GPIO_PIN(2, 30, 0x210, 0x674), + MX35_PIN_D3_FPSHIFT = _MXC_BUILD_GPIO_PIN(2, 31, 0x214, 0x678), + MX35_PIN_D3_DRDY = _MXC_BUILD_GPIO_PIN(0, 0, 0x218, 0x67C), + MX35_PIN_CONTRAST = _MXC_BUILD_GPIO_PIN(0, 1, 0x21C, 0x680), + MX35_PIN_D3_VSYNC = _MXC_BUILD_GPIO_PIN(0, 2, 0x220, 0x684), + MX35_PIN_D3_REV = _MXC_BUILD_GPIO_PIN(0, 3, 0x224, 0x688), + MX35_PIN_D3_CLS = _MXC_BUILD_GPIO_PIN(0, 4, 0x228, 0x68C), + MX35_PIN_D3_SPL = _MXC_BUILD_GPIO_PIN(0, 5, 0x22C, 0x690), + + MX35_PIN_SD1_CMD = _MXC_BUILD_GPIO_PIN(0, 6, 0x230, 0x694), + MX35_PIN_SD1_CLK = _MXC_BUILD_GPIO_PIN(0, 7, 0x234, 0x698), + MX35_PIN_SD1_DATA0 = _MXC_BUILD_GPIO_PIN(0, 8, 0x238, 0x69C), + MX35_PIN_SD1_DATA1 = _MXC_BUILD_GPIO_PIN(0, 9, 0x23C, 0x6A0), + MX35_PIN_SD1_DATA2 = _MXC_BUILD_GPIO_PIN(0, 10, 0x240, 0x6A4), + MX35_PIN_SD1_DATA3 = _MXC_BUILD_GPIO_PIN(0, 11, 0x244, 0x6A8), + MX35_PIN_SD2_CMD = _MXC_BUILD_GPIO_PIN(1, 0, 0x248, 0x6AC), + MX35_PIN_SD2_CLK = _MXC_BUILD_GPIO_PIN(1, 1, 0x24C, 0x6B0), + MX35_PIN_SD2_DATA0 = _MXC_BUILD_GPIO_PIN(1, 2, 0x250, 0x6B4), + MX35_PIN_SD2_DATA1 = _MXC_BUILD_GPIO_PIN(1, 3, 0x254, 0x6B8), + MX35_PIN_SD2_DATA2 = _MXC_BUILD_GPIO_PIN(1, 4, 0x258, 0x6BC), + MX35_PIN_SD2_DATA3 = _MXC_BUILD_GPIO_PIN(1, 5, 0x25C, 0x6C0), + + MX35_PIN_ATA_CS0 = _MXC_BUILD_GPIO_PIN(1, 6, 0x260, 0x6C4), + MX35_PIN_ATA_CS1 = _MXC_BUILD_GPIO_PIN(1, 7, 0x264, 0x6C8), + MX35_PIN_ATA_DIOR = _MXC_BUILD_GPIO_PIN(1, 8, 0x268, 0x6CC), + MX35_PIN_ATA_DIOW = _MXC_BUILD_GPIO_PIN(1, 9, 0x26C, 0x6D0), + MX35_PIN_ATA_DMACK = _MXC_BUILD_GPIO_PIN(1, 10, 0x270, 0x6D4), + MX35_PIN_ATA_RESET_B = _MXC_BUILD_GPIO_PIN(1, 11, 0x274, 0x6D8), + MX35_PIN_ATA_IORDY = _MXC_BUILD_GPIO_PIN(1, 12, 0x278, 0x6DC), + MX35_PIN_ATA_DATA0 = _MXC_BUILD_GPIO_PIN(1, 13, 0x27C, 0x6E0), + MX35_PIN_ATA_DATA1 = _MXC_BUILD_GPIO_PIN(1, 14, 0x280, 0x6E4), + MX35_PIN_ATA_DATA2 = _MXC_BUILD_GPIO_PIN(1, 15, 0x284, 0x6E8), + MX35_PIN_ATA_DATA3 = _MXC_BUILD_GPIO_PIN(1, 16, 0x288, 0x6EC), + MX35_PIN_ATA_DATA4 = _MXC_BUILD_GPIO_PIN(1, 17, 0x28C, 0x6F0), + MX35_PIN_ATA_DATA5 = _MXC_BUILD_GPIO_PIN(1, 18, 0x290, 0x6F4), + MX35_PIN_ATA_DATA6 = _MXC_BUILD_GPIO_PIN(1, 19, 0x294, 0x6F8), + MX35_PIN_ATA_DATA7 = _MXC_BUILD_GPIO_PIN(1, 20, 0x298, 0x6FC), + MX35_PIN_ATA_DATA8 = _MXC_BUILD_GPIO_PIN(1, 21, 0x29C, 0x700), + MX35_PIN_ATA_DATA9 = _MXC_BUILD_GPIO_PIN(1, 22, 0x2A0, 0x704), + MX35_PIN_ATA_DATA10 = _MXC_BUILD_GPIO_PIN(1, 23, 0x2A4, 0x708), + MX35_PIN_ATA_DATA11 = _MXC_BUILD_GPIO_PIN(1, 24, 0x2A8, 0x70C), + MX35_PIN_ATA_DATA12 = _MXC_BUILD_GPIO_PIN(1, 25, 0x2AC, 0x710), + MX35_PIN_ATA_DATA13 = _MXC_BUILD_GPIO_PIN(1, 26, 0x2B0, 0x714), + MX35_PIN_ATA_DATA14 = _MXC_BUILD_GPIO_PIN(1, 27, 0x2B4, 0x718), + MX35_PIN_ATA_DATA15 = _MXC_BUILD_GPIO_PIN(1, 28, 0x2B8, 0x71C), + MX35_PIN_ATA_INTRQ = _MXC_BUILD_GPIO_PIN(1, 29, 0x2BC, 0x720), + MX35_PIN_ATA_BUFF_EN = _MXC_BUILD_GPIO_PIN(1, 30, 0x2C0, 0x724), + MX35_PIN_ATA_DMARQ = _MXC_BUILD_GPIO_PIN(1, 31, 0x2C4, 0x728), + MX35_PIN_ATA_DA0 = _MXC_BUILD_GPIO_PIN(2, 0, 0x2C8, 0x72C), + MX35_PIN_ATA_DA1 = _MXC_BUILD_GPIO_PIN(2, 1, 0x2CC, 0x730), + MX35_PIN_ATA_DA2 = _MXC_BUILD_GPIO_PIN(2, 2, 0x2D0, 0x734), + + MX35_PIN_MLB_CLK = _MXC_BUILD_GPIO_PIN(2, 3, 0x2D4, 0x738), + MX35_PIN_MLB_DAT = _MXC_BUILD_GPIO_PIN(2, 4, 0x2D8, 0x73C), + MX35_PIN_MLB_SIG = _MXC_BUILD_GPIO_PIN(2, 5, 0x2DC, 0x740), + + MX35_PIN_FEC_TX_CLK = _MXC_BUILD_GPIO_PIN(2, 6, 0x2E0, 0x744), + MX35_PIN_FEC_RX_CLK = _MXC_BUILD_GPIO_PIN(2, 7, 0x2E4, 0x748), + MX35_PIN_FEC_RX_DV = _MXC_BUILD_GPIO_PIN(2, 8, 0x2E8, 0x74C), + MX35_PIN_FEC_COL = _MXC_BUILD_GPIO_PIN(2, 9, 0x2EC, 0x750), + MX35_PIN_FEC_RDATA0 = _MXC_BUILD_GPIO_PIN(2, 10, 0x2F0, 0x754), + MX35_PIN_FEC_TDATA0 = _MXC_BUILD_GPIO_PIN(2, 11, 0x2F4, 0x758), + MX35_PIN_FEC_TX_EN = _MXC_BUILD_GPIO_PIN(2, 12, 0x2F8, 0x75C), + MX35_PIN_FEC_MDC = _MXC_BUILD_GPIO_PIN(2, 13, 0x2FC, 0x760), + MX35_PIN_FEC_MDIO = _MXC_BUILD_GPIO_PIN(2, 14, 0x300, 0x764), + MX35_PIN_FEC_TX_ERR = _MXC_BUILD_GPIO_PIN(2, 15, 0x304, 0x768), + MX35_PIN_FEC_RX_ERR = _MXC_BUILD_GPIO_PIN(2, 16, 0x308, 0x76C), + MX35_PIN_FEC_CRS = _MXC_BUILD_GPIO_PIN(2, 17, 0x30C, 0x770), + MX35_PIN_FEC_RDATA1 = _MXC_BUILD_GPIO_PIN(2, 18, 0x310, 0x774), + MX35_PIN_FEC_TDATA1 = _MXC_BUILD_GPIO_PIN(2, 19, 0x314, 0x778), + MX35_PIN_FEC_RDATA2 = _MXC_BUILD_GPIO_PIN(2, 20, 0x318, 0x77C), + MX35_PIN_FEC_TDATA2 = _MXC_BUILD_GPIO_PIN(2, 21, 0x31C, 0x780), + MX35_PIN_FEC_RDATA3 = _MXC_BUILD_GPIO_PIN(2, 22, 0x320, 0x784), + MX35_PIN_FEC_TDATA3 = _MXC_BUILD_GPIO_PIN(2, 23, 0x324, 0x788), +} iomux_pin_name_t; + +#endif +#endif diff --git a/include/asm-arm/arch-mx35/mxc_nand.h b/include/asm-arm/arch-mx35/mxc_nand.h new file mode 100644 index 0000000000..c672e54459 --- /dev/null +++ b/include/asm-arm/arch-mx35/mxc_nand.h @@ -0,0 +1,228 @@ +/* + * Copyright 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file mxc_nd2.h + * + * @brief This file contains the NAND Flash Controller register information. + * + * + * @ingroup NAND_MTD + */ + +#ifndef __MXC_NAND_H__ +#define __MXC_NAND_H__ + +#include + +#define IS_2K_PAGE_NAND ((mtd->writesize / info->num_of_intlv) \ + == NAND_PAGESIZE_2KB) +#define IS_4K_PAGE_NAND ((mtd->writesize / info->num_of_intlv) \ + == NAND_PAGESIZE_4KB) +#define IS_LARGE_PAGE_NAND ((mtd->writesize / info->num_of_intlv) > 512) + +#define GET_NAND_OOB_SIZE (mtd->oobsize / info->num_of_intlv) +#define GET_NAND_PAGE_SIZE (mtd->writesize / info->num_of_intlv) + +#define NAND_PAGESIZE_2KB 2048 +#define NAND_PAGESIZE_4KB 4096 + +/* + * main area for bad block marker is in the last data section + * the spare area for swapped bad block marker is the second + * byte of last spare section + */ +#define NAND_SECTIONS (GET_NAND_PAGE_SIZE >> 9) +#define NAND_OOB_PER_SECTION (((GET_NAND_OOB_SIZE / NAND_SECTIONS) >> 1) << 1) +#define NAND_CHUNKS (GET_NAND_PAGE_SIZE / (512 + NAND_OOB_PER_SECTION)) + +#define BAD_BLK_MARKER_MAIN_OFFS \ + (GET_NAND_PAGE_SIZE - NAND_CHUNKS * NAND_OOB_PER_SECTION) + +#define BAD_BLK_MARKER_SP_OFFS (NAND_CHUNKS * SPARE_LEN) + +#define BAD_BLK_MARKER_OOB_OFFS (NAND_CHUNKS * NAND_OOB_PER_SECTION) + +#define BAD_BLK_MARKER_MAIN \ + ((u32)MAIN_AREA0 + BAD_BLK_MARKER_MAIN_OFFS) + +#define BAD_BLK_MARKER_SP \ + ((u32)SPARE_AREA0 + BAD_BLK_MARKER_SP_OFFS) + + +/* + * Addresses for NFC registers + */ +#define NFC_REG_BASE (NFC_BASE_ADDR + 0x1000) +#define NFC_BUF_ADDR (NFC_REG_BASE + 0xE04) +#define NFC_FLASH_ADDR (NFC_REG_BASE + 0xE06) +#define NFC_FLASH_CMD (NFC_REG_BASE + 0xE08) +#define NFC_CONFIG (NFC_REG_BASE + 0xE0A) +#define NFC_ECC_STATUS_RESULT (NFC_REG_BASE + 0xE0C) +#define NFC_SPAS (NFC_REG_BASE + 0xE10) +#define NFC_WRPROT (NFC_REG_BASE + 0xE12) +#define NFC_UNLOCKSTART_BLKADDR (NFC_REG_BASE + 0xE20) +#define NFC_UNLOCKEND_BLKADDR (NFC_REG_BASE + 0xE22) +#define NFC_CONFIG1 (NFC_REG_BASE + 0xE1A) +#define NFC_CONFIG2 (NFC_REG_BASE + 0xE1C) + +/*! + * Addresses for NFC RAM BUFFER Main area 0 + */ +#define MAIN_AREA0 (u16 *)(NFC_BASE_ADDR + 0x000) +#define MAIN_AREA1 (u16 *)(NFC_BASE_ADDR + 0x200) + +/*! + * Addresses for NFC SPARE BUFFER Spare area 0 + */ +#define SPARE_AREA0 (u16 *)(NFC_BASE_ADDR + 0x1000) +#define SPARE_LEN 64 +#define SPARE_COUNT 8 +#define SPARE_SIZE (SPARE_LEN * SPARE_COUNT) + + +#define SPAS_SHIFT (0) +#define SPAS_MASK (0xFF00) +#define IS_4BIT_ECC \ + ((raw_read(REG_NFC_ECC_MODE) & NFC_ECC_MODE_4) >> 0) + +#define NFC_SET_SPAS(v) \ + raw_write(((raw_read(REG_NFC_SPAS) & SPAS_MASK) | \ + ((v<> 1); \ + } \ +} while (0) + + +#define WRITE_NFC_IP_REG(val, reg) \ + raw_write((raw_read(REG_NFC_OPS_STAT) & ~NFC_OPS_STAT), \ + REG_NFC_OPS_STAT) + +#define GET_NFC_ECC_STATUS() \ + raw_read(REG_NFC_ECC_STATUS_RESULT); + +/*! + * Set INT to 0, Set 1 to specific operation bit, rest to 0 in LAUNCH_NFC Register for + * Specific operation + */ +#define NFC_CMD 0x1 +#define NFC_ADDR 0x2 +#define NFC_INPUT 0x4 +#define NFC_OUTPUT 0x8 +#define NFC_ID 0x10 +#define NFC_STATUS 0x20 + +/* Bit Definitions */ +#define NFC_OPS_STAT (1 << 15) +#define NFC_SP_EN (1 << 2) +#define NFC_ECC_EN (1 << 3) +#define NFC_INT_MSK (1 << 4) +#define NFC_BIG (1 << 5) +#define NFC_RST (1 << 6) +#define NFC_CE (1 << 7) +#define NFC_ONE_CYCLE (1 << 8) +#define NFC_BLS_LOCKED 0 +#define NFC_BLS_LOCKED_DEFAULT 1 +#define NFC_BLS_UNLCOKED 2 +#define NFC_WPC_LOCK_TIGHT 1 +#define NFC_WPC_LOCK (1 << 1) +#define NFC_WPC_UNLOCK (1 << 2) +#define NFC_FLASH_ADDR_SHIFT 0 +#define NFC_UNLOCK_END_ADDR_SHIFT 0 + +#define NFC_ECC_MODE_4 (1<<0) +#define NFC_ECC_MODE_8 (~(1<<0)) +#define NFC_SPAS_16 8 +#define NFC_SPAS_64 32 +#define NFC_SPAS_128 64 +#define NFC_SPAS_218 109 + +/* NFC Register Mapping */ +#define REG_NFC_OPS_STAT NFC_CONFIG2 +#define REG_NFC_INTRRUPT NFC_CONFIG1 +#define REG_NFC_FLASH_ADDR NFC_FLASH_ADDR +#define REG_NFC_FLASH_CMD NFC_FLASH_CMD +#define REG_NFC_OPS NFC_CONFIG2 +#define REG_NFC_SET_RBA NFC_BUF_ADDR +#define REG_NFC_ECC_EN NFC_CONFIG1 +#define REG_NFC_ECC_STATUS_RESULT NFC_ECC_STATUS_RESULT +#define REG_NFC_CE NFC_CONFIG1 +#define REG_NFC_SP_EN NFC_CONFIG1 +#define REG_NFC_BLS NFC_CONFIG +#define REG_NFC_WPC NFC_WRPROT +#define REG_START_BLKADDR NFC_UNLOCKSTART_BLKADDR +#define REG_END_BLKADDR NFC_UNLOCKEND_BLKADDR +#define REG_NFC_RST NFC_CONFIG1 +#define REG_NFC_ECC_MODE NFC_CONFIG1 +#define REG_NFC_SPAS NFC_SPAS + + +/* NFC V1/V2 Specific MACRO functions definitions */ + +#define raw_write(v, a) __raw_writew(v, a) +#define raw_read(a) __raw_readw(a) + +#define NFC_SET_BLS(val) val + +#define UNLOCK_ADDR(start_addr, end_addr) \ +{ \ + raw_write(start_addr, REG_START_BLKADDR); \ + raw_write(end_addr, REG_END_BLKADDR); \ +} + +#define NFC_SET_NFC_ACTIVE_CS(val) +#define NFC_SET_WPC(val) val + +/* NULL Definitions */ +#define ACK_OPS +#define NFC_SET_RBA(val) raw_write(val, REG_NFC_SET_RBA); + +#define READ_PAGE() send_read_page(0) +#define PROG_PAGE() send_prog_page(0) +#define CHECK_NFC_RB 1 + +#endif /* __MXC_NAND_H__ */ diff --git a/include/asm-arm/arch-mx50/imx_spi_pmic.h b/include/asm-arm/arch-mx50/imx_spi_pmic.h new file mode 100644 index 0000000000..170c609472 --- /dev/null +++ b/include/asm-arm/arch-mx50/imx_spi_pmic.h @@ -0,0 +1,33 @@ +/* + * (C) Copyright 2008-2010 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _IMX_SPI_PMIC_H_ +#define _IMX_SPI_PMIC_H_ + +#include + +extern struct spi_slave *spi_pmic_probe(void); +extern void spi_pmic_free(struct spi_slave *slave); +extern u32 pmic_reg(struct spi_slave *slave, + u32 reg, u32 val, u32 write); + +#endif /* _IMX_SPI_PMIC_H_ */ diff --git a/include/asm-arm/arch-mx50/iomux.h b/include/asm-arm/arch-mx50/iomux.h new file mode 100644 index 0000000000..87e73eabaf --- /dev/null +++ b/include/asm-arm/arch-mx50/iomux.h @@ -0,0 +1,230 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef __MACH_MX50_IOMUX_H__ +#define __MACH_MX50_IOMUX_H__ + +#include +#include +#include +#include + +typedef unsigned int iomux_pin_name_t; + +/* various IOMUX output functions */ +typedef enum iomux_config { + IOMUX_CONFIG_ALT0, /*!< used as alternate function 0 */ + IOMUX_CONFIG_ALT1, /*!< used as alternate function 1 */ + IOMUX_CONFIG_ALT2, /*!< used as alternate function 2 */ + IOMUX_CONFIG_ALT3, /*!< used as alternate function 3 */ + IOMUX_CONFIG_ALT4, /*!< used as alternate function 4 */ + IOMUX_CONFIG_ALT5, /*!< used as alternate function 5 */ + IOMUX_CONFIG_ALT6, /*!< used as alternate function 6 */ + IOMUX_CONFIG_ALT7, /*!< used as alternate function 7 */ + IOMUX_CONFIG_GPIO, /*!< added to help user use GPIO mode */ + IOMUX_CONFIG_SION = 0x1 << 4, /*!< used as LOOPBACK:MUX SION bit */ +} iomux_pin_cfg_t; + +/* various IOMUX pad functions */ +typedef enum iomux_pad_config { + PAD_CTL_SRE_SLOW = 0x0 << 0, + PAD_CTL_SRE_FAST = 0x1 << 0, + PAD_CTL_DRV_LOW = 0x0 << 1, + PAD_CTL_DRV_MEDIUM = 0x1 << 1, + PAD_CTL_DRV_HIGH = 0x2 << 1, + PAD_CTL_DRV_MAX = 0x3 << 1, + PAD_CTL_ODE_OPENDRAIN_NONE = 0x0 << 3, + PAD_CTL_ODE_OPENDRAIN_ENABLE = 0x1 << 3, + PAD_CTL_100K_PD = 0x0 << 4, + PAD_CTL_47K_PU = 0x1 << 4, + PAD_CTL_100K_PU = 0x2 << 4, + PAD_CTL_22K_PU = 0x3 << 4, + PAD_CTL_PUE_KEEPER = 0x0 << 6, + PAD_CTL_PUE_PULL = 0x1 << 6, + PAD_CTL_PKE_NONE = 0x0 << 7, + PAD_CTL_PKE_ENABLE = 0x1 << 7, + PAD_CTL_HYS_NONE = 0x0 << 8, + PAD_CTL_HYS_ENABLE = 0x1 << 8, + PAD_CTL_DDR_INPUT_CMOS = 0x0 << 9, + PAD_CTL_DDR_INPUT_DDR = 0x1 << 9, + PAD_CTL_DRV_VOT_LOW = 0x0 << 13, + PAD_CTL_DRV_VOT_HIGH = 0x1 << 13, +} iomux_pad_config_t; + +/* various IOMUX input select register index */ +typedef enum iomux_input_select { + MUX_IN_AUDMUX_P4_INPUT_DA_AMX_SELECT_I = 0, + MUX_IN_AUDMUX_P4_INPUT_DB_AMX_SELECT_I, + MUX_IN_AUDMUX_P4_INPUT_RXCLK_AMX_SELECT_INPUT, + MUX_IN_AUDMUX_P4_INPUT_RXFS_AMX_SELECT_INPUT, + MUX_IN_AUDMUX_P4_INPUT_TXCLK_AMX_SELECT_INPUT, + MUX_IN_AUDMUX_P4_INPUT_TXFS_AMX_SELECT_INPUT, + MUX_IN_CCM_PLL1_BYPASS_CLK_SELECT_INPUT, + MUX_IN_CCM_PLL2_BYPASS_CLK_SELECT_INPUT, + MUX_IN_CCM_PLL3_BYPASS_CLK_SELECT_INPUT, + MUX_IN_CSPI_IPP_IND_DATAREADY_B_SELECT_INPUT, + MUX_IN_CSPI_IPP_IND_SS1_B_SELECT_INPUT, + MUX_IN_CSPI_IPP_IND_SS2_B_SELECT_INPUT, + MUX_IN_CSPI_IPP_IND_SS3_B_SELECT_INPUT, + MUX_IN_ELCDIF_LCDIF_BUSY_SELECT_INPUT, + MUX_IN_ELCDIF_LCDIF_RXDATA_0_SELECT_INPUT, + MUX_IN_ELCDIF_LCDIF_RXDATA_1_SELECT_INPUT, + MUX_IN_ELCDIF_LCDIF_RXDATA_2_SELECT_INPUT, + MUX_IN_ELCDIF_LCDIF_RXDATA_3_SELECT_INPUT, + MUX_IN_ELCDIF_LCDIF_RXDATA_4_SELECT_INPUT, + MUX_IN_ELCDIF_LCDIF_RXDATA_5_SELECT_INPUT, + MUX_IN_ELCDIF_LCDIF_RXDATA_6_SELECT_INPUT, + MUX_IN_ELCDIF_LCDIF_RXDATA_7_SELECT_INPUT, + MUX_IN_ELCDIF_LCDIF_RXDATA_8_SELECT_INPUT, + MUX_IN_ELCDIF_LCDIF_RXDATA_9_SELECT_INPUT, + MUX_IN_ELCDIF_LCDIF_RXDATA_10_SELECT_INPUT, + MUX_IN_ELCDIF_LCDIF_RXDATA_11_SELECT_INPUT, + MUX_IN_ELCDIF_LCDIF_RXDATA_12_SELECT_INPUT, + MUX_IN_ELCDIF_LCDIF_RXDATA_13_SELECT_INPUT, + MUX_IN_ELCDIF_LCDIF_RXDATA_14_SELECT_INPUT, + MUX_IN_ELCDIF_LCDIF_RXDATA_15_SELECT_INPUT, + MUX_IN_ELCDIF_VSYNC_I_SELECT_INPUT, + MUX_IN_ESDHC2_IPP_CARD_DET_SELECT_INPUT, + MUX_IN_ESDHC2_IPP_WP_ON_SELECT_INPUT, + MUX_IN_ESDHC4_IPP_CARD_CLK_IN_SELECT_INPUT, + MUX_IN_ESDHC4_IPP_CMD_IN_SELECT_INPUT, + MUX_IN_ESDHC4_IPP_DAT0_IN_SELECT_INPUT, + MUX_IN_ESDHC4_IPP_DAT1_IN_SELECT_INPUT, + MUX_IN_ESDHC4_IPP_DAT2_IN_SELECT_INPUT, + MUX_IN_ESDHC4_IPP_DAT3_IN_SELECT_INPUT, + MUX_IN_ESDHC4_IPP_DAT4_IN_SELECT_INPUT, + MUX_IN_ESDHC4_IPP_DAT5_IN_SELECT_INPUT, + MUX_IN_ESDHC4_IPP_DAT6_IN_SELECT_INPUT, + MUX_IN_ESDHC4_IPP_DAT7_IN_SELECT_INPUT, + MUX_IN_FEC_FEC_COL_SELECT_INPUT, + MUX_IN_FEC_FEC_MDI_SELECT_INPUT, + MUX_IN_FEC_FEC_RDATA_0_SELECT_INPUT, + MUX_IN_FEC_FEC_RDATA_1_SELECT_INPUT, + MUX_IN_FEC_FEC_RX_CLK_SELECT_INPUT, + MUX_IN_FEC_FEC_RX_DV_SELECT_INPUT, + MUX_IN_FEC_FEC_RX_ER_SELECT_INPUT, + MUX_IN_FEC_FEC_TX_CLK_SELECT_INPUT, + MUX_IN_KPP_IPP_IND_COL_4_SELECT_INPUT, + MUX_IN_KPP_IPP_IND_COL_5_SELECT_INPUT, + MUX_IN_KPP_IPP_IND_COL_6_SELECT_INPUT, + MUX_IN_KPP_IPP_IND_COL_7_SELECT_INPUT, + MUX_IN_KPP_IPP_IND_ROW_4_SELECT_INPUT, + MUX_IN_KPP_IPP_IND_ROW_5_SELECT_INPUT, + MUX_IN_KPP_IPP_IND_ROW_6_SELECT_INPUT, + MUX_IN_KPP_IPP_IND_ROW_7_SELECT_INPUT, + MUX_IN_RAWNAND_U_GPMI_INPUT_GPMI_DQS_IN_SELECT_INPUT, + MUX_IN_RAWNAND_U_GPMI_INPUT_GPMI_RDY0_IN_SELECT_INPUT, + MUX_IN_SDMA_EVENTS_14_SELECT_INPUT, + MUX_IN_SDMA_EVENTS_15_SELECT_INPUT, + MUX_IN_UART1_IPP_UART_RTS_B_SELECT_INPUT, + MUX_IN_UART1_IPP_UART_RXD_MUX_SELECT_INPUT, + MUX_IN_UART2_IPP_UART_RTS_B_SELECT_INPUT, + MUX_IN_UART2_IPP_UART_RXD_MUX_SELECT_INPUT, + MUX_IN_UART3_IPP_UART_RTS_B_SELECT_INPUT, + MUX_IN_UART3_IPP_UART_RXD_MUX_SELECT_INPUT, + MUX_IN_UART4_IPP_UART_RTS_B_SELECT_INPUT, + MUX_IN_UART4_IPP_UART_RXD_MUX_SELECT_INPUT, + MUX_IN_UART5_IPP_UART_RTS_B_SELECT_INPUT, + MUX_IN_UART5_IPP_UART_RXD_MUX_SELECT_INPUT, + MUX_IN_USBOH1_IPP_IND_OTG_OC_SELECT_INPUT, + MUX_IN_WEIMV2_IPP_IND_READ_DATA_0_SELECT_INPUT, + MUX_IN_WEIMV2_IPP_IND_READ_DATA_1_SELECT_INPUT, + MUX_IN_WEIMV2_IPP_IND_READ_DATA_2_SELECT_INPUT, + MUX_IN_WEIMV2_IPP_IND_READ_DATA_3_SELECT_INPUT, + MUX_IN_WEIMV2_IPP_IND_READ_DATA_4_SELECT_INPUT, + MUX_IN_WEIMV2_IPP_IND_READ_DATA_5_SELECT_INPUT, + MUX_IN_WEIMV2_IPP_IND_READ_DATA_6_SELECT_INPUT, + MUX_IN_WEIMV2_IPP_IND_READ_DATA_7_SELECT_INPUT, + MUX_IN_WEIMV2_IPP_IND_READ_DATA_8_SELECT_INPUT, + MUX_IN_WEIMV2_IPP_IND_READ_DATA_9_SELECT_INPUT, + MUX_IN_WEIMV2_IPP_IND_READ_DATA_10_SELECT_INPUT, + MUX_IN_WEIMV2_IPP_IND_READ_DATA_11_SELECT_INPUT, + MUX_IN_WEIMV2_IPP_IND_READ_DATA_12_SELECT_INPUT, + MUX_IN_WEIMV2_IPP_IND_READ_DATA_13_SELECT_INPUT, + MUX_IN_WEIMV2_IPP_IND_READ_DATA_14_SELECT_INPUT, + MUX_IN_WEIMV2_IPP_IND_READ_DATA_15_SELECT_INPUT, + MUX_INPUT_NUM_MUX, +} iomux_input_select_t; + +/* various IOMUX input functions */ +typedef enum iomux_input_config { + INPUT_CTL_PATH0 = 0x0, + INPUT_CTL_PATH1, + INPUT_CTL_PATH2, + INPUT_CTL_PATH3, + INPUT_CTL_PATH4, + INPUT_CTL_PATH5, + INPUT_CTL_PATH6, + INPUT_CTL_PATH7, +} iomux_input_config_t; + +struct mxc_iomux_pin_cfg { + iomux_pin_name_t pin; + u8 mux_mode; + u16 pad_cfg; + u8 in_select; + u8 in_mode; +}; + +/* + * Request ownership for an IO pin. This function has to be the first one + * being called before that pin is used. The caller has to check the + * return value to make sure it returns 0. + * + * @param pin a name defined by \b iomux_pin_name_t + * @param config config as defined in \b #iomux_pin_ocfg_t + * + * @return 0 if successful; Non-zero otherwise + */ +int mxc_request_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t config); + +/* + * Release ownership for an IO pin + * + * @param pin a name defined by \b iomux_pin_name_t + * @param config config as defined in \b #iomux_pin_ocfg_t + */ +void mxc_free_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t config); + +/* + * This function configures the pad value for a IOMUX pin. + * + * @param pin a pin number as defined in \b #iomux_pin_name_t + * @param config the ORed value of elements defined in + * \b #iomux_pad_config_t + */ +void mxc_iomux_set_pad(iomux_pin_name_t pin, u32 config); + +/* + * This function gets the current pad value for a IOMUX pin. + * + * @param pin a pin number as defined in \b #iomux_pin_name_t + * @return current pad value + */ +unsigned int mxc_iomux_get_pad(iomux_pin_name_t pin); + +/* + * This function configures input path. + * + * @param input index of input select register as defined in + * \b #iomux_input_select_t + * @param config the binary value of elements defined in \b #iomux_input_config_t + */ +void mxc_iomux_set_input(iomux_input_select_t input, u32 config); + +#endif /* __MACH_MX50_IOMUX_H__ */ diff --git a/include/asm-arm/arch-mx50/mmu.h b/include/asm-arm/arch-mx50/mmu.h new file mode 100644 index 0000000000..5fa2fc060c --- /dev/null +++ b/include/asm-arm/arch-mx50/mmu.h @@ -0,0 +1,174 @@ +/* + * Copyright 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#ifndef __ARM_ARCH_MMU_H +#define __ARM_ARCH_MMU_H + +#include + +/* + * Translation Table Base Bit Masks + */ +#define ARM_TRANSLATION_TABLE_MASK 0xFFFFC000 + +/* + * Domain Access Control Bit Masks + */ +#define ARM_ACCESS_TYPE_NO_ACCESS(domain_num) (0x0 << (domain_num)*2) +#define ARM_ACCESS_TYPE_CLIENT(domain_num) (0x1 << (domain_num)*2) +#define ARM_ACCESS_TYPE_MANAGER(domain_num) (0x3 << (domain_num)*2) + +struct ARM_MMU_FIRST_LEVEL_FAULT { + unsigned int id:2; + unsigned int sbz:30; +}; + +#define ARM_MMU_FIRST_LEVEL_FAULT_ID 0x0 + +struct ARM_MMU_FIRST_LEVEL_PAGE_TABLE { + unsigned int id:2; + unsigned int imp:2; + unsigned int domain:4; + unsigned int sbz:1; + unsigned int base_address:23; +}; + +#define ARM_MMU_FIRST_LEVEL_PAGE_TABLE_ID 0x1 + +struct ARM_MMU_FIRST_LEVEL_SECTION { + unsigned int id:2; + unsigned int b:1; + unsigned int c:1; + unsigned int imp:1; + unsigned int domain:4; + unsigned int sbz0:1; + unsigned int ap:2; + unsigned int sbz1:8; + unsigned int base_address:12; +}; + +#define ARM_MMU_FIRST_LEVEL_SECTION_ID 0x2 + +struct ARM_MMU_FIRST_LEVEL_RESERVED { + unsigned int id:2; + unsigned int sbz:30; +}; + +#define ARM_MMU_FIRST_LEVEL_RESERVED_ID 0x3 + +#define ARM_MMU_FIRST_LEVEL_DESCRIPTOR_ADDRESS(ttb_base, table_index) \ + (unsigned long *)((unsigned long)(ttb_base) + ((table_index) << 2)) + +#define ARM_FIRST_LEVEL_PAGE_TABLE_SIZE 0x4000 + +#define ARM_MMU_SECTION(ttb_base, actual_base, virtual_base, \ + cacheable, bufferable, perm) \ + { \ + register union ARM_MMU_FIRST_LEVEL_DESCRIPTOR desc; \ + desc.word = 0; \ + desc.section.id = ARM_MMU_FIRST_LEVEL_SECTION_ID; \ + desc.section.domain = 0; \ + desc.section.c = (cacheable); \ + desc.section.b = (bufferable); \ + desc.section.ap = (perm); \ + desc.section.base_address = (actual_base); \ + *ARM_MMU_FIRST_LEVEL_DESCRIPTOR_ADDRESS(ttb_base, (virtual_base)) \ + = desc.word; \ + } + +#define X_ARM_MMU_SECTION(abase, vbase, size, cache, buff, access) \ + { \ + int i; int j = abase; int k = vbase; \ + for (i = size; i > 0 ; i--, j++, k++) \ + ARM_MMU_SECTION(ttb_base, j, k, cache, buff, access); \ + } + +union ARM_MMU_FIRST_LEVEL_DESCRIPTOR { + unsigned long word; + struct ARM_MMU_FIRST_LEVEL_FAULT fault; + struct ARM_MMU_FIRST_LEVEL_PAGE_TABLE page_table; + struct ARM_MMU_FIRST_LEVEL_SECTION section; + struct ARM_MMU_FIRST_LEVEL_RESERVED reserved; +}; + +#define ARM_UNCACHEABLE 0 +#define ARM_CACHEABLE 1 +#define ARM_UNBUFFERABLE 0 +#define ARM_BUFFERABLE 1 + +#define ARM_ACCESS_PERM_NONE_NONE 0 +#define ARM_ACCESS_PERM_RO_NONE 0 +#define ARM_ACCESS_PERM_RO_RO 0 +#define ARM_ACCESS_PERM_RW_NONE 1 +#define ARM_ACCESS_PERM_RW_RO 2 +#define ARM_ACCESS_PERM_RW_RW 3 + +/* + * Initialization for the Domain Access Control Register + */ +#define ARM_ACCESS_DACR_DEFAULT ( \ + ARM_ACCESS_TYPE_MANAGER(0) | \ + ARM_ACCESS_TYPE_NO_ACCESS(1) | \ + ARM_ACCESS_TYPE_NO_ACCESS(2) | \ + ARM_ACCESS_TYPE_NO_ACCESS(3) | \ + ARM_ACCESS_TYPE_NO_ACCESS(4) | \ + ARM_ACCESS_TYPE_NO_ACCESS(5) | \ + ARM_ACCESS_TYPE_NO_ACCESS(6) | \ + ARM_ACCESS_TYPE_NO_ACCESS(7) | \ + ARM_ACCESS_TYPE_NO_ACCESS(8) | \ + ARM_ACCESS_TYPE_NO_ACCESS(9) | \ + ARM_ACCESS_TYPE_NO_ACCESS(10) | \ + ARM_ACCESS_TYPE_NO_ACCESS(11) | \ + ARM_ACCESS_TYPE_NO_ACCESS(12) | \ + ARM_ACCESS_TYPE_NO_ACCESS(13) | \ + ARM_ACCESS_TYPE_NO_ACCESS(14) | \ + ARM_ACCESS_TYPE_NO_ACCESS(15)) + +/* + * Translate the virtual address of ram space to physical address + * It is dependent on the implementation of mmu_init + */ +inline void *iomem_to_phys(unsigned long virt) +{ + if (virt >= 0xB0000000) + return (void *)((virt - 0xB0000000) + PHYS_SDRAM_1); + + return (void *)virt; +} + +/* + * remap the physical address of ram space to uncacheable virtual address space + * It is dependent on the implementation of hal_mmu_init + */ +void *__ioremap(unsigned long offset, size_t size, unsigned long flags) +{ + if (1 == flags) { + if (offset >= PHYS_SDRAM_1 && + offset < (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE)) + return (void *)(offset - PHYS_SDRAM_1) + 0xB0000000; + else + return NULL; + } else + return (void *)offset; +} + +/* + * Remap the physical address of ram space to uncacheable virtual address space + * It is dependent on the implementation of hal_mmu_init + */ +void __iounmap(void *addr) +{ + return; +} + +#endif diff --git a/include/asm-arm/arch-mx50/mx50.h b/include/asm-arm/arch-mx50/mx50.h new file mode 100644 index 0000000000..23952525b4 --- /dev/null +++ b/include/asm-arm/arch-mx50/mx50.h @@ -0,0 +1,331 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef __ASM_ARCH_MXC_MX50_H__ +#define __ASM_ARCH_MXC_MX50_H__ + +#define __REG(x) (*((volatile u32 *)(x))) +#define __REG16(x) (*((volatile u16 *)(x))) +#define __REG8(x) (*((volatile u8 *)(x))) + + /* + * IRAM + */ +#define IRAM_BASE_ADDR 0xF8000000 /* internal ram */ +#define IRAM_PARTITIONS 16 +#define IRAM_SIZE (IRAM_PARTITIONS*SZ_8K) /* 128KB */ + +#define TZIC_BASE_ADDR 0x0FFFC000 +#define DATABAHN_BASE_ADDR 0x14000000 + +#define DEBUG_BASE_ADDR 0x40000000 +#define ETB_BASE_ADDR (DEBUG_BASE_ADDR + 0x00001000) +#define ETM_BASE_ADDR (DEBUG_BASE_ADDR + 0x00002000) +#define TPIU_BASE_ADDR (DEBUG_BASE_ADDR + 0x00003000) +#define CTI0_BASE_ADDR (DEBUG_BASE_ADDR + 0x00004000) +#define CTI1_BASE_ADDR (DEBUG_BASE_ADDR + 0x00005000) +#define CTI2_BASE_ADDR (DEBUG_BASE_ADDR + 0x00006000) +#define CTI3_BASE_ADDR (DEBUG_BASE_ADDR + 0x00007000) +#define CORTEX_DBG_BASE_ADDR (DEBUG_BASE_ADDR + 0x00008000) +#define OCOTP_CTRL_BASE_ADDR (DEBUG_BASE_ADDR + 0x01002000) +#define EPDC_BASE_ADDR (DEBUG_BASE_ADDR + 0x01010000) + +/* + * SPBA global module enabled #0 + */ +#define SPBA0_BASE_ADDR 0x50000000 + +#define MMC_SDHC1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00004000) +#define MMC_SDHC2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00008000) +#define UART3_BASE_ADDR (SPBA0_BASE_ADDR + 0x0000C000) +#define CSPI1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00010000) +#define SSI2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00014000) +#define MMC_SDHC3_BASE_ADDR (SPBA0_BASE_ADDR + 0x00020000) +#define MMC_SDHC4_BASE_ADDR (SPBA0_BASE_ADDR + 0x00024000) +#define SPBA_CTRL_BASE_ADDR (SPBA0_BASE_ADDR + 0x0003C000) + +/* + * defines for SPBA modules + */ +#define SPBA_SDHC1 0x04 +#define SPBA_SDHC2 0x08 +#define SPBA_UART3 0x0C +#define SPBA_CSPI1 0x10 +#define SPBA_SSI2 0x14 +#define SPBA_ESAI 0x18 +#define SPBA_SDHC3 0x20 +#define SPBA_SDHC4 0x24 +#define SPBA_SPDIF 0x28 +#define SPBA_ASRC 0x2C +#define SPBA_ATA 0x30 +#define SPBA_CTRL 0x3C + +/* + * AIPS 1 + */ +#define AIPS1_BASE_ADDR 0x53F00000 + +#define OTG_BASE_ADDR (AIPS1_BASE_ADDR + 0x00080000) +#define GPIO1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00084000) +#define GPIO2_BASE_ADDR (AIPS1_BASE_ADDR + 0x00088000) +#define GPIO3_BASE_ADDR (AIPS1_BASE_ADDR + 0x0008C000) +#define GPIO4_BASE_ADDR (AIPS1_BASE_ADDR + 0x00090000) +#define KPP_BASE_ADDR (AIPS1_BASE_ADDR + 0x00094000) +#define WDOG1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00098000) +#define GPT1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A0000) +#define SRTC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A4000) +#define IOMUXC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A8000) +#define EPIT1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000AC000) +#define PWM1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B4000) +#define PWM2_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B8000) +#define UART1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000BC000) +#define UART2_BASE_ADDR (AIPS1_BASE_ADDR + 0x000C0000) +#define USBOH1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000C4000) +#define SRC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000D0000) +#define CCM_BASE_ADDR (AIPS1_BASE_ADDR + 0x000D4000) +#define GPC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000D8000) +#define GPIO5_BASE_ADDR (AIPS1_BASE_ADDR + 0x000DC000) +#define GPIO6_BASE_ADDR (AIPS1_BASE_ADDR + 0x000E0000) +#define GPIO7_BASE_ADDR (AIPS1_BASE_ADDR + 0x000E4000) +#define ATA_BASE_ADDR (AIPS1_BASE_ADDR + 0x000E8000) +#define I2C3_BASE_ADDR (AIPS1_BASE_ADDR + 0x000EC000) +#define UART4_BASE_ADDR (AIPS1_BASE_ADDR + 0x000F0000) +#define MSHC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000F4000) +#define RNGB_BASE_ADDR (AIPS1_BASE_ADDR + 0x000F8000) + +/* + * AIPS 2 + */ +#define AIPS2_BASE_ADDR 0x63F00000 + +#define PLL1_BASE_ADDR (AIPS2_BASE_ADDR + 0x00080000) +#define PLL2_BASE_ADDR (AIPS2_BASE_ADDR + 0x00084000) +#define PLL3_BASE_ADDR (AIPS2_BASE_ADDR + 0x00088000) +#define UART5_BASE_ADDR (AIPS2_BASE_ADDR + 0x00090000) +#define AHBMAX_BASE_ADDR (AIPS2_BASE_ADDR + 0x00094000) +#define ARM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A0000) +#define OWIRE_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A4000) +#define CSPI2_BASE_ADDR (AIPS2_BASE_ADDR + 0x000AC000) +#define SDMA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000B0000) +#define ROMCP_BASE_ADDR (AIPS2_BASE_ADDR + 0x000B8000) +#define CSPI3_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C0000) +#define I2C2_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C4000) +#define I2C1_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C8000) +#define SSI1_BASE_ADDR (AIPS2_BASE_ADDR + 0x000CC000) +#define AUDMUX_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D0000) +#define M4IF_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D8000) +#define ESDCTL_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D9000) +#define WEIM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DA000) +#define NFC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DB000) +#define EMI_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DBF00) +#define FEC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000EC000) + +/* + * Some of i.MX50 SoC registers are associated with four addresses + * used for different operations - read/write, set, clear and toggle bits. + * + * Some of registers do not implement such feature and, thus, should be + * accessed/manipulated via single address in common way. + */ +#define REG_RD(base, reg) \ + (*(volatile unsigned int *)((base) + (reg))) +#define REG_WR(base, reg, value) \ + ((*(volatile unsigned int *)((base) + (reg))) = (value)) +#define REG_SET(base, reg, value) \ + ((*(volatile unsigned int *)((base) + (reg ## _SET))) = (value)) +#define REG_CLR(base, reg, value) \ + ((*(volatile unsigned int *)((base) + (reg ## _CLR))) = (value)) +#define REG_TOG(base, reg, value) \ + ((*(volatile unsigned int *)((base) + (reg ## _TOG))) = (value)) + +#define REG_RD_ADDR(addr) \ + (*(volatile unsigned int *)((addr))) +#define REG_WR_ADDR(addr, value) \ + ((*(volatile unsigned int *)((addr))) = (value)) +#define REG_SET_ADDR(addr, value) \ + ((*(volatile unsigned int *)((addr) + 0x4)) = (value)) +#define REG_CLR_ADDR(addr, value) \ + ((*(volatile unsigned int *)((addr) + 0x8)) = (value)) +#define REG_TOG_ADDR(addr, value) \ + ((*(volatile unsigned int *)((addr) + 0xc)) = (value)) + +/* + * Memory regions and CS + */ +#define CSD0_BASE_ADDR 0x70000000 +#define CSD1_BASE_ADDR 0xB0000000 + +/* gpio and gpio based interrupt handling */ +#define GPIO_DR 0x00 +#define GPIO_GDIR 0x04 +#define GPIO_PSR 0x08 +#define GPIO_ICR1 0x0C +#define GPIO_ICR2 0x10 +#define GPIO_IMR 0x14 +#define GPIO_ISR 0x18 +#define GPIO_INT_LOW_LEV 0x0 +#define GPIO_INT_HIGH_LEV 0x1 +#define GPIO_INT_RISE_EDGE 0x2 +#define GPIO_INT_FALL_EDGE 0x3 +#define GPIO_INT_NONE 0x4 + +#define CLKCTL_CCR 0x00 +#define CLKCTL_CCDR 0x04 +#define CLKCTL_CSR 0x08 +#define CLKCTL_CCSR 0x0C +#define CLKCTL_CACRR 0x10 +#define CLKCTL_CBCDR 0x14 +#define CLKCTL_CBCMR 0x18 +#define CLKCTL_CSCMR1 0x1C +#define CLKCTL_CSCMR2 0x20 +#define CLKCTL_CSCDR1 0x24 +#define CLKCTL_CS1CDR 0x28 +#define CLKCTL_CS2CDR 0x2C +#define CLKCTL_CDCDR 0x30 +#define CLKCTL_CHSCDR 0x34 +#define CLKCTL_CSCDR2 0x38 +#define CLKCTL_CSCDR3 0x3C +#define CLKCTL_CSCDR4 0x40 +#define CLKCTL_CWDR 0x44 +#define CLKCTL_CDHIPR 0x48 +#define CLKCTL_CDCR 0x4C +#define CLKCTL_CTOR 0x50 +#define CLKCTL_CLPCR 0x54 +#define CLKCTL_CISR 0x58 +#define CLKCTL_CIMR 0x5C +#define CLKCTL_CCOSR 0x60 +#define CLKCTL_CGPR 0x64 +#define CLKCTL_CCGR0 0x68 +#define CLKCTL_CCGR1 0x6C +#define CLKCTL_CCGR2 0x70 +#define CLKCTL_CCGR3 0x74 +#define CLKCTL_CCGR4 0x78 +#define CLKCTL_CCGR5 0x7C +#define CLKCTL_CCGR6 0x80 +#define CLKCTL_CCGR7 0x84 +#define CLKCTL_CMEOR 0x88 + +#define CLKCTL_CSR2 0x8C +#define CLKCTL_CLKSEQ_BYPASS 0x90 +#define CLKCTL_CLK_SYS 0x94 +#define CLKCTL_CLK_DDR 0x98 + +#define CHIP_REV_1_0 0x10 +#define PLATFORM_ICGC 0x14 + +/* Assuming 24MHz input clock with doubler ON */ +/* MFI PDF */ +#define DP_OP_850 ((8 << 4) + ((1 - 1) << 0)) +#define DP_MFD_850 (48 - 1) +#define DP_MFN_850 41 + +#define DP_OP_800 ((8 << 4) + ((1 - 1) << 0)) +#define DP_MFD_800 (3 - 1) +#define DP_MFN_800 1 + +#define DP_OP_700 ((7 << 4) + ((1 - 1) << 0)) +#define DP_MFD_700 (24 - 1) +#define DP_MFN_700 7 + +#define DP_OP_600 ((6 << 4) + ((1 - 1) << 0)) +#define DP_MFD_600 (4 - 1) +#define DP_MFN_600 1 + +#define DP_OP_665 ((6 << 4) + ((1 - 1) << 0)) +#define DP_MFD_665 (96 - 1) +#define DP_MFN_665 89 + +#define DP_OP_532 ((5 << 4) + ((1 - 1) << 0)) +#define DP_MFD_532 (24 - 1) +#define DP_MFN_532 13 + +#define DP_OP_400 ((8 << 4) + ((2 - 1) << 0)) +#define DP_MFD_400 (3 - 1) +#define DP_MFN_400 1 + +#define DP_OP_216 ((6 << 4) + ((3 - 1) << 0)) +#define DP_MFD_216 (4 - 1) +#define DP_MFN_216 3 + +#define PLL_DP_CTL 0x00 +#define PLL_DP_CONFIG 0x04 +#define PLL_DP_OP 0x08 +#define PLL_DP_MFD 0x0C +#define PLL_DP_MFN 0x10 +#define PLL_DP_MFNMINUS 0x14 +#define PLL_DP_MFNPLUS 0x18 +#define PLL_DP_HFS_OP 0x1C +#define PLL_DP_HFS_MFD 0x20 +#define PLL_DP_HFS_MFN 0x24 +#define PLL_DP_TOGC 0x28 +#define PLL_DP_DESTAT 0x2C + +#ifndef __ASSEMBLER__ + +enum boot_device { + WEIM_NOR_BOOT, + ONE_NAND_BOOT, + PATA_BOOT, + SATA_BOOT, + I2C_BOOT, + SPI_NOR_BOOT, + SD_BOOT, + MMC_BOOT, + NAND_BOOT, + UNKNOWN_BOOT +}; + +enum mxc_clock { + MXC_ARM_CLK = 0, + MXC_PER_CLK, + MXC_AHB_CLK, + MXC_IPG_CLK, + MXC_IPG_PERCLK, + MXC_UART_CLK, + MXC_CSPI_CLK, + MXC_AXI_A_CLK, + MXC_AXI_B_CLK, + MXC_EMI_SLOW_CLK, + MXC_DDR_CLK, + MXC_ESDHC_CLK, + MXC_ESDHC2_CLK, + MXC_ESDHC3_CLK, + MXC_ESDHC4_CLK, +}; + +enum mxc_peri_clocks { + MXC_UART1_BAUD, + MXC_UART2_BAUD, + MXC_UART3_BAUD, + MXC_SSI1_BAUD, + MXC_SSI2_BAUD, + MXC_CSI_BAUD, + MXC_MSTICK1_CLK, + MXC_MSTICK2_CLK, + MXC_SPI1_CLK, + MXC_SPI2_CLK, +}; + +extern unsigned int mxc_get_clock(enum mxc_clock clk); +extern unsigned int get_board_rev(void); +extern int is_soc_rev(int rev); +extern enum boot_device get_boot_device(void); + +#endif /* __ASSEMBLER__*/ + +#endif /* __ASM_ARCH_MXC_MX50_H__ */ diff --git a/include/asm-arm/arch-mx50/mx50_pins.h b/include/asm-arm/arch-mx50/mx50_pins.h new file mode 100644 index 0000000000..05935c907a --- /dev/null +++ b/include/asm-arm/arch-mx50/mx50_pins.h @@ -0,0 +1,285 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ +#ifndef __ASM_ARCH_MXC_MX50_PINS_H__ +#define __ASM_ARCH_MXC_MX50_PINS_H__ + +#ifndef __ASSEMBLY__ + +/* + * In order to identify pins more effectively, each mux-controlled pin's + * enumerated value is constructed in the following way: + * + * ------------------------------------------------------------------- + * 31-29 | 28 - 24 | 23 - 21 | 20 - 10| 9 - 0 + * ------------------------------------------------------------------- + * IO_P | IO_I | GPIO_I | PAD_I | MUX_I + * ------------------------------------------------------------------- + * + * Bit 0 to 9 contains MUX_I used to identify the register + * offset (0-based. base is IOMUX_module_base) defined in the Section + * "sw_pad_ctl & sw_mux_ctl details" of the IC Spec. The + * similar field definitions are used for the pad control register. + * For example, the MX50_PIN_GPIO_19 is defined in the enumeration: + * ( (0x20 - MUX_I_START) << MUX_I)|( (0x348 - PAD_I_START) << PAD_I) + * It means the mux control register is at register offset 0x20. The pad control + * register offset is: 0x348 and also occupy the least significant bits + * within the register. + */ + +/* + * Starting bit position within each entry of \b iomux_pins to represent the + * MUX control register offset + */ +#define MUX_I 0 +/* + * Starting bit position within each entry of \b iomux_pins to represent the + * PAD control register offset + */ +#define PAD_I 10 +/* + * Starting bit position within each entry of \b iomux_pins to represent which + * mux mode is for GPIO (0-based) + */ +#define GPIO_I 21 + +#define MUX_IO_P 29 +#define MUX_IO_I 24 + +#define NON_GPIO_PORT 0x7 +#define PIN_TO_MUX_MASK ((1 << (PAD_I - MUX_I)) - 1) +#define PIN_TO_PAD_MASK ((1 << (GPIO_I - PAD_I)) - 1) +#define PIN_TO_ALT_GPIO_MASK ((1 << (MUX_IO_I - GPIO_I)) - 1) + +#define NON_MUX_I PIN_TO_MUX_MASK +#define NON_PAD_I PIN_TO_PAD_MASK +#define MUX_I_START 0x0020 +#define PAD_I_START 0x2CC +#define INPUT_CTL_START 0x6C4 +#define MUX_I_END (PAD_I_START - 4) + +#define _MXC_BUILD_PIN(gp, gi, ga, mi, pi) \ + (((gp) << MUX_IO_P) | ((gi) << MUX_IO_I) | \ + ((mi) << MUX_I) | \ + ((pi - PAD_I_START) << PAD_I) | \ + ((ga) << GPIO_I)) + +#define _MXC_BUILD_GPIO_PIN(gp, gi, ga, mi, pi) \ + _MXC_BUILD_PIN(gp, gi, ga, mi, pi) + +#define _MXC_BUILD_NON_GPIO_PIN(mi, pi) \ + _MXC_BUILD_PIN(NON_GPIO_PORT, 0, 0, mi, pi) + +#define PIN_TO_IOMUX_MUX(pin) ((pin >> MUX_I) & PIN_TO_MUX_MASK) +#define PIN_TO_IOMUX_PAD(pin) ((pin >> PAD_I) & PIN_TO_PAD_MASK) +#define PIN_TO_ALT_GPIO(pin) ((pin >> GPIO_I) & PIN_TO_ALT_GPIO_MASK) +#define PIN_TO_IOMUX_INDEX(pin) (PIN_TO_IOMUX_MUX(pin) >> 2) + +/* + * This enumeration is constructed based on the Section + * "sw_pad_ctl & sw_mux_ctl details" of the MX50 IC Spec. Each enumerated + * value is constructed based on the rules described above. + */ +enum iomux_pins { + MX50_PIN_KEY_COL0 = _MXC_BUILD_GPIO_PIN(3, 0, 1, 0x20, 0x2CC), + MX50_PIN_KEY_ROW0 = _MXC_BUILD_GPIO_PIN(3, 1, 1, 0x24, 0x2D0), + MX50_PIN_KEY_COL1 = _MXC_BUILD_GPIO_PIN(3, 2, 1, 0x28, 0x2D4), + MX50_PIN_KEY_ROW1 = _MXC_BUILD_GPIO_PIN(3, 3, 1, 0x2C, 0x2D8), + MX50_PIN_KEY_COL2 = _MXC_BUILD_GPIO_PIN(3, 4, 1, 0x30, 0x2DC), + MX50_PIN_KEY_ROW2 = _MXC_BUILD_GPIO_PIN(3, 5, 1, 0x34, 0x2E0), + MX50_PIN_KEY_COL3 = _MXC_BUILD_GPIO_PIN(3, 6, 1, 0x38, 0x2E4), + MX50_PIN_KEY_ROW3 = _MXC_BUILD_GPIO_PIN(3, 7, 1, 0x3C, 0x2E8), + MX50_PIN_I2C1_SCL = _MXC_BUILD_GPIO_PIN(5, 18, 1, 0x40, 0x2EC), + MX50_PIN_I2C1_SDA = _MXC_BUILD_GPIO_PIN(5, 19, 1, 0x44, 0x2F0), + MX50_PIN_I2C2_SCL = _MXC_BUILD_GPIO_PIN(5, 20, 1, 0x48, 0x2F4), + MX50_PIN_I2C2_SDA = _MXC_BUILD_GPIO_PIN(5, 21, 1, 0x4C, 0x2F8), + MX50_PIN_I2C3_SCL = _MXC_BUILD_GPIO_PIN(5, 22, 1, 0x50, 0x2FC), + MX50_PIN_I2C3_SDA = _MXC_BUILD_GPIO_PIN(5, 23, 1, 0x54, 0x300), + MX50_PIN_PWM1 = _MXC_BUILD_GPIO_PIN(5, 24, 1, 0x58, 0x304), + MX50_PIN_PWM2 = _MXC_BUILD_GPIO_PIN(5, 25, 1, 0x5C, 0x308), + MX50_PIN_OWIRE = _MXC_BUILD_GPIO_PIN(5, 26, 1, 0x60, 0x30C), + MX50_PIN_EPITO = _MXC_BUILD_GPIO_PIN(5, 27, 1, 0x64, 0x310), + MX50_PIN_WDOG = _MXC_BUILD_GPIO_PIN(5, 28, 1, 0x68, 0x314), + MX50_PIN_SSI_TXFS = _MXC_BUILD_GPIO_PIN(5, 0, 1, 0x6C, 0x318), + MX50_PIN_SSI_TXC = _MXC_BUILD_GPIO_PIN(5, 1, 1, 0x70, 0x31C), + MX50_PIN_SSI_TXD = _MXC_BUILD_GPIO_PIN(5, 2, 1, 0x74, 0x320), + MX50_PIN_SSI_RXD = _MXC_BUILD_GPIO_PIN(5, 3, 1, 0x78, 0x324), + MX50_PIN_SSI_RXFS = _MXC_BUILD_GPIO_PIN(5, 4, 1, 0x7C, 0x328), + MX50_PIN_SSI_RXC = _MXC_BUILD_GPIO_PIN(5, 5, 1, 0x80, 0x32C), + MX50_PIN_UART1_TXD = _MXC_BUILD_GPIO_PIN(5, 6, 1, 0x84, 0x330), + MX50_PIN_UART1_RXD = _MXC_BUILD_GPIO_PIN(5, 7, 1, 0x88, 0x334), + MX50_PIN_UART1_CTS = _MXC_BUILD_GPIO_PIN(5, 8, 1, 0x8C, 0x338), + MX50_PIN_UART1_RTS = _MXC_BUILD_GPIO_PIN(5, 9, 1, 0x90, 0x33C), + MX50_PIN_UART2_TXD = _MXC_BUILD_GPIO_PIN(5, 10, 1, 0x94, 0x340), + MX50_PIN_UART2_RXD = _MXC_BUILD_GPIO_PIN(5, 11, 1, 0x98, 0x344), + MX50_PIN_UART2_CTS = _MXC_BUILD_GPIO_PIN(5, 12, 1, 0x9C, 0x348), + MX50_PIN_UART2_RTS = _MXC_BUILD_GPIO_PIN(5, 13, 1, 0xA0, 0x34C), + MX50_PIN_UART3_TXD = _MXC_BUILD_GPIO_PIN(5, 14, 1, 0xA4, 0x350), + MX50_PIN_UART3_RXD = _MXC_BUILD_GPIO_PIN(5, 15, 1, 0xA8, 0x354), + MX50_PIN_UART4_TXD = _MXC_BUILD_GPIO_PIN(5, 16, 1, 0xAC, 0x358), + MX50_PIN_UART4_RXD = _MXC_BUILD_GPIO_PIN(5, 17, 1, 0xB0, 0x35C), + MX50_PIN_CSPI_SCLK = _MXC_BUILD_GPIO_PIN(3, 8, 1, 0xB4, 0x360), + MX50_PIN_CSPI_MOSI = _MXC_BUILD_GPIO_PIN(3, 9, 1, 0xB8, 0x364), + MX50_PIN_CSPI_MISO = _MXC_BUILD_GPIO_PIN(3, 10, 1, 0xBC, 0x368), + MX50_PIN_CSPI_SS0 = _MXC_BUILD_GPIO_PIN(3, 11, 1, 0xC0, 0x36C), + MX50_PIN_ECSPI1_SCLK = _MXC_BUILD_GPIO_PIN(3, 12, 1, 0xC4, 0x370), + MX50_PIN_ECSPI1_MOSI = _MXC_BUILD_GPIO_PIN(3, 13, 1, 0xC8, 0x374), + MX50_PIN_ECSPI1_MISO = _MXC_BUILD_GPIO_PIN(3, 14, 1, 0xCC, 0x378), + MX50_PIN_ECSPI1_SS0 = _MXC_BUILD_GPIO_PIN(3, 15, 1, 0xD0, 0x37C), + MX50_PIN_ECSPI2_SCLK = _MXC_BUILD_GPIO_PIN(3, 16, 1, 0xD4, 0x380), + MX50_PIN_ECSPI2_MOSI = _MXC_BUILD_GPIO_PIN(3, 17, 1, 0xD8, 0x384), + MX50_PIN_ECSPI2_MISO = _MXC_BUILD_GPIO_PIN(3, 18, 1, 0xDC, 0x388), + MX50_PIN_ECSPI2_SS0 = _MXC_BUILD_GPIO_PIN(3, 19, 1, 0xE0, 0x38C), + MX50_PIN_SD1_CLK = _MXC_BUILD_GPIO_PIN(4, 0, 1, 0xE4, 0x390), + MX50_PIN_SD1_CMD = _MXC_BUILD_GPIO_PIN(4, 1, 1, 0xE8, 0x394), + MX50_PIN_SD1_D0 = _MXC_BUILD_GPIO_PIN(4, 2, 1, 0xEC, 0x398), + MX50_PIN_SD1_D1 = _MXC_BUILD_GPIO_PIN(4, 3, 1, 0xF0, 0x39C), + MX50_PIN_SD1_D2 = _MXC_BUILD_GPIO_PIN(4, 4, 1, 0xF4, 0x3A0), + MX50_PIN_SD1_D3 = _MXC_BUILD_GPIO_PIN(4, 5, 1, 0xF8, 0x3A4), + MX50_PIN_SD2_CLK = _MXC_BUILD_GPIO_PIN(4, 6, 1, 0xFC, 0x3A8), + MX50_PIN_SD2_CMD = _MXC_BUILD_GPIO_PIN(4, 7, 1, 0x100, 0x3AC), + MX50_PIN_SD2_D0 = _MXC_BUILD_GPIO_PIN(4, 8, 1, 0x104, 0x3B0), + MX50_PIN_SD2_D1 = _MXC_BUILD_GPIO_PIN(4, 9, 1, 0x108, 0x3B4), + MX50_PIN_SD2_D2 = _MXC_BUILD_GPIO_PIN(4, 10, 1, 0x10C, 0x3B8), + MX50_PIN_SD2_D3 = _MXC_BUILD_GPIO_PIN(4, 11, 1, 0x110, 0x3BC), + MX50_PIN_SD2_D4 = _MXC_BUILD_GPIO_PIN(4, 12, 1, 0x114, 0x3C0), + MX50_PIN_SD2_D5 = _MXC_BUILD_GPIO_PIN(4, 13, 1, 0x118, 0x3C4), + MX50_PIN_SD2_D6 = _MXC_BUILD_GPIO_PIN(4, 14, 1, 0x11C, 0x3C8), + MX50_PIN_SD2_D7 = _MXC_BUILD_GPIO_PIN(4, 15, 1, 0x120, 0x3CC), + MX50_PIN_SD2_WP = _MXC_BUILD_GPIO_PIN(4, 16, 1, 0x124, 0x3D0), + MX50_PIN_SD2_CD = _MXC_BUILD_GPIO_PIN(4, 17, 1, 0x128, 0x3D4), + MX50_PIN_PMIC_ON_REQ = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x3D8), + MX50_PIN_PMIC_STBY_REQ = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x3DC), + MX50_PIN_PMIC_PORT_B = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x3E0), + MX50_PIN_PMIC_BOOT_MODE1 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x3E4), + MX50_PIN_PMIC_RESET_IN_B = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x3E8), + MX50_PIN_PMIC_BOOT_MODE0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x3EC), + MX50_PIN_PMIC_TEST_MODE = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x3F0), + MX50_PIN_PMIC_JTAG_TMS = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x3F4), + MX50_PIN_PMIC_JTAG_MOD = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x3F8), + MX50_PIN_PMIC_JTAG_TRSTB = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x3FC), + MX50_PIN_PMIC_JTAG_TDI = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x400), + MX50_PIN_PMIC_JTAG_TCK = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x404), + MX50_PIN_PMIC_JTAG_TDO = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x408), + MX50_PIN_DISP_D0 = _MXC_BUILD_GPIO_PIN(1, 0, 1, 0x12C, 0x40C), + MX50_PIN_DISP_D1 = _MXC_BUILD_GPIO_PIN(1, 1, 1, 0x130, 0x410), + MX50_PIN_DISP_D2 = _MXC_BUILD_GPIO_PIN(1, 2, 1, 0x134, 0x414), + MX50_PIN_DISP_D3 = _MXC_BUILD_GPIO_PIN(1, 3, 1, 0x138, 0x418), + MX50_PIN_DISP_D4 = _MXC_BUILD_GPIO_PIN(1, 4, 1, 0x13C, 0x41C), + MX50_PIN_DISP_D5 = _MXC_BUILD_GPIO_PIN(1, 5, 1, 0x140, 0x420), + MX50_PIN_DISP_D6 = _MXC_BUILD_GPIO_PIN(1, 6, 1, 0x144, 0x424), + MX50_PIN_DISP_D7 = _MXC_BUILD_GPIO_PIN(1, 7, 1, 0x148, 0x428), + MX50_PIN_DISP_WR = _MXC_BUILD_GPIO_PIN(1, 16, 1, 0x14C, 0x42C), + MX50_PIN_DISP_RD = _MXC_BUILD_GPIO_PIN(1, 19, 1, 0x150, 0x430), + MX50_PIN_DISP_RS = _MXC_BUILD_GPIO_PIN(1, 17, 1, 0x154, 0x434), + MX50_PIN_DISP_CS = _MXC_BUILD_GPIO_PIN(1, 21, 1, 0x158, 0x438), + MX50_PIN_DISP_BUSY = _MXC_BUILD_GPIO_PIN(1, 18, 1, 0x15C, 0x43C), + MX50_PIN_DISP_RESET = _MXC_BUILD_GPIO_PIN(1, 20, 1, 0x160, 0x440), + MX50_PIN_SD3_CMD = _MXC_BUILD_GPIO_PIN(4, 18, 1, 0x164, 0x444), + MX50_PIN_SD3_CLK = _MXC_BUILD_GPIO_PIN(4, 19, 1, 0x168, 0x448), + MX50_PIN_SD3_D0 = _MXC_BUILD_GPIO_PIN(4, 20, 1, 0x16C, 0x44C), + MX50_PIN_SD3_D1 = _MXC_BUILD_GPIO_PIN(4, 21, 1, 0x170, 0x450), + MX50_PIN_SD3_D2 = _MXC_BUILD_GPIO_PIN(4, 22, 1, 0x174, 0x454), + MX50_PIN_SD3_D3 = _MXC_BUILD_GPIO_PIN(4, 23, 1, 0x178, 0x458), + MX50_PIN_SD3_D4 = _MXC_BUILD_GPIO_PIN(4, 24, 1, 0x17C, 0x45C), + MX50_PIN_SD3_D5 = _MXC_BUILD_GPIO_PIN(4, 25, 1, 0x180, 0x460), + MX50_PIN_SD3_D6 = _MXC_BUILD_GPIO_PIN(4, 26, 1, 0x184, 0x464), + MX50_PIN_SD3_D7 = _MXC_BUILD_GPIO_PIN(4, 27, 1, 0x188, 0x468), + MX50_PIN_SD3_WP = _MXC_BUILD_GPIO_PIN(4, 28, 1, 0x18C, 0x46C), + MX50_PIN_DISP_D8 = _MXC_BUILD_GPIO_PIN(1, 8, 1, 0x190, 0x470), + MX50_PIN_DISP_D9 = _MXC_BUILD_GPIO_PIN(1, 9, 1, 0x194, 0x474), + MX50_PIN_DISP_D10 = _MXC_BUILD_GPIO_PIN(1, 10, 1, 0x198, 0x478), + MX50_PIN_DISP_D11 = _MXC_BUILD_GPIO_PIN(1, 11, 1, 0x19C, 0x47C), + MX50_PIN_DISP_D12 = _MXC_BUILD_GPIO_PIN(1, 12, 1, 0x1A0, 0x480), + MX50_PIN_DISP_D13 = _MXC_BUILD_GPIO_PIN(1, 13, 1, 0x1A4, 0x484), + MX50_PIN_DISP_D14 = _MXC_BUILD_GPIO_PIN(1, 14, 1, 0x1A8, 0x488), + MX50_PIN_DISP_D15 = _MXC_BUILD_GPIO_PIN(1, 15, 1, 0x1AC, 0x48C), + MX50_PIN_EPDC_D0 = _MXC_BUILD_GPIO_PIN(2, 0, 1, 0x1B0, 0x54C), + MX50_PIN_EPDC_D1 = _MXC_BUILD_GPIO_PIN(2, 1, 1, 0x1B4, 0x550), + MX50_PIN_EPDC_D2 = _MXC_BUILD_GPIO_PIN(2, 2, 1, 0x1B8, 0x554), + MX50_PIN_EPDC_D3 = _MXC_BUILD_GPIO_PIN(2, 3, 1, 0x1BC, 0x558), + MX50_PIN_EPDC_D4 = _MXC_BUILD_GPIO_PIN(2, 4, 1, 0x1C0, 0x55C), + MX50_PIN_EPDC_D5 = _MXC_BUILD_GPIO_PIN(2, 5, 1, 0x1C4, 0x560), + MX50_PIN_EPDC_D6 = _MXC_BUILD_GPIO_PIN(2, 6, 1, 0x1C8, 0x564), + MX50_PIN_EPDC_D7 = _MXC_BUILD_GPIO_PIN(2, 7, 1, 0x1CC, 0x568), + MX50_PIN_EPDC_D8 = _MXC_BUILD_GPIO_PIN(2, 8, 1, 0x1D0, 0x56C), + MX50_PIN_EPDC_D9 = _MXC_BUILD_GPIO_PIN(2, 9, 1, 0x1D4, 0x570), + MX50_PIN_EPDC_D10 = _MXC_BUILD_GPIO_PIN(2, 10, 1, 0x1D8, 0x574), + MX50_PIN_EPDC_D11 = _MXC_BUILD_GPIO_PIN(2, 11, 1, 0x1DC, 0x578), + MX50_PIN_EPDC_D12 = _MXC_BUILD_GPIO_PIN(2, 12, 1, 0x1E0, 0x57C), + MX50_PIN_EPDC_D13 = _MXC_BUILD_GPIO_PIN(2, 13, 1, 0x1E4, 0x580), + MX50_PIN_EPDC_D14 = _MXC_BUILD_GPIO_PIN(2, 14, 1, 0x1E8, 0x584), + MX50_PIN_EPDC_D15 = _MXC_BUILD_GPIO_PIN(2, 15, 1, 0x1EC, 0x588), + MX50_PIN_EPDC_GDCLK = _MXC_BUILD_GPIO_PIN(2, 16, 1, 0x1F0, 0x58C), + MX50_PIN_EPDC_GDSP = _MXC_BUILD_GPIO_PIN(2, 17, 1, 0x1F4, 0x590), + MX50_PIN_EPDC_GDOE = _MXC_BUILD_GPIO_PIN(2, 18, 1, 0x1F8, 0x594), + MX50_PIN_EPDC_GDRL = _MXC_BUILD_GPIO_PIN(2, 19, 1, 0x1FC, 0x598), + MX50_PIN_EPDC_SDCLK = _MXC_BUILD_GPIO_PIN(2, 20, 1, 0x200, 0x59C), + MX50_PIN_EPDC_SDOEZ = _MXC_BUILD_GPIO_PIN(2, 21, 1, 0x204, 0x5A0), + MX50_PIN_EPDC_SDOED = _MXC_BUILD_GPIO_PIN(2, 22, 1, 0x208, 0x5A4), + MX50_PIN_EPDC_SDOE = _MXC_BUILD_GPIO_PIN(2, 23, 1, 0x20C, 0x5A8), + MX50_PIN_EPDC_SDLE = _MXC_BUILD_GPIO_PIN(2, 24, 1, 0x210, 0x5AC), + MX50_PIN_EPDC_SDCLKN = _MXC_BUILD_GPIO_PIN(2, 25, 1, 0x214, 0x5B0), + MX50_PIN_EPDC_SDSHR = _MXC_BUILD_GPIO_PIN(2, 26, 1, 0x218, 0x5B4), + MX50_PIN_EPDC_PWRCOM = _MXC_BUILD_GPIO_PIN(2, 27, 1, 0x21C, 0x5B8), + MX50_PIN_EPDC_PWRSTAT = _MXC_BUILD_GPIO_PIN(2, 28, 1, 0x220, 0x5BC), + MX50_PIN_EPDC_PWRCTRL0 = _MXC_BUILD_GPIO_PIN(2, 29, 1, 0x224, 0x5C0), + MX50_PIN_EPDC_PWRCTRL1 = _MXC_BUILD_GPIO_PIN(2, 30, 1, 0x228, 0x5C4), + MX50_PIN_EPDC_PWRCTRL2 = _MXC_BUILD_GPIO_PIN(2, 31, 1, 0x22C, 0x5C8), + MX50_PIN_EPDC_PWRCTRL3 = _MXC_BUILD_GPIO_PIN(3, 20, 1, 0x230, 0x5CC), + MX50_PIN_EPDC_VCOM0 = _MXC_BUILD_GPIO_PIN(3, 21, 1, 0x234, 0x5D0), + MX50_PIN_EPDC_VCOM1 = _MXC_BUILD_GPIO_PIN(3, 22, 1, 0x238, 0x5D4), + MX50_PIN_EPDC_BDR0 = _MXC_BUILD_GPIO_PIN(3, 23, 1, 0x23C, 0x5D8), + MX50_PIN_EPDC_BDR1 = _MXC_BUILD_GPIO_PIN(3, 24, 1, 0x240, 0x5DC), + MX50_PIN_EPDC_SDCE0 = _MXC_BUILD_GPIO_PIN(3, 25, 1, 0x244, 0x5E0), + MX50_PIN_EPDC_SDCE1 = _MXC_BUILD_GPIO_PIN(3, 26, 1, 0x248, 0x5E4), + MX50_PIN_EPDC_SDCE2 = _MXC_BUILD_GPIO_PIN(3, 27, 1, 0x24C, 0x5E8), + MX50_PIN_EPDC_SDCE3 = _MXC_BUILD_GPIO_PIN(3, 28, 1, 0x250, 0x5EC), + MX50_PIN_EPDC_SDCE4 = _MXC_BUILD_GPIO_PIN(3, 29, 1, 0x254, 0x5F0), + MX50_PIN_EPDC_SDCE5 = _MXC_BUILD_GPIO_PIN(3, 30, 1, 0x258, 0x5F4), + MX50_PIN_EIM_DA0 = _MXC_BUILD_GPIO_PIN(0, 0, 1, 0x25C, 0x5F8), + MX50_PIN_EIM_DA1 = _MXC_BUILD_GPIO_PIN(0, 1, 1, 0x260, 0x5FC), + MX50_PIN_EIM_DA2 = _MXC_BUILD_GPIO_PIN(0, 2, 1, 0x264, 0x600), + MX50_PIN_EIM_DA3 = _MXC_BUILD_GPIO_PIN(0, 3, 1, 0x268, 0x604), + MX50_PIN_EIM_DA4 = _MXC_BUILD_GPIO_PIN(0, 4, 1, 0x26C, 0x608), + MX50_PIN_EIM_DA5 = _MXC_BUILD_GPIO_PIN(0, 5, 1, 0x270, 0x60C), + MX50_PIN_EIM_DA6 = _MXC_BUILD_GPIO_PIN(0, 6, 1, 0x274, 0x610), + MX50_PIN_EIM_DA7 = _MXC_BUILD_GPIO_PIN(0, 7, 1, 0x278, 0x614), + MX50_PIN_EIM_DA8 = _MXC_BUILD_GPIO_PIN(0, 8, 1, 0x27C, 0x618), + MX50_PIN_EIM_DA9 = _MXC_BUILD_GPIO_PIN(0, 9, 1, 0x280, 0x61C), + MX50_PIN_EIM_DA10 = _MXC_BUILD_GPIO_PIN(0, 10, 1, 0x284, 0x620), + MX50_PIN_EIM_DA11 = _MXC_BUILD_GPIO_PIN(0, 11, 1, 0x288, 0x624), + MX50_PIN_EIM_DA12 = _MXC_BUILD_GPIO_PIN(0, 12, 1, 0x28C, 0x628), + MX50_PIN_EIM_DA13 = _MXC_BUILD_GPIO_PIN(0, 13, 1, 0x290, 0x62C), + MX50_PIN_EIM_DA14 = _MXC_BUILD_GPIO_PIN(0, 14, 1, 0x294, 0x630), + MX50_PIN_EIM_DA15 = _MXC_BUILD_GPIO_PIN(0, 15, 1, 0x298, 0x634), + MX50_PIN_EIM_CS2 = _MXC_BUILD_GPIO_PIN(0, 16, 1, 0x29C, 0x638), + MX50_PIN_EIM_CS1 = _MXC_BUILD_GPIO_PIN(0, 17, 1, 0x2A0, 0x63C), + MX50_PIN_EIM_CS0 = _MXC_BUILD_GPIO_PIN(0, 18, 1, 0x2A4, 0x640), + MX50_PIN_EIM_EB0 = _MXC_BUILD_GPIO_PIN(0, 19, 1, 0x2A8, 0x644), + MX50_PIN_EIM_EB1 = _MXC_BUILD_GPIO_PIN(0, 20, 1, 0x2AC, 0x648), + MX50_PIN_EIM_WAIT = _MXC_BUILD_GPIO_PIN(0, 21, 1, 0x2B0, 0x64C), + MX50_PIN_EIM_BCLK = _MXC_BUILD_GPIO_PIN(0, 22, 1, 0x2B4, 0x650), + MX50_PIN_EIM_RDY = _MXC_BUILD_GPIO_PIN(0, 23, 1, 0x2B8, 0x654), + MX50_PIN_EIM_OE = _MXC_BUILD_GPIO_PIN(0, 24, 1, 0x2BC, 0x658), + MX50_PIN_EIM_RW = _MXC_BUILD_GPIO_PIN(0, 25, 1, 0x2C0, 0x65C), + MX50_PIN_EIM_LBA = _MXC_BUILD_GPIO_PIN(0, 26, 1, 0x2C4, 0x660), + MX50_PIN_EIM_CRE = _MXC_BUILD_GPIO_PIN(0, 27, 1, 0x2C8, 0x664), +}; + +#endif /* __ASSEMBLY__ */ +#endif /* __ASM_ARCH_MXC_MX50_PINS_H__ */ diff --git a/include/asm-arm/arch-mx51/imx_spi_pmic.h b/include/asm-arm/arch-mx51/imx_spi_pmic.h new file mode 100644 index 0000000000..21e6cd21ad --- /dev/null +++ b/include/asm-arm/arch-mx51/imx_spi_pmic.h @@ -0,0 +1,33 @@ +/* + * (C) Copyright 2008-2009 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _IMX_SPI_PMIC_H_ +#define _IMX_SPI_PMIC_H_ + +#include + +extern struct spi_slave *spi_pmic_probe(void); +extern void spi_pmic_free(struct spi_slave *slave); +extern u32 pmic_reg(struct spi_slave *slave, + u32 reg, u32 val, u32 write); + +#endif /* _IMX_SPI_PMIC_H_ */ diff --git a/include/asm-arm/arch-mx51/iomux.h b/include/asm-arm/arch-mx51/iomux.h new file mode 100644 index 0000000000..fa0298421f --- /dev/null +++ b/include/asm-arm/arch-mx51/iomux.h @@ -0,0 +1,240 @@ +/* + * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#ifndef __MACH_MX51_IOMUX_H__ +#define __MACH_MX51_IOMUX_H__ + +#include +#include +#include +#include + +/*! + * @file iomux.h + * + * @brief I/O Muxing control definitions and functions + * + * @ingroup GPIO_MX51 + */ + +typedef unsigned int iomux_pin_name_t; + +/*! + * various IOMUX output functions + */ +typedef enum iomux_config { + IOMUX_CONFIG_ALT0, /*!< used as alternate function 0 */ + IOMUX_CONFIG_ALT1, /*!< used as alternate function 1 */ + IOMUX_CONFIG_ALT2, /*!< used as alternate function 2 */ + IOMUX_CONFIG_ALT3, /*!< used as alternate function 3 */ + IOMUX_CONFIG_ALT4, /*!< used as alternate function 4 */ + IOMUX_CONFIG_ALT5, /*!< used as alternate function 5 */ + IOMUX_CONFIG_ALT6, /*!< used as alternate function 6 */ + IOMUX_CONFIG_ALT7, /*!< used as alternate function 7 */ + IOMUX_CONFIG_GPIO, /*!< added to help user use GPIO mode */ + IOMUX_CONFIG_SION = 0x1 << 4, /*!< used as LOOPBACK:MUX SION bit */ +} iomux_pin_cfg_t; + +/*! + * various IOMUX pad functions + */ +typedef enum iomux_pad_config { + PAD_CTL_SRE_SLOW = 0x0 << 0, + PAD_CTL_SRE_FAST = 0x1 << 0, + PAD_CTL_DRV_LOW = 0x0 << 1, + PAD_CTL_DRV_MEDIUM = 0x1 << 1, + PAD_CTL_DRV_HIGH = 0x2 << 1, + PAD_CTL_DRV_MAX = 0x3 << 1, + PAD_CTL_ODE_OPENDRAIN_NONE = 0x0 << 3, + PAD_CTL_ODE_OPENDRAIN_ENABLE = 0x1 << 3, + PAD_CTL_100K_PD = 0x0 << 4, + PAD_CTL_47K_PU = 0x1 << 4, + PAD_CTL_100K_PU = 0x2 << 4, + PAD_CTL_22K_PU = 0x3 << 4, + PAD_CTL_PUE_KEEPER = 0x0 << 6, + PAD_CTL_PUE_PULL = 0x1 << 6, + PAD_CTL_PKE_NONE = 0x0 << 7, + PAD_CTL_PKE_ENABLE = 0x1 << 7, + PAD_CTL_HYS_NONE = 0x0 << 8, + PAD_CTL_HYS_ENABLE = 0x1 << 8, + PAD_CTL_DDR_INPUT_CMOS = 0x0 << 9, + PAD_CTL_DDR_INPUT_DDR = 0x1 << 9, + PAD_CTL_DRV_VOT_LOW = 0x0 << 13, + PAD_CTL_DRV_VOT_HIGH = 0x1 << 13, +} iomux_pad_config_t; + +/*! + * various IOMUX input select register index + */ +typedef enum iomux_input_select { + MUX_IN_AUDMUX_P4_INPUT_DA_AMX_SELECT_I = 0, + MUX_IN_AUDMUX_P4_INPUT_DB_AMX_SELECT_I, + MUX_IN_AUDMUX_P4_INPUT_TXCLK_AMX_SELECT_INPUT, + MUX_IN_AUDMUX_P4_INPUT_TXFS_AMX_SELECT_INPUT, + MUX_IN_AUDMUX_P5_INPUT_DA_AMX_SELECT_INPUT, + MUX_IN_AUDMUX_P5_INPUT_DB_AMX_SELECT_INPUT, + MUX_IN_AUDMUX_P5_INPUT_RXCLK_AMX_SELECT_INPUT, + MUX_IN_AUDMUX_P5_INPUT_RXFS_AMX_SELECT, + MUX_IN_AUDMUX_P5_INPUT_TXCLK_AMX_SELECT_INPUT, + MUX_IN_AUDMUX_P5_INPUT_TXFS_AMX_SELECT_INPUT, + MUX_IN_AUDMUX_P6_INPUT_DA_AMX_SELECT_INPUT, + MUX_IN_AUDMUX_P6_INPUT_DB_AMX_SELECT_INPUT, + MUX_IN_AUDMUX_P6_INPUT_RXCLK_AMX_SELECT_INPUT, + MUX_IN_AUDMUX_P6_INPUT_RXFS_AMX_SELECT_INPUT, + MUX_IN_AUDMUX_P6_INPUT_TXCLK_AMX_SELECT_INPUT, + MUX_IN_AUDMUX_P6_INPUT_TXFS_AMX_SELECT_INPUT, + MUX_IN_CCM_IPP_DI_CLK_SELECT_INPUT, + /* TO2 */ + MUX_IN_CCM_IPP_DI1_CLK_SELECT_INPUT, + MUX_IN_CCM_PLL1_BYPASS_CLK_SELECT_INPUT, + MUX_IN_CCM_PLL2_BYPASS_CLK_SELECT_INPUT, + MUX_IN_CSPI_IPP_CSPI_CLK_IN_SELECT_INPUT, + MUX_IN_CSPI_IPP_IND_MISO_SELECT_INPUT, + MUX_IN_CSPI_IPP_IND_MOSI_SELECT_INPUT, + MUX_IN_CSPI_IPP_IND_SS_B_1_SELECT_INPUT, + MUX_IN_CSPI_IPP_IND_SS_B_2_SELECT_INPUT, + MUX_IN_CSPI_IPP_IND_SS_B_3_SELECT_INPUT, + MUX_IN_DPLLIP1_L1T_TOG_EN_SELECT_INPUT, + /* TO2 */ + MUX_IN_ECSPI2_IPP_IND_SS_B_1_SELECT_INPUT, + MUX_IN_ECSPI2_IPP_IND_SS_B_3_SELECT_INPUT, + MUX_IN_EMI_IPP_IND_RDY_INT_SELECT_INPUT, + MUX_IN_ESDHC3_IPP_DAT0_IN_SELECT_INPUT, + MUX_IN_ESDHC3_IPP_DAT1_IN_SELECT_INPUT, + MUX_IN_ESDHC3_IPP_DAT2_IN_SELECT_INPUT, + MUX_IN_ESDHC3_IPP_DAT3_IN_SELECT_INPUT, + MUX_IN_FEC_FEC_COL_SELECT_INPUT, + MUX_IN_FEC_FEC_CRS_SELECT_INPUT, + MUX_IN_FEC_FEC_MDI_SELECT_INPUT, + MUX_IN_FEC_FEC_RDATA_0_SELECT_INPUT, + MUX_IN_FEC_FEC_RDATA_1_SELECT_INPUT, + MUX_IN_FEC_FEC_RDATA_2_SELECT_INPUT, + MUX_IN_FEC_FEC_RDATA_3_SELECT_INPUT, + MUX_IN_FEC_FEC_RX_CLK_SELECT_INPUT, + MUX_IN_FEC_FEC_RX_DV_SELECT_INPUT, + MUX_IN_FEC_FEC_RX_ER_SELECT_INPUT, + MUX_IN_FEC_FEC_TX_CLK_SELECT_INPUT, + MUX_IN_GPIO3_IPP_IND_G_IN_1_SELECT_INPUT, + MUX_IN_GPIO3_IPP_IND_G_IN_2_SELECT_INPUT, + MUX_IN_GPIO3_IPP_IND_G_IN_3_SELECT_INPUT, + MUX_IN_GPIO3_IPP_IND_G_IN_4_SELECT_INPUT, + MUX_IN_GPIO3_IPP_IND_G_IN_5_SELECT_INPUT, + MUX_IN_GPIO3_IPP_IND_G_IN_6_SELECT_INPUT, + MUX_IN_GPIO3_IPP_IND_G_IN_7_SELECT_INPUT, + MUX_IN_GPIO3_IPP_IND_G_IN_8_SELECT_INPUT, + /* TO2 */ + MUX_IN_GPIO3_IPP_IND_G_IN_12_SELECT_INPUT, + MUX_IN_HSC_MIPI_MIX_IPP_IND_SENS1_DATA_EN_SELECT_INPUT, + MUX_IN_HSC_MIPI_MIX_IPP_IND_SENS2_DATA_EN_SELECT_INPUT, + /* TO2 */ + MUX_IN_HSC_MIPI_MIX_PAR_VSYNC_SELECT_INPUT, + /* TO2 */ + MUX_IN_HSC_MIPI_MIX_PAR_DI_WAIT_SELECT_INPUT, + MUX_IN_HSC_MIPI_MIX_PAR_SISG_TRIG_SELECT_INPUT, + MUX_IN_I2C1_IPP_SCL_IN_SELECT_INPUT, + MUX_IN_I2C1_IPP_SDA_IN_SELECT_INPUT, + MUX_IN_I2C2_IPP_SCL_IN_SELECT_INPUT, + MUX_IN_I2C2_IPP_SDA_IN_SELECT_INPUT, + + MUX_IN_IPU_IPP_DI_0_IND_DISPB_SD_D_SELECT_INPUT, + + MUX_IN_IPU_IPP_DI_1_IND_DISPB_SD_D_SELECT_INPUT, + + MUX_IN_KPP_IPP_IND_COL_6_SELECT_INPUT, + MUX_IN_KPP_IPP_IND_COL_7_SELECT_INPUT, + MUX_IN_KPP_IPP_IND_ROW_4_SELECT_INPUT, + MUX_IN_KPP_IPP_IND_ROW_5_SELECT_INPUT, + MUX_IN_KPP_IPP_IND_ROW_6_SELECT_INPUT, + MUX_IN_KPP_IPP_IND_ROW_7_SELECT_INPUT, + MUX_IN_UART1_IPP_UART_RTS_B_SELECT_INPUT, + MUX_IN_UART1_IPP_UART_RXD_MUX_SELECT_INPUT, + MUX_IN_UART2_IPP_UART_RTS_B_SELECT_INPUT, + MUX_IN_UART2_IPP_UART_RXD_MUX_SELECT_INPUT, + MUX_IN_UART3_IPP_UART_RTS_B_SELECT_INPUT, + MUX_IN_UART3_IPP_UART_RXD_MUX_SELECT_INPUT, + MUX_IN_USBOH3_IPP_IND_UH3_CLK_SELECT_INPUT, + MUX_IN_USBOH3_IPP_IND_UH3_DATA_0_SELECT_INPUT, + MUX_IN_USBOH3_IPP_IND_UH3_DATA_1_SELECT_INPUT, + MUX_IN_USBOH3_IPP_IND_UH3_DATA_2_SELECT_INPUT, + MUX_IN_USBOH3_IPP_IND_UH3_DATA_3_SELECT_INPUT, + MUX_IN_USBOH3_IPP_IND_UH3_DATA_4_SELECT_INPUT, + MUX_IN_USBOH3_IPP_IND_UH3_DATA_5_SELECT_INPUT, + MUX_IN_USBOH3_IPP_IND_UH3_DATA_6_SELECT_INPUT, + MUX_IN_USBOH3_IPP_IND_UH3_DATA_7_SELECT_INPUT, + MUX_IN_USBOH3_IPP_IND_UH3_DIR_SELECT_INPUT, + MUX_IN_USBOH3_IPP_IND_UH3_NXT_SELECT_INPUT, + MUX_IN_USBOH3_IPP_IND_UH3_STP_SELECT_INPUT, + MUX_INPUT_NUM_MUX, +} iomux_input_select_t; + +/*! + * various IOMUX input functions + */ +typedef enum iomux_input_config { + INPUT_CTL_PATH0 = 0x0, + INPUT_CTL_PATH1, + INPUT_CTL_PATH2, + INPUT_CTL_PATH3, + INPUT_CTL_PATH4, + INPUT_CTL_PATH5, + INPUT_CTL_PATH6, + INPUT_CTL_PATH7, +} iomux_input_config_t; + +/*! + * Request ownership for an IO pin. This function has to be the first one + * being called before that pin is used. The caller has to check the + * return value to make sure it returns 0. + * + * @param pin a name defined by \b iomux_pin_name_t + * @param config config as defined in \b #iomux_pin_ocfg_t + * + * @return 0 if successful; Non-zero otherwise + */ +int mxc_request_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t config); + +/*! + * Release ownership for an IO pin + * + * @param pin a name defined by \b iomux_pin_name_t + * @param config config as defined in \b #iomux_pin_ocfg_t + */ +void mxc_free_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t config); + +/*! + * This function configures the pad value for a IOMUX pin. + * + * @param pin a pin number as defined in \b #iomux_pin_name_t + * @param config the ORed value of elements defined in + * \b #iomux_pad_config_t + */ +void mxc_iomux_set_pad(iomux_pin_name_t pin, u32 config); + +/*! + * This function gets the current pad value for a IOMUX pin. + * + * @param pin a pin number as defined in \b #iomux_pin_name_t + * @return current pad value + */ +unsigned int mxc_iomux_get_pad(iomux_pin_name_t pin); + +/*! + * This function configures input path. + * + * @param input index of input select register as defined in + * \b #iomux_input_select_t + * @param config the binary value of elements defined in + * \b #iomux_input_config_t + */ +void mxc_iomux_set_input(iomux_input_select_t input, u32 config); + +#endif /* __MACH_MX51_IOMUX_H__ */ diff --git a/include/asm-arm/arch-mx51/keypad.h b/include/asm-arm/arch-mx51/keypad.h new file mode 100644 index 0000000000..5846364b08 --- /dev/null +++ b/include/asm-arm/arch-mx51/keypad.h @@ -0,0 +1,65 @@ +/* + * (C) Copyright 2009-2010 Freescale Semiconductor, Inc. + * + * Configuration settings for the MX51-3Stack Freescale board. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _MXC_KEYPAD_H_ +#define _MXC_KEYPAD_H_ + +#include + +#define KEY_1 2 +#define KEY_2 3 +#define KEY_3 4 +#define KEY_F1 59 +#define KEY_UP 103 +#define KEY_F2 60 + +#define KEY_4 5 +#define KEY_5 6 +#define KEY_6 7 +#define KEY_LEFT 105 +#define KEY_SELECT 0x161 +#define KEY_RIGHT 106 + +#define KEY_7 8 +#define KEY_8 9 +#define KEY_9 10 +#define KEY_F3 61 +#define KEY_DOWN 108 +#define KEY_F4 62 + +#define KEY_0 11 +#define KEY_OK 0x160 +#define KEY_ESC 1 +#define KEY_ENTER 28 +#define KEY_MENU 139 /* Menu (show menu) */ +#define KEY_BACK 158 /* AC Back */ + +#if defined(CONFIG_MX51_BBG) +#define TEST_HOME_KEY_DEPRESS(k, e) (((k) == (KEY_F1)) && (((e) == (KDepress)))) +#define TEST_POWER_KEY_DEPRESS(k, e) (((k) == (KEY_F3)) && (((e) == (KDepress)))) +#elif defined(CONFIG_MX51_3DS) +#define TEST_HOME_KEY_DEPRESS(k, e) (((k) == (KEY_MENU)) && (((e) == (KDepress)))) +#define TEST_POWER_KEY_DEPRESS(k, e) (((k) == (KEY_F2)) && (((e) == (KDepress)))) +#else +# error Undefined board type! +#endif + +#endif diff --git a/include/asm-arm/arch-mx51/mmu.h b/include/asm-arm/arch-mx51/mmu.h new file mode 100644 index 0000000000..1c58977a54 --- /dev/null +++ b/include/asm-arm/arch-mx51/mmu.h @@ -0,0 +1,215 @@ +/* + * Copyright 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#ifndef __ARM_ARCH_MMU_H +#define __ARM_ARCH_MMU_H + +#include + +/* + * Translation Table Base Bit Masks + */ +#define ARM_TRANSLATION_TABLE_MASK 0xFFFFC000 + +/* + * Domain Access Control Bit Masks + */ +#define ARM_ACCESS_TYPE_NO_ACCESS(domain_num) (0x0 << (domain_num)*2) +#define ARM_ACCESS_TYPE_CLIENT(domain_num) (0x1 << (domain_num)*2) +#define ARM_ACCESS_TYPE_MANAGER(domain_num) (0x3 << (domain_num)*2) + +struct ARM_MMU_FIRST_LEVEL_FAULT { + unsigned int id:2; + unsigned int sbz:30; +}; + +#define ARM_MMU_FIRST_LEVEL_FAULT_ID 0x0 + +struct ARM_MMU_FIRST_LEVEL_PAGE_TABLE { + unsigned int id:2; + unsigned int imp:2; + unsigned int domain:4; + unsigned int sbz:1; + unsigned int base_address:23; +}; + +#define ARM_MMU_FIRST_LEVEL_PAGE_TABLE_ID 0x1 + +struct ARM_MMU_FIRST_LEVEL_SECTION { + unsigned int id:2; + unsigned int b:1; + unsigned int c:1; + unsigned int imp:1; + unsigned int domain:4; + unsigned int sbz0:1; + unsigned int ap:2; + unsigned int sbz1:8; + unsigned int base_address:12; +}; + +#define ARM_MMU_FIRST_LEVEL_SECTION_ID 0x2 + +struct ARM_MMU_FIRST_LEVEL_RESERVED { + unsigned int id:2; + unsigned int sbz:30; +}; + +#define ARM_MMU_FIRST_LEVEL_RESERVED_ID 0x3 + +#define ARM_MMU_FIRST_LEVEL_DESCRIPTOR_ADDRESS(ttb_base, table_index) \ + (unsigned long *)((unsigned long)(ttb_base) + ((table_index) << 2)) + +#define ARM_FIRST_LEVEL_PAGE_TABLE_SIZE 0x4000 + +#define ARM_MMU_SECTION(ttb_base, actual_base, virtual_base, \ + cacheable, bufferable, perm) \ + { \ + register union ARM_MMU_FIRST_LEVEL_DESCRIPTOR desc; \ + desc.word = 0; \ + desc.section.id = ARM_MMU_FIRST_LEVEL_SECTION_ID; \ + desc.section.domain = 0; \ + desc.section.c = (cacheable); \ + desc.section.b = (bufferable); \ + desc.section.ap = (perm); \ + desc.section.base_address = (actual_base); \ + *ARM_MMU_FIRST_LEVEL_DESCRIPTOR_ADDRESS(ttb_base, (virtual_base)) \ + = desc.word; \ + } + +#define X_ARM_MMU_SECTION(abase, vbase, size, cache, buff, access) \ + { \ + int i; int j = abase; int k = vbase; \ + for (i = size; i > 0 ; i--, j++, k++) \ + ARM_MMU_SECTION(ttb_base, j, k, cache, buff, access); \ + } + +union ARM_MMU_FIRST_LEVEL_DESCRIPTOR { + unsigned long word; + struct ARM_MMU_FIRST_LEVEL_FAULT fault; + struct ARM_MMU_FIRST_LEVEL_PAGE_TABLE page_table; + struct ARM_MMU_FIRST_LEVEL_SECTION section; + struct ARM_MMU_FIRST_LEVEL_RESERVED reserved; +}; + +#define ARM_UNCACHEABLE 0 +#define ARM_CACHEABLE 1 +#define ARM_UNBUFFERABLE 0 +#define ARM_BUFFERABLE 1 + +#define ARM_ACCESS_PERM_NONE_NONE 0 +#define ARM_ACCESS_PERM_RO_NONE 0 +#define ARM_ACCESS_PERM_RO_RO 0 +#define ARM_ACCESS_PERM_RW_NONE 1 +#define ARM_ACCESS_PERM_RW_RO 2 +#define ARM_ACCESS_PERM_RW_RW 3 + +/* + * Initialization for the Domain Access Control Register + */ +#define ARM_ACCESS_DACR_DEFAULT ( \ + ARM_ACCESS_TYPE_MANAGER(0) | \ + ARM_ACCESS_TYPE_NO_ACCESS(1) | \ + ARM_ACCESS_TYPE_NO_ACCESS(2) | \ + ARM_ACCESS_TYPE_NO_ACCESS(3) | \ + ARM_ACCESS_TYPE_NO_ACCESS(4) | \ + ARM_ACCESS_TYPE_NO_ACCESS(5) | \ + ARM_ACCESS_TYPE_NO_ACCESS(6) | \ + ARM_ACCESS_TYPE_NO_ACCESS(7) | \ + ARM_ACCESS_TYPE_NO_ACCESS(8) | \ + ARM_ACCESS_TYPE_NO_ACCESS(9) | \ + ARM_ACCESS_TYPE_NO_ACCESS(10) | \ + ARM_ACCESS_TYPE_NO_ACCESS(11) | \ + ARM_ACCESS_TYPE_NO_ACCESS(12) | \ + ARM_ACCESS_TYPE_NO_ACCESS(13) | \ + ARM_ACCESS_TYPE_NO_ACCESS(14) | \ + ARM_ACCESS_TYPE_NO_ACCESS(15)) + +#if defined(CONFIG_MX51_3DS) + +/* + * Translate the virtual address of ram space to physical address + * It is dependent on the implementation of mmu_init + */ +inline unsigned long iomem_to_phys(unsigned long virt) +{ + if (virt < 0x08000000) + return (unsigned long)(virt | PHYS_SDRAM_1); + + if ((virt & 0xF0000000) == PHYS_SDRAM_1) + return (unsigned long)(virt & (~0x08000000)); + + return (unsigned long)virt; +} + +/* + * remap the physical address of ram space to uncacheable virtual address space + * It is dependent on the implementation of hal_mmu_init + */ +void *__ioremap(unsigned long offset, size_t size, unsigned long flags) +{ + if (1 == flags) { + /* 0x98000000~0x9FFFFFFF is uncacheable meory + space which is mapped to SDRAM */ + if ((offset & 0xF0000000) == PHYS_SDRAM_1) + return (void *)(offset |= 0x08000000); + else + return NULL; + } else + return (void *)offset; +} + +#elif defined(CONFIG_MX51_BBG) + +/* + * Translate the virtual address of ram space to physical address + * It is dependent on the implementation of mmu_init + */ +inline unsigned long iomem_to_phys(unsigned long virt) +{ + if (virt < (PHYS_SDRAM_1_SIZE - 0x100000)) + return (unsigned long)(virt + PHYS_SDRAM_1); + + if (virt >= 0xE0000000) + return (unsigned long)((virt - 0xE0000000) + PHYS_SDRAM_1); + + return (unsigned long)virt; +} + +/* + * Remap the physical address of ram space to uncacheable virtual address space + * It is dependent on the implementation of hal_mmu_init + */ +void __iounmap(void *addr) +{ + return; +} + +void *__ioremap(unsigned long offset, size_t size, unsigned long flags) +{ + if (1 == flags) { + /* 0xE0000000~0xFFFFFFFF is uncacheable + meory space which is mapped to SDRAM */ + if (offset >= PHYS_SDRAM_1 && + offset < (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE)) + return (void *)((offset - PHYS_SDRAM_1) + 0xE0000000); + else + return NULL; + } else + return (void *)offset; +} + +#else + #error "No such platforms for MMU!" +#endif + +#endif diff --git a/include/asm-arm/arch-mx51/mx51.h b/include/asm-arm/arch-mx51/mx51.h new file mode 100644 index 0000000000..5fc57bbd64 --- /dev/null +++ b/include/asm-arm/arch-mx51/mx51.h @@ -0,0 +1,493 @@ +/* + * Copyright 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#ifndef __ASM_ARCH_MXC_MX51_H__ +#define __ASM_ARCH_MXC_MX51_H__ + +#define __REG(x) (*((volatile u32 *)(x))) +#define __REG16(x) (*((volatile u16 *)(x))) +#define __REG8(x) (*((volatile u8 *)(x))) +/* + * IRAM + */ +#define IRAM_BASE_ADDR 0x1FFE8000 /* internal ram */ +/* + * Graphics Memory of GPU + */ +#define GPU_BASE_ADDR 0x20000000 +#define GPU_CTRL_BASE_ADDR 0x30000000 +#define IPU_CTRL_BASE_ADDR 0x40000000 +/* + * Debug + */ +#define DEBUG_BASE_ADDR 0x60000000 +#define ETB_BASE_ADDR (DEBUG_BASE_ADDR + 0x00001000) +#define ETM_BASE_ADDR (DEBUG_BASE_ADDR + 0x00002000) +#define TPIU_BASE_ADDR (DEBUG_BASE_ADDR + 0x00003000) +#define CTI0_BASE_ADDR (DEBUG_BASE_ADDR + 0x00004000) +#define CTI1_BASE_ADDR (DEBUG_BASE_ADDR + 0x00005000) +#define CTI2_BASE_ADDR (DEBUG_BASE_ADDR + 0x00006000) +#define CTI3_BASE_ADDR (DEBUG_BASE_ADDR + 0x00007000) +#define CORTEX_DBG_BASE_ADDR (DEBUG_BASE_ADDR + 0x00008000) + +/* + * SPBA global module enabled #0 + */ +#define SPBA0_BASE_ADDR 0x70000000 + +#define MMC_SDHC1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00004000) +#define MMC_SDHC2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00008000) +#define UART3_BASE_ADDR (SPBA0_BASE_ADDR + 0x0000C000) +#define CSPI1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00010000) +#define SSI2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00014000) +#define MMC_SDHC3_BASE_ADDR (SPBA0_BASE_ADDR + 0x00020000) +#define MMC_SDHC4_BASE_ADDR (SPBA0_BASE_ADDR + 0x00024000) +#define SPDIF_BASE_ADDR (SPBA0_BASE_ADDR + 0x00028000) +#define ATA_DMA_BASE_ADDR (SPBA0_BASE_ADDR + 0x00030000) +#define SLIM_DMA_BASE_ADDR (SPBA0_BASE_ADDR + 0x00034000) +#define HSI2C_DMA_BASE_ADDR (SPBA0_BASE_ADDR + 0x00038000) +#define SPBA_CTRL_BASE_ADDR (SPBA0_BASE_ADDR + 0x0003C000) + +/* + * AIPS 1 + */ +#define AIPS1_BASE_ADDR 0x73F00000 + +#define OTG_BASE_ADDR (AIPS1_BASE_ADDR + 0x00080000) +#define GPIO1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00084000) +#define GPIO2_BASE_ADDR (AIPS1_BASE_ADDR + 0x00088000) +#define GPIO3_BASE_ADDR (AIPS1_BASE_ADDR + 0x0008C000) +#define GPIO4_BASE_ADDR (AIPS1_BASE_ADDR + 0x00090000) +#define KPP_BASE_ADDR (AIPS1_BASE_ADDR + 0x00094000) +#define WDOG1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00098000) +#define WDOG2_BASE_ADDR (AIPS1_BASE_ADDR + 0x0009C000) +#define GPT1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A0000) +#define SRTC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A4000) +#define IOMUXC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A8000) +#define EPIT1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000AC000) +#define EPIT2_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B0000) +#define PWM1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B4000) +#define PWM2_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B8000) +#define UART1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000BC000) +#define UART2_BASE_ADDR (AIPS1_BASE_ADDR + 0x000C0000) +#define SRC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000D0000) +#define CCM_BASE_ADDR (AIPS1_BASE_ADDR + 0x000D4000) +#define GPC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000D8000) + +/* + * AIPS 2 + */ +#define AIPS2_BASE_ADDR 0x83F00000 + +#define PLL1_BASE_ADDR (AIPS2_BASE_ADDR + 0x00080000) +#define PLL2_BASE_ADDR (AIPS2_BASE_ADDR + 0x00084000) +#define PLL3_BASE_ADDR (AIPS2_BASE_ADDR + 0x00088000) +#define AHBMAX_BASE_ADDR (AIPS2_BASE_ADDR + 0x00094000) +#define IIM_BASE_ADDR (AIPS2_BASE_ADDR + 0x00098000) +#define CSU_BASE_ADDR (AIPS2_BASE_ADDR + 0x0009C000) +#define ARM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A0000) +#define OWIRE_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A4000) +#define FIRI_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A8000) +#define CSPI2_BASE_ADDR (AIPS2_BASE_ADDR + 0x000AC000) +#define SDMA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000B0000) +#define SCC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000B4000) +#define ROMCP_BASE_ADDR (AIPS2_BASE_ADDR + 0x000B8000) +#define RTIC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000BC000) +#define CSPI3_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C0000) +#define I2C2_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C4000) +#define I2C1_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C8000) +#define SSI1_BASE_ADDR (AIPS2_BASE_ADDR + 0x000CC000) +#define AUDMUX_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D0000) +#define M4IF_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D8000) +#define ESDCTL_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D9000) +#define WEIM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DA000) +#define NFC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DB000) +#define EMI_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DBF00) +#define MIPI_HSC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DC000) +#define ATA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000E0000) +#define SIM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000E4000) +#define SSI3BASE_ADDR (AIPS2_BASE_ADDR + 0x000E8000) +#define FEC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000EC000) +#define TVE_BASE_ADDR (AIPS2_BASE_ADDR + 0x000F0000) +#define VPU_BASE_ADDR (AIPS2_BASE_ADDR + 0x000F4000) +#define SAHARA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000F8000) + +#define TZIC_BASE_ADDR 0x8FFFC000 + +/* + * Memory regions and CS + */ +#define CSD0_BASE_ADDR 0x90000000 +#define CSD1_BASE_ADDR 0xA0000000 +#define CS0_BASE_ADDR 0xB0000000 +#define CS1_BASE_ADDR 0xB8000000 +#define CS2_BASE_ADDR 0xC0000000 +#define CS3_BASE_ADDR 0xC8000000 +#define CS4_BASE_ADDR 0xCC000000 +#define CS5_BASE_ADDR 0xCE000000 + +/* + * NFC + */ +#define NFC_BASE_ADDR_AXI 0xCFFF0000 /* NAND flash AXI */ + +/*! + * defines for SPBA modules + */ +#define SPBA_SDHC1 0x04 +#define SPBA_SDHC2 0x08 +#define SPBA_UART3 0x0C +#define SPBA_CSPI1 0x10 +#define SPBA_SSI2 0x14 +#define SPBA_SDHC3 0x20 +#define SPBA_SDHC4 0x24 +#define SPBA_SPDIF 0x28 +#define SPBA_ATA 0x30 +#define SPBA_SLIM 0x34 +#define SPBA_HSI2C 0x38 +#define SPBA_CTRL 0x3C + +/* + * Interrupt numbers + */ +#define MXC_INT_BASE 0 +#define MXC_INT_RESV0 0 +#define MXC_INT_MMC_SDHC1 1 +#define MXC_INT_MMC_SDHC2 2 +#define MXC_INT_MMC_SDHC3 3 +#define MXC_INT_MMC_SDHC4 4 +#define MXC_INT_RESV5 5 +#define MXC_INT_SDMA 6 +#define MXC_INT_IOMUX 7 +#define MXC_INT_NFC 8 +#define MXC_INT_VPU 9 +#define MXC_INT_IPU_ERR 10 +#define MXC_INT_IPU_SYN 11 +#define MXC_INT_GPU 12 +#define MXC_INT_RESV13 13 +#define MXC_INT_USB_H1 14 +#define MXC_INT_EMI 15 +#define MXC_INT_USB_H2 16 +#define MXC_INT_USB_H3 17 +#define MXC_INT_USB_OTG 18 +#define MXC_INT_SAHARA_H0 19 +#define MXC_INT_SAHARA_H1 20 +#define MXC_INT_SCC_SMN 21 +#define MXC_INT_SCC_STZ 22 +#define MXC_INT_SCC_SCM 23 +#define MXC_INT_SRTC_NTZ 24 +#define MXC_INT_SRTC_TZ 25 +#define MXC_INT_RTIC 26 +#define MXC_INT_CSU 27 +#define MXC_INT_SLIM_B 28 +#define MXC_INT_SSI1 29 +#define MXC_INT_SSI2 30 +#define MXC_INT_UART1 31 +#define MXC_INT_UART2 32 +#define MXC_INT_UART3 33 +#define MXC_INT_RESV34 34 +#define MXC_INT_RESV35 35 +#define MXC_INT_CSPI1 36 +#define MXC_INT_CSPI2 37 +#define MXC_INT_CSPI 38 +#define MXC_INT_GPT 39 +#define MXC_INT_EPIT1 40 +#define MXC_INT_EPIT2 41 +#define MXC_INT_GPIO1_INT7 42 +#define MXC_INT_GPIO1_INT6 43 +#define MXC_INT_GPIO1_INT5 44 +#define MXC_INT_GPIO1_INT4 45 +#define MXC_INT_GPIO1_INT3 46 +#define MXC_INT_GPIO1_INT2 47 +#define MXC_INT_GPIO1_INT1 48 +#define MXC_INT_GPIO1_INT0 49 +#define MXC_INT_GPIO1_LOW 50 +#define MXC_INT_GPIO1_HIGH 51 +#define MXC_INT_GPIO2_LOW 52 +#define MXC_INT_GPIO2_HIGH 53 +#define MXC_INT_GPIO3_LOW 54 +#define MXC_INT_GPIO3_HIGH 55 +#define MXC_INT_GPIO4_LOW 56 +#define MXC_INT_GPIO4_HIGH 57 +#define MXC_INT_WDOG1 58 +#define MXC_INT_WDOG2 59 +#define MXC_INT_KPP 60 +#define MXC_INT_PWM1 61 +#define MXC_INT_I2C1 62 +#define MXC_INT_I2C2 63 +#define MXC_INT_HS_I2C 64 +#define MXC_INT_RESV65 65 +#define MXC_INT_RESV66 66 +#define MXC_INT_SIM_IPB 67 +#define MXC_INT_SIM_DAT 68 +#define MXC_INT_IIM 69 +#define MXC_INT_ATA 70 +#define MXC_INT_CCM1 71 +#define MXC_INT_CCM2 72 +#define MXC_INT_GPC1 73 +#define MXC_INT_GPC2 74 +#define MXC_INT_SRC 75 +#define MXC_INT_NM 76 +#define MXC_INT_PMU 77 +#define MXC_INT_CTI_IRQ 78 +#define MXC_INT_CTI1_TG0 79 +#define MXC_INT_CTI1_TG1 80 +#define MXC_INT_MCG_ERR 81 +#define MXC_INT_MCG_TMR 82 +#define MXC_INT_MCG_FUNC 83 +#define MXC_INT_RESV84 84 +#define MXC_INT_RESV85 85 +#define MXC_INT_RESV86 86 +#define MXC_INT_FEC 87 +#define MXC_INT_OWIRE 88 +#define MXC_INT_CTI1_TG2 89 +#define MXC_INT_SJC 90 +#define MXC_INT_SPDIF 91 +#define MXC_INT_TVE 92 +#define MXC_INT_FIRI 93 +#define MXC_INT_PWM2 94 +#define MXC_INT_SLIM_EXP 95 +#define MXC_INT_SSI3 96 +#define MXC_INT_RESV97 97 +#define MXC_INT_CTI1_TG3 98 +#define MXC_INT_SMC_RX 99 +#define MXC_INT_VPU_IDLE 100 +#define MXC_INT_RESV101 101 +#define MXC_INT_GPU_IDLE 102 + +#define MXC_MAX_INT_LINES 128 + +#define MXC_GPIO_INT_BASE (MXC_MAX_INT_LINES) + +/*! + * Number of GPIO port as defined in the IC Spec + */ +#define GPIO_PORT_NUM 4 +/*! + * Number of GPIO pins per port + */ +#define GPIO_NUM_PIN 32 + +#define MXC_GPIO_SPLIT_IRQ_2 + +#define IIM_SREV 0x24 +#define ROM_SI_REV 0x48 + +#define NFC_BUF_SIZE 0x1000 + +/* WEIM registers */ +#define CSGCR1 0x00 +#define CSGCR2 0x04 +#define CSRCR1 0x08 +#define CSRCR2 0x0C +#define CSWCR1 0x10 + +/* M4IF */ +#define M4IF_FBPM0 0x40 +#define M4IF_FIDBP 0x48 + +/* ESDCTL */ +#define ESDCTL_ESDCTL0 0x00 +#define ESDCTL_ESDCFG0 0x04 +#define ESDCTL_ESDCTL1 0x08 +#define ESDCTL_ESDCFG1 0x0C +#define ESDCTL_ESDMISC 0x10 +#define ESDCTL_ESDSCR 0x14 +#define ESDCTL_ESDCDLY1 0x20 +#define ESDCTL_ESDCDLY2 0x24 +#define ESDCTL_ESDCDLY3 0x28 +#define ESDCTL_ESDCDLY4 0x2C +#define ESDCTL_ESDCDLY5 0x30 +#define ESDCTL_ESDCDLYGD 0x34 + +/* CCM */ +#define CLKCTL_CCR 0x00 +#define CLKCTL_CCDR 0x04 +#define CLKCTL_CSR 0x08 +#define CLKCTL_CCSR 0x0C +#define CLKCTL_CACRR 0x10 +#define CLKCTL_CBCDR 0x14 +#define CLKCTL_CBCMR 0x18 +#define CLKCTL_CSCMR1 0x1C +#define CLKCTL_CSCMR2 0x20 +#define CLKCTL_CSCDR1 0x24 +#define CLKCTL_CS1CDR 0x28 +#define CLKCTL_CS2CDR 0x2C +#define CLKCTL_CDCDR 0x30 +#define CLKCTL_CHSCCDR 0x34 +#define CLKCTL_CSCDR2 0x38 +#define CLKCTL_CSCDR3 0x3C +#define CLKCTL_CSCDR4 0x40 +#define CLKCTL_CWDR 0x44 +#define CLKCTL_CDHIPR 0x48 +#define CLKCTL_CDCR 0x4C +#define CLKCTL_CTOR 0x50 +#define CLKCTL_CLPCR 0x54 +#define CLKCTL_CISR 0x58 +#define CLKCTL_CIMR 0x5C +#define CLKCTL_CCOSR 0x60 +#define CLKCTL_CGPR 0x64 +#define CLKCTL_CCGR0 0x68 +#define CLKCTL_CCGR1 0x6C +#define CLKCTL_CCGR2 0x70 +#define CLKCTL_CCGR3 0x74 +#define CLKCTL_CCGR4 0x78 +#define CLKCTL_CCGR5 0x7C +#define CLKCTL_CCGR6 0x80 +#define CLKCTL_CMEOR 0x84 + +/* DPLL */ +#define PLL_DP_CTL 0x00 +#define PLL_DP_CONFIG 0x04 +#define PLL_DP_OP 0x08 +#define PLL_DP_MFD 0x0C +#define PLL_DP_MFN 0x10 +#define PLL_DP_MFNMINUS 0x14 +#define PLL_DP_MFNPLUS 0x18 +#define PLL_DP_HFS_OP 0x1C +#define PLL_DP_HFS_MFD 0x20 +#define PLL_DP_HFS_MFN 0x24 +#define PLL_DP_TOGC 0x28 +#define PLL_DP_DESTAT 0x2C + +/* Assuming 24MHz input clock with doubler ON */ +/* MFI PDF */ +#define DP_OP_850 ((8 << 4) + ((1 - 1) << 0)) +#define DP_MFD_850 (48 - 1) +#define DP_MFN_850 41 + +#define DP_OP_800 ((8 << 4) + ((1 - 1) << 0)) +#define DP_MFD_800 (3 - 1) +#define DP_MFN_800 1 + +#define DP_OP_700 ((7 << 4) + ((1 - 1) << 0)) +#define DP_MFD_700 (24 - 1) +#define DP_MFN_700 7 + +#define DP_OP_665 ((6 << 4) + ((1 - 1) << 0)) +#define DP_MFD_665 (96 - 1) +#define DP_MFN_665 89 + +#define DP_OP_532 ((5 << 4) + ((1 - 1) << 0)) +#define DP_MFD_532 (24 - 1) +#define DP_MFN_532 13 + +#define DP_OP_400 ((8 << 4) + ((2 - 1) << 0)) +#define DP_MFD_400 (3 - 1) +#define DP_MFN_400 1 + +#define DP_OP_216 ((6 << 4) + ((3 - 1) << 0)) +#define DP_MFD_216 (4 - 1) +#define DP_MFN_216 3 + +/* IIM */ +#define IIM_STAT_OFF 0x00 +#define IIM_STAT_BUSY (1 << 7) +#define IIM_STAT_PRGD (1 << 1) +#define IIM_STAT_SNSD (1 << 0) +#define IIM_STATM_OFF 0x04 +#define IIM_ERR_OFF 0x08 +#define IIM_ERR_PRGE (1 << 7) +#define IIM_ERR_WPE (1 << 6) +#define IIM_ERR_OPE (1 << 5) +#define IIM_ERR_RPE (1 << 4) +#define IIM_ERR_WLRE (1 << 3) +#define IIM_ERR_SNSE (1 << 2) +#define IIM_ERR_PARITYE (1 << 1) +#define IIM_EMASK_OFF 0x0C +#define IIM_FCTL_OFF 0x10 +#define IIM_UA_OFF 0x14 +#define IIM_LA_OFF 0x18 +#define IIM_SDAT_OFF 0x1C +#define IIM_PREV_OFF 0x20 +#define IIM_SREV_OFF 0x24 +#define IIM_PREG_P_OFF 0x28 +#define IIM_SCS0_OFF 0x2C +#define IIM_SCS1_P_OFF 0x30 +#define IIM_SCS2_OFF 0x34 +#define IIM_SCS3_P_OFF 0x38 + +#define IIM_PROD_REV_SH 3 +#define IIM_PROD_REV_LEN 5 +#define IIM_SREV_REV_SH 4 +#define IIM_SREV_REV_LEN 4 +#define PROD_SIGNATURE_MX51 0x1 + +#define CHIP_REV_1_0 0x10 +#define CHIP_REV_1_1 0x11 +#define CHIP_REV_2_0 0x20 +#define CHIP_REV_2_5 0x25 +#define CHIP_REV_3_0 0x30 + +#define BOARD_REV_1_0 0x0 +#define BOARD_REV_2_0 0x1 + +#define BOARD_VER_OFFSET 0x8 + +#define NAND_FLASH_BOOT 0x10000000 +#define SPI_NOR_FLASH_BOOT 0x80000000 +#define MMC_FLASH_BOOT 0x40000000 + +#ifndef __ASSEMBLER__ + +enum boot_device { + UNKNOWN_BOOT, + NAND_BOOT, + SPI_NOR_BOOT, + MMC_BOOT, +}; + +enum mxc_clock { +MXC_ARM_CLK = 0, +MXC_AHB_CLK, +MXC_IPG_CLK, +MXC_IPG_PERCLK, +MXC_UART_CLK, +MXC_CSPI_CLK, +MXC_FEC_CLK, +MXC_ESDHC_CLK, +}; + +/* +enum mxc_main_clocks { + MXC_CPU_CLK, + MXC_AHB_CLK, + MXC_IPG_CLK, + MXC_IPG_PER_CLK, + MXC_DDR_CLK, + MXC_NFC_CLK, + MXC_USB_CLK, +}; +*/ + +enum mxc_peri_clocks { + MXC_UART1_BAUD, + MXC_UART2_BAUD, + MXC_UART3_BAUD, + MXC_SSI1_BAUD, + MXC_SSI2_BAUD, + MXC_CSI_BAUD, + MXC_MSTICK1_CLK, + MXC_MSTICK2_CLK, + MXC_SPI1_CLK, + MXC_SPI2_CLK, +}; + +extern unsigned int mxc_get_clock(enum mxc_clock clk); +extern unsigned int get_board_rev(void); +extern int is_soc_rev(int rev); +extern enum boot_device get_boot_device(void); + +#endif /* __ASSEMBLER__*/ + +#endif /* __ASM_ARCH_MXC_MX51_H__ */ diff --git a/include/asm-arm/arch-mx51/mx51_pins.h b/include/asm-arm/arch-mx51/mx51_pins.h new file mode 100644 index 0000000000..63fdd8ca47 --- /dev/null +++ b/include/asm-arm/arch-mx51/mx51_pins.h @@ -0,0 +1,370 @@ +/* + * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#ifndef __ASM_ARCH_MXC_MX51_PINS_H__ +#define __ASM_ARCH_MXC_MX51_PINS_H__ + +/*! + * @file arch-mxc/mx51_pins.h + * + * @brief MX51 I/O Pin List + * + * @ingroup GPIO_MX51 + */ + +#ifndef __ASSEMBLY__ + +/*! + * @name IOMUX/PAD Bit field definitions + */ + +/*! @{ */ + +/*! + * In order to identify pins more effectively, each mux-controlled pin's + * enumerated value is constructed in the following way: + * + * ------------------------------------------------------------------- + * 31-29 | 28 - 24 | 23 - 21 | 20 - 10| 9 - 0 + * ------------------------------------------------------------------- + * IO_P | IO_I | GPIO_I | PAD_I | MUX_I + * ------------------------------------------------------------------- + * + * Bit 0 to 9 contains MUX_I used to identify the register + * offset (0-based. base is IOMUX_module_base) defined in the Section + * "sw_pad_ctl & sw_mux_ctl details" of the IC Spec. The + * similar field definitions are used for the pad control register. + * For example, the MX51_PIN_ETM_D0 is defined in the enumeration: + * ( (0x28 - MUX_I_START) << MUX_I)|( (0x250 - PAD_I_START) << PAD_I) + * It means the mux control register is at register offset 0x28. The pad control + * register offset is: 0x250 and also occupy the least significant bits + * within the register. + */ + +/*! + * Starting bit position within each entry of \b iomux_pins to represent the + * MUX control register offset + */ +#define MUX_I 0 +/*! + * Starting bit position within each entry of \b iomux_pins to represent the + * PAD control register offset + */ +#define PAD_I 10 +/*! + * Starting bit position within each entry of \b iomux_pins to represent which + * mux mode is for GPIO (0-based) + */ +#define GPIO_I 21 + +#define MUX_IO_P 29 +#define MUX_IO_I 24 +#define IOMUX_TO_GPIO(pin) ((((unsigned int)pin >> MUX_IO_P) * \ + GPIO_NUM_PIN) + ((pin >> MUX_IO_I) &\ + ((1 << (MUX_IO_P - MUX_IO_I)) - 1))) +#define IOMUX_TO_IRQ(pin) (MXC_GPIO_INT_BASE + IOMUX_TO_GPIO(pin)) +#define GPIO_TO_PORT(n) (n / GPIO_NUM_PIN) +#define GPIO_TO_INDEX(n) (n % GPIO_NUM_PIN) + +#define NON_GPIO_PORT 0x7 +#define PIN_TO_MUX_MASK ((1 << (PAD_I - MUX_I)) - 1) +#define PIN_TO_PAD_MASK ((1 << (GPIO_I - PAD_I)) - 1) +#define PIN_TO_ALT_GPIO_MASK ((1 << (MUX_IO_I - GPIO_I)) - 1) + +#define NON_MUX_I PIN_TO_MUX_MASK +#define MUX_I_START 0x001C +#define PAD_I_START 0x3F0 +#define INPUT_CTL_START 0x8C4 +#define INPUT_CTL_START_TO1 0x928 +#define MUX_I_END (PAD_I_START - 4) + +#define _MXC_BUILD_PIN(gp, gi, ga, mi, pi) \ + (((gp) << MUX_IO_P) | ((gi) << MUX_IO_I) | \ + ((mi) << MUX_I) | \ + ((pi - PAD_I_START) << PAD_I) | \ + ((ga) << GPIO_I)) + +#define _MXC_BUILD_GPIO_PIN(gp, gi, ga, mi, pi) \ + _MXC_BUILD_PIN(gp, gi, ga, mi, pi) + +#define _MXC_BUILD_NON_GPIO_PIN(mi, pi) \ + _MXC_BUILD_PIN(NON_GPIO_PORT, 0, 0, mi, pi) + +#define PIN_TO_IOMUX_MUX(pin) ((pin >> MUX_I) & PIN_TO_MUX_MASK) +#define PIN_TO_IOMUX_PAD(pin) ((pin >> PAD_I) & PIN_TO_PAD_MASK) +#define PIN_TO_ALT_GPIO(pin) ((pin >> GPIO_I) & PIN_TO_ALT_GPIO_MASK) +#define PIN_TO_IOMUX_INDEX(pin) (PIN_TO_IOMUX_MUX(pin) >> 2) + +/*! @} End IOMUX/PAD Bit field definitions */ + +/*! + * This enumeration is constructed based on the Section + * "sw_pad_ctl & sw_mux_ctl details" of the MX51 IC Spec. Each enumerated + * value is constructed based on the rules described above. + */ +enum iomux_pins { + MX51_PIN_EIM_DA0 = _MXC_BUILD_NON_GPIO_PIN(0x1C, 0x7A8), + MX51_PIN_EIM_DA1 = _MXC_BUILD_NON_GPIO_PIN(0x20, 0x7A8), + MX51_PIN_EIM_DA2 = _MXC_BUILD_NON_GPIO_PIN(0x24, 0x7A8), + MX51_PIN_EIM_DA3 = _MXC_BUILD_NON_GPIO_PIN(0x28, 0x7A8), + MX51_PIN_EIM_DA4 = _MXC_BUILD_NON_GPIO_PIN(0x2C, 0x7AC), + MX51_PIN_EIM_DA5 = _MXC_BUILD_NON_GPIO_PIN(0x30, 0x7AC), + MX51_PIN_EIM_DA6 = _MXC_BUILD_NON_GPIO_PIN(0x34, 0x7AC), + MX51_PIN_EIM_DA7 = _MXC_BUILD_NON_GPIO_PIN(0x38, 0x7AC), + MX51_PIN_EIM_DA8 = _MXC_BUILD_NON_GPIO_PIN(0x3C, 0x7B0), + MX51_PIN_EIM_DA9 = _MXC_BUILD_NON_GPIO_PIN(0x40, 0x7B0), + MX51_PIN_EIM_DA10 = _MXC_BUILD_NON_GPIO_PIN(0x44, 0x7B0), + MX51_PIN_EIM_DA11 = _MXC_BUILD_NON_GPIO_PIN(0x48, 0x7B0), + MX51_PIN_EIM_DA12 = _MXC_BUILD_NON_GPIO_PIN(0x4C, 0x7BC), + MX51_PIN_EIM_DA13 = _MXC_BUILD_NON_GPIO_PIN(0x50, 0x7BC), + MX51_PIN_EIM_DA14 = _MXC_BUILD_NON_GPIO_PIN(0x54, 0x7BC), + MX51_PIN_EIM_DA15 = _MXC_BUILD_NON_GPIO_PIN(0x58, 0x7BC), + MX51_PIN_EIM_D16 = _MXC_BUILD_GPIO_PIN(1, 0, 1, 0x5C, 0x3F0), + MX51_PIN_EIM_D17 = _MXC_BUILD_GPIO_PIN(1, 1, 1, 0x60, 0x3F4), + MX51_PIN_EIM_D18 = _MXC_BUILD_GPIO_PIN(1, 2, 1, 0x64, 0x3F8), + MX51_PIN_EIM_D19 = _MXC_BUILD_GPIO_PIN(1, 3, 1, 0x68, 0x3FC), + MX51_PIN_EIM_D20 = _MXC_BUILD_GPIO_PIN(1, 4, 1, 0x6C, 0x400), + MX51_PIN_EIM_D21 = _MXC_BUILD_GPIO_PIN(1, 5, 1, 0x70, 0x404), + MX51_PIN_EIM_D22 = _MXC_BUILD_GPIO_PIN(1, 6, 1, 0x74, 0x408), + MX51_PIN_EIM_D23 = _MXC_BUILD_GPIO_PIN(1, 7, 1, 0x78, 0x40C), + MX51_PIN_EIM_D24 = _MXC_BUILD_GPIO_PIN(1, 8, 1, 0x7C, 0x410), + MX51_PIN_EIM_D25 = _MXC_BUILD_NON_GPIO_PIN(0x80, 0x414), + MX51_PIN_EIM_D26 = _MXC_BUILD_NON_GPIO_PIN(0x84, 0x418), + MX51_PIN_EIM_D27 = _MXC_BUILD_GPIO_PIN(1, 9, 1, 0x88, 0x41C), + MX51_PIN_EIM_D28 = _MXC_BUILD_NON_GPIO_PIN(0x8C, 0x420), + MX51_PIN_EIM_D29 = _MXC_BUILD_NON_GPIO_PIN(0x90, 0x424), + MX51_PIN_EIM_D30 = _MXC_BUILD_NON_GPIO_PIN(0x94, 0x428), + MX51_PIN_EIM_D31 = _MXC_BUILD_NON_GPIO_PIN(0x98, 0x42C), + MX51_PIN_EIM_A16 = _MXC_BUILD_GPIO_PIN(1, 10, 1, 0x9C, 0x430), + MX51_PIN_EIM_A17 = _MXC_BUILD_GPIO_PIN(1, 11, 1, 0xA0, 0x434), + MX51_PIN_EIM_A18 = _MXC_BUILD_GPIO_PIN(1, 12, 1, 0xA4, 0x438), + MX51_PIN_EIM_A19 = _MXC_BUILD_GPIO_PIN(1, 13, 1, 0xA8, 0x43C), + MX51_PIN_EIM_A20 = _MXC_BUILD_GPIO_PIN(1, 14, 1, 0xAC, 0x440), + MX51_PIN_EIM_A21 = _MXC_BUILD_GPIO_PIN(1, 15, 1, 0xB0, 0x444), + MX51_PIN_EIM_A22 = _MXC_BUILD_GPIO_PIN(1, 16, 1, 0xB4, 0x448), + MX51_PIN_EIM_A23 = _MXC_BUILD_GPIO_PIN(1, 17, 1, 0xB8, 0x44C), + MX51_PIN_EIM_A24 = _MXC_BUILD_GPIO_PIN(1, 18, 1, 0xBC, 0x450), + MX51_PIN_EIM_A25 = _MXC_BUILD_GPIO_PIN(1, 19, 1, 0xC0, 0x454), + MX51_PIN_EIM_A26 = _MXC_BUILD_GPIO_PIN(1, 20, 1, 0xC4, 0x458), + MX51_PIN_EIM_A27 = _MXC_BUILD_GPIO_PIN(1, 21, 1, 0xC8, 0x45C), + MX51_PIN_EIM_EB0 = _MXC_BUILD_NON_GPIO_PIN(0xCC, 0x460), + MX51_PIN_EIM_EB1 = _MXC_BUILD_NON_GPIO_PIN(0xD0, 0x464), + MX51_PIN_EIM_EB2 = _MXC_BUILD_GPIO_PIN(1, 22, 1, 0xD4, 0x468), + MX51_PIN_EIM_EB3 = _MXC_BUILD_GPIO_PIN(1, 23, 1, 0xD8, 0x46C), + MX51_PIN_EIM_OE = _MXC_BUILD_GPIO_PIN(1, 24, 1, 0xDC, 0x470), + MX51_PIN_EIM_CS0 = _MXC_BUILD_GPIO_PIN(1, 25, 1, 0xE0, 0x474), + MX51_PIN_EIM_CS1 = _MXC_BUILD_GPIO_PIN(1, 26, 1, 0xE4, 0x478), + MX51_PIN_EIM_CS2 = _MXC_BUILD_GPIO_PIN(1, 27, 1, 0xE8, 0x47C), + MX51_PIN_EIM_CS3 = _MXC_BUILD_GPIO_PIN(1, 28, 1, 0xEC, 0x480), + MX51_PIN_EIM_CS4 = _MXC_BUILD_GPIO_PIN(1, 29, 1, 0xF0, 0x484), + MX51_PIN_EIM_CS5 = _MXC_BUILD_GPIO_PIN(1, 30, 1, 0xF4, 0x488), + MX51_PIN_EIM_DTACK = _MXC_BUILD_GPIO_PIN(1, 31, 1, 0xF8, 0x48C), + MX51_PIN_EIM_LBA = _MXC_BUILD_GPIO_PIN(2, 1, 1, 0xFC, 0x494), + MX51_PIN_EIM_CRE = _MXC_BUILD_GPIO_PIN(2, 2, 1, 0x100, 0x4A0), + MX51_PIN_DRAM_CS1 = _MXC_BUILD_NON_GPIO_PIN(0x104, 0x4D0), + MX51_PIN_NANDF_WE_B = _MXC_BUILD_GPIO_PIN(2, 3, 3, 0x108, 0x4E4), + MX51_PIN_NANDF_RE_B = _MXC_BUILD_GPIO_PIN(2, 4, 3, 0x10C, 0x4E8), + MX51_PIN_NANDF_ALE = _MXC_BUILD_GPIO_PIN(2, 5, 3, 0x110, 0x4EC), + MX51_PIN_NANDF_CLE = _MXC_BUILD_GPIO_PIN(2, 6, 3, 0x114, 0x4F0), + MX51_PIN_NANDF_WP_B = _MXC_BUILD_GPIO_PIN(2, 7, 3, 0x118, 0x4F4), + MX51_PIN_NANDF_RB0 = _MXC_BUILD_GPIO_PIN(2, 8, 3, 0x11C, 0x4F8), + MX51_PIN_NANDF_RB1 = _MXC_BUILD_GPIO_PIN(2, 9, 3, 0x120, 0x4FC), + MX51_PIN_NANDF_RB2 = _MXC_BUILD_GPIO_PIN(2, 10, 3, 0x124, 0x500), + MX51_PIN_NANDF_RB3 = _MXC_BUILD_GPIO_PIN(2, 11, 3, 0x128, 0x504), + MX51_PIN_GPIO_NAND = _MXC_BUILD_GPIO_PIN(2, 12, 3, 0x12C, 0x514), + MX51_PIN_NANDF_RB4 = MX51_PIN_GPIO_NAND, + MX51_PIN_NANDF_RB5 = _MXC_BUILD_GPIO_PIN(2, 13, 3, 0x130, 0x5D8), + MX51_PIN_NANDF_RB6 = _MXC_BUILD_GPIO_PIN(2, 14, 3, 0x134, 0x5DC), + MX51_PIN_NANDF_RB7 = _MXC_BUILD_GPIO_PIN(2, 15, 3, 0x138, 0x5E0), + MX51_PIN_NANDF_CS0 = _MXC_BUILD_GPIO_PIN(2, 16, 3, 0x130, 0x518), + MX51_PIN_NANDF_CS1 = _MXC_BUILD_GPIO_PIN(2, 17, 3, 0x134, 0x51C), + MX51_PIN_NANDF_CS2 = _MXC_BUILD_GPIO_PIN(2, 18, 3, 0x138, 0x520), + MX51_PIN_NANDF_CS3 = _MXC_BUILD_GPIO_PIN(2, 19, 3, 0x13C, 0x524), + MX51_PIN_NANDF_CS4 = _MXC_BUILD_GPIO_PIN(2, 20, 3, 0x140, 0x528), + MX51_PIN_NANDF_CS5 = _MXC_BUILD_GPIO_PIN(2, 21, 3, 0x144, 0x52C), + MX51_PIN_NANDF_CS6 = _MXC_BUILD_GPIO_PIN(2, 22, 3, 0x148, 0x530), + MX51_PIN_NANDF_CS7 = _MXC_BUILD_GPIO_PIN(2, 23, 3, 0x14C, 0x534), + MX51_PIN_NANDF_RDY_INT = _MXC_BUILD_GPIO_PIN(2, 24, 3, 0x150, 0x538), + MX51_PIN_NANDF_D15 = _MXC_BUILD_GPIO_PIN(2, 25, 3, 0x154, 0x53C), + MX51_PIN_NANDF_D14 = _MXC_BUILD_GPIO_PIN(2, 26, 3, 0x158, 0x540), + MX51_PIN_NANDF_D13 = _MXC_BUILD_GPIO_PIN(2, 27, 3, 0x15C, 0x544), + MX51_PIN_NANDF_D12 = _MXC_BUILD_GPIO_PIN(2, 28, 3, 0x160, 0x548), + MX51_PIN_NANDF_D11 = _MXC_BUILD_GPIO_PIN(2, 29, 3, 0x164, 0x54C), + MX51_PIN_NANDF_D10 = _MXC_BUILD_GPIO_PIN(2, 30, 3, 0x168, 0x550), + MX51_PIN_NANDF_D9 = _MXC_BUILD_GPIO_PIN(2, 31, 3, 0x16C, 0x554), + MX51_PIN_NANDF_D8 = _MXC_BUILD_GPIO_PIN(3, 0, 3, 0x170, 0x558), + MX51_PIN_NANDF_D7 = _MXC_BUILD_GPIO_PIN(3, 1, 3, 0x174, 0x55C), + MX51_PIN_NANDF_D6 = _MXC_BUILD_GPIO_PIN(3, 2, 3, 0x178, 0x560), + MX51_PIN_NANDF_D5 = _MXC_BUILD_GPIO_PIN(3, 3, 3, 0x17C, 0x564), + MX51_PIN_NANDF_D4 = _MXC_BUILD_GPIO_PIN(3, 4, 3, 0x180, 0x568), + MX51_PIN_NANDF_D3 = _MXC_BUILD_GPIO_PIN(3, 5, 3, 0x184, 0x56C), + MX51_PIN_NANDF_D2 = _MXC_BUILD_GPIO_PIN(3, 6, 3, 0x188, 0x570), + MX51_PIN_NANDF_D1 = _MXC_BUILD_GPIO_PIN(3, 7, 3, 0x18C, 0x574), + MX51_PIN_NANDF_D0 = _MXC_BUILD_GPIO_PIN(3, 8, 3, 0x190, 0x578), + MX51_PIN_CSI1_D8 = _MXC_BUILD_GPIO_PIN(2, 12, 3, 0x194, 0x57C), + MX51_PIN_CSI1_D9 = _MXC_BUILD_GPIO_PIN(2, 13, 3, 0x198, 0x580), + MX51_PIN_CSI1_D10 = _MXC_BUILD_NON_GPIO_PIN(0x19C, 0x584), + MX51_PIN_CSI1_D11 = _MXC_BUILD_NON_GPIO_PIN(0x1A0, 0x588), + MX51_PIN_CSI1_D12 = _MXC_BUILD_NON_GPIO_PIN(0x1A4, 0x58C), + MX51_PIN_CSI1_D13 = _MXC_BUILD_NON_GPIO_PIN(0x1A8, 0x590), + MX51_PIN_CSI1_D14 = _MXC_BUILD_NON_GPIO_PIN(0x1AC, 0x594), + MX51_PIN_CSI1_D15 = _MXC_BUILD_NON_GPIO_PIN(0x1B0, 0x598), + MX51_PIN_CSI1_D16 = _MXC_BUILD_NON_GPIO_PIN(0x1B4, 0x59C), + MX51_PIN_CSI1_D17 = _MXC_BUILD_NON_GPIO_PIN(0x1B8, 0x5A0), + MX51_PIN_CSI1_D18 = _MXC_BUILD_NON_GPIO_PIN(0x1BC, 0x5A4), + MX51_PIN_CSI1_D19 = _MXC_BUILD_NON_GPIO_PIN(0x1C0, 0x5A8), + MX51_PIN_CSI1_VSYNC = _MXC_BUILD_NON_GPIO_PIN(0x1C4, 0x5AC), + MX51_PIN_CSI1_HSYNC = _MXC_BUILD_NON_GPIO_PIN(0x1C8, 0x5B0), + MX51_PIN_CSI1_PIXCLK = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x5B4), + MX51_PIN_CSI1_MCLK = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x5B8), + MX51_PIN_CSI1_PKE0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x860), + MX51_PIN_CSI2_D12 = _MXC_BUILD_GPIO_PIN(3, 9, 3, 0x1CC, 0x5BC), + MX51_PIN_CSI2_D13 = _MXC_BUILD_GPIO_PIN(3, 10, 3, 0x1D0, 0x5C0), + MX51_PIN_CSI2_D14 = _MXC_BUILD_GPIO_PIN(3, 11, 3, 0x1D4, 0x5C4), + MX51_PIN_CSI2_D15 = _MXC_BUILD_GPIO_PIN(3, 12, 3, 0x1D8, 0x5C8), + MX51_PIN_CSI2_D16 = _MXC_BUILD_GPIO_PIN(3, 11, 3, 0x1DC, 0x5CC), + MX51_PIN_CSI2_D17 = _MXC_BUILD_GPIO_PIN(3, 12, 3, 0x1E0, 0x5D0), + MX51_PIN_CSI2_D18 = _MXC_BUILD_GPIO_PIN(3, 11, 3, 0x1E4, 0x5D4), + MX51_PIN_CSI2_D19 = _MXC_BUILD_GPIO_PIN(3, 12, 3, 0x1E8, 0x5D8), + MX51_PIN_CSI2_VSYNC = _MXC_BUILD_GPIO_PIN(3, 13, 3, 0x1EC, 0x5DC), + MX51_PIN_CSI2_HSYNC = _MXC_BUILD_GPIO_PIN(3, 14, 3, 0x1F0, 0x5E0), + MX51_PIN_CSI2_PIXCLK = _MXC_BUILD_GPIO_PIN(3, 15, 3, 0x1F4, 0x5E4), + MX51_PIN_CSI2_PKE0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x81C), + MX51_PIN_I2C1_CLK = _MXC_BUILD_GPIO_PIN(3, 16, 3, 0x1F8, 0x5E8), + MX51_PIN_I2C1_DAT = _MXC_BUILD_GPIO_PIN(3, 17, 3, 0x1FC, 0x5EC), + MX51_PIN_AUD3_BB_TXD = _MXC_BUILD_GPIO_PIN(3, 18, 3, 0x200, 0x5F0), + MX51_PIN_AUD3_BB_RXD = _MXC_BUILD_GPIO_PIN(3, 19, 3, 0x204, 0x5F4), + MX51_PIN_AUD3_BB_CK = _MXC_BUILD_GPIO_PIN(3, 20, 3, 0x208, 0x5F8), + MX51_PIN_AUD3_BB_FS = _MXC_BUILD_GPIO_PIN(3, 21, 3, 0x20C, 0x5FC), + MX51_PIN_CSPI1_MOSI = _MXC_BUILD_GPIO_PIN(3, 22, 3, 0x210, 0x600), + MX51_PIN_CSPI1_MISO = _MXC_BUILD_GPIO_PIN(3, 23, 3, 0x214, 0x604), + MX51_PIN_CSPI1_SS0 = _MXC_BUILD_GPIO_PIN(3, 24, 3, 0x218, 0x608), + MX51_PIN_CSPI1_SS1 = _MXC_BUILD_GPIO_PIN(3, 25, 3, 0x21C, 0x60C), + MX51_PIN_CSPI1_RDY = _MXC_BUILD_GPIO_PIN(3, 26, 3, 0x220, 0x610), + MX51_PIN_CSPI1_SCLK = _MXC_BUILD_GPIO_PIN(3, 27, 3, 0x224, 0x614), + MX51_PIN_UART1_RXD = _MXC_BUILD_GPIO_PIN(3, 28, 3, 0x228, 0x618), + MX51_PIN_UART1_TXD = _MXC_BUILD_GPIO_PIN(3, 29, 3, 0x22C, 0x61C), + MX51_PIN_UART1_RTS = _MXC_BUILD_GPIO_PIN(3, 30, 3, 0x230, 0x620), + MX51_PIN_UART1_CTS = _MXC_BUILD_GPIO_PIN(3, 31, 3, 0x234, 0x624), + MX51_PIN_UART2_RXD = _MXC_BUILD_GPIO_PIN(0, 20, 3, 0x238, 0x628), + MX51_PIN_UART2_TXD = _MXC_BUILD_GPIO_PIN(0, 21, 3, 0x23C, 0x62C), + MX51_PIN_UART3_RXD = _MXC_BUILD_GPIO_PIN(0, 22, 3, 0x240, 0x630), + MX51_PIN_UART3_TXD = _MXC_BUILD_GPIO_PIN(0, 23, 3, 0x244, 0x634), + MX51_PIN_OWIRE_LINE = _MXC_BUILD_GPIO_PIN(0, 24, 3, 0x248, 0x638), + MX51_PIN_KEY_ROW0 = _MXC_BUILD_NON_GPIO_PIN(0x24C, 0x63C), + MX51_PIN_KEY_ROW1 = _MXC_BUILD_NON_GPIO_PIN(0x250, 0x640), + MX51_PIN_KEY_ROW2 = _MXC_BUILD_NON_GPIO_PIN(0x254, 0x644), + MX51_PIN_KEY_ROW3 = _MXC_BUILD_NON_GPIO_PIN(0x258, 0x648), + MX51_PIN_KEY_COL0 = _MXC_BUILD_NON_GPIO_PIN(0x25C, 0x64C), + MX51_PIN_KEY_COL1 = _MXC_BUILD_NON_GPIO_PIN(0x260, 0x650), + MX51_PIN_KEY_COL2 = _MXC_BUILD_NON_GPIO_PIN(0x264, 0x654), + MX51_PIN_KEY_COL3 = _MXC_BUILD_NON_GPIO_PIN(0x268, 0x658), + MX51_PIN_KEY_COL4 = _MXC_BUILD_NON_GPIO_PIN(0x26C, 0x65C), + MX51_PIN_KEY_COL5 = _MXC_BUILD_NON_GPIO_PIN(0x270, 0x660), + MX51_PIN_USBH1_CLK = _MXC_BUILD_GPIO_PIN(0, 25, 2, 0x278, 0x678), + MX51_PIN_USBH1_DIR = _MXC_BUILD_GPIO_PIN(0, 26, 2, 0x27C, 0x67C), + MX51_PIN_USBH1_STP = _MXC_BUILD_GPIO_PIN(0, 27, 2, 0x280, 0x680), + MX51_PIN_USBH1_NXT = _MXC_BUILD_GPIO_PIN(0, 28, 2, 0x284, 0x684), + MX51_PIN_USBH1_DATA0 = _MXC_BUILD_GPIO_PIN(0, 11, 2, 0x288, 0x688), + MX51_PIN_USBH1_DATA1 = _MXC_BUILD_GPIO_PIN(0, 12, 2, 0x28C, 0x68C), + MX51_PIN_USBH1_DATA2 = _MXC_BUILD_GPIO_PIN(0, 13, 2, 0x290, 0x690), + MX51_PIN_USBH1_DATA3 = _MXC_BUILD_GPIO_PIN(0, 14, 2, 0x294, 0x694), + MX51_PIN_USBH1_DATA4 = _MXC_BUILD_GPIO_PIN(0, 15, 2, 0x298, 0x698), + MX51_PIN_USBH1_DATA5 = _MXC_BUILD_GPIO_PIN(0, 16, 2, 0x29C, 0x69C), + MX51_PIN_USBH1_DATA6 = _MXC_BUILD_GPIO_PIN(0, 17, 2, 0x2A0, 0x6A0), + MX51_PIN_USBH1_DATA7 = _MXC_BUILD_GPIO_PIN(0, 18, 2, 0x2A4, 0x6A4), + MX51_PIN_DI1_PIN11 = _MXC_BUILD_GPIO_PIN(2, 0, 4, 0x2A8, 0x6A8), + MX51_PIN_DI1_PIN12 = _MXC_BUILD_GPIO_PIN(2, 1, 4, 0x2AC, 0x6AC), + MX51_PIN_DI1_PIN13 = _MXC_BUILD_GPIO_PIN(2, 2, 4, 0x2B0, 0x6B0), + MX51_PIN_DI1_D0_CS = _MXC_BUILD_GPIO_PIN(2, 3, 4, 0x2B4, 0x6B4), + MX51_PIN_DI1_D1_CS = _MXC_BUILD_GPIO_PIN(2, 4, 4, 0x2B8, 0x6B8), + MX51_PIN_DISPB2_SER_DIN = _MXC_BUILD_GPIO_PIN(2, 5, 4, 0x2BC, 0x6BC), + MX51_PIN_DISPB2_SER_DIO = _MXC_BUILD_GPIO_PIN(2, 6, 4, 0x2C0, 0x6C0), + MX51_PIN_DISPB2_SER_CLK = _MXC_BUILD_GPIO_PIN(2, 7, 4, 0x2C4, 0x6C4), + MX51_PIN_DISPB2_SER_RS = _MXC_BUILD_GPIO_PIN(2, 8, 4, 0x2C8, 0x6C8), + MX51_PIN_DISP1_DAT0 = _MXC_BUILD_NON_GPIO_PIN(0x2CC, 0x6CC), + MX51_PIN_DISP1_DAT1 = _MXC_BUILD_NON_GPIO_PIN(0x2D0, 0x6D0), + MX51_PIN_DISP1_DAT2 = _MXC_BUILD_NON_GPIO_PIN(0x2D4, 0x6D4), + MX51_PIN_DISP1_DAT3 = _MXC_BUILD_NON_GPIO_PIN(0x2D8, 0x6D8), + MX51_PIN_DISP1_DAT4 = _MXC_BUILD_NON_GPIO_PIN(0x2DC, 0x6DC), + MX51_PIN_DISP1_DAT5 = _MXC_BUILD_NON_GPIO_PIN(0x2E0, 0x6E0), + MX51_PIN_DISP1_DAT6 = _MXC_BUILD_NON_GPIO_PIN(0x2E4, 0x6E4), + MX51_PIN_DISP1_DAT7 = _MXC_BUILD_NON_GPIO_PIN(0x2E8, 0x6E8), + MX51_PIN_DISP1_DAT8 = _MXC_BUILD_NON_GPIO_PIN(0x2EC, 0x6EC), + MX51_PIN_DISP1_DAT9 = _MXC_BUILD_NON_GPIO_PIN(0x2F0, 0x6F0), + MX51_PIN_DISP1_DAT10 = _MXC_BUILD_NON_GPIO_PIN(0x2F4, 0x6F4), + MX51_PIN_DISP1_DAT11 = _MXC_BUILD_NON_GPIO_PIN(0x2F8, 0x6F8), + MX51_PIN_DISP1_DAT12 = _MXC_BUILD_NON_GPIO_PIN(0x2FC, 0x6FC), + MX51_PIN_DISP1_DAT13 = _MXC_BUILD_NON_GPIO_PIN(0x300, 0x700), + MX51_PIN_DISP1_DAT14 = _MXC_BUILD_NON_GPIO_PIN(0x304, 0x704), + MX51_PIN_DISP1_DAT15 = _MXC_BUILD_NON_GPIO_PIN(0x308, 0x708), + MX51_PIN_DISP1_DAT16 = _MXC_BUILD_NON_GPIO_PIN(0x30C, 0x70C), + MX51_PIN_DISP1_DAT17 = _MXC_BUILD_NON_GPIO_PIN(0x310, 0x710), + MX51_PIN_DISP1_DAT18 = _MXC_BUILD_NON_GPIO_PIN(0x314, 0x714), + MX51_PIN_DISP1_DAT19 = _MXC_BUILD_NON_GPIO_PIN(0x318, 0x718), + MX51_PIN_DISP1_DAT20 = _MXC_BUILD_NON_GPIO_PIN(0x31C, 0x71C), + MX51_PIN_DISP1_DAT21 = _MXC_BUILD_NON_GPIO_PIN(0x320, 0x720), + MX51_PIN_DISP1_DAT22 = _MXC_BUILD_NON_GPIO_PIN(0x324, 0x724), + MX51_PIN_DISP1_DAT23 = _MXC_BUILD_NON_GPIO_PIN(0x328, 0x728), + MX51_PIN_DI1_PIN3 = _MXC_BUILD_NON_GPIO_PIN(0x32C, 0x72C), + MX51_PIN_DI1_PIN2 = _MXC_BUILD_NON_GPIO_PIN(0x330, 0x734), + MX51_PIN_DI_GP1 = _MXC_BUILD_NON_GPIO_PIN(0x334, 0x73C), + MX51_PIN_DI_GP2 = _MXC_BUILD_NON_GPIO_PIN(0x338, 0x740), + MX51_PIN_DI_GP3 = _MXC_BUILD_NON_GPIO_PIN(0x33C, 0x744), + MX51_PIN_DI2_PIN4 = _MXC_BUILD_NON_GPIO_PIN(0x340, 0x748), + MX51_PIN_DI2_PIN2 = _MXC_BUILD_NON_GPIO_PIN(0x344, 0x74C), + MX51_PIN_DI2_PIN3 = _MXC_BUILD_NON_GPIO_PIN(0x348, 0x750), + MX51_PIN_DI2_DISP_CLK = _MXC_BUILD_NON_GPIO_PIN(0x34C, 0x754), + MX51_PIN_DI_GP4 = _MXC_BUILD_NON_GPIO_PIN(0x350, 0x758), + MX51_PIN_DISP2_DAT0 = _MXC_BUILD_NON_GPIO_PIN(0x354, 0x75C), + MX51_PIN_DISP2_DAT1 = _MXC_BUILD_NON_GPIO_PIN(0x358, 0x760), + MX51_PIN_DISP2_DAT2 = _MXC_BUILD_NON_GPIO_PIN(0x35C, 0x764), + MX51_PIN_DISP2_DAT3 = _MXC_BUILD_NON_GPIO_PIN(0x360, 0x768), + MX51_PIN_DISP2_DAT4 = _MXC_BUILD_NON_GPIO_PIN(0x364, 0x76C), + MX51_PIN_DISP2_DAT5 = _MXC_BUILD_NON_GPIO_PIN(0x368, 0x770), + MX51_PIN_DISP2_DAT6 = _MXC_BUILD_GPIO_PIN(0, 19, 5, 0x36C, 0x774), + MX51_PIN_DISP2_DAT7 = _MXC_BUILD_GPIO_PIN(0, 29, 5, 0x370, 0x778), + MX51_PIN_DISP2_DAT8 = _MXC_BUILD_GPIO_PIN(0, 30, 5, 0x374, 0x77C), + MX51_PIN_DISP2_DAT9 = _MXC_BUILD_GPIO_PIN(0, 31, 5, 0x378, 0x780), + MX51_PIN_DISP2_DAT10 = _MXC_BUILD_NON_GPIO_PIN(0x37C, 0x784), + MX51_PIN_DISP2_DAT11 = _MXC_BUILD_NON_GPIO_PIN(0x380, 0x788), + MX51_PIN_DISP2_DAT12 = _MXC_BUILD_NON_GPIO_PIN(0x384, 0x78C), + MX51_PIN_DISP2_DAT13 = _MXC_BUILD_NON_GPIO_PIN(0x388, 0x790), + MX51_PIN_DISP2_DAT14 = _MXC_BUILD_NON_GPIO_PIN(0x38C, 0x794), + MX51_PIN_DISP2_DAT15 = _MXC_BUILD_NON_GPIO_PIN(0x390, 0x798), + MX51_PIN_SD1_CMD = _MXC_BUILD_NON_GPIO_PIN(0x394, 0x79C), + MX51_PIN_SD1_CLK = _MXC_BUILD_NON_GPIO_PIN(0x398, 0x7A0), + MX51_PIN_SD1_DATA0 = _MXC_BUILD_NON_GPIO_PIN(0x39C, 0x7A4), + MX51_PIN_SD1_DATA1 = _MXC_BUILD_NON_GPIO_PIN(0x3A0, 0x7A8), + MX51_PIN_SD1_DATA2 = _MXC_BUILD_NON_GPIO_PIN(0x3A4, 0x7AC), + MX51_PIN_SD1_DATA3 = _MXC_BUILD_NON_GPIO_PIN(0x3A8, 0x7B0), + MX51_PIN_GPIO1_0 = _MXC_BUILD_GPIO_PIN(0, 0, 1, 0x3AC, 0x7B4), + MX51_PIN_GPIO1_1 = _MXC_BUILD_GPIO_PIN(0, 1, 1, 0x3B0, 0x7B8), + MX51_PIN_SD2_CMD = _MXC_BUILD_NON_GPIO_PIN(0x3B4, 0x7BC), + MX51_PIN_SD2_CLK = _MXC_BUILD_NON_GPIO_PIN(0x3B8, 0x7C0), + MX51_PIN_SD2_DATA0 = _MXC_BUILD_NON_GPIO_PIN(0x3BC, 0x7C4), + MX51_PIN_SD2_DATA1 = _MXC_BUILD_NON_GPIO_PIN(0x3C0, 0x7C8), + MX51_PIN_SD2_DATA2 = _MXC_BUILD_NON_GPIO_PIN(0x3C4, 0x7CC), + MX51_PIN_SD2_DATA3 = _MXC_BUILD_NON_GPIO_PIN(0x3C8, 0x7D0), + MX51_PIN_GPIO1_2 = _MXC_BUILD_GPIO_PIN(0, 2, 0, 0x3CC, 0x7D4), + MX51_PIN_GPIO1_3 = _MXC_BUILD_GPIO_PIN(0, 3, 0, 0x3D0, 0x7D8), + MX51_PIN_PMIC_INT_REQ = _MXC_BUILD_NON_GPIO_PIN(0x3D4, 0x7FC), + MX51_PIN_GPIO1_4 = _MXC_BUILD_GPIO_PIN(0, 4, 0, 0x3D8, 0x804), + MX51_PIN_GPIO1_5 = _MXC_BUILD_GPIO_PIN(0, 5, 0, 0x3DC, 0x808), + MX51_PIN_GPIO1_6 = _MXC_BUILD_GPIO_PIN(0, 6, 0, 0x3E0, 0x80C), + MX51_PIN_GPIO1_7 = _MXC_BUILD_GPIO_PIN(0, 7, 0, 0x3E4, 0x810), + MX51_PIN_GPIO1_8 = _MXC_BUILD_GPIO_PIN(0, 8, 0, 0x3E8, 0x814), + MX51_PIN_GPIO1_9 = _MXC_BUILD_GPIO_PIN(0, 9, 0, 0x3EC, 0x818), +}; + +#endif /* __ASSEMBLY__ */ +#endif /* __ASM_ARCH_MXC_MX51_PINS_H__ */ diff --git a/include/asm-arm/arch-mx51/mxc_nand.h b/include/asm-arm/arch-mx51/mxc_nand.h new file mode 100644 index 0000000000..843f080bc9 --- /dev/null +++ b/include/asm-arm/arch-mx51/mxc_nand.h @@ -0,0 +1,391 @@ +/* + * Copyright 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file mxc_nand.h + * + * @brief This file contains the NAND Flash Controller register information. + * + * + * @ingroup NAND_MTD + */ + +#ifndef __MXC_NAND_H__ +#define __MXC_NAND_H__ + +#include + +#define IS_2K_PAGE_NAND ((mtd->writesize / info->num_of_intlv) \ + == NAND_PAGESIZE_2KB) +#define IS_4K_PAGE_NAND ((mtd->writesize / info->num_of_intlv) \ + == NAND_PAGESIZE_4KB) +#define IS_LARGE_PAGE_NAND ((mtd->writesize / info->num_of_intlv) > 512) + +#define GET_NAND_OOB_SIZE (mtd->oobsize / info->num_of_intlv) +#define GET_NAND_PAGE_SIZE (mtd->writesize / info->num_of_intlv) + +/* + * main area for bad block marker is in the last data section + * the spare area for swapped bad block marker is the second + * byte of last spare section + */ +#define NAND_SECTIONS (GET_NAND_PAGE_SIZE >> 9) +#define NAND_OOB_PER_SECTION (((GET_NAND_OOB_SIZE / NAND_SECTIONS) >> 1) << 1) +#define NAND_CHUNKS (GET_NAND_PAGE_SIZE / (512 + NAND_OOB_PER_SECTION)) + +#define BAD_BLK_MARKER_MAIN_OFFS \ + (GET_NAND_PAGE_SIZE - NAND_CHUNKS * NAND_OOB_PER_SECTION) + +#define BAD_BLK_MARKER_SP_OFFS (NAND_CHUNKS * SPARE_LEN) + +#define BAD_BLK_MARKER_OOB_OFFS (NAND_CHUNKS * NAND_OOB_PER_SECTION) + +#define BAD_BLK_MARKER_MAIN \ + ((u32)MAIN_AREA0 + BAD_BLK_MARKER_MAIN_OFFS) + +#define BAD_BLK_MARKER_SP \ + ((u32)SPARE_AREA0 + BAD_BLK_MARKER_SP_OFFS) + +#define NAND_PAGESIZE_2KB 2048 +#define NAND_PAGESIZE_4KB 4096 + +#define NFC_AXI_BASE_ADDR NFC_BASE_ADDR_AXI +#define NFC_IP_BASE_ADDR NFC_BASE_ADDR +#define MXC_INT_NANDFC MXC_INT_NFC +#define CONFIG_MXC_NFC_SP_AUTO +#define NFC_FLASH_CMD (NFC_AXI_BASE_ADDR + 0x1E00) +#define NFC_FLASH_ADDR0 (NFC_AXI_BASE_ADDR + 0x1E04) +#define NFC_FLASH_ADDR8 (NFC_AXI_BASE_ADDR + 0x1E24) +#define NFC_CONFIG1 (NFC_AXI_BASE_ADDR + 0x1E34) +#define NFC_ECC_STATUS_RESULT (NFC_AXI_BASE_ADDR + 0x1E38) +#define NFC_ECC_STATUS_SUM (NFC_AXI_BASE_ADDR + 0x1E3C) +#define LAUNCH_NFC (NFC_AXI_BASE_ADDR + 0x1E40) +#define NFC_WRPROT (NFC_IP_BASE_ADDR + 0x00) +#define NFC_WRPROT_UNLOCK_BLK_ADD0 (NFC_IP_BASE_ADDR + 0x04) +#define NFC_CONFIG2 (NFC_IP_BASE_ADDR + 0x24) +#define NFC_CONFIG3 (NFC_IP_BASE_ADDR + 0x28) +#define NFC_IPC (NFC_IP_BASE_ADDR + 0x2C) + +/*! + * Addresses for NFC RAM BUFFER Main area 0 + */ +#define MAIN_AREA0 ((u16 *)(NFC_AXI_BASE_ADDR + 0x000)) +#define MAIN_AREA1 ((u16 *)(NFC_AXI_BASE_ADDR + 0x200)) + +/*! + * Addresses for NFC SPARE BUFFER Spare area 0 + */ +#define SPARE_AREA0 ((u16 *)(NFC_AXI_BASE_ADDR + 0x1000)) +#define SPARE_LEN 64 +#define SPARE_COUNT 8 +#define SPARE_SIZE (SPARE_LEN * SPARE_COUNT) + +#define NFC_SPAS_WIDTH 8 +#define NFC_SPAS_SHIFT 16 + +#define IS_4BIT_ECC \ +( \ + is_soc_rev(CHIP_REV_2_0) >= 0 ? \ + !((raw_read(NFC_CONFIG2) & NFC_ECC_MODE_4) >> 6) : \ + ((raw_read(NFC_CONFIG2) & NFC_ECC_MODE_4) >> 6) \ +) + +#define NFC_SET_SPAS(v) \ + raw_write((((raw_read(NFC_CONFIG2) & \ + NFC_FIELD_RESET(NFC_SPAS_WIDTH, NFC_SPAS_SHIFT)) | ((v) << 16))), \ + NFC_CONFIG2) + +#define NFC_SET_ECC_MODE(v) \ +do { \ + if (is_soc_rev(CHIP_REV_2_0) >= 0) { \ + if ((v) == NFC_SPAS_218 || (v) == NFC_SPAS_112) \ + raw_write(((raw_read(NFC_CONFIG2) & \ + NFC_ECC_MODE_MASK) | \ + NFC_ECC_MODE_4), NFC_CONFIG2); \ + else \ + raw_write(((raw_read(NFC_CONFIG2) & \ + NFC_ECC_MODE_MASK) & \ + NFC_ECC_MODE_8), NFC_CONFIG2); \ + } else { \ + if ((v) == NFC_SPAS_218 || (v) == NFC_SPAS_112) \ + raw_write(((raw_read(NFC_CONFIG2) & \ + NFC_ECC_MODE_MASK) & \ + NFC_ECC_MODE_8), NFC_CONFIG2); \ + else \ + raw_write(((raw_read(NFC_CONFIG2) & \ + NFC_ECC_MODE_MASK) | \ + NFC_ECC_MODE_4), NFC_CONFIG2); \ + } \ +} while (0) + +#define WRITE_NFC_IP_REG(val, reg) \ + do { \ + raw_write(NFC_IPC_CREQ, NFC_IPC); \ + while (!((raw_read(NFC_IPC) & NFC_IPC_ACK)>>1)) \ + ; \ + raw_write(val, reg); \ + raw_write(0, NFC_IPC); \ + } while (0) + +#define GET_NFC_ECC_STATUS() raw_read(REG_NFC_ECC_STATUS_RESULT); + +/*! + * Set 1 to specific operation bit, rest to 0 in LAUNCH_NFC Register for + * Specific operation + */ +#define NFC_CMD 0x1 +#define NFC_ADDR 0x2 +#define NFC_INPUT 0x4 +#define NFC_OUTPUT 0x8 +#define NFC_ID 0x10 +#define NFC_STATUS 0x20 +#define NFC_AUTO_PROG 0x40 +#define NFC_AUTO_READ 0x80 +#define NFC_AUTO_ERASE 0x200 +#define NFC_COPY_BACK_0 0x400 +#define NFC_COPY_BACK_1 0x800 +#define NFC_AUTO_STATE 0x1000 + +/* Bit Definitions for NFC_IPC*/ +#define NFC_OPS_STAT (1 << 31) +#define NFC_OP_DONE (1 << 30) +#define NFC_RB (1 << 28) +#define NFC_PS_WIDTH 2 +#define NFC_PS_SHIFT 0 +#define NFC_PS_512 0 +#define NFC_PS_2K 1 +#define NFC_PS_4K 2 + + +#define NFC_ONE_CYCLE (1 << 2) +#define NFC_INT_MSK (1 << 15) +#define NFC_AUTO_PROG_DONE_MSK (1 << 14) +#define NFC_NUM_ADDR_PHASE1_WIDTH 2 +#define NFC_NUM_ADDR_PHASE1_SHIFT 12 +#define NFC_NUM_ADDR_PHASE0_WIDTH 1 +#define NFC_NUM_ADDR_PHASE0_SHIFT 5 +#define NFC_ONE_LESS_PHASE1 0 +#define NFC_TWO_LESS_PHASE1 1 +#define NFC_FLASH_ADDR_SHIFT 0 +#define NFC_UNLOCK_END_ADDR_SHIFT 16 + +/* Bit definition for NFC_CONFIGRATION_1 */ +#define NFC_SP_EN (1 << 0) +#define NFC_CE (1 << 1) +#define NFC_RST (1 << 2) +#define NFC_ECC_EN (1 << 3) + +#define NFC_FIELD_RESET(width, shift) (~(((1 << (width)) - 1) << (shift))) + +#define NFC_RBA_SHIFT 4 +#define NFC_RBA_WIDTH 3 + +#define NFC_ITERATION_SHIFT 8 +#define NFC_ITERATION_WIDTH 4 +#define NFC_ACTIVE_CS_SHIFT 12 +#define NFC_ACTIVE_CS_WIDTH 3 +/* bit definition for CONFIGRATION3 */ +#define NFC_NO_SDMA (1 << 20) +#define NFC_FMP_SHIFT 16 +#define NFC_FMP_WIDTH 4 +#define NFC_RBB_MODE (1 << 15) +#define NFC_NUM_OF_DEVICES_SHIFT 12 +#define NFC_NUM_OF_DEVICES_WIDTH 4 +#define NFC_DMA_MODE_SHIFT 11 +#define NFC_DMA_MODE_WIDTH 1 +#define NFC_SBB_SHIFT 8 +#define NFC_SBB_WIDTH 3 +#define NFC_BIG (1 << 7) +#define NFC_SB2R_SHIFT 4 +#define NFC_SB2R_WIDTH 3 +#define NFC_FW_SHIFT 3 +#define NFC_FW_WIDTH 1 +#define NFC_TOO (1 << 2) +#define NFC_ADD_OP_SHIFT 0 +#define NFC_ADD_OP_WIDTH 2 +#define NFC_FW_8 1 +#define NFC_FW_16 0 +#define NFC_ST_CMD_SHITF 24 +#define NFC_ST_CMD_WIDTH 8 + +#define NFC_PPB_32 (0 << 7) +#define NFC_PPB_64 (1 << 7) +#define NFC_PPB_128 (2 << 7) +#define NFC_PPB_256 (3 << 7) +#define NFC_PPB_RESET (~(3 << 7)) + +#define NFC_BLS_LOCKED (0 << 6) +#define NFC_BLS_LOCKED_DEFAULT (1 << 6) +#define NFC_BLS_UNLCOKED (2 << 6) +#define NFC_BLS_RESET (~(3 << 16)) +#define NFC_WPC_LOCK_TIGHT 1 +#define NFC_WPC_LOCK (1 << 1) +#define NFC_WPC_UNLOCK (1 << 2) +#define NFC_WPC_RESET (~(7)) +#define NFC_ECC_MODE_4 (1 << 6) +#define NFC_ECC_MODE_8 (~(1 << 6)) +#define NFC_ECC_MODE_MASK (~(1 << 6)) +#define NFC_SPAS_16 8 +#define NFC_SPAS_64 32 +#define NFC_SPAS_128 64 +#define NFC_SPAS_112 56 +#define NFC_SPAS_218 109 +#define NFC_IPC_CREQ (1 << 0) +#define NFC_IPC_ACK (1 << 1) + +#define REG_NFC_OPS_STAT NFC_IPC +#define REG_NFC_INTRRUPT NFC_CONFIG2 +#define REG_NFC_FLASH_ADDR NFC_FLASH_ADDR0 +#define REG_NFC_FLASH_CMD NFC_FLASH_CMD +#define REG_NFC_OPS LAUNCH_NFC +#define REG_NFC_SET_RBA NFC_CONFIG1 +#define REG_NFC_RB NFC_IPC +#define REG_NFC_ECC_EN NFC_CONFIG2 +#define REG_NFC_ECC_STATUS_RESULT NFC_ECC_STATUS_RESULT +#define REG_NFC_CE NFC_CONFIG1 +#define REG_NFC_RST NFC_CONFIG1 +#define REG_NFC_PPB NFC_CONFIG2 +#define REG_NFC_SP_EN NFC_CONFIG1 +#define REG_NFC_BLS NFC_WRPROT +#define REG_UNLOCK_BLK_ADD0 NFC_WRPROT_UNLOCK_BLK_ADD0 +#define REG_UNLOCK_BLK_ADD1 NFC_WRPROT_UNLOCK_BLK_ADD1 +#define REG_UNLOCK_BLK_ADD2 NFC_WRPROT_UNLOCK_BLK_ADD2 +#define REG_UNLOCK_BLK_ADD3 NFC_WRPROT_UNLOCK_BLK_ADD3 +#define REG_NFC_WPC NFC_WRPROT +#define REG_NFC_ONE_CYCLE NFC_CONFIG2 + +/* NFC V3 Specific MACRO functions definitions */ +#define raw_write(v, a) __raw_writel(v, a) +#define raw_read(a) __raw_readl(a) + +/* Explcit ack ops status (if any), before issue of any command */ +#define ACK_OPS \ + raw_write((raw_read(REG_NFC_OPS_STAT) & ~NFC_OPS_STAT), \ + REG_NFC_OPS_STAT); + +/* Set RBA buffer id*/ +#define NFC_SET_RBA(val) \ + raw_write((raw_read(REG_NFC_SET_RBA) & \ + (NFC_FIELD_RESET(NFC_RBA_WIDTH, NFC_RBA_SHIFT))) | \ + ((val) << NFC_RBA_SHIFT), REG_NFC_SET_RBA); + +#define NFC_SET_PS(val) \ + raw_write((raw_read(NFC_CONFIG2) & \ + (NFC_FIELD_RESET(NFC_PS_WIDTH, NFC_PS_SHIFT))) | \ + ((val) << NFC_PS_SHIFT), NFC_CONFIG2); + +#define UNLOCK_ADDR(start_addr, end_addr) \ +{ \ + int i = 0; \ + for (; i < NAND_MAX_CHIPS; i++) \ + raw_write(start_addr | \ + (end_addr << NFC_UNLOCK_END_ADDR_SHIFT), \ + REG_UNLOCK_BLK_ADD0 + (i << 2)); \ +} + +#define NFC_SET_NFC_ACTIVE_CS(val) \ + raw_write((raw_read(NFC_CONFIG1) & \ + (NFC_FIELD_RESET(NFC_ACTIVE_CS_WIDTH, NFC_ACTIVE_CS_SHIFT))) | \ + ((val) << NFC_ACTIVE_CS_SHIFT), NFC_CONFIG1); + +#define NFC_GET_MAXCHIP_SP() 8 + +#define NFC_SET_BLS(val) ((raw_read(REG_NFC_BLS) & NFC_BLS_RESET) | val) +#define NFC_SET_WPC(val) ((raw_read(REG_NFC_WPC) & NFC_WPC_RESET) | val) +#define CHECK_NFC_RB (raw_read(REG_NFC_RB) & NFC_RB) + +#define NFC_SET_NFC_NUM_ADDR_PHASE1(val) \ + raw_write((raw_read(NFC_CONFIG2) & \ + (NFC_FIELD_RESET(NFC_NUM_ADDR_PHASE1_WIDTH, \ + NFC_NUM_ADDR_PHASE1_SHIFT))) | \ + ((val) << NFC_NUM_ADDR_PHASE1_SHIFT), NFC_CONFIG2); + +#define NFC_SET_NFC_NUM_ADDR_PHASE0(val) \ + raw_write((raw_read(NFC_CONFIG2) & \ + (NFC_FIELD_RESET(NFC_NUM_ADDR_PHASE0_WIDTH, \ + NFC_NUM_ADDR_PHASE0_SHIFT))) | \ + ((val) << NFC_NUM_ADDR_PHASE0_SHIFT), NFC_CONFIG2); + +#define NFC_SET_NFC_ITERATION(val) \ + raw_write((raw_read(NFC_CONFIG1) & \ + (NFC_FIELD_RESET(NFC_ITERATION_WIDTH, NFC_ITERATION_SHIFT))) | \ + ((val) << NFC_ITERATION_SHIFT), NFC_CONFIG1); + +#define NFC_SET_FW(val) \ + raw_write((raw_read(NFC_CONFIG3) & \ + (NFC_FIELD_RESET(NFC_FW_WIDTH, NFC_FW_SHIFT))) | \ + ((val) << NFC_FW_SHIFT), NFC_CONFIG3); + +#define NFC_SET_NUM_OF_DEVICE(val) \ + raw_write((raw_read(NFC_CONFIG3) & \ + (NFC_FIELD_RESET(NFC_NUM_OF_DEVICES_WIDTH, \ + NFC_NUM_OF_DEVICES_SHIFT))) | \ + ((val) << NFC_NUM_OF_DEVICES_SHIFT), NFC_CONFIG3); + +#define NFC_SET_ADD_OP_MODE(val) \ + raw_write((raw_read(NFC_CONFIG3) & \ + (NFC_FIELD_RESET(NFC_ADD_OP_WIDTH, NFC_ADD_OP_SHIFT))) | \ + ((val) << NFC_ADD_OP_SHIFT), NFC_CONFIG3); + +#define NFC_SET_ADD_CS_MODE(val) \ +{ \ + NFC_SET_ADD_OP_MODE(val); \ + NFC_SET_NUM_OF_DEVICE(this->numchips - 1); \ +} + +#define NFC_SET_ST_CMD(val) \ + raw_write((raw_read(NFC_CONFIG2) & \ + (NFC_FIELD_RESET(NFC_ST_CMD_WIDTH, \ + NFC_ST_CMD_SHITF))) | \ + ((val) << NFC_ST_CMD_SHITF), NFC_CONFIG2); + +#define NFMS_NF_DWIDTH 0 +#define NFMS_NF_PG_SZ 1 +#define NFC_CMD_1_SHIFT 8 + +#define NUM_OF_ADDR_CYCLE ((ffs(~(info->page_mask)) - 1) >> 3) + +/*should set the fw,ps,spas,ppb*/ +#define NFC_SET_NFMS(v) \ +do { \ + if (!(v)) \ + NFC_SET_FW(NFC_FW_8); \ + if (((v) & (1 << NFMS_NF_DWIDTH))) \ + NFC_SET_FW(NFC_FW_16); \ + if (((v) & (1 << NFMS_NF_PG_SZ))) { \ + if (IS_2K_PAGE_NAND) { \ + NFC_SET_PS(NFC_PS_2K); \ + NFC_SET_NFC_NUM_ADDR_PHASE1(NUM_OF_ADDR_CYCLE); \ + NFC_SET_NFC_NUM_ADDR_PHASE0(NFC_TWO_LESS_PHASE1); \ + } else if (IS_4K_PAGE_NAND) { \ + NFC_SET_PS(NFC_PS_4K); \ + NFC_SET_NFC_NUM_ADDR_PHASE1(NUM_OF_ADDR_CYCLE); \ + NFC_SET_NFC_NUM_ADDR_PHASE0(NFC_TWO_LESS_PHASE1); \ + } else { \ + NFC_SET_PS(NFC_PS_512); \ + NFC_SET_NFC_NUM_ADDR_PHASE1(NUM_OF_ADDR_CYCLE - 1); \ + NFC_SET_NFC_NUM_ADDR_PHASE0(NFC_ONE_LESS_PHASE1); \ + } \ + NFC_SET_ADD_CS_MODE(1); \ + NFC_SET_SPAS(GET_NAND_OOB_SIZE >> 1); \ + NFC_SET_ECC_MODE(GET_NAND_OOB_SIZE >> 1); \ + NFC_SET_ST_CMD(0x70); \ + raw_write(raw_read(NFC_CONFIG3) | NFC_NO_SDMA, NFC_CONFIG3); \ + raw_write(raw_read(NFC_CONFIG3) | NFC_RBB_MODE, NFC_CONFIG3); \ + } \ +} while (0) + +#define READ_PAGE() send_read_page(0) +#define PROG_PAGE() send_prog_page(0) + +#endif /* __MXC_NAND_H__ */ diff --git a/include/asm-arm/arch-mx53/iomux.h b/include/asm-arm/arch-mx53/iomux.h new file mode 100644 index 0000000000..21848635b8 --- /dev/null +++ b/include/asm-arm/arch-mx53/iomux.h @@ -0,0 +1,249 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef __MACH_MX53_IOMUX_H__ +#define __MACH_MX53_IOMUX_H__ + +#include +#include +#include +#include + +/*! + * @file mach-mx53/iomux.h + * + * @brief I/O Muxing control definitions and functions + * + * @ingroup GPIO_MX53 + */ + +typedef unsigned int iomux_pin_name_t; + +/*! + * various IOMUX output functions + */ +typedef enum iomux_config { + IOMUX_CONFIG_ALT0, /*!< used as alternate function 0 */ + IOMUX_CONFIG_ALT1, /*!< used as alternate function 1 */ + IOMUX_CONFIG_ALT2, /*!< used as alternate function 2 */ + IOMUX_CONFIG_ALT3, /*!< used as alternate function 3 */ + IOMUX_CONFIG_ALT4, /*!< used as alternate function 4 */ + IOMUX_CONFIG_ALT5, /*!< used as alternate function 5 */ + IOMUX_CONFIG_ALT6, /*!< used as alternate function 6 */ + IOMUX_CONFIG_ALT7, /*!< used as alternate function 7 */ + IOMUX_CONFIG_GPIO, /*!< added to help user use GPIO mode */ + IOMUX_CONFIG_SION = 0x1 << 4, /*!< used as LOOPBACK:MUX SION bit */ +} iomux_pin_cfg_t; + +/*! + * various IOMUX pad functions + */ +typedef enum iomux_pad_config { + PAD_CTL_SRE_SLOW = 0x0 << 0, + PAD_CTL_SRE_FAST = 0x1 << 0, + PAD_CTL_DRV_LOW = 0x0 << 1, + PAD_CTL_DRV_MEDIUM = 0x1 << 1, + PAD_CTL_DRV_HIGH = 0x2 << 1, + PAD_CTL_DRV_MAX = 0x3 << 1, + PAD_CTL_ODE_OPENDRAIN_NONE = 0x0 << 3, + PAD_CTL_ODE_OPENDRAIN_ENABLE = 0x1 << 3, + PAD_CTL_100K_PD = 0x0 << 4, + PAD_CTL_47K_PU = 0x1 << 4, + PAD_CTL_100K_PU = 0x2 << 4, + PAD_CTL_22K_PU = 0x3 << 4, + PAD_CTL_PUE_KEEPER = 0x0 << 6, + PAD_CTL_PUE_PULL = 0x1 << 6, + PAD_CTL_PKE_NONE = 0x0 << 7, + PAD_CTL_PKE_ENABLE = 0x1 << 7, + PAD_CTL_HYS_NONE = 0x0 << 8, + PAD_CTL_HYS_ENABLE = 0x1 << 8, + PAD_CTL_DDR_INPUT_CMOS = 0x0 << 9, + PAD_CTL_DDR_INPUT_DDR = 0x1 << 9, + PAD_CTL_DRV_VOT_LOW = 0x0 << 13, + PAD_CTL_DRV_VOT_HIGH = 0x1 << 13, +} iomux_pad_config_t; + +/*! + * various IOMUX input select register index + */ +typedef enum iomux_input_select { + MUX_IN_AUDMUX_P4_INPUT_DA_AMX_SELECT_I = 0, + MUX_IN_AUDMUX_P4_INPUT_DB_AMX_SELECT_I, + MUX_IN_AUDMUX_P4_INPUT_RXCLK_AMX_SELECT_INPUT, + MUX_IN_AUDMUX_P4_INPUT_RXFS_AMX_SELECT_INPUT, + MUX_IN_AUDMUX_P4_INPUT_TXCLK_AMX_SELECT_INPUT, + MUX_IN_AUDMUX_P4_INPUT_TXFS_AMX_SELECT_INPUT, + MUX_IN_AUDMUX_P5_INPUT_DA_AMX_SELECT_I, + MUX_IN_AUDMUX_P5_INPUT_DB_AMX_SELECT_I, + MUX_IN_AUDMUX_P5_INPUT_RXCLK_AMX_SELECT_INPUT, + MUX_IN_AUDMUX_P5_INPUT_RXFS_AMX_SELECT_INPUT, + MUX_IN_AUDMUX_P5_INPUT_TXCLK_AMX_SELECT_INPUT, + MUX_IN_AUDMUX_P5_INPUT_TXFS_AMX_SELECT_INPUT, + MUX_IN_CAN1_IPP_IND_CANRX_SELECT_INPUT, /*0x760*/ + MUX_IN_CAN2_IPP_IND_CANRX_SELECT_INPUT, + MUX_IN_CCM_IPP_ASRC_EXT_SELECT_INPUT, + MUX_IN_CCM_IPP_DI1_CLK_SELECT_INPUT, + MUX_IN_CCM_PLL1_BYPASS_CLK_SELECT_INPUT, + MUX_IN_CCM_PLL2_BYPASS_CLK_SELECT_INPUT, + MUX_IN_CCM_PLL3_BYPASS_CLK_SELECT_INPUT, + MUX_IN_CCM_PLL4_BYPASS_CLK_SELECT_INPUT, + MUX_IN_CSPI_IPP_CSPI_CLK_IN_SELECT_INPUT, /*0x780*/ + MUX_IN_CSPI_IPP_IND_MISO_SELECT_INPUT, + MUX_IN_CSPI_IPP_IND_MOSI_SELECT_INPUT, + MUX_IN_CSPI_IPP_IND_SS_B_1_SELECT_INPUT, + MUX_IN_CSPI_IPP_IND_SS_B_2_SELECT_INPUT, + MUX_IN_CSPI_IPP_IND_SS_B_3_SELECT_INPUT, + MUX_IN_CSPI_IPP_IND_SS_B_4_SELECT_INPUT, + MUX_IN_ECSPI1_IPP_CSPI_CLK_IN_SELECT_INPUT, + MUX_IN_ECSPI1_IPP_IND_MISO_SELECT_INPUT, + MUX_IN_ECSPI1_IPP_IND_MOSI_SELECT_INPUT, + MUX_IN_ECSPI1_IPP_IND_SS_B_1_SELECT_INPUT, + MUX_IN_ECSPI1_IPP_IND_SS_B_2_SELECT_INPUT, + MUX_IN_ECSPI1_IPP_IND_SS_B_3_SELECT_INPUT, /*0x7B0*/ + MUX_IN_ECSPI1_IPP_IND_SS_B_4_SELECT_INPUT, + MUX_IN_ECSPI2_IPP_CSPI_CLK_IN_SELECT_INPUT, + MUX_IN_ECSPI2_IPP_IND_MISO_SELECT_INPUT, + MUX_IN_ECSPI2_IPP_IND_MOSI_SELECT_INPUT, + MUX_IN_ECSPI2_IPP_IND_SS_B_1_SELECT_INPUT, + MUX_IN_ECSPI2_IPP_IND_SS_B_2_SELECT_INPUT, + MUX_IN_ESAI1_IPP_IND_FSR_SELECT_INPUT, + MUX_IN_ESAI1_IPP_IND_FST_SELECT_INPUT, + MUX_IN_ESAI1_IPP_IND_HCKR_SELECT_INPUT, + MUX_IN_ESAI1_IPP_IND_HCKT_SELECT_INPUT, + MUX_IN_ESAI1_IPP_IND_SCKR_SELECT_INPUT, + MUX_IN_ESAI1_IPP_IND_SCKT_SELECT_INPUT, /*0x7E0*/ + MUX_IN_ESAI1_IPP_IND_SDO0_SELECT_INPUT, + MUX_IN_ESAI1_IPP_IND_SDO1_SELECT_INPUT, + MUX_IN_ESAI1_IPP_IND_SDO2_SDI3_SELECT_INPUT, + MUX_IN_ESAI1_IPP_IND_SDO3_SDI2_SELECT_INPUT, + MUX_IN_ESAI1_IPP_IND_SDO4_SDI1_SELECT_INPUT, + MUX_IN_ESAI1_IPP_IND_SDO5_SDI0_SELECT_INPUT, + MUX_IN_ESDHC1_IPP_WP_ON_SELECT_INPUT, + MUX_IN_FEC_FEC_COL_SELECT_INPUT, /*0x800*/ + MUX_IN_FEC_FEC_MDI_SELECT_INPUT, + MUX_IN_FEC_FEC_RX_CLK_SELECT_INPUT, + MUX_IN_FIRI_IPP_IND_RXD_SELECT_INPUT, + MUX_IN_GPC_PMIC_RDY_SELECT_INPUT, + MUX_IN_I2C1_IPP_SCL_IN_SELECT_INPUT, + MUX_IN_I2C1_IPP_SDA_IN_SELECT_INPUT, + MUX_IN_I2C2_IPP_SCL_IN_SELECT_INPUT, + MUX_IN_I2C2_IPP_SDA_IN_SELECT_INPUT, + MUX_IN_I2C3_IPP_SCL_IN_SELECT_INPUT, + MUX_IN_I2C3_IPP_SDA_IN_SELECT_INPUT, + MUX_IN_IPU_IPP_DI_0_IND_DISPB_SD_D_SELECT_INPUT, + MUX_IN_IPU_IPP_DI_1_IND_DISPB_SD_D_SELECT_INPUT, + MUX_IN_IPU_IPP_IND_SENS1_DATA_EN_SELECT_INPUT, + MUX_IN_IPU_IPP_IND_SENS1_HSYNC_SELECT_INPUT, + MUX_IN_IPU_IPP_IND_SENS1_VSYNC_SELECT_INPUT, + MUX_IN_KPP_IPP_IND_COL_5_SELECT_INPUT, /*0x840*/ + MUX_IN_KPP_IPP_IND_COL_6_SELECT_INPUT, + MUX_IN_KPP_IPP_IND_COL_7_SELECT_INPUT, + MUX_IN_KPP_IPP_IND_ROW_5_SELECT_INPUT, + MUX_IN_KPP_IPP_IND_ROW_6_SELECT_INPUT, + MUX_IN_KPP_IPP_IND_ROW_7_SELECT_INPUT, + MUX_IN_MLB_MLBCLK_IN_SELECT_INPUT, + MUX_IN_MLB_MLBDAT_IN_SELECT_INPUT, + MUX_IN_MLB_MLBSIG_IN_SELECT_INPUT, + MUX_IN_OWIRE_BATTERY_LINE_IN_SELECT_INPUT, + MUX_IN_SDMA_EVENTS_14_SELECT_INPUT, + MUX_IN_SDMA_EVENTS_15_SELECT_INPUT, + MUX_IN_SPDIF_SPDIF_IN1_SELECT_INPUT, /*0x870*/ + MUX_IN_UART1_IPP_UART_RTS_B_SELECT_INPUT, + MUX_IN_UART1_IPP_UART_RXD_MUX_SELECT_INPUT, + MUX_IN_UART2_IPP_UART_RTS_B_SELECT_INPUT, + MUX_IN_UART2_IPP_UART_RXD_MUX_SELECT_INPUT, + MUX_IN_UART3_IPP_UART_RTS_B_SELECT_INPUT, + MUX_IN_UART3_IPP_UART_RXD_MUX_SELECT_INPUT, + MUX_IN_UART4_IPP_UART_RTS_B_SELECT_INPUT, + MUX_IN_UART4_IPP_UART_RXD_MUX_SELECT_INPUT, + MUX_IN_UART5_IPP_UART_RTS_B_SELECT_INPUT, + MUX_IN_UART5_IPP_UART_RXD_MUX_SELECT_INPUT, + MUX_IN_USBOH3_IPP_IND_OTG_OC_SELECT_INPUT, + MUX_IN_USBOH3_IPP_IND_UH1_OC_SELECT_INPUT, + MUX_IN_USBOH3_IPP_IND_UH2_OC_SELECT_INPUT, +} iomux_input_select_t; + +/*! + * various IOMUX input functions + */ +typedef enum iomux_input_config { + INPUT_CTL_PATH0 = 0x0, + INPUT_CTL_PATH1, + INPUT_CTL_PATH2, + INPUT_CTL_PATH3, + INPUT_CTL_PATH4, + INPUT_CTL_PATH5, + INPUT_CTL_PATH6, + INPUT_CTL_PATH7, +} iomux_input_config_t; + +struct mxc_iomux_pin_cfg { + iomux_pin_name_t pin; + u8 mux_mode; + u16 pad_cfg; + u8 in_select; + u8 in_mode; +}; + +/*! + * Request ownership for an IO pin. This function has to be the first one + * being called before that pin is used. The caller has to check the + * return value to make sure it returns 0. + * + * @param pin a name defined by \b iomux_pin_name_t + * @param config config as defined in \b #iomux_pin_ocfg_t + * + * @return 0 if successful; Non-zero otherwise + */ +int mxc_request_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t config); + +/*! + * Release ownership for an IO pin + * + * @param pin a name defined by \b iomux_pin_name_t + * @param config config as defined in \b #iomux_pin_ocfg_t + */ +void mxc_free_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t config); + +/*! + * This function configures the pad value for a IOMUX pin. + * + * @param pin a pin number as defined in \b #iomux_pin_name_t + * @param config the ORed value of elements defined in + * \b #iomux_pad_config_t + */ +void mxc_iomux_set_pad(iomux_pin_name_t pin, u32 config); + +/*! + * This function gets the current pad value for a IOMUX pin. + * + * @param pin a pin number as defined in \b #iomux_pin_name_t + * @return current pad value + */ +unsigned int mxc_iomux_get_pad(iomux_pin_name_t pin); + +/*! + * This function configures input path. + * + * @param input index of input select register as defined in + * \b #iomux_input_select_t + * @param config the binary value of elements defined in \b #iomux_input_config_t + */ +void mxc_iomux_set_input(iomux_input_select_t input, u32 config); + +#endif /* __MACH_MX53_IOMUX_H__ */ diff --git a/include/asm-arm/arch-mx53/mmu.h b/include/asm-arm/arch-mx53/mmu.h new file mode 100644 index 0000000000..5063528965 --- /dev/null +++ b/include/asm-arm/arch-mx53/mmu.h @@ -0,0 +1,174 @@ +/* + * Copyright 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#ifndef __ARM_ARCH_MMU_H +#define __ARM_ARCH_MMU_H + +#include + +/* + * Translation Table Base Bit Masks + */ +#define ARM_TRANSLATION_TABLE_MASK 0xFFFFC000 + +/* + * Domain Access Control Bit Masks + */ +#define ARM_ACCESS_TYPE_NO_ACCESS(domain_num) (0x0 << (domain_num)*2) +#define ARM_ACCESS_TYPE_CLIENT(domain_num) (0x1 << (domain_num)*2) +#define ARM_ACCESS_TYPE_MANAGER(domain_num) (0x3 << (domain_num)*2) + +struct ARM_MMU_FIRST_LEVEL_FAULT { + unsigned int id:2; + unsigned int sbz:30; +}; + +#define ARM_MMU_FIRST_LEVEL_FAULT_ID 0x0 + +struct ARM_MMU_FIRST_LEVEL_PAGE_TABLE { + unsigned int id:2; + unsigned int imp:2; + unsigned int domain:4; + unsigned int sbz:1; + unsigned int base_address:23; +}; + +#define ARM_MMU_FIRST_LEVEL_PAGE_TABLE_ID 0x1 + +struct ARM_MMU_FIRST_LEVEL_SECTION { + unsigned int id:2; + unsigned int b:1; + unsigned int c:1; + unsigned int imp:1; + unsigned int domain:4; + unsigned int sbz0:1; + unsigned int ap:2; + unsigned int sbz1:8; + unsigned int base_address:12; +}; + +#define ARM_MMU_FIRST_LEVEL_SECTION_ID 0x2 + +struct ARM_MMU_FIRST_LEVEL_RESERVED { + unsigned int id:2; + unsigned int sbz:30; +}; + +#define ARM_MMU_FIRST_LEVEL_RESERVED_ID 0x3 + +#define ARM_MMU_FIRST_LEVEL_DESCRIPTOR_ADDRESS(ttb_base, table_index) \ + (unsigned long *)((unsigned long)(ttb_base) + ((table_index) << 2)) + +#define ARM_FIRST_LEVEL_PAGE_TABLE_SIZE 0x4000 + +#define ARM_MMU_SECTION(ttb_base, actual_base, virtual_base, \ + cacheable, bufferable, perm) \ + { \ + register union ARM_MMU_FIRST_LEVEL_DESCRIPTOR desc; \ + desc.word = 0; \ + desc.section.id = ARM_MMU_FIRST_LEVEL_SECTION_ID; \ + desc.section.domain = 0; \ + desc.section.c = (cacheable); \ + desc.section.b = (bufferable); \ + desc.section.ap = (perm); \ + desc.section.base_address = (actual_base); \ + *ARM_MMU_FIRST_LEVEL_DESCRIPTOR_ADDRESS(ttb_base, (virtual_base)) \ + = desc.word; \ + } + +#define X_ARM_MMU_SECTION(abase, vbase, size, cache, buff, access) \ + { \ + int i; int j = abase; int k = vbase; \ + for (i = size; i > 0 ; i--, j++, k++) \ + ARM_MMU_SECTION(ttb_base, j, k, cache, buff, access); \ + } + +union ARM_MMU_FIRST_LEVEL_DESCRIPTOR { + unsigned long word; + struct ARM_MMU_FIRST_LEVEL_FAULT fault; + struct ARM_MMU_FIRST_LEVEL_PAGE_TABLE page_table; + struct ARM_MMU_FIRST_LEVEL_SECTION section; + struct ARM_MMU_FIRST_LEVEL_RESERVED reserved; +}; + +#define ARM_UNCACHEABLE 0 +#define ARM_CACHEABLE 1 +#define ARM_UNBUFFERABLE 0 +#define ARM_BUFFERABLE 1 + +#define ARM_ACCESS_PERM_NONE_NONE 0 +#define ARM_ACCESS_PERM_RO_NONE 0 +#define ARM_ACCESS_PERM_RO_RO 0 +#define ARM_ACCESS_PERM_RW_NONE 1 +#define ARM_ACCESS_PERM_RW_RO 2 +#define ARM_ACCESS_PERM_RW_RW 3 + +/* + * Initialization for the Domain Access Control Register + */ +#define ARM_ACCESS_DACR_DEFAULT ( \ + ARM_ACCESS_TYPE_MANAGER(0) | \ + ARM_ACCESS_TYPE_NO_ACCESS(1) | \ + ARM_ACCESS_TYPE_NO_ACCESS(2) | \ + ARM_ACCESS_TYPE_NO_ACCESS(3) | \ + ARM_ACCESS_TYPE_NO_ACCESS(4) | \ + ARM_ACCESS_TYPE_NO_ACCESS(5) | \ + ARM_ACCESS_TYPE_NO_ACCESS(6) | \ + ARM_ACCESS_TYPE_NO_ACCESS(7) | \ + ARM_ACCESS_TYPE_NO_ACCESS(8) | \ + ARM_ACCESS_TYPE_NO_ACCESS(9) | \ + ARM_ACCESS_TYPE_NO_ACCESS(10) | \ + ARM_ACCESS_TYPE_NO_ACCESS(11) | \ + ARM_ACCESS_TYPE_NO_ACCESS(12) | \ + ARM_ACCESS_TYPE_NO_ACCESS(13) | \ + ARM_ACCESS_TYPE_NO_ACCESS(14) | \ + ARM_ACCESS_TYPE_NO_ACCESS(15)) + +/* + * Translate the virtual address of ram space to physical address + * It is dependent on the implementation of mmu_init + */ +inline unsigned long iomem_to_phys(unsigned long virt) +{ + if (virt >= 0xB0000000) + return (unsigned long)((virt - 0xB0000000) + PHYS_SDRAM_1); + + return (unsigned long)virt; +} + +/* + * remap the physical address of ram space to uncacheable virtual address space + * It is dependent on the implementation of hal_mmu_init + */ +void *__ioremap(unsigned long offset, size_t size, unsigned long flags) +{ + if (1 == flags) { + if (offset >= PHYS_SDRAM_1 && + offset < (unsigned long)(PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE)) + return (void *)((offset - PHYS_SDRAM_1) + 0xB0000000); + else + return NULL; + } else + return (void *)offset; +} + +/* + * Remap the physical address of ram space to uncacheable virtual address space + * It is dependent on the implementation of hal_mmu_init + */ +void __iounmap(void *addr) +{ + return; +} + +#endif diff --git a/include/asm-arm/arch-mx53/mx53.h b/include/asm-arm/arch-mx53/mx53.h new file mode 100644 index 0000000000..ea0487736e --- /dev/null +++ b/include/asm-arm/arch-mx53/mx53.h @@ -0,0 +1,438 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef __ASM_ARCH_MXC_MX53_H__ +#define __ASM_ARCH_MXC_MX53_H__ + +#define __REG(x) (*((volatile u32 *)(x))) +#define __REG16(x) (*((volatile u16 *)(x))) +#define __REG8(x) (*((volatile u8 *)(x))) + +/* + * SATA + */ +#define SATA_BASE_ADDR 0x10000000 + +/* + * IRAM + */ +#define IRAM_BASE_ADDR 0xF8000000 /* internal ram */ +#define IRAM_PARTITIONS 16 +#define IRAM_SIZE (IRAM_PARTITIONS*SZ_8K) /* 128KB */ + +/* + * NFC + */ +#define NFC_BASE_ADDR_AXI 0xF7FF0000 /* NAND flash AXI */ +#define NFC_AXI_SIZE SZ_64K + +#define TZIC_BASE_ADDR 0x0FFFC000 + +#define DEBUG_BASE_ADDR 0x40000000 +#define ETB_BASE_ADDR (DEBUG_BASE_ADDR + 0x00001000) +#define ETM_BASE_ADDR (DEBUG_BASE_ADDR + 0x00002000) +#define TPIU_BASE_ADDR (DEBUG_BASE_ADDR + 0x00003000) +#define CTI0_BASE_ADDR (DEBUG_BASE_ADDR + 0x00004000) +#define CTI1_BASE_ADDR (DEBUG_BASE_ADDR + 0x00005000) +#define CTI2_BASE_ADDR (DEBUG_BASE_ADDR + 0x00006000) +#define CTI3_BASE_ADDR (DEBUG_BASE_ADDR + 0x00007000) +#define CORTEX_DBG_BASE_ADDR (DEBUG_BASE_ADDR + 0x00008000) + +/* + * SPBA global module enabled #0 + */ +#define SPBA0_BASE_ADDR 0x50000000 + +#define MMC_SDHC1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00004000) +#define MMC_SDHC2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00008000) +#define UART3_BASE_ADDR (SPBA0_BASE_ADDR + 0x0000C000) +#define CSPI1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00010000) +#define SSI2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00014000) +#define ESAI_BASE_ADDR (SPBA0_BASE_ADDR + 0x00018000) +#define MMC_SDHC3_BASE_ADDR (SPBA0_BASE_ADDR + 0x00020000) +#define MMC_SDHC4_BASE_ADDR (SPBA0_BASE_ADDR + 0x00024000) +#define SPDIF_BASE_ADDR (SPBA0_BASE_ADDR + 0x00028000) +#define ASRC_BASE_ADDR (SPBA0_BASE_ADDR + 0x0002C000) +#define ATA_DMA_BASE_ADDR (SPBA0_BASE_ADDR + 0x00030000) +#define SPBA_CTRL_BASE_ADDR (SPBA0_BASE_ADDR + 0x0003C000) + +/*! + * defines for SPBA modules + */ +#define SPBA_SDHC1 0x04 +#define SPBA_SDHC2 0x08 +#define SPBA_UART3 0x0C +#define SPBA_CSPI1 0x10 +#define SPBA_SSI2 0x14 +#define SPBA_ESAI 0x18 +#define SPBA_SDHC3 0x20 +#define SPBA_SDHC4 0x24 +#define SPBA_SPDIF 0x28 +#define SPBA_ASRC 0x2C +#define SPBA_ATA 0x30 +#define SPBA_CTRL 0x3C + +/* + * AIPS 1 + */ +#define AIPS1_BASE_ADDR 0x53F00000 + +#define OTG_BASE_ADDR (AIPS1_BASE_ADDR + 0x00080000) +#define GPIO1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00084000) +#define GPIO2_BASE_ADDR (AIPS1_BASE_ADDR + 0x00088000) +#define GPIO3_BASE_ADDR (AIPS1_BASE_ADDR + 0x0008C000) +#define GPIO4_BASE_ADDR (AIPS1_BASE_ADDR + 0x00090000) +#define KPP_BASE_ADDR (AIPS1_BASE_ADDR + 0x00094000) +#define WDOG1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00098000) +#define WDOG2_BASE_ADDR (AIPS1_BASE_ADDR + 0x0009C000) +#define GPT1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A0000) +#define SRTC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A4000) +#define IOMUXC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A8000) +#define EPIT1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000AC000) +#define EPIT2_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B0000) +#define PWM1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B4000) +#define PWM2_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B8000) +#define UART1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000BC000) +#define UART2_BASE_ADDR (AIPS1_BASE_ADDR + 0x000C0000) +#define CAN1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000C8000) +#define CAN2_BASE_ADDR (AIPS1_BASE_ADDR + 0x000CC000) +#define SRC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000D0000) +#define CCM_BASE_ADDR (AIPS1_BASE_ADDR + 0x000D4000) +#define GPC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000D8000) +#define GPIO5_BASE_ADDR (AIPS1_BASE_ADDR + 0x000DC000) +#define GPIO6_BASE_ADDR (AIPS1_BASE_ADDR + 0x000E0000) +#define GPIO7_BASE_ADDR (AIPS1_BASE_ADDR + 0x000E4000) +#define ATA_BASE_ADDR (AIPS1_BASE_ADDR + 0x000E8000) +#define I2C3_BASE_ADDR (AIPS1_BASE_ADDR + 0x000EC000) +#define UART4_BASE_ADDR (AIPS1_BASE_ADDR + 0x000F0000) + +/* + * AIPS 2 + */ +#define AIPS2_BASE_ADDR 0x63F00000 + +#define PLL1_BASE_ADDR (AIPS2_BASE_ADDR + 0x00080000) +#define PLL2_BASE_ADDR (AIPS2_BASE_ADDR + 0x00084000) +#define PLL3_BASE_ADDR (AIPS2_BASE_ADDR + 0x00088000) +#define PLL4_BASE_ADDR (AIPS2_BASE_ADDR + 0x0008C000) +#define UART5_BASE_ADDR (AIPS2_BASE_ADDR + 0x00090000) +#define AHBMAX_BASE_ADDR (AIPS2_BASE_ADDR + 0x00094000) +#define IIM_BASE_ADDR (AIPS2_BASE_ADDR + 0x00098000) +#define CSU_BASE_ADDR (AIPS2_BASE_ADDR + 0x0009C000) +#define ARM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A0000) +#define OWIRE_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A4000) +#define FIRI_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A8000) +#define CSPI2_BASE_ADDR (AIPS2_BASE_ADDR + 0x000AC000) +#define SDMA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000B0000) +#define SCC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000B4000) +#define ROMCP_BASE_ADDR (AIPS2_BASE_ADDR + 0x000B8000) +#define RTIC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000BC000) +#define CSPI3_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C0000) +#define I2C2_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C4000) +#define I2C1_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C8000) +#define SSI1_BASE_ADDR (AIPS2_BASE_ADDR + 0x000CC000) +#define AUDMUX_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D0000) +#define RTC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D4000) +#define M4IF_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D8000) +#define ESDCTL_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D9000) +#define WEIM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DA000) +#define NFC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DB000) +#define EMI_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DBF00) +#define MLB_BASE_ADDR (AIPS2_BASE_ADDR + 0x000E4000) +#define SSI3_BASE_ADDR (AIPS2_BASE_ADDR + 0x000E8000) +#define FEC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000EC000) +#define TVE_BASE_ADDR (AIPS2_BASE_ADDR + 0x000F0000) +#define VPU_BASE_ADDR (AIPS2_BASE_ADDR + 0x000F4000) +#define SAHARA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000F8000) +#define PTP_BASE_ADDR (AIPS2_BASE_ADDR + 0x000FC000) + +/* + * Memory regions and CS + */ +#define CSD0_BASE_ADDR 0x70000000 +#define CSD1_BASE_ADDR 0xB0000000 + +/* + * Interrupt numbers + */ +#define MXC_INT_BASE 0 +#define MXC_INT_RESV0 0 +#define MXC_INT_MMC_SDHC1 1 +#define MXC_INT_MMC_SDHC2 2 +#define MXC_INT_MMC_SDHC3 3 +#define MXC_INT_MMC_SDHC4 4 +#define MXC_INT_DAP 5 +#define MXC_INT_SDMA 6 +#define MXC_INT_IOMUX 7 +#define MXC_INT_NFC 8 +#define MXC_INT_VPU 9 +#define MXC_INT_IPU_ERR 10 +#define MXC_INT_IPU_SYN 11 +#define MXC_INT_GPU 12 +#define MXC_INT_UART4 13 +#define MXC_INT_USB_H1 14 +#define MXC_INT_EMI 15 +#define MXC_INT_USB_H2 16 +#define MXC_INT_USB_H3 17 +#define MXC_INT_USB_OTG 18 +#define MXC_INT_SAHARA_H0 19 +#define MXC_INT_SAHARA_H1 20 +#define MXC_INT_SCC_SMN 21 +#define MXC_INT_SCC_STZ 22 +#define MXC_INT_SCC_SCM 23 +#define MXC_INT_SRTC_NTZ 24 +#define MXC_INT_SRTC_TZ 25 +#define MXC_INT_RTIC 26 +#define MXC_INT_CSU 27 +#define MXC_INT_SATA 28 +#define MXC_INT_SSI1 29 +#define MXC_INT_SSI2 30 +#define MXC_INT_UART1 31 +#define MXC_INT_UART2 32 +#define MXC_INT_UART3 33 +#define MXC_INT_RTC 34 +#define MXC_INT_PTP 35 +#define MXC_INT_CSPI1 36 +#define MXC_INT_CSPI2 37 +#define MXC_INT_CSPI 38 +#define MXC_INT_GPT 39 +#define MXC_INT_EPIT1 40 +#define MXC_INT_EPIT2 41 +#define MXC_INT_GPIO1_INT7 42 +#define MXC_INT_GPIO1_INT6 43 +#define MXC_INT_GPIO1_INT5 44 +#define MXC_INT_GPIO1_INT4 45 +#define MXC_INT_GPIO1_INT3 46 +#define MXC_INT_GPIO1_INT2 47 +#define MXC_INT_GPIO1_INT1 48 +#define MXC_INT_GPIO1_INT0 49 +#define MXC_INT_GPIO1_LOW 50 +#define MXC_INT_GPIO1_HIGH 51 +#define MXC_INT_GPIO2_LOW 52 +#define MXC_INT_GPIO2_HIGH 53 +#define MXC_INT_GPIO3_LOW 54 +#define MXC_INT_GPIO3_HIGH 55 +#define MXC_INT_GPIO4_LOW 56 +#define MXC_INT_GPIO4_HIGH 57 +#define MXC_INT_WDOG1 58 +#define MXC_INT_WDOG2 59 +#define MXC_INT_KPP 60 +#define MXC_INT_PWM1 61 +#define MXC_INT_I2C1 62 +#define MXC_INT_I2C2 63 +#define MXC_INT_I2C3 64 +#define MXC_INT_MLB 65 +#define MXC_INT_ASRC 66 +#define MXC_INT_SPDIF 67 +#define MXC_INT_RESV1 68 +#define MXC_INT_IIM 69 +#define MXC_INT_ATA 70 +#define MXC_INT_CCM1 71 +#define MXC_INT_CCM2 72 +#define MXC_INT_GPC1 73 +#define MXC_INT_GPC2 74 +#define MXC_INT_SRC 75 +#define MXC_INT_NM 76 +#define MXC_INT_PMU 77 +#define MXC_INT_CTI_IRQ 78 +#define MXC_INT_CTI1_TG0 79 +#define MXC_INT_CTI1_TG1 80 +#define MXC_INT_ESAI 81 +#define MXC_INT_CAN1 82 +#define MXC_INT_CAN2 83 +#define MXC_INT_GPU2_IRQ 84 +#define MXC_INT_GPU2_BUSY 85 +#define MXC_INT_UART5 86 +#define MXC_INT_FEC 87 +#define MXC_INT_OWIRE 88 +#define MXC_INT_CTI1_TG2 89 +#define MXC_INT_SJC 90 +#define MXC_INT_RESV2 91 +#define MXC_INT_TVE 92 +#define MXC_INT_FIRI 93 +#define MXC_INT_PWM2 94 +#define MXC_INT_RESV3 95 +#define MXC_INT_SSI3 96 +#define MXC_INT_RESV4 97 +#define MXC_INT_CTI1_TG3 98 +#define MXC_INT_RESV5 99 +#define MXC_INT_VPU_IDLE 100 +#define MXC_INT_EMI_NFC 101 +#define MXC_INT_GPU_IDLE 102 +#define MXC_INT_GPIO5_LOW 103 +#define MXC_INT_GPIO5_HIGH 104 +#define MXC_INT_GPIO6_LOW 105 +#define MXC_INT_GPIO6_HIGH 106 +#define MXC_INT_GPIO7_LOW 107 +#define MXC_INT_GPIO7_HIGH 108 + +/* gpio and gpio based interrupt handling */ +#define GPIO_DR 0x00 +#define GPIO_GDIR 0x04 +#define GPIO_PSR 0x08 +#define GPIO_ICR1 0x0C +#define GPIO_ICR2 0x10 +#define GPIO_IMR 0x14 +#define GPIO_ISR 0x18 +#define GPIO_INT_LOW_LEV 0x0 +#define GPIO_INT_HIGH_LEV 0x1 +#define GPIO_INT_RISE_EDGE 0x2 +#define GPIO_INT_FALL_EDGE 0x3 +#define GPIO_INT_NONE 0x4 + +#define CLKCTL_CCR 0x00 +#define CLKCTL_CCDR 0x04 +#define CLKCTL_CSR 0x08 +#define CLKCTL_CCSR 0x0C +#define CLKCTL_CACRR 0x10 +#define CLKCTL_CBCDR 0x14 +#define CLKCTL_CBCMR 0x18 +#define CLKCTL_CSCMR1 0x1C +#define CLKCTL_CSCMR2 0x20 +#define CLKCTL_CSCDR1 0x24 +#define CLKCTL_CS1CDR 0x28 +#define CLKCTL_CS2CDR 0x2C +#define CLKCTL_CDCDR 0x30 +#define CLKCTL_CHSCDR 0x34 +#define CLKCTL_CSCDR2 0x38 +#define CLKCTL_CSCDR3 0x3C +#define CLKCTL_CSCDR4 0x40 +#define CLKCTL_CWDR 0x44 +#define CLKCTL_CDHIPR 0x48 +#define CLKCTL_CDCR 0x4C +#define CLKCTL_CTOR 0x50 +#define CLKCTL_CLPCR 0x54 +#define CLKCTL_CISR 0x58 +#define CLKCTL_CIMR 0x5C +#define CLKCTL_CCOSR 0x60 +#define CLKCTL_CGPR 0x64 +#define CLKCTL_CCGR0 0x68 +#define CLKCTL_CCGR1 0x6C +#define CLKCTL_CCGR2 0x70 +#define CLKCTL_CCGR3 0x74 +#define CLKCTL_CCGR4 0x78 +#define CLKCTL_CCGR5 0x7C +#define CLKCTL_CCGR6 0x80 +#define CLKCTL_CCGR7 0x84 +#define CLKCTL_CMEOR 0x88 + +#define CHIP_REV_1_0 0x10 +#define PLATFORM_ICGC 0x14 + +/* Assuming 24MHz input clock with doubler ON */ +/* MFI PDF */ +#define DP_OP_850 ((8 << 4) + ((1 - 1) << 0)) +#define DP_MFD_850 (48 - 1) +#define DP_MFN_850 41 + +#define DP_OP_800 ((8 << 4) + ((1 - 1) << 0)) +#define DP_MFD_800 (3 - 1) +#define DP_MFN_800 1 + +#define DP_OP_700 ((7 << 4) + ((1 - 1) << 0)) +#define DP_MFD_700 (24 - 1) +#define DP_MFN_700 7 + +#define DP_OP_600 ((6 << 4) + ((1 - 1) << 0)) +#define DP_MFD_600 (4 - 1) +#define DP_MFN_600 1 + +#define DP_OP_665 ((6 << 4) + ((1 - 1) << 0)) +#define DP_MFD_665 (96 - 1) +#define DP_MFN_665 89 + +#define DP_OP_532 ((5 << 4) + ((1 - 1) << 0)) +#define DP_MFD_532 (24 - 1) +#define DP_MFN_532 13 + +#define DP_OP_400 ((8 << 4) + ((2 - 1) << 0)) +#define DP_MFD_400 (3 - 1) +#define DP_MFN_400 1 + +#define DP_OP_216 ((6 << 4) + ((3 - 1) << 0)) +#define DP_MFD_216 (4 - 1) +#define DP_MFN_216 3 + +#define PLL_DP_CTL 0x00 +#define PLL_DP_CONFIG 0x04 +#define PLL_DP_OP 0x08 +#define PLL_DP_MFD 0x0C +#define PLL_DP_MFN 0x10 +#define PLL_DP_MFNMINUS 0x14 +#define PLL_DP_MFNPLUS 0x18 +#define PLL_DP_HFS_OP 0x1C +#define PLL_DP_HFS_MFD 0x20 +#define PLL_DP_HFS_MFN 0x24 +#define PLL_DP_TOGC 0x28 +#define PLL_DP_DESTAT 0x2C + +#ifndef __ASSEMBLER__ + +enum boot_device { + WEIM_NOR_BOOT, + ONE_NAND_BOOT, + PATA_BOOT, + SATA_BOOT, + I2C_BOOT, + SPI_NOR_BOOT, + SD_BOOT, + MMC_BOOT, + NAND_BOOT, + UNKNOWN_BOOT +}; + +enum mxc_clock { + MXC_ARM_CLK = 0, + MXC_PER_CLK, + MXC_AHB_CLK, + MXC_IPG_CLK, + MXC_IPG_PERCLK, + MXC_UART_CLK, + MXC_CSPI_CLK, + MXC_AXI_A_CLK, + MXC_AXI_B_CLK, + MXC_EMI_SLOW_CLK, + MXC_DDR_CLK, + MXC_ESDHC_CLK, + MXC_ESDHC2_CLK, + MXC_ESDHC3_CLK, + MXC_ESDHC4_CLK, + MXC_SATA_CLK +}; + +enum mxc_peri_clocks { + MXC_UART1_BAUD, + MXC_UART2_BAUD, + MXC_UART3_BAUD, + MXC_SSI1_BAUD, + MXC_SSI2_BAUD, + MXC_CSI_BAUD, + MXC_MSTICK1_CLK, + MXC_MSTICK2_CLK, + MXC_SPI1_CLK, + MXC_SPI2_CLK, +}; + +extern unsigned int mxc_get_clock(enum mxc_clock clk); +extern unsigned int get_board_rev(void); +extern int is_soc_rev(int rev); +extern enum boot_device get_boot_device(void); + +#endif /* __ASSEMBLER__*/ + +#endif /* __ASM_ARCH_MXC_MX53_H__ */ diff --git a/include/asm-arm/arch-mx53/mx53_pins.h b/include/asm-arm/arch-mx53/mx53_pins.h new file mode 100644 index 0000000000..e5afcd73bd --- /dev/null +++ b/include/asm-arm/arch-mx53/mx53_pins.h @@ -0,0 +1,374 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ +#ifndef __ASM_ARCH_MXC_MX53_PINS_H__ +#define __ASM_ARCH_MXC_MX53_PINS_H__ + +/*! + * @file arch-mxc/mx53_pins.h + * + * @brief MX53 I/O Pin List + * + * @ingroup GPIO_MX53 + */ + +#ifndef __ASSEMBLY__ + +/*! + * @name IOMUX/PAD Bit field definitions + */ + +/*! @{ */ + +/*! + * In order to identify pins more effectively, each mux-controlled pin's + * enumerated value is constructed in the following way: + * + * ------------------------------------------------------------------- + * 31-29 | 28 - 24 | 23 - 21 | 20 - 10| 9 - 0 + * ------------------------------------------------------------------- + * IO_P | IO_I | GPIO_I | PAD_I | MUX_I + * ------------------------------------------------------------------- + * + * Bit 0 to 9 contains MUX_I used to identify the register + * offset (0-based. base is IOMUX_module_base) defined in the Section + * "sw_pad_ctl & sw_mux_ctl details" of the IC Spec. The + * similar field definitions are used for the pad control register. + * For example, the MX53_PIN_GPIO_19 is defined in the enumeration: + * ( (0x20 - MUX_I_START) << MUX_I)|( (0x348 - PAD_I_START) << PAD_I) + * It means the mux control register is at register offset 0x20. The pad control + * register offset is: 0x348 and also occupy the least significant bits + * within the register. + */ + +/*! + * Starting bit position within each entry of \b iomux_pins to represent the + * MUX control register offset + */ +#define MUX_I 0 +/*! + * Starting bit position within each entry of \b iomux_pins to represent the + * PAD control register offset + */ +#define PAD_I 10 +/*! + * Starting bit position within each entry of \b iomux_pins to represent which + * mux mode is for GPIO (0-based) + */ +#define GPIO_I 21 + +#define MUX_IO_P 29 +#define MUX_IO_I 24 + +#define NON_GPIO_PORT 0x7 +#define PIN_TO_MUX_MASK ((1 << (PAD_I - MUX_I)) - 1) +#define PIN_TO_PAD_MASK ((1 << (GPIO_I - PAD_I)) - 1) +#define PIN_TO_ALT_GPIO_MASK ((1 << (MUX_IO_I - GPIO_I)) - 1) + +#define NON_MUX_I PIN_TO_MUX_MASK +#define NON_PAD_I PIN_TO_PAD_MASK +#define MUX_I_START 0x0020 +#define PAD_I_START 0x348 +#define INPUT_CTL_START 0x730 +#define MUX_I_END (PAD_I_START - 4) + +#define _MXC_BUILD_PIN(gp, gi, ga, mi, pi) \ + (((gp) << MUX_IO_P) | ((gi) << MUX_IO_I) | \ + ((mi) << MUX_I) | \ + ((pi - PAD_I_START) << PAD_I) | \ + ((ga) << GPIO_I)) + +#define _MXC_BUILD_GPIO_PIN(gp, gi, ga, mi, pi) \ + _MXC_BUILD_PIN(gp, gi, ga, mi, pi) + +#define _MXC_BUILD_NON_GPIO_PIN(mi, pi) \ + _MXC_BUILD_PIN(NON_GPIO_PORT, 0, 0, mi, pi) + +#define PIN_TO_IOMUX_MUX(pin) ((pin >> MUX_I) & PIN_TO_MUX_MASK) +#define PIN_TO_IOMUX_PAD(pin) ((pin >> PAD_I) & PIN_TO_PAD_MASK) +#define PIN_TO_ALT_GPIO(pin) ((pin >> GPIO_I) & PIN_TO_ALT_GPIO_MASK) +#define PIN_TO_IOMUX_INDEX(pin) (PIN_TO_IOMUX_MUX(pin) >> 2) + +/*! @} End IOMUX/PAD Bit field definitions */ + +/*! + * This enumeration is constructed based on the Section + * "sw_pad_ctl & sw_mux_ctl details" of the MX53 IC Spec. Each enumerated + * value is constructed based on the rules described above. + */ +enum iomux_pins { + MX53_PIN_GPIO_19 = _MXC_BUILD_GPIO_PIN(3, 5, 1, 0x20, 0x348), + MX53_PIN_KEY_COL0 = _MXC_BUILD_GPIO_PIN(3, 6, 1, 0x24, 0x34C), + MX53_PIN_KEY_ROW0 = _MXC_BUILD_GPIO_PIN(3, 7, 1, 0x28, 0x350), + MX53_PIN_KEY_COL1 = _MXC_BUILD_GPIO_PIN(3, 8, 1, 0x2C, 0x354), + MX53_PIN_KEY_ROW1 = _MXC_BUILD_GPIO_PIN(3, 9, 1, 0x30, 0x358), + MX53_PIN_KEY_COL2 = _MXC_BUILD_GPIO_PIN(3, 10, 1, 0x34, 0x35C), + MX53_PIN_KEY_ROW2 = _MXC_BUILD_GPIO_PIN(3, 11, 1, 0x38, 0x360), + MX53_PIN_KEY_COL3 = _MXC_BUILD_GPIO_PIN(3, 12, 1, 0x3C, 0x364), + MX53_PIN_KEY_ROW3 = _MXC_BUILD_GPIO_PIN(3, 13, 1, 0x40, 0x368), + MX53_PIN_KEY_COL4 = _MXC_BUILD_GPIO_PIN(3, 14, 1, 0x44, 0x36C), + MX53_PIN_KEY_ROW4 = _MXC_BUILD_GPIO_PIN(3, 15, 1, 0x48, 0x370), + MX53_PIN_NVCC_KEYPAD = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x374), + MX53_PIN_DI0_DISP_CLK = _MXC_BUILD_GPIO_PIN(3, 16, 1, 0x4C, 0x378), + MX53_PIN_DI0_PIN15 = _MXC_BUILD_GPIO_PIN(3, 17, 1, 0x50, 0x37C), + MX53_PIN_DI0_PIN2 = _MXC_BUILD_GPIO_PIN(3, 18, 1, 0x54, 0x380), + MX53_PIN_DI0_PIN3 = _MXC_BUILD_GPIO_PIN(3, 19, 1, 0x58, 0x384), + MX53_PIN_DI0_PIN4 = _MXC_BUILD_GPIO_PIN(3, 20, 1, 0x5C, 0x388), + MX53_PIN_DISP0_DAT0 = _MXC_BUILD_GPIO_PIN(3, 21, 1, 0x60, 0x38C), + MX53_PIN_DISP0_DAT1 = _MXC_BUILD_GPIO_PIN(3, 22, 1, 0x64, 0x390), + MX53_PIN_DISP0_DAT2 = _MXC_BUILD_GPIO_PIN(3, 23, 1, 0x68, 0x394), + MX53_PIN_DISP0_DAT3 = _MXC_BUILD_GPIO_PIN(3, 24, 1, 0x6C, 0x398), + MX53_PIN_DISP0_DAT4 = _MXC_BUILD_GPIO_PIN(3, 25, 1, 0x70, 0x39C), + MX53_PIN_DISP0_DAT5 = _MXC_BUILD_GPIO_PIN(3, 26, 1, 0x74, 0x3A0), + MX53_PIN_DISP0_DAT6 = _MXC_BUILD_GPIO_PIN(3, 27, 1, 0x78, 0x3A4), + MX53_PIN_DISP0_DAT7 = _MXC_BUILD_GPIO_PIN(3, 28, 1, 0x7C, 0x3A8), + MX53_PIN_DISP0_DAT8 = _MXC_BUILD_GPIO_PIN(3, 29, 1, 0x80, 0x3AC), + MX53_PIN_DISP0_DAT9 = _MXC_BUILD_GPIO_PIN(3, 30, 1, 0x84, 0x3B0), + MX53_PIN_DISP0_DAT10 = _MXC_BUILD_GPIO_PIN(3, 31, 1, 0x88, 0x3B4), + MX53_PIN_DISP0_DAT11 = _MXC_BUILD_GPIO_PIN(4, 5, 1, 0x8C, 0x3B8), + MX53_PIN_DISP0_DAT12 = _MXC_BUILD_GPIO_PIN(4, 6, 1, 0x90, 0x3BC), + MX53_PIN_DISP0_DAT13 = _MXC_BUILD_GPIO_PIN(4, 7, 1, 0x94, 0x3C0), + MX53_PIN_DISP0_DAT14 = _MXC_BUILD_GPIO_PIN(4, 8, 1, 0x98, 0x3C4), + MX53_PIN_DISP0_DAT15 = _MXC_BUILD_GPIO_PIN(4, 9, 1, 0x9C, 0x3C8), + MX53_PIN_DISP0_DAT16 = _MXC_BUILD_GPIO_PIN(4, 10, 1, 0xA0, 0x3CC), + MX53_PIN_DISP0_DAT17 = _MXC_BUILD_GPIO_PIN(4, 11, 1, 0xA4, 0x3D0), + MX53_PIN_DISP0_DAT18 = _MXC_BUILD_GPIO_PIN(4, 12, 1, 0xA8, 0x3D4), + MX53_PIN_DISP0_DAT19 = _MXC_BUILD_GPIO_PIN(4, 13, 1, 0xAC, 0x3D8), + MX53_PIN_DISP0_DAT20 = _MXC_BUILD_GPIO_PIN(4, 14, 1, 0xB0, 0x3DC), + MX53_PIN_DISP0_DAT21 = _MXC_BUILD_GPIO_PIN(4, 15, 1, 0xB4, 0x3E0), + MX53_PIN_DISP0_DAT22 = _MXC_BUILD_GPIO_PIN(4, 16, 1, 0xB8, 0x3E4), + MX53_PIN_DISP0_DAT23 = _MXC_BUILD_GPIO_PIN(4, 17, 1, 0xBC, 0x3E8), + MX53_PIN_CSI0_PIXCLK = _MXC_BUILD_GPIO_PIN(4, 18, 1, 0xC0, 0x3EC), + MX53_PIN_CSI0_MCLK = _MXC_BUILD_GPIO_PIN(4, 19, 1, 0xC4, 0x3F0), + MX53_PIN_CSI0_DATA_EN = _MXC_BUILD_GPIO_PIN(4, 20, 1, 0xC8, 0x3F4), + MX53_PIN_CSI0_VSYNC = _MXC_BUILD_GPIO_PIN(4, 21, 1, 0xCC, 0x3F8), + MX53_PIN_CSI0_D4 = _MXC_BUILD_GPIO_PIN(4, 22, 1, 0xD0, 0x3FC), + MX53_PIN_CSI0_D5 = _MXC_BUILD_GPIO_PIN(4, 23, 1, 0xD4, 0x400), + MX53_PIN_CSI0_D6 = _MXC_BUILD_GPIO_PIN(4, 24, 1, 0xD8, 0x404), + MX53_PIN_CSI0_D7 = _MXC_BUILD_GPIO_PIN(4, 25, 1, 0xDC, 0x408), + MX53_PIN_CSI0_D8 = _MXC_BUILD_GPIO_PIN(4, 26, 1, 0xE0, 0x40C), + MX53_PIN_CSI0_D9 = _MXC_BUILD_GPIO_PIN(4, 27, 1, 0xE4, 0x410), + MX53_PIN_CSI0_D10 = _MXC_BUILD_GPIO_PIN(4, 28, 1, 0xE8, 0x414), + MX53_PIN_CSI0_D11 = _MXC_BUILD_GPIO_PIN(4, 29, 1, 0xEC, 0x418), + MX53_PIN_CSI0_D12 = _MXC_BUILD_GPIO_PIN(4, 30, 1, 0xF0, 0x41C), + MX53_PIN_CSI0_D13 = _MXC_BUILD_GPIO_PIN(4, 31, 1, 0xF4, 0x420), + MX53_PIN_CSI0_D14 = _MXC_BUILD_GPIO_PIN(5, 0, 1, 0xF8, 0x424), + MX53_PIN_CSI0_D15 = _MXC_BUILD_GPIO_PIN(5, 1, 1, 0xFC, 0x428), + MX53_PIN_CSI0_D16 = _MXC_BUILD_GPIO_PIN(5, 2, 1, 0x100, 0x42C), + MX53_PIN_CSI0_D17 = _MXC_BUILD_GPIO_PIN(5, 3, 1, 0x104, 0x430), + MX53_PIN_CSI0_D18 = _MXC_BUILD_GPIO_PIN(5, 4, 1, 0x108, 0x434), + MX53_PIN_CSI0_D19 = _MXC_BUILD_GPIO_PIN(5, 5, 1, 0x10C, 0x438), + MX53_PIN_NVCC_CSI0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x43C), + MX53_PIN_JTAG_TMS = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x440), + MX53_PIN_JTAG_MOD = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x444), + MX53_PIN_JTAG_TRSTB = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x448), + MX53_PIN_JTAG_TDI = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x44C), + MX53_PIN_JTAG_TCK = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x450), + MX53_PIN_JTAG_TDO = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x454), + MX53_PIN_EIM_A25 = _MXC_BUILD_GPIO_PIN(4, 2, 1, 0x110, 0x458), + MX53_PIN_EIM_EB2 = _MXC_BUILD_GPIO_PIN(1, 30, 1, 0x114, 0x45C), + MX53_PIN_EIM_D16 = _MXC_BUILD_GPIO_PIN(2, 16, 1, 0x118, 0x460), + MX53_PIN_EIM_D17 = _MXC_BUILD_GPIO_PIN(2, 17, 1, 0x11C, 0x464), + MX53_PIN_EIM_D18 = _MXC_BUILD_GPIO_PIN(2, 18, 1, 0x120, 0x468), + MX53_PIN_EIM_D19 = _MXC_BUILD_GPIO_PIN(2, 19, 1, 0x124, 0x46C), + MX53_PIN_EIM_D20 = _MXC_BUILD_GPIO_PIN(2, 20, 1, 0x128, 0x470), + MX53_PIN_EIM_D21 = _MXC_BUILD_GPIO_PIN(2, 21, 1, 0x12C, 0x474), + MX53_PIN_EIM_D22 = _MXC_BUILD_GPIO_PIN(2, 22, 1, 0x130, 0x478), + MX53_PIN_EIM_D23 = _MXC_BUILD_GPIO_PIN(2, 23, 1, 0x134, 0x47C), + MX53_PIN_EIM_EB3 = _MXC_BUILD_GPIO_PIN(1, 31, 1, 0x138, 0x480), + MX53_PIN_EIM_D24 = _MXC_BUILD_GPIO_PIN(2, 24, 1, 0x13C, 0x484), + MX53_PIN_EIM_D25 = _MXC_BUILD_GPIO_PIN(2, 25, 1, 0x140, 0x488), + MX53_PIN_EIM_D26 = _MXC_BUILD_GPIO_PIN(2, 26, 1, 0x144, 0x48C), + MX53_PIN_EIM_D27 = _MXC_BUILD_GPIO_PIN(2, 27, 1, 0x148, 0x490), + MX53_PIN_EIM_D28 = _MXC_BUILD_GPIO_PIN(2, 28, 1, 0x14C, 0x494), + MX53_PIN_EIM_D29 = _MXC_BUILD_GPIO_PIN(2, 29, 1, 0x150, 0x498), + MX53_PIN_EIM_D30 = _MXC_BUILD_GPIO_PIN(2, 30, 1, 0x154, 0x49C), + MX53_PIN_EIM_D31 = _MXC_BUILD_GPIO_PIN(2, 31, 1, 0x158, 0x4A0), + MX53_PIN_NVCC_EIM1 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x4A4), + MX53_PIN_EIM_A24 = _MXC_BUILD_GPIO_PIN(4, 4, 1, 0x15C, 0x4A8), + MX53_PIN_EIM_A23 = _MXC_BUILD_GPIO_PIN(5, 6, 1, 0x160, 0x4AC), + MX53_PIN_EIM_A22 = _MXC_BUILD_GPIO_PIN(1, 16, 1, 0x164, 0x4B0), + MX53_PIN_EIM_A21 = _MXC_BUILD_GPIO_PIN(1, 17, 1, 0x168, 0x4B4), + MX53_PIN_EIM_A20 = _MXC_BUILD_GPIO_PIN(1, 18, 1, 0x16C, 0x4B8), + MX53_PIN_EIM_A19 = _MXC_BUILD_GPIO_PIN(1, 19, 1, 0x170, 0x4BC), + MX53_PIN_EIM_A18 = _MXC_BUILD_GPIO_PIN(1, 20, 1, 0x174, 0x4C0), + MX53_PIN_EIM_A17 = _MXC_BUILD_GPIO_PIN(1, 21, 1, 0x178, 0x4C4), + MX53_PIN_EIM_A16 = _MXC_BUILD_GPIO_PIN(1, 22, 1, 0x17C, 0x4C8), + MX53_PIN_EIM_CS0 = _MXC_BUILD_GPIO_PIN(1, 23, 1, 0x180, 0x4CC), + MX53_PIN_EIM_CS1 = _MXC_BUILD_GPIO_PIN(1, 24, 1, 0x184, 0x4D0), + MX53_PIN_EIM_OE = _MXC_BUILD_GPIO_PIN(1, 25, 1, 0x188, 0x4D4), + MX53_PIN_EIM_RW = _MXC_BUILD_GPIO_PIN(1, 26, 1, 0x18C, 0x4D8), + MX53_PIN_EIM_LBA = _MXC_BUILD_GPIO_PIN(1, 27, 1, 0x190, 0x4DC), + MX53_PIN_NVCC_EIM4 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x4E0), + MX53_PIN_EIM_EB0 = _MXC_BUILD_GPIO_PIN(1, 28, 1, 0x194, 0x4E4), + MX53_PIN_EIM_EB1 = _MXC_BUILD_GPIO_PIN(1, 29, 1, 0x198, 0x4E8), + MX53_PIN_EIM_DA0 = _MXC_BUILD_GPIO_PIN(2, 0, 1, 0x19C, 0x4EC), + MX53_PIN_EIM_DA1 = _MXC_BUILD_GPIO_PIN(2, 1, 1, 0x1A0, 0x4F0), + MX53_PIN_EIM_DA2 = _MXC_BUILD_GPIO_PIN(2, 2, 1, 0x1A4, 0x4F4), + MX53_PIN_EIM_DA3 = _MXC_BUILD_GPIO_PIN(2, 3, 1, 0x1A8, 0x4F8), + MX53_PIN_EIM_DA4 = _MXC_BUILD_GPIO_PIN(2, 4, 1, 0x1AC, 0x4FC), + MX53_PIN_EIM_DA5 = _MXC_BUILD_GPIO_PIN(2, 5, 1, 0x1B0, 0x500), + MX53_PIN_EIM_DA6 = _MXC_BUILD_GPIO_PIN(2, 6, 1, 0x1B4, 0x504), + MX53_PIN_EIM_DA7 = _MXC_BUILD_GPIO_PIN(2, 7, 1, 0x1B8, 0x508), + MX53_PIN_EIM_DA8 = _MXC_BUILD_GPIO_PIN(2, 8, 1, 0x1BC, 0x50C), + MX53_PIN_EIM_DA9 = _MXC_BUILD_GPIO_PIN(2, 9, 1, 0x1C0, 0x510), + MX53_PIN_EIM_DA10 = _MXC_BUILD_GPIO_PIN(2, 10, 1, 0x1C4, 0x514), + MX53_PIN_EIM_DA11 = _MXC_BUILD_GPIO_PIN(2, 11, 1, 0x1C8, 0x518), + MX53_PIN_EIM_DA12 = _MXC_BUILD_GPIO_PIN(2, 12, 1, 0x1CC, 0x51C), + MX53_PIN_EIM_DA13 = _MXC_BUILD_GPIO_PIN(2, 13, 1, 0x1D0, 0x520), + MX53_PIN_EIM_DA14 = _MXC_BUILD_GPIO_PIN(2, 14, 1, 0x1D4, 0x524), + MX53_PIN_EIM_DA15 = _MXC_BUILD_GPIO_PIN(2, 15, 1, 0x1D8, 0x528), + MX53_PIN_NANDF_WE_B = _MXC_BUILD_GPIO_PIN(5, 12, 1, 0x1DC, 0x52C), + MX53_PIN_NANDF_RE_B = _MXC_BUILD_GPIO_PIN(5, 13, 1, 0x1E0, 0x530), + MX53_PIN_EIM_WAIT = _MXC_BUILD_GPIO_PIN(4, 0, 1, 0x1E4, 0x534), + MX53_PIN_EIM_BCLK = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x538), + MX53_PIN_NVCC_EIM7 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x53C), + MX53_PIN_LVDS1_TX3_P = _MXC_BUILD_GPIO_PIN(5, 22, 0, 0x1EC, NON_PAD_I), + MX53_PIN_LVDS1_TX2_P = _MXC_BUILD_GPIO_PIN(5, 24, 0, 0x1F0, NON_PAD_I), + MX53_PIN_LVDS1_CLK_P = _MXC_BUILD_GPIO_PIN(5, 26, 0, 0x1F4, NON_PAD_I), + MX53_PIN_LVDS1_TX1_P = _MXC_BUILD_GPIO_PIN(5, 28, 0, 0x1F8, NON_PAD_I), + MX53_PIN_LVDS1_TX0_P = _MXC_BUILD_GPIO_PIN(5, 30, 0, 0x1FC, NON_PAD_I), + MX53_PIN_LVDS0_TX3_P = _MXC_BUILD_GPIO_PIN(6, 22, 0, 0x200, NON_PAD_I), + MX53_PIN_LVDS0_CLK_P = _MXC_BUILD_GPIO_PIN(6, 24, 0, 0x204, NON_PAD_I), + MX53_PIN_LVDS0_TX2_P = _MXC_BUILD_GPIO_PIN(6, 26, 0, 0x208, NON_PAD_I), + MX53_PIN_LVDS0_TX1_P = _MXC_BUILD_GPIO_PIN(6, 28, 0, 0x20C, NON_PAD_I), + MX53_PIN_LVDS0_TX0_P = _MXC_BUILD_GPIO_PIN(6, 30, 0, 0x210, NON_PAD_I), + MX53_PIN_GPIO_10 = _MXC_BUILD_GPIO_PIN(3, 0, 0, 0x214, 0x540), + MX53_PIN_GPIO_11 = _MXC_BUILD_GPIO_PIN(3, 1, 0, 0x218, 0x544), + MX53_PIN_GPIO_12 = _MXC_BUILD_GPIO_PIN(3, 2, 0, 0x21C, 0x548), + MX53_PIN_GPIO_13 = _MXC_BUILD_GPIO_PIN(3, 3, 0, 0x220, 0x54C), + MX53_PIN_GPIO_14 = _MXC_BUILD_GPIO_PIN(3, 4, 0, 0x224, 0x550), + MX53_PIN_DRAM_DQM3 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x554), + MX53_PIN_DRAM_SDQS3 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x558), + MX53_PIN_DRAM_SDCKE1 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x55C), + MX53_PIN_DRAM_DQM2 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x560), + MX53_PIN_DRAM_SDODT1 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x564), + MX53_PIN_DRAM_SDQS2 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x568), + MX53_PIN_DRAM_RESET = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x56C), + MX53_PIN_DRAM_SDCLK1 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x570), + MX53_PIN_DRAM_CAS = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x574), + MX53_PIN_DRAM_SDCLK0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x578), + MX53_PIN_DRAM_SDQS0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x57C), + MX53_PIN_DRAM_SDODT0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x580), + MX53_PIN_DRAM_DQM0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x584), + MX53_PIN_DRAM_RAS = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x588), + MX53_PIN_DRAM_SDCKE0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x58C), + MX53_PIN_DRAM_SDQS1 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x590), + MX53_PIN_DRAM_DQM1 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x594), + MX53_PIN_PMIC_ON_REQ = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x598), + MX53_PIN_PMIC_STBY_REQ = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x59C), + MX53_PIN_NANDF_CLE = _MXC_BUILD_GPIO_PIN(5, 7, 1, 0x228, 0x5A0), + MX53_PIN_NANDF_ALE = _MXC_BUILD_GPIO_PIN(5, 8 , 1, 0x22C, 0x5A4), + MX53_PIN_NANDF_WP_B = _MXC_BUILD_GPIO_PIN(5, 9, 1, 0x230, 0x5A8), + MX53_PIN_NANDF_RB0 = _MXC_BUILD_GPIO_PIN(5, 10, 1, 0x234, 0x5AC), + MX53_PIN_NANDF_CS0 = _MXC_BUILD_GPIO_PIN(5, 11, 1, 0x238, 0x5B0), + MX53_PIN_NANDF_CS1 = _MXC_BUILD_GPIO_PIN(5, 14, 1, 0x23C, 0x5B4), + MX53_PIN_NANDF_CS2 = _MXC_BUILD_GPIO_PIN(5, 15, 1, 0x240, 0x5B8), + MX53_PIN_NANDF_CS3 = _MXC_BUILD_GPIO_PIN(5, 16, 1, 0x244, 0x5BC), + MX53_PIN_NVCC_NANDF = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x5C0), + MX53_PIN_FEC_MDIO = _MXC_BUILD_GPIO_PIN(0, 22, 1, 0x248, 0x5C4), + MX53_PIN_FEC_REF_CLK = _MXC_BUILD_GPIO_PIN(0, 23, 1, 0x24C, 0x5C8), + MX53_PIN_FEC_RX_ER = _MXC_BUILD_GPIO_PIN(0, 24, 1, 0x250, 0x5CC), + MX53_PIN_FEC_CRS_DV = _MXC_BUILD_GPIO_PIN(0, 25, 1, 0x254, 0x5D0), + MX53_PIN_FEC_RXD1 = _MXC_BUILD_GPIO_PIN(0, 26, 1, 0x258, 0x5D4), + MX53_PIN_FEC_RXD0 = _MXC_BUILD_GPIO_PIN(0, 27, 1, 0x25C, 0x5D8), + MX53_PIN_FEC_TX_EN = _MXC_BUILD_GPIO_PIN(0, 28, 1, 0x260, 0x5DC), + MX53_PIN_FEC_TXD1 = _MXC_BUILD_GPIO_PIN(0, 29, 1, 0x264, 0x5E0), + MX53_PIN_FEC_TXD0 = _MXC_BUILD_GPIO_PIN(0, 30, 1, 0x268, 0x5E4), + MX53_PIN_FEC_MDC = _MXC_BUILD_GPIO_PIN(0, 31, 1, 0x26C, 0x5E8), + MX53_PIN_NVCC_FEC = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x5EC), + MX53_PIN_ATA_DIOW = _MXC_BUILD_GPIO_PIN(5, 17, 1, 0x270, 0x5F0), + MX53_PIN_ATA_DMACK = _MXC_BUILD_GPIO_PIN(5, 18, 1, 0x274, 0x5F4), + MX53_PIN_ATA_DMARQ = _MXC_BUILD_GPIO_PIN(6, 0, 1, 0x278, 0x5F8), + MX53_PIN_ATA_BUFFER_EN = _MXC_BUILD_GPIO_PIN(6, 1, 1, 0x27C, 0x5FC), + MX53_PIN_ATA_INTRQ = _MXC_BUILD_GPIO_PIN(6, 2, 1, 0x280, 0x600), + MX53_PIN_ATA_DIOR = _MXC_BUILD_GPIO_PIN(6, 3, 1, 0x284, 0x604), + MX53_PIN_ATA_RESET_B = _MXC_BUILD_GPIO_PIN(6, 4, 1, 0x288, 0x608), + MX53_PIN_ATA_IORDY = _MXC_BUILD_GPIO_PIN(6, 5, 1, 0x28C, 0x60C), + MX53_PIN_ATA_DA_0 = _MXC_BUILD_GPIO_PIN(6, 6, 1, 0x290, 0x610), + MX53_PIN_ATA_DA_1 = _MXC_BUILD_GPIO_PIN(6, 7, 1, 0x294, 0x614), + MX53_PIN_ATA_DA_2 = _MXC_BUILD_GPIO_PIN(6, 8, 1, 0x298, 0x618), + MX53_PIN_ATA_CS_0 = _MXC_BUILD_GPIO_PIN(6, 9, 1, 0x29C, 0x61C), + MX53_PIN_ATA_CS_1 = _MXC_BUILD_GPIO_PIN(6, 10, 1, 0x2A0, 0x620), + MX53_PIN_NVCC_ATA2 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x624), + MX53_PIN_ATA_DATA0 = _MXC_BUILD_GPIO_PIN(1, 0, 1, 0x2A4, 0x628), + MX53_PIN_ATA_DATA1 = _MXC_BUILD_GPIO_PIN(1, 1, 1, 0x2A8, 0x62C), + MX53_PIN_ATA_DATA2 = _MXC_BUILD_GPIO_PIN(1, 2, 1, 0x2AC, 0x630), + MX53_PIN_ATA_DATA3 = _MXC_BUILD_GPIO_PIN(1, 3, 1, 0x2B0, 0x634), + MX53_PIN_ATA_DATA4 = _MXC_BUILD_GPIO_PIN(1, 4, 1, 0x2B4, 0x638), + MX53_PIN_ATA_DATA5 = _MXC_BUILD_GPIO_PIN(1, 5, 1, 0x2B8, 0x63C), + MX53_PIN_ATA_DATA6 = _MXC_BUILD_GPIO_PIN(1, 6, 1, 0x2BC, 0x640), + MX53_PIN_ATA_DATA7 = _MXC_BUILD_GPIO_PIN(1, 7, 1, 0x2C0, 0x644), + MX53_PIN_ATA_DATA8 = _MXC_BUILD_GPIO_PIN(1, 8, 1, 0x2C4, 0x648), + MX53_PIN_ATA_DATA9 = _MXC_BUILD_GPIO_PIN(1, 9, 1, 0x2C8, 0x64C), + MX53_PIN_ATA_DATA10 = _MXC_BUILD_GPIO_PIN(1, 10, 1, 0x2CC, 0x650), + MX53_PIN_ATA_DATA11 = _MXC_BUILD_GPIO_PIN(1, 11, 1, 0x2D0, 0x654), + MX53_PIN_ATA_DATA12 = _MXC_BUILD_GPIO_PIN(1, 12, 1, 0x2D4, 0x658), + MX53_PIN_ATA_DATA13 = _MXC_BUILD_GPIO_PIN(1, 13, 1, 0x2D8, 0x65C), + MX53_PIN_ATA_DATA14 = _MXC_BUILD_GPIO_PIN(1, 14, 1, 0x2DC, 0x660), + MX53_PIN_ATA_DATA15 = _MXC_BUILD_GPIO_PIN(1, 15, 1, 0x2E0, 0x664), + MX53_PIN_NVCC_ATA0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x668), + MX53_PIN_SD1_DATA0 = _MXC_BUILD_GPIO_PIN(0, 16, 1, 0x2E4, 0x66C), + MX53_PIN_SD1_DATA1 = _MXC_BUILD_GPIO_PIN(0, 17, 1, 0x2E8, 0x670), + MX53_PIN_SD1_CMD = _MXC_BUILD_GPIO_PIN(0, 18, 1, 0x2EC, 0x674), + MX53_PIN_SD1_DATA2 = _MXC_BUILD_GPIO_PIN(0, 19, 1, 0x2F0, 0x678), + MX53_PIN_SD1_CLK = _MXC_BUILD_GPIO_PIN(0, 20, 1, 0x2F4, 0x67C), + MX53_PIN_SD1_DATA3 = _MXC_BUILD_GPIO_PIN(0, 21, 1, 0x2F8, 0x680), + MX53_PIN_NVCC_SD1 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x684), + MX53_PIN_SD2_CLK = _MXC_BUILD_GPIO_PIN(0, 10, 1, 0x2FC, 0x688), + MX53_PIN_SD2_CMD = _MXC_BUILD_GPIO_PIN(0, 11, 1, 0x300, 0x68C), + MX53_PIN_SD2_DATA3 = _MXC_BUILD_GPIO_PIN(0, 12, 1, 0x304, 0x690), + MX53_PIN_SD2_DATA2 = _MXC_BUILD_GPIO_PIN(0, 13, 1, 0x308, 0x694), + MX53_PIN_SD2_DATA1 = _MXC_BUILD_GPIO_PIN(0, 14, 1, 0x30C, 0x698), + MX53_PIN_SD2_DATA0 = _MXC_BUILD_GPIO_PIN(0, 15, 1, 0x310, 0x69C), + MX53_PIN_NVCC_SD2 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x6A0), + MX53_PIN_GPIO_0 = _MXC_BUILD_GPIO_PIN(0, 0, 1, 0x314, 0x6A4), + MX53_PIN_GPIO_1 = _MXC_BUILD_GPIO_PIN(0, 1, 1, 0x318, 0x6A8), + MX53_PIN_GPIO_9 = _MXC_BUILD_GPIO_PIN(0, 9, 1, 0x31C, 0x6AC), + MX53_PIN_GPIO_3 = _MXC_BUILD_GPIO_PIN(0, 3, 1, 0x320, 0x6B0), + MX53_PIN_GPIO_6 = _MXC_BUILD_GPIO_PIN(0, 6, 1, 0x324, 0x6B4), + MX53_PIN_GPIO_2 = _MXC_BUILD_GPIO_PIN(0, 2, 1, 0x328, 0x6B8), + MX53_PIN_GPIO_4 = _MXC_BUILD_GPIO_PIN(0, 4, 1, 0x32C, 0x6BC), + MX53_PIN_GPIO_5 = _MXC_BUILD_GPIO_PIN(0, 5, 1, 0x330, 0x6C0), + MX53_PIN_GPIO_7 = _MXC_BUILD_GPIO_PIN(0, 7, 1, 0x334, 0x6C4), + MX53_PIN_GPIO_8 = _MXC_BUILD_GPIO_PIN(0, 8, 1, 0x338, 0x6C8), + MX53_PIN_GPIO_16 = _MXC_BUILD_GPIO_PIN(6, 11, 1, 0x33C, 0x6CC), + MX53_PIN_GPIO_17 = _MXC_BUILD_GPIO_PIN(6, 12, 1, 0x340, 0x6D0), + MX53_PIN_GPIO_18 = _MXC_BUILD_GPIO_PIN(6, 13, 1, 0x344, 0x6D4), + MX53_PIN_NVCC_GPIO = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x6D8), + MX53_PIN_POR_B = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x6DC), + MX53_PIN_BOOT_MODE1 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x6E0), + MX53_PIN_RESET_IN_B = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x6E4), + MX53_PIN_BOOT_MODE0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x6E8), + MX53_PIN_TEST_MODE = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x6EC), + MX53_PIN_GRP_ADDDS = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x6F0), + MX53_PIN_GRP_DDRMODE_CTL = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x6F4), + MX53_PIN_GRP_DDRPKE = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x6FC), + MX53_PIN_GRP_DDRPK = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x708), + MX53_PIN_GRP_TERM_CTL3 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x70C), + MX53_PIN_GRP_DDRHYS = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x710), + MX53_PIN_GRP_DDRMODE = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x714), + MX53_PIN_GRP_B0DS = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x718), + MX53_PIN_GRP_B1DS = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x71C), + MX53_PIN_GRP_CTLDS = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x720), + MX53_PIN_GRP_DDR_TYPE = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x724), + MX53_PIN_GRP_B2DS = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x728), + MX53_PIN_GRP_B3DS = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x72C), +}; + +#endif /* __ASSEMBLY__ */ +#endif /* __ASM_ARCH_MXC_MX53_PINS_H__ */ diff --git a/include/asm-arm/bitops.h b/include/asm-arm/bitops.h index 4b8bab2837..8eeada55d5 100644 --- a/include/asm-arm/bitops.h +++ b/include/asm-arm/bitops.h @@ -17,6 +17,8 @@ #ifdef __KERNEL__ +#include + #define smp_mb__before_clear_bit() do { } while (0) #define smp_mb__after_clear_bit() do { } while (0) @@ -25,59 +27,72 @@ */ extern void set_bit(int nr, volatile void * addr); -static inline void __set_bit(int nr, volatile void *addr) -{ - ((unsigned char *) addr)[nr >> 3] |= (1U << (nr & 7)); -} - extern void clear_bit(int nr, volatile void * addr); -static inline void __clear_bit(int nr, volatile void *addr) -{ - ((unsigned char *) addr)[nr >> 3] &= ~(1U << (nr & 7)); -} - extern void change_bit(int nr, volatile void * addr); static inline void __change_bit(int nr, volatile void *addr) { - ((unsigned char *) addr)[nr >> 3] ^= (1U << (nr & 7)); -} + unsigned long mask = BIT_MASK(nr); + unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); -extern int test_and_set_bit(int nr, volatile void * addr); + *p ^= mask; +} static inline int __test_and_set_bit(int nr, volatile void *addr) { - unsigned int mask = 1 << (nr & 7); - unsigned int oldval; + unsigned long mask = BIT_MASK(nr); + unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); + unsigned long old = *p; - oldval = ((unsigned char *) addr)[nr >> 3]; - ((unsigned char *) addr)[nr >> 3] = oldval | mask; - return oldval & mask; + *p = old | mask; + return (old & mask) != 0; } -extern int test_and_clear_bit(int nr, volatile void * addr); +static inline int test_and_set_bit(int nr, volatile void *addr) +{ + unsigned long flags; + int out; + + local_irq_save(flags); + out = __test_and_set_bit(nr, addr); + local_irq_restore(flags); + + return out; +} static inline int __test_and_clear_bit(int nr, volatile void *addr) { - unsigned int mask = 1 << (nr & 7); - unsigned int oldval; + unsigned long mask = BIT_MASK(nr); + unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); + unsigned long old = *p; - oldval = ((unsigned char *) addr)[nr >> 3]; - ((unsigned char *) addr)[nr >> 3] = oldval & ~mask; - return oldval & mask; + *p = old & ~mask; + return (old & mask) != 0; +} + +static inline int test_and_clear_bit(int nr, volatile void *addr) +{ + unsigned long flags; + int out; + + local_irq_save(flags); + out = __test_and_clear_bit(nr, addr); + local_irq_restore(flags); + + return out; } extern int test_and_change_bit(int nr, volatile void * addr); static inline int __test_and_change_bit(int nr, volatile void *addr) { - unsigned int mask = 1 << (nr & 7); - unsigned int oldval; + unsigned long mask = BIT_MASK(nr); + unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); + unsigned long old = *p; - oldval = ((unsigned char *) addr)[nr >> 3]; - ((unsigned char *) addr)[nr >> 3] = oldval ^ mask; - return oldval & mask; + *p = old ^ mask; + return (old & mask) != 0; } extern int find_first_zero_bit(void * addr, unsigned size); @@ -109,14 +124,6 @@ static inline unsigned long ffz(unsigned long word) return k; } -/* - * ffs: find first bit set. This is defined the same way as - * the libc and compiler builtin ffs routines, therefore - * differs in spirit from the above ffz (man ffs). - */ - -#define ffs(x) generic_ffs(x) - /* * hweightN: returns the hamming weight (i.e. the number * of bits set) of a N-bit word diff --git a/lib_arm/cache-cp15.c b/include/asm-arm/cache-cp15.h similarity index 57% rename from lib_arm/cache-cp15.c rename to include/asm-arm/cache-cp15.h index 62ed54fb4d..4996ee0efb 100644 --- a/lib_arm/cache-cp15.c +++ b/include/asm-arm/cache-cp15.h @@ -1,4 +1,6 @@ /* + * (C) Copyright 2008-2010 Freescale Semiconductor, Inc. + * * (C) Copyright 2002 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * @@ -25,96 +27,62 @@ #include #if !(defined(CONFIG_SYS_NO_ICACHE) && defined(CONFIG_SYS_NO_DCACHE)) -static void cp_delay (void) -{ - volatile int i; - - /* copro seems to need some delay between reading and writing */ - for (i = 0; i < 100; i++) - nop(); +#define cp_delay() \ +{ \ + volatile int i; \ + /* copro seems to need some delay between reading and writing */ \ + for (i = 0; i < 100; i++) \ + nop(); \ } /* cache_bit must be either CR_I or CR_C */ -static void cache_enable(uint32_t cache_bit) -{ - uint32_t reg; - - reg = get_cr(); /* get control reg. */ - cp_delay(); - set_cr(reg | cache_bit); +#define cache_enable(cache_bit) \ +{ \ + uint32_t reg; \ + reg = get_cr(); /* get control reg. */ \ + set_cr(reg | cache_bit); \ + cp_delay(); \ } /* cache_bit must be either CR_I or CR_C */ -static void cache_disable(uint32_t cache_bit) -{ - uint32_t reg; - - reg = get_cr(); - cp_delay(); - set_cr(reg & ~cache_bit); +#define cache_disable(cache_bit) \ +{ \ + uint32_t reg; \ + reg = get_cr(); \ + set_cr(reg & ~cache_bit); \ + cp_delay(); \ } + #endif #ifdef CONFIG_SYS_NO_ICACHE -void icache_enable (void) -{ - return; -} +#define icache_enable() -void icache_disable (void) -{ - return; -} +#define icache_disable() -int icache_status (void) -{ - return 0; /* always off */ -} +#define icache_status() #else -void icache_enable(void) -{ - cache_enable(CR_I); -} +#define icache_enable() (cache_enable(CR_I)) -void icache_disable(void) -{ - cache_disable(CR_I); -} +#define icache_disable() (cache_disable(CR_I)) -int icache_status(void) -{ - return (get_cr() & CR_I) != 0; -} +#define icache_status() ((get_cr() & CR_I) != 0) #endif #ifdef CONFIG_SYS_NO_DCACHE -void dcache_enable (void) -{ - return; -} +#define dcache_enable() -void dcache_disable (void) -{ - return; -} +#define dcache_disable() -int dcache_status (void) -{ - return 0; /* always off */ -} +#define dcache_status() #else -void dcache_enable(void) -{ - cache_enable(CR_C); -} +#define dcache_enable() (cache_enable(CR_C)) -void dcache_disable(void) -{ - cache_disable(CR_C); +#define dcache_disable() \ +{ \ + cache_disable(CR_C); \ } -int dcache_status(void) -{ - return (get_cr() & CR_C) != 0; -} +#define dcache_status() ((get_cr() & CR_C) != 0) + #endif diff --git a/include/asm-arm/clock.h b/include/asm-arm/clock.h new file mode 100644 index 0000000000..fe2813e86a --- /dev/null +++ b/include/asm-arm/clock.h @@ -0,0 +1,44 @@ +/* + * (C) Copyright 2008-2010 Freescale Semiconductor, Inc. + * Terry Lv + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ASM_ARCH_CLOCK_H__ +#define __ASM_ARCH_CLOCK_H__ +#include + +enum { + CPU_CLK = 0, + PERIPH_CLK, + AHB_CLK, + IPG_CLK, + IPG_PERCLK, + UART_CLK, + CSPI_CLK, + DDR_CLK, + NFC_CLK, + ALL_CLK, +}; + +int clk_config(u32 ref, u32 freq, u32 clk_type); +int clk_info(u32 clk_type); + +#endif diff --git a/include/asm-arm/dma-mapping.h b/include/asm-arm/dma-mapping.h index 501ce0e680..344c7d75d2 100644 --- a/include/asm-arm/dma-mapping.h +++ b/include/asm-arm/dma-mapping.h @@ -28,6 +28,7 @@ enum dma_data_direction { DMA_BIDIRECTIONAL = 0, DMA_TO_DEVICE = 1, DMA_FROM_DEVICE = 2, + DMA_NONE = 3, }; static void *dma_alloc_coherent(size_t len, unsigned long *handle) diff --git a/include/asm-arm/fec.h b/include/asm-arm/fec.h new file mode 100644 index 0000000000..60a769020b --- /dev/null +++ b/include/asm-arm/fec.h @@ -0,0 +1,284 @@ +/* + * fec.h -- Fast Ethernet Controller definitions + * + * Some definitions copied from commproc.h for MPC8xx: + * MPC8xx Communication Processor Module. + * Copyright (c) 1997 Dan Malek (dmalek@jlc.net) + * + * Add FEC Structure and definitions + * Copyright 2004-2010 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef fec_h +#define fec_h + +extern int fec_get_mac_addr(unsigned char *mac); + +#include + +/* Buffer descriptors used FEC. +*/ +typedef struct cpm_buf_desc { + ushort cbd_datlen; /* Data length in buffer */ + ushort cbd_sc; /* Status and Control */ + ulong cbd_bufaddr; /* Buffer address in host memory */ +} cbd_t; + +#define BD_SC_EMPTY ((ushort)0x8000) /* Recieve is empty */ +#define BD_SC_READY ((ushort)0x8000) /* Transmit is ready */ +#define BD_SC_WRAP ((ushort)0x2000)/* Last buffer descriptor */ +#define BD_SC_INTRPT ((ushort)0x1000)/* Interrupt on change */ +#define BD_SC_LAST ((ushort)0x0800)/* Last buffer in frame */ +#define BD_SC_TC ((ushort)0x0400) /* Transmit CRC */ +#define BD_SC_CM ((ushort)0x0200) /* Continous mode */ +#define BD_SC_ID ((ushort)0x0100)/* Rec'd too many idles */ +#define BD_SC_P ((ushort)0x0100) /* xmt preamble */ +#define BD_SC_BR ((ushort)0x0020) /* Break received */ +#define BD_SC_FR ((ushort)0x0010) /* Framing error */ +#define BD_SC_PR ((ushort)0x0008) /* Parity error */ +#define BD_SC_OV ((ushort)0x0002) /* Overrun */ +#define BD_SC_CD ((ushort)0x0001)/* Carrier Detect lost */ + +/* Buffer descriptor control/status used by Ethernet receive. +*/ +#define BD_ENET_RX_EMPTY ((ushort)0x8000) +#define BD_ENET_RX_RO1 ((ushort)0x4000) +#define BD_ENET_RX_WRAP ((ushort)0x2000) +#define BD_ENET_RX_INTR ((ushort)0x1000) +#define BD_ENET_RX_RO2 BD_ENET_RX_INTR +#define BD_ENET_RX_LAST ((ushort)0x0800) +#define BD_ENET_RX_FIRST ((ushort)0x0400) +#define BD_ENET_RX_MISS ((ushort)0x0100) +#define BD_ENET_RX_BC ((ushort)0x0080) +#define BD_ENET_RX_MC ((ushort)0x0040) +#define BD_ENET_RX_LG ((ushort)0x0020) +#define BD_ENET_RX_NO ((ushort)0x0010) +#define BD_ENET_RX_SH ((ushort)0x0008) +#define BD_ENET_RX_CR ((ushort)0x0004) +#define BD_ENET_RX_OV ((ushort)0x0002) +#define BD_ENET_RX_CL ((ushort)0x0001) +#define BD_ENET_RX_TR BD_ENET_RX_CL +#define BD_ENET_RX_STATS ((ushort)0x013f) /* All status bits */ + +/* Buffer descriptor control/status used by Ethernet transmit. +*/ +#define BD_ENET_TX_READY ((ushort)0x8000) +#define BD_ENET_TX_PAD ((ushort)0x4000) +#define BD_ENET_TX_TO1 BD_ENET_TX_PAD +#define BD_ENET_TX_WRAP ((ushort)0x2000) +#define BD_ENET_TX_INTR ((ushort)0x1000) +#define BD_ENET_TX_TO2 BD_ENET_TX_INTR_ +#define BD_ENET_TX_LAST ((ushort)0x0800) +#define BD_ENET_TX_TC ((ushort)0x0400) +#define BD_ENET_TX_DEF ((ushort)0x0200) +#define BD_ENET_TX_ABC BD_ENET_TX_DEF +#define BD_ENET_TX_HB ((ushort)0x0100) +#define BD_ENET_TX_LC ((ushort)0x0080) +#define BD_ENET_TX_RL ((ushort)0x0040) +#define BD_ENET_TX_RCMASK ((ushort)0x003c) +#define BD_ENET_TX_UN ((ushort)0x0002) +#define BD_ENET_TX_CSL ((ushort)0x0001) +#define BD_ENET_TX_STATS ((ushort)0x03ff) /* All status bits */ + +/********************************************************************* +* Fast Ethernet Controller (FEC) +*********************************************************************/ +/* FEC private information */ +struct fec_info_s { + int index; + volatile void *iobase; + int phy_addr; + int dup_spd; + char *phy_name; + int phyname_init; + cbd_t *rxbd; /* Rx BD */ + cbd_t *txbd; /* Tx BD */ + uint rxIdx; + uint txIdx; + char *txbuf; +#ifdef CONFIG_ARCH_MMU + char *rxbuf[PKTBUFSRX]; +#endif + int initialized; + struct fec_info_s *next; +}; + +/* Register read/write struct */ +typedef struct fec { + u32 resv0; + u32 eir; + u32 eimr; + u32 resv1; + u32 rdar; + u32 tdar; + u32 resv2[0x03]; + u32 ecr; + u32 resv3[0x06]; + u32 mmfr; + u32 mscr; + u32 resv4[0x07]; + u32 mibc; + u32 resv5[0x07]; + u32 rcr; + u32 resv6[0x0F]; + u32 tcr; + u32 resv7[0x07]; + u32 palr; + u32 paur; + u32 opd; + u32 resv8[0x0A]; + u32 iaur; + u32 ialr; + u32 gaur; + u32 galr; + u32 resv9[0x07]; + u32 tfwr; + u32 resv10; + u32 frbr; + u32 frsr; + u32 resv11[0x0B]; + u32 erdsr; + u32 etdsr; + u32 emrbr; + u32 resv12[93]; + u32 fec_miigsk_cfgr; + u32 fec_reserved13; + u32 fec_miigsk_enr; +} fec_t; + +/********************************************************************* +* Fast Ethernet Controller (FEC) +*********************************************************************/ +/* Bit definitions and macros for FEC_EIR */ +#define FEC_EIR_CLEAR_ALL (0xFFF80000) +#define FEC_EIR_HBERR (0x80000000) +#define FEC_EIR_BABR (0x40000000) +#define FEC_EIR_BABT (0x20000000) +#define FEC_EIR_GRA (0x10000000) +#define FEC_EIR_TXF (0x08000000) +#define FEC_EIR_TXB (0x04000000) +#define FEC_EIR_RXF (0x02000000) +#define FEC_EIR_RXB (0x01000000) +#define FEC_EIR_MII (0x00800000) +#define FEC_EIR_EBERR (0x00400000) +#define FEC_EIR_LC (0x00200000) +#define FEC_EIR_RL (0x00100000) +#define FEC_EIR_UN (0x00080000) + +/* Bit definitions and macros for FEC_RDAR */ +#define FEC_RDAR_R_DES_ACTIVE (0x01000000) + +/* Bit definitions and macros for FEC_TDAR */ +#define FEC_TDAR_X_DES_ACTIVE (0x01000000) + +/* Bit definitions and macros for FEC_ECR */ +#define FEC_ECR_ETHER_EN (0x00000002) +#define FEC_ECR_RESET (0x00000001) + +/* Bit definitions and macros for FEC_MMFR */ +#define FEC_MMFR_DATA(x) (((x)&0xFFFF)) +#define FEC_MMFR_ST(x) (((x)&0x03)<<30) +#define FEC_MMFR_ST_01 (0x40000000) +#define FEC_MMFR_OP_RD (0x20000000) +#define FEC_MMFR_OP_WR (0x10000000) +#define FEC_MMFR_PA(x) (((x)&0x1F)<<23) +#define FEC_MMFR_RA(x) (((x)&0x1F)<<18) +#define FEC_MMFR_TA(x) (((x)&0x03)<<16) +#define FEC_MMFR_TA_10 (0x00020000) + +/* Bit definitions and macros for FEC_MSCR */ +#define FEC_MSCR_DIS_PREAMBLE (0x00000080) +#define FEC_MSCR_MII_SPEED(x) (((x)&0x3F)<<1) + +/* Bit definitions and macros for FEC_MIBC */ +#define FEC_MIBC_MIB_DISABLE (0x80000000) +#define FEC_MIBC_MIB_IDLE (0x40000000) + +/* Bit definitions and macros for FEC_RCR */ +#define FEC_RCR_GRS (0x80000000) +#define FEC_RCR_NO_LGTH_CHECK (0x40000000) +#define FEC_RCR_MAX_FL(x) (((x)&0x7FF)<<16) +#define FEC_RCR_CNTL_FRM_ENA (0x00008000) +#define FEC_RCR_CRC_FWD (0x00004000) +#define FEC_RCR_PAUSE_FWD (0x00002000) +#define FEC_RCR_PAD_EN (0x00001000) +#define FEC_RCR_RMII_ECHO (0x00000800) +#define FEC_RCR_RMII_LOOP (0x00000400) +#define FEC_RCR_RMII_10T (0x00000200) +#define FEC_RCR_RMII_MODE (0x00000100) +#define FEC_RCR_SGMII_ENA (0x00000080) +#define FEC_RCR_RGMII_ENA (0x00000040) +#define FEC_RCR_FCE (0x00000020) +#define FEC_RCR_BC_REJ (0x00000010) +#define FEC_RCR_PROM (0x00000008) +#define FEC_RCR_MII_MODE (0x00000004) +#define FEC_RCR_DRT (0x00000002) +#define FEC_RCR_LOOP (0x00000001) + +/* Bit definitions and macros for FEC_TCR */ +#define FEC_TCR_RFC_PAUSE (0x00000010) +#define FEC_TCR_TFC_PAUSE (0x00000008) +#define FEC_TCR_FDEN (0x00000004) +#define FEC_TCR_HBC (0x00000002) +#define FEC_TCR_GTS (0x00000001) + +/* Bit definitions and macros for FEC_PAUR */ +#define FEC_PAUR_PADDR2(x) (((x)&0xFFFF)<<16) +#define FEC_PAUR_TYPE(x) ((x)&0xFFFF) + +/* Bit definitions and macros for FEC_OPD */ +#define FEC_OPD_PAUSE_DUR(x) (((x)&0x0000FFFF)<<0) +#define FEC_OPD_OPCODE(x) (((x)&0x0000FFFF)<<16) + +/* Bit definitions and macros for FEC_TFWR */ +#define FEC_TFWR_X_WMRK(x) ((x)&0x03) +#define FEC_TFWR_X_WMRK_64 (0x01) +#define FEC_TFWR_X_WMRK_128 (0x02) +#define FEC_TFWR_X_WMRK_192 (0x03) + +/* Bit definitions and macros for FEC_FRBR */ +#define FEC_FRBR_R_BOUND(x) (((x)&0xFF)<<2) + +/* Bit definitions and macros for FEC_FRSR */ +#define FEC_FRSR_R_FSTART(x) (((x)&0xFF)<<2) + +/* Bit definitions and macros for FEC_ERDSR */ +#define FEC_ERDSR_R_DES_START(x) (((x)&0x3FFFFFFF)<<2) + +/* Bit definitions and macros for FEC_ETDSR */ +#define FEC_ETDSR_X_DES_START(x) (((x)&0x3FFFFFFF)<<2) + +/* Bit definitions and macros for FEC_EMRBR */ +#define FEC_EMRBR_R_BUF_SIZE(x) (((x)&0x7F)<<4) + +#define FEC_RESET_DELAY 100 +#define FEC_RX_TOUT 100 + +#define FEC_MAX_TIMEOUT 50000 +#define FEC_TIMEOUT_TICKET 2 + +/* + * Functions + */ +int mxc_fec_initialize(bd_t *bis); + +#endif /* fec_h */ diff --git a/include/asm-arm/imx_iim.h b/include/asm-arm/imx_iim.h new file mode 100644 index 0000000000..d2ccd3476b --- /dev/null +++ b/include/asm-arm/imx_iim.h @@ -0,0 +1,71 @@ +/* + * (C) Copyright 2009-2010 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __IMX_IIM_H__ +#define __IMX_IIM_H__ + +/* IIM Control Registers */ +struct iim_regs { +#define IIM_STAT_BUSY (1 << 7) +#define IIM_STAT_PRGD (1 << 1) +#define IIM_STAT_SNSD (1 << 0) + u32 stat; + u32 statm; +#define IIM_ERR_PRGE (1 << 7) +#define IIM_ERR_WPE (1 << 6) +#define IIM_ERR_OPE (1 << 5) +#define IIM_ERR_RPE (1 << 4) +#define IIM_ERR_WLRE (1 << 3) +#define IIM_ERR_SNSE (1 << 2) +#define IIM_ERR_PARITYE (1 << 1) + u32 err; + u32 emask; + u32 fctl; + u32 ua; + u32 la; + u32 sdat; + u32 prev; + u32 srev; + u32 preg_p; + u32 scs0; + u32 scs1; + u32 scs2; + u32 scs3; +}; + +#define IIM_PROD_REV_SH 3 +#define IIM_PROD_REV_LEN 5 +#define IIM_SREV_REV_SH 4 +#define IIM_SREV_REV_LEN 4 +#define PROD_SIGNATURE_MX51 0x1 + +#define IIM_ERR_SHIFT 8 +#define POLL_FUSE_PRGD (IIM_STAT_PRGD | (IIM_ERR_PRGE << IIM_ERR_SHIFT)) +#define POLL_FUSE_SNSD (IIM_STAT_SNSD | (IIM_ERR_SNSE << IIM_ERR_SHIFT)) + +#define IIM_BANK_AREA_0_OFFSET 0x800 +#define IIM_BANK_AREA_1_OFFSET 0xc00 +#define IIM_BANK_AREA_2_OFFSET 0x1000 +#define IIM_BANK_AREA_3_OFFSET 0x1400 + +int iim_read(int bank, char row); +int iim_blow(int bank, int row, int val); +int iim_blow_func(char *func_name, char *func_val); + +#endif diff --git a/include/asm-arm/io.h b/include/asm-arm/io.h index fec3a7eace..a79db837ca 100644 --- a/include/asm-arm/io.h +++ b/include/asm-arm/io.h @@ -182,9 +182,19 @@ extern void __raw_readsl(unsigned int addr, void *data, int longlen); * linux/Documentation/IO-mapping.txt. If you want a * physical address, use __ioremap instead. */ +#ifdef CONFIG_ARCH_MMU extern void * __ioremap(unsigned long offset, size_t size, unsigned long flags); extern void __iounmap(void *addr); +#else +static inline void *__ioremap(unsigned long offset, size_t size, unsigned long flags) +{ + return (void *)offset; +} +static inline void __iounmap(void *addr) +{ +} +#endif /* * Generic ioremap support. * @@ -198,7 +208,7 @@ extern void __iounmap(void *addr); unsigned long _off = (off), _size = (sz); \ void *_ret = (void *)0; \ if (iomem_valid_addr(_off, _size)) \ - _ret = __ioremap(iomem_to_phys(_off),_size,0); \ + _ret = __ioremap(iomem_to_phys(_off), _size, nocache); \ _ret; \ }) diff --git a/include/asm-arm/mach-types.h b/include/asm-arm/mach-types.h index 5293d679eb..b06902cc5f 100644 --- a/include/asm-arm/mach-types.h +++ b/include/asm-arm/mach-types.h @@ -1451,7 +1451,7 @@ extern unsigned int __machine_arch_type; #define MACH_TYPE_H6044 1458 #define MACH_TYPE_APP 1459 #define MACH_TYPE_TCT_HAMMER 1460 -#define MACH_TYPE_HERMES 1461 +#define MACH_TYPE_HERALD 1461 #define MACH_TYPE_ARTEMIS 1462 #define MACH_TYPE_HTCTITAN 1463 #define MACH_TYPE_QRANIUM 1464 @@ -1634,7 +1634,7 @@ extern unsigned int __machine_arch_type; #define MACH_TYPE_AML_M8050 1644 #define MACH_TYPE_MX35_3DS 1645 #define MACH_TYPE_MARS 1646 -#define MACH_TYPE_NTOSD_644XA 1647 +#define MACH_TYPE_NEUROS_OSD2 1647 #define MACH_TYPE_BADGER 1648 #define MACH_TYPE_TRIZEPS4WL 1649 #define MACH_TYPE_TRIZEPS5 1650 @@ -1650,7 +1650,7 @@ extern unsigned int __machine_arch_type; #define MACH_TYPE_ZORAN43XX 1660 #define MACH_TYPE_SONIX926 1661 #define MACH_TYPE_CELESTIALSEMI 1662 -#define MACH_TYPE_CC9M2443 1663 +#define MACH_TYPE_CC9M2443JS 1663 #define MACH_TYPE_TW5334 1664 #define MACH_TYPE_HTCARTEMIS 1665 #define MACH_TYPE_NAL_HLITE 1666 @@ -1765,13 +1765,14 @@ extern unsigned int __machine_arch_type; #define MACH_TYPE_MI424WR 1778 #define MACH_TYPE_AXS_ULTRAX 1779 #define MACH_TYPE_AT572D940DEB 1780 -#define MACH_TYPE_DAVINCI_DA8XX_EVM 1781 +#define MACH_TYPE_DAVINCI_DA830_EVM 1781 #define MACH_TYPE_EP9302 1782 #define MACH_TYPE_AT572D940HFEB 1783 #define MACH_TYPE_CYBOOK3 1784 #define MACH_TYPE_WDG002 1785 #define MACH_TYPE_SG560ADSL 1786 #define MACH_TYPE_NEXTIO_N2800_ICA 1787 +#define MACH_TYPE_DOVE_DB 1788 #define MACH_TYPE_MARVELL_NEWDB 1789 #define MACH_TYPE_VANDIHUD 1790 #define MACH_TYPE_MAGX_E8 1791 @@ -1798,7 +1799,7 @@ extern unsigned int __machine_arch_type; #define MACH_TYPE_RD88F5181L_GE 1812 #define MACH_TYPE_SIFMAIN 1813 #define MACH_TYPE_SAM9_L9261 1814 -#define MACH_TYPE_CC9M2443JS 1815 +#define MACH_TYPE_CC9M2443 1815 #define MACH_TYPE_XARIA300 1816 #define MACH_TYPE_IT9200 1817 #define MACH_TYPE_RD88F5181L_FXO 1818 @@ -1989,7 +1990,7 @@ extern unsigned int __machine_arch_type; #define MACH_TYPE_BENZINA 2003 #define MACH_TYPE_BLAZE 2004 #define MACH_TYPE_LINKSTATION_LS_HGL 2005 -#define MACH_TYPE_HTCVENUS 2006 +#define MACH_TYPE_HTCKOVSKY 2006 #define MACH_TYPE_SONY_PRS505 2007 #define MACH_TYPE_HANLIN_V3 2008 #define MACH_TYPE_SAPPHIRA 2009 @@ -2241,6 +2242,788 @@ extern unsigned int __machine_arch_type; #define MACH_TYPE_OMAP3_WL_FF 2258 #define MACH_TYPE_SIMCOM 2259 #define MACH_TYPE_MCWEBIO 2260 +#define MACH_TYPE_OMAP3_PHRAZER 2261 +#define MACH_TYPE_DARWIN 2262 +#define MACH_TYPE_ORATISCOMU 2263 +#define MACH_TYPE_RTSBC20 2264 +#define MACH_TYPE_I780 2265 +#define MACH_TYPE_GEMINI324 2266 +#define MACH_TYPE_ORATISLAN 2267 +#define MACH_TYPE_ORATISALOG 2268 +#define MACH_TYPE_ORATISMADI 2269 +#define MACH_TYPE_ORATISOT16 2270 +#define MACH_TYPE_ORATISDESK 2271 +#define MACH_TYPE_VEXPRESS 2272 +#define MACH_TYPE_SINTEXO 2273 +#define MACH_TYPE_CM3389 2274 +#define MACH_TYPE_OMAP3_CIO 2275 +#define MACH_TYPE_SGH_I900 2276 +#define MACH_TYPE_BST100 2277 +#define MACH_TYPE_PASSION 2278 +#define MACH_TYPE_INDESIGN_AT91SAM 2279 +#define MACH_TYPE_C4_BADGER 2280 +#define MACH_TYPE_C4_VIPER 2281 +#define MACH_TYPE_D2NET 2282 +#define MACH_TYPE_BIGDISK 2283 +#define MACH_TYPE_NOTALVISION 2284 +#define MACH_TYPE_OMAP3_KBOC 2285 +#define MACH_TYPE_CYCLONE 2286 +#define MACH_TYPE_NINJA 2287 +#define MACH_TYPE_AT91SAM9G20EK_2MMC 2288 +#define MACH_TYPE_BCMRING 2289 +#define MACH_TYPE_RESOL_DL2 2290 +#define MACH_TYPE_IFOSW 2291 +#define MACH_TYPE_HTCRHODIUM 2292 +#define MACH_TYPE_HTCTOPAZ 2293 +#define MACH_TYPE_MATRIX504 2294 +#define MACH_TYPE_MRFSA 2295 +#define MACH_TYPE_SC_P270 2296 +#define MACH_TYPE_ATLAS5_EVB 2297 +#define MACH_TYPE_PELCO_LOBOX 2298 +#define MACH_TYPE_DILAX_PCU200 2299 +#define MACH_TYPE_LEONARDO 2300 +#define MACH_TYPE_ZORAN_APPROACH7 2301 +#define MACH_TYPE_DP6XX 2302 +#define MACH_TYPE_BCM2153_VESPER 2303 +#define MACH_TYPE_MAHIMAHI 2304 +#define MACH_TYPE_CLICKC 2305 +#define MACH_TYPE_ZB_GATEWAY 2306 +#define MACH_TYPE_TAZCARD 2307 +#define MACH_TYPE_TAZDEV 2308 +#define MACH_TYPE_ANNAX_CB_ARM 2309 +#define MACH_TYPE_ANNAX_DM3 2310 +#define MACH_TYPE_CEREBRIC 2311 +#define MACH_TYPE_ORCA 2312 +#define MACH_TYPE_PC9260 2313 +#define MACH_TYPE_EMS285A 2314 +#define MACH_TYPE_GEC2410 2315 +#define MACH_TYPE_GEC2440 2316 +#define MACH_TYPE_ARCH_MW903 2317 +#define MACH_TYPE_MW2440 2318 +#define MACH_TYPE_ECAC2378 2319 +#define MACH_TYPE_TAZKIOSK 2320 +#define MACH_TYPE_WHITERABBIT_MCH 2321 +#define MACH_TYPE_SBOX9263 2322 +#define MACH_TYPE_OREO 2323 +#define MACH_TYPE_SMDK6442 2324 +#define MACH_TYPE_OPENRD_BASE 2325 +#define MACH_TYPE_INCREDIBLE 2326 +#define MACH_TYPE_INCREDIBLEC 2327 +#define MACH_TYPE_HEROCT 2328 +#define MACH_TYPE_MMNET1000 2329 +#define MACH_TYPE_DEVKIT8000 2330 +#define MACH_TYPE_DEVKIT9000 2331 +#define MACH_TYPE_MX31TXTR 2332 +#define MACH_TYPE_U380 2333 +#define MACH_TYPE_HUALU_BOARD 2334 +#define MACH_TYPE_NPCMX50 2335 +#define MACH_TYPE_MX51_LANGE51 2336 +#define MACH_TYPE_MX51_LANGE52 2337 +#define MACH_TYPE_RIOM 2338 +#define MACH_TYPE_COMCAS 2339 +#define MACH_TYPE_WSI_MX27 2340 +#define MACH_TYPE_CM_T35 2341 +#define MACH_TYPE_NET2BIG 2342 +#define MACH_TYPE_MOTOROLA_A1600 2343 +#define MACH_TYPE_IGEP0020 2344 +#define MACH_TYPE_IGEP0010 2345 +#define MACH_TYPE_MV6281GTWGE2 2346 +#define MACH_TYPE_SCAT100 2347 +#define MACH_TYPE_SANMINA 2348 +#define MACH_TYPE_MOMENTO 2349 +#define MACH_TYPE_NUC9XX 2350 +#define MACH_TYPE_NUC910EVB 2351 +#define MACH_TYPE_NUC920EVB 2352 +#define MACH_TYPE_NUC950EVB 2353 +#define MACH_TYPE_NUC945EVB 2354 +#define MACH_TYPE_NUC960EVB 2355 +#define MACH_TYPE_NUC932EVB 2356 +#define MACH_TYPE_NUC900 2357 +#define MACH_TYPE_SD1SOC 2358 +#define MACH_TYPE_LN2440BC 2359 +#define MACH_TYPE_RSBC 2360 +#define MACH_TYPE_OPENRD_CLIENT 2361 +#define MACH_TYPE_HPIPAQ11X 2362 +#define MACH_TYPE_WAYLAND 2363 +#define MACH_TYPE_ACNBSX102 2364 +#define MACH_TYPE_HWAT91 2365 +#define MACH_TYPE_AT91SAM9263CS 2366 +#define MACH_TYPE_CSB732 2367 +#define MACH_TYPE_U8500 2368 +#define MACH_TYPE_HUQIU 2369 +#define MACH_TYPE_MX51_KUNLUN 2370 +#define MACH_TYPE_PMT1G 2371 +#define MACH_TYPE_HTCELF 2372 +#define MACH_TYPE_ARMADILLO420 2373 +#define MACH_TYPE_ARMADILLO440 2374 +#define MACH_TYPE_U_CHIP_DUAL_ARM 2375 +#define MACH_TYPE_CSR_BDB3 2376 +#define MACH_TYPE_DOLBY_CAT1018 2377 +#define MACH_TYPE_HY9307 2378 +#define MACH_TYPE_A_ES 2379 +#define MACH_TYPE_DAVINCI_IRIF 2380 +#define MACH_TYPE_AGAMA9263 2381 +#define MACH_TYPE_MARVELL_JASPER 2382 +#define MACH_TYPE_FLINT 2383 +#define MACH_TYPE_TAVOREVB3 2384 +#define MACH_TYPE_SCH_M490 2386 +#define MACH_TYPE_RBL01 2387 +#define MACH_TYPE_OMNIFI 2388 +#define MACH_TYPE_OTAVALO 2389 +#define MACH_TYPE_SIENNA 2390 +#define MACH_TYPE_HTC_EXCALIBUR_S620 2391 +#define MACH_TYPE_HTC_OPAL 2392 +#define MACH_TYPE_TOUCHBOOK 2393 +#define MACH_TYPE_LATTE 2394 +#define MACH_TYPE_XA200 2395 +#define MACH_TYPE_NIMROD 2396 +#define MACH_TYPE_CC9P9215_3G 2397 +#define MACH_TYPE_CC9P9215_3GJS 2398 +#define MACH_TYPE_TK71 2399 +#define MACH_TYPE_COMHAM3525 2400 +#define MACH_TYPE_MX31EREBUS 2401 +#define MACH_TYPE_MCARDMX27 2402 +#define MACH_TYPE_PARADISE 2403 +#define MACH_TYPE_TIDE 2404 +#define MACH_TYPE_WZL2440 2405 +#define MACH_TYPE_SDRDEMO 2406 +#define MACH_TYPE_ETHERCAN2 2407 +#define MACH_TYPE_ECMIMG20 2408 +#define MACH_TYPE_OMAP_DRAGON 2409 +#define MACH_TYPE_HALO 2410 +#define MACH_TYPE_HUANGSHAN 2411 +#define MACH_TYPE_VL_MA2SC 2412 +#define MACH_TYPE_RAUMFELD_RC 2413 +#define MACH_TYPE_RAUMFELD_CONNECTOR 2414 +#define MACH_TYPE_RAUMFELD_SPEAKER 2415 +#define MACH_TYPE_MULTIBUS_MASTER 2416 +#define MACH_TYPE_MULTIBUS_PBK 2417 +#define MACH_TYPE_TNETV107X 2418 +#define MACH_TYPE_SNAKE 2419 +#define MACH_TYPE_CWMX27 2420 +#define MACH_TYPE_SCH_M480 2421 +#define MACH_TYPE_PLATYPUS 2422 +#define MACH_TYPE_PSS2 2423 +#define MACH_TYPE_DAVINCI_APM150 2424 +#define MACH_TYPE_STR9100 2425 +#define MACH_TYPE_NET5BIG 2426 +#define MACH_TYPE_SEABED9263 2427 +#define MACH_TYPE_MX51_M2ID 2428 +#define MACH_TYPE_OCTVOCPLUS_EB 2429 +#define MACH_TYPE_KLK_FIREFOX 2430 +#define MACH_TYPE_KLK_WIRMA_MODULE 2431 +#define MACH_TYPE_KLK_WIRMA_MMI 2432 +#define MACH_TYPE_SUPERSONIC 2433 +#define MACH_TYPE_LIBERTY 2434 +#define MACH_TYPE_MH355 2435 +#define MACH_TYPE_PC7802 2436 +#define MACH_TYPE_GNET_SGC 2437 +#define MACH_TYPE_EINSTEIN15 2438 +#define MACH_TYPE_CMPD 2439 +#define MACH_TYPE_DAVINCI_HASE1 2440 +#define MACH_TYPE_LGEINCITEPHONE 2441 +#define MACH_TYPE_EA313X 2442 +#define MACH_TYPE_FWBD_39064 2443 +#define MACH_TYPE_FWBD_390128 2444 +#define MACH_TYPE_PELCO_MOE 2445 +#define MACH_TYPE_MINIMIX27 2446 +#define MACH_TYPE_OMAP3_THUNDER 2447 +#define MACH_TYPE_PASSIONC 2448 +#define MACH_TYPE_MX27AMATA 2449 +#define MACH_TYPE_BGAT1 2450 +#define MACH_TYPE_BUZZ 2451 +#define MACH_TYPE_MB9G20 2452 +#define MACH_TYPE_YUSHAN 2453 +#define MACH_TYPE_LIZARD 2454 +#define MACH_TYPE_OMAP3POLYCOM 2455 +#define MACH_TYPE_SMDKV210 2456 +#define MACH_TYPE_BRAVO 2457 +#define MACH_TYPE_SIOGENTOO1 2458 +#define MACH_TYPE_SIOGENTOO2 2459 +#define MACH_TYPE_SM3K 2460 +#define MACH_TYPE_ACER_TEMPO_F900 2461 +#define MACH_TYPE_SST61VC010_DEV 2462 +#define MACH_TYPE_GLITTERTIND 2463 +#define MACH_TYPE_OMAP_ZOOM3 2464 +#define MACH_TYPE_OMAP_3630SDP 2465 +#define MACH_TYPE_CYBOOK2440 2466 +#define MACH_TYPE_TORINO_S 2467 +#define MACH_TYPE_HAVANA 2468 +#define MACH_TYPE_BEAUMONT_11 2469 +#define MACH_TYPE_VANGUARD 2470 +#define MACH_TYPE_S5PC110_DRACO 2471 +#define MACH_TYPE_CARTESIO_TWO 2472 +#define MACH_TYPE_ASTER 2473 +#define MACH_TYPE_VOGUESV210 2474 +#define MACH_TYPE_ACM500X 2475 +#define MACH_TYPE_KM9260 2476 +#define MACH_TYPE_NIDEFLEXG1 2477 +#define MACH_TYPE_CTERA_PLUG_IO 2478 +#define MACH_TYPE_SMARTQ7 2479 +#define MACH_TYPE_AT91SAM9G10EK2 2480 +#define MACH_TYPE_ASUSP527 2481 +#define MACH_TYPE_AT91SAM9G20MPM2 2482 +#define MACH_TYPE_TOPASA900 2483 +#define MACH_TYPE_ELECTRUM_100 2484 +#define MACH_TYPE_MX51GRB 2485 +#define MACH_TYPE_XEA300 2486 +#define MACH_TYPE_HTCSTARTREK 2487 +#define MACH_TYPE_LIMA 2488 +#define MACH_TYPE_CSB740 2489 +#define MACH_TYPE_USB_S8815 2490 +#define MACH_TYPE_WATSON_EFM_PLUGIN 2491 +#define MACH_TYPE_MILKYWAY 2492 +#define MACH_TYPE_G4EVM 2493 +#define MACH_TYPE_PICOMOD6 2494 +#define MACH_TYPE_OMAPL138_HAWKBOARD 2495 +#define MACH_TYPE_IP6000 2496 +#define MACH_TYPE_IP6010 2497 +#define MACH_TYPE_UTM400 2498 +#define MACH_TYPE_OMAP3_ZYBEX 2499 +#define MACH_TYPE_WIRELESS_SPACE 2500 +#define MACH_TYPE_SX560 2501 +#define MACH_TYPE_TS41X 2502 +#define MACH_TYPE_ELPHEL10373 2503 +#define MACH_TYPE_RHOBOT 2504 +#define MACH_TYPE_MX51_REFRESH 2505 +#define MACH_TYPE_LS9260 2506 +#define MACH_TYPE_SHANK 2507 +#define MACH_TYPE_QSD8X50_ST1 2508 +#define MACH_TYPE_AT91SAM9M10EKES 2509 +#define MACH_TYPE_HIRAM 2510 +#define MACH_TYPE_PHY3250 2511 +#define MACH_TYPE_EA3250 2512 +#define MACH_TYPE_FDI3250 2513 +#define MACH_TYPE_WHITESTONE 2514 +#define MACH_TYPE_AT91SAM9263NIT 2515 +#define MACH_TYPE_CCMX51 2516 +#define MACH_TYPE_CCMX51JS 2517 +#define MACH_TYPE_CCWMX51 2518 +#define MACH_TYPE_CCWMX51JS 2519 +#define MACH_TYPE_MINI6410 2520 +#define MACH_TYPE_TINY6410 2521 +#define MACH_TYPE_NANO6410 2522 +#define MACH_TYPE_AT572D940HFNLDB 2523 +#define MACH_TYPE_HTCLEO 2524 +#define MACH_TYPE_AVP13 2525 +#define MACH_TYPE_XXSVIDEOD 2526 +#define MACH_TYPE_VPNEXT 2527 +#define MACH_TYPE_SWARCO_ITC3 2528 +#define MACH_TYPE_TX51 2529 +#define MACH_TYPE_DOLBY_CAT1021 2530 +#define MACH_TYPE_MX28EVK 2531 +#define MACH_TYPE_PHOENIX260 2532 +#define MACH_TYPE_UVACA_STORK 2533 +#define MACH_TYPE_SMARTQ5 2534 +#define MACH_TYPE_ALL3078 2535 +#define MACH_TYPE_CTERA_2BAY_DS 2536 +#define MACH_TYPE_SIOGENTOO3 2537 +#define MACH_TYPE_EPB5000 2538 +#define MACH_TYPE_HY9263 2539 +#define MACH_TYPE_ACER_TEMPO_M900 2540 +#define MACH_TYPE_ACER_TEMPO_DX900 2541 +#define MACH_TYPE_ACER_TEMPO_X960 2542 +#define MACH_TYPE_ACER_ETEN_V900 2543 +#define MACH_TYPE_ACER_ETEN_X900 2544 +#define MACH_TYPE_BONNELL 2545 +#define MACH_TYPE_OHT_MX27 2546 +#define MACH_TYPE_HTCQUARTZ 2547 +#define MACH_TYPE_DAVINCI_DM6467TEVM 2548 +#define MACH_TYPE_C3AX03 2549 +#define MACH_TYPE_MXT_TD60 2550 +#define MACH_TYPE_ESYX 2551 +#define MACH_TYPE_DOVE_DB2 2552 +#define MACH_TYPE_BULLDOG 2553 +#define MACH_TYPE_DERELL_ME2000 2554 +#define MACH_TYPE_BCMRING_BASE 2555 +#define MACH_TYPE_BCMRING_EVM 2556 +#define MACH_TYPE_BCMRING_EVM_JAZZ 2557 +#define MACH_TYPE_BCMRING_SP 2558 +#define MACH_TYPE_BCMRING_SV 2559 +#define MACH_TYPE_BCMRING_SV_JAZZ 2560 +#define MACH_TYPE_BCMRING_TABLET 2561 +#define MACH_TYPE_BCMRING_VP 2562 +#define MACH_TYPE_BCMRING_EVM_SEIKOR 2563 +#define MACH_TYPE_BCMRING_SP_WQVGA 2564 +#define MACH_TYPE_BCMRING_CUSTOM 2565 +#define MACH_TYPE_ACER_S200 2566 +#define MACH_TYPE_BT270 2567 +#define MACH_TYPE_ISEO 2568 +#define MACH_TYPE_CEZANNE 2569 +#define MACH_TYPE_LUCCA 2570 +#define MACH_TYPE_SUPERSMART 2571 +#define MACH_TYPE_CS_MISANO 2572 +#define MACH_TYPE_MAGNOLIA2 2573 +#define MACH_TYPE_EMXX 2574 +#define MACH_TYPE_OUTLAW 2575 +#define MACH_TYPE_RIOT_BEI2 2576 +#define MACH_TYPE_RIOT_VOX 2577 +#define MACH_TYPE_RIOT_X37 2578 +#define MACH_TYPE_MEGA25MX 2579 +#define MACH_TYPE_BENZINA2 2580 +#define MACH_TYPE_IGNITE 2581 +#define MACH_TYPE_FOGGIA 2582 +#define MACH_TYPE_AREZZO 2583 +#define MACH_TYPE_LEICA_SKYWALKER 2584 +#define MACH_TYPE_JACINTO2_JAMR 2585 +#define MACH_TYPE_GTS_NOVA 2586 +#define MACH_TYPE_P3600 2587 +#define MACH_TYPE_DLT2 2588 +#define MACH_TYPE_DF3120 2589 +#define MACH_TYPE_ECUCORE_9G20 2590 +#define MACH_TYPE_NAUTEL_LPC3240 2591 +#define MACH_TYPE_GLACIER 2592 +#define MACH_TYPE_PHRAZER_BULLDOG 2593 +#define MACH_TYPE_OMAP3_BULLDOG 2594 +#define MACH_TYPE_PCA101 2595 +#define MACH_TYPE_BUZZC 2596 +#define MACH_TYPE_SASIE2 2597 +#define MACH_TYPE_DAVINCI_CIO 2598 +#define MACH_TYPE_SMARTMETER_DL 2599 +#define MACH_TYPE_WZL6410 2600 +#define MACH_TYPE_WZL6410M 2601 +#define MACH_TYPE_WZL6410F 2602 +#define MACH_TYPE_WZL6410I 2603 +#define MACH_TYPE_SPACECOM1 2604 +#define MACH_TYPE_PINGU920 2605 +#define MACH_TYPE_BRAVOC 2606 +#define MACH_TYPE_CYBO2440 2607 +#define MACH_TYPE_VDSSW 2608 +#define MACH_TYPE_ROMULUS 2609 +#define MACH_TYPE_OMAP_MAGIC 2610 +#define MACH_TYPE_ELTD100 2611 +#define MACH_TYPE_CAPC7117 2612 +#define MACH_TYPE_SWAN 2613 +#define MACH_TYPE_VEU 2614 +#define MACH_TYPE_RM2 2615 +#define MACH_TYPE_TT2100 2616 +#define MACH_TYPE_VENICE 2617 +#define MACH_TYPE_PC7323 2618 +#define MACH_TYPE_MASP 2619 +#define MACH_TYPE_FUJITSU_TVSTBSOC 2620 +#define MACH_TYPE_FUJITSU_TVSTBSOC1 2621 +#define MACH_TYPE_LEXIKON 2622 +#define MACH_TYPE_MINI2440V2 2623 +#define MACH_TYPE_ICONTROL 2624 +#define MACH_TYPE_SHEEVAD 2625 +#define MACH_TYPE_QSD8X50A_ST1_1 2626 +#define MACH_TYPE_QSD8X50A_ST1_5 2627 +#define MACH_TYPE_BEE 2628 +#define MACH_TYPE_MX23EVK 2629 +#define MACH_TYPE_AP4EVB 2630 +#define MACH_TYPE_STOCKHOLM 2631 +#define MACH_TYPE_LPC_H3131 2632 +#define MACH_TYPE_STINGRAY 2633 +#define MACH_TYPE_KRAKEN 2634 +#define MACH_TYPE_GW2388 2635 +#define MACH_TYPE_JADECPU 2636 +#define MACH_TYPE_CARLISLE 2637 +#define MACH_TYPE_LUX_SFT9 2638 +#define MACH_TYPE_NEMID_TB 2639 +#define MACH_TYPE_TERRIER 2640 +#define MACH_TYPE_TURBOT 2641 +#define MACH_TYPE_SANDDAB 2642 +#define MACH_TYPE_MX35_CICADA 2643 +#define MACH_TYPE_GHI2703D 2644 +#define MACH_TYPE_LUX_SFX9 2645 +#define MACH_TYPE_LUX_SF9G 2646 +#define MACH_TYPE_LUX_EDK9 2647 +#define MACH_TYPE_HW90240 2648 +#define MACH_TYPE_DM365_LEOPARD 2649 +#define MACH_TYPE_MITYOMAPL138 2650 +#define MACH_TYPE_SCAT110 2651 +#define MACH_TYPE_ACER_A1 2652 +#define MACH_TYPE_CMCONTROL 2653 +#define MACH_TYPE_PELCO_LAMAR 2654 +#define MACH_TYPE_RFP43 2655 +#define MACH_TYPE_SK86R0301 2656 +#define MACH_TYPE_CTPXA 2657 +#define MACH_TYPE_EPB_ARM9_A 2658 +#define MACH_TYPE_GURUPLUG 2659 +#define MACH_TYPE_SPEAR310 2660 +#define MACH_TYPE_SPEAR320 2661 +#define MACH_TYPE_ROBOTX 2662 +#define MACH_TYPE_LSXHL 2663 +#define MACH_TYPE_SMARTLITE 2664 +#define MACH_TYPE_CWS2 2665 +#define MACH_TYPE_M619 2666 +#define MACH_TYPE_SMARTVIEW 2667 +#define MACH_TYPE_LSA_SALSA 2668 +#define MACH_TYPE_KIZBOX 2669 +#define MACH_TYPE_HTCCHARMER 2670 +#define MACH_TYPE_GUF_NESO_LT 2671 +#define MACH_TYPE_PM9G45 2672 +#define MACH_TYPE_HTCPANTHER 2673 +#define MACH_TYPE_HTCPANTHER_CDMA 2674 +#define MACH_TYPE_REB01 2675 +#define MACH_TYPE_AQUILA 2676 +#define MACH_TYPE_SPARK_SLS_HW2 2677 +#define MACH_TYPE_ESATA_SHEEVAPLUG 2678 +#define MACH_TYPE_MSM7X30_SURF 2679 +#define MACH_TYPE_MICRO2440 2680 +#define MACH_TYPE_AM2440 2681 +#define MACH_TYPE_TQ2440 2682 +#define MACH_TYPE_LPC2478OEM 2683 +#define MACH_TYPE_AK880X 2684 +#define MACH_TYPE_COBRA3530 2685 +#define MACH_TYPE_PMPPB 2686 +#define MACH_TYPE_U6715 2687 +#define MACH_TYPE_AXAR1500_SENDER 2688 +#define MACH_TYPE_G30_DVB 2689 +#define MACH_TYPE_VC088X 2690 +#define MACH_TYPE_MIOA702 2691 +#define MACH_TYPE_HPMIN 2692 +#define MACH_TYPE_AK880XAK 2693 +#define MACH_TYPE_ARM926TOMAP850 2694 +#define MACH_TYPE_LKEVM 2695 +#define MACH_TYPE_MW6410 2696 +#define MACH_TYPE_TERASTATION_WXL 2697 +#define MACH_TYPE_CPU8000E 2698 +#define MACH_TYPE_CATANIA 2699 +#define MACH_TYPE_TOKYO 2700 +#define MACH_TYPE_MSM7201A_SURF 2701 +#define MACH_TYPE_MSM7201A_FFA 2702 +#define MACH_TYPE_MSM7X25_SURF 2703 +#define MACH_TYPE_MSM7X25_FFA 2704 +#define MACH_TYPE_MSM7X27_SURF 2705 +#define MACH_TYPE_MSM7X27_FFA 2706 +#define MACH_TYPE_MSM7X30_FFA 2707 +#define MACH_TYPE_QSD8X50_SURF 2708 +#define MACH_TYPE_QSD8X50_COMET 2709 +#define MACH_TYPE_QSD8X50_FFA 2710 +#define MACH_TYPE_QSD8X50A_SURF 2711 +#define MACH_TYPE_QSD8X50A_FFA 2712 +#define MACH_TYPE_ADX_XGCP10 2713 +#define MACH_TYPE_MCGWUMTS2A 2714 +#define MACH_TYPE_MOBIKT 2715 +#define MACH_TYPE_MX53_EVK 2716 +#define MACH_TYPE_IGEP0030 2717 +#define MACH_TYPE_AXELL_H40_H50_CTRL 2718 +#define MACH_TYPE_DTCOMMOD 2719 +#define MACH_TYPE_GOULD 2720 +#define MACH_TYPE_SIBERIA 2721 +#define MACH_TYPE_SBC3530 2722 +#define MACH_TYPE_QARM 2723 +#define MACH_TYPE_MIPS 2724 +#define MACH_TYPE_MX27GRB 2725 +#define MACH_TYPE_SBC8100 2726 +#define MACH_TYPE_SAARB 2727 +#define MACH_TYPE_OMAP3MINI 2728 +#define MACH_TYPE_CNMBOOK7SE 2729 +#define MACH_TYPE_CATAN 2730 +#define MACH_TYPE_HARMONY 2731 +#define MACH_TYPE_TONGA 2732 +#define MACH_TYPE_CYBOOK_ORIZON 2733 +#define MACH_TYPE_HTCRHODIUMCDMA 2734 +#define MACH_TYPE_EPC_G45 2735 +#define MACH_TYPE_EPC_LPC3250 2736 +#define MACH_TYPE_MXC91341EVB 2737 +#define MACH_TYPE_RTW1000 2738 +#define MACH_TYPE_BOBCAT 2739 +#define MACH_TYPE_TRIZEPS6 2740 +#define MACH_TYPE_MSM7X30_FLUID 2741 +#define MACH_TYPE_NEDAP9263 2742 +#define MACH_TYPE_NETGEAR_MS2110 2743 +#define MACH_TYPE_BMX 2744 +#define MACH_TYPE_NETSTREAM 2745 +#define MACH_TYPE_VPNEXT_RCU 2746 +#define MACH_TYPE_VPNEXT_MPU 2747 +#define MACH_TYPE_BCMRING_TABLET_V1 2748 +#define MACH_TYPE_SGARM10 2749 +#define MACH_TYPE_CM_T3517 2750 +#define MACH_TYPE_OMAP3_CPS 2751 +#define MACH_TYPE_AXAR1500_RECEIVER 2752 +#define MACH_TYPE_WBD222 2753 +#define MACH_TYPE_MT65XX 2754 +#define MACH_TYPE_MSM8X60_SURF 2755 +#define MACH_TYPE_MSM8X60_SIM 2756 +#define MACH_TYPE_VMC300 2757 +#define MACH_TYPE_TCC8000_SDK 2758 +#define MACH_TYPE_NANOS 2759 +#define MACH_TYPE_STAMP9G10 2760 +#define MACH_TYPE_STAMP9G45 2761 +#define MACH_TYPE_H6053 2762 +#define MACH_TYPE_SMINT01 2763 +#define MACH_TYPE_PRTLVT2 2764 +#define MACH_TYPE_AP420 2765 +#define MACH_TYPE_HTCSHIFT 2766 +#define MACH_TYPE_DAVINCI_DM365_FC 2767 +#define MACH_TYPE_MSM8X55_SURF 2768 +#define MACH_TYPE_MSM8X55_FFA 2769 +#define MACH_TYPE_ESL_VAMANA 2770 +#define MACH_TYPE_SBC35 2771 +#define MACH_TYPE_MPX6446 2772 +#define MACH_TYPE_OREO_CONTROLLER 2773 +#define MACH_TYPE_KOPIN_MODELS 2774 +#define MACH_TYPE_TTC_VISION2 2775 +#define MACH_TYPE_CNS3420VB 2776 +#define MACH_TYPE_LPC2 2777 +#define MACH_TYPE_OLYMPUS 2778 +#define MACH_TYPE_VORTEX 2779 +#define MACH_TYPE_S5PC200 2780 +#define MACH_TYPE_ECUCORE_9263 2781 +#define MACH_TYPE_SMDKC200 2782 +#define MACH_TYPE_EMSISO_SX27 2783 +#define MACH_TYPE_APX_SOM9G45_EK 2784 +#define MACH_TYPE_SONGSHAN 2785 +#define MACH_TYPE_TIANSHAN 2786 +#define MACH_TYPE_VPX500 2787 +#define MACH_TYPE_AM3517SAM 2788 +#define MACH_TYPE_SKAT91_SIM508 2789 +#define MACH_TYPE_SKAT91_S3E 2790 +#define MACH_TYPE_OMAP4_PANDA 2791 +#define MACH_TYPE_DF7220 2792 +#define MACH_TYPE_NEMINI 2793 +#define MACH_TYPE_T8200 2794 +#define MACH_TYPE_APF51 2795 +#define MACH_TYPE_DR_RC_UNIT 2796 +#define MACH_TYPE_BORDEAUX 2797 +#define MACH_TYPE_CATANIA_B 2798 +#define MACH_TYPE_MX51_OCEAN 2799 +#define MACH_TYPE_TI8168EVM 2800 +#define MACH_TYPE_NEOCOREOMAP 2801 +#define MACH_TYPE_WITHINGS_WBP 2802 +#define MACH_TYPE_DBPS 2803 +#define MACH_TYPE_SBC9261 2804 +#define MACH_TYPE_PCBFP0001 2805 +#define MACH_TYPE_SPEEDY 2806 +#define MACH_TYPE_CHRYSAOR 2807 +#define MACH_TYPE_TANGO 2808 +#define MACH_TYPE_SYNOLOGY_DSX11 2809 +#define MACH_TYPE_HANLIN_V3EXT 2810 +#define MACH_TYPE_HANLIN_V5 2811 +#define MACH_TYPE_HANLIN_V3PLUS 2812 +#define MACH_TYPE_IRIVER_STORY 2813 +#define MACH_TYPE_IREX_ILIAD 2814 +#define MACH_TYPE_IREX_DR1000 2815 +#define MACH_TYPE_TETON_BGA 2816 +#define MACH_TYPE_SNAPPER9G45 2817 +#define MACH_TYPE_TAM3517 2818 +#define MACH_TYPE_PDC100 2819 +#define MACH_TYPE_EUKREA_CPUIMX25 2820 +#define MACH_TYPE_EUKREA_CPUIMX35 2821 +#define MACH_TYPE_EUKREA_CPUIMX51SD 2822 +#define MACH_TYPE_EUKREA_CPUIMX51 2823 +#define MACH_TYPE_P565 2824 +#define MACH_TYPE_ACER_A4 2825 +#define MACH_TYPE_DAVINCI_DM368_BIP 2826 +#define MACH_TYPE_ESHARE 2827 +#define MACH_TYPE_HW_OMAPL138_EUROPA 2828 +#define MACH_TYPE_WLBARGN 2829 +#define MACH_TYPE_BM170 2830 +#define MACH_TYPE_NETSPACE_MINI_V2 2831 +#define MACH_TYPE_NETSPACE_PLUG_V2 2832 +#define MACH_TYPE_SIEMENS_L1 2833 +#define MACH_TYPE_ELV_LCU1 2834 +#define MACH_TYPE_MCU1 2835 +#define MACH_TYPE_OMAP3_TAO3530 2836 +#define MACH_TYPE_OMAP3_PCUTOUCH 2837 +#define MACH_TYPE_SMDKC210 2838 +#define MACH_TYPE_OMAP3_BRAILLO 2839 +#define MACH_TYPE_SPYPLUG 2840 +#define MACH_TYPE_GINGER 2841 +#define MACH_TYPE_TNY_T3530 2842 +#define MACH_TYPE_PCA102 2843 +#define MACH_TYPE_SPADE 2844 +#define MACH_TYPE_MXC25_TOPAZ 2845 +#define MACH_TYPE_T5325 2846 +#define MACH_TYPE_GW2361 2847 +#define MACH_TYPE_ELOG 2848 +#define MACH_TYPE_INCOME 2849 +#define MACH_TYPE_BCM589X 2850 +#define MACH_TYPE_ETNA 2851 +#define MACH_TYPE_HAWKS 2852 +#define MACH_TYPE_MESON 2853 +#define MACH_TYPE_XSBASE255 2854 +#define MACH_TYPE_PVM2030 2855 +#define MACH_TYPE_MIOA502 2856 +#define MACH_TYPE_VVBOX_SDORIG2 2857 +#define MACH_TYPE_VVBOX_SDLITE2 2858 +#define MACH_TYPE_VVBOX_SDPRO4 2859 +#define MACH_TYPE_HTC_SPV_M700 2860 +#define MACH_TYPE_MX257SX 2861 +#define MACH_TYPE_GONI 2862 +#define MACH_TYPE_MSM8X55_SVLTE_FFA 2863 +#define MACH_TYPE_MSM8X55_SVLTE_SURF 2864 +#define MACH_TYPE_QUICKSTEP 2865 +#define MACH_TYPE_DMW96 2866 +#define MACH_TYPE_HAMMERHEAD 2867 +#define MACH_TYPE_TRIDENT 2868 +#define MACH_TYPE_LIGHTNING 2869 +#define MACH_TYPE_ICONNECT 2870 +#define MACH_TYPE_AUTOBOT 2871 +#define MACH_TYPE_COCONUT 2872 +#define MACH_TYPE_DURIAN 2873 +#define MACH_TYPE_CAYENNE 2874 +#define MACH_TYPE_FUJI 2875 +#define MACH_TYPE_SYNOLOGY_6282 2876 +#define MACH_TYPE_EM1SY 2877 +#define MACH_TYPE_M502 2878 +#define MACH_TYPE_MATRIX518 2879 +#define MACH_TYPE_TINY_GURNARD 2880 +#define MACH_TYPE_SPEAR1310 2881 +#define MACH_TYPE_BV07 2882 +#define MACH_TYPE_MXT_TD61 2883 +#define MACH_TYPE_OPENRD_ULTIMATE 2884 +#define MACH_TYPE_DEVIXP 2885 +#define MACH_TYPE_MICCPT 2886 +#define MACH_TYPE_MIC256 2887 +#define MACH_TYPE_AS1167 2888 +#define MACH_TYPE_OMAP3_IBIZA 2889 +#define MACH_TYPE_U5500 2890 +#define MACH_TYPE_DAVINCI_PICTO 2891 +#define MACH_TYPE_MECHA 2892 +#define MACH_TYPE_BUBBA3 2893 +#define MACH_TYPE_PUPITRE 2894 +#define MACH_TYPE_TEGRA_HARMONY 2895 +#define MACH_TYPE_TEGRA_VOGUE 2896 +#define MACH_TYPE_TEGRA_E1165 2897 +#define MACH_TYPE_SIMPLENET 2898 +#define MACH_TYPE_EC4350TBM 2899 +#define MACH_TYPE_PEC_TC 2900 +#define MACH_TYPE_PEC_HC2 2901 +#define MACH_TYPE_ESL_MOBILIS_A 2902 +#define MACH_TYPE_ESL_MOBILIS_B 2903 +#define MACH_TYPE_ESL_WAVE_A 2904 +#define MACH_TYPE_ESL_WAVE_B 2905 +#define MACH_TYPE_UNISENSE_MMM 2906 +#define MACH_TYPE_BLUESHARK 2907 +#define MACH_TYPE_E10 2908 +#define MACH_TYPE_APP3K_ROBIN 2909 +#define MACH_TYPE_POV15HD 2910 +#define MACH_TYPE_STELLA 2911 +#define MACH_TYPE_MACH_HTC_IOLITE 2912 +#define MACH_TYPE_LINKSTATION_LSCHL 2913 +#define MACH_TYPE_NETWALKER 2914 +#define MACH_TYPE_ACSX106 2915 +#define MACH_TYPE_ATLAS5_C1 2916 +#define MACH_TYPE_NSB3AST 2917 +#define MACH_TYPE_GNET_SLC 2918 +#define MACH_TYPE_AF4000 2919 +#define MACH_TYPE_ARK9431 2920 +#define MACH_TYPE_FS_S5PC100 2921 +#define MACH_TYPE_OMAP3505NOVA8 2922 +#define MACH_TYPE_OMAP3621_EDP1 2923 +#define MACH_TYPE_ORATISAES 2924 +#define MACH_TYPE_SMDKV310 2925 +#define MACH_TYPE_SIEMENS_L0 2926 +#define MACH_TYPE_VENTANA 2927 +#define MACH_TYPE_WM8505_7IN_NETBOOK 2928 +#define MACH_TYPE_EC4350SDB 2929 +#define MACH_TYPE_MIMAS 2930 +#define MACH_TYPE_TITAN 2931 +#define MACH_TYPE_CRANEBOARD 2932 +#define MACH_TYPE_ES2440 2933 +#define MACH_TYPE_NAJAY_A9263 2934 +#define MACH_TYPE_HTCTORNADO 2935 +#define MACH_TYPE_DIMM_MX257 2936 +#define MACH_TYPE_JIGEN 2937 +#define MACH_TYPE_SMDK6450 2938 +#define MACH_TYPE_MENO_QNG 2939 +#define MACH_TYPE_NS2416 2940 +#define MACH_TYPE_RPC353 2941 +#define MACH_TYPE_TQ6410 2942 +#define MACH_TYPE_SKY6410 2943 +#define MACH_TYPE_DYNASTY 2944 +#define MACH_TYPE_VIVO 2945 +#define MACH_TYPE_BURY_BL7582 2946 +#define MACH_TYPE_BURY_BPS5270 2947 +#define MACH_TYPE_BASI 2948 +#define MACH_TYPE_TN200 2949 +#define MACH_TYPE_C2MMI 2950 +#define MACH_TYPE_MESON_6236M 2951 +#define MACH_TYPE_MESON_8626M 2952 +#define MACH_TYPE_TUBE 2953 +#define MACH_TYPE_MESSINA 2954 +#define MACH_TYPE_MX50_ARM2 2955 +#define MACH_TYPE_CETUS9263 2956 +#define MACH_TYPE_BROWNSTONE 2957 +#define MACH_TYPE_VMX25 2958 +#define MACH_TYPE_VMX51 2959 +#define MACH_TYPE_ABACUS 2960 +#define MACH_TYPE_CM4745 2961 +#define MACH_TYPE_ORATISLINK 2962 +#define MACH_TYPE_DAVINCI_DM365_DVR 2963 +#define MACH_TYPE_NETVIZ 2964 +#define MACH_TYPE_FLEXIBITY 2965 +#define MACH_TYPE_WLAN_COMPUTER 2966 +#define MACH_TYPE_LPC24XX 2967 +#define MACH_TYPE_SPICA 2968 +#define MACH_TYPE_GPSDISPLAY 2969 +#define MACH_TYPE_BIPNET 2970 +#define MACH_TYPE_OVERO_CTU_INERTIAL 2971 +#define MACH_TYPE_DAVINCI_DM355_MMM 2972 +#define MACH_TYPE_PC9260_V2 2973 +#define MACH_TYPE_PTX7545 2974 +#define MACH_TYPE_TM_EFDC 2975 +#define MACH_TYPE_WALDO1 2976 +#define MACH_TYPE_OMAP3_WALDO1 2977 +#define MACH_TYPE_FLYER 2978 +#define MACH_TYPE_TORNADO3240 2979 +#define MACH_TYPE_SOLI_01 2980 +#define MACH_TYPE_OMAPL138_EUROPALC 2981 +#define MACH_TYPE_HELIOS_V1 2982 +#define MACH_TYPE_NETSPACE_LITE_V2 2983 +#define MACH_TYPE_SSC 2984 +#define MACH_TYPE_PREMIERWAVE_EN 2985 +#define MACH_TYPE_WASABI 2986 +#define MACH_TYPE_VIVOW 2987 +#define MACH_TYPE_MX50_RDP 2988 +#define MACH_TYPE_UNIVERSAL 2989 +#define MACH_TYPE_REAL6410 2990 +#define MACH_TYPE_SPX_SAKURA 2991 +#define MACH_TYPE_IJ3K_2440 2992 +#define MACH_TYPE_OMAP3_BC10 2993 +#define MACH_TYPE_THEBE 2994 +#define MACH_TYPE_RV082 2995 +#define MACH_TYPE_ARMLGUEST 2996 +#define MACH_TYPE_TJINC1000 2997 +#define MACH_TYPE_DOCKSTAR 2998 +#define MACH_TYPE_AX8008 2999 +#define MACH_TYPE_GNET_SGCE 3000 +#define MACH_TYPE_PXWNAS_500_1000 3001 +#define MACH_TYPE_EA20 3002 +#define MACH_TYPE_AWM2 3003 +#define MACH_TYPE_TI8148EVM 3004 +#define MACH_TYPE_TEGRA_SEABOARD 3005 +#define MACH_TYPE_LINKSTATION_CHLV2 3006 +#define MACH_TYPE_TERA_PRO2_RACK 3007 +#define MACH_TYPE_RUBYS 3008 +#define MACH_TYPE_AQUARIUS 3009 +#define MACH_TYPE_MX53_ARD 3010 +#define MACH_TYPE_MX53_SMD 3011 +#define MACH_TYPE_LSWXL 3012 +#define MACH_TYPE_DOVE_AVNG_V3 3013 +#define MACH_TYPE_SDI_ESS_9263 3014 +#define MACH_TYPE_JOCPU550 3015 +#define MACH_TYPE_MSM8X60_RUMI3 3016 +#define MACH_TYPE_MSM8X60_FFA 3017 +#define MACH_TYPE_YANOMAMI 3018 +#define MACH_TYPE_GTA04 3019 +#define MACH_TYPE_CM_A510 3020 +#define MACH_TYPE_OMAP3_RFS200 3021 +#define MACH_TYPE_KX33XX 3022 +#define MACH_TYPE_PTX7510 3023 +#define MACH_TYPE_TOP9000 3024 +#define MACH_TYPE_TEENOTE 3025 +#define MACH_TYPE_TS3 3026 +#define MACH_TYPE_A0 3027 +#define MACH_TYPE_FSM9XXX_SURF 3028 +#define MACH_TYPE_FSM9XXX_FFA 3029 +#define MACH_TYPE_FRRHWCDMA60W 3030 +#define MACH_TYPE_REMUS 3031 +#define MACH_TYPE_AT91CAP7XDK 3032 +#define MACH_TYPE_AT91CAP7STK 3033 +#define MACH_TYPE_KT_SBC_SAM9_1 3034 +#define MACH_TYPE_ORATISROUTER 3035 +#define MACH_TYPE_ARMADA_XP_DB 3036 +#define MACH_TYPE_SPDM 3037 +#define MACH_TYPE_GTIB 3038 +#define MACH_TYPE_DGM3240 3039 +#define MACH_TYPE_ATLAS_I_LPE 3040 +#define MACH_TYPE_HTCMEGA 3041 +#define MACH_TYPE_TRICORDER 3042 +#define MACH_TYPE_TX28 3043 #ifdef CONFIG_ARCH_EBSA110 # ifdef machine_arch_type @@ -13193,9 +13976,9 @@ extern unsigned int __machine_arch_type; # else # define machine_arch_type MACH_TYPE_REA_2D # endif -# define machine_is_rea_2d() (machine_arch_type == MACH_TYPE_REA_2D) +# define machine_is_rea_cpu2() (machine_arch_type == MACH_TYPE_REA_2D) #else -# define machine_is_rea_2d() (0) +# define machine_is_rea_cpu2() (0) #endif #ifdef CONFIG_MACH_TI3E524 @@ -17885,9 +18668,9 @@ extern unsigned int __machine_arch_type; # else # define machine_arch_type MACH_TYPE_HYNET_INE # endif -# define machine_is_hynet_ine() (machine_arch_type == MACH_TYPE_HYNET_INE) +# define machine_is_argonst_foundation() (machine_arch_type == MACH_TYPE_HYNET_INE) #else -# define machine_is_hynet_ine() (0) +# define machine_is_argonst_foundation() (0) #endif #ifdef CONFIG_MACH_HYNET_APP @@ -19510,14 +20293,14 @@ extern unsigned int __machine_arch_type; # define machine_is_tct_hammer() (0) #endif -#ifdef CONFIG_MACH_HERMES +#ifdef CONFIG_MACH_HERALD # ifdef machine_arch_type # undef machine_arch_type # define machine_arch_type __machine_arch_type # else -# define machine_arch_type MACH_TYPE_HERMES +# define machine_arch_type MACH_TYPE_HERALD # endif -# define machine_is_herald() (machine_arch_type == MACH_TYPE_HERMES) +# define machine_is_herald() (machine_arch_type == MACH_TYPE_HERALD) #else # define machine_is_herald() (0) #endif @@ -21706,16 +22489,16 @@ extern unsigned int __machine_arch_type; # define machine_is_mars() (0) #endif -#ifdef CONFIG_MACH_NTOSD_644XA +#ifdef CONFIG_MACH_NEUROS_OSD2 # ifdef machine_arch_type # undef machine_arch_type # define machine_arch_type __machine_arch_type # else -# define machine_arch_type MACH_TYPE_NTOSD_644XA +# define machine_arch_type MACH_TYPE_NEUROS_OSD2 # endif -# define machine_is_ntosd_644xa() (machine_arch_type == MACH_TYPE_NTOSD_644XA) +# define machine_is_neuros_osd2() (machine_arch_type == MACH_TYPE_NEUROS_OSD2) #else -# define machine_is_ntosd_644xa() (0) +# define machine_is_neuros_osd2() (0) #endif #ifdef CONFIG_MACH_BADGER @@ -21898,16 +22681,16 @@ extern unsigned int __machine_arch_type; # define machine_is_celestialsemi() (0) #endif -#ifdef CONFIG_MACH_CC9M2443 +#ifdef CONFIG_MACH_CC9M2443JS # ifdef machine_arch_type # undef machine_arch_type # define machine_arch_type __machine_arch_type # else -# define machine_arch_type MACH_TYPE_CC9M2443 +# define machine_arch_type MACH_TYPE_CC9M2443JS # endif -# define machine_is_cc9m2443() (machine_arch_type == MACH_TYPE_CC9M2443) +# define machine_is_cc9m2443js() (machine_arch_type == MACH_TYPE_CC9M2443JS) #else -# define machine_is_cc9m2443() (0) +# define machine_is_cc9m2443js() (0) #endif #ifdef CONFIG_MACH_TW5334 @@ -23278,16 +24061,16 @@ extern unsigned int __machine_arch_type; # define machine_is_at572d940deb() (0) #endif -#ifdef CONFIG_MACH_DAVINCI_DA8XX_EVM +#ifdef CONFIG_MACH_DAVINCI_DA830_EVM # ifdef machine_arch_type # undef machine_arch_type # define machine_arch_type __machine_arch_type # else -# define machine_arch_type MACH_TYPE_DAVINCI_DA8XX_EVM +# define machine_arch_type MACH_TYPE_DAVINCI_DA830_EVM # endif -# define machine_is_davinci_da8xx_evm() (machine_arch_type == MACH_TYPE_DAVINCI_DA8XX_EVM) +# define machine_is_davinci_da830_evm() (machine_arch_type == MACH_TYPE_DAVINCI_DA830_EVM) #else -# define machine_is_davinci_da8xx_evm() (0) +# define machine_is_davinci_da830_evm() (0) #endif #ifdef CONFIG_MACH_EP9302 @@ -23362,6 +24145,18 @@ extern unsigned int __machine_arch_type; # define machine_is_nextio_n2800_ica() (0) #endif +#ifdef CONFIG_MACH_DOVE_DB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DOVE_DB +# endif +# define machine_is_dove_db() (machine_arch_type == MACH_TYPE_DOVE_DB) +#else +# define machine_is_dove_db() (0) +#endif + #ifdef CONFIG_MACH_MARVELL_NEWDB # ifdef machine_arch_type # undef machine_arch_type @@ -23369,9 +24164,9 @@ extern unsigned int __machine_arch_type; # else # define machine_arch_type MACH_TYPE_MARVELL_NEWDB # endif -# define machine_is_marvell_newdb() (machine_arch_type == MACH_TYPE_MARVELL_NEWDB) +# define machine_is_dove_avng() (machine_arch_type == MACH_TYPE_MARVELL_NEWDB) #else -# define machine_is_marvell_newdb() (0) +# define machine_is_dove_avng() (0) #endif #ifdef CONFIG_MACH_VANDIHUD @@ -23674,16 +24469,16 @@ extern unsigned int __machine_arch_type; # define machine_is_sam9_l9261() (0) #endif -#ifdef CONFIG_MACH_CC9M2443JS +#ifdef CONFIG_MACH_CC9M2443 # ifdef machine_arch_type # undef machine_arch_type # define machine_arch_type __machine_arch_type # else -# define machine_arch_type MACH_TYPE_CC9M2443JS +# define machine_arch_type MACH_TYPE_CC9M2443 # endif -# define machine_is_cc9m2443js() (machine_arch_type == MACH_TYPE_CC9M2443JS) +# define machine_is_cc9m2443() (machine_arch_type == MACH_TYPE_CC9M2443) #else -# define machine_is_cc9m2443js() (0) +# define machine_is_cc9m2443() (0) #endif #ifdef CONFIG_MACH_XARIA300 @@ -25601,9 +26396,9 @@ extern unsigned int __machine_arch_type; # else # define machine_arch_type MACH_TYPE_CPUIMX27 # endif -# define machine_is_cpuimx27() (machine_arch_type == MACH_TYPE_CPUIMX27) +# define machine_is_eukrea_cpuimx27() (machine_arch_type == MACH_TYPE_CPUIMX27) #else -# define machine_is_cpuimx27() (0) +# define machine_is_eukrea_cpuimx27() (0) #endif #ifdef CONFIG_MACH_CHEFLUX @@ -25966,14 +26761,14 @@ extern unsigned int __machine_arch_type; # define machine_is_linkstation_ls_hgl() (0) #endif -#ifdef CONFIG_MACH_HTCVENUS +#ifdef CONFIG_MACH_HTCKOVSKY # ifdef machine_arch_type # undef machine_arch_type # define machine_arch_type __machine_arch_type # else -# define machine_arch_type MACH_TYPE_HTCVENUS +# define machine_arch_type MACH_TYPE_HTCKOVSKY # endif -# define machine_is_htckovsky() (machine_arch_type == MACH_TYPE_HTCVENUS) +# define machine_is_htckovsky() (machine_arch_type == MACH_TYPE_HTCKOVSKY) #else # define machine_is_htckovsky() (0) #endif @@ -28990,6 +29785,9390 @@ extern unsigned int __machine_arch_type; # define machine_is_mcwebio() (0) #endif +#ifdef CONFIG_MACH_OMAP3_PHRAZER +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAP3_PHRAZER +# endif +# define machine_is_omap3_phrazer() (machine_arch_type == MACH_TYPE_OMAP3_PHRAZER) +#else +# define machine_is_omap3_phrazer() (0) +#endif + +#ifdef CONFIG_MACH_DARWIN +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DARWIN +# endif +# define machine_is_darwin() (machine_arch_type == MACH_TYPE_DARWIN) +#else +# define machine_is_darwin() (0) +#endif + +#ifdef CONFIG_MACH_ORATISCOMU +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ORATISCOMU +# endif +# define machine_is_oratiscomu() (machine_arch_type == MACH_TYPE_ORATISCOMU) +#else +# define machine_is_oratiscomu() (0) +#endif + +#ifdef CONFIG_MACH_RTSBC20 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_RTSBC20 +# endif +# define machine_is_rtsbc20() (machine_arch_type == MACH_TYPE_RTSBC20) +#else +# define machine_is_rtsbc20() (0) +#endif + +#ifdef CONFIG_MACH_I780 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_I780 +# endif +# define machine_is_sgh_i780() (machine_arch_type == MACH_TYPE_I780) +#else +# define machine_is_sgh_i780() (0) +#endif + +#ifdef CONFIG_MACH_GEMINI324 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_GEMINI324 +# endif +# define machine_is_gemini324() (machine_arch_type == MACH_TYPE_GEMINI324) +#else +# define machine_is_gemini324() (0) +#endif + +#ifdef CONFIG_MACH_ORATISLAN +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ORATISLAN +# endif +# define machine_is_oratislan() (machine_arch_type == MACH_TYPE_ORATISLAN) +#else +# define machine_is_oratislan() (0) +#endif + +#ifdef CONFIG_MACH_ORATISALOG +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ORATISALOG +# endif +# define machine_is_oratisalog() (machine_arch_type == MACH_TYPE_ORATISALOG) +#else +# define machine_is_oratisalog() (0) +#endif + +#ifdef CONFIG_MACH_ORATISMADI +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ORATISMADI +# endif +# define machine_is_oratismadi() (machine_arch_type == MACH_TYPE_ORATISMADI) +#else +# define machine_is_oratismadi() (0) +#endif + +#ifdef CONFIG_MACH_ORATISOT16 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ORATISOT16 +# endif +# define machine_is_oratisot16() (machine_arch_type == MACH_TYPE_ORATISOT16) +#else +# define machine_is_oratisot16() (0) +#endif + +#ifdef CONFIG_MACH_ORATISDESK +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ORATISDESK +# endif +# define machine_is_oratisdesk() (machine_arch_type == MACH_TYPE_ORATISDESK) +#else +# define machine_is_oratisdesk() (0) +#endif + +#ifdef CONFIG_MACH_VEXPRESS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_VEXPRESS +# endif +# define machine_is_vexpress() (machine_arch_type == MACH_TYPE_VEXPRESS) +#else +# define machine_is_vexpress() (0) +#endif + +#ifdef CONFIG_MACH_SINTEXO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SINTEXO +# endif +# define machine_is_sintexo() (machine_arch_type == MACH_TYPE_SINTEXO) +#else +# define machine_is_sintexo() (0) +#endif + +#ifdef CONFIG_MACH_CM3389 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CM3389 +# endif +# define machine_is_cm3389() (machine_arch_type == MACH_TYPE_CM3389) +#else +# define machine_is_cm3389() (0) +#endif + +#ifdef CONFIG_MACH_OMAP3_CIO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAP3_CIO +# endif +# define machine_is_omap3_cio() (machine_arch_type == MACH_TYPE_OMAP3_CIO) +#else +# define machine_is_omap3_cio() (0) +#endif + +#ifdef CONFIG_MACH_SGH_I900 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SGH_I900 +# endif +# define machine_is_sgh_i900() (machine_arch_type == MACH_TYPE_SGH_I900) +#else +# define machine_is_sgh_i900() (0) +#endif + +#ifdef CONFIG_MACH_BST100 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BST100 +# endif +# define machine_is_bst100() (machine_arch_type == MACH_TYPE_BST100) +#else +# define machine_is_bst100() (0) +#endif + +#ifdef CONFIG_MACH_PASSION +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PASSION +# endif +# define machine_is_passion() (machine_arch_type == MACH_TYPE_PASSION) +#else +# define machine_is_passion() (0) +#endif + +#ifdef CONFIG_MACH_INDESIGN_AT91SAM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_INDESIGN_AT91SAM +# endif +# define machine_is_indesign_at91sam() (machine_arch_type == MACH_TYPE_INDESIGN_AT91SAM) +#else +# define machine_is_indesign_at91sam() (0) +#endif + +#ifdef CONFIG_MACH_C4_BADGER +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_C4_BADGER +# endif +# define machine_is_c4_badger() (machine_arch_type == MACH_TYPE_C4_BADGER) +#else +# define machine_is_c4_badger() (0) +#endif + +#ifdef CONFIG_MACH_C4_VIPER +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_C4_VIPER +# endif +# define machine_is_c4_viper() (machine_arch_type == MACH_TYPE_C4_VIPER) +#else +# define machine_is_c4_viper() (0) +#endif + +#ifdef CONFIG_MACH_D2NET +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_D2NET +# endif +# define machine_is_d2net() (machine_arch_type == MACH_TYPE_D2NET) +#else +# define machine_is_d2net() (0) +#endif + +#ifdef CONFIG_MACH_BIGDISK +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BIGDISK +# endif +# define machine_is_bigdisk() (machine_arch_type == MACH_TYPE_BIGDISK) +#else +# define machine_is_bigdisk() (0) +#endif + +#ifdef CONFIG_MACH_NOTALVISION +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NOTALVISION +# endif +# define machine_is_notalvision() (machine_arch_type == MACH_TYPE_NOTALVISION) +#else +# define machine_is_notalvision() (0) +#endif + +#ifdef CONFIG_MACH_OMAP3_KBOC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAP3_KBOC +# endif +# define machine_is_omap3_kboc() (machine_arch_type == MACH_TYPE_OMAP3_KBOC) +#else +# define machine_is_omap3_kboc() (0) +#endif + +#ifdef CONFIG_MACH_CYCLONE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CYCLONE +# endif +# define machine_is_cyclone() (machine_arch_type == MACH_TYPE_CYCLONE) +#else +# define machine_is_cyclone() (0) +#endif + +#ifdef CONFIG_MACH_NINJA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NINJA +# endif +# define machine_is_ninja() (machine_arch_type == MACH_TYPE_NINJA) +#else +# define machine_is_ninja() (0) +#endif + +#ifdef CONFIG_MACH_AT91SAM9G20EK_2MMC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AT91SAM9G20EK_2MMC +# endif +# define machine_is_at91sam9g20ek_2mmc() (machine_arch_type == MACH_TYPE_AT91SAM9G20EK_2MMC) +#else +# define machine_is_at91sam9g20ek_2mmc() (0) +#endif + +#ifdef CONFIG_MACH_BCMRING +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BCMRING +# endif +# define machine_is_bcmring() (machine_arch_type == MACH_TYPE_BCMRING) +#else +# define machine_is_bcmring() (0) +#endif + +#ifdef CONFIG_MACH_RESOL_DL2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_RESOL_DL2 +# endif +# define machine_is_resol_dl2() (machine_arch_type == MACH_TYPE_RESOL_DL2) +#else +# define machine_is_resol_dl2() (0) +#endif + +#ifdef CONFIG_MACH_IFOSW +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IFOSW +# endif +# define machine_is_ifosw() (machine_arch_type == MACH_TYPE_IFOSW) +#else +# define machine_is_ifosw() (0) +#endif + +#ifdef CONFIG_MACH_HTCRHODIUM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HTCRHODIUM +# endif +# define machine_is_htcrhodium() (machine_arch_type == MACH_TYPE_HTCRHODIUM) +#else +# define machine_is_htcrhodium() (0) +#endif + +#ifdef CONFIG_MACH_HTCTOPAZ +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HTCTOPAZ +# endif +# define machine_is_htctopaz() (machine_arch_type == MACH_TYPE_HTCTOPAZ) +#else +# define machine_is_htctopaz() (0) +#endif + +#ifdef CONFIG_MACH_MATRIX504 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MATRIX504 +# endif +# define machine_is_matrix504() (machine_arch_type == MACH_TYPE_MATRIX504) +#else +# define machine_is_matrix504() (0) +#endif + +#ifdef CONFIG_MACH_MRFSA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MRFSA +# endif +# define machine_is_mrfsa() (machine_arch_type == MACH_TYPE_MRFSA) +#else +# define machine_is_mrfsa() (0) +#endif + +#ifdef CONFIG_MACH_SC_P270 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SC_P270 +# endif +# define machine_is_sc_p270() (machine_arch_type == MACH_TYPE_SC_P270) +#else +# define machine_is_sc_p270() (0) +#endif + +#ifdef CONFIG_MACH_ATLAS5_EVB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ATLAS5_EVB +# endif +# define machine_is_atlas5_evb() (machine_arch_type == MACH_TYPE_ATLAS5_EVB) +#else +# define machine_is_atlas5_evb() (0) +#endif + +#ifdef CONFIG_MACH_PELCO_LOBOX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PELCO_LOBOX +# endif +# define machine_is_pelco_lobox() (machine_arch_type == MACH_TYPE_PELCO_LOBOX) +#else +# define machine_is_pelco_lobox() (0) +#endif + +#ifdef CONFIG_MACH_DILAX_PCU200 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DILAX_PCU200 +# endif +# define machine_is_dilax_pcu200() (machine_arch_type == MACH_TYPE_DILAX_PCU200) +#else +# define machine_is_dilax_pcu200() (0) +#endif + +#ifdef CONFIG_MACH_LEONARDO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LEONARDO +# endif +# define machine_is_leonardo() (machine_arch_type == MACH_TYPE_LEONARDO) +#else +# define machine_is_leonardo() (0) +#endif + +#ifdef CONFIG_MACH_ZORAN_APPROACH7 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ZORAN_APPROACH7 +# endif +# define machine_is_zoran_approach7() (machine_arch_type == MACH_TYPE_ZORAN_APPROACH7) +#else +# define machine_is_zoran_approach7() (0) +#endif + +#ifdef CONFIG_MACH_DP6XX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DP6XX +# endif +# define machine_is_dp6xx() (machine_arch_type == MACH_TYPE_DP6XX) +#else +# define machine_is_dp6xx() (0) +#endif + +#ifdef CONFIG_MACH_BCM2153_VESPER +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BCM2153_VESPER +# endif +# define machine_is_bcm2153_vesper() (machine_arch_type == MACH_TYPE_BCM2153_VESPER) +#else +# define machine_is_bcm2153_vesper() (0) +#endif + +#ifdef CONFIG_MACH_MAHIMAHI +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MAHIMAHI +# endif +# define machine_is_mahimahi() (machine_arch_type == MACH_TYPE_MAHIMAHI) +#else +# define machine_is_mahimahi() (0) +#endif + +#ifdef CONFIG_MACH_CLICKC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CLICKC +# endif +# define machine_is_clickc() (machine_arch_type == MACH_TYPE_CLICKC) +#else +# define machine_is_clickc() (0) +#endif + +#ifdef CONFIG_MACH_ZB_GATEWAY +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ZB_GATEWAY +# endif +# define machine_is_zb_gateway() (machine_arch_type == MACH_TYPE_ZB_GATEWAY) +#else +# define machine_is_zb_gateway() (0) +#endif + +#ifdef CONFIG_MACH_TAZCARD +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TAZCARD +# endif +# define machine_is_tazcard() (machine_arch_type == MACH_TYPE_TAZCARD) +#else +# define machine_is_tazcard() (0) +#endif + +#ifdef CONFIG_MACH_TAZDEV +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TAZDEV +# endif +# define machine_is_tazdev() (machine_arch_type == MACH_TYPE_TAZDEV) +#else +# define machine_is_tazdev() (0) +#endif + +#ifdef CONFIG_MACH_ANNAX_CB_ARM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ANNAX_CB_ARM +# endif +# define machine_is_annax_cb_arm() (machine_arch_type == MACH_TYPE_ANNAX_CB_ARM) +#else +# define machine_is_annax_cb_arm() (0) +#endif + +#ifdef CONFIG_MACH_ANNAX_DM3 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ANNAX_DM3 +# endif +# define machine_is_annax_dm3() (machine_arch_type == MACH_TYPE_ANNAX_DM3) +#else +# define machine_is_annax_dm3() (0) +#endif + +#ifdef CONFIG_MACH_CEREBRIC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CEREBRIC +# endif +# define machine_is_cerebric() (machine_arch_type == MACH_TYPE_CEREBRIC) +#else +# define machine_is_cerebric() (0) +#endif + +#ifdef CONFIG_MACH_ORCA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ORCA +# endif +# define machine_is_orca() (machine_arch_type == MACH_TYPE_ORCA) +#else +# define machine_is_orca() (0) +#endif + +#ifdef CONFIG_MACH_PC9260 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PC9260 +# endif +# define machine_is_pc9260() (machine_arch_type == MACH_TYPE_PC9260) +#else +# define machine_is_pc9260() (0) +#endif + +#ifdef CONFIG_MACH_EMS285A +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EMS285A +# endif +# define machine_is_ems285a() (machine_arch_type == MACH_TYPE_EMS285A) +#else +# define machine_is_ems285a() (0) +#endif + +#ifdef CONFIG_MACH_GEC2410 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_GEC2410 +# endif +# define machine_is_gec2410() (machine_arch_type == MACH_TYPE_GEC2410) +#else +# define machine_is_gec2410() (0) +#endif + +#ifdef CONFIG_MACH_GEC2440 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_GEC2440 +# endif +# define machine_is_gec2440() (machine_arch_type == MACH_TYPE_GEC2440) +#else +# define machine_is_gec2440() (0) +#endif + +#ifdef CONFIG_MACH_ARCH_MW903 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ARCH_MW903 +# endif +# define machine_is_mw903() (machine_arch_type == MACH_TYPE_ARCH_MW903) +#else +# define machine_is_mw903() (0) +#endif + +#ifdef CONFIG_MACH_MW2440 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MW2440 +# endif +# define machine_is_mw2440() (machine_arch_type == MACH_TYPE_MW2440) +#else +# define machine_is_mw2440() (0) +#endif + +#ifdef CONFIG_MACH_ECAC2378 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ECAC2378 +# endif +# define machine_is_ecac2378() (machine_arch_type == MACH_TYPE_ECAC2378) +#else +# define machine_is_ecac2378() (0) +#endif + +#ifdef CONFIG_MACH_TAZKIOSK +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TAZKIOSK +# endif +# define machine_is_tazkiosk() (machine_arch_type == MACH_TYPE_TAZKIOSK) +#else +# define machine_is_tazkiosk() (0) +#endif + +#ifdef CONFIG_MACH_WHITERABBIT_MCH +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_WHITERABBIT_MCH +# endif +# define machine_is_whiterabbit_mch() (machine_arch_type == MACH_TYPE_WHITERABBIT_MCH) +#else +# define machine_is_whiterabbit_mch() (0) +#endif + +#ifdef CONFIG_MACH_SBOX9263 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SBOX9263 +# endif +# define machine_is_sbox9263() (machine_arch_type == MACH_TYPE_SBOX9263) +#else +# define machine_is_sbox9263() (0) +#endif + +#ifdef CONFIG_MACH_OREO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OREO +# endif +# define machine_is_oreo_camera() (machine_arch_type == MACH_TYPE_OREO) +#else +# define machine_is_oreo_camera() (0) +#endif + +#ifdef CONFIG_MACH_SMDK6442 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SMDK6442 +# endif +# define machine_is_smdk6442() (machine_arch_type == MACH_TYPE_SMDK6442) +#else +# define machine_is_smdk6442() (0) +#endif + +#ifdef CONFIG_MACH_OPENRD_BASE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OPENRD_BASE +# endif +# define machine_is_openrd_base() (machine_arch_type == MACH_TYPE_OPENRD_BASE) +#else +# define machine_is_openrd_base() (0) +#endif + +#ifdef CONFIG_MACH_INCREDIBLE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_INCREDIBLE +# endif +# define machine_is_incredible() (machine_arch_type == MACH_TYPE_INCREDIBLE) +#else +# define machine_is_incredible() (0) +#endif + +#ifdef CONFIG_MACH_INCREDIBLEC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_INCREDIBLEC +# endif +# define machine_is_incrediblec() (machine_arch_type == MACH_TYPE_INCREDIBLEC) +#else +# define machine_is_incrediblec() (0) +#endif + +#ifdef CONFIG_MACH_HEROCT +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HEROCT +# endif +# define machine_is_heroct() (machine_arch_type == MACH_TYPE_HEROCT) +#else +# define machine_is_heroct() (0) +#endif + +#ifdef CONFIG_MACH_MMNET1000 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MMNET1000 +# endif +# define machine_is_mmnet1000() (machine_arch_type == MACH_TYPE_MMNET1000) +#else +# define machine_is_mmnet1000() (0) +#endif + +#ifdef CONFIG_MACH_DEVKIT8000 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DEVKIT8000 +# endif +# define machine_is_devkit8000() (machine_arch_type == MACH_TYPE_DEVKIT8000) +#else +# define machine_is_devkit8000() (0) +#endif + +#ifdef CONFIG_MACH_DEVKIT9000 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DEVKIT9000 +# endif +# define machine_is_devkit9000() (machine_arch_type == MACH_TYPE_DEVKIT9000) +#else +# define machine_is_devkit9000() (0) +#endif + +#ifdef CONFIG_MACH_MX31TXTR +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MX31TXTR +# endif +# define machine_is_mx31txtr() (machine_arch_type == MACH_TYPE_MX31TXTR) +#else +# define machine_is_mx31txtr() (0) +#endif + +#ifdef CONFIG_MACH_U380 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_U380 +# endif +# define machine_is_u380() (machine_arch_type == MACH_TYPE_U380) +#else +# define machine_is_u380() (0) +#endif + +#ifdef CONFIG_MACH_HUALU_BOARD +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HUALU_BOARD +# endif +# define machine_is_oamp3_hualu() (machine_arch_type == MACH_TYPE_HUALU_BOARD) +#else +# define machine_is_oamp3_hualu() (0) +#endif + +#ifdef CONFIG_MACH_NPCMX50 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NPCMX50 +# endif +# define machine_is_npcmx50() (machine_arch_type == MACH_TYPE_NPCMX50) +#else +# define machine_is_npcmx50() (0) +#endif + +#ifdef CONFIG_MACH_MX51_LANGE51 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MX51_LANGE51 +# endif +# define machine_is_mx51_lange51() (machine_arch_type == MACH_TYPE_MX51_LANGE51) +#else +# define machine_is_mx51_lange51() (0) +#endif + +#ifdef CONFIG_MACH_MX51_LANGE52 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MX51_LANGE52 +# endif +# define machine_is_mx51_lange52() (machine_arch_type == MACH_TYPE_MX51_LANGE52) +#else +# define machine_is_mx51_lange52() (0) +#endif + +#ifdef CONFIG_MACH_RIOM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_RIOM +# endif +# define machine_is_riom() (machine_arch_type == MACH_TYPE_RIOM) +#else +# define machine_is_riom() (0) +#endif + +#ifdef CONFIG_MACH_COMCAS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_COMCAS +# endif +# define machine_is_comcas() (machine_arch_type == MACH_TYPE_COMCAS) +#else +# define machine_is_comcas() (0) +#endif + +#ifdef CONFIG_MACH_WSI_MX27 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_WSI_MX27 +# endif +# define machine_is_wsi_mx27() (machine_arch_type == MACH_TYPE_WSI_MX27) +#else +# define machine_is_wsi_mx27() (0) +#endif + +#ifdef CONFIG_MACH_CM_T35 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CM_T35 +# endif +# define machine_is_cm_t35() (machine_arch_type == MACH_TYPE_CM_T35) +#else +# define machine_is_cm_t35() (0) +#endif + +#ifdef CONFIG_MACH_NET2BIG +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NET2BIG +# endif +# define machine_is_net2big() (machine_arch_type == MACH_TYPE_NET2BIG) +#else +# define machine_is_net2big() (0) +#endif + +#ifdef CONFIG_MACH_MOTOROLA_A1600 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MOTOROLA_A1600 +# endif +# define machine_is_motorola_a1600() (machine_arch_type == MACH_TYPE_MOTOROLA_A1600) +#else +# define machine_is_motorola_a1600() (0) +#endif + +#ifdef CONFIG_MACH_IGEP0020 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IGEP0020 +# endif +# define machine_is_igep0020() (machine_arch_type == MACH_TYPE_IGEP0020) +#else +# define machine_is_igep0020() (0) +#endif + +#ifdef CONFIG_MACH_IGEP0010 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IGEP0010 +# endif +# define machine_is_igep0010() (machine_arch_type == MACH_TYPE_IGEP0010) +#else +# define machine_is_igep0010() (0) +#endif + +#ifdef CONFIG_MACH_MV6281GTWGE2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MV6281GTWGE2 +# endif +# define machine_is_mv6281gtwge2() (machine_arch_type == MACH_TYPE_MV6281GTWGE2) +#else +# define machine_is_mv6281gtwge2() (0) +#endif + +#ifdef CONFIG_MACH_SCAT100 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SCAT100 +# endif +# define machine_is_scat100() (machine_arch_type == MACH_TYPE_SCAT100) +#else +# define machine_is_scat100() (0) +#endif + +#ifdef CONFIG_MACH_SANMINA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SANMINA +# endif +# define machine_is_sanmina() (machine_arch_type == MACH_TYPE_SANMINA) +#else +# define machine_is_sanmina() (0) +#endif + +#ifdef CONFIG_MACH_MOMENTO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MOMENTO +# endif +# define machine_is_momento() (machine_arch_type == MACH_TYPE_MOMENTO) +#else +# define machine_is_momento() (0) +#endif + +#ifdef CONFIG_MACH_NUC9XX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NUC9XX +# endif +# define machine_is_nuc9xx() (machine_arch_type == MACH_TYPE_NUC9XX) +#else +# define machine_is_nuc9xx() (0) +#endif + +#ifdef CONFIG_MACH_NUC910EVB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NUC910EVB +# endif +# define machine_is_nuc910evb() (machine_arch_type == MACH_TYPE_NUC910EVB) +#else +# define machine_is_nuc910evb() (0) +#endif + +#ifdef CONFIG_MACH_NUC920EVB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NUC920EVB +# endif +# define machine_is_nuc920evb() (machine_arch_type == MACH_TYPE_NUC920EVB) +#else +# define machine_is_nuc920evb() (0) +#endif + +#ifdef CONFIG_MACH_NUC950EVB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NUC950EVB +# endif +# define machine_is_nuc950evb() (machine_arch_type == MACH_TYPE_NUC950EVB) +#else +# define machine_is_nuc950evb() (0) +#endif + +#ifdef CONFIG_MACH_NUC945EVB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NUC945EVB +# endif +# define machine_is_nuc945evb() (machine_arch_type == MACH_TYPE_NUC945EVB) +#else +# define machine_is_nuc945evb() (0) +#endif + +#ifdef CONFIG_MACH_NUC960EVB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NUC960EVB +# endif +# define machine_is_nuc960evb() (machine_arch_type == MACH_TYPE_NUC960EVB) +#else +# define machine_is_nuc960evb() (0) +#endif + +#ifdef CONFIG_MACH_NUC932EVB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NUC932EVB +# endif +# define machine_is_nuc932evb() (machine_arch_type == MACH_TYPE_NUC932EVB) +#else +# define machine_is_nuc932evb() (0) +#endif + +#ifdef CONFIG_MACH_NUC900 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NUC900 +# endif +# define machine_is_nuc900() (machine_arch_type == MACH_TYPE_NUC900) +#else +# define machine_is_nuc900() (0) +#endif + +#ifdef CONFIG_MACH_SD1SOC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SD1SOC +# endif +# define machine_is_sd1soc() (machine_arch_type == MACH_TYPE_SD1SOC) +#else +# define machine_is_sd1soc() (0) +#endif + +#ifdef CONFIG_MACH_LN2440BC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LN2440BC +# endif +# define machine_is_ln2440bc() (machine_arch_type == MACH_TYPE_LN2440BC) +#else +# define machine_is_ln2440bc() (0) +#endif + +#ifdef CONFIG_MACH_RSBC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_RSBC +# endif +# define machine_is_rsbc() (machine_arch_type == MACH_TYPE_RSBC) +#else +# define machine_is_rsbc() (0) +#endif + +#ifdef CONFIG_MACH_OPENRD_CLIENT +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OPENRD_CLIENT +# endif +# define machine_is_openrd_client() (machine_arch_type == MACH_TYPE_OPENRD_CLIENT) +#else +# define machine_is_openrd_client() (0) +#endif + +#ifdef CONFIG_MACH_HPIPAQ11X +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HPIPAQ11X +# endif +# define machine_is_hpipaq11x() (machine_arch_type == MACH_TYPE_HPIPAQ11X) +#else +# define machine_is_hpipaq11x() (0) +#endif + +#ifdef CONFIG_MACH_WAYLAND +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_WAYLAND +# endif +# define machine_is_wayland() (machine_arch_type == MACH_TYPE_WAYLAND) +#else +# define machine_is_wayland() (0) +#endif + +#ifdef CONFIG_MACH_ACNBSX102 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ACNBSX102 +# endif +# define machine_is_acnbsx102() (machine_arch_type == MACH_TYPE_ACNBSX102) +#else +# define machine_is_acnbsx102() (0) +#endif + +#ifdef CONFIG_MACH_HWAT91 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HWAT91 +# endif +# define machine_is_hwat91() (machine_arch_type == MACH_TYPE_HWAT91) +#else +# define machine_is_hwat91() (0) +#endif + +#ifdef CONFIG_MACH_AT91SAM9263CS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AT91SAM9263CS +# endif +# define machine_is_at91sam9263cs() (machine_arch_type == MACH_TYPE_AT91SAM9263CS) +#else +# define machine_is_at91sam9263cs() (0) +#endif + +#ifdef CONFIG_MACH_CSB732 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CSB732 +# endif +# define machine_is_csb732() (machine_arch_type == MACH_TYPE_CSB732) +#else +# define machine_is_csb732() (0) +#endif + +#ifdef CONFIG_MACH_U8500 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_U8500 +# endif +# define machine_is_u8500() (machine_arch_type == MACH_TYPE_U8500) +#else +# define machine_is_u8500() (0) +#endif + +#ifdef CONFIG_MACH_HUQIU +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HUQIU +# endif +# define machine_is_huqiu() (machine_arch_type == MACH_TYPE_HUQIU) +#else +# define machine_is_huqiu() (0) +#endif + +#ifdef CONFIG_MACH_MX51_KUNLUN +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MX51_KUNLUN +# endif +# define machine_is_mx51_kunlun() (machine_arch_type == MACH_TYPE_MX51_KUNLUN) +#else +# define machine_is_mx51_kunlun() (0) +#endif + +#ifdef CONFIG_MACH_PMT1G +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PMT1G +# endif +# define machine_is_pmt1g() (machine_arch_type == MACH_TYPE_PMT1G) +#else +# define machine_is_pmt1g() (0) +#endif + +#ifdef CONFIG_MACH_HTCELF +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HTCELF +# endif +# define machine_is_htcelf() (machine_arch_type == MACH_TYPE_HTCELF) +#else +# define machine_is_htcelf() (0) +#endif + +#ifdef CONFIG_MACH_ARMADILLO420 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ARMADILLO420 +# endif +# define machine_is_armadillo420() (machine_arch_type == MACH_TYPE_ARMADILLO420) +#else +# define machine_is_armadillo420() (0) +#endif + +#ifdef CONFIG_MACH_ARMADILLO440 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ARMADILLO440 +# endif +# define machine_is_armadillo440() (machine_arch_type == MACH_TYPE_ARMADILLO440) +#else +# define machine_is_armadillo440() (0) +#endif + +#ifdef CONFIG_MACH_U_CHIP_DUAL_ARM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_U_CHIP_DUAL_ARM +# endif +# define machine_is_u_chip_dual_arm() (machine_arch_type == MACH_TYPE_U_CHIP_DUAL_ARM) +#else +# define machine_is_u_chip_dual_arm() (0) +#endif + +#ifdef CONFIG_MACH_CSR_BDB3 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CSR_BDB3 +# endif +# define machine_is_csr_bdb3() (machine_arch_type == MACH_TYPE_CSR_BDB3) +#else +# define machine_is_csr_bdb3() (0) +#endif + +#ifdef CONFIG_MACH_DOLBY_CAT1018 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DOLBY_CAT1018 +# endif +# define machine_is_dolby_cat1018() (machine_arch_type == MACH_TYPE_DOLBY_CAT1018) +#else +# define machine_is_dolby_cat1018() (0) +#endif + +#ifdef CONFIG_MACH_HY9307 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HY9307 +# endif +# define machine_is_hy9307() (machine_arch_type == MACH_TYPE_HY9307) +#else +# define machine_is_hy9307() (0) +#endif + +#ifdef CONFIG_MACH_A_ES +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_A_ES +# endif +# define machine_is_aspire_easystore() (machine_arch_type == MACH_TYPE_A_ES) +#else +# define machine_is_aspire_easystore() (0) +#endif + +#ifdef CONFIG_MACH_DAVINCI_IRIF +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DAVINCI_IRIF +# endif +# define machine_is_davinci_irif() (machine_arch_type == MACH_TYPE_DAVINCI_IRIF) +#else +# define machine_is_davinci_irif() (0) +#endif + +#ifdef CONFIG_MACH_AGAMA9263 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AGAMA9263 +# endif +# define machine_is_agama9263() (machine_arch_type == MACH_TYPE_AGAMA9263) +#else +# define machine_is_agama9263() (0) +#endif + +#ifdef CONFIG_MACH_MARVELL_JASPER +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MARVELL_JASPER +# endif +# define machine_is_marvell_jasper() (machine_arch_type == MACH_TYPE_MARVELL_JASPER) +#else +# define machine_is_marvell_jasper() (0) +#endif + +#ifdef CONFIG_MACH_FLINT +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_FLINT +# endif +# define machine_is_flint() (machine_arch_type == MACH_TYPE_FLINT) +#else +# define machine_is_flint() (0) +#endif + +#ifdef CONFIG_MACH_TAVOREVB3 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TAVOREVB3 +# endif +# define machine_is_tavorevb3() (machine_arch_type == MACH_TYPE_TAVOREVB3) +#else +# define machine_is_tavorevb3() (0) +#endif + +#ifdef CONFIG_MACH_SCH_M490 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SCH_M490 +# endif +# define machine_is_sch_m490() (machine_arch_type == MACH_TYPE_SCH_M490) +#else +# define machine_is_sch_m490() (0) +#endif + +#ifdef CONFIG_MACH_RBL01 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_RBL01 +# endif +# define machine_is_rbl01() (machine_arch_type == MACH_TYPE_RBL01) +#else +# define machine_is_rbl01() (0) +#endif + +#ifdef CONFIG_MACH_OMNIFI +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMNIFI +# endif +# define machine_is_omnifi() (machine_arch_type == MACH_TYPE_OMNIFI) +#else +# define machine_is_omnifi() (0) +#endif + +#ifdef CONFIG_MACH_OTAVALO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OTAVALO +# endif +# define machine_is_otavalo() (machine_arch_type == MACH_TYPE_OTAVALO) +#else +# define machine_is_otavalo() (0) +#endif + +#ifdef CONFIG_MACH_SIENNA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SIENNA +# endif +# define machine_is_siena() (machine_arch_type == MACH_TYPE_SIENNA) +#else +# define machine_is_siena() (0) +#endif + +#ifdef CONFIG_MACH_HTC_EXCALIBUR_S620 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HTC_EXCALIBUR_S620 +# endif +# define machine_is_htc_excalibur_s620() (machine_arch_type == MACH_TYPE_HTC_EXCALIBUR_S620) +#else +# define machine_is_htc_excalibur_s620() (0) +#endif + +#ifdef CONFIG_MACH_HTC_OPAL +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HTC_OPAL +# endif +# define machine_is_htc_opal() (machine_arch_type == MACH_TYPE_HTC_OPAL) +#else +# define machine_is_htc_opal() (0) +#endif + +#ifdef CONFIG_MACH_TOUCHBOOK +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TOUCHBOOK +# endif +# define machine_is_touchbook() (machine_arch_type == MACH_TYPE_TOUCHBOOK) +#else +# define machine_is_touchbook() (0) +#endif + +#ifdef CONFIG_MACH_LATTE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LATTE +# endif +# define machine_is_latte() (machine_arch_type == MACH_TYPE_LATTE) +#else +# define machine_is_latte() (0) +#endif + +#ifdef CONFIG_MACH_XA200 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_XA200 +# endif +# define machine_is_xa200() (machine_arch_type == MACH_TYPE_XA200) +#else +# define machine_is_xa200() (0) +#endif + +#ifdef CONFIG_MACH_NIMROD +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NIMROD +# endif +# define machine_is_nimrod() (machine_arch_type == MACH_TYPE_NIMROD) +#else +# define machine_is_nimrod() (0) +#endif + +#ifdef CONFIG_MACH_CC9P9215_3G +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CC9P9215_3G +# endif +# define machine_is_cc9p9215_3g() (machine_arch_type == MACH_TYPE_CC9P9215_3G) +#else +# define machine_is_cc9p9215_3g() (0) +#endif + +#ifdef CONFIG_MACH_CC9P9215_3GJS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CC9P9215_3GJS +# endif +# define machine_is_cc9p9215_3gjs() (machine_arch_type == MACH_TYPE_CC9P9215_3GJS) +#else +# define machine_is_cc9p9215_3gjs() (0) +#endif + +#ifdef CONFIG_MACH_TK71 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TK71 +# endif +# define machine_is_tk71() (machine_arch_type == MACH_TYPE_TK71) +#else +# define machine_is_tk71() (0) +#endif + +#ifdef CONFIG_MACH_COMHAM3525 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_COMHAM3525 +# endif +# define machine_is_comham3525() (machine_arch_type == MACH_TYPE_COMHAM3525) +#else +# define machine_is_comham3525() (0) +#endif + +#ifdef CONFIG_MACH_MX31EREBUS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MX31EREBUS +# endif +# define machine_is_mx31erebus() (machine_arch_type == MACH_TYPE_MX31EREBUS) +#else +# define machine_is_mx31erebus() (0) +#endif + +#ifdef CONFIG_MACH_MCARDMX27 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MCARDMX27 +# endif +# define machine_is_mcardmx27() (machine_arch_type == MACH_TYPE_MCARDMX27) +#else +# define machine_is_mcardmx27() (0) +#endif + +#ifdef CONFIG_MACH_PARADISE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PARADISE +# endif +# define machine_is_paradise() (machine_arch_type == MACH_TYPE_PARADISE) +#else +# define machine_is_paradise() (0) +#endif + +#ifdef CONFIG_MACH_TIDE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TIDE +# endif +# define machine_is_tide() (machine_arch_type == MACH_TYPE_TIDE) +#else +# define machine_is_tide() (0) +#endif + +#ifdef CONFIG_MACH_WZL2440 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_WZL2440 +# endif +# define machine_is_wzl2440() (machine_arch_type == MACH_TYPE_WZL2440) +#else +# define machine_is_wzl2440() (0) +#endif + +#ifdef CONFIG_MACH_SDRDEMO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SDRDEMO +# endif +# define machine_is_sdrdemo() (machine_arch_type == MACH_TYPE_SDRDEMO) +#else +# define machine_is_sdrdemo() (0) +#endif + +#ifdef CONFIG_MACH_ETHERCAN2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ETHERCAN2 +# endif +# define machine_is_ethercan2() (machine_arch_type == MACH_TYPE_ETHERCAN2) +#else +# define machine_is_ethercan2() (0) +#endif + +#ifdef CONFIG_MACH_ECMIMG20 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ECMIMG20 +# endif +# define machine_is_ecmimg20() (machine_arch_type == MACH_TYPE_ECMIMG20) +#else +# define machine_is_ecmimg20() (0) +#endif + +#ifdef CONFIG_MACH_OMAP_DRAGON +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAP_DRAGON +# endif +# define machine_is_omap_dragon() (machine_arch_type == MACH_TYPE_OMAP_DRAGON) +#else +# define machine_is_omap_dragon() (0) +#endif + +#ifdef CONFIG_MACH_HALO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HALO +# endif +# define machine_is_halo() (machine_arch_type == MACH_TYPE_HALO) +#else +# define machine_is_halo() (0) +#endif + +#ifdef CONFIG_MACH_HUANGSHAN +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HUANGSHAN +# endif +# define machine_is_huangshan() (machine_arch_type == MACH_TYPE_HUANGSHAN) +#else +# define machine_is_huangshan() (0) +#endif + +#ifdef CONFIG_MACH_VL_MA2SC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_VL_MA2SC +# endif +# define machine_is_vl_ma2sc() (machine_arch_type == MACH_TYPE_VL_MA2SC) +#else +# define machine_is_vl_ma2sc() (0) +#endif + +#ifdef CONFIG_MACH_RAUMFELD_RC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_RAUMFELD_RC +# endif +# define machine_is_raumfeld_rc() (machine_arch_type == MACH_TYPE_RAUMFELD_RC) +#else +# define machine_is_raumfeld_rc() (0) +#endif + +#ifdef CONFIG_MACH_RAUMFELD_CONNECTOR +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_RAUMFELD_CONNECTOR +# endif +# define machine_is_raumfeld_connector() (machine_arch_type == MACH_TYPE_RAUMFELD_CONNECTOR) +#else +# define machine_is_raumfeld_connector() (0) +#endif + +#ifdef CONFIG_MACH_RAUMFELD_SPEAKER +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_RAUMFELD_SPEAKER +# endif +# define machine_is_raumfeld_speaker() (machine_arch_type == MACH_TYPE_RAUMFELD_SPEAKER) +#else +# define machine_is_raumfeld_speaker() (0) +#endif + +#ifdef CONFIG_MACH_MULTIBUS_MASTER +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MULTIBUS_MASTER +# endif +# define machine_is_multibus_master() (machine_arch_type == MACH_TYPE_MULTIBUS_MASTER) +#else +# define machine_is_multibus_master() (0) +#endif + +#ifdef CONFIG_MACH_MULTIBUS_PBK +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MULTIBUS_PBK +# endif +# define machine_is_multibus_pbk() (machine_arch_type == MACH_TYPE_MULTIBUS_PBK) +#else +# define machine_is_multibus_pbk() (0) +#endif + +#ifdef CONFIG_MACH_TNETV107X +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TNETV107X +# endif +# define machine_is_tnetv107x() (machine_arch_type == MACH_TYPE_TNETV107X) +#else +# define machine_is_tnetv107x() (0) +#endif + +#ifdef CONFIG_MACH_SNAKE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SNAKE +# endif +# define machine_is_snake() (machine_arch_type == MACH_TYPE_SNAKE) +#else +# define machine_is_snake() (0) +#endif + +#ifdef CONFIG_MACH_CWMX27 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CWMX27 +# endif +# define machine_is_cwmx27() (machine_arch_type == MACH_TYPE_CWMX27) +#else +# define machine_is_cwmx27() (0) +#endif + +#ifdef CONFIG_MACH_SCH_M480 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SCH_M480 +# endif +# define machine_is_sch_m480() (machine_arch_type == MACH_TYPE_SCH_M480) +#else +# define machine_is_sch_m480() (0) +#endif + +#ifdef CONFIG_MACH_PLATYPUS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PLATYPUS +# endif +# define machine_is_platypus() (machine_arch_type == MACH_TYPE_PLATYPUS) +#else +# define machine_is_platypus() (0) +#endif + +#ifdef CONFIG_MACH_PSS2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PSS2 +# endif +# define machine_is_pss2() (machine_arch_type == MACH_TYPE_PSS2) +#else +# define machine_is_pss2() (0) +#endif + +#ifdef CONFIG_MACH_DAVINCI_APM150 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DAVINCI_APM150 +# endif +# define machine_is_davinci_apm150() (machine_arch_type == MACH_TYPE_DAVINCI_APM150) +#else +# define machine_is_davinci_apm150() (0) +#endif + +#ifdef CONFIG_MACH_STR9100 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_STR9100 +# endif +# define machine_is_str9100() (machine_arch_type == MACH_TYPE_STR9100) +#else +# define machine_is_str9100() (0) +#endif + +#ifdef CONFIG_MACH_NET5BIG +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NET5BIG +# endif +# define machine_is_net5big() (machine_arch_type == MACH_TYPE_NET5BIG) +#else +# define machine_is_net5big() (0) +#endif + +#ifdef CONFIG_MACH_SEABED9263 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SEABED9263 +# endif +# define machine_is_seabed9263() (machine_arch_type == MACH_TYPE_SEABED9263) +#else +# define machine_is_seabed9263() (0) +#endif + +#ifdef CONFIG_MACH_MX51_M2ID +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MX51_M2ID +# endif +# define machine_is_mx51_m2id() (machine_arch_type == MACH_TYPE_MX51_M2ID) +#else +# define machine_is_mx51_m2id() (0) +#endif + +#ifdef CONFIG_MACH_OCTVOCPLUS_EB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OCTVOCPLUS_EB +# endif +# define machine_is_octvocplus_eb() (machine_arch_type == MACH_TYPE_OCTVOCPLUS_EB) +#else +# define machine_is_octvocplus_eb() (0) +#endif + +#ifdef CONFIG_MACH_KLK_FIREFOX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_KLK_FIREFOX +# endif +# define machine_is_klk_firefox() (machine_arch_type == MACH_TYPE_KLK_FIREFOX) +#else +# define machine_is_klk_firefox() (0) +#endif + +#ifdef CONFIG_MACH_KLK_WIRMA_MODULE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_KLK_WIRMA_MODULE +# endif +# define machine_is_klk_wirma_module() (machine_arch_type == MACH_TYPE_KLK_WIRMA_MODULE) +#else +# define machine_is_klk_wirma_module() (0) +#endif + +#ifdef CONFIG_MACH_KLK_WIRMA_MMI +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_KLK_WIRMA_MMI +# endif +# define machine_is_klk_wirma_mmi() (machine_arch_type == MACH_TYPE_KLK_WIRMA_MMI) +#else +# define machine_is_klk_wirma_mmi() (0) +#endif + +#ifdef CONFIG_MACH_SUPERSONIC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SUPERSONIC +# endif +# define machine_is_supersonic() (machine_arch_type == MACH_TYPE_SUPERSONIC) +#else +# define machine_is_supersonic() (0) +#endif + +#ifdef CONFIG_MACH_LIBERTY +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LIBERTY +# endif +# define machine_is_liberty() (machine_arch_type == MACH_TYPE_LIBERTY) +#else +# define machine_is_liberty() (0) +#endif + +#ifdef CONFIG_MACH_MH355 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MH355 +# endif +# define machine_is_mh355() (machine_arch_type == MACH_TYPE_MH355) +#else +# define machine_is_mh355() (0) +#endif + +#ifdef CONFIG_MACH_PC7802 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PC7802 +# endif +# define machine_is_pc7802() (machine_arch_type == MACH_TYPE_PC7802) +#else +# define machine_is_pc7802() (0) +#endif + +#ifdef CONFIG_MACH_GNET_SGC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_GNET_SGC +# endif +# define machine_is_gnet_sgc() (machine_arch_type == MACH_TYPE_GNET_SGC) +#else +# define machine_is_gnet_sgc() (0) +#endif + +#ifdef CONFIG_MACH_EINSTEIN15 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EINSTEIN15 +# endif +# define machine_is_einstein15() (machine_arch_type == MACH_TYPE_EINSTEIN15) +#else +# define machine_is_einstein15() (0) +#endif + +#ifdef CONFIG_MACH_CMPD +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CMPD +# endif +# define machine_is_cmpd() (machine_arch_type == MACH_TYPE_CMPD) +#else +# define machine_is_cmpd() (0) +#endif + +#ifdef CONFIG_MACH_DAVINCI_HASE1 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DAVINCI_HASE1 +# endif +# define machine_is_davinci_hase1() (machine_arch_type == MACH_TYPE_DAVINCI_HASE1) +#else +# define machine_is_davinci_hase1() (0) +#endif + +#ifdef CONFIG_MACH_LGEINCITEPHONE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LGEINCITEPHONE +# endif +# define machine_is_lgeincitephone() (machine_arch_type == MACH_TYPE_LGEINCITEPHONE) +#else +# define machine_is_lgeincitephone() (0) +#endif + +#ifdef CONFIG_MACH_EA313X +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EA313X +# endif +# define machine_is_ea313x() (machine_arch_type == MACH_TYPE_EA313X) +#else +# define machine_is_ea313x() (0) +#endif + +#ifdef CONFIG_MACH_FWBD_39064 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_FWBD_39064 +# endif +# define machine_is_fwbd_39064() (machine_arch_type == MACH_TYPE_FWBD_39064) +#else +# define machine_is_fwbd_39064() (0) +#endif + +#ifdef CONFIG_MACH_FWBD_390128 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_FWBD_390128 +# endif +# define machine_is_fwbd_390128() (machine_arch_type == MACH_TYPE_FWBD_390128) +#else +# define machine_is_fwbd_390128() (0) +#endif + +#ifdef CONFIG_MACH_PELCO_MOE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PELCO_MOE +# endif +# define machine_is_pelco_moe() (machine_arch_type == MACH_TYPE_PELCO_MOE) +#else +# define machine_is_pelco_moe() (0) +#endif + +#ifdef CONFIG_MACH_MINIMIX27 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MINIMIX27 +# endif +# define machine_is_minimix27() (machine_arch_type == MACH_TYPE_MINIMIX27) +#else +# define machine_is_minimix27() (0) +#endif + +#ifdef CONFIG_MACH_OMAP3_THUNDER +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAP3_THUNDER +# endif +# define machine_is_omap3_thunder() (machine_arch_type == MACH_TYPE_OMAP3_THUNDER) +#else +# define machine_is_omap3_thunder() (0) +#endif + +#ifdef CONFIG_MACH_PASSIONC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PASSIONC +# endif +# define machine_is_passionc() (machine_arch_type == MACH_TYPE_PASSIONC) +#else +# define machine_is_passionc() (0) +#endif + +#ifdef CONFIG_MACH_MX27AMATA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MX27AMATA +# endif +# define machine_is_mx27amata() (machine_arch_type == MACH_TYPE_MX27AMATA) +#else +# define machine_is_mx27amata() (0) +#endif + +#ifdef CONFIG_MACH_BGAT1 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BGAT1 +# endif +# define machine_is_bgat1() (machine_arch_type == MACH_TYPE_BGAT1) +#else +# define machine_is_bgat1() (0) +#endif + +#ifdef CONFIG_MACH_BUZZ +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BUZZ +# endif +# define machine_is_buzz() (machine_arch_type == MACH_TYPE_BUZZ) +#else +# define machine_is_buzz() (0) +#endif + +#ifdef CONFIG_MACH_MB9G20 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MB9G20 +# endif +# define machine_is_mb9g20() (machine_arch_type == MACH_TYPE_MB9G20) +#else +# define machine_is_mb9g20() (0) +#endif + +#ifdef CONFIG_MACH_YUSHAN +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_YUSHAN +# endif +# define machine_is_yushan() (machine_arch_type == MACH_TYPE_YUSHAN) +#else +# define machine_is_yushan() (0) +#endif + +#ifdef CONFIG_MACH_LIZARD +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LIZARD +# endif +# define machine_is_lizard() (machine_arch_type == MACH_TYPE_LIZARD) +#else +# define machine_is_lizard() (0) +#endif + +#ifdef CONFIG_MACH_OMAP3POLYCOM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAP3POLYCOM +# endif +# define machine_is_omap3polycom() (machine_arch_type == MACH_TYPE_OMAP3POLYCOM) +#else +# define machine_is_omap3polycom() (0) +#endif + +#ifdef CONFIG_MACH_SMDKV210 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SMDKV210 +# endif +# define machine_is_smdkv210() (machine_arch_type == MACH_TYPE_SMDKV210) +#else +# define machine_is_smdkv210() (0) +#endif + +#ifdef CONFIG_MACH_BRAVO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BRAVO +# endif +# define machine_is_bravo() (machine_arch_type == MACH_TYPE_BRAVO) +#else +# define machine_is_bravo() (0) +#endif + +#ifdef CONFIG_MACH_SIOGENTOO1 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SIOGENTOO1 +# endif +# define machine_is_siogentoo1() (machine_arch_type == MACH_TYPE_SIOGENTOO1) +#else +# define machine_is_siogentoo1() (0) +#endif + +#ifdef CONFIG_MACH_SIOGENTOO2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SIOGENTOO2 +# endif +# define machine_is_siogentoo2() (machine_arch_type == MACH_TYPE_SIOGENTOO2) +#else +# define machine_is_siogentoo2() (0) +#endif + +#ifdef CONFIG_MACH_SM3K +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SM3K +# endif +# define machine_is_sm3k() (machine_arch_type == MACH_TYPE_SM3K) +#else +# define machine_is_sm3k() (0) +#endif + +#ifdef CONFIG_MACH_ACER_TEMPO_F900 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ACER_TEMPO_F900 +# endif +# define machine_is_acer_tempo_f900() (machine_arch_type == MACH_TYPE_ACER_TEMPO_F900) +#else +# define machine_is_acer_tempo_f900() (0) +#endif + +#ifdef CONFIG_MACH_SST61VC010_DEV +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SST61VC010_DEV +# endif +# define machine_is_sst61vc010_dev() (machine_arch_type == MACH_TYPE_SST61VC010_DEV) +#else +# define machine_is_sst61vc010_dev() (0) +#endif + +#ifdef CONFIG_MACH_GLITTERTIND +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_GLITTERTIND +# endif +# define machine_is_glittertind() (machine_arch_type == MACH_TYPE_GLITTERTIND) +#else +# define machine_is_glittertind() (0) +#endif + +#ifdef CONFIG_MACH_OMAP_ZOOM3 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAP_ZOOM3 +# endif +# define machine_is_omap_zoom3() (machine_arch_type == MACH_TYPE_OMAP_ZOOM3) +#else +# define machine_is_omap_zoom3() (0) +#endif + +#ifdef CONFIG_MACH_OMAP_3630SDP +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAP_3630SDP +# endif +# define machine_is_omap_3630sdp() (machine_arch_type == MACH_TYPE_OMAP_3630SDP) +#else +# define machine_is_omap_3630sdp() (0) +#endif + +#ifdef CONFIG_MACH_CYBOOK2440 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CYBOOK2440 +# endif +# define machine_is_cybook2440() (machine_arch_type == MACH_TYPE_CYBOOK2440) +#else +# define machine_is_cybook2440() (0) +#endif + +#ifdef CONFIG_MACH_TORINO_S +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TORINO_S +# endif +# define machine_is_torino_s() (machine_arch_type == MACH_TYPE_TORINO_S) +#else +# define machine_is_torino_s() (0) +#endif + +#ifdef CONFIG_MACH_HAVANA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HAVANA +# endif +# define machine_is_havana() (machine_arch_type == MACH_TYPE_HAVANA) +#else +# define machine_is_havana() (0) +#endif + +#ifdef CONFIG_MACH_BEAUMONT_11 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BEAUMONT_11 +# endif +# define machine_is_beaumont_11() (machine_arch_type == MACH_TYPE_BEAUMONT_11) +#else +# define machine_is_beaumont_11() (0) +#endif + +#ifdef CONFIG_MACH_VANGUARD +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_VANGUARD +# endif +# define machine_is_vanguard() (machine_arch_type == MACH_TYPE_VANGUARD) +#else +# define machine_is_vanguard() (0) +#endif + +#ifdef CONFIG_MACH_S5PC110_DRACO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_S5PC110_DRACO +# endif +# define machine_is_s5pc110_draco() (machine_arch_type == MACH_TYPE_S5PC110_DRACO) +#else +# define machine_is_s5pc110_draco() (0) +#endif + +#ifdef CONFIG_MACH_CARTESIO_TWO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CARTESIO_TWO +# endif +# define machine_is_cartesio_two() (machine_arch_type == MACH_TYPE_CARTESIO_TWO) +#else +# define machine_is_cartesio_two() (0) +#endif + +#ifdef CONFIG_MACH_ASTER +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ASTER +# endif +# define machine_is_aster() (machine_arch_type == MACH_TYPE_ASTER) +#else +# define machine_is_aster() (0) +#endif + +#ifdef CONFIG_MACH_VOGUESV210 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_VOGUESV210 +# endif +# define machine_is_voguesv210() (machine_arch_type == MACH_TYPE_VOGUESV210) +#else +# define machine_is_voguesv210() (0) +#endif + +#ifdef CONFIG_MACH_ACM500X +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ACM500X +# endif +# define machine_is_acm500x() (machine_arch_type == MACH_TYPE_ACM500X) +#else +# define machine_is_acm500x() (0) +#endif + +#ifdef CONFIG_MACH_KM9260 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_KM9260 +# endif +# define machine_is_km9260() (machine_arch_type == MACH_TYPE_KM9260) +#else +# define machine_is_km9260() (0) +#endif + +#ifdef CONFIG_MACH_NIDEFLEXG1 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NIDEFLEXG1 +# endif +# define machine_is_nideflexg1() (machine_arch_type == MACH_TYPE_NIDEFLEXG1) +#else +# define machine_is_nideflexg1() (0) +#endif + +#ifdef CONFIG_MACH_CTERA_PLUG_IO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CTERA_PLUG_IO +# endif +# define machine_is_ctera_plug_io() (machine_arch_type == MACH_TYPE_CTERA_PLUG_IO) +#else +# define machine_is_ctera_plug_io() (0) +#endif + +#ifdef CONFIG_MACH_SMARTQ7 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SMARTQ7 +# endif +# define machine_is_smartq7() (machine_arch_type == MACH_TYPE_SMARTQ7) +#else +# define machine_is_smartq7() (0) +#endif + +#ifdef CONFIG_MACH_AT91SAM9G10EK2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AT91SAM9G10EK2 +# endif +# define machine_is_at91sam9g10ek2() (machine_arch_type == MACH_TYPE_AT91SAM9G10EK2) +#else +# define machine_is_at91sam9g10ek2() (0) +#endif + +#ifdef CONFIG_MACH_ASUSP527 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ASUSP527 +# endif +# define machine_is_asusp527() (machine_arch_type == MACH_TYPE_ASUSP527) +#else +# define machine_is_asusp527() (0) +#endif + +#ifdef CONFIG_MACH_AT91SAM9G20MPM2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AT91SAM9G20MPM2 +# endif +# define machine_is_at91sam9g20mpm2() (machine_arch_type == MACH_TYPE_AT91SAM9G20MPM2) +#else +# define machine_is_at91sam9g20mpm2() (0) +#endif + +#ifdef CONFIG_MACH_TOPASA900 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TOPASA900 +# endif +# define machine_is_topasa900() (machine_arch_type == MACH_TYPE_TOPASA900) +#else +# define machine_is_topasa900() (0) +#endif + +#ifdef CONFIG_MACH_ELECTRUM_100 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ELECTRUM_100 +# endif +# define machine_is_electrum_100() (machine_arch_type == MACH_TYPE_ELECTRUM_100) +#else +# define machine_is_electrum_100() (0) +#endif + +#ifdef CONFIG_MACH_MX51GRB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MX51GRB +# endif +# define machine_is_mx51grb() (machine_arch_type == MACH_TYPE_MX51GRB) +#else +# define machine_is_mx51grb() (0) +#endif + +#ifdef CONFIG_MACH_XEA300 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_XEA300 +# endif +# define machine_is_xea300() (machine_arch_type == MACH_TYPE_XEA300) +#else +# define machine_is_xea300() (0) +#endif + +#ifdef CONFIG_MACH_HTCSTARTREK +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HTCSTARTREK +# endif +# define machine_is_htcstartrek() (machine_arch_type == MACH_TYPE_HTCSTARTREK) +#else +# define machine_is_htcstartrek() (0) +#endif + +#ifdef CONFIG_MACH_LIMA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LIMA +# endif +# define machine_is_lima() (machine_arch_type == MACH_TYPE_LIMA) +#else +# define machine_is_lima() (0) +#endif + +#ifdef CONFIG_MACH_CSB740 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CSB740 +# endif +# define machine_is_csb740() (machine_arch_type == MACH_TYPE_CSB740) +#else +# define machine_is_csb740() (0) +#endif + +#ifdef CONFIG_MACH_USB_S8815 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_USB_S8815 +# endif +# define machine_is_usb_s8815() (machine_arch_type == MACH_TYPE_USB_S8815) +#else +# define machine_is_usb_s8815() (0) +#endif + +#ifdef CONFIG_MACH_WATSON_EFM_PLUGIN +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_WATSON_EFM_PLUGIN +# endif +# define machine_is_watson_efm_plugin() (machine_arch_type == MACH_TYPE_WATSON_EFM_PLUGIN) +#else +# define machine_is_watson_efm_plugin() (0) +#endif + +#ifdef CONFIG_MACH_MILKYWAY +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MILKYWAY +# endif +# define machine_is_milkyway() (machine_arch_type == MACH_TYPE_MILKYWAY) +#else +# define machine_is_milkyway() (0) +#endif + +#ifdef CONFIG_MACH_G4EVM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_G4EVM +# endif +# define machine_is_g4evm() (machine_arch_type == MACH_TYPE_G4EVM) +#else +# define machine_is_g4evm() (0) +#endif + +#ifdef CONFIG_MACH_PICOMOD6 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PICOMOD6 +# endif +# define machine_is_picomod6() (machine_arch_type == MACH_TYPE_PICOMOD6) +#else +# define machine_is_picomod6() (0) +#endif + +#ifdef CONFIG_MACH_OMAPL138_HAWKBOARD +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAPL138_HAWKBOARD +# endif +# define machine_is_omapl138_hawkboard() (machine_arch_type == MACH_TYPE_OMAPL138_HAWKBOARD) +#else +# define machine_is_omapl138_hawkboard() (0) +#endif + +#ifdef CONFIG_MACH_IP6000 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IP6000 +# endif +# define machine_is_ip6000() (machine_arch_type == MACH_TYPE_IP6000) +#else +# define machine_is_ip6000() (0) +#endif + +#ifdef CONFIG_MACH_IP6010 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IP6010 +# endif +# define machine_is_ip6010() (machine_arch_type == MACH_TYPE_IP6010) +#else +# define machine_is_ip6010() (0) +#endif + +#ifdef CONFIG_MACH_UTM400 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_UTM400 +# endif +# define machine_is_utm400() (machine_arch_type == MACH_TYPE_UTM400) +#else +# define machine_is_utm400() (0) +#endif + +#ifdef CONFIG_MACH_OMAP3_ZYBEX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAP3_ZYBEX +# endif +# define machine_is_omap3_zybex() (machine_arch_type == MACH_TYPE_OMAP3_ZYBEX) +#else +# define machine_is_omap3_zybex() (0) +#endif + +#ifdef CONFIG_MACH_WIRELESS_SPACE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_WIRELESS_SPACE +# endif +# define machine_is_wireless_space() (machine_arch_type == MACH_TYPE_WIRELESS_SPACE) +#else +# define machine_is_wireless_space() (0) +#endif + +#ifdef CONFIG_MACH_SX560 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SX560 +# endif +# define machine_is_sx560() (machine_arch_type == MACH_TYPE_SX560) +#else +# define machine_is_sx560() (0) +#endif + +#ifdef CONFIG_MACH_TS41X +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TS41X +# endif +# define machine_is_ts41x() (machine_arch_type == MACH_TYPE_TS41X) +#else +# define machine_is_ts41x() (0) +#endif + +#ifdef CONFIG_MACH_ELPHEL10373 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ELPHEL10373 +# endif +# define machine_is_elphel10373() (machine_arch_type == MACH_TYPE_ELPHEL10373) +#else +# define machine_is_elphel10373() (0) +#endif + +#ifdef CONFIG_MACH_RHOBOT +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_RHOBOT +# endif +# define machine_is_rhobot() (machine_arch_type == MACH_TYPE_RHOBOT) +#else +# define machine_is_rhobot() (0) +#endif + +#ifdef CONFIG_MACH_MX51_REFRESH +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MX51_REFRESH +# endif +# define machine_is_mx51_refresh() (machine_arch_type == MACH_TYPE_MX51_REFRESH) +#else +# define machine_is_mx51_refresh() (0) +#endif + +#ifdef CONFIG_MACH_LS9260 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LS9260 +# endif +# define machine_is_ls9260() (machine_arch_type == MACH_TYPE_LS9260) +#else +# define machine_is_ls9260() (0) +#endif + +#ifdef CONFIG_MACH_SHANK +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SHANK +# endif +# define machine_is_shank() (machine_arch_type == MACH_TYPE_SHANK) +#else +# define machine_is_shank() (0) +#endif + +#ifdef CONFIG_MACH_QSD8X50_ST1 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_QSD8X50_ST1 +# endif +# define machine_is_qsd8x50_st1() (machine_arch_type == MACH_TYPE_QSD8X50_ST1) +#else +# define machine_is_qsd8x50_st1() (0) +#endif + +#ifdef CONFIG_MACH_AT91SAM9M10EKES +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AT91SAM9M10EKES +# endif +# define machine_is_at91sam9m10ekes() (machine_arch_type == MACH_TYPE_AT91SAM9M10EKES) +#else +# define machine_is_at91sam9m10ekes() (0) +#endif + +#ifdef CONFIG_MACH_HIRAM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HIRAM +# endif +# define machine_is_hiram() (machine_arch_type == MACH_TYPE_HIRAM) +#else +# define machine_is_hiram() (0) +#endif + +#ifdef CONFIG_MACH_PHY3250 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PHY3250 +# endif +# define machine_is_phy3250() (machine_arch_type == MACH_TYPE_PHY3250) +#else +# define machine_is_phy3250() (0) +#endif + +#ifdef CONFIG_MACH_EA3250 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EA3250 +# endif +# define machine_is_ea3250() (machine_arch_type == MACH_TYPE_EA3250) +#else +# define machine_is_ea3250() (0) +#endif + +#ifdef CONFIG_MACH_FDI3250 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_FDI3250 +# endif +# define machine_is_fdi3250() (machine_arch_type == MACH_TYPE_FDI3250) +#else +# define machine_is_fdi3250() (0) +#endif + +#ifdef CONFIG_MACH_WHITESTONE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_WHITESTONE +# endif +# define machine_is_htcwhitestone() (machine_arch_type == MACH_TYPE_WHITESTONE) +#else +# define machine_is_htcwhitestone() (0) +#endif + +#ifdef CONFIG_MACH_AT91SAM9263NIT +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AT91SAM9263NIT +# endif +# define machine_is_at91sam9263nit() (machine_arch_type == MACH_TYPE_AT91SAM9263NIT) +#else +# define machine_is_at91sam9263nit() (0) +#endif + +#ifdef CONFIG_MACH_CCMX51 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CCMX51 +# endif +# define machine_is_ccmx51() (machine_arch_type == MACH_TYPE_CCMX51) +#else +# define machine_is_ccmx51() (0) +#endif + +#ifdef CONFIG_MACH_CCMX51JS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CCMX51JS +# endif +# define machine_is_ccmx51js() (machine_arch_type == MACH_TYPE_CCMX51JS) +#else +# define machine_is_ccmx51js() (0) +#endif + +#ifdef CONFIG_MACH_CCWMX51 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CCWMX51 +# endif +# define machine_is_ccwmx51() (machine_arch_type == MACH_TYPE_CCWMX51) +#else +# define machine_is_ccwmx51() (0) +#endif + +#ifdef CONFIG_MACH_CCWMX51JS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CCWMX51JS +# endif +# define machine_is_ccwmx51js() (machine_arch_type == MACH_TYPE_CCWMX51JS) +#else +# define machine_is_ccwmx51js() (0) +#endif + +#ifdef CONFIG_MACH_MINI6410 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MINI6410 +# endif +# define machine_is_mini6410() (machine_arch_type == MACH_TYPE_MINI6410) +#else +# define machine_is_mini6410() (0) +#endif + +#ifdef CONFIG_MACH_TINY6410 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TINY6410 +# endif +# define machine_is_tiny6410() (machine_arch_type == MACH_TYPE_TINY6410) +#else +# define machine_is_tiny6410() (0) +#endif + +#ifdef CONFIG_MACH_NANO6410 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NANO6410 +# endif +# define machine_is_nano6410() (machine_arch_type == MACH_TYPE_NANO6410) +#else +# define machine_is_nano6410() (0) +#endif + +#ifdef CONFIG_MACH_AT572D940HFNLDB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AT572D940HFNLDB +# endif +# define machine_is_at572d940hfnldb() (machine_arch_type == MACH_TYPE_AT572D940HFNLDB) +#else +# define machine_is_at572d940hfnldb() (0) +#endif + +#ifdef CONFIG_MACH_HTCLEO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HTCLEO +# endif +# define machine_is_htcleo() (machine_arch_type == MACH_TYPE_HTCLEO) +#else +# define machine_is_htcleo() (0) +#endif + +#ifdef CONFIG_MACH_AVP13 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AVP13 +# endif +# define machine_is_avp13() (machine_arch_type == MACH_TYPE_AVP13) +#else +# define machine_is_avp13() (0) +#endif + +#ifdef CONFIG_MACH_XXSVIDEOD +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_XXSVIDEOD +# endif +# define machine_is_xxsvideod() (machine_arch_type == MACH_TYPE_XXSVIDEOD) +#else +# define machine_is_xxsvideod() (0) +#endif + +#ifdef CONFIG_MACH_VPNEXT +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_VPNEXT +# endif +# define machine_is_vpnext() (machine_arch_type == MACH_TYPE_VPNEXT) +#else +# define machine_is_vpnext() (0) +#endif + +#ifdef CONFIG_MACH_SWARCO_ITC3 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SWARCO_ITC3 +# endif +# define machine_is_swarco_itc3() (machine_arch_type == MACH_TYPE_SWARCO_ITC3) +#else +# define machine_is_swarco_itc3() (0) +#endif + +#ifdef CONFIG_MACH_TX51 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TX51 +# endif +# define machine_is_tx51() (machine_arch_type == MACH_TYPE_TX51) +#else +# define machine_is_tx51() (0) +#endif + +#ifdef CONFIG_MACH_DOLBY_CAT1021 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DOLBY_CAT1021 +# endif +# define machine_is_dolby_cat1021() (machine_arch_type == MACH_TYPE_DOLBY_CAT1021) +#else +# define machine_is_dolby_cat1021() (0) +#endif + +#ifdef CONFIG_MACH_MX28EVK +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MX28EVK +# endif +# define machine_is_mx28evk() (machine_arch_type == MACH_TYPE_MX28EVK) +#else +# define machine_is_mx28evk() (0) +#endif + +#ifdef CONFIG_MACH_PHOENIX260 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PHOENIX260 +# endif +# define machine_is_phoenix260() (machine_arch_type == MACH_TYPE_PHOENIX260) +#else +# define machine_is_phoenix260() (0) +#endif + +#ifdef CONFIG_MACH_UVACA_STORK +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_UVACA_STORK +# endif +# define machine_is_uvaca_stork() (machine_arch_type == MACH_TYPE_UVACA_STORK) +#else +# define machine_is_uvaca_stork() (0) +#endif + +#ifdef CONFIG_MACH_SMARTQ5 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SMARTQ5 +# endif +# define machine_is_smartq5() (machine_arch_type == MACH_TYPE_SMARTQ5) +#else +# define machine_is_smartq5() (0) +#endif + +#ifdef CONFIG_MACH_ALL3078 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ALL3078 +# endif +# define machine_is_all3078() (machine_arch_type == MACH_TYPE_ALL3078) +#else +# define machine_is_all3078() (0) +#endif + +#ifdef CONFIG_MACH_CTERA_2BAY_DS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CTERA_2BAY_DS +# endif +# define machine_is_ctera_2bay_ds() (machine_arch_type == MACH_TYPE_CTERA_2BAY_DS) +#else +# define machine_is_ctera_2bay_ds() (0) +#endif + +#ifdef CONFIG_MACH_SIOGENTOO3 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SIOGENTOO3 +# endif +# define machine_is_siogentoo3() (machine_arch_type == MACH_TYPE_SIOGENTOO3) +#else +# define machine_is_siogentoo3() (0) +#endif + +#ifdef CONFIG_MACH_EPB5000 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EPB5000 +# endif +# define machine_is_epb5000() (machine_arch_type == MACH_TYPE_EPB5000) +#else +# define machine_is_epb5000() (0) +#endif + +#ifdef CONFIG_MACH_HY9263 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HY9263 +# endif +# define machine_is_hy9263() (machine_arch_type == MACH_TYPE_HY9263) +#else +# define machine_is_hy9263() (0) +#endif + +#ifdef CONFIG_MACH_ACER_TEMPO_M900 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ACER_TEMPO_M900 +# endif +# define machine_is_acer_tempo_m900() (machine_arch_type == MACH_TYPE_ACER_TEMPO_M900) +#else +# define machine_is_acer_tempo_m900() (0) +#endif + +#ifdef CONFIG_MACH_ACER_TEMPO_DX900 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ACER_TEMPO_DX900 +# endif +# define machine_is_acer_tempo_dx650() (machine_arch_type == MACH_TYPE_ACER_TEMPO_DX900) +#else +# define machine_is_acer_tempo_dx650() (0) +#endif + +#ifdef CONFIG_MACH_ACER_TEMPO_X960 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ACER_TEMPO_X960 +# endif +# define machine_is_acer_tempo_x960() (machine_arch_type == MACH_TYPE_ACER_TEMPO_X960) +#else +# define machine_is_acer_tempo_x960() (0) +#endif + +#ifdef CONFIG_MACH_ACER_ETEN_V900 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ACER_ETEN_V900 +# endif +# define machine_is_acer_eten_v900() (machine_arch_type == MACH_TYPE_ACER_ETEN_V900) +#else +# define machine_is_acer_eten_v900() (0) +#endif + +#ifdef CONFIG_MACH_ACER_ETEN_X900 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ACER_ETEN_X900 +# endif +# define machine_is_acer_eten_x900() (machine_arch_type == MACH_TYPE_ACER_ETEN_X900) +#else +# define machine_is_acer_eten_x900() (0) +#endif + +#ifdef CONFIG_MACH_BONNELL +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BONNELL +# endif +# define machine_is_bonnell() (machine_arch_type == MACH_TYPE_BONNELL) +#else +# define machine_is_bonnell() (0) +#endif + +#ifdef CONFIG_MACH_OHT_MX27 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OHT_MX27 +# endif +# define machine_is_oht_mx27() (machine_arch_type == MACH_TYPE_OHT_MX27) +#else +# define machine_is_oht_mx27() (0) +#endif + +#ifdef CONFIG_MACH_HTCQUARTZ +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HTCQUARTZ +# endif +# define machine_is_htcquartz() (machine_arch_type == MACH_TYPE_HTCQUARTZ) +#else +# define machine_is_htcquartz() (0) +#endif + +#ifdef CONFIG_MACH_DAVINCI_DM6467TEVM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DAVINCI_DM6467TEVM +# endif +# define machine_is_davinci_dm6467tevm() (machine_arch_type == MACH_TYPE_DAVINCI_DM6467TEVM) +#else +# define machine_is_davinci_dm6467tevm() (0) +#endif + +#ifdef CONFIG_MACH_C3AX03 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_C3AX03 +# endif +# define machine_is_c3ax03() (machine_arch_type == MACH_TYPE_C3AX03) +#else +# define machine_is_c3ax03() (0) +#endif + +#ifdef CONFIG_MACH_MXT_TD60 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MXT_TD60 +# endif +# define machine_is_mxt_td60() (machine_arch_type == MACH_TYPE_MXT_TD60) +#else +# define machine_is_mxt_td60() (0) +#endif + +#ifdef CONFIG_MACH_ESYX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ESYX +# endif +# define machine_is_esyx() (machine_arch_type == MACH_TYPE_ESYX) +#else +# define machine_is_esyx() (0) +#endif + +#ifdef CONFIG_MACH_DOVE_DB2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DOVE_DB2 +# endif +# define machine_is_dove_db2() (machine_arch_type == MACH_TYPE_DOVE_DB2) +#else +# define machine_is_dove_db2() (0) +#endif + +#ifdef CONFIG_MACH_BULLDOG +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BULLDOG +# endif +# define machine_is_bulldog() (machine_arch_type == MACH_TYPE_BULLDOG) +#else +# define machine_is_bulldog() (0) +#endif + +#ifdef CONFIG_MACH_DERELL_ME2000 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DERELL_ME2000 +# endif +# define machine_is_derell_me2000() (machine_arch_type == MACH_TYPE_DERELL_ME2000) +#else +# define machine_is_derell_me2000() (0) +#endif + +#ifdef CONFIG_MACH_BCMRING_BASE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BCMRING_BASE +# endif +# define machine_is_bcmring_base() (machine_arch_type == MACH_TYPE_BCMRING_BASE) +#else +# define machine_is_bcmring_base() (0) +#endif + +#ifdef CONFIG_MACH_BCMRING_EVM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BCMRING_EVM +# endif +# define machine_is_bcmring_evm() (machine_arch_type == MACH_TYPE_BCMRING_EVM) +#else +# define machine_is_bcmring_evm() (0) +#endif + +#ifdef CONFIG_MACH_BCMRING_EVM_JAZZ +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BCMRING_EVM_JAZZ +# endif +# define machine_is_bcmring_evm_jazz() (machine_arch_type == MACH_TYPE_BCMRING_EVM_JAZZ) +#else +# define machine_is_bcmring_evm_jazz() (0) +#endif + +#ifdef CONFIG_MACH_BCMRING_SP +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BCMRING_SP +# endif +# define machine_is_bcmring_sp() (machine_arch_type == MACH_TYPE_BCMRING_SP) +#else +# define machine_is_bcmring_sp() (0) +#endif + +#ifdef CONFIG_MACH_BCMRING_SV +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BCMRING_SV +# endif +# define machine_is_bcmring_sv() (machine_arch_type == MACH_TYPE_BCMRING_SV) +#else +# define machine_is_bcmring_sv() (0) +#endif + +#ifdef CONFIG_MACH_BCMRING_SV_JAZZ +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BCMRING_SV_JAZZ +# endif +# define machine_is_bcmring_sv_jazz() (machine_arch_type == MACH_TYPE_BCMRING_SV_JAZZ) +#else +# define machine_is_bcmring_sv_jazz() (0) +#endif + +#ifdef CONFIG_MACH_BCMRING_TABLET +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BCMRING_TABLET +# endif +# define machine_is_bcmring_tablet() (machine_arch_type == MACH_TYPE_BCMRING_TABLET) +#else +# define machine_is_bcmring_tablet() (0) +#endif + +#ifdef CONFIG_MACH_BCMRING_VP +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BCMRING_VP +# endif +# define machine_is_bcmring_vp() (machine_arch_type == MACH_TYPE_BCMRING_VP) +#else +# define machine_is_bcmring_vp() (0) +#endif + +#ifdef CONFIG_MACH_BCMRING_EVM_SEIKOR +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BCMRING_EVM_SEIKOR +# endif +# define machine_is_bcmring_evm_seikor() (machine_arch_type == MACH_TYPE_BCMRING_EVM_SEIKOR) +#else +# define machine_is_bcmring_evm_seikor() (0) +#endif + +#ifdef CONFIG_MACH_BCMRING_SP_WQVGA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BCMRING_SP_WQVGA +# endif +# define machine_is_bcmring_sp_wqvga() (machine_arch_type == MACH_TYPE_BCMRING_SP_WQVGA) +#else +# define machine_is_bcmring_sp_wqvga() (0) +#endif + +#ifdef CONFIG_MACH_BCMRING_CUSTOM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BCMRING_CUSTOM +# endif +# define machine_is_bcmring_custom() (machine_arch_type == MACH_TYPE_BCMRING_CUSTOM) +#else +# define machine_is_bcmring_custom() (0) +#endif + +#ifdef CONFIG_MACH_ACER_S200 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ACER_S200 +# endif +# define machine_is_acer_s200() (machine_arch_type == MACH_TYPE_ACER_S200) +#else +# define machine_is_acer_s200() (0) +#endif + +#ifdef CONFIG_MACH_BT270 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BT270 +# endif +# define machine_is_bt270() (machine_arch_type == MACH_TYPE_BT270) +#else +# define machine_is_bt270() (0) +#endif + +#ifdef CONFIG_MACH_ISEO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ISEO +# endif +# define machine_is_iseo() (machine_arch_type == MACH_TYPE_ISEO) +#else +# define machine_is_iseo() (0) +#endif + +#ifdef CONFIG_MACH_CEZANNE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CEZANNE +# endif +# define machine_is_cezanne() (machine_arch_type == MACH_TYPE_CEZANNE) +#else +# define machine_is_cezanne() (0) +#endif + +#ifdef CONFIG_MACH_LUCCA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LUCCA +# endif +# define machine_is_lucca() (machine_arch_type == MACH_TYPE_LUCCA) +#else +# define machine_is_lucca() (0) +#endif + +#ifdef CONFIG_MACH_SUPERSMART +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SUPERSMART +# endif +# define machine_is_supersmart() (machine_arch_type == MACH_TYPE_SUPERSMART) +#else +# define machine_is_supersmart() (0) +#endif + +#ifdef CONFIG_MACH_CS_MISANO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CS_MISANO +# endif +# define machine_is_arm11_board() (machine_arch_type == MACH_TYPE_CS_MISANO) +#else +# define machine_is_arm11_board() (0) +#endif + +#ifdef CONFIG_MACH_MAGNOLIA2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MAGNOLIA2 +# endif +# define machine_is_magnolia2() (machine_arch_type == MACH_TYPE_MAGNOLIA2) +#else +# define machine_is_magnolia2() (0) +#endif + +#ifdef CONFIG_MACH_EMXX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EMXX +# endif +# define machine_is_emxx() (machine_arch_type == MACH_TYPE_EMXX) +#else +# define machine_is_emxx() (0) +#endif + +#ifdef CONFIG_MACH_OUTLAW +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OUTLAW +# endif +# define machine_is_outlaw() (machine_arch_type == MACH_TYPE_OUTLAW) +#else +# define machine_is_outlaw() (0) +#endif + +#ifdef CONFIG_MACH_RIOT_BEI2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_RIOT_BEI2 +# endif +# define machine_is_riot_bei2() (machine_arch_type == MACH_TYPE_RIOT_BEI2) +#else +# define machine_is_riot_bei2() (0) +#endif + +#ifdef CONFIG_MACH_RIOT_VOX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_RIOT_VOX +# endif +# define machine_is_riot_gx2() (machine_arch_type == MACH_TYPE_RIOT_VOX) +#else +# define machine_is_riot_gx2() (0) +#endif + +#ifdef CONFIG_MACH_RIOT_X37 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_RIOT_X37 +# endif +# define machine_is_riot_x37() (machine_arch_type == MACH_TYPE_RIOT_X37) +#else +# define machine_is_riot_x37() (0) +#endif + +#ifdef CONFIG_MACH_MEGA25MX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MEGA25MX +# endif +# define machine_is_mega25mx() (machine_arch_type == MACH_TYPE_MEGA25MX) +#else +# define machine_is_mega25mx() (0) +#endif + +#ifdef CONFIG_MACH_BENZINA2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BENZINA2 +# endif +# define machine_is_benzina2() (machine_arch_type == MACH_TYPE_BENZINA2) +#else +# define machine_is_benzina2() (0) +#endif + +#ifdef CONFIG_MACH_IGNITE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IGNITE +# endif +# define machine_is_ignite() (machine_arch_type == MACH_TYPE_IGNITE) +#else +# define machine_is_ignite() (0) +#endif + +#ifdef CONFIG_MACH_FOGGIA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_FOGGIA +# endif +# define machine_is_foggia() (machine_arch_type == MACH_TYPE_FOGGIA) +#else +# define machine_is_foggia() (0) +#endif + +#ifdef CONFIG_MACH_AREZZO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AREZZO +# endif +# define machine_is_arezzo() (machine_arch_type == MACH_TYPE_AREZZO) +#else +# define machine_is_arezzo() (0) +#endif + +#ifdef CONFIG_MACH_LEICA_SKYWALKER +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LEICA_SKYWALKER +# endif +# define machine_is_leica_skywalker() (machine_arch_type == MACH_TYPE_LEICA_SKYWALKER) +#else +# define machine_is_leica_skywalker() (0) +#endif + +#ifdef CONFIG_MACH_JACINTO2_JAMR +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_JACINTO2_JAMR +# endif +# define machine_is_jacinto2_jamr() (machine_arch_type == MACH_TYPE_JACINTO2_JAMR) +#else +# define machine_is_jacinto2_jamr() (0) +#endif + +#ifdef CONFIG_MACH_GTS_NOVA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_GTS_NOVA +# endif +# define machine_is_gts_nova() (machine_arch_type == MACH_TYPE_GTS_NOVA) +#else +# define machine_is_gts_nova() (0) +#endif + +#ifdef CONFIG_MACH_P3600 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_P3600 +# endif +# define machine_is_p3600() (machine_arch_type == MACH_TYPE_P3600) +#else +# define machine_is_p3600() (0) +#endif + +#ifdef CONFIG_MACH_DLT2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DLT2 +# endif +# define machine_is_dlt2() (machine_arch_type == MACH_TYPE_DLT2) +#else +# define machine_is_dlt2() (0) +#endif + +#ifdef CONFIG_MACH_DF3120 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DF3120 +# endif +# define machine_is_df3120() (machine_arch_type == MACH_TYPE_DF3120) +#else +# define machine_is_df3120() (0) +#endif + +#ifdef CONFIG_MACH_ECUCORE_9G20 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ECUCORE_9G20 +# endif +# define machine_is_ecucore_9g20() (machine_arch_type == MACH_TYPE_ECUCORE_9G20) +#else +# define machine_is_ecucore_9g20() (0) +#endif + +#ifdef CONFIG_MACH_NAUTEL_LPC3240 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NAUTEL_LPC3240 +# endif +# define machine_is_nautel_lpc3240() (machine_arch_type == MACH_TYPE_NAUTEL_LPC3240) +#else +# define machine_is_nautel_lpc3240() (0) +#endif + +#ifdef CONFIG_MACH_GLACIER +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_GLACIER +# endif +# define machine_is_glacier() (machine_arch_type == MACH_TYPE_GLACIER) +#else +# define machine_is_glacier() (0) +#endif + +#ifdef CONFIG_MACH_PHRAZER_BULLDOG +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PHRAZER_BULLDOG +# endif +# define machine_is_phrazer_bulldog() (machine_arch_type == MACH_TYPE_PHRAZER_BULLDOG) +#else +# define machine_is_phrazer_bulldog() (0) +#endif + +#ifdef CONFIG_MACH_OMAP3_BULLDOG +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAP3_BULLDOG +# endif +# define machine_is_omap3_bulldog() (machine_arch_type == MACH_TYPE_OMAP3_BULLDOG) +#else +# define machine_is_omap3_bulldog() (0) +#endif + +#ifdef CONFIG_MACH_PCA101 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PCA101 +# endif +# define machine_is_pca101() (machine_arch_type == MACH_TYPE_PCA101) +#else +# define machine_is_pca101() (0) +#endif + +#ifdef CONFIG_MACH_BUZZC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BUZZC +# endif +# define machine_is_buzzc() (machine_arch_type == MACH_TYPE_BUZZC) +#else +# define machine_is_buzzc() (0) +#endif + +#ifdef CONFIG_MACH_SASIE2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SASIE2 +# endif +# define machine_is_sasie2() (machine_arch_type == MACH_TYPE_SASIE2) +#else +# define machine_is_sasie2() (0) +#endif + +#ifdef CONFIG_MACH_DAVINCI_CIO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DAVINCI_CIO +# endif +# define machine_is_davinci_dm6467_cio() (machine_arch_type == MACH_TYPE_DAVINCI_CIO) +#else +# define machine_is_davinci_dm6467_cio() (0) +#endif + +#ifdef CONFIG_MACH_SMARTMETER_DL +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SMARTMETER_DL +# endif +# define machine_is_smartmeter_dl() (machine_arch_type == MACH_TYPE_SMARTMETER_DL) +#else +# define machine_is_smartmeter_dl() (0) +#endif + +#ifdef CONFIG_MACH_WZL6410 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_WZL6410 +# endif +# define machine_is_wzl6410() (machine_arch_type == MACH_TYPE_WZL6410) +#else +# define machine_is_wzl6410() (0) +#endif + +#ifdef CONFIG_MACH_WZL6410M +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_WZL6410M +# endif +# define machine_is_wzl6410m() (machine_arch_type == MACH_TYPE_WZL6410M) +#else +# define machine_is_wzl6410m() (0) +#endif + +#ifdef CONFIG_MACH_WZL6410F +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_WZL6410F +# endif +# define machine_is_wzl6410f() (machine_arch_type == MACH_TYPE_WZL6410F) +#else +# define machine_is_wzl6410f() (0) +#endif + +#ifdef CONFIG_MACH_WZL6410I +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_WZL6410I +# endif +# define machine_is_wzl6410i() (machine_arch_type == MACH_TYPE_WZL6410I) +#else +# define machine_is_wzl6410i() (0) +#endif + +#ifdef CONFIG_MACH_SPACECOM1 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SPACECOM1 +# endif +# define machine_is_spacecom1() (machine_arch_type == MACH_TYPE_SPACECOM1) +#else +# define machine_is_spacecom1() (0) +#endif + +#ifdef CONFIG_MACH_PINGU920 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PINGU920 +# endif +# define machine_is_pingu920() (machine_arch_type == MACH_TYPE_PINGU920) +#else +# define machine_is_pingu920() (0) +#endif + +#ifdef CONFIG_MACH_BRAVOC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BRAVOC +# endif +# define machine_is_bravoc() (machine_arch_type == MACH_TYPE_BRAVOC) +#else +# define machine_is_bravoc() (0) +#endif + +#ifdef CONFIG_MACH_CYBO2440 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CYBO2440 +# endif +# define machine_is_cybo2440() (machine_arch_type == MACH_TYPE_CYBO2440) +#else +# define machine_is_cybo2440() (0) +#endif + +#ifdef CONFIG_MACH_VDSSW +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_VDSSW +# endif +# define machine_is_vdssw() (machine_arch_type == MACH_TYPE_VDSSW) +#else +# define machine_is_vdssw() (0) +#endif + +#ifdef CONFIG_MACH_ROMULUS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ROMULUS +# endif +# define machine_is_romulus() (machine_arch_type == MACH_TYPE_ROMULUS) +#else +# define machine_is_romulus() (0) +#endif + +#ifdef CONFIG_MACH_OMAP_MAGIC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAP_MAGIC +# endif +# define machine_is_omap_magic() (machine_arch_type == MACH_TYPE_OMAP_MAGIC) +#else +# define machine_is_omap_magic() (0) +#endif + +#ifdef CONFIG_MACH_ELTD100 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ELTD100 +# endif +# define machine_is_eltd100() (machine_arch_type == MACH_TYPE_ELTD100) +#else +# define machine_is_eltd100() (0) +#endif + +#ifdef CONFIG_MACH_CAPC7117 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CAPC7117 +# endif +# define machine_is_capc7117() (machine_arch_type == MACH_TYPE_CAPC7117) +#else +# define machine_is_capc7117() (0) +#endif + +#ifdef CONFIG_MACH_SWAN +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SWAN +# endif +# define machine_is_swan() (machine_arch_type == MACH_TYPE_SWAN) +#else +# define machine_is_swan() (0) +#endif + +#ifdef CONFIG_MACH_VEU +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_VEU +# endif +# define machine_is_veu() (machine_arch_type == MACH_TYPE_VEU) +#else +# define machine_is_veu() (0) +#endif + +#ifdef CONFIG_MACH_RM2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_RM2 +# endif +# define machine_is_rm2() (machine_arch_type == MACH_TYPE_RM2) +#else +# define machine_is_rm2() (0) +#endif + +#ifdef CONFIG_MACH_TT2100 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TT2100 +# endif +# define machine_is_tt2100() (machine_arch_type == MACH_TYPE_TT2100) +#else +# define machine_is_tt2100() (0) +#endif + +#ifdef CONFIG_MACH_VENICE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_VENICE +# endif +# define machine_is_venice() (machine_arch_type == MACH_TYPE_VENICE) +#else +# define machine_is_venice() (0) +#endif + +#ifdef CONFIG_MACH_PC7323 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PC7323 +# endif +# define machine_is_pc7323() (machine_arch_type == MACH_TYPE_PC7323) +#else +# define machine_is_pc7323() (0) +#endif + +#ifdef CONFIG_MACH_MASP +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MASP +# endif +# define machine_is_masp() (machine_arch_type == MACH_TYPE_MASP) +#else +# define machine_is_masp() (0) +#endif + +#ifdef CONFIG_MACH_FUJITSU_TVSTBSOC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_FUJITSU_TVSTBSOC +# endif +# define machine_is_fujitsu_tvstbsoc0() (machine_arch_type == MACH_TYPE_FUJITSU_TVSTBSOC) +#else +# define machine_is_fujitsu_tvstbsoc0() (0) +#endif + +#ifdef CONFIG_MACH_FUJITSU_TVSTBSOC1 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_FUJITSU_TVSTBSOC1 +# endif +# define machine_is_fujitsu_tvstbsoc1() (machine_arch_type == MACH_TYPE_FUJITSU_TVSTBSOC1) +#else +# define machine_is_fujitsu_tvstbsoc1() (0) +#endif + +#ifdef CONFIG_MACH_LEXIKON +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LEXIKON +# endif +# define machine_is_lexikon() (machine_arch_type == MACH_TYPE_LEXIKON) +#else +# define machine_is_lexikon() (0) +#endif + +#ifdef CONFIG_MACH_MINI2440V2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MINI2440V2 +# endif +# define machine_is_mini2440v2() (machine_arch_type == MACH_TYPE_MINI2440V2) +#else +# define machine_is_mini2440v2() (0) +#endif + +#ifdef CONFIG_MACH_ICONTROL +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ICONTROL +# endif +# define machine_is_icontrol() (machine_arch_type == MACH_TYPE_ICONTROL) +#else +# define machine_is_icontrol() (0) +#endif + +#ifdef CONFIG_MACH_SHEEVAD +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SHEEVAD +# endif +# define machine_is_gplugd() (machine_arch_type == MACH_TYPE_SHEEVAD) +#else +# define machine_is_gplugd() (0) +#endif + +#ifdef CONFIG_MACH_QSD8X50A_ST1_1 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_QSD8X50A_ST1_1 +# endif +# define machine_is_qsd8x50a_st1_1() (machine_arch_type == MACH_TYPE_QSD8X50A_ST1_1) +#else +# define machine_is_qsd8x50a_st1_1() (0) +#endif + +#ifdef CONFIG_MACH_QSD8X50A_ST1_5 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_QSD8X50A_ST1_5 +# endif +# define machine_is_qsd8x50a_st1_5() (machine_arch_type == MACH_TYPE_QSD8X50A_ST1_5) +#else +# define machine_is_qsd8x50a_st1_5() (0) +#endif + +#ifdef CONFIG_MACH_BEE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BEE +# endif +# define machine_is_bee() (machine_arch_type == MACH_TYPE_BEE) +#else +# define machine_is_bee() (0) +#endif + +#ifdef CONFIG_MACH_MX23EVK +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MX23EVK +# endif +# define machine_is_mx23evk() (machine_arch_type == MACH_TYPE_MX23EVK) +#else +# define machine_is_mx23evk() (0) +#endif + +#ifdef CONFIG_MACH_AP4EVB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AP4EVB +# endif +# define machine_is_ap4evb() (machine_arch_type == MACH_TYPE_AP4EVB) +#else +# define machine_is_ap4evb() (0) +#endif + +#ifdef CONFIG_MACH_STOCKHOLM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_STOCKHOLM +# endif +# define machine_is_stockholm() (machine_arch_type == MACH_TYPE_STOCKHOLM) +#else +# define machine_is_stockholm() (0) +#endif + +#ifdef CONFIG_MACH_LPC_H3131 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LPC_H3131 +# endif +# define machine_is_lpc_h3131() (machine_arch_type == MACH_TYPE_LPC_H3131) +#else +# define machine_is_lpc_h3131() (0) +#endif + +#ifdef CONFIG_MACH_STINGRAY +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_STINGRAY +# endif +# define machine_is_stingray() (machine_arch_type == MACH_TYPE_STINGRAY) +#else +# define machine_is_stingray() (0) +#endif + +#ifdef CONFIG_MACH_KRAKEN +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_KRAKEN +# endif +# define machine_is_kraken() (machine_arch_type == MACH_TYPE_KRAKEN) +#else +# define machine_is_kraken() (0) +#endif + +#ifdef CONFIG_MACH_GW2388 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_GW2388 +# endif +# define machine_is_gw2388() (machine_arch_type == MACH_TYPE_GW2388) +#else +# define machine_is_gw2388() (0) +#endif + +#ifdef CONFIG_MACH_JADECPU +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_JADECPU +# endif +# define machine_is_jadecpu() (machine_arch_type == MACH_TYPE_JADECPU) +#else +# define machine_is_jadecpu() (0) +#endif + +#ifdef CONFIG_MACH_CARLISLE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CARLISLE +# endif +# define machine_is_carlisle() (machine_arch_type == MACH_TYPE_CARLISLE) +#else +# define machine_is_carlisle() (0) +#endif + +#ifdef CONFIG_MACH_LUX_SFT9 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LUX_SFT9 +# endif +# define machine_is_lux_sf9() (machine_arch_type == MACH_TYPE_LUX_SFT9) +#else +# define machine_is_lux_sf9() (0) +#endif + +#ifdef CONFIG_MACH_NEMID_TB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NEMID_TB +# endif +# define machine_is_nemid_tb() (machine_arch_type == MACH_TYPE_NEMID_TB) +#else +# define machine_is_nemid_tb() (0) +#endif + +#ifdef CONFIG_MACH_TERRIER +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TERRIER +# endif +# define machine_is_terrier() (machine_arch_type == MACH_TYPE_TERRIER) +#else +# define machine_is_terrier() (0) +#endif + +#ifdef CONFIG_MACH_TURBOT +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TURBOT +# endif +# define machine_is_turbot() (machine_arch_type == MACH_TYPE_TURBOT) +#else +# define machine_is_turbot() (0) +#endif + +#ifdef CONFIG_MACH_SANDDAB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SANDDAB +# endif +# define machine_is_sanddab() (machine_arch_type == MACH_TYPE_SANDDAB) +#else +# define machine_is_sanddab() (0) +#endif + +#ifdef CONFIG_MACH_MX35_CICADA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MX35_CICADA +# endif +# define machine_is_mx35_cicada() (machine_arch_type == MACH_TYPE_MX35_CICADA) +#else +# define machine_is_mx35_cicada() (0) +#endif + +#ifdef CONFIG_MACH_GHI2703D +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_GHI2703D +# endif +# define machine_is_ghi2703d() (machine_arch_type == MACH_TYPE_GHI2703D) +#else +# define machine_is_ghi2703d() (0) +#endif + +#ifdef CONFIG_MACH_LUX_SFX9 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LUX_SFX9 +# endif +# define machine_is_lux_sfx9() (machine_arch_type == MACH_TYPE_LUX_SFX9) +#else +# define machine_is_lux_sfx9() (0) +#endif + +#ifdef CONFIG_MACH_LUX_SF9G +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LUX_SF9G +# endif +# define machine_is_lux_sf9g() (machine_arch_type == MACH_TYPE_LUX_SF9G) +#else +# define machine_is_lux_sf9g() (0) +#endif + +#ifdef CONFIG_MACH_LUX_EDK9 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LUX_EDK9 +# endif +# define machine_is_lux_edk9() (machine_arch_type == MACH_TYPE_LUX_EDK9) +#else +# define machine_is_lux_edk9() (0) +#endif + +#ifdef CONFIG_MACH_HW90240 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HW90240 +# endif +# define machine_is_hw90240() (machine_arch_type == MACH_TYPE_HW90240) +#else +# define machine_is_hw90240() (0) +#endif + +#ifdef CONFIG_MACH_DM365_LEOPARD +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DM365_LEOPARD +# endif +# define machine_is_dm365_leopard() (machine_arch_type == MACH_TYPE_DM365_LEOPARD) +#else +# define machine_is_dm365_leopard() (0) +#endif + +#ifdef CONFIG_MACH_MITYOMAPL138 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MITYOMAPL138 +# endif +# define machine_is_mityomapl138() (machine_arch_type == MACH_TYPE_MITYOMAPL138) +#else +# define machine_is_mityomapl138() (0) +#endif + +#ifdef CONFIG_MACH_SCAT110 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SCAT110 +# endif +# define machine_is_scat110() (machine_arch_type == MACH_TYPE_SCAT110) +#else +# define machine_is_scat110() (0) +#endif + +#ifdef CONFIG_MACH_ACER_A1 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ACER_A1 +# endif +# define machine_is_acer_a1() (machine_arch_type == MACH_TYPE_ACER_A1) +#else +# define machine_is_acer_a1() (0) +#endif + +#ifdef CONFIG_MACH_CMCONTROL +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CMCONTROL +# endif +# define machine_is_cmcontrol() (machine_arch_type == MACH_TYPE_CMCONTROL) +#else +# define machine_is_cmcontrol() (0) +#endif + +#ifdef CONFIG_MACH_PELCO_LAMAR +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PELCO_LAMAR +# endif +# define machine_is_pelco_lamar() (machine_arch_type == MACH_TYPE_PELCO_LAMAR) +#else +# define machine_is_pelco_lamar() (0) +#endif + +#ifdef CONFIG_MACH_RFP43 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_RFP43 +# endif +# define machine_is_rfp43() (machine_arch_type == MACH_TYPE_RFP43) +#else +# define machine_is_rfp43() (0) +#endif + +#ifdef CONFIG_MACH_SK86R0301 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SK86R0301 +# endif +# define machine_is_sk86r0301() (machine_arch_type == MACH_TYPE_SK86R0301) +#else +# define machine_is_sk86r0301() (0) +#endif + +#ifdef CONFIG_MACH_CTPXA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CTPXA +# endif +# define machine_is_ctpxa() (machine_arch_type == MACH_TYPE_CTPXA) +#else +# define machine_is_ctpxa() (0) +#endif + +#ifdef CONFIG_MACH_EPB_ARM9_A +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EPB_ARM9_A +# endif +# define machine_is_epb_arm9_a() (machine_arch_type == MACH_TYPE_EPB_ARM9_A) +#else +# define machine_is_epb_arm9_a() (0) +#endif + +#ifdef CONFIG_MACH_GURUPLUG +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_GURUPLUG +# endif +# define machine_is_guruplug() (machine_arch_type == MACH_TYPE_GURUPLUG) +#else +# define machine_is_guruplug() (0) +#endif + +#ifdef CONFIG_MACH_SPEAR310 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SPEAR310 +# endif +# define machine_is_spear310() (machine_arch_type == MACH_TYPE_SPEAR310) +#else +# define machine_is_spear310() (0) +#endif + +#ifdef CONFIG_MACH_SPEAR320 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SPEAR320 +# endif +# define machine_is_spear320() (machine_arch_type == MACH_TYPE_SPEAR320) +#else +# define machine_is_spear320() (0) +#endif + +#ifdef CONFIG_MACH_ROBOTX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ROBOTX +# endif +# define machine_is_robotx() (machine_arch_type == MACH_TYPE_ROBOTX) +#else +# define machine_is_robotx() (0) +#endif + +#ifdef CONFIG_MACH_LSXHL +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LSXHL +# endif +# define machine_is_lsxhl() (machine_arch_type == MACH_TYPE_LSXHL) +#else +# define machine_is_lsxhl() (0) +#endif + +#ifdef CONFIG_MACH_SMARTLITE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SMARTLITE +# endif +# define machine_is_smartlite() (machine_arch_type == MACH_TYPE_SMARTLITE) +#else +# define machine_is_smartlite() (0) +#endif + +#ifdef CONFIG_MACH_CWS2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CWS2 +# endif +# define machine_is_cws2() (machine_arch_type == MACH_TYPE_CWS2) +#else +# define machine_is_cws2() (0) +#endif + +#ifdef CONFIG_MACH_M619 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_M619 +# endif +# define machine_is_m619() (machine_arch_type == MACH_TYPE_M619) +#else +# define machine_is_m619() (0) +#endif + +#ifdef CONFIG_MACH_SMARTVIEW +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SMARTVIEW +# endif +# define machine_is_smartview() (machine_arch_type == MACH_TYPE_SMARTVIEW) +#else +# define machine_is_smartview() (0) +#endif + +#ifdef CONFIG_MACH_LSA_SALSA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LSA_SALSA +# endif +# define machine_is_lsa_salsa() (machine_arch_type == MACH_TYPE_LSA_SALSA) +#else +# define machine_is_lsa_salsa() (0) +#endif + +#ifdef CONFIG_MACH_KIZBOX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_KIZBOX +# endif +# define machine_is_kizbox() (machine_arch_type == MACH_TYPE_KIZBOX) +#else +# define machine_is_kizbox() (0) +#endif + +#ifdef CONFIG_MACH_HTCCHARMER +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HTCCHARMER +# endif +# define machine_is_htccharmer() (machine_arch_type == MACH_TYPE_HTCCHARMER) +#else +# define machine_is_htccharmer() (0) +#endif + +#ifdef CONFIG_MACH_GUF_NESO_LT +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_GUF_NESO_LT +# endif +# define machine_is_guf_neso_lt() (machine_arch_type == MACH_TYPE_GUF_NESO_LT) +#else +# define machine_is_guf_neso_lt() (0) +#endif + +#ifdef CONFIG_MACH_PM9G45 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PM9G45 +# endif +# define machine_is_pm9g45() (machine_arch_type == MACH_TYPE_PM9G45) +#else +# define machine_is_pm9g45() (0) +#endif + +#ifdef CONFIG_MACH_HTCPANTHER +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HTCPANTHER +# endif +# define machine_is_htcpanther() (machine_arch_type == MACH_TYPE_HTCPANTHER) +#else +# define machine_is_htcpanther() (0) +#endif + +#ifdef CONFIG_MACH_HTCPANTHER_CDMA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HTCPANTHER_CDMA +# endif +# define machine_is_htcpanther_cdma() (machine_arch_type == MACH_TYPE_HTCPANTHER_CDMA) +#else +# define machine_is_htcpanther_cdma() (0) +#endif + +#ifdef CONFIG_MACH_REB01 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_REB01 +# endif +# define machine_is_reb01() (machine_arch_type == MACH_TYPE_REB01) +#else +# define machine_is_reb01() (0) +#endif + +#ifdef CONFIG_MACH_AQUILA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AQUILA +# endif +# define machine_is_aquila() (machine_arch_type == MACH_TYPE_AQUILA) +#else +# define machine_is_aquila() (0) +#endif + +#ifdef CONFIG_MACH_SPARK_SLS_HW2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SPARK_SLS_HW2 +# endif +# define machine_is_spark_sls_hw2() (machine_arch_type == MACH_TYPE_SPARK_SLS_HW2) +#else +# define machine_is_spark_sls_hw2() (0) +#endif + +#ifdef CONFIG_MACH_ESATA_SHEEVAPLUG +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ESATA_SHEEVAPLUG +# endif +# define machine_is_sheeva_esata() (machine_arch_type == MACH_TYPE_ESATA_SHEEVAPLUG) +#else +# define machine_is_sheeva_esata() (0) +#endif + +#ifdef CONFIG_MACH_MSM7X30_SURF +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MSM7X30_SURF +# endif +# define machine_is_msm7x30_surf() (machine_arch_type == MACH_TYPE_MSM7X30_SURF) +#else +# define machine_is_msm7x30_surf() (0) +#endif + +#ifdef CONFIG_MACH_MICRO2440 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MICRO2440 +# endif +# define machine_is_micro2440() (machine_arch_type == MACH_TYPE_MICRO2440) +#else +# define machine_is_micro2440() (0) +#endif + +#ifdef CONFIG_MACH_AM2440 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AM2440 +# endif +# define machine_is_am2440() (machine_arch_type == MACH_TYPE_AM2440) +#else +# define machine_is_am2440() (0) +#endif + +#ifdef CONFIG_MACH_TQ2440 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TQ2440 +# endif +# define machine_is_tq2440() (machine_arch_type == MACH_TYPE_TQ2440) +#else +# define machine_is_tq2440() (0) +#endif + +#ifdef CONFIG_MACH_LPC2478OEM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LPC2478OEM +# endif +# define machine_is_lpc2478oem() (machine_arch_type == MACH_TYPE_LPC2478OEM) +#else +# define machine_is_lpc2478oem() (0) +#endif + +#ifdef CONFIG_MACH_AK880X +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AK880X +# endif +# define machine_is_ak880x() (machine_arch_type == MACH_TYPE_AK880X) +#else +# define machine_is_ak880x() (0) +#endif + +#ifdef CONFIG_MACH_COBRA3530 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_COBRA3530 +# endif +# define machine_is_cobra3530() (machine_arch_type == MACH_TYPE_COBRA3530) +#else +# define machine_is_cobra3530() (0) +#endif + +#ifdef CONFIG_MACH_PMPPB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PMPPB +# endif +# define machine_is_pmppb() (machine_arch_type == MACH_TYPE_PMPPB) +#else +# define machine_is_pmppb() (0) +#endif + +#ifdef CONFIG_MACH_U6715 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_U6715 +# endif +# define machine_is_u6715() (machine_arch_type == MACH_TYPE_U6715) +#else +# define machine_is_u6715() (0) +#endif + +#ifdef CONFIG_MACH_AXAR1500_SENDER +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AXAR1500_SENDER +# endif +# define machine_is_axar1500_sender() (machine_arch_type == MACH_TYPE_AXAR1500_SENDER) +#else +# define machine_is_axar1500_sender() (0) +#endif + +#ifdef CONFIG_MACH_G30_DVB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_G30_DVB +# endif +# define machine_is_g30_dvb() (machine_arch_type == MACH_TYPE_G30_DVB) +#else +# define machine_is_g30_dvb() (0) +#endif + +#ifdef CONFIG_MACH_VC088X +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_VC088X +# endif +# define machine_is_vc088x() (machine_arch_type == MACH_TYPE_VC088X) +#else +# define machine_is_vc088x() (0) +#endif + +#ifdef CONFIG_MACH_MIOA702 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MIOA702 +# endif +# define machine_is_mioa702() (machine_arch_type == MACH_TYPE_MIOA702) +#else +# define machine_is_mioa702() (0) +#endif + +#ifdef CONFIG_MACH_HPMIN +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HPMIN +# endif +# define machine_is_hpmin() (machine_arch_type == MACH_TYPE_HPMIN) +#else +# define machine_is_hpmin() (0) +#endif + +#ifdef CONFIG_MACH_AK880XAK +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AK880XAK +# endif +# define machine_is_ak880xak() (machine_arch_type == MACH_TYPE_AK880XAK) +#else +# define machine_is_ak880xak() (0) +#endif + +#ifdef CONFIG_MACH_ARM926TOMAP850 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ARM926TOMAP850 +# endif +# define machine_is_arm926tomap850() (machine_arch_type == MACH_TYPE_ARM926TOMAP850) +#else +# define machine_is_arm926tomap850() (0) +#endif + +#ifdef CONFIG_MACH_LKEVM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LKEVM +# endif +# define machine_is_lkevm() (machine_arch_type == MACH_TYPE_LKEVM) +#else +# define machine_is_lkevm() (0) +#endif + +#ifdef CONFIG_MACH_MW6410 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MW6410 +# endif +# define machine_is_mw6410() (machine_arch_type == MACH_TYPE_MW6410) +#else +# define machine_is_mw6410() (0) +#endif + +#ifdef CONFIG_MACH_TERASTATION_WXL +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TERASTATION_WXL +# endif +# define machine_is_terastation_wxl() (machine_arch_type == MACH_TYPE_TERASTATION_WXL) +#else +# define machine_is_terastation_wxl() (0) +#endif + +#ifdef CONFIG_MACH_CPU8000E +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CPU8000E +# endif +# define machine_is_cpu8000e() (machine_arch_type == MACH_TYPE_CPU8000E) +#else +# define machine_is_cpu8000e() (0) +#endif + +#ifdef CONFIG_MACH_CATANIA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CATANIA +# endif +# define machine_is_catania() (machine_arch_type == MACH_TYPE_CATANIA) +#else +# define machine_is_catania() (0) +#endif + +#ifdef CONFIG_MACH_TOKYO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TOKYO +# endif +# define machine_is_tokyo() (machine_arch_type == MACH_TYPE_TOKYO) +#else +# define machine_is_tokyo() (0) +#endif + +#ifdef CONFIG_MACH_MSM7201A_SURF +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MSM7201A_SURF +# endif +# define machine_is_msm7201a_surf() (machine_arch_type == MACH_TYPE_MSM7201A_SURF) +#else +# define machine_is_msm7201a_surf() (0) +#endif + +#ifdef CONFIG_MACH_MSM7201A_FFA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MSM7201A_FFA +# endif +# define machine_is_msm7201a_ffa() (machine_arch_type == MACH_TYPE_MSM7201A_FFA) +#else +# define machine_is_msm7201a_ffa() (0) +#endif + +#ifdef CONFIG_MACH_MSM7X25_SURF +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MSM7X25_SURF +# endif +# define machine_is_msm7x25_surf() (machine_arch_type == MACH_TYPE_MSM7X25_SURF) +#else +# define machine_is_msm7x25_surf() (0) +#endif + +#ifdef CONFIG_MACH_MSM7X25_FFA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MSM7X25_FFA +# endif +# define machine_is_msm7x25_ffa() (machine_arch_type == MACH_TYPE_MSM7X25_FFA) +#else +# define machine_is_msm7x25_ffa() (0) +#endif + +#ifdef CONFIG_MACH_MSM7X27_SURF +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MSM7X27_SURF +# endif +# define machine_is_msm7x27_surf() (machine_arch_type == MACH_TYPE_MSM7X27_SURF) +#else +# define machine_is_msm7x27_surf() (0) +#endif + +#ifdef CONFIG_MACH_MSM7X27_FFA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MSM7X27_FFA +# endif +# define machine_is_msm7x27_ffa() (machine_arch_type == MACH_TYPE_MSM7X27_FFA) +#else +# define machine_is_msm7x27_ffa() (0) +#endif + +#ifdef CONFIG_MACH_MSM7X30_FFA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MSM7X30_FFA +# endif +# define machine_is_msm7x30_ffa() (machine_arch_type == MACH_TYPE_MSM7X30_FFA) +#else +# define machine_is_msm7x30_ffa() (0) +#endif + +#ifdef CONFIG_MACH_QSD8X50_SURF +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_QSD8X50_SURF +# endif +# define machine_is_qsd8x50_surf() (machine_arch_type == MACH_TYPE_QSD8X50_SURF) +#else +# define machine_is_qsd8x50_surf() (0) +#endif + +#ifdef CONFIG_MACH_QSD8X50_COMET +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_QSD8X50_COMET +# endif +# define machine_is_qsd8x50_comet() (machine_arch_type == MACH_TYPE_QSD8X50_COMET) +#else +# define machine_is_qsd8x50_comet() (0) +#endif + +#ifdef CONFIG_MACH_QSD8X50_FFA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_QSD8X50_FFA +# endif +# define machine_is_qsd8x50_ffa() (machine_arch_type == MACH_TYPE_QSD8X50_FFA) +#else +# define machine_is_qsd8x50_ffa() (0) +#endif + +#ifdef CONFIG_MACH_QSD8X50A_SURF +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_QSD8X50A_SURF +# endif +# define machine_is_qsd8x50a_surf() (machine_arch_type == MACH_TYPE_QSD8X50A_SURF) +#else +# define machine_is_qsd8x50a_surf() (0) +#endif + +#ifdef CONFIG_MACH_QSD8X50A_FFA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_QSD8X50A_FFA +# endif +# define machine_is_qsd8x50a_ffa() (machine_arch_type == MACH_TYPE_QSD8X50A_FFA) +#else +# define machine_is_qsd8x50a_ffa() (0) +#endif + +#ifdef CONFIG_MACH_ADX_XGCP10 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ADX_XGCP10 +# endif +# define machine_is_adx_xgcp10() (machine_arch_type == MACH_TYPE_ADX_XGCP10) +#else +# define machine_is_adx_xgcp10() (0) +#endif + +#ifdef CONFIG_MACH_MCGWUMTS2A +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MCGWUMTS2A +# endif +# define machine_is_mcgwumts2a() (machine_arch_type == MACH_TYPE_MCGWUMTS2A) +#else +# define machine_is_mcgwumts2a() (0) +#endif + +#ifdef CONFIG_MACH_MOBIKT +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MOBIKT +# endif +# define machine_is_mobikt() (machine_arch_type == MACH_TYPE_MOBIKT) +#else +# define machine_is_mobikt() (0) +#endif + +#ifdef CONFIG_MACH_MX53_EVK +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MX53_EVK +# endif +# define machine_is_mx53_evk() (machine_arch_type == MACH_TYPE_MX53_EVK) +#else +# define machine_is_mx53_evk() (0) +#endif + +#ifdef CONFIG_MACH_IGEP0030 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IGEP0030 +# endif +# define machine_is_igep0030() (machine_arch_type == MACH_TYPE_IGEP0030) +#else +# define machine_is_igep0030() (0) +#endif + +#ifdef CONFIG_MACH_AXELL_H40_H50_CTRL +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AXELL_H40_H50_CTRL +# endif +# define machine_is_axell_h40_h50_ctrl() (machine_arch_type == MACH_TYPE_AXELL_H40_H50_CTRL) +#else +# define machine_is_axell_h40_h50_ctrl() (0) +#endif + +#ifdef CONFIG_MACH_DTCOMMOD +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DTCOMMOD +# endif +# define machine_is_dtcommod() (machine_arch_type == MACH_TYPE_DTCOMMOD) +#else +# define machine_is_dtcommod() (0) +#endif + +#ifdef CONFIG_MACH_GOULD +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_GOULD +# endif +# define machine_is_gould() (machine_arch_type == MACH_TYPE_GOULD) +#else +# define machine_is_gould() (0) +#endif + +#ifdef CONFIG_MACH_SIBERIA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SIBERIA +# endif +# define machine_is_siberia() (machine_arch_type == MACH_TYPE_SIBERIA) +#else +# define machine_is_siberia() (0) +#endif + +#ifdef CONFIG_MACH_SBC3530 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SBC3530 +# endif +# define machine_is_sbc3530() (machine_arch_type == MACH_TYPE_SBC3530) +#else +# define machine_is_sbc3530() (0) +#endif + +#ifdef CONFIG_MACH_QARM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_QARM +# endif +# define machine_is_qarm() (machine_arch_type == MACH_TYPE_QARM) +#else +# define machine_is_qarm() (0) +#endif + +#ifdef CONFIG_MACH_MIPS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MIPS +# endif +# define machine_is_mips() (machine_arch_type == MACH_TYPE_MIPS) +#else +# define machine_is_mips() (0) +#endif + +#ifdef CONFIG_MACH_MX27GRB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MX27GRB +# endif +# define machine_is_mx27grb() (machine_arch_type == MACH_TYPE_MX27GRB) +#else +# define machine_is_mx27grb() (0) +#endif + +#ifdef CONFIG_MACH_SBC8100 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SBC8100 +# endif +# define machine_is_sbc8100() (machine_arch_type == MACH_TYPE_SBC8100) +#else +# define machine_is_sbc8100() (0) +#endif + +#ifdef CONFIG_MACH_SAARB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SAARB +# endif +# define machine_is_saarb() (machine_arch_type == MACH_TYPE_SAARB) +#else +# define machine_is_saarb() (0) +#endif + +#ifdef CONFIG_MACH_OMAP3MINI +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAP3MINI +# endif +# define machine_is_omap3mini() (machine_arch_type == MACH_TYPE_OMAP3MINI) +#else +# define machine_is_omap3mini() (0) +#endif + +#ifdef CONFIG_MACH_CNMBOOK7SE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CNMBOOK7SE +# endif +# define machine_is_cnmbook7se() (machine_arch_type == MACH_TYPE_CNMBOOK7SE) +#else +# define machine_is_cnmbook7se() (0) +#endif + +#ifdef CONFIG_MACH_CATAN +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CATAN +# endif +# define machine_is_catan() (machine_arch_type == MACH_TYPE_CATAN) +#else +# define machine_is_catan() (0) +#endif + +#ifdef CONFIG_MACH_HARMONY +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HARMONY +# endif +# define machine_is_harmony() (machine_arch_type == MACH_TYPE_HARMONY) +#else +# define machine_is_harmony() (0) +#endif + +#ifdef CONFIG_MACH_TONGA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TONGA +# endif +# define machine_is_tonga() (machine_arch_type == MACH_TYPE_TONGA) +#else +# define machine_is_tonga() (0) +#endif + +#ifdef CONFIG_MACH_CYBOOK_ORIZON +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CYBOOK_ORIZON +# endif +# define machine_is_cybook_orizon() (machine_arch_type == MACH_TYPE_CYBOOK_ORIZON) +#else +# define machine_is_cybook_orizon() (0) +#endif + +#ifdef CONFIG_MACH_HTCRHODIUMCDMA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HTCRHODIUMCDMA +# endif +# define machine_is_htcrhodiumcdma() (machine_arch_type == MACH_TYPE_HTCRHODIUMCDMA) +#else +# define machine_is_htcrhodiumcdma() (0) +#endif + +#ifdef CONFIG_MACH_EPC_G45 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EPC_G45 +# endif +# define machine_is_epc_g45() (machine_arch_type == MACH_TYPE_EPC_G45) +#else +# define machine_is_epc_g45() (0) +#endif + +#ifdef CONFIG_MACH_EPC_LPC3250 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EPC_LPC3250 +# endif +# define machine_is_epc_lpc3250() (machine_arch_type == MACH_TYPE_EPC_LPC3250) +#else +# define machine_is_epc_lpc3250() (0) +#endif + +#ifdef CONFIG_MACH_MXC91341EVB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MXC91341EVB +# endif +# define machine_is_mxc91341evb() (machine_arch_type == MACH_TYPE_MXC91341EVB) +#else +# define machine_is_mxc91341evb() (0) +#endif + +#ifdef CONFIG_MACH_RTW1000 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_RTW1000 +# endif +# define machine_is_rtw1000() (machine_arch_type == MACH_TYPE_RTW1000) +#else +# define machine_is_rtw1000() (0) +#endif + +#ifdef CONFIG_MACH_BOBCAT +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BOBCAT +# endif +# define machine_is_bobcat() (machine_arch_type == MACH_TYPE_BOBCAT) +#else +# define machine_is_bobcat() (0) +#endif + +#ifdef CONFIG_MACH_TRIZEPS6 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TRIZEPS6 +# endif +# define machine_is_trizeps6() (machine_arch_type == MACH_TYPE_TRIZEPS6) +#else +# define machine_is_trizeps6() (0) +#endif + +#ifdef CONFIG_MACH_MSM7X30_FLUID +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MSM7X30_FLUID +# endif +# define machine_is_msm7x30_fluid() (machine_arch_type == MACH_TYPE_MSM7X30_FLUID) +#else +# define machine_is_msm7x30_fluid() (0) +#endif + +#ifdef CONFIG_MACH_NEDAP9263 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NEDAP9263 +# endif +# define machine_is_nedap9263() (machine_arch_type == MACH_TYPE_NEDAP9263) +#else +# define machine_is_nedap9263() (0) +#endif + +#ifdef CONFIG_MACH_NETGEAR_MS2110 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NETGEAR_MS2110 +# endif +# define machine_is_netgear_ms2110() (machine_arch_type == MACH_TYPE_NETGEAR_MS2110) +#else +# define machine_is_netgear_ms2110() (0) +#endif + +#ifdef CONFIG_MACH_BMX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BMX +# endif +# define machine_is_bmx() (machine_arch_type == MACH_TYPE_BMX) +#else +# define machine_is_bmx() (0) +#endif + +#ifdef CONFIG_MACH_NETSTREAM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NETSTREAM +# endif +# define machine_is_netstream() (machine_arch_type == MACH_TYPE_NETSTREAM) +#else +# define machine_is_netstream() (0) +#endif + +#ifdef CONFIG_MACH_VPNEXT_RCU +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_VPNEXT_RCU +# endif +# define machine_is_vpnext_rcu() (machine_arch_type == MACH_TYPE_VPNEXT_RCU) +#else +# define machine_is_vpnext_rcu() (0) +#endif + +#ifdef CONFIG_MACH_VPNEXT_MPU +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_VPNEXT_MPU +# endif +# define machine_is_vpnext_mpu() (machine_arch_type == MACH_TYPE_VPNEXT_MPU) +#else +# define machine_is_vpnext_mpu() (0) +#endif + +#ifdef CONFIG_MACH_BCMRING_TABLET_V1 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BCMRING_TABLET_V1 +# endif +# define machine_is_bcmring_tablet_v1() (machine_arch_type == MACH_TYPE_BCMRING_TABLET_V1) +#else +# define machine_is_bcmring_tablet_v1() (0) +#endif + +#ifdef CONFIG_MACH_SGARM10 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SGARM10 +# endif +# define machine_is_sgarm10() (machine_arch_type == MACH_TYPE_SGARM10) +#else +# define machine_is_sgarm10() (0) +#endif + +#ifdef CONFIG_MACH_CM_T3517 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CM_T3517 +# endif +# define machine_is_cm_t3517() (machine_arch_type == MACH_TYPE_CM_T3517) +#else +# define machine_is_cm_t3517() (0) +#endif + +#ifdef CONFIG_MACH_OMAP3_CPS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAP3_CPS +# endif +# define machine_is_omap3_cps() (machine_arch_type == MACH_TYPE_OMAP3_CPS) +#else +# define machine_is_omap3_cps() (0) +#endif + +#ifdef CONFIG_MACH_AXAR1500_RECEIVER +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AXAR1500_RECEIVER +# endif +# define machine_is_axar1500_receiver() (machine_arch_type == MACH_TYPE_AXAR1500_RECEIVER) +#else +# define machine_is_axar1500_receiver() (0) +#endif + +#ifdef CONFIG_MACH_WBD222 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_WBD222 +# endif +# define machine_is_wbd222() (machine_arch_type == MACH_TYPE_WBD222) +#else +# define machine_is_wbd222() (0) +#endif + +#ifdef CONFIG_MACH_MT65XX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MT65XX +# endif +# define machine_is_mt65xx() (machine_arch_type == MACH_TYPE_MT65XX) +#else +# define machine_is_mt65xx() (0) +#endif + +#ifdef CONFIG_MACH_MSM8X60_SURF +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MSM8X60_SURF +# endif +# define machine_is_msm8x60_surf() (machine_arch_type == MACH_TYPE_MSM8X60_SURF) +#else +# define machine_is_msm8x60_surf() (0) +#endif + +#ifdef CONFIG_MACH_MSM8X60_SIM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MSM8X60_SIM +# endif +# define machine_is_msm8x60_sim() (machine_arch_type == MACH_TYPE_MSM8X60_SIM) +#else +# define machine_is_msm8x60_sim() (0) +#endif + +#ifdef CONFIG_MACH_VMC300 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_VMC300 +# endif +# define machine_is_vmc300() (machine_arch_type == MACH_TYPE_VMC300) +#else +# define machine_is_vmc300() (0) +#endif + +#ifdef CONFIG_MACH_TCC8000_SDK +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TCC8000_SDK +# endif +# define machine_is_tcc8000_sdk() (machine_arch_type == MACH_TYPE_TCC8000_SDK) +#else +# define machine_is_tcc8000_sdk() (0) +#endif + +#ifdef CONFIG_MACH_NANOS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NANOS +# endif +# define machine_is_nanos() (machine_arch_type == MACH_TYPE_NANOS) +#else +# define machine_is_nanos() (0) +#endif + +#ifdef CONFIG_MACH_STAMP9G10 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_STAMP9G10 +# endif +# define machine_is_stamp9g10() (machine_arch_type == MACH_TYPE_STAMP9G10) +#else +# define machine_is_stamp9g10() (0) +#endif + +#ifdef CONFIG_MACH_STAMP9G45 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_STAMP9G45 +# endif +# define machine_is_stamp9g45() (machine_arch_type == MACH_TYPE_STAMP9G45) +#else +# define machine_is_stamp9g45() (0) +#endif + +#ifdef CONFIG_MACH_H6053 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_H6053 +# endif +# define machine_is_h6053() (machine_arch_type == MACH_TYPE_H6053) +#else +# define machine_is_h6053() (0) +#endif + +#ifdef CONFIG_MACH_SMINT01 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SMINT01 +# endif +# define machine_is_smint01() (machine_arch_type == MACH_TYPE_SMINT01) +#else +# define machine_is_smint01() (0) +#endif + +#ifdef CONFIG_MACH_PRTLVT2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PRTLVT2 +# endif +# define machine_is_prtlvt2() (machine_arch_type == MACH_TYPE_PRTLVT2) +#else +# define machine_is_prtlvt2() (0) +#endif + +#ifdef CONFIG_MACH_AP420 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AP420 +# endif +# define machine_is_ap420() (machine_arch_type == MACH_TYPE_AP420) +#else +# define machine_is_ap420() (0) +#endif + +#ifdef CONFIG_MACH_HTCSHIFT +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HTCSHIFT +# endif +# define machine_is_htcclio() (machine_arch_type == MACH_TYPE_HTCSHIFT) +#else +# define machine_is_htcclio() (0) +#endif + +#ifdef CONFIG_MACH_DAVINCI_DM365_FC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DAVINCI_DM365_FC +# endif +# define machine_is_davinci_dm365_fc() (machine_arch_type == MACH_TYPE_DAVINCI_DM365_FC) +#else +# define machine_is_davinci_dm365_fc() (0) +#endif + +#ifdef CONFIG_MACH_MSM8X55_SURF +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MSM8X55_SURF +# endif +# define machine_is_msm8x55_surf() (machine_arch_type == MACH_TYPE_MSM8X55_SURF) +#else +# define machine_is_msm8x55_surf() (0) +#endif + +#ifdef CONFIG_MACH_MSM8X55_FFA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MSM8X55_FFA +# endif +# define machine_is_msm8x55_ffa() (machine_arch_type == MACH_TYPE_MSM8X55_FFA) +#else +# define machine_is_msm8x55_ffa() (0) +#endif + +#ifdef CONFIG_MACH_ESL_VAMANA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ESL_VAMANA +# endif +# define machine_is_esl_vamana() (machine_arch_type == MACH_TYPE_ESL_VAMANA) +#else +# define machine_is_esl_vamana() (0) +#endif + +#ifdef CONFIG_MACH_SBC35 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SBC35 +# endif +# define machine_is_sbc35() (machine_arch_type == MACH_TYPE_SBC35) +#else +# define machine_is_sbc35() (0) +#endif + +#ifdef CONFIG_MACH_MPX6446 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MPX6446 +# endif +# define machine_is_mpx6446() (machine_arch_type == MACH_TYPE_MPX6446) +#else +# define machine_is_mpx6446() (0) +#endif + +#ifdef CONFIG_MACH_OREO_CONTROLLER +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OREO_CONTROLLER +# endif +# define machine_is_oreo_controller() (machine_arch_type == MACH_TYPE_OREO_CONTROLLER) +#else +# define machine_is_oreo_controller() (0) +#endif + +#ifdef CONFIG_MACH_KOPIN_MODELS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_KOPIN_MODELS +# endif +# define machine_is_kopin_models() (machine_arch_type == MACH_TYPE_KOPIN_MODELS) +#else +# define machine_is_kopin_models() (0) +#endif + +#ifdef CONFIG_MACH_TTC_VISION2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TTC_VISION2 +# endif +# define machine_is_ttc_vision2() (machine_arch_type == MACH_TYPE_TTC_VISION2) +#else +# define machine_is_ttc_vision2() (0) +#endif + +#ifdef CONFIG_MACH_CNS3420VB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CNS3420VB +# endif +# define machine_is_cns3420vb() (machine_arch_type == MACH_TYPE_CNS3420VB) +#else +# define machine_is_cns3420vb() (0) +#endif + +#ifdef CONFIG_MACH_LPC2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LPC2 +# endif +# define machine_is_lpc_evo() (machine_arch_type == MACH_TYPE_LPC2) +#else +# define machine_is_lpc_evo() (0) +#endif + +#ifdef CONFIG_MACH_OLYMPUS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OLYMPUS +# endif +# define machine_is_olympus() (machine_arch_type == MACH_TYPE_OLYMPUS) +#else +# define machine_is_olympus() (0) +#endif + +#ifdef CONFIG_MACH_VORTEX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_VORTEX +# endif +# define machine_is_vortex() (machine_arch_type == MACH_TYPE_VORTEX) +#else +# define machine_is_vortex() (0) +#endif + +#ifdef CONFIG_MACH_S5PC200 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_S5PC200 +# endif +# define machine_is_s5pc200() (machine_arch_type == MACH_TYPE_S5PC200) +#else +# define machine_is_s5pc200() (0) +#endif + +#ifdef CONFIG_MACH_ECUCORE_9263 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ECUCORE_9263 +# endif +# define machine_is_ecucore_9263() (machine_arch_type == MACH_TYPE_ECUCORE_9263) +#else +# define machine_is_ecucore_9263() (0) +#endif + +#ifdef CONFIG_MACH_SMDKC200 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SMDKC200 +# endif +# define machine_is_smdkc200() (machine_arch_type == MACH_TYPE_SMDKC200) +#else +# define machine_is_smdkc200() (0) +#endif + +#ifdef CONFIG_MACH_EMSISO_SX27 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EMSISO_SX27 +# endif +# define machine_is_emsiso_sx27() (machine_arch_type == MACH_TYPE_EMSISO_SX27) +#else +# define machine_is_emsiso_sx27() (0) +#endif + +#ifdef CONFIG_MACH_APX_SOM9G45_EK +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_APX_SOM9G45_EK +# endif +# define machine_is_apx_som9g45_ek() (machine_arch_type == MACH_TYPE_APX_SOM9G45_EK) +#else +# define machine_is_apx_som9g45_ek() (0) +#endif + +#ifdef CONFIG_MACH_SONGSHAN +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SONGSHAN +# endif +# define machine_is_songshan() (machine_arch_type == MACH_TYPE_SONGSHAN) +#else +# define machine_is_songshan() (0) +#endif + +#ifdef CONFIG_MACH_TIANSHAN +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TIANSHAN +# endif +# define machine_is_tianshan() (machine_arch_type == MACH_TYPE_TIANSHAN) +#else +# define machine_is_tianshan() (0) +#endif + +#ifdef CONFIG_MACH_VPX500 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_VPX500 +# endif +# define machine_is_vpx500() (machine_arch_type == MACH_TYPE_VPX500) +#else +# define machine_is_vpx500() (0) +#endif + +#ifdef CONFIG_MACH_AM3517SAM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AM3517SAM +# endif +# define machine_is_am3517sam() (machine_arch_type == MACH_TYPE_AM3517SAM) +#else +# define machine_is_am3517sam() (0) +#endif + +#ifdef CONFIG_MACH_SKAT91_SIM508 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SKAT91_SIM508 +# endif +# define machine_is_skat91_sim508() (machine_arch_type == MACH_TYPE_SKAT91_SIM508) +#else +# define machine_is_skat91_sim508() (0) +#endif + +#ifdef CONFIG_MACH_SKAT91_S3E +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SKAT91_S3E +# endif +# define machine_is_skat91_s3e() (machine_arch_type == MACH_TYPE_SKAT91_S3E) +#else +# define machine_is_skat91_s3e() (0) +#endif + +#ifdef CONFIG_MACH_OMAP4_PANDA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAP4_PANDA +# endif +# define machine_is_omap4_panda() (machine_arch_type == MACH_TYPE_OMAP4_PANDA) +#else +# define machine_is_omap4_panda() (0) +#endif + +#ifdef CONFIG_MACH_DF7220 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DF7220 +# endif +# define machine_is_df7220() (machine_arch_type == MACH_TYPE_DF7220) +#else +# define machine_is_df7220() (0) +#endif + +#ifdef CONFIG_MACH_NEMINI +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NEMINI +# endif +# define machine_is_nemini() (machine_arch_type == MACH_TYPE_NEMINI) +#else +# define machine_is_nemini() (0) +#endif + +#ifdef CONFIG_MACH_T8200 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_T8200 +# endif +# define machine_is_t8200() (machine_arch_type == MACH_TYPE_T8200) +#else +# define machine_is_t8200() (0) +#endif + +#ifdef CONFIG_MACH_APF51 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_APF51 +# endif +# define machine_is_apf51() (machine_arch_type == MACH_TYPE_APF51) +#else +# define machine_is_apf51() (0) +#endif + +#ifdef CONFIG_MACH_DR_RC_UNIT +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DR_RC_UNIT +# endif +# define machine_is_dr_rc_unit() (machine_arch_type == MACH_TYPE_DR_RC_UNIT) +#else +# define machine_is_dr_rc_unit() (0) +#endif + +#ifdef CONFIG_MACH_BORDEAUX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BORDEAUX +# endif +# define machine_is_bordeaux() (machine_arch_type == MACH_TYPE_BORDEAUX) +#else +# define machine_is_bordeaux() (0) +#endif + +#ifdef CONFIG_MACH_CATANIA_B +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CATANIA_B +# endif +# define machine_is_catania_b() (machine_arch_type == MACH_TYPE_CATANIA_B) +#else +# define machine_is_catania_b() (0) +#endif + +#ifdef CONFIG_MACH_MX51_OCEAN +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MX51_OCEAN +# endif +# define machine_is_mx51_ocean() (machine_arch_type == MACH_TYPE_MX51_OCEAN) +#else +# define machine_is_mx51_ocean() (0) +#endif + +#ifdef CONFIG_MACH_TI8168EVM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TI8168EVM +# endif +# define machine_is_ti8168evm() (machine_arch_type == MACH_TYPE_TI8168EVM) +#else +# define machine_is_ti8168evm() (0) +#endif + +#ifdef CONFIG_MACH_NEOCOREOMAP +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NEOCOREOMAP +# endif +# define machine_is_neocoreomap() (machine_arch_type == MACH_TYPE_NEOCOREOMAP) +#else +# define machine_is_neocoreomap() (0) +#endif + +#ifdef CONFIG_MACH_WITHINGS_WBP +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_WITHINGS_WBP +# endif +# define machine_is_withings_wbp() (machine_arch_type == MACH_TYPE_WITHINGS_WBP) +#else +# define machine_is_withings_wbp() (0) +#endif + +#ifdef CONFIG_MACH_DBPS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DBPS +# endif +# define machine_is_dbps() (machine_arch_type == MACH_TYPE_DBPS) +#else +# define machine_is_dbps() (0) +#endif + +#ifdef CONFIG_MACH_SBC9261 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SBC9261 +# endif +# define machine_is_at91sam9261() (machine_arch_type == MACH_TYPE_SBC9261) +#else +# define machine_is_at91sam9261() (0) +#endif + +#ifdef CONFIG_MACH_PCBFP0001 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PCBFP0001 +# endif +# define machine_is_pcbfp0001() (machine_arch_type == MACH_TYPE_PCBFP0001) +#else +# define machine_is_pcbfp0001() (0) +#endif + +#ifdef CONFIG_MACH_SPEEDY +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SPEEDY +# endif +# define machine_is_speedy() (machine_arch_type == MACH_TYPE_SPEEDY) +#else +# define machine_is_speedy() (0) +#endif + +#ifdef CONFIG_MACH_CHRYSAOR +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CHRYSAOR +# endif +# define machine_is_chrysaor() (machine_arch_type == MACH_TYPE_CHRYSAOR) +#else +# define machine_is_chrysaor() (0) +#endif + +#ifdef CONFIG_MACH_TANGO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TANGO +# endif +# define machine_is_tango() (machine_arch_type == MACH_TYPE_TANGO) +#else +# define machine_is_tango() (0) +#endif + +#ifdef CONFIG_MACH_SYNOLOGY_DSX11 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SYNOLOGY_DSX11 +# endif +# define machine_is_synology_dsx11() (machine_arch_type == MACH_TYPE_SYNOLOGY_DSX11) +#else +# define machine_is_synology_dsx11() (0) +#endif + +#ifdef CONFIG_MACH_HANLIN_V3EXT +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HANLIN_V3EXT +# endif +# define machine_is_hanlin_v3ext() (machine_arch_type == MACH_TYPE_HANLIN_V3EXT) +#else +# define machine_is_hanlin_v3ext() (0) +#endif + +#ifdef CONFIG_MACH_HANLIN_V5 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HANLIN_V5 +# endif +# define machine_is_hanlin_v5() (machine_arch_type == MACH_TYPE_HANLIN_V5) +#else +# define machine_is_hanlin_v5() (0) +#endif + +#ifdef CONFIG_MACH_HANLIN_V3PLUS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HANLIN_V3PLUS +# endif +# define machine_is_hanlin_v3plus() (machine_arch_type == MACH_TYPE_HANLIN_V3PLUS) +#else +# define machine_is_hanlin_v3plus() (0) +#endif + +#ifdef CONFIG_MACH_IRIVER_STORY +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IRIVER_STORY +# endif +# define machine_is_iriver_story() (machine_arch_type == MACH_TYPE_IRIVER_STORY) +#else +# define machine_is_iriver_story() (0) +#endif + +#ifdef CONFIG_MACH_IREX_ILIAD +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IREX_ILIAD +# endif +# define machine_is_irex_iliad() (machine_arch_type == MACH_TYPE_IREX_ILIAD) +#else +# define machine_is_irex_iliad() (0) +#endif + +#ifdef CONFIG_MACH_IREX_DR1000 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IREX_DR1000 +# endif +# define machine_is_irex_dr1000() (machine_arch_type == MACH_TYPE_IREX_DR1000) +#else +# define machine_is_irex_dr1000() (0) +#endif + +#ifdef CONFIG_MACH_TETON_BGA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TETON_BGA +# endif +# define machine_is_teton_bga() (machine_arch_type == MACH_TYPE_TETON_BGA) +#else +# define machine_is_teton_bga() (0) +#endif + +#ifdef CONFIG_MACH_SNAPPER9G45 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SNAPPER9G45 +# endif +# define machine_is_snapper9g45() (machine_arch_type == MACH_TYPE_SNAPPER9G45) +#else +# define machine_is_snapper9g45() (0) +#endif + +#ifdef CONFIG_MACH_TAM3517 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TAM3517 +# endif +# define machine_is_tam3517() (machine_arch_type == MACH_TYPE_TAM3517) +#else +# define machine_is_tam3517() (0) +#endif + +#ifdef CONFIG_MACH_PDC100 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PDC100 +# endif +# define machine_is_pdc100() (machine_arch_type == MACH_TYPE_PDC100) +#else +# define machine_is_pdc100() (0) +#endif + +#ifdef CONFIG_MACH_EUKREA_CPUIMX25 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EUKREA_CPUIMX25 +# endif +# define machine_is_eukrea_cpuimx25sd() (machine_arch_type == MACH_TYPE_EUKREA_CPUIMX25) +#else +# define machine_is_eukrea_cpuimx25sd() (0) +#endif + +#ifdef CONFIG_MACH_EUKREA_CPUIMX35 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EUKREA_CPUIMX35 +# endif +# define machine_is_eukrea_cpuimx35sd() (machine_arch_type == MACH_TYPE_EUKREA_CPUIMX35) +#else +# define machine_is_eukrea_cpuimx35sd() (0) +#endif + +#ifdef CONFIG_MACH_EUKREA_CPUIMX51SD +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EUKREA_CPUIMX51SD +# endif +# define machine_is_eukrea_cpuimx51sd() (machine_arch_type == MACH_TYPE_EUKREA_CPUIMX51SD) +#else +# define machine_is_eukrea_cpuimx51sd() (0) +#endif + +#ifdef CONFIG_MACH_EUKREA_CPUIMX51 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EUKREA_CPUIMX51 +# endif +# define machine_is_eukrea_cpuimx51() (machine_arch_type == MACH_TYPE_EUKREA_CPUIMX51) +#else +# define machine_is_eukrea_cpuimx51() (0) +#endif + +#ifdef CONFIG_MACH_P565 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_P565 +# endif +# define machine_is_p565() (machine_arch_type == MACH_TYPE_P565) +#else +# define machine_is_p565() (0) +#endif + +#ifdef CONFIG_MACH_ACER_A4 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ACER_A4 +# endif +# define machine_is_acer_a4() (machine_arch_type == MACH_TYPE_ACER_A4) +#else +# define machine_is_acer_a4() (0) +#endif + +#ifdef CONFIG_MACH_DAVINCI_DM368_BIP +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DAVINCI_DM368_BIP +# endif +# define machine_is_davinci_dm368_bip() (machine_arch_type == MACH_TYPE_DAVINCI_DM368_BIP) +#else +# define machine_is_davinci_dm368_bip() (0) +#endif + +#ifdef CONFIG_MACH_ESHARE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ESHARE +# endif +# define machine_is_eshare() (machine_arch_type == MACH_TYPE_ESHARE) +#else +# define machine_is_eshare() (0) +#endif + +#ifdef CONFIG_MACH_HW_OMAPL138_EUROPA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HW_OMAPL138_EUROPA +# endif +# define machine_is_omapl138_europa() (machine_arch_type == MACH_TYPE_HW_OMAPL138_EUROPA) +#else +# define machine_is_omapl138_europa() (0) +#endif + +#ifdef CONFIG_MACH_WLBARGN +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_WLBARGN +# endif +# define machine_is_wlbargn() (machine_arch_type == MACH_TYPE_WLBARGN) +#else +# define machine_is_wlbargn() (0) +#endif + +#ifdef CONFIG_MACH_BM170 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BM170 +# endif +# define machine_is_bm170() (machine_arch_type == MACH_TYPE_BM170) +#else +# define machine_is_bm170() (0) +#endif + +#ifdef CONFIG_MACH_NETSPACE_MINI_V2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NETSPACE_MINI_V2 +# endif +# define machine_is_netspace_mini_v2() (machine_arch_type == MACH_TYPE_NETSPACE_MINI_V2) +#else +# define machine_is_netspace_mini_v2() (0) +#endif + +#ifdef CONFIG_MACH_NETSPACE_PLUG_V2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NETSPACE_PLUG_V2 +# endif +# define machine_is_netspace_plug_v2() (machine_arch_type == MACH_TYPE_NETSPACE_PLUG_V2) +#else +# define machine_is_netspace_plug_v2() (0) +#endif + +#ifdef CONFIG_MACH_SIEMENS_L1 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SIEMENS_L1 +# endif +# define machine_is_siemens_l1() (machine_arch_type == MACH_TYPE_SIEMENS_L1) +#else +# define machine_is_siemens_l1() (0) +#endif + +#ifdef CONFIG_MACH_ELV_LCU1 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ELV_LCU1 +# endif +# define machine_is_elv_lcu1() (machine_arch_type == MACH_TYPE_ELV_LCU1) +#else +# define machine_is_elv_lcu1() (0) +#endif + +#ifdef CONFIG_MACH_MCU1 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MCU1 +# endif +# define machine_is_mcu1() (machine_arch_type == MACH_TYPE_MCU1) +#else +# define machine_is_mcu1() (0) +#endif + +#ifdef CONFIG_MACH_OMAP3_TAO3530 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAP3_TAO3530 +# endif +# define machine_is_omap3_tao3530() (machine_arch_type == MACH_TYPE_OMAP3_TAO3530) +#else +# define machine_is_omap3_tao3530() (0) +#endif + +#ifdef CONFIG_MACH_OMAP3_PCUTOUCH +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAP3_PCUTOUCH +# endif +# define machine_is_omap3_pcutouch() (machine_arch_type == MACH_TYPE_OMAP3_PCUTOUCH) +#else +# define machine_is_omap3_pcutouch() (0) +#endif + +#ifdef CONFIG_MACH_SMDKC210 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SMDKC210 +# endif +# define machine_is_smdkc210() (machine_arch_type == MACH_TYPE_SMDKC210) +#else +# define machine_is_smdkc210() (0) +#endif + +#ifdef CONFIG_MACH_OMAP3_BRAILLO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAP3_BRAILLO +# endif +# define machine_is_omap3_braillo() (machine_arch_type == MACH_TYPE_OMAP3_BRAILLO) +#else +# define machine_is_omap3_braillo() (0) +#endif + +#ifdef CONFIG_MACH_SPYPLUG +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SPYPLUG +# endif +# define machine_is_spyplug() (machine_arch_type == MACH_TYPE_SPYPLUG) +#else +# define machine_is_spyplug() (0) +#endif + +#ifdef CONFIG_MACH_GINGER +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_GINGER +# endif +# define machine_is_ginger() (machine_arch_type == MACH_TYPE_GINGER) +#else +# define machine_is_ginger() (0) +#endif + +#ifdef CONFIG_MACH_TNY_T3530 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TNY_T3530 +# endif +# define machine_is_tny_t3530() (machine_arch_type == MACH_TYPE_TNY_T3530) +#else +# define machine_is_tny_t3530() (0) +#endif + +#ifdef CONFIG_MACH_PCA102 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PCA102 +# endif +# define machine_is_pca102() (machine_arch_type == MACH_TYPE_PCA102) +#else +# define machine_is_pca102() (0) +#endif + +#ifdef CONFIG_MACH_SPADE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SPADE +# endif +# define machine_is_spade() (machine_arch_type == MACH_TYPE_SPADE) +#else +# define machine_is_spade() (0) +#endif + +#ifdef CONFIG_MACH_MXC25_TOPAZ +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MXC25_TOPAZ +# endif +# define machine_is_mxc25_topaz() (machine_arch_type == MACH_TYPE_MXC25_TOPAZ) +#else +# define machine_is_mxc25_topaz() (0) +#endif + +#ifdef CONFIG_MACH_T5325 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_T5325 +# endif +# define machine_is_t5325() (machine_arch_type == MACH_TYPE_T5325) +#else +# define machine_is_t5325() (0) +#endif + +#ifdef CONFIG_MACH_GW2361 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_GW2361 +# endif +# define machine_is_gw2361() (machine_arch_type == MACH_TYPE_GW2361) +#else +# define machine_is_gw2361() (0) +#endif + +#ifdef CONFIG_MACH_ELOG +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ELOG +# endif +# define machine_is_elog() (machine_arch_type == MACH_TYPE_ELOG) +#else +# define machine_is_elog() (0) +#endif + +#ifdef CONFIG_MACH_INCOME +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_INCOME +# endif +# define machine_is_income() (machine_arch_type == MACH_TYPE_INCOME) +#else +# define machine_is_income() (0) +#endif + +#ifdef CONFIG_MACH_BCM589X +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BCM589X +# endif +# define machine_is_bcm589x() (machine_arch_type == MACH_TYPE_BCM589X) +#else +# define machine_is_bcm589x() (0) +#endif + +#ifdef CONFIG_MACH_ETNA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ETNA +# endif +# define machine_is_etna() (machine_arch_type == MACH_TYPE_ETNA) +#else +# define machine_is_etna() (0) +#endif + +#ifdef CONFIG_MACH_HAWKS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HAWKS +# endif +# define machine_is_hawks() (machine_arch_type == MACH_TYPE_HAWKS) +#else +# define machine_is_hawks() (0) +#endif + +#ifdef CONFIG_MACH_MESON +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MESON +# endif +# define machine_is_meson() (machine_arch_type == MACH_TYPE_MESON) +#else +# define machine_is_meson() (0) +#endif + +#ifdef CONFIG_MACH_XSBASE255 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_XSBASE255 +# endif +# define machine_is_xsbase255() (machine_arch_type == MACH_TYPE_XSBASE255) +#else +# define machine_is_xsbase255() (0) +#endif + +#ifdef CONFIG_MACH_PVM2030 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PVM2030 +# endif +# define machine_is_pvm2030() (machine_arch_type == MACH_TYPE_PVM2030) +#else +# define machine_is_pvm2030() (0) +#endif + +#ifdef CONFIG_MACH_MIOA502 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MIOA502 +# endif +# define machine_is_mioa502() (machine_arch_type == MACH_TYPE_MIOA502) +#else +# define machine_is_mioa502() (0) +#endif + +#ifdef CONFIG_MACH_VVBOX_SDORIG2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_VVBOX_SDORIG2 +# endif +# define machine_is_vvbox_sdorig2() (machine_arch_type == MACH_TYPE_VVBOX_SDORIG2) +#else +# define machine_is_vvbox_sdorig2() (0) +#endif + +#ifdef CONFIG_MACH_VVBOX_SDLITE2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_VVBOX_SDLITE2 +# endif +# define machine_is_vvbox_sdlite2() (machine_arch_type == MACH_TYPE_VVBOX_SDLITE2) +#else +# define machine_is_vvbox_sdlite2() (0) +#endif + +#ifdef CONFIG_MACH_VVBOX_SDPRO4 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_VVBOX_SDPRO4 +# endif +# define machine_is_vvbox_sdpro4() (machine_arch_type == MACH_TYPE_VVBOX_SDPRO4) +#else +# define machine_is_vvbox_sdpro4() (0) +#endif + +#ifdef CONFIG_MACH_HTC_SPV_M700 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HTC_SPV_M700 +# endif +# define machine_is_htc_spv_m700() (machine_arch_type == MACH_TYPE_HTC_SPV_M700) +#else +# define machine_is_htc_spv_m700() (0) +#endif + +#ifdef CONFIG_MACH_MX257SX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MX257SX +# endif +# define machine_is_mx257sx() (machine_arch_type == MACH_TYPE_MX257SX) +#else +# define machine_is_mx257sx() (0) +#endif + +#ifdef CONFIG_MACH_GONI +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_GONI +# endif +# define machine_is_goni() (machine_arch_type == MACH_TYPE_GONI) +#else +# define machine_is_goni() (0) +#endif + +#ifdef CONFIG_MACH_MSM8X55_SVLTE_FFA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MSM8X55_SVLTE_FFA +# endif +# define machine_is_msm8x55_svlte_ffa() (machine_arch_type == MACH_TYPE_MSM8X55_SVLTE_FFA) +#else +# define machine_is_msm8x55_svlte_ffa() (0) +#endif + +#ifdef CONFIG_MACH_MSM8X55_SVLTE_SURF +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MSM8X55_SVLTE_SURF +# endif +# define machine_is_msm8x55_svlte_surf() (machine_arch_type == MACH_TYPE_MSM8X55_SVLTE_SURF) +#else +# define machine_is_msm8x55_svlte_surf() (0) +#endif + +#ifdef CONFIG_MACH_QUICKSTEP +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_QUICKSTEP +# endif +# define machine_is_quickstep() (machine_arch_type == MACH_TYPE_QUICKSTEP) +#else +# define machine_is_quickstep() (0) +#endif + +#ifdef CONFIG_MACH_DMW96 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DMW96 +# endif +# define machine_is_dmw96() (machine_arch_type == MACH_TYPE_DMW96) +#else +# define machine_is_dmw96() (0) +#endif + +#ifdef CONFIG_MACH_HAMMERHEAD +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HAMMERHEAD +# endif +# define machine_is_hammerhead() (machine_arch_type == MACH_TYPE_HAMMERHEAD) +#else +# define machine_is_hammerhead() (0) +#endif + +#ifdef CONFIG_MACH_TRIDENT +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TRIDENT +# endif +# define machine_is_trident() (machine_arch_type == MACH_TYPE_TRIDENT) +#else +# define machine_is_trident() (0) +#endif + +#ifdef CONFIG_MACH_LIGHTNING +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LIGHTNING +# endif +# define machine_is_lightning() (machine_arch_type == MACH_TYPE_LIGHTNING) +#else +# define machine_is_lightning() (0) +#endif + +#ifdef CONFIG_MACH_ICONNECT +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ICONNECT +# endif +# define machine_is_iconnect() (machine_arch_type == MACH_TYPE_ICONNECT) +#else +# define machine_is_iconnect() (0) +#endif + +#ifdef CONFIG_MACH_AUTOBOT +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AUTOBOT +# endif +# define machine_is_autobot() (machine_arch_type == MACH_TYPE_AUTOBOT) +#else +# define machine_is_autobot() (0) +#endif + +#ifdef CONFIG_MACH_COCONUT +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_COCONUT +# endif +# define machine_is_coconut() (machine_arch_type == MACH_TYPE_COCONUT) +#else +# define machine_is_coconut() (0) +#endif + +#ifdef CONFIG_MACH_DURIAN +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DURIAN +# endif +# define machine_is_durian() (machine_arch_type == MACH_TYPE_DURIAN) +#else +# define machine_is_durian() (0) +#endif + +#ifdef CONFIG_MACH_CAYENNE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CAYENNE +# endif +# define machine_is_cayenne() (machine_arch_type == MACH_TYPE_CAYENNE) +#else +# define machine_is_cayenne() (0) +#endif + +#ifdef CONFIG_MACH_FUJI +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_FUJI +# endif +# define machine_is_fuji() (machine_arch_type == MACH_TYPE_FUJI) +#else +# define machine_is_fuji() (0) +#endif + +#ifdef CONFIG_MACH_SYNOLOGY_6282 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SYNOLOGY_6282 +# endif +# define machine_is_synology_6282() (machine_arch_type == MACH_TYPE_SYNOLOGY_6282) +#else +# define machine_is_synology_6282() (0) +#endif + +#ifdef CONFIG_MACH_EM1SY +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EM1SY +# endif +# define machine_is_em1sy() (machine_arch_type == MACH_TYPE_EM1SY) +#else +# define machine_is_em1sy() (0) +#endif + +#ifdef CONFIG_MACH_M502 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_M502 +# endif +# define machine_is_m502() (machine_arch_type == MACH_TYPE_M502) +#else +# define machine_is_m502() (0) +#endif + +#ifdef CONFIG_MACH_MATRIX518 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MATRIX518 +# endif +# define machine_is_matrix518() (machine_arch_type == MACH_TYPE_MATRIX518) +#else +# define machine_is_matrix518() (0) +#endif + +#ifdef CONFIG_MACH_TINY_GURNARD +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TINY_GURNARD +# endif +# define machine_is_tiny_gurnard() (machine_arch_type == MACH_TYPE_TINY_GURNARD) +#else +# define machine_is_tiny_gurnard() (0) +#endif + +#ifdef CONFIG_MACH_SPEAR1310 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SPEAR1310 +# endif +# define machine_is_spear1310() (machine_arch_type == MACH_TYPE_SPEAR1310) +#else +# define machine_is_spear1310() (0) +#endif + +#ifdef CONFIG_MACH_BV07 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BV07 +# endif +# define machine_is_bv07() (machine_arch_type == MACH_TYPE_BV07) +#else +# define machine_is_bv07() (0) +#endif + +#ifdef CONFIG_MACH_MXT_TD61 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MXT_TD61 +# endif +# define machine_is_mxt_td61() (machine_arch_type == MACH_TYPE_MXT_TD61) +#else +# define machine_is_mxt_td61() (0) +#endif + +#ifdef CONFIG_MACH_OPENRD_ULTIMATE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OPENRD_ULTIMATE +# endif +# define machine_is_openrd_ultimate() (machine_arch_type == MACH_TYPE_OPENRD_ULTIMATE) +#else +# define machine_is_openrd_ultimate() (0) +#endif + +#ifdef CONFIG_MACH_DEVIXP +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DEVIXP +# endif +# define machine_is_devixp() (machine_arch_type == MACH_TYPE_DEVIXP) +#else +# define machine_is_devixp() (0) +#endif + +#ifdef CONFIG_MACH_MICCPT +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MICCPT +# endif +# define machine_is_miccpt() (machine_arch_type == MACH_TYPE_MICCPT) +#else +# define machine_is_miccpt() (0) +#endif + +#ifdef CONFIG_MACH_MIC256 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MIC256 +# endif +# define machine_is_mic256() (machine_arch_type == MACH_TYPE_MIC256) +#else +# define machine_is_mic256() (0) +#endif + +#ifdef CONFIG_MACH_AS1167 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AS1167 +# endif +# define machine_is_as1167() (machine_arch_type == MACH_TYPE_AS1167) +#else +# define machine_is_as1167() (0) +#endif + +#ifdef CONFIG_MACH_OMAP3_IBIZA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAP3_IBIZA +# endif +# define machine_is_omap3_ibiza() (machine_arch_type == MACH_TYPE_OMAP3_IBIZA) +#else +# define machine_is_omap3_ibiza() (0) +#endif + +#ifdef CONFIG_MACH_U5500 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_U5500 +# endif +# define machine_is_u5500() (machine_arch_type == MACH_TYPE_U5500) +#else +# define machine_is_u5500() (0) +#endif + +#ifdef CONFIG_MACH_DAVINCI_PICTO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DAVINCI_PICTO +# endif +# define machine_is_davinci_picto() (machine_arch_type == MACH_TYPE_DAVINCI_PICTO) +#else +# define machine_is_davinci_picto() (0) +#endif + +#ifdef CONFIG_MACH_MECHA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MECHA +# endif +# define machine_is_mecha() (machine_arch_type == MACH_TYPE_MECHA) +#else +# define machine_is_mecha() (0) +#endif + +#ifdef CONFIG_MACH_BUBBA3 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BUBBA3 +# endif +# define machine_is_bubba3() (machine_arch_type == MACH_TYPE_BUBBA3) +#else +# define machine_is_bubba3() (0) +#endif + +#ifdef CONFIG_MACH_PUPITRE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PUPITRE +# endif +# define machine_is_pupitre() (machine_arch_type == MACH_TYPE_PUPITRE) +#else +# define machine_is_pupitre() (0) +#endif + +#ifdef CONFIG_MACH_TEGRA_HARMONY +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TEGRA_HARMONY +# endif +# define machine_is_tegra_harmony() (machine_arch_type == MACH_TYPE_TEGRA_HARMONY) +#else +# define machine_is_tegra_harmony() (0) +#endif + +#ifdef CONFIG_MACH_TEGRA_VOGUE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TEGRA_VOGUE +# endif +# define machine_is_tegra_vogue() (machine_arch_type == MACH_TYPE_TEGRA_VOGUE) +#else +# define machine_is_tegra_vogue() (0) +#endif + +#ifdef CONFIG_MACH_TEGRA_E1165 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TEGRA_E1165 +# endif +# define machine_is_tegra_e1165() (machine_arch_type == MACH_TYPE_TEGRA_E1165) +#else +# define machine_is_tegra_e1165() (0) +#endif + +#ifdef CONFIG_MACH_SIMPLENET +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SIMPLENET +# endif +# define machine_is_simplenet() (machine_arch_type == MACH_TYPE_SIMPLENET) +#else +# define machine_is_simplenet() (0) +#endif + +#ifdef CONFIG_MACH_EC4350TBM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EC4350TBM +# endif +# define machine_is_ec4350tbm() (machine_arch_type == MACH_TYPE_EC4350TBM) +#else +# define machine_is_ec4350tbm() (0) +#endif + +#ifdef CONFIG_MACH_PEC_TC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PEC_TC +# endif +# define machine_is_pec_tc() (machine_arch_type == MACH_TYPE_PEC_TC) +#else +# define machine_is_pec_tc() (0) +#endif + +#ifdef CONFIG_MACH_PEC_HC2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PEC_HC2 +# endif +# define machine_is_pec_hc2() (machine_arch_type == MACH_TYPE_PEC_HC2) +#else +# define machine_is_pec_hc2() (0) +#endif + +#ifdef CONFIG_MACH_ESL_MOBILIS_A +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ESL_MOBILIS_A +# endif +# define machine_is_esl_mobilis_a() (machine_arch_type == MACH_TYPE_ESL_MOBILIS_A) +#else +# define machine_is_esl_mobilis_a() (0) +#endif + +#ifdef CONFIG_MACH_ESL_MOBILIS_B +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ESL_MOBILIS_B +# endif +# define machine_is_esl_mobilis_b() (machine_arch_type == MACH_TYPE_ESL_MOBILIS_B) +#else +# define machine_is_esl_mobilis_b() (0) +#endif + +#ifdef CONFIG_MACH_ESL_WAVE_A +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ESL_WAVE_A +# endif +# define machine_is_esl_wave_a() (machine_arch_type == MACH_TYPE_ESL_WAVE_A) +#else +# define machine_is_esl_wave_a() (0) +#endif + +#ifdef CONFIG_MACH_ESL_WAVE_B +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ESL_WAVE_B +# endif +# define machine_is_esl_wave_b() (machine_arch_type == MACH_TYPE_ESL_WAVE_B) +#else +# define machine_is_esl_wave_b() (0) +#endif + +#ifdef CONFIG_MACH_UNISENSE_MMM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_UNISENSE_MMM +# endif +# define machine_is_unisense_mmm() (machine_arch_type == MACH_TYPE_UNISENSE_MMM) +#else +# define machine_is_unisense_mmm() (0) +#endif + +#ifdef CONFIG_MACH_BLUESHARK +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BLUESHARK +# endif +# define machine_is_blueshark() (machine_arch_type == MACH_TYPE_BLUESHARK) +#else +# define machine_is_blueshark() (0) +#endif + +#ifdef CONFIG_MACH_E10 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_E10 +# endif +# define machine_is_e10() (machine_arch_type == MACH_TYPE_E10) +#else +# define machine_is_e10() (0) +#endif + +#ifdef CONFIG_MACH_APP3K_ROBIN +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_APP3K_ROBIN +# endif +# define machine_is_app3k_robin() (machine_arch_type == MACH_TYPE_APP3K_ROBIN) +#else +# define machine_is_app3k_robin() (0) +#endif + +#ifdef CONFIG_MACH_POV15HD +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_POV15HD +# endif +# define machine_is_pov15hd() (machine_arch_type == MACH_TYPE_POV15HD) +#else +# define machine_is_pov15hd() (0) +#endif + +#ifdef CONFIG_MACH_STELLA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_STELLA +# endif +# define machine_is_stella() (machine_arch_type == MACH_TYPE_STELLA) +#else +# define machine_is_stella() (0) +#endif + +#ifdef CONFIG_MACH_MACH_HTC_IOLITE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MACH_HTC_IOLITE +# endif +# define machine_is_htc_iolite() (machine_arch_type == MACH_TYPE_MACH_HTC_IOLITE) +#else +# define machine_is_htc_iolite() (0) +#endif + +#ifdef CONFIG_MACH_LINKSTATION_LSCHL +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LINKSTATION_LSCHL +# endif +# define machine_is_linkstation_lschl() (machine_arch_type == MACH_TYPE_LINKSTATION_LSCHL) +#else +# define machine_is_linkstation_lschl() (0) +#endif + +#ifdef CONFIG_MACH_NETWALKER +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NETWALKER +# endif +# define machine_is_netwalker() (machine_arch_type == MACH_TYPE_NETWALKER) +#else +# define machine_is_netwalker() (0) +#endif + +#ifdef CONFIG_MACH_ACSX106 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ACSX106 +# endif +# define machine_is_acsx106() (machine_arch_type == MACH_TYPE_ACSX106) +#else +# define machine_is_acsx106() (0) +#endif + +#ifdef CONFIG_MACH_ATLAS5_C1 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ATLAS5_C1 +# endif +# define machine_is_atlas5_c1() (machine_arch_type == MACH_TYPE_ATLAS5_C1) +#else +# define machine_is_atlas5_c1() (0) +#endif + +#ifdef CONFIG_MACH_NSB3AST +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NSB3AST +# endif +# define machine_is_nsb3ast() (machine_arch_type == MACH_TYPE_NSB3AST) +#else +# define machine_is_nsb3ast() (0) +#endif + +#ifdef CONFIG_MACH_GNET_SLC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_GNET_SLC +# endif +# define machine_is_gnet_slc() (machine_arch_type == MACH_TYPE_GNET_SLC) +#else +# define machine_is_gnet_slc() (0) +#endif + +#ifdef CONFIG_MACH_AF4000 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AF4000 +# endif +# define machine_is_af4000() (machine_arch_type == MACH_TYPE_AF4000) +#else +# define machine_is_af4000() (0) +#endif + +#ifdef CONFIG_MACH_ARK9431 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ARK9431 +# endif +# define machine_is_ark9431() (machine_arch_type == MACH_TYPE_ARK9431) +#else +# define machine_is_ark9431() (0) +#endif + +#ifdef CONFIG_MACH_FS_S5PC100 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_FS_S5PC100 +# endif +# define machine_is_fs_s5pc100() (machine_arch_type == MACH_TYPE_FS_S5PC100) +#else +# define machine_is_fs_s5pc100() (0) +#endif + +#ifdef CONFIG_MACH_OMAP3505NOVA8 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAP3505NOVA8 +# endif +# define machine_is_omap3505nova8() (machine_arch_type == MACH_TYPE_OMAP3505NOVA8) +#else +# define machine_is_omap3505nova8() (0) +#endif + +#ifdef CONFIG_MACH_OMAP3621_EDP1 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAP3621_EDP1 +# endif +# define machine_is_omap3621_edp1() (machine_arch_type == MACH_TYPE_OMAP3621_EDP1) +#else +# define machine_is_omap3621_edp1() (0) +#endif + +#ifdef CONFIG_MACH_ORATISAES +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ORATISAES +# endif +# define machine_is_oratisaes() (machine_arch_type == MACH_TYPE_ORATISAES) +#else +# define machine_is_oratisaes() (0) +#endif + +#ifdef CONFIG_MACH_SMDKV310 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SMDKV310 +# endif +# define machine_is_smdkv310() (machine_arch_type == MACH_TYPE_SMDKV310) +#else +# define machine_is_smdkv310() (0) +#endif + +#ifdef CONFIG_MACH_SIEMENS_L0 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SIEMENS_L0 +# endif +# define machine_is_siemens_l0() (machine_arch_type == MACH_TYPE_SIEMENS_L0) +#else +# define machine_is_siemens_l0() (0) +#endif + +#ifdef CONFIG_MACH_VENTANA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_VENTANA +# endif +# define machine_is_ventana() (machine_arch_type == MACH_TYPE_VENTANA) +#else +# define machine_is_ventana() (0) +#endif + +#ifdef CONFIG_MACH_WM8505_7IN_NETBOOK +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_WM8505_7IN_NETBOOK +# endif +# define machine_is_wm8505_7in_netbook() (machine_arch_type == MACH_TYPE_WM8505_7IN_NETBOOK) +#else +# define machine_is_wm8505_7in_netbook() (0) +#endif + +#ifdef CONFIG_MACH_EC4350SDB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EC4350SDB +# endif +# define machine_is_ec4350sdb() (machine_arch_type == MACH_TYPE_EC4350SDB) +#else +# define machine_is_ec4350sdb() (0) +#endif + +#ifdef CONFIG_MACH_MIMAS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MIMAS +# endif +# define machine_is_mimas() (machine_arch_type == MACH_TYPE_MIMAS) +#else +# define machine_is_mimas() (0) +#endif + +#ifdef CONFIG_MACH_TITAN +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TITAN +# endif +# define machine_is_titan() (machine_arch_type == MACH_TYPE_TITAN) +#else +# define machine_is_titan() (0) +#endif + +#ifdef CONFIG_MACH_CRANEBOARD +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CRANEBOARD +# endif +# define machine_is_craneboard() (machine_arch_type == MACH_TYPE_CRANEBOARD) +#else +# define machine_is_craneboard() (0) +#endif + +#ifdef CONFIG_MACH_ES2440 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ES2440 +# endif +# define machine_is_es2440() (machine_arch_type == MACH_TYPE_ES2440) +#else +# define machine_is_es2440() (0) +#endif + +#ifdef CONFIG_MACH_NAJAY_A9263 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NAJAY_A9263 +# endif +# define machine_is_najay_a9263() (machine_arch_type == MACH_TYPE_NAJAY_A9263) +#else +# define machine_is_najay_a9263() (0) +#endif + +#ifdef CONFIG_MACH_HTCTORNADO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HTCTORNADO +# endif +# define machine_is_htctornado() (machine_arch_type == MACH_TYPE_HTCTORNADO) +#else +# define machine_is_htctornado() (0) +#endif + +#ifdef CONFIG_MACH_DIMM_MX257 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DIMM_MX257 +# endif +# define machine_is_dimm_mx257() (machine_arch_type == MACH_TYPE_DIMM_MX257) +#else +# define machine_is_dimm_mx257() (0) +#endif + +#ifdef CONFIG_MACH_JIGEN +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_JIGEN +# endif +# define machine_is_jigen301() (machine_arch_type == MACH_TYPE_JIGEN) +#else +# define machine_is_jigen301() (0) +#endif + +#ifdef CONFIG_MACH_SMDK6450 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SMDK6450 +# endif +# define machine_is_smdk6450() (machine_arch_type == MACH_TYPE_SMDK6450) +#else +# define machine_is_smdk6450() (0) +#endif + +#ifdef CONFIG_MACH_MENO_QNG +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MENO_QNG +# endif +# define machine_is_meno_qng() (machine_arch_type == MACH_TYPE_MENO_QNG) +#else +# define machine_is_meno_qng() (0) +#endif + +#ifdef CONFIG_MACH_NS2416 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NS2416 +# endif +# define machine_is_ns2416() (machine_arch_type == MACH_TYPE_NS2416) +#else +# define machine_is_ns2416() (0) +#endif + +#ifdef CONFIG_MACH_RPC353 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_RPC353 +# endif +# define machine_is_rpc353() (machine_arch_type == MACH_TYPE_RPC353) +#else +# define machine_is_rpc353() (0) +#endif + +#ifdef CONFIG_MACH_TQ6410 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TQ6410 +# endif +# define machine_is_tq6410() (machine_arch_type == MACH_TYPE_TQ6410) +#else +# define machine_is_tq6410() (0) +#endif + +#ifdef CONFIG_MACH_SKY6410 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SKY6410 +# endif +# define machine_is_sky6410() (machine_arch_type == MACH_TYPE_SKY6410) +#else +# define machine_is_sky6410() (0) +#endif + +#ifdef CONFIG_MACH_DYNASTY +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DYNASTY +# endif +# define machine_is_dynasty() (machine_arch_type == MACH_TYPE_DYNASTY) +#else +# define machine_is_dynasty() (0) +#endif + +#ifdef CONFIG_MACH_VIVO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_VIVO +# endif +# define machine_is_vivo() (machine_arch_type == MACH_TYPE_VIVO) +#else +# define machine_is_vivo() (0) +#endif + +#ifdef CONFIG_MACH_BURY_BL7582 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BURY_BL7582 +# endif +# define machine_is_bury_bl7582() (machine_arch_type == MACH_TYPE_BURY_BL7582) +#else +# define machine_is_bury_bl7582() (0) +#endif + +#ifdef CONFIG_MACH_BURY_BPS5270 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BURY_BPS5270 +# endif +# define machine_is_bury_bps5270() (machine_arch_type == MACH_TYPE_BURY_BPS5270) +#else +# define machine_is_bury_bps5270() (0) +#endif + +#ifdef CONFIG_MACH_BASI +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BASI +# endif +# define machine_is_basi() (machine_arch_type == MACH_TYPE_BASI) +#else +# define machine_is_basi() (0) +#endif + +#ifdef CONFIG_MACH_TN200 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TN200 +# endif +# define machine_is_tn200() (machine_arch_type == MACH_TYPE_TN200) +#else +# define machine_is_tn200() (0) +#endif + +#ifdef CONFIG_MACH_C2MMI +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_C2MMI +# endif +# define machine_is_c2mmi() (machine_arch_type == MACH_TYPE_C2MMI) +#else +# define machine_is_c2mmi() (0) +#endif + +#ifdef CONFIG_MACH_MESON_6236M +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MESON_6236M +# endif +# define machine_is_meson_6236m() (machine_arch_type == MACH_TYPE_MESON_6236M) +#else +# define machine_is_meson_6236m() (0) +#endif + +#ifdef CONFIG_MACH_MESON_8626M +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MESON_8626M +# endif +# define machine_is_meson_8626m() (machine_arch_type == MACH_TYPE_MESON_8626M) +#else +# define machine_is_meson_8626m() (0) +#endif + +#ifdef CONFIG_MACH_TUBE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TUBE +# endif +# define machine_is_tube() (machine_arch_type == MACH_TYPE_TUBE) +#else +# define machine_is_tube() (0) +#endif + +#ifdef CONFIG_MACH_MESSINA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MESSINA +# endif +# define machine_is_messina() (machine_arch_type == MACH_TYPE_MESSINA) +#else +# define machine_is_messina() (0) +#endif + +#ifdef CONFIG_MACH_MX50_ARM2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MX50_ARM2 +# endif +# define machine_is_mx50_arm2() (machine_arch_type == MACH_TYPE_MX50_ARM2) +#else +# define machine_is_mx50_arm2() (0) +#endif + +#ifdef CONFIG_MACH_CETUS9263 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CETUS9263 +# endif +# define machine_is_cetus9263() (machine_arch_type == MACH_TYPE_CETUS9263) +#else +# define machine_is_cetus9263() (0) +#endif + +#ifdef CONFIG_MACH_BROWNSTONE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BROWNSTONE +# endif +# define machine_is_brownstone() (machine_arch_type == MACH_TYPE_BROWNSTONE) +#else +# define machine_is_brownstone() (0) +#endif + +#ifdef CONFIG_MACH_VMX25 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_VMX25 +# endif +# define machine_is_vmx25() (machine_arch_type == MACH_TYPE_VMX25) +#else +# define machine_is_vmx25() (0) +#endif + +#ifdef CONFIG_MACH_VMX51 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_VMX51 +# endif +# define machine_is_vmx51() (machine_arch_type == MACH_TYPE_VMX51) +#else +# define machine_is_vmx51() (0) +#endif + +#ifdef CONFIG_MACH_ABACUS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ABACUS +# endif +# define machine_is_abacus() (machine_arch_type == MACH_TYPE_ABACUS) +#else +# define machine_is_abacus() (0) +#endif + +#ifdef CONFIG_MACH_CM4745 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CM4745 +# endif +# define machine_is_cm4745() (machine_arch_type == MACH_TYPE_CM4745) +#else +# define machine_is_cm4745() (0) +#endif + +#ifdef CONFIG_MACH_ORATISLINK +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ORATISLINK +# endif +# define machine_is_oratislink() (machine_arch_type == MACH_TYPE_ORATISLINK) +#else +# define machine_is_oratislink() (0) +#endif + +#ifdef CONFIG_MACH_DAVINCI_DM365_DVR +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DAVINCI_DM365_DVR +# endif +# define machine_is_davinci_dm365_dvr() (machine_arch_type == MACH_TYPE_DAVINCI_DM365_DVR) +#else +# define machine_is_davinci_dm365_dvr() (0) +#endif + +#ifdef CONFIG_MACH_NETVIZ +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NETVIZ +# endif +# define machine_is_netviz() (machine_arch_type == MACH_TYPE_NETVIZ) +#else +# define machine_is_netviz() (0) +#endif + +#ifdef CONFIG_MACH_FLEXIBITY +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_FLEXIBITY +# endif +# define machine_is_flexibity() (machine_arch_type == MACH_TYPE_FLEXIBITY) +#else +# define machine_is_flexibity() (0) +#endif + +#ifdef CONFIG_MACH_WLAN_COMPUTER +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_WLAN_COMPUTER +# endif +# define machine_is_wlan_computer() (machine_arch_type == MACH_TYPE_WLAN_COMPUTER) +#else +# define machine_is_wlan_computer() (0) +#endif + +#ifdef CONFIG_MACH_LPC24XX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LPC24XX +# endif +# define machine_is_lpc24xx() (machine_arch_type == MACH_TYPE_LPC24XX) +#else +# define machine_is_lpc24xx() (0) +#endif + +#ifdef CONFIG_MACH_SPICA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SPICA +# endif +# define machine_is_spica() (machine_arch_type == MACH_TYPE_SPICA) +#else +# define machine_is_spica() (0) +#endif + +#ifdef CONFIG_MACH_GPSDISPLAY +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_GPSDISPLAY +# endif +# define machine_is_gpsdisplay() (machine_arch_type == MACH_TYPE_GPSDISPLAY) +#else +# define machine_is_gpsdisplay() (0) +#endif + +#ifdef CONFIG_MACH_BIPNET +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BIPNET +# endif +# define machine_is_bipnet() (machine_arch_type == MACH_TYPE_BIPNET) +#else +# define machine_is_bipnet() (0) +#endif + +#ifdef CONFIG_MACH_OVERO_CTU_INERTIAL +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OVERO_CTU_INERTIAL +# endif +# define machine_is_overo_ctu_inertial() (machine_arch_type == MACH_TYPE_OVERO_CTU_INERTIAL) +#else +# define machine_is_overo_ctu_inertial() (0) +#endif + +#ifdef CONFIG_MACH_DAVINCI_DM355_MMM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DAVINCI_DM355_MMM +# endif +# define machine_is_davinci_dm355_mmm() (machine_arch_type == MACH_TYPE_DAVINCI_DM355_MMM) +#else +# define machine_is_davinci_dm355_mmm() (0) +#endif + +#ifdef CONFIG_MACH_PC9260_V2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PC9260_V2 +# endif +# define machine_is_pc9260_v2() (machine_arch_type == MACH_TYPE_PC9260_V2) +#else +# define machine_is_pc9260_v2() (0) +#endif + +#ifdef CONFIG_MACH_PTX7545 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PTX7545 +# endif +# define machine_is_ptx7545() (machine_arch_type == MACH_TYPE_PTX7545) +#else +# define machine_is_ptx7545() (0) +#endif + +#ifdef CONFIG_MACH_TM_EFDC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TM_EFDC +# endif +# define machine_is_tm_efdc() (machine_arch_type == MACH_TYPE_TM_EFDC) +#else +# define machine_is_tm_efdc() (0) +#endif + +#ifdef CONFIG_MACH_WALDO1 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_WALDO1 +# endif +# define machine_is_remove_me() (machine_arch_type == MACH_TYPE_WALDO1) +#else +# define machine_is_remove_me() (0) +#endif + +#ifdef CONFIG_MACH_OMAP3_WALDO1 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAP3_WALDO1 +# endif +# define machine_is_omap3_waldo1() (machine_arch_type == MACH_TYPE_OMAP3_WALDO1) +#else +# define machine_is_omap3_waldo1() (0) +#endif + +#ifdef CONFIG_MACH_FLYER +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_FLYER +# endif +# define machine_is_flyer() (machine_arch_type == MACH_TYPE_FLYER) +#else +# define machine_is_flyer() (0) +#endif + +#ifdef CONFIG_MACH_TORNADO3240 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TORNADO3240 +# endif +# define machine_is_tornado3240() (machine_arch_type == MACH_TYPE_TORNADO3240) +#else +# define machine_is_tornado3240() (0) +#endif + +#ifdef CONFIG_MACH_SOLI_01 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SOLI_01 +# endif +# define machine_is_soli_01() (machine_arch_type == MACH_TYPE_SOLI_01) +#else +# define machine_is_soli_01() (0) +#endif + +#ifdef CONFIG_MACH_OMAPL138_EUROPALC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAPL138_EUROPALC +# endif +# define machine_is_omapl138_europalc() (machine_arch_type == MACH_TYPE_OMAPL138_EUROPALC) +#else +# define machine_is_omapl138_europalc() (0) +#endif + +#ifdef CONFIG_MACH_HELIOS_V1 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HELIOS_V1 +# endif +# define machine_is_helios_v1() (machine_arch_type == MACH_TYPE_HELIOS_V1) +#else +# define machine_is_helios_v1() (0) +#endif + +#ifdef CONFIG_MACH_NETSPACE_LITE_V2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NETSPACE_LITE_V2 +# endif +# define machine_is_netspace_lite_v2() (machine_arch_type == MACH_TYPE_NETSPACE_LITE_V2) +#else +# define machine_is_netspace_lite_v2() (0) +#endif + +#ifdef CONFIG_MACH_SSC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SSC +# endif +# define machine_is_ssc() (machine_arch_type == MACH_TYPE_SSC) +#else +# define machine_is_ssc() (0) +#endif + +#ifdef CONFIG_MACH_PREMIERWAVE_EN +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PREMIERWAVE_EN +# endif +# define machine_is_premierwave_en() (machine_arch_type == MACH_TYPE_PREMIERWAVE_EN) +#else +# define machine_is_premierwave_en() (0) +#endif + +#ifdef CONFIG_MACH_WASABI +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_WASABI +# endif +# define machine_is_wasabi() (machine_arch_type == MACH_TYPE_WASABI) +#else +# define machine_is_wasabi() (0) +#endif + +#ifdef CONFIG_MACH_VIVOW +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_VIVOW +# endif +# define machine_is_vivo_w() (machine_arch_type == MACH_TYPE_VIVOW) +#else +# define machine_is_vivo_w() (0) +#endif + +#ifdef CONFIG_MACH_MX50_RDP +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MX50_RDP +# endif +# define machine_is_mx50_rdp() (machine_arch_type == MACH_TYPE_MX50_RDP) +#else +# define machine_is_mx50_rdp() (0) +#endif + +#ifdef CONFIG_MACH_UNIVERSAL +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_UNIVERSAL +# endif +# define machine_is_universal() (machine_arch_type == MACH_TYPE_UNIVERSAL) +#else +# define machine_is_universal() (0) +#endif + +#ifdef CONFIG_MACH_REAL6410 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_REAL6410 +# endif +# define machine_is_real6410() (machine_arch_type == MACH_TYPE_REAL6410) +#else +# define machine_is_real6410() (0) +#endif + +#ifdef CONFIG_MACH_SPX_SAKURA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SPX_SAKURA +# endif +# define machine_is_spx_sakura() (machine_arch_type == MACH_TYPE_SPX_SAKURA) +#else +# define machine_is_spx_sakura() (0) +#endif + +#ifdef CONFIG_MACH_IJ3K_2440 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IJ3K_2440 +# endif +# define machine_is_ij3k_2440() (machine_arch_type == MACH_TYPE_IJ3K_2440) +#else +# define machine_is_ij3k_2440() (0) +#endif + +#ifdef CONFIG_MACH_OMAP3_BC10 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAP3_BC10 +# endif +# define machine_is_omap3_bc10() (machine_arch_type == MACH_TYPE_OMAP3_BC10) +#else +# define machine_is_omap3_bc10() (0) +#endif + +#ifdef CONFIG_MACH_THEBE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_THEBE +# endif +# define machine_is_thebe() (machine_arch_type == MACH_TYPE_THEBE) +#else +# define machine_is_thebe() (0) +#endif + +#ifdef CONFIG_MACH_RV082 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_RV082 +# endif +# define machine_is_rv082() (machine_arch_type == MACH_TYPE_RV082) +#else +# define machine_is_rv082() (0) +#endif + +#ifdef CONFIG_MACH_ARMLGUEST +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ARMLGUEST +# endif +# define machine_is_armlguest() (machine_arch_type == MACH_TYPE_ARMLGUEST) +#else +# define machine_is_armlguest() (0) +#endif + +#ifdef CONFIG_MACH_TJINC1000 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TJINC1000 +# endif +# define machine_is_tjinc1000() (machine_arch_type == MACH_TYPE_TJINC1000) +#else +# define machine_is_tjinc1000() (0) +#endif + +#ifdef CONFIG_MACH_DOCKSTAR +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DOCKSTAR +# endif +# define machine_is_dockstar() (machine_arch_type == MACH_TYPE_DOCKSTAR) +#else +# define machine_is_dockstar() (0) +#endif + +#ifdef CONFIG_MACH_AX8008 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AX8008 +# endif +# define machine_is_ax8008() (machine_arch_type == MACH_TYPE_AX8008) +#else +# define machine_is_ax8008() (0) +#endif + +#ifdef CONFIG_MACH_GNET_SGCE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_GNET_SGCE +# endif +# define machine_is_gnet_sgce() (machine_arch_type == MACH_TYPE_GNET_SGCE) +#else +# define machine_is_gnet_sgce() (0) +#endif + +#ifdef CONFIG_MACH_PXWNAS_500_1000 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PXWNAS_500_1000 +# endif +# define machine_is_pxwnas_500_1000() (machine_arch_type == MACH_TYPE_PXWNAS_500_1000) +#else +# define machine_is_pxwnas_500_1000() (0) +#endif + +#ifdef CONFIG_MACH_EA20 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EA20 +# endif +# define machine_is_ea20() (machine_arch_type == MACH_TYPE_EA20) +#else +# define machine_is_ea20() (0) +#endif + +#ifdef CONFIG_MACH_AWM2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AWM2 +# endif +# define machine_is_awm2() (machine_arch_type == MACH_TYPE_AWM2) +#else +# define machine_is_awm2() (0) +#endif + +#ifdef CONFIG_MACH_TI8148EVM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TI8148EVM +# endif +# define machine_is_ti8148evm() (machine_arch_type == MACH_TYPE_TI8148EVM) +#else +# define machine_is_ti8148evm() (0) +#endif + +#ifdef CONFIG_MACH_TEGRA_SEABOARD +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TEGRA_SEABOARD +# endif +# define machine_is_tegra_seaboard() (machine_arch_type == MACH_TYPE_TEGRA_SEABOARD) +#else +# define machine_is_tegra_seaboard() (0) +#endif + +#ifdef CONFIG_MACH_LINKSTATION_CHLV2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LINKSTATION_CHLV2 +# endif +# define machine_is_linkstation_chlv2() (machine_arch_type == MACH_TYPE_LINKSTATION_CHLV2) +#else +# define machine_is_linkstation_chlv2() (0) +#endif + +#ifdef CONFIG_MACH_TERA_PRO2_RACK +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TERA_PRO2_RACK +# endif +# define machine_is_tera_pro2_rack() (machine_arch_type == MACH_TYPE_TERA_PRO2_RACK) +#else +# define machine_is_tera_pro2_rack() (0) +#endif + +#ifdef CONFIG_MACH_RUBYS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_RUBYS +# endif +# define machine_is_rubys() (machine_arch_type == MACH_TYPE_RUBYS) +#else +# define machine_is_rubys() (0) +#endif + +#ifdef CONFIG_MACH_AQUARIUS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AQUARIUS +# endif +# define machine_is_aquarius() (machine_arch_type == MACH_TYPE_AQUARIUS) +#else +# define machine_is_aquarius() (0) +#endif + +#ifdef CONFIG_MACH_MX53_ARD +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MX53_ARD +# endif +# define machine_is_mx53_ard() (machine_arch_type == MACH_TYPE_MX53_ARD) +#else +# define machine_is_mx53_ard() (0) +#endif + +#ifdef CONFIG_MACH_MX53_SMD +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MX53_SMD +# endif +# define machine_is_mx53_smd() (machine_arch_type == MACH_TYPE_MX53_SMD) +#else +# define machine_is_mx53_smd() (0) +#endif + +#ifdef CONFIG_MACH_LSWXL +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LSWXL +# endif +# define machine_is_lswxl() (machine_arch_type == MACH_TYPE_LSWXL) +#else +# define machine_is_lswxl() (0) +#endif + +#ifdef CONFIG_MACH_DOVE_AVNG_V3 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DOVE_AVNG_V3 +# endif +# define machine_is_dove_avng_v3() (machine_arch_type == MACH_TYPE_DOVE_AVNG_V3) +#else +# define machine_is_dove_avng_v3() (0) +#endif + +#ifdef CONFIG_MACH_SDI_ESS_9263 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SDI_ESS_9263 +# endif +# define machine_is_sdi_ess_9263() (machine_arch_type == MACH_TYPE_SDI_ESS_9263) +#else +# define machine_is_sdi_ess_9263() (0) +#endif + +#ifdef CONFIG_MACH_JOCPU550 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_JOCPU550 +# endif +# define machine_is_jocpu550() (machine_arch_type == MACH_TYPE_JOCPU550) +#else +# define machine_is_jocpu550() (0) +#endif + +#ifdef CONFIG_MACH_MSM8X60_RUMI3 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MSM8X60_RUMI3 +# endif +# define machine_is_msm8x60_rumi3() (machine_arch_type == MACH_TYPE_MSM8X60_RUMI3) +#else +# define machine_is_msm8x60_rumi3() (0) +#endif + +#ifdef CONFIG_MACH_MSM8X60_FFA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MSM8X60_FFA +# endif +# define machine_is_msm8x60_ffa() (machine_arch_type == MACH_TYPE_MSM8X60_FFA) +#else +# define machine_is_msm8x60_ffa() (0) +#endif + +#ifdef CONFIG_MACH_YANOMAMI +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_YANOMAMI +# endif +# define machine_is_yanomami() (machine_arch_type == MACH_TYPE_YANOMAMI) +#else +# define machine_is_yanomami() (0) +#endif + +#ifdef CONFIG_MACH_GTA04 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_GTA04 +# endif +# define machine_is_gta04() (machine_arch_type == MACH_TYPE_GTA04) +#else +# define machine_is_gta04() (0) +#endif + +#ifdef CONFIG_MACH_CM_A510 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CM_A510 +# endif +# define machine_is_cm_a510() (machine_arch_type == MACH_TYPE_CM_A510) +#else +# define machine_is_cm_a510() (0) +#endif + +#ifdef CONFIG_MACH_OMAP3_RFS200 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAP3_RFS200 +# endif +# define machine_is_omap3_rfs200() (machine_arch_type == MACH_TYPE_OMAP3_RFS200) +#else +# define machine_is_omap3_rfs200() (0) +#endif + +#ifdef CONFIG_MACH_KX33XX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_KX33XX +# endif +# define machine_is_kx33xx() (machine_arch_type == MACH_TYPE_KX33XX) +#else +# define machine_is_kx33xx() (0) +#endif + +#ifdef CONFIG_MACH_PTX7510 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PTX7510 +# endif +# define machine_is_ptx7510() (machine_arch_type == MACH_TYPE_PTX7510) +#else +# define machine_is_ptx7510() (0) +#endif + +#ifdef CONFIG_MACH_TOP9000 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TOP9000 +# endif +# define machine_is_top9000() (machine_arch_type == MACH_TYPE_TOP9000) +#else +# define machine_is_top9000() (0) +#endif + +#ifdef CONFIG_MACH_TEENOTE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TEENOTE +# endif +# define machine_is_teenote() (machine_arch_type == MACH_TYPE_TEENOTE) +#else +# define machine_is_teenote() (0) +#endif + +#ifdef CONFIG_MACH_TS3 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TS3 +# endif +# define machine_is_ts3() (machine_arch_type == MACH_TYPE_TS3) +#else +# define machine_is_ts3() (0) +#endif + +#ifdef CONFIG_MACH_A0 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_A0 +# endif +# define machine_is_a0() (machine_arch_type == MACH_TYPE_A0) +#else +# define machine_is_a0() (0) +#endif + +#ifdef CONFIG_MACH_FSM9XXX_SURF +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_FSM9XXX_SURF +# endif +# define machine_is_fsm9xxx_surf() (machine_arch_type == MACH_TYPE_FSM9XXX_SURF) +#else +# define machine_is_fsm9xxx_surf() (0) +#endif + +#ifdef CONFIG_MACH_FSM9XXX_FFA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_FSM9XXX_FFA +# endif +# define machine_is_fsm9xxx_ffa() (machine_arch_type == MACH_TYPE_FSM9XXX_FFA) +#else +# define machine_is_fsm9xxx_ffa() (0) +#endif + +#ifdef CONFIG_MACH_FRRHWCDMA60W +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_FRRHWCDMA60W +# endif +# define machine_is_frrhwcdma60w() (machine_arch_type == MACH_TYPE_FRRHWCDMA60W) +#else +# define machine_is_frrhwcdma60w() (0) +#endif + +#ifdef CONFIG_MACH_REMUS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_REMUS +# endif +# define machine_is_remus() (machine_arch_type == MACH_TYPE_REMUS) +#else +# define machine_is_remus() (0) +#endif + +#ifdef CONFIG_MACH_AT91CAP7XDK +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AT91CAP7XDK +# endif +# define machine_is_at91cap7xdk() (machine_arch_type == MACH_TYPE_AT91CAP7XDK) +#else +# define machine_is_at91cap7xdk() (0) +#endif + +#ifdef CONFIG_MACH_AT91CAP7STK +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AT91CAP7STK +# endif +# define machine_is_at91cap7stk() (machine_arch_type == MACH_TYPE_AT91CAP7STK) +#else +# define machine_is_at91cap7stk() (0) +#endif + +#ifdef CONFIG_MACH_KT_SBC_SAM9_1 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_KT_SBC_SAM9_1 +# endif +# define machine_is_kt_sbc_sam9_1() (machine_arch_type == MACH_TYPE_KT_SBC_SAM9_1) +#else +# define machine_is_kt_sbc_sam9_1() (0) +#endif + +#ifdef CONFIG_MACH_ORATISROUTER +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ORATISROUTER +# endif +# define machine_is_at91sam9263router() (machine_arch_type == MACH_TYPE_ORATISROUTER) +#else +# define machine_is_at91sam9263router() (0) +#endif + +#ifdef CONFIG_MACH_ARMADA_XP_DB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ARMADA_XP_DB +# endif +# define machine_is_armada_xp_db() (machine_arch_type == MACH_TYPE_ARMADA_XP_DB) +#else +# define machine_is_armada_xp_db() (0) +#endif + +#ifdef CONFIG_MACH_SPDM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SPDM +# endif +# define machine_is_spdm() (machine_arch_type == MACH_TYPE_SPDM) +#else +# define machine_is_spdm() (0) +#endif + +#ifdef CONFIG_MACH_GTIB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_GTIB +# endif +# define machine_is_gtib() (machine_arch_type == MACH_TYPE_GTIB) +#else +# define machine_is_gtib() (0) +#endif + +#ifdef CONFIG_MACH_DGM3240 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DGM3240 +# endif +# define machine_is_dgm3240() (machine_arch_type == MACH_TYPE_DGM3240) +#else +# define machine_is_dgm3240() (0) +#endif + +#ifdef CONFIG_MACH_ATLAS_I_LPE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ATLAS_I_LPE +# endif +# define machine_is_iv_atlas_i_lpe() (machine_arch_type == MACH_TYPE_ATLAS_I_LPE) +#else +# define machine_is_iv_atlas_i_lpe() (0) +#endif + +#ifdef CONFIG_MACH_HTCMEGA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HTCMEGA +# endif +# define machine_is_htcmega() (machine_arch_type == MACH_TYPE_HTCMEGA) +#else +# define machine_is_htcmega() (0) +#endif + +#ifdef CONFIG_MACH_TRICORDER +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TRICORDER +# endif +# define machine_is_tricorder() (machine_arch_type == MACH_TYPE_TRICORDER) +#else +# define machine_is_tricorder() (0) +#endif + +#ifdef CONFIG_MACH_TX28 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TX28 +# endif +# define machine_is_tx28() (machine_arch_type == MACH_TYPE_TX28) +#else +# define machine_is_tx28() (0) +#endif + /* * These have not yet been registered */ diff --git a/include/asm-arm/mmu.h b/include/asm-arm/mmu.h new file mode 100644 index 0000000000..f1b75747ea --- /dev/null +++ b/include/asm-arm/mmu.h @@ -0,0 +1,118 @@ +/* + * Copyright 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#ifndef __ASM_MMU_H +#define __ASM_MMU_H + +#include + +#define MMU_L1_TYPE 0x03 /* Descriptor type */ +#define MMU_L1_TYPE_Fault 0x00 /* Invalid */ +#define MMU_L1_TYPE_Page 0x11 /* Individual page mapping */ +#define MMU_L1_TYPE_Section 0x12 /* Mapping for 1M segment */ + +#define MMU_L2_TYPE 0x03 /* Descriptor type */ +#define MMU_L2_TYPE_Fault 0x00 /* Invalid data */ +#define MMU_L2_TYPE_Large 0x01 /* Large page (64K) */ +#define MMU_L2_TYPE_Small 0x02 /* Small page (4K) */ + +#define MMU_Bufferable 0x04 /* Data can use write-buffer */ +#define MMU_Cacheable 0x08 /* Data can use cache */ + +#define MMU_AP_Limited 0x000 /* Limited access */ +#define MMU_AP_Supervisor 0x400 /* Supervisor RW, User none */ +#define MMU_AP_UserRead 0x800 /* Supervisor RW, User read only */ +#define MMU_AP_Any 0xC00 /* Supervisor RW, User RW */ + +#define MMU_AP_ap0_Any 0x030 +#define MMU_AP_ap1_Any 0x0C0 +#define MMU_AP_ap2_Any 0x300 +#define MMU_AP_ap3_Any 0xC00 +#define MMU_AP_All (MMU_AP_ap0_Any|MMU_AP_ap1_Any|MMU_AP_ap2_Any|MMU_AP_ap3_Any) + +#define MMU_DOMAIN(x) ((x)<<5) + +#define MMU_PAGE_SIZE 0x1000 +#define MMU_SECTION_SIZE 0x100000 + +#define MMU_CP p15 /* Co-processor ID */ +#define MMU_Control c1 /* Control register */ +#define MMU_Base c2 /* Page tables base */ +#define MMU_DomainAccess c3 /* Domain access control */ +#define MMU_FaultStatus c5 /* Fault status register */ +#define MMU_FaultAddress c6 /* Fault Address */ +#define MMU_InvalidateCache c7 /* Invalidate cache data */ +#define MMU_TLB c8 /* Translation Lookaside Buffer */ + +/* These seem to be 710 specific */ +#define MMU_FlushTLB c5 +#define MMU_FlushIDC c7 + +#define MMU_Control_M 0x001 /* Enable MMU */ +#define MMU_Control_A 0x002 /* Enable address alignment faults */ +#define MMU_Control_C 0x004 /* Enable cache */ +#define MMU_Control_W 0x008 /* Enable write-buffer */ +#define MMU_Control_P 0x010 /* Compatability: 32 bit code */ +#define MMU_Control_D 0x020 /* Compatability: 32 bit data */ +#define MMU_Control_L 0x040 /* Compatability: */ +#define MMU_Control_B 0x080 /* Enable Big-Endian */ +#define MMU_Control_S 0x100 /* Enable system protection */ +#define MMU_Control_R 0x200 /* Enable ROM protection */ +#define MMU_Control_I 0x1000 /* Enable Instruction cache */ +#define MMU_Control_X 0x2000 /* Set interrupt vectors at 0xFFFF0000 */ +#define MMU_Control_Init (MMU_Control_P|MMU_Control_D|MMU_Control_L) + +/* Extras for some newer versions eg. ARM920 with architecture version 4. */ +#define MMU_Control_F 0x400 /* IMPLEMENTATION DEFINED */ +#define MMU_Control_Z 0x800 /* Enable branch predicion */ +#define MMU_Control_RR 0x4000 /* Select non-random cache replacement */ + +#ifdef CONFIG_ARCH_MMU + +#define MMU_ON() \ + { \ + unsigned long cr = 0; \ + asm volatile ("mrc p15, 0, %0, c1, c0;" : "=r"(cr) : /*:*/); \ + cr |= (CR_M | CR_A | CR_C | CR_Z); \ + asm volatile ("mcr p15, 0, %0, c1, c0;" : : "r"(cr) /*:*/); \ + /* Clean instruction pipeline */ \ + asm volatile ( \ + "b skip;" \ + "nop;" \ + "nop;" \ + "nop;" \ + "skip:" \ + ); \ + } + +#define MMU_OFF() \ + { \ + unsigned long cr = 0; \ + asm volatile ("mrc p15, 0, %0, c1, c0;" : "=r"(cr) /*: :*/); \ + cr &= (~(CR_M | CR_A | CR_C | CR_I)); \ + asm volatile ("mcr p15, 0, %0, c1, c0;" : : "r"(cr) /*:*/); \ + asm volatile ( \ + "nop;" /* flush i+d-TLBs */ \ + "nop;" /* flush i+d-TLBs */ \ + "nop;" /* flush i+d-TLBs */ \ + ); \ + } + +#else + +#define MMU_ON() +#define MMU_OFF() + +#endif + +#endif diff --git a/include/asm-arm/proc-armv/system.h b/include/asm-arm/proc-armv/system.h index e7b0fe6fb7..b4cfa68ca3 100644 --- a/include/asm-arm/proc-armv/system.h +++ b/include/asm-arm/proc-armv/system.h @@ -12,36 +12,6 @@ #include -#define set_cr(x) \ - __asm__ __volatile__( \ - "mcr p15, 0, %0, c1, c0 @ set CR" \ - : : "r" (x)) - -#define CR_M (1 << 0) /* MMU enable */ -#define CR_A (1 << 1) /* Alignment abort enable */ -#define CR_C (1 << 2) /* Dcache enable */ -#define CR_W (1 << 3) /* Write buffer enable */ -#define CR_P (1 << 4) /* 32-bit exception handler */ -#define CR_D (1 << 5) /* 32-bit data address range */ -#define CR_L (1 << 6) /* Implementation defined */ -#define CD_B (1 << 7) /* Big endian */ -#define CR_S (1 << 8) /* System MMU protection */ -#define CD_R (1 << 9) /* ROM MMU protection */ -#define CR_F (1 << 10) /* Implementation defined */ -#define CR_Z (1 << 11) /* Implementation defined */ -#define CR_I (1 << 12) /* Icache enable */ -#define CR_V (1 << 13) /* Vectors relocated to 0xffff0000 */ -#define CR_RR (1 << 14) /* Round Robin cache replacement */ - -extern unsigned long cr_no_alignment; /* defined in entry-armv.S */ -extern unsigned long cr_alignment; /* defined in entry-armv.S */ - -#if __LINUX_ARM_ARCH__ >= 4 -#define vectors_base() ((cr_alignment & CR_V) ? 0xffff0000 : 0) -#else -#define vectors_base() (0) -#endif - /* * Save the current interrupt enable state & disable IRQs */ diff --git a/include/configs/mx23_evk.h b/include/configs/mx23_evk.h new file mode 100644 index 0000000000..16001284cb --- /dev/null +++ b/include/configs/mx23_evk.h @@ -0,0 +1,154 @@ +/* + * Copyright (C) 2008 Embedded Alley Solutions, Inc. + * + * (C) Copyright 2009-2010 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H +#include + +/* + * Define this to make U-Boot skip low level initialization when loaded + * by initial bootloader. Not required by NAND U-Boot version but IS + * required for a NOR version used to burn the real NOR U-Boot into + * NOR Flash. NAND and NOR support for DaVinci chips is mutually exclusive + * so it is NOT possible to build a U-Boot with both NAND and NOR routines. + * NOR U-Boot is loaded directly from Flash so it must perform all the + * low level initialization itself. NAND version is loaded by an initial + * bootloader (UBL in TI-ese) that performs such an initialization so it's + * skipped in NAND version. The third DaVinci boot mode loads a bootloader + * via UART0 and that bootloader in turn loads and runs U-Boot (or whatever) + * performing low level init prior to loading. All that means we can NOT use + * NAND version to put U-Boot into NOR because it doesn't have NOR support and + * we can NOT use NOR version because it performs low level initialization + * effectively destroying itself in DDR memory. That's why a separate NOR + * version with this define is needed. It is loaded via UART, then one uses + * it to somehow download a proper NOR version built WITHOUT this define to + * RAM (tftp?) and burn it to NOR Flash. I would be probably able to squeeze + * NOR support into the initial bootloader so it won't be needed but DaVinci + * static RAM might be too small for this (I have something like 2Kbytes left + * as of now, without NOR support) so this might've not happened... + * + */ + +/*===================*/ +/* SoC Configuration */ +/*===================*/ +#define CONFIG_ARM926EJS /* arm926ejs CPU core */ +#define CONFIG_MX23 /* MX23 SoC */ +#define CONFIG_MX23_EVK /* MX23 EVK board */ +#define CONFIG_SYS_CLK_FREQ 120000000 /* Arm Clock frequency */ +#define CONFIG_USE_TIMER0 /* use timer 0 */ +#define CONFIG_SYS_HZ 1000 /* Ticks per second */ +/*=============*/ +/* Memory Info */ +/*=============*/ +#define CONFIG_SYS_MALLOC_LEN (0x10000 + 128*1024) /* malloc() len */ +#define CONFIG_SYS_GBL_DATA_SIZE 128 /* reserved for initial data */ +#define CONFIG_SYS_MEMTEST_START 0x40000000 /* memtest start address */ +#define CONFIG_SYS_MEMTEST_END 0x41000000 /* 16MB RAM test */ +#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ +#define CONFIG_STACKSIZE (256*1024) /* regular stack */ +#define PHYS_SDRAM_1 0x40000000 /* mDDR Start */ +#define PHYS_SDRAM_1_SIZE 0x02000000 /* mDDR size 32MB */ + +/*====================*/ +/* Serial Driver info */ +/*====================*/ +#define CONFIG_STMP3XXX_DBGUART /* 378x debug UART */ +#define CONFIG_DBGUART_CLK 24000000 +#define CONFIG_BAUDRATE 115200 /* Default baud rate */ +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/*====================*/ +/* SPI Driver info */ +/*====================*/ +#define CONFIG_SSP_CLK 48000000 +#define CONFIG_SPI_CLK 3000000 +#define CONFIG_SPI_SSP1 +#undef CONFIG_SPI_SSP2 + +/*=====================*/ +/* Flash & Environment */ +/*=====================*/ +#define CONFIG_SYS_NO_FLASH /* Flash is not supported */ +#define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ +#define CONFIG_ENV_SIZE 0x20000 + +/*==============================*/ +/* U-Boot general configuration */ +/*==============================*/ +#undef CONFIG_USE_IRQ /* No IRQ/FIQ in U-Boot */ +#define CONFIG_MISC_INIT_R +#define CONFIG_NETMASK 255.255.255.0 +#define CONFIG_IPADDR 192.167.10.2 +#define CONFIG_SERVERIP 192.167.10.1 +#define CONFIG_BOOTDELAY 2 +#define CONFIG_BOOTFILE "uImage" /* Boot file name */ +#define CONFIG_SYS_PROMPT "MX23 U-Boot > " + /* Monitor Command Prompt */ +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) + /* Print buffer sz */ +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + /* Boot Argument Buffer Size */ +#define CONFIG_SYS_LOAD_ADDR 0x40400000 + /* default Linux kernel load address */ +#define CONFIG_VERSION_VARIABLE +#define CONFIG_AUTO_COMPLETE /* Won't work with hush so far, may be later */ +#define CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +#define CONFIG_CMDLINE_EDITING +#define CFG_LONGHELP +#define CONFIG_CRC32_VERIFY +#define CONFIG_MX_CYCLIC + +/*===================*/ +/* Linux Information */ +/*===================*/ +#define LINUX_BOOT_PARAM_ADDR 0x40000100 +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_BOOTARGS "console=ttyAM0,115200n8 "\ + "root=/dev/mtdblock1 rootfstype=jffs2 lcd_panel=lms350" +#define CONFIG_BOOTCOMMAND "tftpboot ; bootm" + +/*=================*/ +/* U-Boot commands */ +/*=================*/ +#include +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_DHCP +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_DNS +#undef CONFIG_CMD_DIAG +#define CONFIG_CMD_MII +#define CONFIG_CMD_PING +#define CONFIG_CMD_NET +#define CONFIG_CMD_SAVES +#undef CONFIG_CMD_IMLS + +/* Ethernet chip - select an alternative driver */ +#define CONFIG_ENC28J60_ETH +#define CONFIG_ENC28J60_ETH_SPI_BUS 0 +#define CONFIG_ENC28J60_ETH_SPI_CS 0 + +#endif /* __CONFIG_H */ diff --git a/include/configs/mx25_3stack.h b/include/configs/mx25_3stack.h new file mode 100644 index 0000000000..e8383c26b6 --- /dev/null +++ b/include/configs/mx25_3stack.h @@ -0,0 +1,282 @@ +/* + * (C) Copyright 2009-2010 Freescale Semiconductor + * + * (C) Copyright 2004 + * Texas Instruments. + * Richard Woodruff + * Kshitij Gupta + * + * Configuration settings for the Freescale i.MX31 PDK board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include +#include + +/* High Level Configuration Options */ +#define CONFIG_ARM926EJS 1 /* This is an arm1136 CPU core */ +#define CONFIG_MX25 1 /* in a mx31 */ +#define CONFIG_MX25_HCLK_FREQ 24000000 +#define CONFIG_MX25_CLK32 32768 + +#define CONFIG_IMX_CSPI 1 +#define IMX_CSPI_VER_0_7 1 +#define CONFIG_IMX_SPI_CPLD + +/* IF iMX25 3DS V-1.0 define it */ +/* #define CONFIG_MX25_3DS_V10 */ + +#ifdef CONFIG_MX25_3DS_V10 +#define MXC_MEMORY_MDDR +#endif + +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO + +#define CONFIG_SYS_64BIT_VSPRINTF + +#define BOARD_LATE_INIT + +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 + +/* No support for NAND boot for i.MX31 PDK yet, so we rely on some other + * program to initialize the SDRAM. + */ +#define CONFIG_SKIP_RELOCATE_UBOOT + +/* + * Size of malloc() pool + */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 512 * 1024) +#define CONFIG_SYS_GBL_DATA_SIZE 128 /* bytes reserved initial data */ + +/* + * Hardware drivers + */ +#define CONFIG_HARD_I2C 1 +#define CONFIG_I2C_MXC 1 +#define CONFIG_SYS_I2C_PORT I2C1_BASE +#define CONFIG_SYS_I2C_SPEED 40000 +#define CONFIG_SYS_I2C_SLAVE 0xfe + +#define CONFIG_MX25_UART 1 +#define CONFIG_MX25_UART1 1 + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200} + +/*********************************************************** + * Command definition + ***********************************************************/ + +#include + +#define CONFIG_CMD_I2C +#define CONFIG_CMD_MII +#define CONFIG_CMD_PING +/* #define CONFIG_CMD_SPI */ +/* #define CONFIG_CMD_DATE */ +#define CONFIG_CMD_NAND +#define CONFIG_CMD_MMC +#define CONFIG_MXC_NAND + + +/* + * MMC Configs + * */ +#ifdef CONFIG_CMD_MMC + #define CONFIG_MMC 1 + #define CONFIG_GENERIC_MMC + #define CONFIG_IMX_MMC + #define CONFIG_SYS_FSL_ESDHC_NUM 2 + #define CONFIG_SYS_FSL_ESDHC_ADDR 0 + #define CONFIG_SYS_MMC_ENV_DEV 0 + #define CONFIG_IMX_ESDHC_V1 + #define CONFIG_DOS_PARTITION 1 + #define CONFIG_CMD_FAT 1 +#endif + +/* Disabled due to compilation errors in cmd_bootm.c (IMLS seems to require + * that CONFIG_NO_FLASH is undefined). + */ +#undef CONFIG_CMD_IMLS + +#define CONFIG_BOOTDELAY 3 + +#define CONFIG_LOADADDR 0x80800000 /* loadaddr env var */ + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "ethprime=smc911x-0\0" \ + "uboot=u-boot.bin\0" \ + "uboot_addr=0xa0000000\0" \ + "kernel=uImage\0" \ + "bootargs_base=setenv bootargs console=ttymxc0,115200\0" \ + "bootargs_nfs=setenv bootargs $(bootargs) root=/dev/nfs " \ + "ip=dhcp nfsroot=$(serverip):$(nfsrootfs),v3,tcp\0" \ + "bootcmd=run bootcmd_net\0" \ + "bootcmd_net=run bootargs_base bootargs_nfs; " \ + "tftpboot ${loadaddr} ${kernel}; bootm\0" \ + "load_uboot=tftpboot ${loadaddr} ${uboot}\0" \ + "splashimage=0x80800000\0" + +/*Support LAN9217*/ +#define CONFIG_SMC911X +#define CONFIG_SMC911X_CPLD +#define CONFIG_SMC911X_BASE 0 + +#define CONFIG_HAS_ETH1 +#define CONFIG_CMD_NET +#define CONFIG_NET_RETRY_COUNT 100 +#define CONFIG_CMD_DHCP +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_DNS +#define CONFIG_NET_MULTI +#define CONFIG_ETHPRIME + +#define CONFIG_MXC_FEC +#define CONFIG_MII +#define CONFIG_MII_GASKET +#define CONFIG_DISCOVER_PHY + +#define CONFIG_GET_FEC_MAC_ADDR_FROM_IIM +#define CONFIG_IIM_MAC_ADDR_OFFSET 0x68 + +#define CONFIG_FEC0_IOBASE FEC_BASE +#define CONFIG_FEC0_PINMUX -1 +#define CONFIG_FEC0_PHY_ADDR 0x1F +#define CONFIG_FEC0_MIIBASE -1 + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_PROMPT "MX25 U-Boot > " +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buf Size */ + +#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1 /* memtest works on */ +#define CONFIG_SYS_MEMTEST_END 0x10000 + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR /* default load address */ + +#define CONFIG_SYS_HZ 1000 + +#define UBOOT_IMAGE_SIZE 0x40000 + +#define CONFIG_CMDLINE_EDITING 1 + +/*----------------------------------------------------------------------- + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */ + +/*----------------------------------------------------------------------- + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM_1 CSD0_BASE + +/* iMX25 V-1.0 has 128MB but V-1.1 has only 64MB */ +#ifdef CONFIG_MX25_3DS_V10 +#define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024) +#else +#define PHYS_SDRAM_1_SIZE (64 * 1024 * 1024) +#endif + +/* LCD */ +/* +#define CONFIG_SPLASH_SCREEN +*/ + +#ifdef CONFIG_SPLASH_SCREEN + #define CONFIG_LCD + #define CONFIG_MXC2_LCD 1 + #undef LCD_TEST_PATTERN + #define CONFIG_FB_BASE 0x81400000 + #define CONFIG_SYS_CONSOLE_IS_IN_ENV 1 + #define CONFIG_SPLASH_SCREEN 1 + #define CONFIG_SPLASH_IS_IN_MMC 1 + #define LCD_BPP LCD_COLOR16 + /* #define CONFIG_SPLASH_SCREEN_ALIGN 1 */ + + #define CONFIG_CMD_BMP + #define CONFIG_BMP_24BPP 1 + #define CONFIG_BMP_16BPP 1 +#endif + + +#ifdef CONFIG_SPLASH_IS_IN_MMC + #define CONFIG_SPLASH_IMG_MMC_DEV 0 + #define CONFIG_SPLASH_IMG_OFFSET 0x4c000 + #define CONFIG_SPLASH_IMG_SIZE 0x19000 +#endif + +/* Monitor at beginning of flash */ +/* #define CONFIG_FSL_ENV_IN_MMC */ +#define CONFIG_FSL_ENV_IN_NAND + +/*----------------------------------------------------------------------- + * FLASH and environment organization + */ +#if defined(CONFIG_FSL_ENV_IN_NAND) + #define CONFIG_ENV_IS_IN_NAND 1 + #define CONFIG_ENV_OFFSET 0x80000 +#elif defined(CONFIG_FSL_ENV_IN_MMC) + #define CONFIG_ENV_IS_IN_MMC 1 + #define CONFIG_ENV_OFFSET (768 * 1024) +#else + #define CONFIG_ENV_IS_NOWHERE 1 +#endif + +#define CONFIG_ENV_SECT_SIZE (256 * 1024) +#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE + +/*----------------------------------------------------------------------- + * NAND FLASH driver setup + */ +#define CONFIG_SYS_NO_FLASH +#define NAND_MAX_CHIPS 1 +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE 0x40000000 + +/* + * JFFS2 partitions TODO: + */ +#undef CONFIG_JFFS2_CMDLINE +#define CONFIG_JFFS2_DEV "nand0" + +#endif /* __CONFIG_H */ + diff --git a/include/configs/mx25_3stack_mfg.h b/include/configs/mx25_3stack_mfg.h new file mode 100644 index 0000000000..a907d0636a --- /dev/null +++ b/include/configs/mx25_3stack_mfg.h @@ -0,0 +1,262 @@ +/* + * (C) Copyright 2009-2010 Freescale Semiconductor + * + * (C) Copyright 2004 + * Texas Instruments. + * Richard Woodruff + * Kshitij Gupta + * + * Configuration settings for the Freescale i.MX31 PDK board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include +#include + +/* High Level Configuration Options */ +#define CONFIG_ARM926EJS 1 /* This is an arm1136 CPU core */ +#define CONFIG_MX25 1 /* in a mx31 */ +#define CONFIG_MX25_HCLK_FREQ 24000000 +#define CONFIG_MX25_CLK32 32768 + +#define CONFIG_MFG 1 +#define CONFIG_IMX_CSPI 1 +#define IMX_CSPI_VER_0_7 1 +#define CONFIG_IMX_SPI_CPLD + +/* IF iMX25 3DS V-1.0 define it */ +/* #define CONFIG_MX25_3DS_V10 */ + +#ifdef CONFIG_MX25_3DS_V10 +#define MXC_MEMORY_MDDR +#endif + +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO + +#define CONFIG_SYS_64BIT_VSPRINTF +#define BOARD_LATE_INIT + +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 +#define CONFIG_REVISION_TAG 1 + +/* No support for NAND boot for i.MX31 PDK yet, so we rely on some other + * program to initialize the SDRAM. + */ +#define CONFIG_SKIP_RELOCATE_UBOOT + +/* + * Size of malloc() pool + */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 512 * 1024) +#define CONFIG_SYS_GBL_DATA_SIZE 128 /* bytes reserved initial data */ + +/* + * Hardware drivers + */ +#define CONFIG_HARD_I2C 1 +#define CONFIG_I2C_MXC 1 +#define CONFIG_SYS_I2C_PORT I2C1_BASE +#define CONFIG_SYS_I2C_SPEED 40000 +#define CONFIG_SYS_I2C_SLAVE 0xfe + +#define CONFIG_MX25_UART 1 +#define CONFIG_MX25_UART1 1 + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200} + +/*********************************************************** + * Command definition + ***********************************************************/ + +#include + +#define CONFIG_CMD_I2C +#define CONFIG_CMD_MII +#define CONFIG_CMD_PING +/* #define CONFIG_CMD_SPI */ +/* #define CONFIG_CMD_DATE */ +#define CONFIG_CMD_NAND +#define CONFIG_CMD_MMC +#define CONFIG_MXC_NAND + +/* + * MMC Configs + * */ +#ifdef CONFIG_CMD_MMC + #define CONFIG_MMC 1 + #define CONFIG_GENERIC_MMC + #define CONFIG_IMX_MMC + #define CONFIG_SYS_FSL_ESDHC_NUM 2 + #define CONFIG_SYS_FSL_ESDHC_ADDR 0 + #define CONFIG_SYS_MMC_ENV_DEV 0 + #define CONFIG_IMX_ESDHC_V1 + #define CONFIG_DOS_PARTITION 1 + #define CONFIG_CMD_FAT 1 +#endif + +/* Disabled due to compilation errors in cmd_bootm.c (IMLS seems to require + * that CONFIG_NO_FLASH is undefined). + */ +#undef CONFIG_CMD_IMLS + +#define CONFIG_BOOTDELAY 0 + +#define CONFIG_LOADADDR 0x80100000 /* loadaddr env var */ + +#define CONFIG_BOOTAGS "console=ttymxc0,115200 "\ + "rdinit=/linuxrc" +#define CONFIG_BOOTCOMMAND "bootm ${loadaddr} 0x80800000" +#define CONFIG_ENV_IS_EMBEDDED + +/* +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "ethprime=smc911x-0\0" \ + "uboot=u-boot.bin\0" \ + "uboot_addr=0xa0000000\0" \ + "kernel=uImage\0" \ + "bootargs_base=setenv bootargs console=ttymxc0,115200\0" \ + "bootargs_nfs=setenv bootargs $(bootargs) root=/dev/nfs " \ + "ip=dhcp nfsroot=$(serverip):$(nfsrootfs),v3,tcp\0" \ + "bootcmd=run bootcmd_net\0" \ + "bootcmd_net=run bootargs_base bootargs_nfs; " \ + "tftpboot ${loadaddr} ${kernel}; bootm\0" \ + "load_uboot=tftpboot ${loadaddr} ${uboot}\0" +*/ + +/*Support LAN9217*/ +#define CONFIG_SMC911X +#define CONFIG_SMC911X_CPLD +#define CONFIG_SMC911X_BASE 0 + +#define CONFIG_HAS_ETH1 +#define CONFIG_CMD_NET +#define CONFIG_NET_RETRY_COUNT 100 +#define CONFIG_CMD_DHCP +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_DNS +#define CONFIG_NET_MULTI +#define CONFIG_ETHPRIME + +#define CONFIG_MXC_FEC +#define CONFIG_MII +#define CONFIG_MII_GASKET +#define CONFIG_DISCOVER_PHY + +#define CONFIG_FEC0_IOBASE FEC_BASE +#define CONFIG_FEC0_PINMUX -1 +#define CONFIG_FEC0_PHY_ADDR 0x1F +#define CONFIG_FEC0_MIIBASE -1 + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_PROMPT "MX25 U-Boot > " +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buf Size */ + +#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1 /* memtest works on */ +#define CONFIG_SYS_MEMTEST_END 0x10000 + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR /* default load address */ + +#define CONFIG_SYS_HZ 1000 + +#define UBOOT_IMAGE_SIZE 0x40000 + +#define CONFIG_CMDLINE_EDITING 1 + +/*----------------------------------------------------------------------- + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */ + +/*----------------------------------------------------------------------- + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM_1 CSD0_BASE + +/* iMX25 V-1.0 has 128MB but V-1.1 has only 64MB */ +#ifdef CONFIG_MX25_3DS_V10 +#define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024) +#else +#define PHYS_SDRAM_1_SIZE (64 * 1024 * 1024) +#endif + +/* Monitor at beginning of flash */ +/* #define CONFIG_FSL_ENV_IN_MMC */ +/*#define CONFIG_FSL_ENV_IN_NAND*/ + +/*----------------------------------------------------------------------- + * FLASH and environment organization + */ +/* +#if defined(CONFIG_FSL_ENV_IN_NAND) + #define CONFIG_ENV_IS_IN_NAND 1 + #define CONFIG_ENV_OFFSET 0x80000 +#elif defined(CONFIG_FSL_ENV_IN_MMC) + #define CONFIG_ENV_IS_IN_MMC 1 + #define CONFIG_ENV_OFFSET (768 * 1024) +#else + #define CONFIG_ENV_IS_NOWHERE 1 +#endif +*/ + +#define CONFIG_ENV_IS_NOWHERE + +#define CONFIG_ENV_SECT_SIZE (256 * 1024) +#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE + +/*----------------------------------------------------------------------- + * NAND FLASH driver setup + */ +#define CONFIG_SYS_NO_FLASH +#define NAND_MAX_CHIPS 1 +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE 0x40000000 + +/* + * JFFS2 partitions TODO: + */ +/* +#undef CONFIG_JFFS2_CMDLINE +#define CONFIG_JFFS2_DEV "nand0" +*/ +#endif /* __CONFIG_H */ + diff --git a/include/configs/mx28_evk.h b/include/configs/mx28_evk.h new file mode 100644 index 0000000000..3148fd2af5 --- /dev/null +++ b/include/configs/mx28_evk.h @@ -0,0 +1,160 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __MX28_EVK_H +#define __MX28_EVK_H + +#include + +/* + * SoC configurations + */ +#define CONFIG_MX28 /* i.MX28 SoC */ +#define CONFIG_MX28_TO1_2 +#define CONFIG_SYS_HZ 1000 /* Ticks per second */ +/* ROM loads UBOOT into DRAM */ +#define CONFIG_SKIP_RELOCATE_UBOOT + +/* + * Memory configurations + */ +#define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */ +#define PHYS_SDRAM_1 0x40000000 /* Base address */ +#define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */ +#define CONFIG_STACKSIZE 0x00020000 /* 128 KB stack */ +#define CONFIG_SYS_MALLOC_LEN 0x00400000 /* 4 MB for malloc */ +#define CONFIG_SYS_GBL_DATA_SIZE 128 /* Reserved for initial data */ +#define CONFIG_SYS_MEMTEST_START 0x40000000 /* Memtest start address */ +#define CONFIG_SYS_MEMTEST_END 0x40400000 /* 4 MB RAM test */ + +/* + * U-Boot general configurations + */ +#define CONFIG_SYS_PROMPT "MX28 U-Boot > " +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */ +#define CONFIG_SYS_PBSIZE \ + (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) + /* Print buffer size */ +#define CONFIG_SYS_MAXARGS 16 /* Max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + /* Boot argument buffer size */ +#define CONFIG_VERSION_VARIABLE /* U-BOOT version */ +#define CONFIG_AUTO_COMPLETE /* Command auto complete */ +#define CONFIG_CMDLINE_EDITING /* Command history etc */ + +#define CONFIG_SYS_64BIT_VSPRINTF + +/* + * Boot Linux + */ +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_BOOTDELAY 3 +#define CONFIG_BOOTFILE "uImage" +#define CONFIG_BOOTARGS "console=ttyAM0,115200n8 " +#define CONFIG_BOOTCOMMAND "run bootcmd_net" +#define CONFIG_LOADADDR 0x42000000 +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +/* + * Extra Environments + */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "nfsroot=/home/notroot/nfs/rootfs\0" \ + "bootargs_nfs=setenv bootargs ${bootargs} root=/dev/nfs " \ + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp " \ + "fec_mac=${ethaddr}\0" \ + "bootcmd_net=run bootargs_nfs; dhcp; bootm\0" \ + "bootargs_mmc=setenv bootargs ${bootargs} root=/dev/mmcblk0p3 " \ + "rw rootwait ip=dhcp fec_mac=${ethaddr}\0" \ + "bootcmd_mmc=run bootargs_mmc; " \ + "mmc read 0 ${loadaddr} 100 3000; bootm\0" \ + +/* + * U-Boot Commands + */ +#define CONFIG_SYS_NO_FLASH +#include +#define CONFIG_ARCH_CPU_INIT +#define CONFIG_DISPLAY_CPUINFO + +/* + * Serial Driver + */ +#define CONFIG_UARTDBG_CLK 24000000 +#define CONFIG_BAUDRATE 115200 /* Default baud rate */ +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/* + * FEC Driver + */ +#define CONFIG_MXC_FEC +#define CONFIG_GET_FEC_MAC_ADDR_FROM_IIM +#define CONFIG_FEC0_IOBASE REGS_ENET_BASE +#define CONFIG_FEC0_PHY_ADDR 0 +#define CONFIG_NET_MULTI +#define CONFIG_ETH_PRIME +#define CONFIG_RMII +#define CONFIG_CMD_MII +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_PING +#define CONFIG_IPADDR 192.168.1.103 +#define CONFIG_SERVERIP 192.168.1.101 +#define CONFIG_NETMASK 255.255.255.0 +/* Add for working with "strict" DHCP server */ +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_DNS + +/* + * MMC Driver + */ +#define CONFIG_CMD_MMC +#define CONFIG_MMC +#define CONFIG_IMX_SSP_MMC /* MMC driver based on SSP */ +#define CONFIG_GENERIC_MMC +#define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_DOS_PARTITION +#define CONFIG_CMD_FAT +#define CONFIG_SYS_SSP_MMC_NUM 2 + +/* + * Environments on MMC + */ +#define CONFIG_CMD_ENV +#define CONFIG_ENV_OVERWRITE +#define CONFIG_ENV_IS_IN_MMC +/* Assoiated with the MMC layout defined in mmcops.c */ +#define CONFIG_ENV_OFFSET (0x400) /* 1 KB */ +#define CONFIG_ENV_SIZE (0x20000 - 0x400) /* 127 KB */ +#define CONFIG_DYNAMIC_MMC_DEVNO + +/* The global boot mode will be detected by ROM code and + * a boot mode value will be stored at fixed address: + * TO1.0 addr 0x0001a7f0 + * TO1.2 addr 0x00019BF0 + */ +#ifndef MX28_EVK_TO1_0 + #define GLOBAL_BOOT_MODE_ADDR 0x00019BF0 +#else + #define GLOBAL_BOOT_MODE_ADDR 0x0001a7f0 +#endif +#define BOOT_MODE_SD0 0x9 +#define BOOT_MODE_SD1 0xa + +#endif /* __MX28_EVK_H */ diff --git a/include/configs/mx31_3stack.h b/include/configs/mx31_3stack.h new file mode 100644 index 0000000000..d7629b2925 --- /dev/null +++ b/include/configs/mx31_3stack.h @@ -0,0 +1,163 @@ +/* + * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. + * + * Configuration settings for the MX31 3Stack Freescale board. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include + + /* High Level Configuration Options */ +#define CONFIG_ARM1136 1 /* This is an arm1136 CPU core */ +#define CONFIG_MX31 1 /* in a mx31 */ +#define CONFIG_MX31_HCLK_FREQ 26000000 +#define CONFIG_MX31_CLK32 32768 + +#define CONFIG_MX31_NAND + +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO + +#define CONFIG_SKIP_RELOCATE_UBOOT + +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 + +/* + * Size of malloc() pool + */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 512 * 1024) +#define CONFIG_SYS_GBL_DATA_SIZE 128 + +/* + * Hardware drivers + */ +#define CONFIG_MXC_UART 1 +#define CONFIG_SYS_MX31_UART1 1 + +#define CONFIG_MXC_SPI 1 + +#define CONFIG_RTC_MC13783 1 +#define CONFIG_MC13783_SPI_BUS 1 +#define CONFIG_MC13783_SPI_CS 0 + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200} + +/*********************************************************** + * Command definition + ***********************************************************/ + +#include + +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_SPI +#define CONFIG_CMD_DATE +#define CONFIG_CMD_NAND +#undef CONFIG_CMD_IMLS + +#define CONFIG_BOOTDELAY 3 + +#define CONFIG_LOADADDR 0x80800000 /* loadaddr env var */ + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "uboot=u-boot.bin\0" \ + "kernel=uImage\0" \ + "loadaddr=0x80010000\0" \ + "tftp_server=10.192.225.58\0" \ + "serverip=10.192.225.211\0" \ + "nfsroot=/tools/rootfs/rootfs-2.6.24\0" \ + "bootargs_base=setenv bootargs console=ttymxc0,115200\0" \ + "bootargs_nfs=setenv bootargs ${bootargs} root=/dev/nfs " \ + "ip=dhcp nfsroot=${serverip}:${nfsroot} rw\0" \ + "bootcmd=run bootcmd_net\0" \ + "bootcmd_net=run bootargs_base bootargs_nfs; " \ + "tftpboot ${loadaddr} ${tftp_server}:${kernel}; bootm\0" + +/* configure for smc91xx debug board ethernet */ +#define CONFIG_NET_MULTI +#define CONFIG_SMC911X 1 +#define CONFIG_SMC911X_16_BIT 1 +#define CONFIG_SMC911X_BASE CS5_BASE + +#define CONFIG_ARP_TIMEOUT 200UL + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_PROMPT "MX31 U-Boot > " +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ + +#define CONFIG_SYS_MEMTEST_START 0 /* memtest works on */ +#define CONFIG_SYS_MEMTEST_END 0x10000 + +#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */ + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +#define CONFIG_SYS_HZ CONFIG_MX31_CLK32 + +#define CONFIG_CMDLINE_EDITING 1 + +/*----------------------------------------------------------------------- + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */ + +/*----------------------------------------------------------------------- + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM_1 CSD0_BASE +#define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024) + +/* + * TODO: NAND Flash configure + */ + +#define CONFIG_SYS_NO_FLASH +#define NAND_MAX_CHIPS 1 +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE 0x40000000 + +#define CONFIG_ENV_IS_IN_NAND 1 +#define CONFIG_ENV_OFFSET 0x40000 /* 2nd block */ +#define CONFIG_ENV_SIZE (128*1024) +/* + * JFFS2 partitions TODO: + */ +#undef CONFIG_JFFS2_CMDLINE +#define CONFIG_JFFS2_DEV "nand0" + +#endif /* __CONFIG_H */ diff --git a/include/configs/mx35_3stack.h b/include/configs/mx35_3stack.h new file mode 100644 index 0000000000..89b9f39b74 --- /dev/null +++ b/include/configs/mx35_3stack.h @@ -0,0 +1,253 @@ +/* + * Copyright (C) 2007, Guennadi Liakhovetski + * + * (C) Copyright 2008-2010 Freescale Semiconductor, Inc. + * + * Configuration settings for the MX31ADS Freescale board. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include + + /* High Level Configuration Options */ +#define CONFIG_ARM1136 1 /* This is an arm1136 CPU core */ +#define CONFIG_MXC 1 +#define CONFIG_MX35 1 /* in a mx31 */ +#define CONFIG_MX35_HCLK_FREQ 24000000 /* RedBoot says 26MHz */ + +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO + +#define CONFIG_SYS_64BIT_VSPRINTF + +#define BOARD_LATE_INIT +/* + * Disabled for now due to build problems under Debian and a significant increase + * in the final file size: 144260 vs. 109536 Bytes. + */ +#if 0 +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_FIT 1 +#define CONFIG_FIT_VERBOSE 1 +#endif + +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_REVISION_TAG 1 +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 + +/* + * Size of malloc() pool + */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 512 * 1024) +#define CONFIG_SYS_GBL_DATA_SIZE 128/* size in bytes reserved for initial data */ + +/* + * Hardware drivers + */ +#define CONFIG_HARD_I2C 1 +#define CONFIG_I2C_MXC 1 +#define CONFIG_SYS_I2C_PORT I2C_BASE_ADDR +#define CONFIG_SYS_I2C_SPEED 100000 +#define CONFIG_SYS_I2C_SLAVE 0xfe + +#define CONFIG_MX35_UART UART1_BASE_ADDR + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200} + +/*********************************************************** + * Command definition + ***********************************************************/ + +#include + +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_DNS +/*#define CONFIG_CMD_SPI*/ +/*#define CONFIG_CMD_DATE*/ +#define CONFIG_CMD_NAND +#define CONFIG_MXC_NAND + +#define CONFIG_CMD_I2C +#define CONFIG_CMD_MII +#define CONFIG_CMD_NET +#define CONFIG_NET_RETRY_COUNT 100 + +#define CONFIG_BOOTDELAY 3 + +#define CONFIG_LOADADDR 0x80800000 /* loadaddr env var */ + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "ethprime=smc911x\0" \ + "uboot_addr=0xa0000000\0" \ + "uboot=u-boot.bin\0" \ + "kernel=uImage\0" \ + "nfsroot=/opt/eldk/arm\0" \ + "bootargs_base=setenv bootargs console=ttymxc0,115200\0"\ + "bootargs_nfs=setenv bootargs ${bootargs} root=/dev/nfs "\ + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0"\ + "bootcmd=run bootcmd_net\0" \ + "bootcmd_net=run bootargs_base bootargs_nfs; " \ + "tftpboot ${loadaddr} ${kernel}; bootm\0" \ + "prg_uboot=tftpboot ${loadaddr} ${uboot}; " \ + "protect off ${uboot_addr} 0xa003ffff; " \ + "erase ${uboot_addr} 0xa003ffff; " \ + "cp.b ${loadaddr} ${uboot_addr} ${filesize}; " \ + "setenv filesize; saveenv\0" + +/*Support LAN9217*/ +#define CONFIG_SMC911X 1 +#define CONFIG_SMC911X_16_BIT 1 +#define CONFIG_SMC911X_BASE CS5_BASE_ADDR + +#define CONFIG_HAS_ETH1 +#define CONFIG_NET_MULTI 1 +#define CONFIG_ETHPRIME +#define CONFIG_MXC_FEC +#define CONFIG_MII +#define CONFIG_DISCOVER_PHY + +#define CONFIG_FEC0_IOBASE FEC_BASE_ADDR +#define CONFIG_FEC0_PINMUX -1 +#define CONFIG_FEC0_PHY_ADDR 0x1F +#define CONFIG_FEC0_MIIBASE -1 + +/* + * The MX31ADS board seems to have a hardware "peculiarity" confirmed under + * U-Boot, RedBoot and Linux: the ethernet Rx signal is reaching the CS8900A + * controller inverted. The controller is capable of detecting and correcting + * this, but it needs 4 network packets for that. Which means, at startup, you + * will not receive answers to the first 4 packest, unless there have been some + * broadcasts on the network, or your board is on a hub. Reducing the ARP + * timeout from default 5 seconds to 200ms we speed up the initial TFTP + * transfer, should the user wish one, significantly. + */ +#define CONFIG_ARP_TIMEOUT 200UL + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_PROMPT "MX35 U-Boot > " +#define CONFIG_ARCH_CPU_INIT +#define CONFIG_ARCH_MMU +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ + +#define CONFIG_SYS_MEMTEST_START 0 /* memtest works on */ +#define CONFIG_SYS_MEMTEST_END 0x10000 + +#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */ + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +#define CONFIG_SYS_HZ 1000 + +#define CONFIG_CMDLINE_EDITING 1 + +/*----------------------------------------------------------------------- + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */ + +/*----------------------------------------------------------------------- + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM_1 CSD0_BASE_ADDR +#define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024) +#define iomem_valid_addr(addr, size) \ + (addr >= PHYS_SDRAM_1 && addr <= (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE)) + +/*----------------------------------------------------------------------- + * FLASH and environment organization + */ +#define CONFIG_SYS_FLASH_BASE CS0_BASE_ADDR +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */ +/* Monitor at beginning of flash */ +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE +#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 256KiB */ + +#define CONFIG_ENV_SECT_SIZE (128 * 1024) +#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE + +/* Address and size of Redundant Environment Sector */ +#define CONFIG_ENV_OFFSET_REDUND (2 * 1024 * 1024) +#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE + +/* + * S29WS256N NOR flash has 4 32KiB small sectors at the beginning and at the + * end. The rest of 32MiB is in 128KiB big sectors. U-Boot occupies the low + * 4 sectors, if we put environment next to it, we will have to occupy 128KiB + * for it. Putting it at the top of flash we use only 32KiB. + */ +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_ENV_SECT_SIZE) + +#if defined(CONFIG_CMD_NAND) + #define CONFIG_FSL_ENV_IN_NAND +#else + #define CONFIG_ENV_IS_IN_FLASH 1 +#endif + +#if defined(CONFIG_FSL_ENV_IN_NAND) + #define CONFIG_ENV_IS_IN_NAND 1 + #define CONFIG_ENV_OFFSET (1024 * 1024) +#elif defined(CONFIG_FSL_ENV_IS_IN_FLASH) + #define CONFIG_ENV_IS_IN_FLASH 1 +#endif + +/*----------------------------------------------------------------------- + * CFI FLASH driver setup + */ +#define CONFIG_SYS_FLASH_CFI 1/* Flash memory is CFI compliant */ +#define CONFIG_FLASH_CFI_DRIVER 1/* Use drivers/cfi_flash.c */ +/* A non-standard buffered write algorithm */ +#define CONFIG_FLASH_SPANSION_S29WS_N 1 +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1/* Use buffered writes (~10x faster) */ +#define CONFIG_SYS_FLASH_PROTECTION 1/* Use hardware sector protection */ + +/*----------------------------------------------------------------------- + * NAND FLASH driver setup + */ +#define NAND_MAX_CHIPS 1 +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE 0x40000000 +/* + * JFFS2 partitions + */ +#undef CONFIG_JFFS2_CMDLINE +#define CONFIG_JFFS2_DEV "nor0" + +#endif /* __CONFIG_H */ diff --git a/include/configs/mx35_3stack_mfg.h b/include/configs/mx35_3stack_mfg.h new file mode 100644 index 0000000000..ba962efe36 --- /dev/null +++ b/include/configs/mx35_3stack_mfg.h @@ -0,0 +1,255 @@ +/* + * Copyright (C) 2007, Guennadi Liakhovetski + * + * (C) Copyright 2008-2010 Freescale Semiconductor, Inc. + * + * Configuration settings for the MX35 3stack Freescale board. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include +/* for mfg firmware */ +#define CONFIG_MFG +#define CONFIG_BOOTARGS "console=ttymxc0,115200 rdinit=/linuxrc" +#define CONFIG_ENV_IS_NOWHERE + /* High Level Configuration Options */ +#define CONFIG_ARM1136 1 /* This is an arm1136 CPU core */ +#define CONFIG_MXC 1 +#define CONFIG_MX35 1 /* in a mx31 */ +#define CONFIG_MX35_HCLK_FREQ 24000000 /* RedBoot says 26MHz */ + +#define CONFIG_ARCH_CPU_INIT +#define CONFIG_ARCH_MMU + +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO + +#define CONFIG_SYS_64BIT_VSPRINTF + +#define BOARD_LATE_INIT +/* + * Disabled for now due to build problems under Debian + * and a significant increase + * in the final file size: 144260 vs. 109536 Bytes. + */ +#if 0 +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_FIT 1 +#define CONFIG_FIT_VERBOSE 1 +#endif + +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_REVISION_TAG 1 +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 + +/* + * Size of malloc() pool + */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 512 * 1024) +/* size in bytes reserved for initial data */ +#define CONFIG_SYS_GBL_DATA_SIZE 128 + +/* + * Hardware drivers + */ +#define CONFIG_HARD_I2C 1 +#define CONFIG_I2C_MXC 1 +#define CONFIG_SYS_I2C_PORT I2C_BASE_ADDR +#define CONFIG_SYS_I2C_SPEED 100000 +#define CONFIG_SYS_I2C_SLAVE 0xfe + +#define CONFIG_MX35_UART UART1_BASE_ADDR + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200} + +/*********************************************************** + * Command definition + ***********************************************************/ + +#include + +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_DNS +/*#define CONFIG_CMD_SPI*/ +/*#define CONFIG_CMD_DATE*/ +/*#define CONFIG_CMD_NAND*/ +#define CONFIG_CMD_ENV +/* #define CONFIG_CMD_MMC */ + +#define CONFIG_CMD_I2C +#define CONFIG_CMD_MII +#define CONFIG_CMD_NET +#define CONFIG_NET_RETRY_COUNT 100 + +#define CONFIG_BOOTDELAY 0 + +#define CONFIG_LOADADDR 0x80100000 /* loadaddr env var */ +#define CONFIG_BOOTCOMMAND "bootm ${loadaddr} 0x80800000" +/*Support LAN9217*/ +#define CONFIG_SMC911X 1 +#define CONFIG_SMC911X_16_BIT 1 +#define CONFIG_SMC911X_BASE CS5_BASE_ADDR + +#define CONFIG_HAS_ETH1 +#define CONFIG_NET_MULTI 1 +#define CONFIG_ETHPRIME +#define CONFIG_MXC_FEC +#define CONFIG_MII +#define CONFIG_DISCOVER_PHY + +#define CONFIG_FEC0_IOBASE FEC_BASE_ADDR +#define CONFIG_FEC0_PINMUX -1 +#define CONFIG_FEC0_PHY_ADDR 0x1F +#define CONFIG_FEC0_MIIBASE -1 + +/* + * The MX31ADS board seems to have a hardware "peculiarity" confirmed under + * U-Boot, RedBoot and Linux: the ethernet Rx signal is reaching the CS8900A + * controller inverted. The controller is capable of detecting and correcting + * this, but it needs 4 network packets for that. Which means, at startup, you + * will not receive answers to the first 4 packest, unless there have been some + * broadcasts on the network, or your board is on a hub. Reducing the ARP + * timeout from default 5 seconds to 200ms we speed up the initial TFTP + * transfer, should the user wish one, significantly. + */ +#define CONFIG_ARP_TIMEOUT 200UL + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_PROMPT "MX35 U-Boot > " +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ + +#define CONFIG_SYS_MEMTEST_START 0 /* memtest works on */ +#define CONFIG_SYS_MEMTEST_END 0x10000 + +#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */ + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +#define CONFIG_SYS_HZ 1000 + +#define CONFIG_CMDLINE_EDITING 1 + +/*----------------------------------------------------------------------- + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */ + +/*----------------------------------------------------------------------- + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM_1 CSD0_BASE_ADDR +#define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024) +#define iomem_valid_addr(addr, size) \ + (addr >= PHYS_SDRAM_1 && addr <= (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE)) + +/* + * MMC Configs + * */ +#ifdef CONFIG_CMD_MMC + #define CONFIG_MMC 1 + #define CONFIG_GENERIC_MMC + #define CONFIG_IMX_MMC + #define CONFIG_SYS_FSL_ESDHC_NUM 2 + #define CONFIG_SYS_FSL_ESDHC_ADDR 0 + #define CONFIG_SYS_MMC_ENV_DEV 0 + #define CONFIG_DOS_PARTITION 1 + #define CONFIG_CMD_FAT 1 +#endif + +#define CONFIG_DOS_PARTITION 1 +#define CONFIG_CMD_FAT 1 + +/*----------------------------------------------------------------------- + * FLASH and environment organization + */ +#define CONFIG_SYS_FLASH_BASE CS0_BASE_ADDR +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */ +/* Monitor at beginning of flash */ +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE +#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 256KiB */ + +#define CONFIG_ENV_SECT_SIZE (128 * 1024) +#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE + +/* Address and size of Redundant Environment Sector */ +#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) +#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE + +/* + * S29WS256N NOR flash has 4 32KiB small sectors at the beginning and at the + * end. The rest of 32MiB is in 128KiB big sectors. U-Boot occupies the low + * 4 sectors, if we put environment next to it, we will have to occupy 128KiB + * for it. Putting it at the top of flash we use only 32KiB. + */ +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_ENV_SECT_SIZE) + +#if defined(CONFIG_CMD_MMC) + #define CONFIG_ENV_IS_IN_MMC 1 + #define CONFIG_ENV_OFFSET (768 * 1024) +#elif defined(CONFIG_CMD_NAND) + #define CONFIG_ENV_IS_IN_NAND 1 + #define CONFIG_ENV_OFFSET 0x100000 +#else + #define CONFIG_ENV_IS_IN_FLASH 1 +#endif + +/*----------------------------------------------------------------------- + * CFI FLASH driver setup + */ +#define CONFIG_SYS_FLASH_CFI 1/* Flash memory is CFI compliant */ +#define CONFIG_FLASH_CFI_DRIVER 1/* Use drivers/cfi_flash.c */ +/* A non-standard buffered write algorithm */ +#define CONFIG_FLASH_SPANSION_S29WS_N 1 +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1/* Use buffered writes (~10x faster) */ +#define CONFIG_SYS_FLASH_PROTECTION 1/* Use hardware sector protection */ + +/*----------------------------------------------------------------------- + * NAND FLASH driver setup + */ +#define NAND_MAX_CHIPS 1 +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE 0x40000000 +/* + * JFFS2 partitions + */ +#undef CONFIG_JFFS2_CMDLINE +#define CONFIG_JFFS2_DEV "nor0" + +#endif /* __CONFIG_H */ diff --git a/include/configs/mx35_3stack_mmc.h b/include/configs/mx35_3stack_mmc.h new file mode 100644 index 0000000000..c0c53fd5f0 --- /dev/null +++ b/include/configs/mx35_3stack_mmc.h @@ -0,0 +1,273 @@ +/* + * Copyright (C) 2007, Guennadi Liakhovetski + * + * (C) Copyright 2008-2010 Freescale Semiconductor, Inc. + * + * Configuration settings for the MX31ADS Freescale board. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include + + /* High Level Configuration Options */ +#define CONFIG_ARM1136 1 /* This is an arm1136 CPU core */ +#define CONFIG_MXC 1 +#define CONFIG_MX35 1 /* in a mx31 */ +#define CONFIG_MX35_HCLK_FREQ 24000000 /* RedBoot says 26MHz */ + +#define CONFIG_ARCH_CPU_INIT +#define CONFIG_ARCH_MMU + +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO + +#define CONFIG_SYS_64BIT_VSPRINTF + +#define BOARD_LATE_INIT +/* + * Disabled for now due to build problems under Debian and a significant increase + * in the final file size: 144260 vs. 109536 Bytes. + */ +#if 0 +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_FIT 1 +#define CONFIG_FIT_VERBOSE 1 +#endif + +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_REVISION_TAG 1 +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 + +/* + * Size of malloc() pool + */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 512 * 1024) +#define CONFIG_SYS_GBL_DATA_SIZE 128/* size in bytes reserved for initial data */ + +/* + * Hardware drivers + */ +#define CONFIG_HARD_I2C 1 +#define CONFIG_I2C_MXC 1 +#define CONFIG_SYS_I2C_PORT I2C_BASE_ADDR +#define CONFIG_SYS_I2C_SPEED 100000 +#define CONFIG_SYS_I2C_SLAVE 0xfe + +#define CONFIG_MX35_UART UART1_BASE_ADDR + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200} + +/*********************************************************** + * Command definition + ***********************************************************/ + +#include + +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_DNS +/*#define CONFIG_CMD_SPI*/ +/*#define CONFIG_CMD_DATE*/ +/*#define CONFIG_CMD_NAND*/ +#define CONFIG_CMD_ENV +#define CONFIG_CMD_MMC + +#define CONFIG_CMD_I2C +#define CONFIG_CMD_MII +#define CONFIG_CMD_NET +#define CONFIG_NET_RETRY_COUNT 100 + +#define CONFIG_BOOTDELAY 3 + +#define CONFIG_LOADADDR 0x80800000 /* loadaddr env var */ + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "ethprime=smc911x\0" \ + "uboot_addr=0xa0000000\0" \ + "uboot=u-boot.bin\0" \ + "kernel=uImage\0" \ + "nfsroot=/opt/eldk/arm\0" \ + "bootargs_base=setenv bootargs console=ttymxc0,115200\0"\ + "bootargs_nfs=setenv bootargs ${bootargs} root=/dev/nfs "\ + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0"\ + "bootcmd=run bootcmd_net\0" \ + "bootcmd_net=run bootargs_base bootargs_nfs; " \ + "tftpboot ${loadaddr} ${kernel}; bootm\0" \ + "prg_uboot=tftpboot ${loadaddr} ${uboot}; " \ + "protect off ${uboot_addr} 0xa003ffff; " \ + "erase ${uboot_addr} 0xa003ffff; " \ + "cp.b ${loadaddr} ${uboot_addr} ${filesize}; " \ + "setenv filesize; saveenv\0" + +/*Support LAN9217*/ +#define CONFIG_SMC911X 1 +#define CONFIG_SMC911X_16_BIT 1 +#define CONFIG_SMC911X_BASE CS5_BASE_ADDR + +#define CONFIG_HAS_ETH1 +#define CONFIG_NET_MULTI 1 +#define CONFIG_ETHPRIME +#define CONFIG_MXC_FEC +#define CONFIG_MII +#define CONFIG_DISCOVER_PHY + +#define CONFIG_FEC0_IOBASE FEC_BASE_ADDR +#define CONFIG_FEC0_PINMUX -1 +#define CONFIG_FEC0_PHY_ADDR 0x1F +#define CONFIG_FEC0_MIIBASE -1 + +/* + * The MX31ADS board seems to have a hardware "peculiarity" confirmed under + * U-Boot, RedBoot and Linux: the ethernet Rx signal is reaching the CS8900A + * controller inverted. The controller is capable of detecting and correcting + * this, but it needs 4 network packets for that. Which means, at startup, you + * will not receive answers to the first 4 packest, unless there have been some + * broadcasts on the network, or your board is on a hub. Reducing the ARP + * timeout from default 5 seconds to 200ms we speed up the initial TFTP + * transfer, should the user wish one, significantly. + */ +#define CONFIG_ARP_TIMEOUT 200UL + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_PROMPT "MX35 U-Boot > " +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ + +#define CONFIG_SYS_MEMTEST_START 0 /* memtest works on */ +#define CONFIG_SYS_MEMTEST_END 0x10000 + +#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */ + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +#define CONFIG_SYS_HZ 1000 + +#define CONFIG_CMDLINE_EDITING 1 + +/*----------------------------------------------------------------------- + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */ + +/*----------------------------------------------------------------------- + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM_1 CSD0_BASE_ADDR +#define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024) +#define iomem_valid_addr(addr, size) \ + (addr >= PHYS_SDRAM_1 && addr <= (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE)) + +/* + * MMC Configs + * */ +#ifdef CONFIG_CMD_MMC + #define CONFIG_MMC 1 + #define CONFIG_GENERIC_MMC + #define CONFIG_IMX_MMC + #define CONFIG_SYS_FSL_ESDHC_NUM 2 + #define CONFIG_SYS_FSL_ESDHC_ADDR 0 + #define CONFIG_SYS_MMC_ENV_DEV 0 + #define CONFIG_DOS_PARTITION 1 + #define CONFIG_CMD_FAT 1 +#endif + +#define CONFIG_FLASH_HEADER 1 +#define CONFIG_FLASH_HEADER_OFFSET 0x400 +#define CONFIG_FLASH_HEADER_BARKER 0xB1 + +#define CONFIG_DOS_PARTITION 1 +#define CONFIG_CMD_FAT 1 + +/*----------------------------------------------------------------------- + * FLASH and environment organization + */ +#define CONFIG_SYS_FLASH_BASE CS0_BASE_ADDR +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */ +/* Monitor at beginning of flash */ +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE +#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 256KiB */ + +#define CONFIG_ENV_SECT_SIZE (128 * 1024) +#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE + +/* Address and size of Redundant Environment Sector */ +#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) +#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE + +/* + * S29WS256N NOR flash has 4 32KiB small sectors at the beginning and at the + * end. The rest of 32MiB is in 128KiB big sectors. U-Boot occupies the low + * 4 sectors, if we put environment next to it, we will have to occupy 128KiB + * for it. Putting it at the top of flash we use only 32KiB. + */ +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_ENV_SECT_SIZE) + +#if defined(CONFIG_CMD_MMC) + #define CONFIG_ENV_IS_IN_MMC 1 + #define CONFIG_ENV_OFFSET (768 * 1024) +#elif defined(CONFIG_CMD_NAND) + #define CONFIG_ENV_IS_IN_NAND 1 + #define CONFIG_ENV_OFFSET 0x100000 +#else + #define CONFIG_ENV_IS_IN_FLASH 1 +#endif + +/*----------------------------------------------------------------------- + * CFI FLASH driver setup + */ +#define CONFIG_SYS_FLASH_CFI 1/* Flash memory is CFI compliant */ +#define CONFIG_FLASH_CFI_DRIVER 1/* Use drivers/cfi_flash.c */ +/* A non-standard buffered write algorithm */ +#define CONFIG_FLASH_SPANSION_S29WS_N 1 +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1/* Use buffered writes (~10x faster) */ +#define CONFIG_SYS_FLASH_PROTECTION 1/* Use hardware sector protection */ + +/*----------------------------------------------------------------------- + * NAND FLASH driver setup + */ +#define NAND_MAX_CHIPS 1 +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE 0x40000000 +/* + * JFFS2 partitions + */ +#undef CONFIG_JFFS2_CMDLINE +#define CONFIG_JFFS2_DEV "nor0" + +#endif /* __CONFIG_H */ diff --git a/include/configs/mx50_arm2.h b/include/configs/mx50_arm2.h new file mode 100644 index 0000000000..c7f8fafc45 --- /dev/null +++ b/include/configs/mx50_arm2.h @@ -0,0 +1,284 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. + * + * Configuration settings for the MX50-ARM2 Freescale board. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include + + /* High Level Configuration Options */ +#define CONFIG_MXC +#define CONFIG_MX50 +#define CONFIG_MX50_ARM2 +#define CONFIG_FLASH_HEADER +#define CONFIG_FLASH_HEADER_OFFSET 0x400 + +#define CONFIG_SKIP_RELOCATE_UBOOT + +#define CONFIG_ARCH_CPU_INIT +#define CONFIG_ARCH_MMU + +#define CONFIG_MX50_HCLK_FREQ 24000000 +#define CONFIG_SYS_PLL2_FREQ 400 +#define CONFIG_SYS_AHB_PODF 2 +#define CONFIG_SYS_AXIA_PODF 0 +#define CONFIG_SYS_AXIB_PODF 1 + +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO + +#define CONFIG_SYS_64BIT_VSPRINTF + +#define BOARD_LATE_INIT +/* + * Disabled for now due to build problems under Debian and a significant + * increase in the final file size: 144260 vs. 109536 Bytes. + */ + +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_REVISION_TAG 1 +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 + +/* + * Size of malloc() pool + */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024) +/* size in bytes reserved for initial data */ +#define CONFIG_SYS_GBL_DATA_SIZE 128 + +/* + * Hardware drivers + */ +#define CONFIG_MX50_UART 1 +#define CONFIG_MX50_UART1 1 + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200} + +/*********************************************************** + * Command definition + ***********************************************************/ + +#include + +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_MII +#define CONFIG_CMD_NET +#define CONFIG_NET_RETRY_COUNT 100 +#define CONFIG_NET_MULTI 1 +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_DNS + +#define CONFIG_CMD_MMC +#define CONFIG_CMD_ENV + +/*#define CONFIG_CMD */ +#define CONFIG_REF_CLK_FREQ CONFIG_MX50_HCLK_FREQ + +#undef CONFIG_CMD_IMLS + +#define CONFIG_BOOTDELAY 3 + +#define CONFIG_PRIME "FEC0" + +#define CONFIG_LOADADDR 0x70800000 /* loadaddr env var */ +#define CONFIG_RD_LOADADDR (CONFIG_LOADADDR + 0x300000) + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "ethprime=FEC0\0" \ + "uboot=u-boot.bin\0" \ + "kernel=uImage\0" \ + "nfsroot=/opt/eldk/arm\0" \ + "bootargs_base=setenv bootargs console=ttymxc0,115200\0"\ + "bootargs_nfs=setenv bootargs ${bootargs} root=/dev/nfs "\ + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0"\ + "bootcmd_net=run bootargs_base bootargs_nfs; " \ + "tftpboot ${loadaddr} ${kernel}; bootm\0" \ + "bootargs_mmc=setenv bootargs ${bootargs} ip=dhcp " \ + "root=/dev/mmcblk0p2 rootwait\0" \ + "bootcmd_mmc=run bootargs_base bootargs_mmc; bootm\0" \ + "bootcmd=run bootcmd_net\0" \ + + +#define CONFIG_ARP_TIMEOUT 200UL + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_PROMPT "ARM2 U-Boot > " +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ + +#define CONFIG_SYS_MEMTEST_START 0 /* memtest works on */ +#define CONFIG_SYS_MEMTEST_END 0x10000 + +#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */ + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +#define CONFIG_SYS_HZ 1000 + +#define CONFIG_CMDLINE_EDITING 1 + +#define CONFIG_FEC0_IOBASE FEC_BASE_ADDR +#define CONFIG_FEC0_PINMUX -1 +#define CONFIG_FEC0_PHY_ADDR -1 +#define CONFIG_FEC0_MIIBASE -1 + +#define CONFIG_GET_FEC_MAC_ADDR_FROM_IIM + +#define CONFIG_MXC_FEC +#define CONFIG_MII +#define CONFIG_MII_GASKET +#define CONFIG_DISCOVER_PHY + +/* +#define CONFIG_SPLASH_SCREEN +*/ + +/* + * SPLASH SCREEN Configs + */ +#ifdef CONFIG_SPLASH_SCREEN + #define CONFIG_LCD + #undef LCD_TEST_PATTERN + #define CONFIG_FB_BASE (TEXT_BASE + 0x300000) + #define CONFIG_SYS_CONSOLE_IS_IN_ENV 1 + /* #define CONFIG_SPLASH_IS_IN_MMC 1 */ + #define LCD_BPP LCD_MONOCHROME + /* #define CONFIG_SPLASH_SCREEN_ALIGN 1 */ + + #define CONFIG_MXC_EPDC 1 + + #define CONFIG_WORKING_BUF_ADDR (TEXT_BASE + 0x100000) + #define CONFIG_WAVEFORM_BUF_ADDR (TEXT_BASE + 0x200000) + #define CONFIG_WAVEFORM_FILE_OFFSET 0x100000 + #define CONFIG_WAVEFORM_FILE_SIZE 0xB4000 + #define CONFIG_WAVEFORM_FILE_IN_MMC +#endif + +#ifdef CONFIG_SPLASH_IS_IN_MMC + #define CONFIG_SPLASH_IMG_OFFSET 0x4c000 + #define CONFIG_SPLASH_IMG_SIZE 0x19000 +#endif + +/* + * I2C Configs + */ +#define CONFIG_CMD_I2C 1 +#define CONFIG_HARD_I2C 1 +#define CONFIG_I2C_MXC 1 +#define CONFIG_SYS_I2C_PORT I2C2_BASE_ADDR +#define CONFIG_SYS_I2C_SPEED 100000 +#define CONFIG_SYS_I2C_SLAVE 0xfe + + +/* + * SPI Configs + */ +#define CONFIG_FSL_SF 1 +#define CONFIG_CMD_SPI +#define CONFIG_CMD_SF +#define CONFIG_SPI_FLASH_IMX_ATMEL 1 +#define CONFIG_SPI_FLASH_CS 1 +#define CONFIG_IMX_CSPI +#define IMX_CSPI_VER_0_7 1 +#define MAX_SPI_BYTES (8 * 4) +#define CONFIG_IMX_SPI_PMIC +#define CONFIG_IMX_SPI_PMIC_CS 0 + +/* + * MMC Configs + */ +#ifdef CONFIG_CMD_MMC + #define CONFIG_MMC 1 + #define CONFIG_GENERIC_MMC + #define CONFIG_IMX_MMC + #define CONFIG_SYS_FSL_ESDHC_NUM 3 + #define CONFIG_SYS_FSL_ESDHC_ADDR 0 + #define CONFIG_SYS_MMC_ENV_DEV 0 + #define CONFIG_DOS_PARTITION 1 + #define CONFIG_CMD_FAT 1 + #define CONFIG_CMD_EXT2 1 + + /* detect whether ESDHC1, ESDHC2, or ESDHC3 is boot device */ + #define CONFIG_DYNAMIC_MMC_DEVNO + + #define CONFIG_BOOT_PARTITION_ACCESS + #define CONFIG_EMMC_DDR_MODE + + /* Indicate to esdhc driver which ports support 8-bit data */ + #define CONFIG_MMC_8BIT_PORTS 0x6 /* ports 1 and 2 */ + +#endif +/*----------------------------------------------------------------------- + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */ + +/*----------------------------------------------------------------------- + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM_1 CSD0_BASE_ADDR +#define PHYS_SDRAM_1_SIZE (256 * 1024 * 1024) +#define iomem_valid_addr(addr, size) \ + (addr >= PHYS_SDRAM_1 && addr <= (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE)) + +/*----------------------------------------------------------------------- + * FLASH and environment organization + */ +#define CONFIG_SYS_NO_FLASH + +/* Monitor at beginning of flash */ +#define CONFIG_FSL_ENV_IN_MMC + +#define CONFIG_ENV_SECT_SIZE (128 * 1024) +#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE + +#if defined(CONFIG_FSL_ENV_IN_NAND) + #define CONFIG_ENV_IS_IN_NAND 1 + #define CONFIG_ENV_OFFSET 0x100000 +#elif defined(CONFIG_FSL_ENV_IN_MMC) + #define CONFIG_ENV_IS_IN_MMC 1 + #define CONFIG_ENV_OFFSET (768 * 1024) +#elif defined(CONFIG_FSL_ENV_IN_SF) + #define CONFIG_ENV_IS_IN_SPI_FLASH 1 + #define CONFIG_ENV_SPI_CS 1 + #define CONFIG_ENV_OFFSET (768 * 1024) +#else + #define CONFIG_ENV_IS_NOWHERE 1 +#endif +#endif /* __CONFIG_H */ diff --git a/include/configs/mx50_arm2_iram.h b/include/configs/mx50_arm2_iram.h new file mode 100644 index 0000000000..0e7f4b4b6a --- /dev/null +++ b/include/configs/mx50_arm2_iram.h @@ -0,0 +1,194 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. + * + * Configuration settings for the MX50-ARM2 Freescale board. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include + + /* High Level Configuration Options */ +#define CONFIG_ARMV7 1 /* This is armv7 Cortex-A8 CPU core */ + +#define CONFIG_MXC +#define CONFIG_MX50 +#define CONFIG_MX50_ARM2 +#define CONFIG_FLASH_HEADER +#define CONFIG_FLASH_HEADER_OFFSET 0x400 + +#define CONFIG_SKIP_RELOCATE_UBOOT + +/* +#define CONFIG_ARCH_CPU_INIT +#define CONFIG_ARCH_MMU +*/ + +#define CONFIG_MX50_HCLK_FREQ 24000000 +#define CONFIG_SYS_PLL2_FREQ 600 +#define CONFIG_SYS_AHB_PODF 4 +#define CONFIG_SYS_AXIA_PODF 1 +#define CONFIG_SYS_AXIB_PODF 2 +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO + +#define BOARD_LATE_INIT + +/* + * Disabled for now due to build problems under Debian and a significant + * increase in the final file size: 144260 vs. 109536 Bytes. + */ + +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_REVISION_TAG 1 +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 + +/* + * Size of malloc() pool + */ +#define CONFIG_SYS_MALLOC_LEN (3 * 1024) +/* size in bytes reserved for initial data */ +#define CONFIG_SYS_GBL_DATA_SIZE 128 + +/* + * Hardware drivers + */ +#define CONFIG_MX50_UART 1 +#define CONFIG_MX50_UART1 1 + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200} + +/*********************************************************** + * Command definition + ***********************************************************/ + +#define CONFIG_CMD_BDI /* bdinfo */ +#define CONFIG_CMD_BOOTD /* bootd */ +#define CONFIG_CMD_CONSOLE /* coninfo */ +#define CONFIG_CMD_RUN /* run command in env variable */ + +/* + * SPI Configs + * */ + +/* + * MMC Configs + * */ +/* + * Eth Configs + */ + + +/* Enable below configure when supporting nand */ +#define CONFIG_CMD_ENV + +#define CONFIG_REF_CLK_FREQ CONFIG_MX50_HCLK_FREQ + +#undef CONFIG_CMD_IMLS + +#define CONFIG_BOOTDELAY 3 + +#define CONFIG_PRIME "FEC0" + +#define CONFIG_LOADADDR 0x70800000 /* loadaddr env var */ +#define CONFIG_RD_LOADADDR (CONFIG_LOADADDR + 0x300000) + +#define CONFIG_BOOTARGS "console=ttymxc0,115200 "\ + "rdinit=/linuxrc" + +#define CONFIG_BOOTCOMMAND "bootm" +#define CONFIG_ENV_IS_EMBEDDED +/* + * The MX51 3stack board seems to have a hardware "peculiarity" confirmed under + * U-Boot, RedBoot and Linux: the ethernet Rx signal is reaching the CS8900A + * controller inverted. The controller is capable of detecting and correcting + * this, but it needs 4 network packets for that. Which means, at startup, you + * will not receive answers to the first 4 packest, unless there have been some + * broadcasts on the network, or your board is on a hub. Reducing the ARP + * timeout from default 5 seconds to 200ms we speed up the initial TFTP + * transfer, should the user wish one, significantly. + */ +#define CONFIG_ARP_TIMEOUT 200UL + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_PROMPT "ARM2 U-Boot > " +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ + +#define CONFIG_SYS_MEMTEST_START 0 /* memtest works on */ +#define CONFIG_SYS_MEMTEST_END 0x10000 + +#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */ + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +#define CONFIG_SYS_HZ 1000 + +#define CONFIG_CMDLINE_EDITING 1 + +/*----------------------------------------------------------------------- + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (6 * 1024) /* regular stack */ + +/*----------------------------------------------------------------------- + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM_1 CSD0_BASE_ADDR +/* TO1 boards */ +/* #define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024) */ +#define PHYS_SDRAM_1_SIZE (512 * 1024 * 1024) +#define iomem_valid_addr(addr, size) \ + (addr >= PHYS_SDRAM_1 && addr <= (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE)) + +/*----------------------------------------------------------------------- + * FLASH and environment organization + */ +#define CONFIG_SYS_NO_FLASH + +/* Monitor at beginning of flash */ +/* #define CONFIG_FSL_ENV_IN_SF +*/ +/* #define CONFIG_FSL_ENV_IN_MMC */ + +#define CONFIG_ENV_SECT_SIZE (1 * 1024) +#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE +#define CONFIG_ENV_IS_NOWHERE + +/* + * JFFS2 partitions + */ +/* +#undef CONFIG_JFFS2_CMDLINE +#define CONFIG_JFFS2_DEV "nand0" +*/ +#endif /* __CONFIG_H */ diff --git a/include/configs/mx50_arm2_lpddr2.h b/include/configs/mx50_arm2_lpddr2.h new file mode 100644 index 0000000000..6efe6a6c08 --- /dev/null +++ b/include/configs/mx50_arm2_lpddr2.h @@ -0,0 +1,286 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. + * + * Configuration settings for the MX50-ARM2 Freescale board. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include + + /* High Level Configuration Options */ +#define CONFIG_MXC +#define CONFIG_MX50 +#define CONFIG_MX50_ARM2 +#define CONFIG_LPDDR2 +#define CONFIG_FLASH_HEADER +#define CONFIG_FLASH_HEADER_OFFSET 0x400 + +#define CONFIG_SKIP_RELOCATE_UBOOT + +#define CONFIG_ARCH_CPU_INIT +#define CONFIG_ARCH_MMU + +#define CONFIG_MX50_HCLK_FREQ 24000000 +#define CONFIG_SYS_PLL2_FREQ 400 +#define CONFIG_SYS_AHB_PODF 2 +#define CONFIG_SYS_AXIA_PODF 0 +#define CONFIG_SYS_AXIB_PODF 1 + +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO + +#define CONFIG_SYS_64BIT_VSPRINTF + +#define BOARD_LATE_INIT +/* + * Disabled for now due to build problems under Debian and a significant + * increase in the final file size: 144260 vs. 109536 Bytes. + */ + +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_REVISION_TAG 1 +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 + +/* + * Size of malloc() pool + */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024) +/* size in bytes reserved for initial data */ +#define CONFIG_SYS_GBL_DATA_SIZE 128 + +/* + * Hardware drivers + */ +#define CONFIG_MX50_UART 1 +#define CONFIG_MX50_UART1 1 + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200} + +/*********************************************************** + * Command definition + ***********************************************************/ + +#include + +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_MII +#define CONFIG_CMD_NET +#define CONFIG_NET_RETRY_COUNT 100 +#define CONFIG_NET_MULTI 1 +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_DNS + +#define CONFIG_CMD_MMC +#define CONFIG_CMD_ENV + +/*#define CONFIG_CMD */ +#define CONFIG_REF_CLK_FREQ CONFIG_MX50_HCLK_FREQ + +#undef CONFIG_CMD_IMLS + +#define CONFIG_BOOTDELAY 3 + +#define CONFIG_PRIME "FEC0" + +#define CONFIG_LOADADDR 0x70800000 /* loadaddr env var */ +#define CONFIG_RD_LOADADDR (CONFIG_LOADADDR + 0x300000) + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "ethprime=FEC0\0" \ + "uboot=u-boot.bin\0" \ + "kernel=uImage\0" \ + "nfsroot=/opt/eldk/arm\0" \ + "bootargs_base=setenv bootargs console=ttymxc0,115200\0"\ + "bootargs_nfs=setenv bootargs ${bootargs} root=/dev/nfs "\ + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0"\ + "bootcmd_net=run bootargs_base bootargs_nfs; " \ + "tftpboot ${loadaddr} ${kernel}; bootm\0" \ + "bootargs_mmc=setenv bootargs ${bootargs} ip=dhcp " \ + "root=/dev/mmcblk0p2 rootwait\0" \ + "bootcmd_mmc=run bootargs_base bootargs_mmc; bootm\0" \ + "bootcmd=run bootcmd_net\0" \ + + +#define CONFIG_ARP_TIMEOUT 200UL + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_PROMPT "ARM2 U-Boot > " +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ + +#define CONFIG_SYS_MEMTEST_START 0 /* memtest works on */ +#define CONFIG_SYS_MEMTEST_END 0x10000 + +#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */ + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +#define CONFIG_SYS_HZ 1000 + +#define CONFIG_CMDLINE_EDITING 1 + +#define CONFIG_FEC0_IOBASE FEC_BASE_ADDR +#define CONFIG_FEC0_PINMUX -1 +#define CONFIG_FEC0_PHY_ADDR -1 +#define CONFIG_FEC0_MIIBASE -1 + +#define CONFIG_GET_FEC_MAC_ADDR_FROM_IIM + +#define CONFIG_MXC_FEC +#define CONFIG_MII +#define CONFIG_MII_GASKET +#define CONFIG_DISCOVER_PHY + +/* +#define CONFIG_SPLASH_SCREEN +*/ + +/* + * SPLASH SCREEN Configs + */ +#ifdef CONFIG_SPLASH_SCREEN + #define CONFIG_LCD + #undef LCD_TEST_PATTERN + #define CONFIG_FB_BASE (TEXT_BASE + 0x300000) + #define CONFIG_SYS_CONSOLE_IS_IN_ENV 1 + /* #define CONFIG_SPLASH_IS_IN_MMC 1 */ + #define LCD_BPP LCD_MONOCHROME + /* #define CONFIG_SPLASH_SCREEN_ALIGN 1 */ + + #define CONFIG_MXC_EPDC 1 + + #define CONFIG_WORKING_BUF_ADDR (TEXT_BASE + 0x100000) + #define CONFIG_WAVEFORM_BUF_ADDR (TEXT_BASE + 0x200000) + #define CONFIG_WAVEFORM_FILE_OFFSET 0x100000 + #define CONFIG_WAVEFORM_FILE_SIZE 0xB4000 + #define CONFIG_WAVEFORM_FILE_IN_MMC +#endif + +#ifdef CONFIG_SPLASH_IS_IN_MMC + #define CONFIG_SPLASH_IMG_OFFSET 0x4c000 + #define CONFIG_SPLASH_IMG_SIZE 0x19000 +#endif + +/* + * I2C Configs + */ +#define CONFIG_CMD_I2C 1 +#define CONFIG_HARD_I2C 1 +#define CONFIG_I2C_MXC 1 +#define CONFIG_SYS_I2C_PORT I2C2_BASE_ADDR +#define CONFIG_SYS_I2C_SPEED 100000 +#define CONFIG_SYS_I2C_SLAVE 0xfe + + +/* + * SPI Configs + */ +#define CONFIG_FSL_SF 1 +#define CONFIG_CMD_SPI +#define CONFIG_CMD_SF +#define CONFIG_SPI_FLASH_IMX_ATMEL 1 +#define CONFIG_SPI_FLASH_CS 1 +#define CONFIG_IMX_CSPI +#define IMX_CSPI_VER_0_7 1 +#define MAX_SPI_BYTES (8 * 4) +#define CONFIG_IMX_SPI_PMIC +#define CONFIG_IMX_SPI_PMIC_CS 0 + +/* + * MMC Configs + */ +#ifdef CONFIG_CMD_MMC + #define CONFIG_MMC 1 + #define CONFIG_GENERIC_MMC + #define CONFIG_IMX_MMC + #define CONFIG_SYS_FSL_ESDHC_NUM 3 + #define CONFIG_SYS_FSL_ESDHC_ADDR 0 + #define CONFIG_SYS_MMC_ENV_DEV 0 + #define CONFIG_DOS_PARTITION 1 + #define CONFIG_CMD_FAT 1 + #define CONFIG_CMD_EXT2 1 + + /* detect whether ESDHC1, ESDHC2, or ESDHC3 is boot device */ + #define CONFIG_DYNAMIC_MMC_DEVNO + + #define CONFIG_BOOT_PARTITION_ACCESS + #define CONFIG_EMMC_DDR_MODE + + /* Indicate to esdhc driver which ports support 8-bit data */ + #define CONFIG_MMC_8BIT_PORTS 0x6 /* ports 1 and 2 */ + + +#endif +/*----------------------------------------------------------------------- + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */ + +/*----------------------------------------------------------------------- + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 2 +#define PHYS_SDRAM_1 CSD0_BASE_ADDR +#define PHYS_SDRAM_1_SIZE (256 * 1024 * 1024) +#define iomem_valid_addr(addr, size) \ + (addr >= PHYS_SDRAM_1 && addr <= (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE)) + +/*----------------------------------------------------------------------- + * FLASH and environment organization + */ +#define CONFIG_SYS_NO_FLASH + +/* Monitor at beginning of flash */ +#define CONFIG_FSL_ENV_IN_MMC + +#define CONFIG_ENV_SECT_SIZE (128 * 1024) +#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE + +#if defined(CONFIG_FSL_ENV_IN_NAND) + #define CONFIG_ENV_IS_IN_NAND 1 + #define CONFIG_ENV_OFFSET 0x100000 +#elif defined(CONFIG_FSL_ENV_IN_MMC) + #define CONFIG_ENV_IS_IN_MMC 1 + #define CONFIG_ENV_OFFSET (768 * 1024) +#elif defined(CONFIG_FSL_ENV_IN_SF) + #define CONFIG_ENV_IS_IN_SPI_FLASH 1 + #define CONFIG_ENV_SPI_CS 1 + #define CONFIG_ENV_OFFSET (768 * 1024) +#else + #define CONFIG_ENV_IS_NOWHERE 1 +#endif +#endif /* __CONFIG_H */ diff --git a/include/configs/mx50_arm2_mfg.h b/include/configs/mx50_arm2_mfg.h new file mode 100644 index 0000000000..b29c7a9552 --- /dev/null +++ b/include/configs/mx50_arm2_mfg.h @@ -0,0 +1,253 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. + * + * Configuration settings for the MX50-ARM2 Freescale board. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include + + /* High Level Configuration Options */ +#define CONFIG_MFG +#define CONFIG_MXC +#define CONFIG_MX50 +#define CONFIG_MX50_ARM2 +#define CONFIG_FLASH_HEADER +#define CONFIG_FLASH_HEADER_OFFSET 0x400 + +#define CONFIG_SKIP_RELOCATE_UBOOT + +#define CONFIG_ARCH_CPU_INIT +#define CONFIG_ARCH_MMU + +#define CONFIG_MX50_HCLK_FREQ 24000000 +#define CONFIG_SYS_PLL2_FREQ 400 +#define CONFIG_SYS_AHB_PODF 2 +#define CONFIG_SYS_AXIA_PODF 0 +#define CONFIG_SYS_AXIB_PODF 1 + +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO + +#define CONFIG_SYS_64BIT_VSPRINTF + +#define BOARD_LATE_INIT +/* + * Disabled for now due to build problems under Debian and a significant + * increase in the final file size: 144260 vs. 109536 Bytes. + */ + +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_REVISION_TAG 1 +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 + +/* + * Size of malloc() pool + */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024) +/* size in bytes reserved for initial data */ +#define CONFIG_SYS_GBL_DATA_SIZE 128 + +/* + * Hardware drivers + */ +#define CONFIG_MX50_UART 1 +#define CONFIG_MX50_UART1 1 + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200} + +/*********************************************************** + * Command definition + ***********************************************************/ + +#include + +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_MII +#define CONFIG_CMD_NET +#define CONFIG_NET_RETRY_COUNT 100 +#define CONFIG_NET_MULTI 1 +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_DNS + +/* #define CONFIG_CMD_MMC */ +/* #define CONFIG_CMD_ENV */ + +/*#define CONFIG_CMD */ +#define CONFIG_REF_CLK_FREQ CONFIG_MX50_HCLK_FREQ + +#undef CONFIG_CMD_IMLS + +#define CONFIG_BOOTDELAY 0 + +#define CONFIG_PRIME "FEC0" + +#define CONFIG_LOADADDR 0x70800000 /* loadaddr env var */ +#define CONFIG_RD_LOADADDR (CONFIG_LOADADDR + 0x300000) + +#define CONFIG_BOOTARGS "console=ttymxc0,115200 "\ + "rdinit=/linuxrc" +#define CONFIG_BOOTCOMMAND "bootm 0x70800000 0x70B00000" +#define CONFIG_ENV_IS_EMBEDDED +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "ethprime=FEC0\0" \ + "uboot=u-boot.bin\0" \ + "kernel=uImage\0" \ + "nfsroot=/opt/eldk/arm\0" \ + "bootargs_base=setenv bootargs console=ttymxc0,115200\0"\ + "bootargs_nfs=setenv bootargs ${bootargs} root=/dev/nfs "\ + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0"\ + "bootcmd_net=run bootargs_base bootargs_nfs; " \ + "tftpboot ${loadaddr} ${kernel}; bootm\0" \ + "bootargs_mmc=setenv bootargs ${bootargs} ip=dhcp " \ + "root=/dev/mmcblk0p2 rootwait\0" \ + "bootcmd_mmc=run bootargs_base bootargs_mmc; bootm\0" \ + "bootcmd=run bootcmd_net\0" \ + + +#define CONFIG_ARP_TIMEOUT 200UL + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_PROMPT "ARM2 MFG U-Boot > " +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ + +#define CONFIG_SYS_MEMTEST_START 0 /* memtest works on */ +#define CONFIG_SYS_MEMTEST_END 0x10000 + +#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */ + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +#define CONFIG_SYS_HZ 1000 + +#define CONFIG_CMDLINE_EDITING 1 + +#define CONFIG_FEC0_IOBASE FEC_BASE_ADDR +#define CONFIG_FEC0_PINMUX -1 +#define CONFIG_FEC0_PHY_ADDR -1 +#define CONFIG_FEC0_MIIBASE -1 + +#define CONFIG_MXC_FEC +#define CONFIG_MII +#define CONFIG_MII_GASKET +#define CONFIG_DISCOVER_PHY + +/* + * I2C Configs + */ +#define CONFIG_CMD_I2C 1 +#define CONFIG_HARD_I2C 1 +#define CONFIG_I2C_MXC 1 +#define CONFIG_SYS_I2C_PORT I2C2_BASE_ADDR +#define CONFIG_SYS_I2C_SPEED 100000 +#define CONFIG_SYS_I2C_SLAVE 0xfe + + +/* + * SPI Configs + */ +#define CONFIG_FSL_SF 1 +#define CONFIG_CMD_SPI +#define CONFIG_CMD_SF +#define CONFIG_SPI_FLASH_IMX_ATMEL 1 +#define CONFIG_SPI_FLASH_CS 1 +#define CONFIG_IMX_CSPI +#define IMX_CSPI_VER_0_7 1 +#define MAX_SPI_BYTES (8 * 4) +#define CONFIG_IMX_SPI_PMIC +#define CONFIG_IMX_SPI_PMIC_CS 0 + +/* + * MMC Configs + */ +#ifdef CONFIG_CMD_MMC + #define CONFIG_MMC 1 + #define CONFIG_GENERIC_MMC + #define CONFIG_IMX_MMC + #define CONFIG_SYS_FSL_ESDHC_NUM 3 + #define CONFIG_SYS_FSL_ESDHC_ADDR 0 + #define CONFIG_SYS_MMC_ENV_DEV 0 + #define CONFIG_DOS_PARTITION 1 + #define CONFIG_CMD_FAT 1 + #define CONFIG_CMD_EXT2 1 + + /* detect whether ESDHC1 or ESDHC3 is boot device */ + #define CONFIG_DYNAMIC_MMC_DEVNO + + #define CONFIG_BOOT_PARTITION_ACCESS + +#endif +/*----------------------------------------------------------------------- + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */ + +/*----------------------------------------------------------------------- + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM_1 CSD0_BASE_ADDR +#define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024) +#define iomem_valid_addr(addr, size) \ + (addr >= PHYS_SDRAM_1 && addr <= (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE)) + +/*----------------------------------------------------------------------- + * FLASH and environment organization + */ +#define CONFIG_SYS_NO_FLASH + +/* Monitor at beginning of flash */ +/* #define CONFIG_FSL_ENV_IN_MMC */ + +#define CONFIG_ENV_SECT_SIZE (128 * 1024) +#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE + +#if defined(CONFIG_FSL_ENV_IN_NAND) + #define CONFIG_ENV_IS_IN_NAND 1 + #define CONFIG_ENV_OFFSET 0x100000 +#elif defined(CONFIG_FSL_ENV_IN_MMC) + #define CONFIG_ENV_IS_IN_MMC 1 + #define CONFIG_ENV_OFFSET (768 * 1024) +#elif defined(CONFIG_FSL_ENV_IN_SF) + #define CONFIG_ENV_IS_IN_SPI_FLASH 1 + #define CONFIG_ENV_SPI_CS 1 + #define CONFIG_ENV_OFFSET (768 * 1024) +#else + #define CONFIG_ENV_IS_NOWHERE 1 +#endif +#endif /* __CONFIG_H */ diff --git a/include/configs/mx51_3stack.h b/include/configs/mx51_3stack.h new file mode 100644 index 0000000000..e628ede5b5 --- /dev/null +++ b/include/configs/mx51_3stack.h @@ -0,0 +1,267 @@ +/* + * Copyright (C) 2007, Guennadi Liakhovetski + * + * (C) Copyright 2009-2010 Freescale Semiconductor, Inc. + * + * Configuration settings for the MX51-3Stack Freescale board. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include + + /* High Level Configuration Options */ +#define CONFIG_ARMV7 1 /* This is armv7 Cortex-A8 CPU core */ +#define CONFIG_SYS_APCS_GNU + +#define CONFIG_MXC 1 +#define CONFIG_MX51_3DS 1 /* in a mx51 */ +#define CONFIG_FLASH_HEADER 1 +#define CONFIG_FLASH_HEADER_OFFSET 0x400 +#define CONFIG_FLASH_HEADER_BARKER 0xB1 + +#define CONFIG_SKIP_RELOCATE_UBOOT + +#define CONFIG_MX51_HCLK_FREQ 24000000 /* RedBoot says 26MHz */ + +#define CONFIG_ARCH_CPU_INIT +#define CONFIG_ARCH_MMU + +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO + +#define CONFIG_SYS_64BIT_VSPRINTF + +#define BOARD_LATE_INIT +/* + * Disabled for now due to build problems under Debian and a significant + * increase in the final file size: 144260 vs. 109536 Bytes. + */ + +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_REVISION_TAG 1 +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 + +/* + * Size of malloc() pool + */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024) +/* size in bytes reserved for initial data */ +#define CONFIG_SYS_GBL_DATA_SIZE 128 + +/* + * Hardware drivers + */ +#define CONFIG_MX51_UART 1 +#define CONFIG_MX51_UART1 1 + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200} + +/*********************************************************** + * Command definition + ***********************************************************/ + +#include + +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_DNS +/* Enable below configure when supporting nand */ +#define CONFIG_CMD_NAND +#define CONFIG_MXC_NAND +#define CONFIG_CMD_ENV +#define CMD_SAVEENV +#undef CONFIG_CMD_IMLS +#define CONFIG_CMD_MII +#define CONFIG_CMD_NET +#define CONFIG_CMD_MMC +#define CONFIG_CMD_IIM + +/* + * FUSE Configs + * */ +#ifdef CONFIG_CMD_IIM + #define CONFIG_IMX_IIM + #define IMX_IIM_BASE IIM_BASE_ADDR + #define CONFIG_IIM_MAC_BANK 1 + #define CONFIG_IIM_MAC_ROW 9 +#endif + +/* + * MMC Configs + */ +#ifdef CONFIG_CMD_MMC + #define CONFIG_MMC 1 + #define CONFIG_GENERIC_MMC + #define CONFIG_IMX_MMC + #define CONFIG_SYS_FSL_ESDHC_ADDR 0 + #define CONFIG_SYS_MMC_ENV_DEV 0 + #define CONFIG_DOS_PARTITION 1 + #define CONFIG_CMD_FAT 1 + #define CONFIG_SYS_FSL_ESDHC_NUM 1 +#endif + +/* + * I2C Configs + */ +#define CONFIG_CMD_I2C 1 +#define CONFIG_HARD_I2C 1 +#define CONFIG_I2C_MXC 1 +#define CONFIG_SYS_I2C_PORT I2C2_BASE_ADDR +#define CONFIG_SYS_I2C_SPEED 400000 +#define CONFIG_SYS_I2C_SLAVE 0xfe + +/* + * Eth Configs + */ +#define CONFIG_HAS_ETH1 +#define CONFIG_ETHPRIME +#define CONFIG_NET_RETRY_COUNT 100 +#define CONFIG_NET_MULTI +#define CONFIG_MXC_FEC +#define CONFIG_MII +#define CONFIG_DISCOVER_PHY + +#define CONFIG_FEC0_IOBASE FEC_BASE_ADDR +#define CONFIG_FEC0_PINMUX -1 +#define CONFIG_FEC0_PHY_ADDR 0x1F +#define CONFIG_FEC0_MIIBASE -1 + + +#define CONFIG_BOOTDELAY 3 + +#define CONFIG_LOADADDR 0x90800000 /* loadaddr env var */ + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "ethprime=smc911x\0" \ + "uboot_addr=0xa0000000\0" \ + "uboot=u-boot.bin\0" \ + "kernel=uImage\0" \ + "nfsroot=/opt/eldk/arm\0" \ + "bootargs_base=setenv bootargs console=ttymxc0,115200\0"\ + "bootargs_nfs=setenv bootargs ${bootargs} root=/dev/nfs "\ + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0"\ + "bootcmd=run bootcmd_net\0" \ + "bootcmd_net=run bootargs_base bootargs_nfs; " \ + "tftpboot ${loadaddr} ${kernel}; bootm\0" \ + "prg_uboot=tftpboot ${loadaddr} ${uboot}; " \ + "protect off ${uboot_addr} 0xa003ffff; " \ + "erase ${uboot_addr} 0xa003ffff; " \ + "cp.b ${loadaddr} ${uboot_addr} ${filesize}; " \ + "setenv filesize; saveenv\0" + +/*Support LAN9217*/ +#define CONFIG_SMC911X 1 +#define CONFIG_SMC911X_16_BIT 1 +#define CONFIG_SMC911X_BASE mx51_io_base_addr + +/* + * The MX51 3stack board seems to have a hardware "peculiarity" confirmed under + * U-Boot, RedBoot and Linux: the ethernet Rx signal is reaching the CS8900A + * controller inverted. The controller is capable of detecting and correcting + * this, but it needs 4 network packets for that. Which means, at startup, you + * will not receive answers to the first 4 packest, unless there have been some + * broadcasts on the network, or your board is on a hub. Reducing the ARP + * timeout from default 5 seconds to 200ms we speed up the initial TFTP + * transfer, should the user wish one, significantly. + */ +#define CONFIG_ARP_TIMEOUT 200UL + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_PROMPT "MX51 U-Boot > " +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ + +#define CONFIG_SYS_MEMTEST_START 0 /* memtest works on */ +#define CONFIG_SYS_MEMTEST_END 0x10000 + +#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */ + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +#define CONFIG_SYS_HZ 1000 + +#define CONFIG_CMDLINE_EDITING 1 + +/*----------------------------------------------------------------------- + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */ + +/*----------------------------------------------------------------------- + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM_1 CSD0_BASE_ADDR +#define PHYS_SDRAM_1_SIZE (512 * 1024 * 1024) +#define iomem_valid_addr(addr, size) \ + (addr >= PHYS_SDRAM_1 && addr <= (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE)) + +/*----------------------------------------------------------------------- + * FLASH and environment organization + */ +#define CONFIG_SYS_NO_FLASH + +/*----------------------------------------------------------------------- + * NAND FLASH driver setup + */ +#define NAND_MAX_CHIPS 8 +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE 0x40000000 +#define CONFIG_NAND_FW_16BIT 0 /* 1: 16bit 0: 8bit */ + +/* Monitor at beginning of flash */ +#define CONFIG_FSL_ENV_IN_NAND +/* #define CONFIG_FSL_ENV_IN_NAND */ + +#define CONFIG_ENV_SECT_SIZE (128 * 1024) +#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE +#if defined(CONFIG_FSL_ENV_IN_NAND) + #define CONFIG_ENV_IS_IN_NAND 1 + #define CONFIG_ENV_OFFSET 0x100000 +#elif defined(CONFIG_FSL_ENV_IN_MMC) + #define CONFIG_ENV_IS_IN_MMC 1 + #define CONFIG_ENV_OFFSET (768 * 1024) +#else + #define CONFIG_ENV_IS_NOWHERE 1 +#endif +/* + * JFFS2 partitions + */ +#undef CONFIG_JFFS2_CMDLINE +#define CONFIG_JFFS2_DEV "nand0" + +#endif /* __CONFIG_H */ diff --git a/include/configs/mx51_3stack_android.h b/include/configs/mx51_3stack_android.h new file mode 100644 index 0000000000..318926967f --- /dev/null +++ b/include/configs/mx51_3stack_android.h @@ -0,0 +1,322 @@ +/* + * Copyright (C) 2007, Guennadi Liakhovetski + * + * (C) Copyright 2009-2010 Freescale Semiconductor, Inc. + * + * Configuration settings for the MX51-3Stack Freescale board. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include + + /* High Level Configuration Options */ +#define CONFIG_ARMV7 1 /* This is armv7 Cortex-A8 CPU core */ +#define CONFIG_SYS_APCS_GNU + +#define CONFIG_MXC 1 +#define CONFIG_MX51_3DS 1 /* in a mx51 */ +#define CONFIG_FLASH_HEADER 1 +#define CONFIG_FLASH_HEADER_OFFSET 0x400 +#define CONFIG_FLASH_HEADER_BARKER 0xB1 + +#define CONFIG_ARCH_CPU_INIT +#define CONFIG_ARCH_MMU + +#define CONFIG_SKIP_RELOCATE_UBOOT + +#define CONFIG_MX51_HCLK_FREQ 24000000 /* RedBoot says 26MHz */ + +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO + +#define CONFIG_SYS_64BIT_VSPRINTF + +#define BOARD_LATE_INIT +/* + * Disabled for now due to build problems under Debian and a significant + * increase in the final file size: 144260 vs. 109536 Bytes. + */ + +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_REVISION_TAG 1 +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 + +/* + * Size of malloc() pool + */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 4 * 1024 * 1024) +/* size in bytes reserved for initial data */ +#define CONFIG_SYS_GBL_DATA_SIZE 128 + +/* + * Hardware drivers + */ +#define CONFIG_MX51_UART 1 +#define CONFIG_MX51_UART1 1 + +/* + * SPI Configs + * */ +/* +#define CONFIG_FSL_SF 1 +#define CONFIG_CMD_SPI +#define CONFIG_CMD_SF +#define CONFIG_SPI_FLASH_IMX_ATMEL 1 +#define CONFIG_SPI_FLASH_CS 1 +#define CONFIG_IMX_ECSPI +#define CONFIG_IMX_SPI_PMIC +#define CONFIG_IMX_SPI_PMIC_CS 0 +#define IMX_CSPI_VER_2_3 1 +#define MAX_SPI_BYTES (64 * 4) +*/ + + +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_DNS +#define CONFIG_CMD_MII +#define CONFIG_CMD_NET +#define CONFIG_NET_RETRY_COUNT 100 + +#define CONFIG_CMD_UBI +#define CONFIG_CMD_UBIFS +#define CONFIG_CMD_MTDPARTS +#define CONFIG_MTD_DEVICE +#define CONFIG_MTD_PARTITIONS +#define MTDIDS_DEFAULT "nand0=nand0" +#define MTDPARTS_DEFAULT "mtdparts=nand0:0x700000@0x0(BOOT),0x100000@0x700000(MISC),0x1400000@0x800000(RECOVERY),-@0x1c00000(ROOT)" +#define MTD_ACTIVE_PART "nand0,3" +#define CONFIG_RBTREE +#define CONFIG_LZO + +/* + * Android support Configs + */ +#include + +#define CONFIG_FSL_ANDROID + +#define CONFIG_MXC_KPD +#define CONFIG_MXC_KEYMAPPING \ + { \ + KEY_1, KEY_2, KEY_3, KEY_F1, KEY_UP, KEY_F2, \ + KEY_4, KEY_5, KEY_6, KEY_LEFT, KEY_SELECT, KEY_RIGHT, \ + KEY_7, KEY_8, KEY_9, KEY_F3, KEY_DOWN, KEY_F4, \ + KEY_0, KEY_OK, KEY_ESC, KEY_ENTER, KEY_MENU, KEY_BACK, \ + } +#define CONFIG_MXC_KPD_COLMAX 6 +#define CONFIG_MXC_KPD_ROWMAX 4 +#define CONFIG_ANDROID_RECOVERY_BOOTARGS_MMC \ + "setenv bootargs ${bootargs} root=/dev/mmcblk0p4 ip=off init=/init rootfstype=ext3" +#define CONFIG_ANDROID_RECOVERY_BOOTCMD_MMC \ + "run bootargs_base bootargs_android;mmc read 0 ${loadaddr} 0x800 0x1280;bootm" +#define CONFIG_ANDROID_RECOVERY_BOOTARGS_NAND \ + "setenv bootargs ${bootargs} ip=off rootfstype=ubifs root=ubi1:recovery init=/init ubi.mtd=3 ubi.mtd=2" +#define CONFIG_ANDROID_RECOVERY_BOOTCMD_NAND \ + "run bootargs_base bootargs_android;nand read ${loadaddr} 0x300000 0x250000;bootm" +#define CONFIG_ANDROID_RECOVERY_CMD_FILE "/recovery/command" +#define CONFIG_ANDROID_BOOTMOD_DELAY 3 +#define CONFIG_ANDROID_CACHE_PARTITION_MMC 6 +#define CONFIG_ANDROID_UBIFS_PARTITION_NM "ROOT" +#define CONFIG_ANDROID_CACHE_PARTITION_NAND "cache" + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200} + +/*********************************************************** + * Command definition + ***********************************************************/ + +#include + +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +/* Enable below configure when supporting nand */ +#define CONFIG_CMD_NAND +#define CONFIG_MXC_NAND +#define CONFIG_CMD_MMC +#define CONFIG_CMD_ENV + +#undef CONFIG_CMD_IMLS + +#define CONFIG_BOOTDELAY 3 + +#define CONFIG_PRIME "FEC0" + +#define CONFIG_LOADADDR 0x90800000 /* loadaddr env var */ +#define CONFIG_RD_LOADADDR (CONFIG_LOADADDR + 0x300000) + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "ethprime=smc911x\0" \ + "uboot_addr=0xa0000000\0" \ + "uboot=u-boot.bin\0" \ + "kernel=uImage\0" \ + "rd_loadaddr=0x90B00000\0" \ + "nfsroot=/opt/eldk/arm\0" \ + "bootargs_base=setenv bootargs console=ttymxc0,115200\0"\ + "bootargs_nfs=setenv bootargs ${bootargs} root=/dev/nfs "\ + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0"\ + "bootargs_android=setenv bootargs ${bootargs} ip=dhcp mem=480M init=/init wvga calibration\0" \ + "bootcmd=run bootcmd_android\0" \ + "bootcmd_net=run bootargs_base bootargs_nfs; " \ + "tftpboot ${loadaddr} ${kernel}; bootm\0" \ + "bootcmd_android=run bootargs_base bootargs_android; " \ + "mmc read 0 ${loadaddr} 0x800 0x1280; " \ + "mmc read 0 ${rd_loadaddr} 0x2000 0x258; " \ + "bootm ${loadaddr} ${rd_loadaddr}\0" \ + "prg_uboot=tftpboot ${loadaddr} ${uboot}; " \ + "protect off ${uboot_addr} 0xa003ffff; " \ + "erase ${uboot_addr} 0xa003ffff; " \ + "cp.b ${loadaddr} ${uboot_addr} ${filesize}; " \ + "setenv filesize; saveenv\0" + +/*Support LAN9217*/ +#define CONFIG_SMC911X 1 +#define CONFIG_SMC911X_16_BIT 1 +#define CONFIG_SMC911X_BASE mx51_io_base_addr + +/* + * MMC Configs + * */ +#ifdef CONFIG_CMD_MMC + #define CONFIG_MMC 1 + #define CONFIG_GENERIC_MMC + #define CONFIG_IMX_MMC + #define CONFIG_SYS_FSL_ESDHC_NUM 2 + #define CONFIG_SYS_FSL_ESDHC_ADDR 0 + #define CONFIG_SYS_MMC_ENV_DEV 0 + #define CONFIG_DOS_PARTITION 1 + #define CONFIG_CMD_FAT 1 + #define CONFIG_CMD_EXT2 1 + #define CONFIG_SYS_FSL_ESDHC_NUM 1 +#endif + +/* + * Eth Configs + */ +#define CONFIG_HAS_ETH1 +#define CONFIG_NET_MULTI 1 +#define CONFIG_ETHPRIME +#define CONFIG_MXC_FEC +#define CONFIG_MII +#define CONFIG_DISCOVER_PHY + +#define CONFIG_FEC0_IOBASE FEC_BASE_ADDR +#define CONFIG_FEC0_PINMUX -1 +#define CONFIG_FEC0_PHY_ADDR 0x1F +#define CONFIG_FEC0_MIIBASE -1 + +/* + * The MX51 3stack board seems to have a hardware "peculiarity" confirmed under + * U-Boot, RedBoot and Linux: the ethernet Rx signal is reaching the CS8900A + * controller inverted. The controller is capable of detecting and correcting + * this, but it needs 4 network packets for that. Which means, at startup, you + * will not receive answers to the first 4 packest, unless there have been some + * broadcasts on the network, or your board is on a hub. Reducing the ARP + * timeout from default 5 seconds to 200ms we speed up the initial TFTP + * transfer, should the user wish one, significantly. + */ +#define CONFIG_ARP_TIMEOUT 200UL + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_PROMPT "MX51 U-Boot > " +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ + +#define CONFIG_SYS_MEMTEST_START 0 /* memtest works on */ +#define CONFIG_SYS_MEMTEST_END 0x10000 + +#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */ + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +#define CONFIG_SYS_HZ 1000 + +#define CONFIG_CMDLINE_EDITING 1 + +/*----------------------------------------------------------------------- + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */ + +/*----------------------------------------------------------------------- + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM_1 CSD0_BASE_ADDR +#define PHYS_SDRAM_1_SIZE (512 * 1024 * 1024) +#define iomem_valid_addr(addr, size) \ + (addr >= PHYS_SDRAM_1 && addr <= (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE)) + +/*----------------------------------------------------------------------- + * FLASH and environment organization + */ +#define CONFIG_SYS_NO_FLASH + +/*----------------------------------------------------------------------- + * NAND FLASH driver setup + */ +#define NAND_MAX_CHIPS 8 +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE 0x40000000 + +/* Monitor at beginning of flash */ +/* #define CONFIG_FSL_ENV_IN_MMC */ +#define CONFIG_FSL_ENV_IN_NAND + +#define CONFIG_ENV_SECT_SIZE (128 * 1024) +#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE + +#if defined(CONFIG_FSL_ENV_IN_NAND) + #define CONFIG_ENV_IS_IN_NAND 1 + #define CONFIG_ENV_OFFSET 0x100000 +#elif defined(CONFIG_FSL_ENV_IN_MMC) + #define CONFIG_ENV_IS_IN_MMC 1 + #define CONFIG_ENV_OFFSET (768 * 1024) +#elif defined(CONFIG_FSL_ENV_IN_SF) + #define CONFIG_ENV_IS_IN_SPI_FLASH 1 + #define CONFIG_ENV_SPI_CS 1 + #define CONFIG_ENV_OFFSET (768 * 1024) +#else + #define CONFIG_ENV_IS_NOWHERE 1 +#endif +/* + * JFFS2 partitions + */ +#undef CONFIG_JFFS2_CMDLINE +#define CONFIG_JFFS2_DEV "nand0" + +#endif /* __CONFIG_H */ diff --git a/include/configs/mx51_bbg.h b/include/configs/mx51_bbg.h new file mode 100644 index 0000000000..c240adacfc --- /dev/null +++ b/include/configs/mx51_bbg.h @@ -0,0 +1,274 @@ +/* + * Copyright (C) 2007, Guennadi Liakhovetski + * + * (C) Copyright 2009-2010 Freescale Semiconductor, Inc. + * + * Configuration settings for the MX51-3Stack Freescale board. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include + + /* High Level Configuration Options */ +#define CONFIG_ARMV7 1 /* This is armv7 Cortex-A8 CPU core */ + +#define CONFIG_MXC 1 +#define CONFIG_MX51_BBG 1 /* in a mx51 */ +#define CONFIG_FLASH_HEADER 1 +#define CONFIG_FLASH_HEADER_OFFSET 0x400 +#define CONFIG_FLASH_HEADER_BARKER 0xB1 + +#define CONFIG_SKIP_RELOCATE_UBOOT + +#define CONFIG_MX51_HCLK_FREQ 24000000 /* RedBoot says 26MHz */ + +#define CONFIG_ARCH_CPU_INIT +#define CONFIG_ARCH_MMU + +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO + +#define CONFIG_SYS_64BIT_VSPRINTF + +#define BOARD_LATE_INIT +/* + * Disabled for now due to build problems under Debian and a significant + * increase in the final file size: 144260 vs. 109536 Bytes. + */ + +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_REVISION_TAG 1 +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 + +/* + * Size of malloc() pool + */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024) +/* size in bytes reserved for initial data */ +#define CONFIG_SYS_GBL_DATA_SIZE 128 + +/* + * Hardware drivers + */ +#define CONFIG_MX51_UART 1 +#define CONFIG_MX51_UART1 1 + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200} + +/*********************************************************** + * Command definition + ***********************************************************/ + +#include + +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_DNS +#define CONFIG_CMD_MII +#define CONFIG_CMD_NET +#define CONFIG_NET_RETRY_COUNT 100 +#define CONFIG_CMD_SPI +#define CONFIG_CMD_SF +#define CONFIG_CMD_MMC +#define CONFIG_CMD_IIM +#define CONFIG_CMD_I2C + +/* + * FUSE Configs + * */ +#ifdef CONFIG_CMD_IIM + #define CONFIG_IMX_IIM + #define IMX_IIM_BASE IIM_BASE_ADDR + #define CONFIG_IIM_MAC_BANK 1 + #define CONFIG_IIM_MAC_ROW 9 +#endif + +/* + * SPI Configs + * */ +#ifdef CONFIG_CMD_SF + #define CONFIG_FSL_SF 1 + #define CONFIG_SPI_FLASH_IMX_ATMEL 1 + #define CONFIG_SPI_FLASH_CS 1 + #define CONFIG_IMX_ECSPI + #define IMX_CSPI_VER_2_3 1 + #define CONFIG_IMX_SPI_PMIC + #define CONFIG_IMX_SPI_PMIC_CS 0 + + #define MAX_SPI_BYTES (64 * 4) +#endif + +/* + * MMC Configs + * */ +#ifdef CONFIG_CMD_MMC + #define CONFIG_MMC 1 + #define CONFIG_GENERIC_MMC + #define CONFIG_IMX_MMC + #define CONFIG_SYS_FSL_ESDHC_NUM 2 + #define CONFIG_SYS_FSL_ESDHC_ADDR 0 + #define CONFIG_SYS_MMC_ENV_DEV 0 + #define CONFIG_DOS_PARTITION 1 + #define CONFIG_CMD_FAT 1 + #define CONFIG_DYNAMIC_MMC_DEVNO +#endif + +/* + * I2C Configs + */ +#ifdef CONFIG_CMD_I2C + #define CONFIG_HARD_I2C 1 + #define CONFIG_I2C_MXC 1 + #define CONFIG_SYS_I2C_PORT I2C1_BASE_ADDR + #define CONFIG_SYS_I2C_SPEED 400000 + #define CONFIG_SYS_I2C_SLAVE 0xfe +#endif + +/* + * Eth Configs + */ +#define CONFIG_HAS_ETH1 +#define CONFIG_NET_MULTI 1 +#define CONFIG_MXC_FEC +#define CONFIG_MII +#define CONFIG_DISCOVER_PHY + +#define CONFIG_GET_FEC_MAC_ADDR_FROM_IIM +#define CONFIG_IIM_MAC_ADDR_OFFSET 0x24 + +#define CONFIG_FEC0_IOBASE FEC_BASE_ADDR +#define CONFIG_FEC0_PINMUX -1 +#define CONFIG_FEC0_PHY_ADDR 0x1F +#define CONFIG_FEC0_MIIBASE -1 + + + +/* Enable below configure when supporting nand */ +#define CONFIG_CMD_ENV + +#undef CONFIG_CMD_IMLS + +#define CONFIG_BOOTDELAY 3 + +#define CONFIG_PRIME "FEC0" + +#define CONFIG_LOADADDR 0x90800000 /* loadaddr env var */ + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "ethprime=FEC0\0" \ + "uboot_addr=0xa0000000\0" \ + "uboot=u-boot.bin\0" \ + "kernel=uImage\0" \ + "bootargs_base=setenv bootargs console=ttymxc0,115200\0"\ + "bootargs_nfs=setenv bootargs ${bootargs} root=/dev/nfs "\ + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0"\ + "bootcmd=run bootcmd_net\0" \ + "bootcmd_net=run bootargs_base bootargs_nfs; " \ + "tftpboot ${loadaddr} ${kernel}; bootm\0" \ + "load_uboot=tftpboot ${loadaddr} ${uboot}\0" \ + +/* + * The MX51 3stack board seems to have a hardware "peculiarity" confirmed under + * U-Boot, RedBoot and Linux: the ethernet Rx signal is reaching the CS8900A + * controller inverted. The controller is capable of detecting and correcting + * this, but it needs 4 network packets for that. Which means, at startup, you + * will not receive answers to the first 4 packest, unless there have been some + * broadcasts on the network, or your board is on a hub. Reducing the ARP + * timeout from default 5 seconds to 200ms we speed up the initial TFTP + * transfer, should the user wish one, significantly. + */ +#define CONFIG_ARP_TIMEOUT 200UL + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_PROMPT "BBG U-Boot > " +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ + +#define CONFIG_SYS_MEMTEST_START 0 /* memtest works on */ +#define CONFIG_SYS_MEMTEST_END 0x10000 + +#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */ + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +#define CONFIG_SYS_HZ 1000 + +#define CONFIG_CMDLINE_EDITING 1 + +/*----------------------------------------------------------------------- + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */ + +/*----------------------------------------------------------------------- + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM_1 CSD0_BASE_ADDR +#define PHYS_SDRAM_1_SIZE (512 * 1024 * 1024) +#define iomem_valid_addr(addr, size) \ + (addr >= PHYS_SDRAM_1 && addr <= (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE)) + +/*----------------------------------------------------------------------- + * FLASH and environment organization + */ +#define CONFIG_SYS_NO_FLASH + +/* Monitor at beginning of flash */ +/* #define CONFIG_FSL_ENV_IN_SF */ +#define CONFIG_FSL_ENV_IN_MMC + +#define CONFIG_ENV_SECT_SIZE (128 * 1024) +#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE + +#if defined(CONFIG_FSL_ENV_IN_MMC) + #define CONFIG_ENV_IS_IN_MMC 1 + #define CONFIG_ENV_OFFSET (768 * 1024) +#elif defined(CONFIG_FSL_ENV_IN_SF) + #define CONFIG_ENV_IS_IN_SPI_FLASH 1 + #define CONFIG_ENV_SPI_CS 1 + #define CONFIG_ENV_OFFSET (768 * 1024) +#else + #define CONFIG_ENV_IS_NOWHERE 1 +#endif +/* + * JFFS2 partitions + */ +#undef CONFIG_JFFS2_CMDLINE +#define CONFIG_JFFS2_DEV "nand0" + +#endif /* __CONFIG_H */ diff --git a/include/configs/mx51_bbg_android.h b/include/configs/mx51_bbg_android.h new file mode 100644 index 0000000000..79aae09e75 --- /dev/null +++ b/include/configs/mx51_bbg_android.h @@ -0,0 +1,326 @@ +/* + * Copyright (C) 2007, Guennadi Liakhovetski + * + * (C) Copyright 2009-2010 Freescale Semiconductor, Inc. + * + * Configuration settings for the MX51-3Stack Freescale board. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include + + /* High Level Configuration Options */ +#define CONFIG_ARMV7 1 /* This is armv7 Cortex-A8 CPU core */ +#define CONFIG_SYS_APCS_GNU + +#define CONFIG_MXC 1 +#define CONFIG_MX51_BBG 1 /* in a mx51 */ +#define CONFIG_FLASH_HEADER 1 +#define CONFIG_FLASH_HEADER_OFFSET 0x400 +#define CONFIG_FLASH_HEADER_BARKER 0xB1 + +#define CONFIG_ARCH_CPU_INIT +#define CONFIG_ARCH_MMU + +#define CONFIG_SKIP_RELOCATE_UBOOT + +#define CONFIG_MX51_HCLK_FREQ 24000000 /* RedBoot says 26MHz */ + +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO + +#define CONFIG_SYS_64BIT_VSPRINTF + +#define BOARD_LATE_INIT +/* + * Disabled for now due to build problems under Debian and a significant + * increase in the final file size: 144260 vs. 109536 Bytes. + */ + +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_REVISION_TAG 1 +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 + +/* + * Size of malloc() pool + */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024) +/* size in bytes reserved for initial data */ +#define CONFIG_SYS_GBL_DATA_SIZE 128 + +/* + * Hardware drivers + */ +#define CONFIG_MX51_UART 1 +#define CONFIG_MX51_UART1 1 + + +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_DNS +#define CONFIG_CMD_MII +#define CONFIG_CMD_NET +#define CONFIG_NET_RETRY_COUNT 100 +#define CONFIG_CMD_I2C + +/* + * Android support Configs + */ +#include + +#define CONFIG_FSL_ANDROID + +#define CONFIG_MTD_DEVICE +#define CONFIG_MTD_PARTITIONS + + +#define CONFIG_MXC_KPD +#define CONFIG_MXC_KEYMAPPING \ + { \ + KEY_1, KEY_2, KEY_3, KEY_F1, KEY_UP, KEY_F2, \ + KEY_4, KEY_5, KEY_6, KEY_LEFT, KEY_SELECT, KEY_RIGHT, \ + KEY_7, KEY_8, KEY_9, KEY_F3, KEY_DOWN, KEY_F4, \ + KEY_0, KEY_OK, KEY_ESC, KEY_ENTER, KEY_MENU, KEY_BACK, \ + } + /* + { \ + KEY_3, KEY_2, KEY_0, KEY_OK, KEY_ESC, KEY_ENTER, + KEY_F1, KEY_4, KEY_6, KEY_5, + KEY_LEFT, KEY_1, KEY_ , KEY_8, KEY_9, KEY_RIGHT, + } + */ +#define CONFIG_MXC_KPD_COLMAX 6 +#define CONFIG_MXC_KPD_ROWMAX 4 +#define CONFIG_ANDROID_RECOVERY_BOOTARGS_MMC \ + "setenv bootargs ${bootargs} root=/dev/mmcblk0p4 ip=off init=/init rootfstype=ext3 wvga" +#define CONFIG_ANDROID_RECOVERY_BOOTCMD_MMC \ + "run bootargs_base bootargs_android;mmc read 0 ${loadaddr} 0x800 0x1280;bootm" +#define CONFIG_ANDROID_RECOVERY_CMD_FILE "/recovery/command" +#define CONFIG_ANDROID_BOOTMOD_DELAY 3 +#define CONFIG_ANDROID_CACHE_PARTITION_MMC 6 + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200} + +/*********************************************************** + * Command definition + ***********************************************************/ + +#include + +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +/* Enable below configure when supporting nand */ +/* #define CONFIG_CMD_NAND */ +#define CONFIG_CMD_MMC +#define CONFIG_CMD_ENV + +#undef CONFIG_CMD_IMLS + +#define CONFIG_BOOTDELAY 3 + +#define CONFIG_PRIME "FEC0" + +#define CONFIG_LOADADDR 0x90800000 /* loadaddr env var */ +#define CONFIG_RD_LOADADDR (CONFIG_LOADADDR + 0x300000) + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "ethprime=FEC0\0" \ + "uboot_addr=0xa0000000\0" \ + "uboot=u-boot.bin\0" \ + "kernel=uImage\0" \ + "rd_loadaddr=0x90B00000\0" \ + "nfsroot=/opt/eldk/arm\0" \ + "bootargs_base=setenv bootargs console=ttymxc0,115200\0"\ + "bootargs_nfs=setenv bootargs ${bootargs} root=/dev/nfs "\ + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0"\ + "bootargs_android=setenv bootargs ${bootargs} ip=dhcp mem=480M init=/init wvga calibration\0" \ + "bootcmd=run bootcmd_android\0" \ + "bootcmd_net=run bootargs_base bootargs_nfs; " \ + "tftpboot ${loadaddr} ${kernel}; bootm\0" \ + "bootcmd_android=run bootargs_base bootargs_android; " \ + "mmcinit;cp.b 0x100000 ${loadaddr} 0x250000; " \ + "cp.b 0x400000 ${rd_loadaddr} 0x4B000; " \ + "bootm ${loadaddr} ${rd_loadaddr}\0" \ + "prg_uboot=tftpboot ${loadaddr} ${uboot}; " \ + "protect off ${uboot_addr} 0xa003ffff; " \ + "erase ${uboot_addr} 0xa003ffff; " \ + "cp.b ${loadaddr} ${uboot_addr} ${filesize}; " \ + "setenv filesize; saveenv\0" + +/*Support LAN9217*/ +/* +#define CONFIG_SMC911X 1 +#define CONFIG_SMC911X_16_BIT 1 +#define CONFIG_SMC911X_BASE mx51_io_base_addr +*/ + +/* + * The MX51 3stack board seems to have a hardware "peculiarity" confirmed under + * U-Boot, RedBoot and Linux: the ethernet Rx signal is reaching the CS8900A + * controller inverted. The controller is capable of detecting and correcting + * this, but it needs 4 network packets for that. Which means, at startup, you + * will not receive answers to the first 4 packest, unless there have been some + * broadcasts on the network, or your board is on a hub. Reducing the ARP + * timeout from default 5 seconds to 200ms we speed up the initial TFTP + * transfer, should the user wish one, significantly. + */ +#define CONFIG_ARP_TIMEOUT 200UL + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_PROMPT "BBG U-Boot > " +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ + +#define CONFIG_SYS_MEMTEST_START 0 /* memtest works on */ +#define CONFIG_SYS_MEMTEST_END 0x10000 + +#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */ + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +#define CONFIG_SYS_HZ 1000 + +#define CONFIG_CMDLINE_EDITING 1 + +/* + * Eth Configs + */ +#define CONFIG_HAS_ETH1 +#define CONFIG_NET_MULTI 1 +#define CONFIG_MXC_FEC +#define CONFIG_MII +#define CONFIG_DISCOVER_PHY + +#define CONFIG_FEC0_IOBASE FEC_BASE_ADDR +#define CONFIG_FEC0_PINMUX -1 +#define CONFIG_FEC0_PHY_ADDR 0x1F +#define CONFIG_FEC0_MIIBASE -1 + +/* + * SPI Configs + * */ +#define CONFIG_FSL_SF 1 +#define CONFIG_CMD_SPI +#define CONFIG_CMD_SF +#define CONFIG_SPI_FLASH_IMX_ATMEL 1 +#define CONFIG_SPI_FLASH_CS 1 +#define CONFIG_IMX_ECSPI +#define CONFIG_IMX_SPI_PMIC +#define CONFIG_IMX_SPI_PMIC_CS 0 +#define IMX_CSPI_VER_2_3 1 + +#define MAX_SPI_BYTES (64 * 4) + +/* + * MMC Configs + * */ +#ifdef CONFIG_CMD_MMC + #define CONFIG_MMC 1 + #define CONFIG_GENERIC_MMC + #define CONFIG_IMX_MMC + #define CONFIG_SYS_FSL_ESDHC_NUM 2 + #define CONFIG_SYS_FSL_ESDHC_ADDR 0 + #define CONFIG_SYS_MMC_ENV_DEV 0 + #define CONFIG_DOS_PARTITION 1 + #define CONFIG_CMD_FAT 1 + #define CONFIG_CMD_EXT2 1 + #define CONFIG_DYNAMIC_MMC_DEVNO +#endif + +/* + * I2C Configs + */ +#define CONFIG_HARD_I2C 1 +#define CONFIG_I2C_MXC 1 +#define CONFIG_SYS_I2C_PORT I2C1_BASE_ADDR +#define CONFIG_SYS_I2C_SPEED 400000 +#define CONFIG_SYS_I2C_SLAVE 0xfe + +/*----------------------------------------------------------------------- + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */ + +/*----------------------------------------------------------------------- + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM_1 CSD0_BASE_ADDR +#define PHYS_SDRAM_1_SIZE (512 * 1024 * 1024) +#define iomem_valid_addr(addr, size) \ + (addr >= PHYS_SDRAM_1 && addr <= (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE)) + +/*----------------------------------------------------------------------- + * FLASH and environment organization + */ +#define CONFIG_SYS_NO_FLASH + +/*----------------------------------------------------------------------- + * NAND FLASH driver setup + */ +#define NAND_MAX_CHIPS 8 +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE 0x40000000 + +/* Monitor at beginning of flash */ +/* #define CONFIG_FSL_ENV_IN_SF */ +#define CONFIG_FSL_ENV_IN_MMC +/* #define CONFIG_FSL_ENV_IN_NAND */ + +#define CONFIG_ENV_SECT_SIZE (128 * 1024) +#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE + +#if defined(CONFIG_FSL_ENV_IN_NAND) + #define CONFIG_ENV_IS_IN_NAND 1 + #define CONFIG_ENV_OFFSET 0x100000 +#elif defined(CONFIG_FSL_ENV_IN_MMC) + #define CONFIG_ENV_IS_IN_MMC 1 + #define CONFIG_ENV_OFFSET (768 * 1024) +#elif defined(CONFIG_FSL_ENV_IN_SF) + #define CONFIG_ENV_IS_IN_SPI_FLASH 1 + #define CONFIG_ENV_SPI_CS 1 + #define CONFIG_ENV_OFFSET (768 * 1024) +#else + #define CONFIG_ENV_IS_NOWHERE 1 +#endif +/* + * JFFS2 partitions + */ +#undef CONFIG_JFFS2_CMDLINE +#define CONFIG_JFFS2_DEV "nand0" + +#endif /* __CONFIG_H */ diff --git a/include/configs/mx51_bbg_mfg.h b/include/configs/mx51_bbg_mfg.h new file mode 100644 index 0000000000..becad7339d --- /dev/null +++ b/include/configs/mx51_bbg_mfg.h @@ -0,0 +1,235 @@ +/* + * Copyright (C) 2007, Guennadi Liakhovetski + * + * (C) Copyright 2009-2010 Freescale Semiconductor, Inc. + * + * Configuration settings for the MX51-3Stack Freescale board. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include + + /* High Level Configuration Options */ +#define CONFIG_ARMV7 1 /* This is armv7 Cortex-A8 CPU core */ + +#define CONFIG_MFG 1 +#define CONFIG_MXC 1 +#define CONFIG_MX51_BBG 1 /* in a mx51 */ +#define CONFIG_FLASH_HEADER 1 +#define CONFIG_FLASH_HEADER_OFFSET 0x400 +#define CONFIG_FLASH_HEADER_BARKER 0xB1 + +#define CONFIG_SKIP_RELOCATE_UBOOT + +#define CONFIG_MX51_HCLK_FREQ 24000000 /* RedBoot says 26MHz */ + +#define CONFIG_ARCH_CPU_INIT +#define CONFIG_ARCH_MMU + +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO + +#define BOARD_LATE_INIT + +/* + * Disabled for now due to build problems under Debian and a significant + * increase in the final file size: 144260 vs. 109536 Bytes. + */ + +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_REVISION_TAG 1 +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 + +/* + * Size of malloc() pool + */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024) +/* size in bytes reserved for initial data */ +#define CONFIG_SYS_GBL_DATA_SIZE 128 + +/* + * Hardware drivers + */ +#define CONFIG_MX51_UART 1 +#define CONFIG_MX51_UART1 1 + +/* + * SPI Configs + * */ +#define CONFIG_FSL_SF 1 +#define CONFIG_SPI_FLASH_IMX_ATMEL 1 +#define CONFIG_SPI_FLASH_CS 1 +#define CONFIG_IMX_ECSPI +#define CONFIG_IMX_SPI_PMIC +#define CONFIG_IMX_SPI_PMIC_CS 0 +#define IMX_CSPI_VER_2_3 1 +#define MAX_SPI_BYTES (64 * 4) + +/* + * MMC Configs + * */ + +/* + * Eth Configs + */ +#define CONFIG_HAS_ETH1 +#define CONFIG_NET_MULTI 1 +#define CONFIG_MXC_FEC +#define CONFIG_MII +#define CONFIG_DISCOVER_PHY + +#define CONFIG_FEC0_IOBASE FEC_BASE_ADDR +#define CONFIG_FEC0_PINMUX -1 +#define CONFIG_FEC0_PHY_ADDR 0x1F +#define CONFIG_FEC0_MIIBASE -1 + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200} + +/*********************************************************** + * Command definition + ***********************************************************/ + +#include + +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_MII +#define CONFIG_CMD_NET +#define CONFIG_NET_RETRY_COUNT 100 + +/* + * SPI Configs + * */ + +/* + * MMC Configs + * */ +/* + * Eth Configs + */ +#define CONFIG_HAS_ETH1 +#define CONFIG_NET_MULTI 1 +#define CONFIG_MXC_FEC +#define CONFIG_MII +#define CONFIG_DISCOVER_PHY + +#define CONFIG_FEC0_IOBASE FEC_BASE_ADDR +#define CONFIG_FEC0_PINMUX -1 +#define CONFIG_FEC0_PHY_ADDR 0x1F +#define CONFIG_FEC0_MIIBASE -1 + + + +/* Enable below configure when supporting nand */ +#define CONFIG_CMD_ENV + +#undef CONFIG_CMD_IMLS + +#define CONFIG_BOOTDELAY 0 + +#define CONFIG_PRIME "FEC0" + +#define CONFIG_LOADADDR 0x90100000 /* loadaddr env var */ + +#define CONFIG_BOOTARGS "console=ttymxc0,115200 "\ + "rdinit=/linuxrc" + +#define CONFIG_BOOTCOMMAND "bootm ${loadaddr} 0x90800000" +#define CONFIG_ENV_IS_EMBEDDED +/* + * The MX51 3stack board seems to have a hardware "peculiarity" confirmed under + * U-Boot, RedBoot and Linux: the ethernet Rx signal is reaching the CS8900A + * controller inverted. The controller is capable of detecting and correcting + * this, but it needs 4 network packets for that. Which means, at startup, you + * will not receive answers to the first 4 packest, unless there have been some + * broadcasts on the network, or your board is on a hub. Reducing the ARP + * timeout from default 5 seconds to 200ms we speed up the initial TFTP + * transfer, should the user wish one, significantly. + */ +#define CONFIG_ARP_TIMEOUT 200UL + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_PROMPT "BBG U-Boot > " +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ + +#define CONFIG_SYS_MEMTEST_START 0 /* memtest works on */ +#define CONFIG_SYS_MEMTEST_END 0x10000 + +#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */ + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +#define CONFIG_SYS_HZ 1000 + +#define CONFIG_CMDLINE_EDITING 1 + +/*----------------------------------------------------------------------- + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */ + +/*----------------------------------------------------------------------- + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM_1 CSD0_BASE_ADDR +/* TO1 boards */ +/* #define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024) */ +#define PHYS_SDRAM_1_SIZE (512 * 1024 * 1024) +#define iomem_valid_addr(addr, size) \ + (addr >= PHYS_SDRAM_1 && addr <= (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE)) + +/*----------------------------------------------------------------------- + * FLASH and environment organization + */ +#define CONFIG_SYS_NO_FLASH + +/* Monitor at beginning of flash */ +/* #define CONFIG_FSL_ENV_IN_SF +*/ +/* #define CONFIG_FSL_ENV_IN_MMC */ + +#define CONFIG_ENV_SECT_SIZE (128 * 1024) +#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE +#define CONFIG_ENV_IS_NOWHERE + +/* + * JFFS2 partitions + */ +/* +#undef CONFIG_JFFS2_CMDLINE +#define CONFIG_JFFS2_DEV "nand0" +*/ +#endif /* __CONFIG_H */ diff --git a/include/configs/mx53_arm2.h b/include/configs/mx53_arm2.h new file mode 100644 index 0000000000..f94191dc83 --- /dev/null +++ b/include/configs/mx53_arm2.h @@ -0,0 +1,274 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. + * + * Configuration settings for the MX53-ARM2 Freescale board. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include + + /* High Level Configuration Options */ +#define CONFIG_ARMV7 /* This is armv7 Cortex-A8 CPU core */ +#define CONFIG_MXC +#define CONFIG_MX53 +#define CONFIG_MX53_ARM2 +#define CONFIG_FLASH_HEADER +#define CONFIG_FLASH_HEADER_OFFSET 0x400 + +#define CONFIG_SKIP_RELOCATE_UBOOT + +#define CONFIG_ARCH_CPU_INIT +#define CONFIG_ARCH_MMU + +#define CONFIG_MX53_HCLK_FREQ 24000000 +#define CONFIG_SYS_PLL2_FREQ 400 +#define CONFIG_SYS_AHB_PODF 2 +#define CONFIG_SYS_AXIA_PODF 0 +#define CONFIG_SYS_AXIB_PODF 1 + +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO + +#define CONFIG_SYS_64BIT_VSPRINTF + +#define BOARD_LATE_INIT +/* + * Disabled for now due to build problems under Debian and a significant + * increase in the final file size: 144260 vs. 109536 Bytes. + */ + +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_REVISION_TAG 1 +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 + +/* + * Size of malloc() pool + */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024) +/* size in bytes reserved for initial data */ +#define CONFIG_SYS_GBL_DATA_SIZE 128 + +/* + * Hardware drivers + */ +#define CONFIG_MX53_UART 1 +#define CONFIG_MX53_UART1 1 + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200} + +/*********************************************************** + * Command definition + ***********************************************************/ + +#include + +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_MII +#define CONFIG_CMD_NET +#define CONFIG_NET_RETRY_COUNT 100 +#define CONFIG_NET_MULTI 1 +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_DNS + +#define CONFIG_CMD_MMC +#define CONFIG_CMD_ENV + +#define CONFIG_CMD_IIM + +#define CONFIG_CMD_CLOCK +#define CONFIG_REF_CLK_FREQ CONFIG_MX53_HCLK_FREQ + +#define CONFIG_CMD_SATA + +#undef CONFIG_CMD_IMLS + +#define CONFIG_BOOTDELAY 3 + +#define CONFIG_PRIME "FEC0" + +#define CONFIG_LOADADDR 0x70800000 /* loadaddr env var */ +#define CONFIG_RD_LOADADDR (CONFIG_LOADADDR + 0x300000) + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "ethprime=FEC0\0" \ + "uboot=u-boot.bin\0" \ + "kernel=uImage\0" \ + "nfsroot=/opt/eldk/arm\0" \ + "bootargs_base=setenv bootargs console=ttymxc0,115200\0"\ + "bootargs_nfs=setenv bootargs ${bootargs} root=/dev/nfs "\ + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0"\ + "bootcmd_net=run bootargs_base bootargs_nfs; " \ + "tftpboot ${loadaddr} ${kernel}; bootm\0" \ + "bootargs_mmc=setenv bootargs ${bootargs} ip=dhcp " \ + "root=/dev/mmcblk0p2 rootwait\0" \ + "bootcmd_mmc=run bootargs_base bootargs_mmc; bootm\0" \ + "bootcmd=run bootcmd_net\0" \ + + +#define CONFIG_ARP_TIMEOUT 200UL + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_PROMPT "ARM2 U-Boot > " +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ + +#define CONFIG_SYS_MEMTEST_START 0 /* memtest works on */ +#define CONFIG_SYS_MEMTEST_END 0x10000 + +#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */ + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +#define CONFIG_SYS_HZ 1000 + +#define CONFIG_CMDLINE_EDITING 1 + +#define CONFIG_FEC0_IOBASE FEC_BASE_ADDR +#define CONFIG_FEC0_PINMUX -1 +#define CONFIG_FEC0_PHY_ADDR -1 +#define CONFIG_FEC0_MIIBASE -1 + +#define CONFIG_GET_FEC_MAC_ADDR_FROM_IIM +#define CONFIG_IIM_MAC_ADDR_OFFSET 0x24 + +#define CONFIG_MXC_FEC +#define CONFIG_MII +#define CONFIG_MII_GASKET +#define CONFIG_DISCOVER_PHY + +/* + * FUSE Configs + * */ +#ifdef CONFIG_CMD_MMC + #define CONFIG_IMX_IIM + #define IMX_IIM_BASE IIM_BASE_ADDR + #define CONFIG_IIM_MAC_BANK 1 + #define CONFIG_IIM_MAC_ROW 9 +#endif + +/* + * I2C Configs + */ +#define CONFIG_CMD_I2C 1 +#define CONFIG_HARD_I2C 1 +#define CONFIG_I2C_MXC 1 +#define CONFIG_SYS_I2C_PORT I2C2_BASE_ADDR +#define CONFIG_SYS_I2C_SPEED 100000 +#define CONFIG_SYS_I2C_SLAVE 0xfe + + +/* + * SPI Configs + */ +#define CONFIG_FSL_SF 1 +#define CONFIG_CMD_SPI +#define CONFIG_CMD_SF +#define CONFIG_SPI_FLASH_IMX_ATMEL 1 +#define CONFIG_SPI_FLASH_CS 1 +#define CONFIG_IMX_ECSPI +#define IMX_CSPI_VER_2_3 1 +#define MAX_SPI_BYTES (64 * 4) + +/* + * MMC Configs + */ +#ifdef CONFIG_CMD_MMC + #define CONFIG_MMC 1 + #define CONFIG_GENERIC_MMC + #define CONFIG_IMX_MMC + #define CONFIG_SYS_FSL_ESDHC_NUM 2 + #define CONFIG_SYS_FSL_ESDHC_ADDR 0 + #define CONFIG_SYS_MMC_ENV_DEV 1 + #define CONFIG_DOS_PARTITION 1 + #define CONFIG_CMD_FAT 1 + #define CONFIG_CMD_EXT2 1 + + #define CONFIG_BOOT_PARTITION_ACCESS +#endif + +/* + * SATA Configs + */ +#ifdef CONFIG_CMD_SATA + #define CONFIG_DWC_AHSATA + #define CONFIG_SYS_SATA_MAX_DEVICE 1 + #define CONFIG_DWC_AHSATA_PORT_ID 0 + #define CONFIG_DWC_AHSATA_BASE_ADDR SATA_BASE_ADDR + #define CONFIG_LBA48 + #define CONFIG_LIBATA +#endif + +/*----------------------------------------------------------------------- + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */ + +/*----------------------------------------------------------------------- + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM_1 CSD0_BASE_ADDR +#define PHYS_SDRAM_1_SIZE (1024 * 1024 * 1024) +#define iomem_valid_addr(addr, size) \ + (addr >= PHYS_SDRAM_1 && addr <= \ + (unsigned long)(PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE)) + +/*----------------------------------------------------------------------- + * FLASH and environment organization + */ +#define CONFIG_SYS_NO_FLASH + +/* Monitor at beginning of flash */ +#define CONFIG_FSL_ENV_IN_MMC + +#define CONFIG_ENV_SECT_SIZE (128 * 1024) +#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE + +#if defined(CONFIG_FSL_ENV_IN_NAND) + #define CONFIG_ENV_IS_IN_NAND 1 + #define CONFIG_ENV_OFFSET 0x100000 +#elif defined(CONFIG_FSL_ENV_IN_MMC) + #define CONFIG_ENV_IS_IN_MMC 1 + #define CONFIG_ENV_OFFSET (768 * 1024) +#elif defined(CONFIG_FSL_ENV_IN_SF) + #define CONFIG_ENV_IS_IN_SPI_FLASH 1 + #define CONFIG_ENV_SPI_CS 1 + #define CONFIG_ENV_OFFSET (768 * 1024) +#else + #define CONFIG_ENV_IS_NOWHERE 1 +#endif +#endif /* __CONFIG_H */ diff --git a/include/configs/mx53_arm2_ddr3.h b/include/configs/mx53_arm2_ddr3.h new file mode 100644 index 0000000000..f4cd6bab27 --- /dev/null +++ b/include/configs/mx53_arm2_ddr3.h @@ -0,0 +1,256 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. + * + * Configuration settings for the MX53-ARM2-DDR3 Freescale board. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include + + /* High Level Configuration Options */ +#define CONFIG_ARMV7 /* This is armv7 Cortex-A8 CPU core */ +#define CONFIG_MXC +#define CONFIG_MX53 +#define CONFIG_MX53_ARM2_DDR3 +#define CONFIG_FLASH_HEADER +#define CONFIG_FLASH_HEADER_OFFSET 0x400 + +#define CONFIG_SKIP_RELOCATE_UBOOT + +#define CONFIG_ARCH_CPU_INIT +#define CONFIG_ARCH_MMU + +#define CONFIG_MX53_HCLK_FREQ 24000000 +#define CONFIG_SYS_PLL2_FREQ 400 +#define CONFIG_SYS_AHB_PODF 2 +#define CONFIG_SYS_AXIA_PODF 0 +#define CONFIG_SYS_AXIB_PODF 1 + +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO + +#define CONFIG_SYS_64BIT_VSPRINTF + +#define BOARD_LATE_INIT +/* + * Disabled for now due to build problems under Debian and a significant + * increase in the final file size: 144260 vs. 109536 Bytes. + */ + +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_REVISION_TAG 1 +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 + +/* + * Size of malloc() pool + */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024) +/* size in bytes reserved for initial data */ +#define CONFIG_SYS_GBL_DATA_SIZE 128 + +/* + * Hardware drivers + */ +#define CONFIG_MX53_UART 1 +#define CONFIG_MX53_UART1 1 + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200} + +/*********************************************************** + * Command definition + ***********************************************************/ + +#include + +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_MII +#define CONFIG_CMD_NET +#define CONFIG_NET_RETRY_COUNT 100 +#define CONFIG_NET_MULTI 1 +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_DNS + +#define CONFIG_CMD_MMC +#define CONFIG_CMD_ENV + +#define CONFIG_CMD_IIM + +#define CONFIG_CMD_CLOCK +#define CONFIG_REF_CLK_FREQ CONFIG_MX53_HCLK_FREQ + +#undef CONFIG_CMD_IMLS + +#define CONFIG_BOOTDELAY 3 + +#define CONFIG_PRIME "FEC0" + +#define CONFIG_LOADADDR 0x70800000 /* loadaddr env var */ +#define CONFIG_RD_LOADADDR (CONFIG_LOADADDR + 0x300000) + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "ethprime=FEC0\0" \ + "uboot=u-boot.bin\0" \ + "kernel=uImage\0" \ + "nfsroot=/opt/eldk/arm\0" \ + "bootargs_base=setenv bootargs console=ttymxc0,115200\0"\ + "bootargs_nfs=setenv bootargs ${bootargs} root=/dev/nfs "\ + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0"\ + "bootcmd_net=run bootargs_base bootargs_nfs; " \ + "tftpboot ${loadaddr} ${kernel}; bootm\0" \ + "bootargs_mmc=setenv bootargs ${bootargs} ip=dhcp " \ + "root=/dev/mmcblk0p2 rootwait\0" \ + "bootcmd_mmc=run bootargs_base bootargs_mmc; bootm\0" \ + "bootcmd=run bootcmd_net\0" \ + + +#define CONFIG_ARP_TIMEOUT 200UL + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_PROMPT "ARM2-DDR3 U-Boot > " +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ + +#define CONFIG_SYS_MEMTEST_START 0 /* memtest works on */ +#define CONFIG_SYS_MEMTEST_END 0x10000 + +#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */ + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +#define CONFIG_SYS_HZ 1000 + +#define CONFIG_CMDLINE_EDITING 1 + +#define CONFIG_FEC0_IOBASE FEC_BASE_ADDR +#define CONFIG_FEC0_PINMUX -1 +#define CONFIG_FEC0_PHY_ADDR -1 +#define CONFIG_FEC0_MIIBASE -1 + +#define CONFIG_GET_FEC_MAC_ADDR_FROM_IIM +#define CONFIG_IIM_MAC_ADDR_OFFSET 0x24 + +#define CONFIG_MXC_FEC +#define CONFIG_MII +#define CONFIG_MII_GASKET +#define CONFIG_DISCOVER_PHY + +/* + * FUSE Configs + * */ +#ifdef CONFIG_CMD_MMC + #define CONFIG_IMX_IIM + #define IMX_IIM_BASE IIM_BASE_ADDR + #define CONFIG_IIM_MAC_BANK 1 + #define CONFIG_IIM_MAC_ROW 9 +#endif + +/* + * I2C Configs + */ +#define CONFIG_CMD_I2C 1 +#define CONFIG_HARD_I2C 1 +#define CONFIG_I2C_MXC 1 +#define CONFIG_SYS_I2C_PORT I2C2_BASE_ADDR +#define CONFIG_SYS_I2C_SPEED 100000 +#define CONFIG_SYS_I2C_SLAVE 0xfe + + +/* + * SPI Configs + */ +#define CONFIG_FSL_SF 1 +#define CONFIG_CMD_SPI +#define CONFIG_CMD_SF +#define CONFIG_SPI_FLASH_IMX_ATMEL 1 +#define CONFIG_SPI_FLASH_CS 1 +#define CONFIG_IMX_ECSPI +#define IMX_CSPI_VER_2_3 1 +#define MAX_SPI_BYTES (64 * 4) + +/* + * MMC Configs + */ +#ifdef CONFIG_CMD_MMC + #define CONFIG_MMC 1 + #define CONFIG_GENERIC_MMC + #define CONFIG_IMX_MMC + #define CONFIG_SYS_FSL_ESDHC_NUM 2 + #define CONFIG_SYS_FSL_ESDHC_ADDR 0 + #define CONFIG_SYS_MMC_ENV_DEV 1 + #define CONFIG_DOS_PARTITION 1 + #define CONFIG_CMD_FAT 1 + #define CONFIG_CMD_EXT2 1 +#endif +/*----------------------------------------------------------------------- + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */ + +/*----------------------------------------------------------------------- + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM_1 CSD0_BASE_ADDR +#define PHYS_SDRAM_1_SIZE (1024 * 1024 * 1024) +#define iomem_valid_addr(addr, size) \ + (addr >= PHYS_SDRAM_1 && addr <= (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE)) + +/*----------------------------------------------------------------------- + * FLASH and environment organization + */ +#define CONFIG_SYS_NO_FLASH + +/* Monitor at beginning of flash */ +#define CONFIG_FSL_ENV_IN_MMC + +#define CONFIG_ENV_SECT_SIZE (128 * 1024) +#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE + +#if defined(CONFIG_FSL_ENV_IN_NAND) + #define CONFIG_ENV_IS_IN_NAND 1 + #define CONFIG_ENV_OFFSET 0x100000 +#elif defined(CONFIG_FSL_ENV_IN_MMC) + #define CONFIG_ENV_IS_IN_MMC 1 + #define CONFIG_ENV_OFFSET (768 * 1024) +#elif defined(CONFIG_FSL_ENV_IN_SF) + #define CONFIG_ENV_IS_IN_SPI_FLASH 1 + #define CONFIG_ENV_SPI_CS 1 + #define CONFIG_ENV_OFFSET (768 * 1024) +#else + #define CONFIG_ENV_IS_NOWHERE 1 +#endif +#endif /* __CONFIG_H */ diff --git a/include/configs/mx53_evk.h b/include/configs/mx53_evk.h new file mode 100644 index 0000000000..0b1e75e542 --- /dev/null +++ b/include/configs/mx53_evk.h @@ -0,0 +1,273 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. + * + * Configuration settings for the MX53-EVK Freescale board. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include + + /* High Level Configuration Options */ +#define CONFIG_ARMV7 /* This is armv7 Cortex-A8 CPU core */ +#define CONFIG_MXC +#define CONFIG_MX53 +#define CONFIG_MX53_EVK +#define CONFIG_FLASH_HEADER +#define CONFIG_FLASH_HEADER_OFFSET 0x400 + +#define CONFIG_SKIP_RELOCATE_UBOOT + +#define CONFIG_ARCH_CPU_INIT +#define CONFIG_ARCH_MMU + +#define CONFIG_MX53_HCLK_FREQ 24000000 +#define CONFIG_SYS_PLL2_FREQ 600 +#define CONFIG_SYS_AHB_PODF 4 +#define CONFIG_SYS_AXIA_PODF 1 +#define CONFIG_SYS_AXIB_PODF 2 + +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO + +#define CONFIG_SYS_64BIT_VSPRINTF + +#define BOARD_LATE_INIT +/* + * Disabled for now due to build problems under Debian and a significant + * increase in the final file size: 144260 vs. 109536 Bytes. + */ + +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_REVISION_TAG 1 +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 + +/* + * Size of malloc() pool + */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024) +/* size in bytes reserved for initial data */ +#define CONFIG_SYS_GBL_DATA_SIZE 128 + +/* + * Hardware drivers + */ +#define CONFIG_MX53_UART 1 +#define CONFIG_MX53_UART1 1 + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200} + +/*********************************************************** + * Command definition + ***********************************************************/ + +#include + +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_MII +#define CONFIG_CMD_NET +#define CONFIG_NET_RETRY_COUNT 100 +#define CONFIG_NET_MULTI 1 +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_DNS +#define CONFIG_CMD_IIM +#define CONFIG_CMD_MMC +#define CONFIG_CMD_ENV + +#define CONFIG_CMD_CLOCK +#define CONFIG_REF_CLK_FREQ CONFIG_MX53_HCLK_FREQ + +#define CONFIG_CMD_SATA +#undef CONFIG_CMD_IMLS + +#define CONFIG_BOOTDELAY 3 + +#define CONFIG_PRIME "FEC0" + +#define CONFIG_LOADADDR 0x70800000 /* loadaddr env var */ +#define CONFIG_RD_LOADADDR (CONFIG_LOADADDR + 0x300000) + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "ethprime=FEC0\0" \ + "uboot=u-boot.bin\0" \ + "kernel=uImage\0" \ + "nfsroot=/opt/eldk/arm\0" \ + "bootargs_base=setenv bootargs console=ttymxc0,115200\0"\ + "bootargs_nfs=setenv bootargs ${bootargs} root=/dev/nfs "\ + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0"\ + "bootcmd_net=run bootargs_base bootargs_nfs; " \ + "tftpboot ${loadaddr} ${kernel}; bootm\0" \ + "bootargs_mmc=setenv bootargs ${bootargs} ip=dhcp " \ + "root=/dev/mmcblk0p2 rootwait\0" \ + "bootcmd_mmc=run bootargs_base bootargs_mmc; bootm\0" \ + "bootcmd=run bootcmd_net\0" \ + + +#define CONFIG_ARP_TIMEOUT 200UL + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_PROMPT "EVK U-Boot > " +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ + +#define CONFIG_SYS_MEMTEST_START 0 /* memtest works on */ +#define CONFIG_SYS_MEMTEST_END 0x10000 + +#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */ + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +#define CONFIG_SYS_HZ 1000 + +#define CONFIG_CMDLINE_EDITING 1 + +#define CONFIG_FEC0_IOBASE FEC_BASE_ADDR +#define CONFIG_FEC0_PINMUX -1 +#define CONFIG_FEC0_PHY_ADDR -1 +#define CONFIG_FEC0_MIIBASE -1 + +#define CONFIG_GET_FEC_MAC_ADDR_FROM_IIM +#define CONFIG_IIM_MAC_ADDR_OFFSET 0x24 + +#define CONFIG_MXC_FEC +#define CONFIG_MII +#define CONFIG_MII_GASKET +#define CONFIG_DISCOVER_PHY + +/* + * FUSE Configs + * */ +#ifdef CONFIG_CMD_MMC + #define CONFIG_IMX_IIM + #define IMX_IIM_BASE IIM_BASE_ADDR + #define CONFIG_IIM_MAC_BANK 1 + #define CONFIG_IIM_MAC_ROW 9 +#endif + +/* + * I2C Configs + */ +#define CONFIG_CMD_I2C 1 +#define CONFIG_HARD_I2C 1 +#define CONFIG_I2C_MXC 1 +#define CONFIG_SYS_I2C_PORT I2C2_BASE_ADDR +#define CONFIG_SYS_I2C_SPEED 100000 +#define CONFIG_SYS_I2C_SLAVE 0xfe + + +/* + * SPI Configs + */ +#define CONFIG_FSL_SF 1 +#define CONFIG_CMD_SPI +#define CONFIG_CMD_SF +#define CONFIG_SPI_FLASH_IMX_ATMEL 1 +#define CONFIG_SPI_FLASH_CS 1 +#define CONFIG_IMX_ECSPI +#define IMX_CSPI_VER_2_3 1 +#define MAX_SPI_BYTES (64 * 4) + +/* + * MMC Configs + */ +#ifdef CONFIG_CMD_MMC + #define CONFIG_MMC 1 + #define CONFIG_GENERIC_MMC + #define CONFIG_IMX_MMC + #define CONFIG_SYS_FSL_ESDHC_NUM 2 + #define CONFIG_SYS_FSL_ESDHC_ADDR 0 + #define CONFIG_SYS_MMC_ENV_DEV 0 + #define CONFIG_DOS_PARTITION 1 + #define CONFIG_CMD_FAT 1 + #define CONFIG_CMD_EXT2 1 + + /* detect whether ESDHC1 or ESDHC3 is boot device */ + #define CONFIG_DYNAMIC_MMC_DEVNO + + #define CONFIG_BOOT_PARTITION_ACCESS +#endif + +/* + * SATA Configs + */ +#ifdef CONFIG_CMD_SATA + #define CONFIG_DWC_AHSATA + #define CONFIG_SYS_SATA_MAX_DEVICE 1 + #define CONFIG_DWC_AHSATA_PORT_ID 0 + #define CONFIG_DWC_AHSATA_BASE_ADDR SATA_BASE_ADDR + #define CONFIG_LBA48 + #define CONFIG_LIBATA +#endif + +/*----------------------------------------------------------------------- + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */ + +/*----------------------------------------------------------------------- + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM_1 CSD0_BASE_ADDR +#define PHYS_SDRAM_1_SIZE (1024 * 1024 * 1024) +#define iomem_valid_addr(addr, size) \ + (addr >= PHYS_SDRAM_1 && addr <= (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE)) + +/*----------------------------------------------------------------------- + * FLASH and environment organization + */ +#define CONFIG_SYS_NO_FLASH + +/* Monitor at beginning of flash */ +#define CONFIG_FSL_ENV_IN_MMC + +#define CONFIG_ENV_SECT_SIZE (128 * 1024) +#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE + +#if defined(CONFIG_FSL_ENV_IN_NAND) + #define CONFIG_ENV_IS_IN_NAND 1 + #define CONFIG_ENV_OFFSET 0x100000 +#elif defined(CONFIG_FSL_ENV_IN_MMC) + #define CONFIG_ENV_IS_IN_MMC 1 + #define CONFIG_ENV_OFFSET (768 * 1024) +#elif defined(CONFIG_FSL_ENV_IN_SF) + #define CONFIG_ENV_IS_IN_SPI_FLASH 1 + #define CONFIG_ENV_SPI_CS 1 + #define CONFIG_ENV_OFFSET (768 * 1024) +#else + #define CONFIG_ENV_IS_NOWHERE 1 +#endif +#endif /* __CONFIG_H */ diff --git a/include/configs/mx53_evk_mfg.h b/include/configs/mx53_evk_mfg.h new file mode 100644 index 0000000000..b2b9f4f6b7 --- /dev/null +++ b/include/configs/mx53_evk_mfg.h @@ -0,0 +1,217 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. + * + * Configuration settings for the MX53-EVK Freescale board. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include + + /* High Level Configuration Options */ +#define CONFIG_MFG 1 +#define CONFIG_ARMV7 /* This is armv7 Cortex-A8 CPU core */ +#define CONFIG_MXC +#define CONFIG_MX53 +#define CONFIG_MX53_EVK +#define CONFIG_FLASH_HEADER +#define CONFIG_FLASH_HEADER_OFFSET 0x400 + +#define CONFIG_SKIP_RELOCATE_UBOOT + +#define CONFIG_ARCH_CPU_INIT +#define CONFIG_ARCH_MMU + +#define CONFIG_MX53_HCLK_FREQ 24000000 +#define CONFIG_SYS_PLL2_FREQ 600 +#define CONFIG_SYS_AHB_PODF 4 +#define CONFIG_SYS_AXIA_PODF 1 +#define CONFIG_SYS_AXIB_PODF 2 + +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO + +#define CONFIG_SYS_64BIT_VSPRINTF + +#define BOARD_LATE_INIT +/* + * Disabled for now due to build problems under Debian and a significant + * increase in the final file size: 144260 vs. 109536 Bytes. + */ + +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_REVISION_TAG 1 +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 + +/* + * Size of malloc() pool + */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024) +/* size in bytes reserved for initial data */ +#define CONFIG_SYS_GBL_DATA_SIZE 128 + +/* + * Hardware drivers + */ +#define CONFIG_MX53_UART 1 +#define CONFIG_MX53_UART1 1 + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200} + +/*********************************************************** + * Command definition + ***********************************************************/ + +#include + +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_MII +#define CONFIG_CMD_NET +#define CONFIG_NET_RETRY_COUNT 100 +#define CONFIG_NET_MULTI 1 +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_DNS + +#define CONFIG_CMD_MMC +#define CONFIG_CMD_ENV + +#define CONFIG_CMD_CLOCK +#define CONFIG_REF_CLK_FREQ CONFIG_MX53_HCLK_FREQ + +#undef CONFIG_CMD_IMLS + +#define CONFIG_BOOTDELAY 0 + +#define CONFIG_PRIME "FEC0" + +#define CONFIG_LOADADDR 0x70800000 /* loadaddr env var */ +#define CONFIG_RD_LOADADDR (CONFIG_LOADADDR + 0x300000) + +#define CONFIG_BOOTARGS "console=ttymxc0,115200 "\ + "rdinit=/linuxrc" +#define CONFIG_BOOTCOMMAND "bootm 0x70800000 0x70B00000" +#define CONFIG_ENV_IS_EMBEDDED + +#define CONFIG_ARP_TIMEOUT 200UL + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_PROMPT "EVK MFG U-Boot > " +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ + +#define CONFIG_SYS_MEMTEST_START 0 /* memtest works on */ +#define CONFIG_SYS_MEMTEST_END 0x10000 + +#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */ + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +#define CONFIG_SYS_HZ 1000 + +#define CONFIG_CMDLINE_EDITING 1 + +#define CONFIG_FEC0_IOBASE FEC_BASE_ADDR +#define CONFIG_FEC0_PINMUX -1 +#define CONFIG_FEC0_PHY_ADDR -1 +#define CONFIG_FEC0_MIIBASE -1 + +#define CONFIG_MXC_FEC +#define CONFIG_MII +#define CONFIG_MII_GASKET +#define CONFIG_DISCOVER_PHY + +/* + * I2C Configs + */ +#define CONFIG_CMD_I2C 1 +#define CONFIG_HARD_I2C 1 +#define CONFIG_I2C_MXC 1 +#define CONFIG_SYS_I2C_PORT I2C2_BASE_ADDR +#define CONFIG_SYS_I2C_SPEED 100000 +#define CONFIG_SYS_I2C_SLAVE 0xfe + + +/* + * SPI Configs + */ +#define CONFIG_FSL_SF 1 +#define CONFIG_CMD_SPI +#define CONFIG_CMD_SF +#define CONFIG_SPI_FLASH_IMX_ATMEL 1 +#define CONFIG_SPI_FLASH_CS 1 +#define CONFIG_IMX_ECSPI +#define IMX_CSPI_VER_2_3 1 +#define MAX_SPI_BYTES (64 * 4) + +/* + * MMC Configs + */ +#ifdef CONFIG_CMD_MMC + #define CONFIG_MMC 1 + #define CONFIG_GENERIC_MMC + #define CONFIG_IMX_MMC + #define CONFIG_SYS_FSL_ESDHC_NUM 2 + #define CONFIG_SYS_FSL_ESDHC_ADDR 0 + #define CONFIG_SYS_MMC_ENV_DEV 0 + #define CONFIG_DOS_PARTITION 1 + #define CONFIG_CMD_FAT 1 + #define CONFIG_CMD_EXT2 1 +#endif +/*----------------------------------------------------------------------- + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */ + +/*----------------------------------------------------------------------- + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM_1 CSD0_BASE_ADDR +#define PHYS_SDRAM_1_SIZE (1024 * 1024 * 1024) +#define iomem_valid_addr(addr, size) \ + (addr >= PHYS_SDRAM_1 && addr <= (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE)) + +/*----------------------------------------------------------------------- + * FLASH and environment organization + */ +#define CONFIG_SYS_NO_FLASH + + +#define CONFIG_ENV_SECT_SIZE (128 * 1024) +#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE + +#define CONFIG_ENV_IS_NOWHERE + +#endif /* __CONFIG_H */ diff --git a/include/configs/triton320.h b/include/configs/triton320.h new file mode 100644 index 0000000000..5af7c1a53d --- /dev/null +++ b/include/configs/triton320.h @@ -0,0 +1,266 @@ +/* + * (C) Copyright 2002 + * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * Configuation settings for the TRITON320 board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ +#define CONFIG_CPU_MONAHANS 1 /* Intel Monahan CPU */ +#define CONFIG_TRITON320 1 /* Zylonite board */ + +/* #define CONFIG_LCD 1 */ +#ifdef CONFIG_LCD +#define CONFIG_SHARP_LM8V31 +#endif +/* #define CONFIG_MMC 1 */ +#define BOARD_LATE_INIT 1 + +#define CONFIG_SKIP_RELOCATE_UBOOT 1 +#undef CONFIG_SKIP_LOWLEVEL_INIT +#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ + +/* + * Size of malloc() pool + */ +#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 256*1024) +#define CFG_GBL_DATA_SIZE 512 /* size in bytes reserved for initial data */ + +/* + * Hardware drivers + */ + + +#define CONFIG_DRIVER_DM9000 1 +#define CONFIG_DM9000_BASE 0x10000300 +#define DM9000_IO CONFIG_DM9000_BASE +#define DM9000_DATA (CONFIG_DM9000_BASE+0x8000) +#define CONFIG_DM9000_USE_16BIT + + + +/* + * select serial console configuration + */ +#define CONFIG_FFUART 1 + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_BAUDRATE 38400 + +#if 0 +# define CONFIG_COMMANDS CFG_CMD_AUTOSCRIPT \ + | CFG_CMD_BDI \ + | CFG_CMD_BOOTD \ + | CFG_CMD_CONSOLE \ + | CFG_CMD_ECHO \ + | CFG_CMD_ENV \ + | CFG_CMD_IMI \ + | CFG_CMD_ITEST \ + | CFG_CMD_LOADB \ + | CFG_CMD_LOADS \ + | CFG_CMD_MEMORY \ + | CFG_CMD_NAND \ + | CFG_CMD_REGINFO \ + | CFG_CMD_RUN \ + & ~(CFG_CMD_JFFS2 | CFG_CMD_FLASH | CFG_CMD_IMLS) +#endif + +#define CONFIG_COMMANDS ((CONFIG_CMD_DFL| \ + CFG_CMD_NAND | \ + CFG_CMD_JFFS2 | \ + CFG_CMD_PING | \ + CFG_CMD_DHCP) & \ + ~(CFG_CMD_FLASH | \ + CFG_CMD_IMLS)) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +#define CONFIG_BOOTDELAY 3 +#define CONFIG_BOOTCOMMAND "bootm 80000" +#define CONFIG_BOOTARGS "root=/dev/mtdblock1 rootfstype=jffs2 console=ttyS0,38400" +#define CONFIG_BOOT_RETRY_TIME -1 +#define CONFIG_BOOT_RETRY_MIN 60 +#define CONFIG_RESET_TO_RETRY +#define CONFIG_AUTOBOOT_PROMPT "autoboot in %d seconds\n" +#define CONFIG_AUTOBOOT_DELAY_STR " " +#define CONFIG_AUTOBOOT_STOP_STR "system" + +#define CONFIG_ETHADDR ff:ff:ff:ff:ff:ff +#define CONFIG_NETMASK 255.255.255.255 +#define CONFIG_IPADDR 0.0.0.0 +#define CONFIG_SERVERIP 0.0.0.0 +#define CONFIG_CMDLINE_TAG 1 +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_CMDLINE_EDITING +#define CONFIG_TIMESTAMP +#define CONFIG_USE_MAC_FROM_ENV + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/* + * Miscellaneous configurable options + */ +#define CFG_HUSH_PARSER 1 +#define CFG_PROMPT_HUSH_PS2 "> " + +#define CFG_LONGHELP /* undef to save memory */ +#ifdef CFG_HUSH_PARSER +#define CFG_PROMPT "$ " /* Monitor Command Prompt */ +#else +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#endif +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_DEVICE_NULLDEV 1 + +#define CFG_MEMTEST_START 0x00400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x00800000 /* 4 ... 8 MB in DRAM */ + +#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ + +#define CFG_HZ 3250000 /* incrementer freq: 3.25 MHz */ + +/* Monahans Core Frequency */ +#define CFG_MONAHANS_RUN_MODE_OSC_RATIO 31 /* valid values: 8, 16, 24, 31 */ +#define CFG_MONAHANS_TURBO_RUN_MODE_RATIO 2 /* valid values: 1, 2 */ + + /* valid baudrates */ +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/* #define CFG_MMC_BASE 0xF0000000 */ + +/* + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128*1024) /* regular stack */ +#ifdef CONFIG_USE_IRQ +#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ +#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ +#endif + +/* + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 banks of DRAM */ +#define PHYS_SDRAM_1 0x80000000 /* SDRAM Bank #1 */ +#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ + +#define CFG_DRAM_BASE PHYS_SDRAM_1 +#define CFG_DRAM_SIZE PHYS_SDRAM_1_SIZE + + +#define CFG_LOAD_ADDR (PHYS_SDRAM_1 + 0x100000) /* default load address */ + +#define CFG_SKIP_DRAM_SCRUB + +/* + * NAND Flash + */ +/* Use the new NAND code. (BOARDLIBS = drivers/nand/libnand.a required) */ +#define CONFIG_NEW_NAND_CODE +#define CFG_NAND0_BASE 0x0 +#undef CFG_NAND1_BASE + +#define CONFIG_MTD_NAND_ECC_JFFS2 1 + +#define CFG_NAND_BASE_LIST { CFG_NAND0_BASE } +#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ + +/* nand timeout values */ +#define CFG_NAND_PROG_ERASE_TO 9000 +#define CFG_NAND_OTHER_TO 2000 +#define CFG_NAND_SENDCMD_RETRY 3 +#undef NAND_ALLOW_ERASE_ALL /* Allow erasing bad blocks - don't use */ + +/* NAND Timing Parameters (in ns) */ +#define NAND_TIMING_tCH 10 +#define NAND_TIMING_tCS 0 +#define NAND_TIMING_tWH 20 +#define NAND_TIMING_tWP 40 + +#define NAND_TIMING_tRH 20 +#define NAND_TIMING_tRP 40 + +#define NAND_TIMING_tR 11123 +#define NAND_TIMING_tWHR 100 +#define NAND_TIMING_tAR 10 + +/* NAND debugging */ +#if 0 +#define CFG_DFC_DEBUG1 /* useful */ +#define CFG_DFC_DEBUG2 /* noisy */ +#define CFG_DFC_DEBUG3 /* extremly noisy */ +#else +#undef CFG_DFC_DEBUG1 /* useful */ +#undef CFG_DFC_DEBUG2 /* noisy */ +#undef CFG_DFC_DEBUG3 /* extremly noisy */ +#endif + +#define CONFIG_MTD_DEBUG 0 +#define CONFIG_MTD_DEBUG_VERBOSE 0 + +#define ADDR_COLUMN 1 +#define ADDR_PAGE 2 +#define ADDR_COLUMN_PAGE 3 + +#define NAND_ChipID_UNKNOWN 0x00 +#define NAND_MAX_FLOORS 1 +#define NAND_MAX_CHIPS 1 + +#define CFG_NO_FLASH 1 + +#define CFG_ENV_IS_IN_NAND 1 +#define CFG_ENV_OFFSET 0x60000 +#undef CFG_ENV_OFFSET_REDUND +#define CFG_ENV_SIZE 0x20000 + +#define CONFIG_JFFS2_NAND 1 +#define CONFIG_JFFS2_NAND_DEV "nand0" /* nand device jffs2 lives on */ +#define CONFIG_JFFS2_NAND_OFF 0x80000 /* start of jffs2 partition */ +#define CONFIG_JFFS2_NAND_SIZE 64*1024*1024 /* size of jffs2 partition */ + + +/* mtdparts command line support */ +#define CONFIG_JFFS2_CMDLINE +#define MTDIDS_DEFAULT "nand0=triton320-nand" +#define MTDPARTS_DEFAULT "mtdparts=triton320-nand:128k(sbootl),256k(u-boot),128k(env),2m(linux_kernel),83456k(userfs),32m(wince);" + +#endif /* __CONFIG_H */ diff --git a/include/configs/tx28.h b/include/configs/tx28.h new file mode 100644 index 0000000000..7a756542e4 --- /dev/null +++ b/include/configs/tx28.h @@ -0,0 +1,218 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __MX28_EVK_H +#define __MX28_EVK_H + +#include + +/* + * SoC configurations + */ +#define CONFIG_MX28 /* i.MX28 SoC */ +#define CONFIG_MX28_TO1_2 +#define CONFIG_SYS_HZ 1000 /* Ticks per second */ +/* ROM loads UBOOT into DRAM */ +#define CONFIG_SKIP_RELOCATE_UBOOT + +/* + * Memory configurations + */ +#define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */ +#define PHYS_SDRAM_1 0x40000000 /* Base address */ +#define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */ +#define CONFIG_STACKSIZE 0x00020000 /* 128 KB stack */ +#define CONFIG_SYS_MALLOC_LEN 0x00400000 /* 4 MB for malloc */ +#define CONFIG_SYS_GBL_DATA_SIZE 128 /* Reserved for initial data */ +#define CONFIG_SYS_MEMTEST_START 0x40000000 /* Memtest start address */ +#define CONFIG_SYS_MEMTEST_END 0x40400000 /* 4 MB RAM test */ + +/* + * U-Boot general configurations + */ +#define CONFIG_SYS_LONGHELP +#define CONFIG_DISPLAY_BOARDINFO +#define CONFIG_SYS_PROMPT "MX28 U-Boot > " +#define CONFIG_SYS_CBSIZE 2048 /* Console I/O buffer size */ +#define CONFIG_SYS_PBSIZE \ + (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) + /* Print buffer size */ +#define CONFIG_SYS_MAXARGS 64 /* Max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + /* Boot argument buffer size */ +#define CONFIG_VERSION_VARIABLE /* U-BOOT version */ +#define CONFIG_AUTO_COMPLETE /* Command auto complete */ +#define CONFIG_CMDLINE_EDITING /* Command history etc */ + +#define CONFIG_SYS_64BIT_VSPRINTF + +/* + * Boot Linux + */ +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_BOOTDELAY 3 +#define CONFIG_BOOTFILE "uImage" +#define CONFIG_BOOTARGS "console=ttyAMA0,115200 tx28_base=stkv3" \ + " tx28_otg_mode=device ro debug panic=1" +#define CONFIG_BOOTCOMMAND "run bootcmd_nand" +#define CONFIG_LOADADDR 0x40100000 +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +/* + * Extra Environments + */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "bootargs_nand=setenv bootargs ${bootargs} ${mtdparts}" \ + " root=/dev/mtdblock3" \ + " rootfstype=jffs2\0" \ + "nfsroot=/tftpboot/rootfs\0" \ + "bootargs_nfs=setenv bootargs ${bootargs} root=/dev/nfs" \ + " ip=dhcp nfsroot=${serverip}:${nfsroot},nolock\0" \ + "bootargs_mmc=setenv bootargs ${bootargs} root=/dev/mmcblk0p3" \ + " rootwait ip=dhcp\0" \ + "bootcmd_nand=set autostart yes;run bootargs_nand;" \ + " nboot linux\0" \ + "bootcmd_net=set autostart yes;run bootargs_nfs; dhcp\0" \ + "bootcmd_mmc=set autostart yes;run bootargs_mmc;" \ + " mmc read 0 ${loadaddr} 100 3000\0" \ + "mtdids=" MTDIDS_DEFAULT "\0" \ + "mtdparts=" MTDPARTS_DEFAULT "\0" \ + "autostart=no\0" + +#define __stringify(s) _stringify(s) +#define _stringify(s) #s + +#define MTD_NAME "gpmi-nand" +#define MTDIDS_DEFAULT "nand0=" MTD_NAME +#define MTDPARTS_DEFAULT "mtdparts=" MTD_NAME ":128k@" \ + __stringify(CONFIG_ENV_OFFSET) \ + "(env),1m@0x40000(u-boot),4m(linux),16m(rootfs),-(userfs)" + +/* + * U-Boot Commands + */ +#define CONFIG_SYS_NO_FLASH +#include +#define CONFIG_ARCH_CPU_INIT +#define CONFIG_DISPLAY_CPUINFO + +/* + * Serial Driver + */ +#define CONFIG_UARTDBG_CLK 24000000 +#define CONFIG_BAUDRATE 115200 /* Default baud rate */ +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/* + * FEC Driver + */ +#define CONFIG_MXC_FEC +#define CONFIG_GET_FEC_MAC_ADDR_FROM_IIM +#define CONFIG_FEC0_IOBASE ((volatile void *)REGS_ENET_BASE) +#define CONFIG_FEC0_PHY_ADDR 0 +#define CONFIG_NET_MULTI +#define CONFIG_ETH_PRIME +#define CONFIG_RMII +#define CONFIG_CMD_MII +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_PING +/* Add for working with "strict" DHCP server */ +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_DNS + +#define CONFIG_CMD_MMC +#define CONFIG_CMD_NAND +#define CONFIG_CMD_MTDPARTS + +/* + * NAND flash driver + */ +#ifdef CONFIG_CMD_NAND +#define CONFIG_MTD_DEVICE +#define CONFIG_ENV_IS_IN_NAND +#define CONFIG_MXS_NAND +#define CONFIG_SYS_MXS_DMA_CHANNEL 4 +#define CONFIG_SYS_MAX_FLASH_SECT 1024 +#define CONFIG_SYS_MAX_FLASH_BANKS 1 +#define CONFIG_SYS_NAND_MAX_CHIPS 1 +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#ifdef CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_OVERWRITE +#define CONFIG_ENV_OFFSET 0x20000 +#define CONFIG_ENV_SIZE 0x20000 /* 128 KiB */ +#endif +#ifndef CONFIG_SYS_NO_FLASH +#define CONFIG_CMD_FLASH +#define CONFIG_SYS_NAND_BASE 0xa0000000 +#define CONFIG_FIT +#define CONFIG_OF_LIBFDT +#else +#define CONFIG_SYS_NAND_BASE 0x00000000 +#define CONFIG_CMD_ROMUPDATE +#endif +#endif /* CONFIG_CMD_NAND */ + +/* + * MMC Driver + */ +#ifdef CONFIG_CMD_MMC +#ifndef CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_IS_IN_MMC +#endif +#define CONFIG_MMC +#define CONFIG_IMX_SSP_MMC /* MMC driver based on SSP */ +#define CONFIG_GENERIC_MMC +#define CONFIG_DOS_PARTITION +#define CONFIG_CMD_FAT +#define CONFIG_SYS_SSP_MMC_NUM 1 + +#define CONFIG_BOOT_PARTITION_ACCESS +#define CONFIG_DOS_PARTITION +#define CONFIG_CMD_FAT +#define CONFIG_CMD_EXT2 + +/* + * Environments on MMC + */ +#ifdef CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_CMD_ENV +#define CONFIG_ENV_OVERWRITE +/* Assoiated with the MMC layout defined in mmcops.c */ +#define CONFIG_ENV_OFFSET 0x400 /* 1 KB */ +#define CONFIG_ENV_SIZE (0x20000 - 0x400) /* 127 KB */ +#define CONFIG_DYNAMIC_MMC_DEVNO +#endif /* CONFIG_ENV_IS_IN_MMC */ +#endif /* CONFIG_CMD_MMC */ + +/* The global boot mode will be detected by ROM code and + * a boot mode value will be stored at fixed address: + * TO1.0 addr 0x0001a7f0 + * TO1.2 addr 0x00019BF0 + */ +#ifndef MX28_EVK_TO1_0 + #define GLOBAL_BOOT_MODE_ADDR 0x00019BF0 +#else + #define GLOBAL_BOOT_MODE_ADDR 0x0001a7f0 +#endif +#define BOOT_MODE_SD0 0x9 +#define BOOT_MODE_SD1 0xa + +#endif /* __MX28_EVK_H */ diff --git a/include/environment.h b/include/environment.h index 5bed32fd47..e0759aeb47 100644 --- a/include/environment.h +++ b/include/environment.h @@ -96,7 +96,30 @@ # endif #endif /* CONFIG_ENV_IS_IN_MG_DISK */ +#if defined(CONFIG_ENV_IS_IN_MMC) +# ifndef CONFIG_ENV_OFFSET +# error "Need to define CONFIG_ENV_OFFSET when using CONFIG_ENV_IS_IN_MMC" +# endif +# ifndef CONFIG_ENV_ADDR +# define CONFIG_ENV_ADDR (CONFIG_ENV_OFFSET) +# endif +# ifndef CONFIG_ENV_OFFSET +# define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR) +# endif +# ifdef CONFIG_ENV_OFFSET_REDUND +# define CONFIG_SYS_REDUNDAND_ENVIRONMENT +# endif +# ifdef CONFIG_ENV_IS_EMBEDDED +# define ENV_IS_EMBEDDED 1 +# endif +#endif /* CONFIG_ENV_IS_IN_MMC */ + #include "compiler.h" +#ifdef USE_HOSTCC +# include +#else +# include +#endif #ifdef CONFIG_SYS_REDUNDAND_ENVIRONMENT # define ENV_HEADER_SIZE (sizeof(uint32_t) + 1) diff --git a/include/fsl_esdhc.h b/include/fsl_esdhc.h index 89b8304d5f..a0b1f5cf37 100644 --- a/include/fsl_esdhc.h +++ b/include/fsl_esdhc.h @@ -2,7 +2,7 @@ * FSL SD/MMC Defines *------------------------------------------------------------------- * - * Copyright 2007-2008, Freescale Semiconductor, Inc + * Copyright (C) 2007-2008, 2010 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -32,7 +32,9 @@ #define SYSCTL 0x0002e02c #define SYSCTL_INITA 0x08000000 #define SYSCTL_TIMEOUT_MASK 0x000f0000 -#define SYSCTL_CLOCK_MASK 0x00000fff +#define SYSCTL_CLOCK_MASK 0x0000fff0 +#define SYSCTL_RSTA 0x01000000 +#define SYSCTL_SDCLKEN 0x00000008 #define SYSCTL_PEREN 0x00000004 #define SYSCTL_HCKEN 0x00000002 #define SYSCTL_IPGEN 0x00000001 @@ -86,6 +88,7 @@ #define PRSSTAT_CDPL (0x00040000) #define PRSSTAT_CINS (0x00010000) #define PRSSTAT_BREN (0x00000800) +#define PRSSTAT_SDSTB (0x00000008) #define PRSSTAT_DLA (0x00000004) #define PRSSTAT_CICHB (0x00000002) #define PRSSTAT_CIDHB (0x00000001) @@ -94,6 +97,7 @@ #define PROCTL_INIT 0x00000020 #define PROCTL_DTW_4 0x00000002 #define PROCTL_DTW_8 0x00000004 +#define PROCTL_D3CD 0x00000008 #define CMDARG 0x0002e008 @@ -112,6 +116,7 @@ #define XFERTYP_RSPTYP_48_BUSY 0x00030000 #define XFERTYP_MSBSEL 0x00000020 #define XFERTYP_DTDSEL 0x00000010 +#define XFERTYP_DDR_EN 0x00000008 #define XFERTYP_AC12EN 0x00000004 #define XFERTYP_BCEN 0x00000002 #define XFERTYP_DMAEN 0x00000001 @@ -133,7 +138,7 @@ #define BLKATTR 0x2e004 #define BLKATTR_CNT(x) ((x & 0xffff) << 16) #define BLKATTR_SIZE(x) (x & 0x1fff) -#define MAX_BLK_CNT 0x7fff /* so malloc will have enough room with 32M */ +#define MAX_BLK_CNT 0xffff /* so malloc will have enough room with 32M */ #define ESDHC_HOSTCAPBLT_VS18 0x04000000 #define ESDHC_HOSTCAPBLT_VS30 0x02000000 @@ -142,8 +147,24 @@ #define ESDHC_HOSTCAPBLT_DMAS 0x00400000 #define ESDHC_HOSTCAPBLT_HSS 0x00200000 -#ifdef CONFIG_FSL_ESDHC +#define ESDHC_HOSTVER_VVN_MASK 0x0000ff00 +#define ESDHC_HOSTVER_VVN_SHIFT 8 +#define ESDHC_HOSTVER_DDR_SUPPORT 0x13 + +#define ESDHC_DLLCTRL_SLV_OVERRIDE_VAL 12 +#define ESDHC_DLLCTRL_SLV_OVERRIDE_VAL_MASK 0x0000FC00 +#define ESDHC_DLLCTRL_SLV_OVERRIDE_VAL_SHIFT 10 +#define ESDHC_DLLCTRL_SLV_OVERRIDE 0x200 + +struct fsl_esdhc_cfg { + u32 esdhc_base; + u32 no_snoop; + u32 clk_enable; +}; + +#if defined(CONFIG_FSL_ESDHC) || defined(CONFIG_IMX_MMC) int fsl_esdhc_mmc_init(bd_t *bis); +int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg); void fdt_fixup_esdhc(void *blob, bd_t *bd); #else static inline int fsl_esdhc_mmc_init(bd_t *bis) { return -ENOSYS; } diff --git a/include/imx_spi.h b/include/imx_spi.h new file mode 100644 index 0000000000..e4f6444334 --- /dev/null +++ b/include/imx_spi.h @@ -0,0 +1,96 @@ +/* + * (C) Copyright 2008-2009 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __IMX_SPI_H__ +#define __IMX_SPI_H__ + +#include + +#undef IMX_SPI_DEBUG + +#define IMX_SPI_ACTIVE_HIGH 1 +#define IMX_SPI_ACTIVE_LOW 0 +#define SPI_RETRY_TIMES 100 + +#if defined(IMX_CSPI_VER_0_7) + #define SPI_RX_DATA 0x0 + #define SPI_TX_DATA 0x4 + #define SPI_CON_REG 0x8 + #define SPI_INT_REG 0xC + #define SPI_DMA_REG 0x10 + #define SPI_STAT_REG 0x14 + #define SPI_PERIOD_REG 0x18 + + #define SPI_CTRL_EN (1 << 0) + #define SPI_CTRL_MODE (1 << 1) + #define SPI_CTRL_REG_XCH_BIT (1 << 2) + #define SPI_CTRL_SSPOL (1 << 7) + #define SPI_CTRL_SSPOL_OFF (7) + #define SPI_CTRL_SSCTL (1 << 6) + #define SPI_CTRL_SSCTL_OFF (6) + #define SPI_CTRL_SCLK_POL (1 << 4) + #define SPI_CTRL_SCLK_POL_OFF (4) + #define SPI_CTRL_SCLK_PHA (1 << 5) + #define SPI_CTRL_SCLK_PHA_OFF (5) + #define SPI_CTRL_SS_OFF (12) + #define SPI_CTRL_SS_MASK (3 << 12) + #define SPI_CTRL_DATA_OFF (16) + #define SPI_CTRL_DATA_MASK (7 << 16) + #define SPI_CTRL_BURST_OFF (20) + #define SPI_CTRL_BURST_MASK (0xFFF << 20) + #define SPI_INT_STAT_TC (1 << 7) + +#elif defined(IMX_CSPI_VER_2_3) + #define SPI_RX_DATA 0x0 + #define SPI_TX_DATA 0x4 + #define SPI_CON_REG 0x8 + #define SPI_CFG_REG 0xC + #define SPI_INT_REG 0x10 + #define SPI_DMA_REG 0x14 + #define SPI_STAT_REG 0x18 + #define SPI_PERIOD_REG 0x1C +#endif + +struct spi_reg_t { + u32 ctrl_reg; + u32 cfg_reg; +}; + +struct imx_spi_dev_t { + struct spi_slave slave; + u32 base; /* base address of SPI module the device is connected to */ + u32 freq; /* desired clock freq in Hz for this device */ + u32 ss_pol; /* ss polarity: 1=active high; 0=active low */ + u32 ss; /* slave select */ + u32 in_sctl; /* inactive sclk ctl: 1=stay low; 0=stay high */ + u32 in_dctl; /* inactive data ctl: 1=stay low; 0=stay high */ + u32 ssctl; /* single burst mode vs multiple: 0=single; 1=multi */ + u32 sclkpol; /* sclk polarity: active high=0; active low=1 */ + u32 sclkpha; /* sclk phase: 0=phase 0; 1=phase1 */ + u32 fifo_sz; /* fifo size in bytes for either tx or rx. Don't add them up! */ + u32 us_delay; /* us delay in each xfer */ + struct spi_reg_t reg; /* pointer to a set of SPI registers */ +}; + +extern void spi_io_init(struct imx_spi_dev_t *dev); + +#endif /* __IMX_SPI_H__ */ diff --git a/include/imx_spi_nor.h b/include/imx_spi_nor.h new file mode 100644 index 0000000000..9425d59f29 --- /dev/null +++ b/include/imx_spi_nor.h @@ -0,0 +1,70 @@ +/* + * (C) Copyright 2008-2010 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _IMX_SPI_NOR_H_ +#define _IMX_SPI_NOR_H_ + +#define READ 0x03 /* tx:1 byte cmd + 3 byte addr;rx:variable bytes */ +#define READ_HS 0x0B /* tx:1 byte cmd + 3 byte addr + 1 byte dummy; */ +#define RDSR 0x05 /* read stat reg 1 byte tx cmd + 1 byte rx status */ +#define RDSR_BUSY (1 << 0) /* 1=write-in-progress (default 0) */ +#define RDSR_WEL (1 << 1) /* 1=write enable (default 0) */ +#define RDSR_BP0 (1 << 2) /* block write prot level (default 1) */ +#define RDSR_BP1 (1 << 3) /* block write prot level (default 1) */ +#define RDSR_BP2 (1 << 4) /* block write prot level (default 1) */ +#define RDSR_BP3 (1 << 5) /* block write prot level (default 1) */ +#define RDSR_AAI (1 << 6) /* 1=AAI prog mode; 0=byte prog (def 0) */ +#define RDSR_BPL (1 << 7) /* 1=BP3,BP2,BP1,BP0 RO; 0=R/W (def 0) */ +#define WREN 0x06 /* write enable. 1 byte tx cmd */ +#define WRDI 0x04 /* write disable. 1 byte tx cmd */ +#define EWSR 0x50 /* Enable write status. 1 byte tx cmd */ +#define WRSR 0x01 /* Write stat reg. 1 byte tx cmd + 1 byte tx val */ +#define ERASE_4K 0x20 /* sector erase. 1 byte cmd + 3 byte addr */ +#define ERASE_32K 0x52 /* 32K block erase. 1 byte cmd + 3 byte addr */ +#define ERASE_64K 0xD8 /* 64K block erase. 1 byte cmd + 3 byte addr */ +#define ERASE_CHIP 0x60 /* whole chip erase */ +#define BYTE_PROG 0x02 /* all tx: 1 cmd + 3 addr + 1 data */ +#define AAI_PROG 0xAD /* all tx: [1 cmd + 3 addr + 2 data] + RDSR */ + /* + [1cmd + 2 data] + .. + [WRDI] + [RDSR] */ +#define JEDEC_ID 0x9F /* read JEDEC ID. tx: 1 byte cmd; rx: 3 byte ID */ + +/* Atmel SPI-NOR commands */ +#define WR_2_MEM_DIR 0x82 +#define BUF1_WR 0x84 +#define BUF2_WR 0x87 +#define BUF1_TO_MEM 0x83 +#define BUF2_TO_MEM 0x86 +#define STAT_READ 0xD7 +#define STAT_PG_SZ (1 << 0) /* 1=Page size is 512, 0=Page size is 528 */ +#define STAT_PROT (1 << 1) /* 1=sector protection enabled (default 0) */ +#define STAT_COMP (1 << 6) +#define STAT_BUSY (1 << 7) /* 1=Device not busy */ +#define CONFIG_REG1 0x3D +#define CONFIG_REG2 0x2A +#define CONFIG_REG3 0x80 +#define CONFIG_REG4 0xA6 + +#define SZ_64K 0x10000 +#define SZ_32K 0x8000 +#define SZ_4K 0x1000 + +#endif /* _IMX_SPI_NOR_H_ */ diff --git a/include/imx_ssp_mmc.h b/include/imx_ssp_mmc.h new file mode 100644 index 0000000000..a3c157d18d --- /dev/null +++ b/include/imx_ssp_mmc.h @@ -0,0 +1,50 @@ +/* + * IMX SSP MMC Defines + *------------------------------------------------------------------- + * + * Copyright (C) 2007-2008, 2010 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + *------------------------------------------------------------------- + * + */ + +#ifndef __IMX_SSP_MMC_H__ +#define __IMX_SSP_MMC_H__ + +/* Common definition */ +#define BM_CLKCTRL_SSP_CLKGATE 0x80000000 +#define BM_CLKCTRL_SSP_BUSY 0x20000000 +#define BM_CLKCTRL_SSP_DIV_FRAC_EN 0x00000200 +#define BM_CLKCTRL_SSP_DIV 0x000001FF +#define BP_CLKCTRL_SSP_DIV 0 + +struct imx_ssp_mmc_cfg { + u32 ssp_mmc_base; + + /* CLKCTRL register offset */ + u32 clkctrl_ssp_offset; + u32 clkctrl_clkseq_ssp_offset; +}; + +#ifdef CONFIG_IMX_SSP_MMC +int imx_ssp_mmc_initialize(bd_t *bis, struct imx_ssp_mmc_cfg *cfg); + +extern u32 ssp_mmc_is_wp(struct mmc *mmc); +#endif /* CONFIG_IMX_SSP_MMC */ + +#endif /* __IMX_SSP_MMC_H__ */ diff --git a/include/lcd.h b/include/lcd.h index 1f85daa8a2..062e0246d6 100644 --- a/include/lcd.h +++ b/include/lcd.h @@ -1,4 +1,6 @@ /* + * Copyright (C) 2004-2010 Freescale Semiconductor, Inc. + * * MPC823 and PXA LCD Controller * * Modeled after video interface by Paolo Scaffardi @@ -181,6 +183,65 @@ typedef struct vidinfo { u_long mmio; /* Memory mapped registers */ } vidinfo_t; +#elif defined(CONFIG_MXC2_LCD) + +typedef struct vidinfo { + u_long vl_refresh; /* Refresh Rate Hz */ + u_long vl_row; /* resolution in x */ + u_long vl_col; /* resolution in y */ + u_long vl_pixclock; /* pixel clock in picoseconds */ + u_long vl_left_margin; /* Horizontal back porch */ + u_long vl_right_margin; /* Horizontal front porch */ + u_long vl_upper_margin; /* Vertical back porch */ + u_long vl_lower_margin; /* Vertical front porch */ + u_long vl_hsync; /* Horizontal sync pulse length */ + u_long vl_vsync; /* Vertical sync pulse length */ + u_long vl_sync; /* Polarity on data enable */ + u_long vl_mode; /* Video Mode */ + u_long vl_flag; + u_char vl_bpix; + ushort *cmap; +} vidinfo_t; + +#elif defined(CONFIG_MXC_EPDC) + +struct waveform_modes { + int mode_init; + int mode_du; + int mode_gc4; + int mode_gc8; + int mode_gc16; + int mode_gc32; +}; + +struct epdc_data_struct { + /* EPDC buffer pointers */ + u_long working_buf_addr; + u_long waveform_buf_addr; + + /* Waveform mode definitions */ + struct waveform_modes wv_modes; +}; + +typedef struct vidinfo { + u_long vl_refresh; /* Refresh Rate Hz */ + u_long vl_row; /* resolution in x */ + u_long vl_col; /* resolution in y */ + u_long vl_pixclock; /* pixel clock in picoseconds */ + u_long vl_left_margin; /* Horizontal back porch */ + u_long vl_right_margin; /* Horizontal front porch */ + u_long vl_upper_margin; /* Vertical back porch */ + u_long vl_lower_margin; /* Vertical front porch */ + u_long vl_hsync; /* Horizontal sync pulse length */ + u_long vl_vsync; /* Vertical sync pulse length */ + u_long vl_sync; /* Polarity on data enable */ + u_long vl_mode; /* Video Mode */ + u_long vl_flag; + u_char vl_bpix; + ushort *cmap; + struct epdc_data_struct epdc_data; +} vidinfo_t; + #else typedef struct vidinfo { diff --git a/include/linux/bitops.h b/include/linux/bitops.h index 7d41ae62cc..e724310298 100644 --- a/include/linux/bitops.h +++ b/include/linux/bitops.h @@ -1,6 +1,7 @@ #ifndef _LINUX_BITOPS_H #define _LINUX_BITOPS_H +#include /* * ffs: find first bit set. This is defined the same way as @@ -37,6 +38,43 @@ static inline int generic_ffs(int x) return r; } +/** + * fls - find last (most-significant) bit set + * @x: the word to search + * + * This is defined the same way as ffs. + * Note fls(0) = 0, fls(1) = 1, fls(0x80000000) = 32. + */ +static inline int generic_fls(int x) +{ + int r = 32; + + if (!x) + return 0; + if (!(x & 0xffff0000u)) { + x <<= 16; + r -= 16; + } + if (!(x & 0xff000000u)) { + x <<= 8; + r -= 8; + } + if (!(x & 0xf0000000u)) { + x <<= 4; + r -= 4; + } + if (!(x & 0xc0000000u)) { + x <<= 2; + r -= 2; + } + if (!(x & 0x80000000u)) { + x <<= 1; + r -= 1; + } + return r; +} + + /* * hweightN: returns the hamming weight (i.e. the number * of bits set) of a N-bit word @@ -66,7 +104,52 @@ static inline unsigned int generic_hweight8(unsigned int w) return (res & 0x0F) + ((res >> 4) & 0x0F); } +#define BIT_MASK(nr) (1UL << ((nr) % BITS_PER_LONG)) +#define BIT_WORD(nr) ((nr) / BITS_PER_LONG) + #include +/* linux/include/asm-generic/bitops/non-atomic.h */ + +#ifndef PLATFORM__SET_BIT +# define __set_bit generic_set_bit +#endif + +#ifndef PLATFORM__CLEAR_BIT +# define __clear_bit generic_clear_bit +#endif + +#ifndef PLATFORM_FFS +# define ffs generic_ffs +#endif + +#ifndef PLATFORM_FLS +# define fls generic_fls +#endif + +/** + * __set_bit - Set a bit in memory + * @nr: the bit to set + * @addr: the address to start counting from + * + * Unlike set_bit(), this function is non-atomic and may be reordered. + * If it's called on the same region of memory simultaneously, the effect + * may be that only one operation succeeds. + */ +static inline void generic_set_bit(int nr, volatile unsigned long *addr) +{ + unsigned long mask = BIT_MASK(nr); + unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); + + *p |= mask; +} + +static inline void generic_clear_bit(int nr, volatile unsigned long *addr) +{ + unsigned long mask = BIT_MASK(nr); + unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); + + *p &= ~mask; +} #endif diff --git a/include/linux/mtd/bbm.h b/include/linux/mtd/bbm.h index 7db25465df..5ccdb67ff4 100644 --- a/include/linux/mtd/bbm.h +++ b/include/linux/mtd/bbm.h @@ -4,15 +4,26 @@ * NAND family Bad Block Management (BBM) header file * - Bad Block Table (BBT) implementation * - * Copyright (c) 2005-2007 Samsung Electronics + * Copyright © 2005 Samsung Electronics * Kyungmin Park * - * Copyright (c) 2000-2005 + * Copyright © 2000-2005 * Thomas Gleixner * * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * */ #ifndef __LINUX_MTD_BBM_H #define __LINUX_MTD_BBM_H @@ -24,22 +35,21 @@ /** * struct nand_bbt_descr - bad block table descriptor - * @param options options for this descriptor - * @param pages the page(s) where we find the bbt, used with - * option BBT_ABSPAGE when bbt is searched, - * then we store the found bbts pages here. - * Its an array and supports up to 8 chips now - * @param offs offset of the pattern in the oob area of the page - * @param veroffs offset of the bbt version counter in the oob are of the page - * @param version version read from the bbt page during scan - * @param len length of the pattern, if 0 no pattern check is performed - * @param maxblocks maximum number of blocks to search for a bbt. This number of - * blocks is reserved at the end of the device - * where the tables are written. - * @param reserved_block_code if non-0, this pattern denotes a reserved - * (rather than bad) block in the stored bbt - * @param pattern pattern to identify bad block table or factory marked - * good / bad blocks, can be NULL, if len = 0 + * @options: options for this descriptor + * @pages: the page(s) where we find the bbt, used with option BBT_ABSPAGE + * when bbt is searched, then we store the found bbts pages here. + * Its an array and supports up to 8 chips now + * @offs: offset of the pattern in the oob area of the page + * @veroffs: offset of the bbt version counter in the oob are of the page + * @version: version read from the bbt page during scan + * @len: length of the pattern, if 0 no pattern check is performed + * @maxblocks: maximum number of blocks to search for a bbt. This number of + * blocks is reserved at the end of the device where the tables are + * written. + * @reserved_block_code: if non-0, this pattern denotes a reserved (rather than + * bad) block in the stored bbt + * @pattern: pattern to identify bad block table or factory marked good / + * bad blocks, can be NULL, if len = 0 * * Descriptor for the bad block table marker and the descriptor for the * pattern which identifies good and bad blocks. The assumption is made @@ -76,7 +86,7 @@ struct nand_bbt_descr { #define NAND_BBT_PERCHIP 0x00000080 /* bbt has a version counter at offset veroffs */ #define NAND_BBT_VERSION 0x00000100 -/* Create a bbt if none axists */ +/* Create a bbt if none exists */ #define NAND_BBT_CREATE 0x00000200 /* Search good / bad pattern through all pages of a block */ #define NAND_BBT_SCANALLPAGES 0x00000400 @@ -88,6 +98,14 @@ struct nand_bbt_descr { #define NAND_BBT_SAVECONTENT 0x00002000 /* Search good / bad pattern on the first and the second page */ #define NAND_BBT_SCAN2NDPAGE 0x00004000 +/* Search good / bad pattern on the last page of the eraseblock */ +#define NAND_BBT_SCANLASTPAGE 0x00008000 +/* Chip stores bad block marker on BOTH 1st and 6th bytes of OOB */ +#define NAND_BBT_SCANBYTE1AND6 0x00100000 +/* The nand_bbt_descr was created dynamicaly and must be freed */ +#define NAND_BBT_DYNAMICSTRUCT 0x00200000 +/* The bad block table does not OOB for marker */ +#define NAND_BBT_NO_OOB 0x00400000 /* The maximum number of blocks to scan for a bbt */ #define NAND_BBT_SCAN_MAXBLOCKS 4 @@ -95,22 +113,27 @@ struct nand_bbt_descr { /* * Constants for oob configuration */ -#define ONENAND_BADBLOCK_POS 0 +#define NAND_SMALL_BADBLOCK_POS 5 +#define NAND_LARGE_BADBLOCK_POS 0 +#define ONENAND_BADBLOCK_POS 0 /* * Bad block scanning errors */ -#define ONENAND_BBT_READ_ERROR 1 -#define ONENAND_BBT_READ_ECC_ERROR 2 -#define ONENAND_BBT_READ_FATAL_ERROR 4 +#define ONENAND_BBT_READ_ERROR 1 +#define ONENAND_BBT_READ_ECC_ERROR 2 +#define ONENAND_BBT_READ_FATAL_ERROR 4 /** - * struct bbt_info - [GENERIC] Bad Block Table data structure - * @param bbt_erase_shift [INTERN] number of address bits in a bbt entry - * @param badblockpos [INTERN] position of the bad block marker in the oob area - * @param bbt [INTERN] bad block table pointer - * @param badblock_pattern [REPLACEABLE] bad block scan pattern used for initial bad block scan - * @param priv [OPTIONAL] pointer to private bbm date + * struct bbm_info - [GENERIC] Bad Block Table data structure + * @bbt_erase_shift: [INTERN] number of address bits in a bbt entry + * @badblockpos: [INTERN] position of the bad block marker in the oob area + * @options: options for this descriptor + * @bbt: [INTERN] bad block table pointer + * @isbad_bbt: function to determine if a block is bad + * @badblock_pattern: [REPLACEABLE] bad block scan pattern used for + * initial bad block scan + * @priv: [OPTIONAL] pointer to private bbm date */ struct bbm_info { int bbt_erase_shift; @@ -119,7 +142,7 @@ struct bbm_info { uint8_t *bbt; - int (*isbad_bbt) (struct mtd_info * mtd, loff_t ofs, int allowbbt); + int (*isbad_bbt)(struct mtd_info *mtd, loff_t ofs, int allowbbt); /* TODO Add more NAND specific fileds */ struct nand_bbt_descr *badblock_pattern; @@ -128,7 +151,7 @@ struct bbm_info { }; /* OneNAND BBT interface */ -extern int onenand_scan_bbt (struct mtd_info *mtd, struct nand_bbt_descr *bd); -extern int onenand_default_bbt (struct mtd_info *mtd); +extern int onenand_scan_bbt(struct mtd_info *mtd, struct nand_bbt_descr *bd); +extern int onenand_default_bbt(struct mtd_info *mtd); -#endif /* __LINUX_MTD_BBM_H */ +#endif /* __LINUX_MTD_BBM_H */ diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h index 3e0044b94f..8880dfe2c1 100644 --- a/include/linux/mtd/nand.h +++ b/include/linux/mtd/nand.h @@ -31,7 +31,6 @@ #include "linux/mtd/mtd.h" #include "linux/mtd/bbm.h" - struct mtd_info; /* Scan and identify a NAND device */ extern int nand_scan (struct mtd_info *mtd, int max_chips); @@ -50,8 +49,8 @@ extern void nand_wait_ready(struct mtd_info *mtd); * is supported now. If you add a chip with bigger oobsize/page * adjust this accordingly. */ -#define NAND_MAX_OOBSIZE 218 -#define NAND_MAX_PAGESIZE 4096 +#define NAND_MAX_OOBSIZE (218 * CONFIG_SYS_NAND_MAX_CHIPS) +#define NAND_MAX_PAGESIZE (4096 * CONFIG_SYS_NAND_MAX_CHIPS) /* * Constants for hardware specific CLE/ALE/NCE function @@ -200,6 +199,11 @@ typedef enum { /* This option is defined if the board driver allocates its own buffers (e.g. because it needs them DMA-coherent */ #define NAND_OWN_BUFFERS 0x00040000 +/* + * If passed additionally to NAND_USE_FLASH_BBT then BBT code will not touch + * the OOB area. + */ +#define NAND_USE_FLASH_BBT_NO_OOB 0x00100000 /* Options set by nand scan */ /* bbt has already been read */ #define NAND_BBT_SCANNED 0x40000000 @@ -437,6 +441,8 @@ struct nand_chip { #define NAND_MFR_HYNIX 0xad #define NAND_MFR_MICRON 0x2c #define NAND_MFR_AMD 0x01 +#define NAND_MFR_SANDISK 0x45 +#define NAND_MFR_INTEL 0x89 /** * struct nand_flash_dev - NAND Flash Device ID Structure @@ -549,5 +555,4 @@ struct platform_nand_chip *get_platform_nandchip(struct mtd_info *mtd) return chip->priv; } - #endif /* __LINUX_MTD_NAND_H */ diff --git a/include/mmc.h b/include/mmc.h index 2dc69abb68..b450f4f145 100644 --- a/include/mmc.h +++ b/include/mmc.h @@ -1,5 +1,7 @@ /* - * Copyright 2008, Freescale Semiconductor, Inc + * (C) Copyright 2009-2010 Freescale Semiconductor, Inc. + * + * Copyright 2008-2010, Freescale Semiconductor, Inc * Andy Fleming * * Based (loosely) on the Linux code @@ -44,6 +46,8 @@ #define MMC_MODE_HS_52MHz 0x010 #define MMC_MODE_4BIT 0x100 #define MMC_MODE_8BIT 0x200 +#define EMMC_MODE_4BIT_DDR 0x400 +#define EMMC_MODE_8BIT_DDR 0x800 #define SD_DATA_4BIT 0x00040000 @@ -79,6 +83,7 @@ #define SD_CMD_SEND_RELATIVE_ADDR 3 #define SD_CMD_SWITCH_FUNC 6 #define SD_CMD_SEND_IF_COND 8 +#define SD_CMD_SELECT_PARTITION 43 #define SD_CMD_APP_SET_BUS_WIDTH 6 #define SD_CMD_APP_SEND_OP_COND 41 @@ -90,7 +95,7 @@ #define MMC_HS_TIMING 0x00000100 #define MMC_HS_52MHZ 0x2 - +#define EMMC_MODE_DDR_3V 0x4 #define OCR_BUSY 0x80000000 #define OCR_HCS 0x40000000 @@ -128,11 +133,14 @@ * EXT_CSD fields */ +#define EXT_CSD_BOOT_BUS_WIDTH 177 /* RW */ +#define EXT_CSD_BOOT_CONFIG 179 /* RW */ #define EXT_CSD_BUS_WIDTH 183 /* R/W */ #define EXT_CSD_HS_TIMING 185 /* R/W */ #define EXT_CSD_CARD_TYPE 196 /* RO */ #define EXT_CSD_REV 192 /* RO */ #define EXT_CSD_SEC_CNT 212 /* RO, 4 bytes */ +#define EXT_CSD_BOOT_SIZE_MULT 226 /* RO */ /* * EXT_CSD field definitions @@ -148,6 +156,24 @@ #define EXT_CSD_BUS_WIDTH_1 0 /* Card is in 1 bit mode */ #define EXT_CSD_BUS_WIDTH_4 1 /* Card is in 4 bit mode */ #define EXT_CSD_BUS_WIDTH_8 2 /* Card is in 8 bit mode */ +#define EXT_CSD_BUS_WIDTH_4_DDR 5 /* eMMC 4.4 in 4-bit DDR mode */ +#define EXT_CSD_BUS_WIDTH_8_DDR 6 /* eMMC 4.4 in 8-bit DDR mode */ + +#define EXT_CSD_BOOT_BUS_WIDTH_1BIT 0 +#define EXT_CSD_BOOT_BUS_WIDTH_4BIT 1 +#define EXT_CSD_BOOT_BUS_WIDTH_8BIT 2 +#define EXT_CSD_BOOT_BUS_WIDTH_DDR (1 << 4) + +#define EXT_CSD_BOOT_PARTITION_ENABLE_MASK (0x7 << 3) +#define EXT_CSD_BOOT_PARTITION_DISABLE (0x0) +#define EXT_CSD_BOOT_PARTITION_PART1 (0x1 << 3) +#define EXT_CSD_BOOT_PARTITION_PART2 (0x2 << 3) +#define EXT_CSD_BOOT_PARTITION_USER (0x7 << 3) + +#define EXT_CSD_BOOT_PARTITION_ACCESS_MASK (0x7) +#define EXT_CSD_BOOT_PARTITION_ACCESS_DISABLE (0x0) +#define EXT_CSD_BOOT_PARTITION_ACCESS_PART1 (0x1) +#define EXT_CSD_BOOT_PARTITION_ACCESS_PART2 (0x2) #define R1_ILLEGAL_COMMAND (1 << 22) #define R1_APP_CMD (1 << 5) @@ -169,7 +195,6 @@ #define MMC_RSP_R6 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE) #define MMC_RSP_R7 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE) - struct mmc_cid { unsigned long psn; unsigned short oid; @@ -259,6 +284,10 @@ struct mmc { uint read_bl_len; uint write_bl_len; u64 capacity; +#ifdef CONFIG_BOOT_PARTITION_ACCESS + uint boot_config; + uint boot_size_mult; +#endif block_dev_desc_t block_dev; int (*send_cmd)(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data); @@ -272,6 +301,10 @@ int mmc_init(struct mmc *mmc); int mmc_read(struct mmc *mmc, u64 src, uchar *dst, int size); struct mmc *find_mmc_device(int dev_num); void print_mmc_devices(char separator); +#ifdef CONFIG_BOOT_PARTITION_ACCESS +int mmc_switch_partition(struct mmc *mmc, uint part, uint enable_boot); +int sd_switch_partition(struct mmc *mmc, uint part); +#endif #ifndef CONFIG_GENERIC_MMC int mmc_legacy_init(int verbose); diff --git a/include/mx2fb.h b/include/mx2fb.h new file mode 100644 index 0000000000..de05bc0973 --- /dev/null +++ b/include/mx2fb.h @@ -0,0 +1,47 @@ +/* + * Copyright (C) 2004-2010 Freescale Semiconductor, Inc. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file mx2fb.h + * + * @brief MX 25 LCD controller header file. + * + * + */ + +#ifndef __MX2FB_H__ +#define __MX2FB_H__ + + +/* LCDC register settings */ + +#define LCDC_LSCR 0x00120300 + +#define LCDC_LRMCR 0x00000000 + +#define LCDC_LDCR 0x00020010 + +#define LCDC_LPCCR 0x00a9037f + +#define LCDC_LPCR 0xFA008B80 + +#define LCDC_LPCR_PCD 0x4 + +#define FB_SYNC_OE_LOW_ACT 0x80000000 +#define FB_SYNC_CLK_LAT_FALL 0x40000000 +#define FB_SYNC_DATA_INVERT 0x20000000 +#define FB_SYNC_CLK_IDLE_EN 0x10000000 +#define FB_SYNC_SHARP_MODE 0x08000000 +#define FB_SYNC_SWAP_RGB 0x04000000 + +#endif /* __MX2FB_H__ */ diff --git a/include/mxc_keyb.h b/include/mxc_keyb.h new file mode 100644 index 0000000000..a4b0a4e75a --- /dev/null +++ b/include/mxc_keyb.h @@ -0,0 +1,201 @@ +/* + * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @defgroup keypad Keypad Driver + */ + +/*! + * @file mxc_keyb.h + * + * @brief MXC keypad header file. + * + * @ingroup keypad + */ +#ifndef __MXC_KEYB_H__ +#define __MXC_KEYB_H__ + +/*! + * Keypad Module Name + */ +#define MOD_NAME "mxckpd" + +/*! + * Keypad irq number + */ +#define KPP_IRQ MXC_INT_KPP + +/*! + * XLATE mode selection + */ +#define KEYPAD_XLATE 0 + +/*! + * RAW mode selection + */ +#define KEYPAD_RAW 1 + +/*! + * Maximum number of keys. + */ +#define MAXROW 8 +#define MAXCOL 8 +#define MXC_MAXKEY (MAXROW * MAXCOL) + +/*! + * This define indicates break scancode for every key release. A constant + * of 128 is added to the key press scancode. + */ +#define MXC_KEYRELEASE 128 + +/* + * _reg_KPP_KPCR _reg_KPP_KPSR _reg_KPP_KDDR _reg_KPP_KPDR + * Keypad Control Register Address + */ +#define KPCR (KPP_BASE_ADDR + 0x00) + +/* + * Keypad Status Register Address + */ +#define KPSR (KPP_BASE_ADDR + 0x02) + +/* + * Keypad Data Direction Address + */ +#define KDDR (KPP_BASE_ADDR + 0x04) + +/* + * Keypad Data Register + */ +#define KPDR (KPP_BASE_ADDR + 0x06) + +/* + * Key Press Interrupt Status bit + */ +#define KBD_STAT_KPKD 0x01 + +/* + * Key Release Interrupt Status bit + */ +#define KBD_STAT_KPKR 0x02 + +/* + * Key Depress Synchronizer Chain Status bit + */ +#define KBD_STAT_KDSC 0x04 + +/* + * Key Release Synchronizer Status bit + */ +#define KBD_STAT_KRSS 0x08 + +/* + * Key Depress Interrupt Enable Status bit + */ +#define KBD_STAT_KDIE 0x100 + +/* + * Key Release Interrupt Enable + */ +#define KBD_STAT_KRIE 0x200 + +/* + * Keypad Clock Enable + */ +#define KBD_STAT_KPPEN 0x400 + +/*! + * Buffer size of keypad queue. Should be a power of 2. + */ +#define KPP_BUF_SIZE 128 + +/*! + * Test whether bit is set for integer c + */ +#define TEST_BIT(c, n) ((c) & (0x1 << (n))) + +/*! + * Set nth bit in the integer c + */ +#define BITSET(c, n) ((c) | (1 << (n))) + +/*! + * Reset nth bit in the integer c + */ +#define BITRESET(c, n) ((c) & ~(1 << (n))) + +enum KeyEvent { + KDepress, + KRelease +}; + +/*! + * This enum represents the keypad state machine to maintain debounce logic + * for key press/release. + */ +enum KeyState { + + /*! + * Key press state. + */ + KStateUp, + + /*! + * Key press debounce state. + */ + KStateFirstDown, + + /*! + * Key release state. + */ + KStateDown, + + /*! + * Key release debounce state. + */ + KStateFirstUp +}; + +/*! + * Keypad Private Data Structure + */ +typedef struct keypad_priv { + + /*! + * Keypad state machine. + */ + enum KeyState iKeyState; + + /*! + * Number of rows configured in the keypad matrix + */ + unsigned long kpp_rows; + + /*! + * Number of Columns configured in the keypad matrix + */ + unsigned long kpp_cols; +} keypad_priv; + +/*! + * Keypad Data Structure + * */ +struct kpp_key_info { + enum KeyEvent evt; + unsigned short val; +}; + +int mxc_kpp_init(void); +int mxc_kpp_getc(struct kpp_key_info *); + +#endif /* __MXC_KEYB_H__ */ diff --git a/include/nand.h b/include/nand.h index 2a81597a65..43381666a2 100644 --- a/include/nand.h +++ b/include/nand.h @@ -30,7 +30,7 @@ extern void nand_init(void); #include #include -extern int board_nand_init(struct nand_chip *nand); +extern int board_nand_init(struct mtd_info *mtd, struct nand_chip *nand); typedef struct mtd_info nand_info_t; diff --git a/include/net.h b/include/net.h index 4873000c0d..17279f7bc3 100644 --- a/include/net.h +++ b/include/net.h @@ -105,6 +105,7 @@ struct eth_device { #ifdef CONFIG_MCAST_TFTP int (*mcast) (struct eth_device*, u32 ip, u8 set); #endif + int (*write_hwaddr) (struct eth_device *); struct eth_device *next; void *priv; }; diff --git a/include/pata.h b/include/pata.h new file mode 100644 index 0000000000..ef1481002b --- /dev/null +++ b/include/pata.h @@ -0,0 +1,35 @@ +#ifndef __PATA_H__ +#define __PATA_H__ + +/* + * (C) Copyright 2008-2009 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +int init_pata(int dev); +int scan_pata(int dev); +ulong pata_read(int dev, ulong blknr, ulong blkcnt, void *buffer); +ulong pata_write(int dev, ulong blknr, ulong blkcnt, const void *buffer); + +int pata_initialize(); + +#endif diff --git a/include/wince.h b/include/wince.h new file mode 100644 index 0000000000..9a80f3758e --- /dev/null +++ b/include/wince.h @@ -0,0 +1,450 @@ +#ifndef __WINCE_H__ +#define __WINCE_H__ + +#define CE_DOFFSET (net->align_offset + ETHER_HDR_SIZE + IP_HDR_SIZE) + +/* Bin image parse results */ + +#define CE_PR_EOF 0 +#define CE_PR_MORE 1 +#define CE_PR_ERROR 2 + + + + +#pragma pack(1) + +/* Edbg BOOTME packet structures */ + +typedef struct +{ + unsigned int id; /* Protocol identifier ("EDBG" on the wire) */ + unsigned char service; /* Service identifier */ + unsigned char flags; /* Flags (see defs below) */ + unsigned char seqNum; /* For detection of dropped packets */ + unsigned char cmd; /* For administrative messages */ + unsigned char data[1]; /* Cmd specific data starts here (format is determined by */ + /* Cmd, len is determined by UDP packet size) */ +} +eth_dbg_hdr; + +#define OFFSETOF(s,m) ((unsigned int)&(((s*)0)->m)) +#define EDBG_DATA_OFFSET (OFFSETOF(eth_dbg_hdr, data)) + +typedef struct +{ + unsigned char versionMajor; // Bootloader version + unsigned char versionMinor; // Bootloader version + unsigned char macAddr[6]; // Ether address of device (net byte order) + unsigned int ipAddr; // IP address of device (net byte order) + char platformId[17]; // Platform Id string (NULL terminated) + char deviceName[17]; // Device name string (NULL terminated). Should include + // platform and number based on Ether address (e.g. Odo42, CEPCLS2346, etc) + unsigned char cpuId; // CPU identifier (upper nibble = type) + // The following fields were added in CE 3.0 Platform Builder release + unsigned char bootmeVer; // BOOTME Version. Must be in the range 2 -> EDBG_CURRENT_BOOTME_VERSION, or + // remaining fields will be ignored by Eshell and defaults will be used. + unsigned int bootFlags; // Boot Flags + unsigned short downloadPort; // Download Port (net byte order) (0 -> EDBG_DOWNLOAD_PORT) + unsigned short svcPort; // Service Port (net byte order) (0 -> EDBG_SVC_PORT) + +} edbg_bootme_data; + +// Packet size + +#define BOOTME_PKT_SIZE (EDBG_DATA_OFFSET + sizeof(edbg_bootme_data)) + +// WinCE .BIN file format signature + +#define CE_BIN_SIGN "B000FF\x0A" +#define CE_BIN_SIGN_LEN 7 + + +typedef struct +{ + unsigned char sign[ CE_BIN_SIGN_LEN ]; + unsigned int rtiPhysAddr; + unsigned int rtiPhysLen; +} +ce_bin_hdr; + +typedef struct +{ + unsigned int physAddr; + unsigned int physLen; + unsigned int chkSum; + unsigned char data[ 1 ]; +} +ce_bin_entry; + +// CE ROM image structures + +#define ROM_SIGNATURE_OFFSET 0x40 // Offset from the image's physfirst address to the ROM signature. +#define ROM_SIGNATURE 0x43454345 // Signature +#define ROM_TOC_POINTER_OFFSET 0x44 // Offset from the image's physfirst address to the TOC pointer. +#define ROM_TOC_OFFSET_OFFSET 0x48 // Offset from the image's physfirst address to the TOC offset (from physfirst). + +typedef struct +{ + unsigned int dllfirst; // first DLL address + unsigned int dlllast; // last DLL address + unsigned int physfirst; // first physical address + unsigned int physlast; // highest physical address + unsigned int nummods; // number of TOCentry's + unsigned int ramStart; // start of RAM + unsigned int ramFree; // start of RAM free space + unsigned int ramEnd; // end of RAM + unsigned int copyEntries; // number of copy section entries + unsigned int copyOffset; // offset to copy section + unsigned int profileLen; // length of PROFentries RAM + unsigned int profileOffset; // offset to PROFentries + unsigned int numfiles; // number of FILES + unsigned int kernelFlags; // optional kernel flags from ROMFLAGS .bib config option + unsigned int fsRamPercent; // Percentage of RAM used for filesystem + // from FSRAMPERCENT .bib config option + // byte 0 = #4K chunks/Mbyte of RAM for filesystem 0-2Mbytes 0-255 + // byte 1 = #4K chunks/Mbyte of RAM for filesystem 2-4Mbytes 0-255 + // byte 2 = #4K chunks/Mbyte of RAM for filesystem 4-6Mbytes 0-255 + // byte 3 = #4K chunks/Mbyte of RAM for filesystem > 6Mbytes 0-255 + + unsigned int drivglobStart; // device driver global starting address + unsigned int drivglobLen; // device driver global length + unsigned short cpuType; // CPU (machine) Type + unsigned short miscFlags; // Miscellaneous flags + void* extensions; // pointer to ROM Header extensions + unsigned int trackingStart; // tracking memory starting address + unsigned int trackingLen; // tracking memory ending address +} +ce_rom_hdr; + +// Win32 FILETIME strcuture + +typedef struct +{ + unsigned int loDateTime; + unsigned int hiDateTime; +} +ce_file_time; + +// Table Of Contents entry structure + +typedef struct +{ + unsigned int fileAttributes; + ce_file_time fileTime; + unsigned int fileSize; + char* fileName; + unsigned int e32Offset; // Offset to E32 structure + unsigned int o32Offset; // Offset to O32 structure + unsigned int loadOffset; // MODULE load buffer offset +} +ce_toc_entry; + +typedef struct +{ /* Extra information header block */ + unsigned int rva; /* Virtual relative address of info */ + unsigned int size; /* Size of information block */ +} +e32_info; + +#define ROM_EXTRA 9 + +typedef struct +{ + unsigned short e32_objcnt; /* Number of memory objects */ + unsigned short e32_imageflags; /* Image flags */ + unsigned int e32_entryrva; /* Relative virt. addr. of entry point */ + unsigned int e32_vbase; /* Virtual base address of module */ + unsigned short e32_subsysmajor;/* The subsystem major version number */ + unsigned short e32_subsysminor;/* The subsystem minor version number */ + unsigned int e32_stackmax; /* Maximum stack size */ + unsigned int e32_vsize; /* Virtual size of the entire image */ + unsigned int e32_sect14rva; /* section 14 rva */ + unsigned int e32_sect14size; /* section 14 size */ + unsigned int e32_timestamp; /* Time EXE/DLL was created/modified */ + e32_info e32_unit[ ROM_EXTRA ]; /* Array of extra info units */ + unsigned short e32_subsys; /* The subsystem type */ +} +e32_rom; + + + +// OS config msg + +#define EDBG_FL_DBGMSG 0x01 // Debug messages +#define EDBG_FL_PPSH 0x02 // Text shell +#define EDBG_FL_KDBG 0x04 // Kernel debugger +#define EDBG_FL_CLEANBOOT 0x08 // Force a clean boot + +typedef struct +{ + unsigned char flags; // Flags that will be used to determine what features are + // enabled over ethernet (saved in driver globals by bootloader) + unsigned char kitlTransport; // Tells KITL which transport to start + + // The following specify addressing info, only valid if the corresponding + // flag is set in the Flags field. + + unsigned int dbgMsgIPAddr; + unsigned short dbgMsgPort; + unsigned int ppshIPAddr; + unsigned short ppshPort; + unsigned int kdbgIPAddr; + unsigned short kdbgPort; + +} edbg_os_config_data; + + + +// Driver globals structure +// Used to pass driver globals info from RedBoot to WinCE core + +#define DRV_GLB_SIGNATURE 0x424C4744 // "DGLB" + +typedef struct +{ + unsigned int signature; // Signature + unsigned int flags; // Misc flags + unsigned int ipAddr; // IP address of device (net byte order) + unsigned int ipGate; // IP address of gateway (net byte order) + unsigned int ipMask; // Subnet mask + unsigned char macAddr[6]; // Ether address of device (net byte order) + edbg_os_config_data edbgConfig; // EDBG services info +} +ce_driver_globals; + + +#pragma pack() + + + +typedef struct +{ + unsigned int rtiPhysAddr; + unsigned int rtiPhysLen; + unsigned int ePhysAddr; + unsigned int ePhysLen; + unsigned int eChkSum; + + unsigned int eEntryPoint; + unsigned int eRamStart; + unsigned int eRamLen; + unsigned int eDrvGlb; + + unsigned char parseState; + unsigned int parseChkSum; + int parseLen; + unsigned char* parsePtr; + int secion; + + int dataLen; + unsigned char* data; + + int binLen; + int endOfBin; + + edbg_os_config_data edbgConfig; +} +ce_bin; + + + + + + + + +// IPv4 support + +// Socket/connection information +struct sockaddr_in { + IPaddr_t sin_addr; + unsigned short sin_port; + unsigned short sin_family; + short sin_len; +}; +#define AF_INET 1 +#define INADDR_ANY 0 + + + + + + + + + +typedef struct +{ + int verbose; + int link; + struct sockaddr_in locAddr; + struct sockaddr_in srvAddrSend; + struct sockaddr_in srvAddrRecv; + int gotJumpingRequest; + unsigned char secNum; + unsigned short blockNum; + int dataLen; + int align_offset; + int got_packet_4me; + unsigned char data[PKTSIZE_ALIGN]; +} +ce_net; + + +struct timeval { + long tv_sec; /* seconds */ + long tv_usec; /* and microseconds */ +}; + + + +// Default UDP ports used for Ethernet download and EDBG messages. May be overriden +// by device in BOOTME message. + +#define EDBG_DOWNLOAD_PORT 980 // For downloading images to bootloader via TFTP +#define EDBG_SVC_PORT 981 // Other types of transfers + +// Byte string for Id field (note - must not conflict with valid TFTP +// opcodes (0-5), as we share the download port with TFTP) + +#define EDBG_ID 0x47424445 // "EDBG" + +// Defs for reserved values of the Service field + +#define EDBG_SVC_DBGMSG 0 // Debug messages +#define EDBG_SVC_PPSH 1 // Text shell and PPFS file system +#define EDBG_SVC_KDBG 2 // Kernel debugger +#define EDBG_SVC_ADMIN 0xFF // Administrative messages + +// Commands + +#define EDBG_CMD_READ_REQ 1 // Read request +#define EDBG_CMD_WRITE_REQ 2 // Write request +#define EDBG_CMD_WRITE 3 // Host ack +#define EDBG_CMD_WRITE_ACK 4 // Target ack +#define EDBG_CMD_ERROR 5 // Error + +// Service Ids from 3-FE are used for user apps + +#define NUM_DFLT_EDBG_SERVICES 3 + +// Size of send and receive windows (except for stop and wait mode) + +#define EDBG_WINDOW_SIZE 8 + +// The window size can be negotiated up to this amount if a client provides +// enough memory. +#define EDBG_MAX_WINDOW_SIZE 16 + +// Max size for an EDBG frame. Based on ethernet MTU - protocol overhead. +// Limited to one MTU because we don't do IP fragmentation on device. + +#define EDBG_MAX_DATA_SIZE 1446 + +// Defs for Flags field. +#define EDBG_FL_FROM_DEV 0x01 // Set if message is from the device +#define EDBG_FL_NACK 0x02 // Set if frame is a nack +#define EDBG_FL_ACK 0x04 // Set if frame is an ack +#define EDBG_FL_SYNC 0x08 // Can be used to reset sequence # to 0 +#define EDBG_FL_ADMIN_RESP 0x10 // For admin messages, indicate whether this is a response + +// Definitions for Cmd field (used for administrative messages) +// Msgs from device + +#define EDBG_CMD_BOOTME 0 // Initial bootup message from device + +// Msgs from PC + +#define EDBG_CMD_SETDEBUG 1 // Used to set debug zones on device (TBD) +#define EDBG_CMD_JUMPIMG 2 // Command to tell bootloader to jump to existing + // flash or RAM image. Data is same as CMD_OS_CONFIG. +#define EDBG_CMD_OS_CONFIG 3 // Configure OS for debug ethernet services +#define EDBG_CMD_QUERYINFO 4 // "Ping" device, and return information (same fmt as bootme) +#define EDBG_CMD_RESET 5 // Command to have platform perform SW reset (e.g. so it + // can be reprogrammed). Support for this command is + // processor dependant, and may not be implemented + // on all platforms (requires HW mods for Odo). + +// Msgs from device or PC + +#define EDBG_CMD_SVC_CONFIG 6 +#define EDBG_CMD_SVC_DATA 7 + +#define EDBG_CMD_DEBUGBREAK 8 // Break into debugger + +// Structures for Data portion of EDBG packets + +#define EDBG_MAX_DEV_NAMELEN 16 + +// BOOTME message - Devices broadcast this message when booted to request configuration + +#define EDBG_CURRENT_BOOTME_VERSION 2 + +// +// Capability and boot Flags for dwBootFlags in EDBG_BOOTME_DATA +// LOWORD for boot flags, HIWORD for capability flags +// + +// Always download image + +#define EDBG_BOOTFLAG_FORCE_DOWNLOAD 0x00000001 + +// Support passive-kitl + +#define EDBG_CAPS_PASSIVEKITL 0x00010000 + +// Defs for CPUId + +#define EDBG_CPU_TYPE_SHX 0x10 +#define EDBG_CPU_TYPE_MIPS 0x20 +#define EDBG_CPU_TYPE_X86 0x30 +#define EDBG_CPU_TYPE_ARM 0x40 +#define EDBG_CPU_TYPE_PPC 0x50 +#define EDBG_CPU_TYPE_THUMB 0x60 + +#define EDBG_CPU_SH3 (EDBG_CPU_TYPE_SHX | 0) +#define EDBG_CPU_SH4 (EDBG_CPU_TYPE_SHX | 1) +#define EDBG_CPU_R3000 (EDBG_CPU_TYPE_MIPS | 0) +#define EDBG_CPU_R4101 (EDBG_CPU_TYPE_MIPS | 1) +#define EDBG_CPU_R4102 (EDBG_CPU_TYPE_MIPS | 2) +#define EDBG_CPU_R4111 (EDBG_CPU_TYPE_MIPS | 3) +#define EDBG_CPU_R4200 (EDBG_CPU_TYPE_MIPS | 4) +#define EDBG_CPU_R4300 (EDBG_CPU_TYPE_MIPS | 5) +#define EDBG_CPU_R5230 (EDBG_CPU_TYPE_MIPS | 6) +#define EDBG_CPU_R5432 (EDBG_CPU_TYPE_MIPS | 7) +#define EDBG_CPU_i486 (EDBG_CPU_TYPE_X86 | 0) +#define EDBG_CPU_SA1100 (EDBG_CPU_TYPE_ARM | 0) +#define EDBG_CPU_ARM720 (EDBG_CPU_TYPE_ARM | 1) +#define EDBG_CPU_PPC821 (EDBG_CPU_TYPE_PPC | 0) +#define EDBG_CPU_PPC403 (EDBG_CPU_TYPE_PPC | 1) +#define EDBG_CPU_THUMB720 (EDBG_CPU_TYPE_THUMB | 0) + + + +#endif + + +int ce_bin_load(void* image, int imglen); +int ce_is_bin_image(void* image, int imglen); +void ce_bin_init_parser(void); +int ce_bin_parse_next(void* parseBuffer, int len); +void ce_init_bin(ce_bin* bin, unsigned char* dataBuffer); +int ce_parse_bin(ce_bin* bin); +int ce_lookup_ep_bin(ce_bin* bin); +void ce_prepare_run_bin(ce_bin* bin); +void ce_run_bin(ce_bin* bin); + +int ce_recv_frame(ce_net* net, int timeout); +int ce_process_download(ce_net* net, ce_bin* bin); +void ce_init_edbg_link(ce_net* net); +void ce_process_edbg(ce_net* net, ce_bin* bin); + +int ce_recv_frame(ce_net* net, int timeout); +int ce_process_download(ce_net* net, ce_bin* bin); +void ce_init_edbg_link(ce_net* net); +void ce_process_edbg(ce_net* net, ce_bin* bin); +int ce_send_write_ack(ce_net* net); +int ce_send_frame(ce_net* net); +int ce_recv_packet(char *buf, int len, struct sockaddr_in *from, struct sockaddr_in *local, struct timeval *timeout); +void ce_dump_block(unsigned char *ptr, int length); diff --git a/lib_arm/Makefile b/lib_arm/Makefile index 02933485cd..6b1561be98 100644 --- a/lib_arm/Makefile +++ b/lib_arm/Makefile @@ -39,9 +39,6 @@ GLCOBJS += div0.o COBJS-y += board.o COBJS-y += bootm.o COBJS-y += cache.o -ifndef CONFIG_SYS_NO_CP15_CACHE -COBJS-y += cache-cp15.o -endif COBJS-y += interrupts.o COBJS-y += reset.o diff --git a/lib_arm/board.c b/lib_arm/board.c index a44d308f67..6b89c249d0 100644 --- a/lib_arm/board.c +++ b/lib_arm/board.c @@ -74,11 +74,11 @@ const char version_string[] = U_BOOT_VERSION" (" U_BOOT_DATE " - " U_BOOT_TIME ")"CONFIG_IDENT_STRING; #ifdef CONFIG_DRIVER_CS8900 -extern void cs8900_get_enetaddr (void); +extern void cs8900_get_enetaddr(void); #endif #ifdef CONFIG_DRIVER_RTL8019 -extern void rtl8019_get_enetaddr (uchar * addr); +extern void rtl8019_get_enetaddr(uchar * addr); #endif #if defined(CONFIG_HARD_I2C) || \ @@ -89,32 +89,32 @@ extern void rtl8019_get_enetaddr (uchar * addr); /* * Begin and End of memory area for malloc(), and current "brk" */ -static ulong mem_malloc_start = 0; -static ulong mem_malloc_end = 0; -static ulong mem_malloc_brk = 0; +static void *mem_malloc_start; +static void *mem_malloc_end; +static void *mem_malloc_brk; static -void mem_malloc_init (ulong dest_addr) +void mem_malloc_init(void *dest_addr) { mem_malloc_start = dest_addr; mem_malloc_end = dest_addr + CONFIG_SYS_MALLOC_LEN; mem_malloc_brk = mem_malloc_start; - memset ((void *) mem_malloc_start, 0, - mem_malloc_end - mem_malloc_start); + memset(mem_malloc_start, 0, + mem_malloc_end - mem_malloc_start); } -void *sbrk (ptrdiff_t increment) +void *sbrk(ptrdiff_t increment) { - ulong old = mem_malloc_brk; - ulong new = old + increment; + void *old = mem_malloc_brk; + void *new = old + increment; if ((new < mem_malloc_start) || (new > mem_malloc_end)) { - return (NULL); + return NULL; } mem_malloc_brk = new; - return ((void *) old); + return old; } @@ -123,24 +123,24 @@ void *sbrk (ptrdiff_t increment) ************************************************************************ * May be supplied by boards if desired */ -void inline __coloured_LED_init (void) {} -void inline coloured_LED_init (void) __attribute__((weak, alias("__coloured_LED_init"))); -void inline __red_LED_on (void) {} -void inline red_LED_on (void) __attribute__((weak, alias("__red_LED_on"))); -void inline __red_LED_off(void) {} -void inline red_LED_off(void) __attribute__((weak, alias("__red_LED_off"))); -void inline __green_LED_on(void) {} -void inline green_LED_on(void) __attribute__((weak, alias("__green_LED_on"))); -void inline __green_LED_off(void) {} -void inline green_LED_off(void)__attribute__((weak, alias("__green_LED_off"))); -void inline __yellow_LED_on(void) {} -void inline yellow_LED_on(void)__attribute__((weak, alias("__yellow_LED_on"))); -void inline __yellow_LED_off(void) {} -void inline yellow_LED_off(void)__attribute__((weak, alias("__yellow_LED_off"))); -void inline __blue_LED_on(void) {} -void inline blue_LED_on(void)__attribute__((weak, alias("__blue_LED_on"))); -void inline __blue_LED_off(void) {} -void inline blue_LED_off(void)__attribute__((weak, alias("__blue_LED_off"))); +void __coloured_LED_init(void) {} +void coloured_LED_init(void) __attribute__((weak, alias("__coloured_LED_init"))); +void __red_LED_on(void) {} +void red_LED_on(void) __attribute__((weak, alias("__red_LED_on"))); +void __red_LED_off(void) {} +void red_LED_off(void) __attribute__((weak, alias("__red_LED_off"))); +void __green_LED_on(void) {} +void green_LED_on(void) __attribute__((weak, alias("__green_LED_on"))); +void __green_LED_off(void) {} +void green_LED_off(void)__attribute__((weak, alias("__green_LED_off"))); +void __yellow_LED_on(void) {} +void yellow_LED_on(void)__attribute__((weak, alias("__yellow_LED_on"))); +void __yellow_LED_off(void) {} +void yellow_LED_off(void)__attribute__((weak, alias("__yellow_LED_off"))); +void __blue_LED_on(void) {} +void blue_LED_on(void)__attribute__((weak, alias("__blue_LED_on"))); +void __blue_LED_off(void) {} +void blue_LED_off(void)__attribute__((weak, alias("__blue_LED_off"))); /************************************************************************ * Init Utilities * @@ -153,31 +153,32 @@ void inline blue_LED_off(void)__attribute__((weak, alias("__blue_LED_off"))); #if defined(CONFIG_ARM_DCC) && !defined(CONFIG_BAUDRATE) #define CONFIG_BAUDRATE 115200 #endif -static int init_baudrate (void) +static int init_baudrate(void) { char tmp[64]; /* long enough for environment variables */ - int i = getenv_r ("baudrate", tmp, sizeof (tmp)); - gd->bd->bi_baudrate = gd->baudrate = (i > 0) - ? (int) simple_strtoul (tmp, NULL, 10) - : CONFIG_BAUDRATE; + int i = getenv_r("baudrate", tmp, sizeof(tmp)); - return (0); + gd->bd->bi_baudrate = gd->baudrate = (i > 0) ? + (int)simple_strtoul(tmp, NULL, 10) : + CONFIG_BAUDRATE; + + return 0; } -static int display_banner (void) +static int display_banner(void) { - printf ("\n\n%s\n\n", version_string); - debug ("U-Boot code: %08lX -> %08lX BSS: -> %08lX\n", + printf("\n\n%s\n\n", version_string); + debug("U-Boot code: %08lX -> %08lX BSS: -> %08lX\n", _armboot_start, _bss_start, _bss_end); #ifdef CONFIG_MODEM_SUPPORT - debug ("Modem Support enabled\n"); + debug("Modem Support enabled\n"); #endif #ifdef CONFIG_USE_IRQ - debug ("IRQ Stack: %08lx\n", IRQ_STACK_START); - debug ("FIQ Stack: %08lx\n", FIQ_STACK_START); + debug("IRQ Stack: %08lx\n", IRQ_STACK_START); + debug("FIQ Stack: %08lx\n", FIQ_STACK_START); #endif - return (0); + return 0; } /* @@ -187,49 +188,49 @@ static int display_banner (void) * gives a simple yet clear indication which part of the * initialization if failing. */ -static int display_dram_config (void) +static int display_dram_config(void) { int i; #ifdef DEBUG - puts ("RAM Configuration:\n"); + puts("RAM Configuration:\n"); - for(i=0; ibd->bi_dram[i].start); - print_size (gd->bd->bi_dram[i].size, "\n"); + for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { + printf("Bank #%d: %08lx ", i, gd->bd->bi_dram[i].start); + print_size(gd->bd->bi_dram[i].size, "\n"); } #else ulong size = 0; - for (i=0; ibd->bi_dram[i].size; } puts("DRAM: "); print_size(size, "\n"); #endif - return (0); + return 0; } #ifndef CONFIG_SYS_NO_FLASH -static void display_flash_config (ulong size) +static void display_flash_config(ulong size) { - puts ("Flash: "); - print_size (size, "\n"); + puts("Flash: "); + print_size(size, "\n"); } #endif /* CONFIG_SYS_NO_FLASH */ #if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C) -static int init_func_i2c (void) +static int init_func_i2c(void) { - puts ("I2C: "); - i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); - puts ("ready\n"); + puts("I2C: "); + i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); + puts("ready\n"); return (0); } #endif -#if defined(CONFIG_CMD_PCI) || defined (CONFIG_PCI) +#if defined(CONFIG_CMD_PCI) || defined(CONFIG_PCI) #include static int arm_pci_init(void) { @@ -261,9 +262,9 @@ static int arm_pci_init(void) * argument, and returns an integer return code, where 0 means * "continue" and != 0 means "fatal error, hang the system". */ -typedef int (init_fnc_t) (void); +typedef int (init_fnc_t)(void); -int print_cpuinfo (void); +int print_cpuinfo(void); init_fnc_t *init_sequence[] = { #if defined(CONFIG_ARCH_CPU_INIT) @@ -289,14 +290,14 @@ init_fnc_t *init_sequence[] = { init_func_i2c, #endif dram_init, /* configure available RAM banks */ -#if defined(CONFIG_CMD_PCI) || defined (CONFIG_PCI) +#if defined(CONFIG_CMD_PCI) || defined(CONFIG_PCI) arm_pci_init, #endif display_dram_config, NULL, }; -void start_armboot (void) +void start_armboot(void) { init_fnc_t **init_fnc_ptr; char *s; @@ -309,9 +310,9 @@ void start_armboot (void) /* compiler optimization barrier needed for GCC >= 3.4 */ __asm__ __volatile__("": : :"memory"); - memset ((void*)gd, 0, sizeof (gd_t)); + memset((void *)gd, 0, sizeof(gd_t)); gd->bd = (bd_t*)((char*)gd - sizeof(bd_t)); - memset (gd->bd, 0, sizeof (bd_t)); + memset(gd->bd, 0, sizeof(bd_t)); gd->flags |= GD_FLG_RELOC; @@ -319,16 +320,16 @@ void start_armboot (void) for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) { if ((*init_fnc_ptr)() != 0) { - hang (); + hang(); } } /* armboot_start is defined in the board-specific linker script */ - mem_malloc_init (_armboot_start - CONFIG_SYS_MALLOC_LEN); + mem_malloc_init((void *)(_armboot_start - CONFIG_SYS_MALLOC_LEN)); #ifndef CONFIG_SYS_NO_FLASH /* configure available FLASH banks */ - display_flash_config (flash_init ()); + display_flash_config(flash_init()); #endif /* CONFIG_SYS_NO_FLASH */ #ifdef CONFIG_VFD @@ -340,7 +341,7 @@ void start_armboot (void) */ /* bss_end is defined in the board-specific linker script */ addr = (_bss_end + (PAGE_SIZE - 1)) & ~(PAGE_SIZE - 1); - vfd_setmem (addr); + vfd_setmem(addr); gd->fb_base = addr; #endif /* CONFIG_VFD */ @@ -355,13 +356,13 @@ void start_armboot (void) */ /* bss_end is defined in the board-specific linker script */ addr = (_bss_end + (PAGE_SIZE - 1)) & ~(PAGE_SIZE - 1); - lcd_setmem (addr); + lcd_setmem(addr); gd->fb_base = addr; } #endif /* CONFIG_LCD */ #if defined(CONFIG_CMD_NAND) - puts ("NAND: "); + puts("NAND: "); nand_init(); /* go init the NAND */ #endif @@ -374,8 +375,13 @@ void start_armboot (void) dataflash_print_info(); #endif +#ifdef CONFIG_GENERIC_MMC + puts("MMC: "); + mmc_initialize(gd->bd); +#endif + /* initialize environment */ - env_relocate (); + env_relocate(); #ifdef CONFIG_VFD /* must do this after the framebuffer is allocated */ @@ -387,36 +393,36 @@ void start_armboot (void) #endif /* IP Address */ - gd->bd->bi_ip_addr = getenv_IPaddr ("ipaddr"); + gd->bd->bi_ip_addr = getenv_IPaddr("ipaddr"); - stdio_init (); /* get the devices list going. */ + stdio_init(); /* get the devices list going. */ - jumptable_init (); + jumptable_init(); #if defined(CONFIG_API) /* Initialize API */ - api_init (); + api_init(); #endif - console_init_r (); /* fully init console as a device */ + console_init_r(); /* fully init console as a device */ #if defined(CONFIG_ARCH_MISC_INIT) /* miscellaneous arch dependent initialisations */ - arch_misc_init (); + arch_misc_init(); #endif #if defined(CONFIG_MISC_INIT_R) /* miscellaneous platform dependent initialisations */ - misc_init_r (); + misc_init_r(); #endif /* enable exceptions */ - enable_interrupts (); + enable_interrupts(); /* Perform network card initialisation if necessary */ #ifdef CONFIG_DRIVER_TI_EMAC /* XXX: this needs to be moved to board init */ -extern void davinci_eth_set_mac_addr (const u_int8_t *addr); - if (getenv ("ethaddr")) { +extern void davinci_eth_set_mac_addr(const u_int8_t *addr); + if (getenv("ethaddr")) { uchar enetaddr[6]; eth_getenv_enetaddr("ethaddr", enetaddr); davinci_eth_set_mac_addr(enetaddr); @@ -425,57 +431,57 @@ extern void davinci_eth_set_mac_addr (const u_int8_t *addr); #ifdef CONFIG_DRIVER_CS8900 /* XXX: this needs to be moved to board init */ - cs8900_get_enetaddr (); + cs8900_get_enetaddr(); #endif -#if defined(CONFIG_DRIVER_SMC91111) || defined (CONFIG_DRIVER_LAN91C96) +#if defined(CONFIG_DRIVER_SMC91111) || defined(CONFIG_DRIVER_LAN91C96) /* XXX: this needs to be moved to board init */ - if (getenv ("ethaddr")) { + if (getenv("ethaddr")) { uchar enetaddr[6]; eth_getenv_enetaddr("ethaddr", enetaddr); smc_set_mac_addr(enetaddr); } #endif /* CONFIG_DRIVER_SMC91111 || CONFIG_DRIVER_LAN91C96 */ +#if defined(CONFIG_ENC28J60_ETH) && !defined(CONFIG_ETHADDR) + extern void enc_set_mac_addr(void); + enc_set_mac_addr(); +#endif /* CONFIG_ENC28J60_ETH && !CONFIG_ETHADDR*/ + /* Initialize from environment */ - if ((s = getenv ("loadaddr")) != NULL) { - load_addr = simple_strtoul (s, NULL, 16); + if ((s = getenv("loadaddr")) != NULL) { + load_addr = simple_strtoul(s, NULL, 16); } #if defined(CONFIG_CMD_NET) - if ((s = getenv ("bootfile")) != NULL) { - copy_filename (BootFile, s, sizeof (BootFile)); + if ((s = getenv("bootfile")) != NULL) { + copy_filename(BootFile, s, sizeof(BootFile)); } #endif #ifdef BOARD_LATE_INIT - board_late_init (); -#endif - -#ifdef CONFIG_GENERIC_MMC - puts ("MMC: "); - mmc_initialize (gd->bd); + board_late_init(); #endif #if defined(CONFIG_CMD_NET) #if defined(CONFIG_NET_MULTI) - puts ("Net: "); + puts("Net: "); #endif eth_initialize(gd->bd); #if defined(CONFIG_RESET_PHY_R) - debug ("Reset Ethernet PHY\n"); + debug("Reset Ethernet PHY\n"); reset_phy(); #endif #endif /* main_loop() can return to retry autoboot, if so just run it again. */ for (;;) { - main_loop (); + main_loop(); } /* NOTREACHED - no way out of command loop except booting */ } -void hang (void) +void hang(void) { - puts ("### ERROR ### Please RESET the board ###\n"); + puts("### ERROR ### Please RESET the board ###\n"); for (;;); } diff --git a/lib_arm/eabi_compat.c b/lib_arm/eabi_compat.c index 86eacf1b0e..79dbe7dac7 100644 --- a/lib_arm/eabi_compat.c +++ b/lib_arm/eabi_compat.c @@ -16,3 +16,8 @@ int raise (int signum) printf("raise: Signal # %d caught\n", signum); return 0; } + +/* Dummy function to avoid linker complaints */ +void __aeabi_unwind_cpp_pr0(void) +{ +} diff --git a/lib_generic/vsprintf.c b/lib_generic/vsprintf.c index 3d95728efb..3eef5e8956 100644 --- a/lib_generic/vsprintf.c +++ b/lib_generic/vsprintf.c @@ -632,8 +632,29 @@ int vsprintf(char *buf, const char *fmt, va_list args) continue; } #ifdef CONFIG_SYS_64BIT_VSPRINTF - if (qualifier == 'L') /* "quad" for 64 bit variables */ - num = va_arg(args, unsigned long long); +#ifndef GCC_VERSION +#define GCC_VERSION (__GNUC__ * 1000 + __GNUC_MINOR__) +#endif + if (qualifier == 'L') /* "quad" for 64 bit variables */ +#if GCC_VERSION <= 3003 || GCC_VERSION > 4004 + /* gcc 3.3.2 handles this correctly + * at least gcc >= 4.3.4 and <= 4.4.1 misalign long long arguments on stack! + */ + num = va_arg(args, long long); +#else +#define get_addr(arg) ({ \ + unsigned long __sp; \ + asm volatile ("mov %0, %1" : "=r"(__sp) : "r"(arg)); \ + __sp; \ + }) + /* workaround for broken gcc */ + { + if (!(get_addr(args) & 0x7)) + num = va_arg(args, long); + num = va_arg(args, long); + num |= (unsigned long long)va_arg(args, long) << 32; + } +#endif else #endif if (qualifier == 'l') { diff --git a/net/eth.c b/net/eth.c index 9b503124fb..7adc9e6f16 100644 --- a/net/eth.c +++ b/net/eth.c @@ -1,5 +1,5 @@ /* - * (C) Copyright 2001-2004 + * (C) Copyright 2001-2010 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * See file CREDITS for list of people who contributed to this @@ -26,7 +26,6 @@ #include #include -#ifdef CONFIG_CMD_NET void eth_parse_enetaddr(const char *addr, uchar *enetaddr) { char *end; @@ -60,9 +59,16 @@ int eth_getenv_enetaddr_by_index(int index, uchar *enetaddr) sprintf(enetvar, index ? "eth%daddr" : "ethaddr", index); return eth_getenv_enetaddr(enetvar, enetaddr); } -#endif -#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI) +#ifdef CONFIG_NET_MULTI + +static int eth_mac_skip(int index) +{ + char enetvar[15]; + char *skip_state; + sprintf(enetvar, index ? "eth%dmacskip" : "ethmacskip", index); + return ((skip_state = getenv(enetvar)) != NULL); +} /* * CPU and board-specific Ethernet initializations. Aliased function @@ -175,7 +181,8 @@ int eth_register(struct eth_device* dev) } #endif } else { - for (d=eth_devices; d->next!=eth_devices; d=d->next); + for (d = eth_devices; d->next != eth_devices; d = d->next) + ; d->next = dev; } @@ -243,6 +250,11 @@ int eth_initialize(bd_t *bis) memcpy(dev->enetaddr, env_enetaddr, 6); } + if (dev->write_hwaddr && + !eth_mac_skip(eth_number) && + is_valid_ether_addr(dev->enetaddr)) { + dev->write_hwaddr(dev); + } eth_number++; dev = dev->next; @@ -492,7 +504,8 @@ char *eth_get_name (void) { return (eth_current ? eth_current->name : "unknown"); } -#elif defined(CONFIG_CMD_NET) && !defined(CONFIG_NET_MULTI) + +#else /* !CONFIG_NET_MULTI */ #warning Ethernet driver is deprecated. Please update to use CONFIG_NET_MULTI diff --git a/post/board/netta/dsp.c b/post/board/netta/dsp.c index 438ced553f..92e2a8f71b 100644 --- a/post/board/netta/dsp.c +++ b/post/board/netta/dsp.c @@ -22,7 +22,9 @@ */ #include +#include +#if defined(CONFIG_INTEGRATOR) || defined(CONFIG_MX25) /* * DSP test * diff --git a/tools/Makefile b/tools/Makefile index b5a1e39b02..9d4cf3af5f 100644 --- a/tools/Makefile +++ b/tools/Makefile @@ -150,6 +150,11 @@ CPPFLAGS = -idirafter $(SRCTREE)/include \ -D__KERNEL_STRICT_NAMES CFLAGS = $(HOSTCFLAGS) $(CPPFLAGS) -O +ifneq ($(BOOT_MEDIA),) + BOOT_MEDIA_MACRO := BOOT_MEDIA_$(shell echo $(BOOT_MEDIA) | tr '[a-z]' '[A-Z]') + CPPFLAGS += -D$(BOOT_MEDIA_MACRO) +endif + # No -pedantic switch to avoid libfdt compilation warnings FIT_CFLAGS = -Wall $(CPPFLAGS) -O -- 2.39.2