From d8a095039f4c7a58925bd2f481c50667af3f8c68 Mon Sep 17 00:00:00 2001
From: Peng Fan <Peng.Fan@freescale.com>
Date: Fri, 7 Aug 2015 16:43:41 +0800
Subject: [PATCH] power: pfuze100 correct SWBST macro definition

According to datasheet, SWBST_MODE starts from bit 2 and it occupies 2 bits.
So SWBST_MODE_MASK should be 0xC, and SWBST_MODE_xx should be ([mode] << 2).

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Przemyslaw Marczak <p.marczak@samsung.com>
Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
---
 include/power/pfuze100_pmic.h | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/include/power/pfuze100_pmic.h b/include/power/pfuze100_pmic.h
index 57b9ca94af..cb1060558a 100644
--- a/include/power/pfuze100_pmic.h
+++ b/include/power/pfuze100_pmic.h
@@ -193,11 +193,11 @@ enum {
 #define SWBST_5_15V	3
 
 #define SWBST_VOL_MASK	0x3
-#define SWBST_MODE_MASK	0x6
-#define SWBST_MODE_OFF	(2 << 0)
-#define SWBST_MODE_PFM	(2 << 1)
+#define SWBST_MODE_MASK	0xC
+#define SWBST_MODE_OFF	(0 << 2)
+#define SWBST_MODE_PFM	(1 << 2)
 #define SWBST_MODE_AUTO	(2 << 2)
-#define SWBST_MODE_APS	(2 << 3)
+#define SWBST_MODE_APS	(3 << 2)
 
 /*
  * Regulator Mode Control
-- 
2.39.2