From ef10f5faa7a37f6a7936ba840c4a308c924baff4 Mon Sep 17 00:00:00 2001 From: =?utf8?q?Lothar=20Wa=C3=9Fmann?= Date: Thu, 30 Jun 2016 11:35:07 +0200 Subject: [PATCH] mxs: spl: replace bogus early_delay() function with standard udelay() calls --- arch/arm/cpu/arm926ejs/mxs/mxs_init.h | 2 -- arch/arm/cpu/arm926ejs/mxs/spl_boot.c | 20 --------------- arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c | 10 ++++---- arch/arm/cpu/arm926ejs/mxs/spl_power_init.c | 28 ++++++++++----------- 4 files changed, 19 insertions(+), 41 deletions(-) diff --git a/arch/arm/cpu/arm926ejs/mxs/mxs_init.h b/arch/arm/cpu/arm926ejs/mxs/mxs_init.h index 1200ae1ad4..d32558f637 100644 --- a/arch/arm/cpu/arm926ejs/mxs/mxs_init.h +++ b/arch/arm/cpu/arm926ejs/mxs/mxs_init.h @@ -10,8 +10,6 @@ #ifndef __M28_INIT_H__ #define __M28_INIT_H__ -void early_delay(int delay); - void mxs_power_init(void); #ifdef CONFIG_SPL_MXS_PSWITCH_WAIT diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_boot.c b/arch/arm/cpu/arm926ejs/mxs/spl_boot.c index 7754a10380..82fa55f6f6 100644 --- a/arch/arm/cpu/arm926ejs/mxs/spl_boot.c +++ b/arch/arm/cpu/arm926ejs/mxs/spl_boot.c @@ -23,26 +23,6 @@ static gd_t gdata __section(".data"); static bd_t bdata __section(".data"); #endif -/* - * This delay function is intended to be used only in early stage of boot, where - * clock are not set up yet. The timer used here is reset on every boot and - * takes a few seconds to roll. The boot doesn't take that long, so to keep the - * code simple, it doesn't take rolling into consideration. - */ -/* - * There's nothing to be taken into consideration for the rollover. - * Two's complement arithmetic used correctly does all that's needed - * automagically. - */ -void early_delay(int delay) -{ - struct mxs_digctl_regs *digctl_regs = - (struct mxs_digctl_regs *)MXS_DIGCTL_BASE; - u32 start = readl(&digctl_regs->hw_digctl_microseconds); - - while (readl(&digctl_regs->hw_digctl_microseconds) - start < delay); -} - #define MUX_CONFIG_BOOTMODE_PAD (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL) static const iomux_cfg_t iomux_boot[] = { #if defined(CONFIG_SOC_MX23) diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c b/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c index 3427616fbe..bd72f36e21 100644 --- a/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c +++ b/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c @@ -254,12 +254,12 @@ static void mx23_mem_setup_vddmem(void) debug("SPL: Setting mx23 VDDMEM\n"); /* We must wait before and after disabling the current limiter! */ - early_delay(10000); + udelay(10000); clrbits_le32(&power_regs->hw_power_vddmemctrl, POWER_VDDMEMCTRL_ENABLE_ILIMIT); - early_delay(10000); + udelay(10000); } @@ -294,12 +294,12 @@ static void mx23_mem_init(void) for (;;) { if (!(readl(MXS_EMI_BASE + 0x10) & (1 << 1))) break; - early_delay(1000); + udelay(1000); } /* Adjust EMI port priority. */ clrsetbits_le32(0x80020000, 0x1f << 16, 0x2); - early_delay(20000); + udelay(20000); setbits_le32(MXS_DRAM_BASE + 0x40, 1 << 19); setbits_le32(MXS_DRAM_BASE + 0x40, 1 << 11); @@ -341,7 +341,7 @@ static void mx28_mem_init(void) void mxs_mem_init(void) { - early_delay(11000); + udelay(11000); mxs_mem_init_clock(); diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c b/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c index 561c04db27..6b5bf2d239 100644 --- a/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c +++ b/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c @@ -123,7 +123,7 @@ static void mxs_power_clock2pll(void) */ setbits_le32(&clkctrl_regs->hw_clkctrl_pll0ctrl0, CLKCTRL_PLL0CTRL0_POWER); - early_delay(100); + udelay(100); /* * TODO: Should the PLL0 FORCE_LOCK bit be set here followed be a @@ -140,7 +140,7 @@ static int mxs_power_wait_rtc_stat(u32 mask) struct mxs_rtc_regs *rtc_regs = (void *)MXS_RTC_BASE; while ((val = readl(&rtc_regs->hw_rtc_stat)) & mask) { - early_delay(1); + udelay(1); if (timeout-- < 0) break; } @@ -267,7 +267,7 @@ static int mxs_is_batt_good(void) writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK, &power_regs->hw_power_5vctrl_clr); - early_delay(500000); + udelay(500000); volt = mxs_get_batt_volt(); @@ -353,7 +353,7 @@ static void mxs_src_power_init(void) if (!fixed_batt_supply) { /* 5V to battery handoff ... FIXME */ setbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER); - early_delay(30); + udelay(30); clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER); } } @@ -438,7 +438,7 @@ static void mxs_enable_4p2_dcdc_input(int xfer) if (xfer) { setbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER); - early_delay(20); + udelay(20); clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER); @@ -449,7 +449,7 @@ static void mxs_enable_4p2_dcdc_input(int xfer) POWER_DCDC4P2_ENABLE_DCDC); } - early_delay(25); + udelay(25); clrsetbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_VBUSVALID_TRSH_MASK, vbus_thresh); @@ -563,7 +563,7 @@ static void mxs_power_init_4p2_regulator(void) POWER_STS_DCDC_4P2_BO)) { tmp = readl(&power_regs->hw_power_5vctrl); tmp |= POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK; - early_delay(100); + udelay(100); writel(tmp, &power_regs->hw_power_5vctrl); break; } else { @@ -573,7 +573,7 @@ static void mxs_power_init_4p2_regulator(void) tmp2 |= tmp << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET; writel(tmp2, &power_regs->hw_power_5vctrl); - early_delay(100); + udelay(100); } } } @@ -654,9 +654,9 @@ static void mxs_power_enable_4p2(void) mxs_power_init_dcdc_4p2_source(); writel(vdddctrl, &power_regs->hw_power_vdddctrl); - early_delay(20); + udelay(20); writel(vddactrl, &power_regs->hw_power_vddactrl); - early_delay(20); + udelay(20); writel(vddioctrl, &power_regs->hw_power_vddioctrl); /* @@ -740,7 +740,7 @@ static void mxs_batt_boot(void) /* 5V to battery handoff. */ setbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER); - early_delay(30); + udelay(30); clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER); writel(POWER_CTRL_ENIRQ_DCDC4P2_BO, &power_regs->hw_power_ctrl_clr); @@ -844,7 +844,7 @@ static void mxs_5v_boot(void) return; } - early_delay(1000); + udelay(1000); if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) { debug("SPL: 5V VDD good (after delay)\n"); mxs_boot_valid_5v(); @@ -1258,7 +1258,7 @@ static void mxs_power_set_vddx(const struct mxs_vddx_cfg *cfg, if (powered_by_linreg || (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO)) { - early_delay(500); + udelay(500); } else { while (!(readl(&power_regs->hw_power_sts) & POWER_STS_DC_OK)) { @@ -1299,7 +1299,7 @@ static void mxs_setup_batt_detect(void) mxs_lradc_init(); mxs_lradc_enable_batt_measurement(); - early_delay(10); + udelay(10); } /** -- 2.39.2