recipes-kernel/linux/linux-karo-4.9.11/tx6/imx6qdl-tx6.dtsi

   1 /*
   2  * Copyright 2016 Lothar Waßmann <LW@KARO-electronics.de>
   3  * Copyright 2016-2017 Oliver Wendt <OW@KARO-electronics.de>
   4  * Copyright 2016 Michael Vyskocil <MV@KARO-electronics.de>
   5  *
   6  * This file is dual-licensed: you can use it either under the terms
   7  * of the GPL or the X11 license, at your option. Note that this dual
   8  * licensing only applies to this file, and not this project as a
   9  * whole.
  10  *
  11  *  a) This file is free software; you can redistribute it and/or
  12  *     modify it under the terms of the GNU General Public License
  13  *     version 2 as published by the Free Software Foundation.
  14  *
  15  *     This file is distributed in the hope that it will be useful,
  16  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  *     GNU General Public License for more details.
  19  *
  20  * Or, alternatively,
  21  *
  22  *  b) Permission is hereby granted, free of charge, to any person
  23  *     obtaining a copy of this software and associated documentation
  24  *     files (the "Software"), to deal in the Software without
  25  *     restriction, including without limitation the rights to use,
  26  *     copy, modify, merge, publish, distribute, sublicense, and/or
  27  *     sell copies of the Software, and to permit persons to whom the
  28  *     Software is furnished to do so, subject to the following
  29  *     conditions:
  30  *
  31  *     The above copyright notice and this permission notice shall be
  32  *     included in all copies or substantial portions of the Software.
  33  *
  34  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  35  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  36  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  37  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  38  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  39  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  40  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  41  *     OTHER DEALINGS IN THE SOFTWARE.
  42  */
  43
  44 /*
  45  * Please be reminded that in general DTSI file(s) are include files that are
  46  * for more than one purpose (usually bound to a SoC) and as such shouldn't be
  47  * edited. For end-user products it should be the DTS file(s) that choose which
  48  * devices and pins are active and setup.
  49  *
  50  * The setup of DT files for Ka-Ro TX COM Modules under Yocto follow a
  51  * different, non-standard, implementation, which can make it necessary.
  52  */
  53
  54 #include <dt-bindings/gpio/gpio.h>
  55 #include <dt-bindings/gpio/imx6qdl-tx6-gpio.h>
  56 #include <dt-bindings/input/input.h>
  57 #include <dt-bindings/pwm/pwm.h>
  58
  59 /*
  60  * Definitions for simpler referencing of TX's standard nodes
  61  */
  62
  63 /* On-board NVMe */
  64 #define TX_EMMC         &usdhc4
  65 #define TX_NAND         &gpmi
  66 /* bus connectors */
  67 #define TX_I2C          &i2c3
  68 #define TX_CAN1         &can2
  69 #define TX_CAN2         &can1
  70 /* video & display */
  71 #define TX_LCD          &lcd
  72 #define TX_LCD_FB       &mxcfb0
  73 #define TX_LDB          &ldb
  74 #define TX_LDB_FB1      &mxcfb1
  75 #define TX_LDB_FB2      &mxcfb2
  76 #define TX_PWM          &pwm2
  77 #define TX_PWM1         &pwm2   /* First  (1st) PWM used (TX's default) */
  78 #define TX_PWM2         &pwm1   /* Second (2nd) PWM used */
  79 /* NVM */
  80 #define TX_SD1          &usdhc1
  81 #define TX_SD2          &usdhc2
  82 #define TX_SPI          &ecspi1
  83 #define TX_SSI1         &audmux
  84 #define TX_SSI_PIN      &pinctrl_ssi1
  85 /* UART */
  86 #define TX_UART1        &uart1
  87 #define TX_UART2        &uart2
  88 #define TX_UART3        &uart3
  89 /* USB */
  90 #define TX_USBH         &usbh1
  91 #define TX_USBOTG       &usbotg
  92
  93 / {
  94         aliases {
  95                 can0 = &can2;
  96                 can1 = &can1;
  97                 emmc = &usdhc4;
  98                 ethernet0 = &fec;
  99                 sdhc0 = &usdhc1;
 100                 sdhc1 = &usdhc2;
 101                 usbh = &usbh1;
 102                 usbotg = &usbotg;
 103         };
 104
 105         memory {
 106                 reg = <0 0>; /* will be filled by U-Boot */
 107         };
 108
 109         /* override imx6dl.dtsi gpu clock definition bug */
 110
 111         clocks {
 112                 #address-cells = <1>;
 113                 #size-cells = <0>;
 114
 115                 mclk: clock {
 116                         compatible = "fixed-clock";
 117                         #clock-cells = <0>;
 118                         clock-frequency = <26000000>;
 119                 };
 120         };
 121
 122         chosen {
 123                 stdout-path = TX_UART1;
 124         };
 125
 126         regulators {
 127                 compatible = "simple-bus";
 128                 #address-cells = <1>;
 129                 #size-cells = <0>;
 130
 131                 reg_3v3_etn: regulator-3v3etn {
 132                         compatible = "regulator-fixed";
 133                         regulator-name = "3V3_ETN";
 134                         regulator-min-microvolt = <3300000>;
 135                         regulator-max-microvolt = <3300000>;
 136                         pinctrl-names = "default";
 137                         pinctrl-0 = <&pinctrl_etnphy_power>;
 138                         gpio = <&gpio3 20 GPIO_ACTIVE_HIGH>;
 139                         enable-active-high;
 140                 };
 141
 142                 reg_usbh1_vbus: regulator-usbh1vbus {
 143                         compatible = "regulator-fixed";
 144                         regulator-name = "usbh1_vbus";
 145                         regulator-min-microvolt = <5000000>;
 146                         regulator-max-microvolt = <5000000>;
 147                         pinctrl-names = "default";
 148                         pinctrl-0 = <&pinctrl_usbh1_vbus>;
 149                         gpio = <TX_GPIO_PIN27 GPIO_ACTIVE_HIGH>;
 150                         enable-active-high;
 151                 };
 152
 153                 reg_usbotg_vbus: regulator-usbotgvbus {
 154                         compatible = "regulator-fixed";
 155                         regulator-name = "usbotg_vbus";
 156                         regulator-min-microvolt = <5000000>;
 157                         regulator-max-microvolt = <5000000>;
 158                         pinctrl-names = "default";
 159                         pinctrl-0 = <&pinctrl_usbotg_vbus>;
 160                         gpio = <TX_GPIO_PIN34 GPIO_ACTIVE_HIGH>;
 161                         enable-active-high;
 162                 };
 163         };
 164
 165         lcd: lcd@0 {
 166                 status = "disabled";
 167         };
 168
 169         mxcfb0: fb@0 {
 170                 compatible = "fsl,mxc_sdc_fb";
 171                 disp_dev = "lcd";
 172                 interface_pix_fmt = "RGB24";
 173                 default_bpp = <16>;
 174                 int_clk = <0>;
 175                 late_init = <0>;
 176                 status = "disabled";
 177         };
 178
 179         mxcfb1: fb@1 {
 180                 compatible = "fsl,mxc_sdc_fb";
 181                 disp_dev = "ldb";
 182                 interface_pix_fmt = "RGB666";
 183                 default_bpp = <16>;
 184                 int_clk = <0>;
 185                 late_init = <0>;
 186                 status = "disabled";
 187         };
 188
 189         mxcfb2: fb@2 {
 190                 compatible = "fsl,mxc_sdc_fb";
 191                 disp_dev = "ldb";
 192                 interface_pix_fmt = "RGB666";
 193                 default_bpp = <16>;
 194                 int_clk = <0>;
 195                 late_init = <0>;
 196                 status = "disabled";
 197         };
 198
 199         v4l2_cap_0 {
 200                 compatible = "fsl,imx6q-v4l2-capture";
 201                 ipu_id = <0>;
 202                 csi_id = <0>;
 203                 mclk_source = <0>;
 204                 status = "disabled";
 205         };
 206
 207         v4l2_cap_1 {
 208                 compatible = "fsl,imx6q-v4l2-capture";
 209                 ipu_id = <0>;
 210                 csi_id = <1>;
 211                 mclk_source = <0>;
 212                 status = "disabled";
 213         };
 214
 215         v4l2_out {
 216                 compatible = "fsl,mxc_v4l2_output";
 217                 status = "disabled";
 218         };
 219 };
 220
 221 &can1 {
 222         pinctrl-names = "default";
 223         pinctrl-0 = <&pinctrl_flexcan1>;
 224         status = "disabled";
 225 };
 226
 227 &can2 {
 228         pinctrl-names = "default";
 229         pinctrl-0 = <&pinctrl_flexcan2>;
 230         status = "disabled";
 231 };
 232
 233 &clks {
 234         fsl,ldb-di0-parent = <&clks IMX6QDL_CLK_PLL2_PFD0_352M>;
 235         fsl,ldb-di1-parent = <&clks IMX6QDL_CLK_PLL2_PFD0_352M>;
 236 };
 237
 238 &dcic2 {
 239         dcic_id = <1>;
 240         dcic_mux = "dcic-lvds1";
 241         status = "okay";
 242 };
 243
 244 &ecspi1 {
 245         pinctrl-names = "default";
 246         pinctrl-0 = <&pinctrl_ecspi1>;
 247         fsl,spi-num-chipselects = <2>;
 248         cs-gpios = <
 249                 TX_GPIO_PIN44 GPIO_ACTIVE_HIGH
 250                 TX_GPIO_PIN45 GPIO_ACTIVE_HIGH
 251         >;
 252         status = "disabled";
 253
 254         spidev0: spi@0 {
 255                 compatible = "spidev";
 256                 reg = <0>;
 257                 spi-max-frequency = <54000000>;
 258         };
 259
 260         spidev1: spi@1 {
 261                 compatible = "spidev";
 262                 reg = <1>;
 263                 spi-max-frequency = <54000000>;
 264         };
 265 };
 266
 267 &fec {
 268         pinctrl-names = "default";
 269         pinctrl-0 = <&pinctrl_enet>;
 270         clocks = <&clks IMX6QDL_CLK_ENET>,
 271                  <&clks IMX6QDL_CLK_ENET>,
 272                  <&clks IMX6QDL_CLK_ENET_REF>,
 273                  <&clks IMX6QDL_CLK_ENET_REF>;
 274         clock-names = "ipg", "ahb", "ptp", "enet_out";
 275         ref-clock = <50000000>;
 276         phy-mode = "rmii";
 277         phy-reset-gpios = <&gpio7 6 GPIO_ACTIVE_HIGH>;
 278         phy-handle = <&etnphy>;
 279         phy-supply = <&reg_3v3_etn>;
 280         fsl,magic-packet;
 281         fsl,err006687-workaround-present;
 282         status = "okay";
 283
 284         mdio {
 285                 #address-cells = <1>;
 286                 #size-cells = <0>;
 287
 288                 etnphy: ethernet-phy@0 {
 289                         compatible = "ethernet-phy-ieee802.3-c22";
 290                         reg = <0>;
 291                         interrupts-extended  = <&gpio7 1 IRQ_TYPE_EDGE_FALLING>;
 292                         status = "okay";
 293                 };
 294         };
 295 };
 296
 297 &gpmi {
 298         pinctrl-names = "default";
 299         pinctrl-0 = <&pinctrl_gpmi_nand>;
 300         nand-on-flash-bbt;
 301         fsl,no-blockmark-swap;
 302         status = "disabled";
 303 };
 304
 305 &i2c3 {
 306         pinctrl-names = "default";
 307         pinctrl-0 = <&pinctrl_i2c3>;
 308         clock-frequency = <400000>;
 309         status = "disabled";
 310 };
 311
 312 &pwm1 {
 313         pinctrl-names = "default";
 314         pinctrl-0 = <&pinctrl_pwm1>;
 315         status = "disabled";
 316 };
 317
 318 &pwm2 {
 319         pinctrl-names = "default";
 320         pinctrl-0 = <&pinctrl_pwm2>;
 321         status = "disabled";
 322 };
 323
 324 &reg_arm {
 325         /delete-property/ regulator-allow-bypass;
 326 };
 327
 328 &reg_pu {
 329         /delete-property/ regulator-allow-bypass;
 330 };
 331
 332 &reg_soc {
 333         /delete-property/ regulator-allow-bypass;
 334 };
 335
 336 &snvs_poweroff {
 337         status = "okay";
 338 };
 339
 340 &ssi1 {
 341         status = "okay";
 342 };
 343
 344 &ssi2 {
 345         status = "okay";
 346 };
 347
 348 &uart1 {
 349         pinctrl-names = "default";
 350         pinctrl-0 = <&pinctrl_uart1 &pinctrl_uart1_rtscts>;
 351         status = "disabled";
 352 };
 353
 354 &uart2 {
 355         pinctrl-names = "default";
 356         pinctrl-0 = <&pinctrl_uart2 &pinctrl_uart2_rtscts>;
 357         status = "disabled";
 358 };
 359
 360 &uart3 {
 361         pinctrl-names = "default";
 362         pinctrl-0 = <&pinctrl_uart3 &pinctrl_uart3_rtscts>;
 363         status = "disabled";
 364 };
 365
 366 &usbotg {
 367         vbus-supply = <&reg_usbotg_vbus>;
 368         pinctrl-names = "default";
 369         pinctrl-0 = <&pinctrl_usbotg>;
 370         dr_mode = "peripheral";
 371         disable-over-current;
 372         status = "disabled";
 373 };
 374
 375 &usbh1 {
 376         vbus-supply = <&reg_usbh1_vbus>;
 377         dr_mode = "host";
 378         disable-over-current;
 379         status = "disabled";
 380 };
 381
 382 &usdhc1 {
 383         pinctrl-names = "default";
 384         pinctrl-0 = <&pinctrl_usdhc1>;
 385         bus-width = <4>;
 386         no-1-8-v;
 387         cd-gpios = <&gpio7 2 GPIO_ACTIVE_LOW>;
 388         fsl,wp-controller;
 389         status = "disabled";
 390 };
 391
 392 &usdhc2 {
 393         pinctrl-names = "default";
 394         pinctrl-0 = <&pinctrl_usdhc2>;
 395         bus-width = <4>;
 396         no-1-8-v;
 397         cd-gpios = <&gpio7 3 GPIO_ACTIVE_LOW>;
 398         fsl,wp-controller;
 399         status = "disabled";
 400 };
 401
 402 &usdhc4 {
 403         pinctrl-names = "default";
 404         pinctrl-0 = <&pinctrl_usdhc4>;
 405         bus-width = <4>;
 406         non-removable;
 407         no-1-8-v;
 408         fsl,wp-controller;
 409         status = "disabled";
 410 };
 411
 412 &iomuxc {
 413         pinctrl-names = "default";
 414         pinctrl-0 = <&pinctrl_hog>;
 415
 416         tx6 {
 417                 pinctrl_hog: hoggrp {
 418                         fsl,pins = <
 419                                 MX6QDL_PAD_SD3_DAT2__GPIO7_IO06         0x1b0b1 /* ETN PHY RESET */
 420                                 MX6QDL_PAD_SD3_DAT4__GPIO7_IO01         0x1b0b1 /* ETN PHY INT */
 421                         >;
 422                 };
 423
 424                 pinctrl_ssi1: audmuxgrp {
 425                         fsl,pins = <
 426                                 MX6QDL_PAD_KEY_ROW1__AUD5_RXD           0x130b0 /* SSI1_RXD */
 427                                 MX6QDL_PAD_KEY_ROW0__AUD5_TXD           0x110b0 /* SSI1_TXD */
 428                                 MX6QDL_PAD_KEY_COL0__AUD5_TXC           0x130b0 /* SSI1_CLK */
 429                                 MX6QDL_PAD_KEY_COL1__AUD5_TXFS          0x130b0 /* SSI1_FS */
 430                         >;
 431                 };
 432
 433                 pinctrl_ecspi1: ecspi1grp {
 434                         fsl,pins = <
 435                                 MX6QDL_PAD_EIM_D18__ECSPI1_MOSI         0x0b0b0
 436                                 MX6QDL_PAD_EIM_D17__ECSPI1_MISO         0x0b0b0
 437                                 MX6QDL_PAD_EIM_D16__ECSPI1_SCLK         0x0b0b0
 438                                 MX6QDL_PAD_GPIO_19__ECSPI1_RDY          0x0b0b0
 439                                 MX6QDL_PAD_EIM_EB2__GPIO2_IO30          0x0b0b0 /* SPI CS0 */
 440                                 MX6QDL_PAD_EIM_D19__GPIO3_IO19          0x0b0b0 /* SPI CS1 */
 441                         >;
 442                 };
 443
 444                 pinctrl_enet: enetgrp {
 445                         fsl,pins = <
 446                                 MX6QDL_PAD_ENET_MDC__ENET_MDC           0x1b0b0
 447                                 MX6QDL_PAD_ENET_MDIO__ENET_MDIO         0x1b0b0
 448                                 MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0     0x1b0b0
 449                                 MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1     0x1b0b0
 450                                 MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER       0x1b0b0
 451                                 MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN       0x1b0b0
 452                                 MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0     0x1b0b0
 453                                 MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1     0x1b0b0
 454                                 MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN      0x1b0b0
 455                         >;
 456                 };
 457
 458                 pinctrl_etnphy_power: etnphy-pwrgrp {
 459                         fsl,pins = <
 460                                 MX6QDL_PAD_EIM_D20__GPIO3_IO20          0x1b0b1 /* ETN PHY POWER */
 461                         >;
 462                 };
 463
 464                 pinctrl_flexcan1: flexcan1grp {
 465                         fsl,pins = <
 466                                 MX6QDL_PAD_GPIO_7__FLEXCAN1_TX          0x1b0b0
 467                                 MX6QDL_PAD_GPIO_8__FLEXCAN1_RX          0x1b0b0
 468                         >;
 469                 };
 470
 471                 pinctrl_flexcan2: flexcan2grp {
 472                         fsl,pins = <
 473                                 MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX        0x1b0b0
 474                                 MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX        0x1b0b0
 475                         >;
 476                 };
 477
 478                 pinctrl_gpmi_nand: gpminandgrp {
 479                         fsl,pins = <
 480                                 MX6QDL_PAD_NANDF_CLE__NAND_CLE          0x0b0b1
 481                                 MX6QDL_PAD_NANDF_ALE__NAND_ALE          0x0b0b1
 482                                 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B        0x0b0b1
 483                                 MX6QDL_PAD_NANDF_RB0__NAND_READY_B      0x0b000
 484                                 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B        0x0b0b1
 485                                 MX6QDL_PAD_SD4_CMD__NAND_RE_B           0x0b0b1
 486                                 MX6QDL_PAD_SD4_CLK__NAND_WE_B           0x0b0b1
 487                                 MX6QDL_PAD_NANDF_D0__NAND_DATA00        0x0b0b1
 488                                 MX6QDL_PAD_NANDF_D1__NAND_DATA01        0x0b0b1
 489                                 MX6QDL_PAD_NANDF_D2__NAND_DATA02        0x0b0b1
 490                                 MX6QDL_PAD_NANDF_D3__NAND_DATA03        0x0b0b1
 491                                 MX6QDL_PAD_NANDF_D4__NAND_DATA04        0x0b0b1
 492                                 MX6QDL_PAD_NANDF_D5__NAND_DATA05        0x0b0b1
 493                                 MX6QDL_PAD_NANDF_D6__NAND_DATA06        0x0b0b1
 494                                 MX6QDL_PAD_NANDF_D7__NAND_DATA07        0x0b0b1
 495                         >;
 496                 };
 497
 498                 pinctrl_i2c3: i2c3grp {
 499                         fsl,pins = <
 500                                 MX6QDL_PAD_GPIO_3__I2C3_SCL             0x4001b8b1
 501                                 MX6QDL_PAD_GPIO_6__I2C3_SDA             0x4001b8b1
 502                         >;
 503                 };
 504
 505                 pinctrl_ipu1: ipu1grp {
 506                         fsl,pins = <
 507                                 MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK      0x10
 508                                 MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15            0x10
 509                                 MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02             0x10
 510                                 MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03             0x10
 511                                 MX6QDL_PAD_DI0_PIN4__IPU1_DI0_PIN04             0x80000000
 512                                 MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00        0x10
 513                                 MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01        0x10
 514                                 MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02        0x10
 515                                 MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03        0x10
 516                                 MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04        0x10
 517                                 MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05        0x10
 518                                 MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06        0x10
 519                                 MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07        0x10
 520                                 MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08        0x10
 521                                 MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09        0x10
 522                                 MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10       0x10
 523                                 MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11       0x10
 524                                 MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12       0x10
 525                                 MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13       0x10
 526                                 MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14       0x10
 527                                 MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15       0x10
 528                                 MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16       0x10
 529                                 MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17       0x10
 530                                 MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18       0x10
 531                                 MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19       0x10
 532                                 MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20       0x10
 533                                 MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21       0x10
 534                                 MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22       0x10
 535                                 MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23       0x10
 536                         >;
 537                 };
 538
 539                 pinctrl_pwm1: pwm1grp {
 540                         fsl,pins = <
 541                                 MX6QDL_PAD_GPIO_9__PWM1_OUT             0x1b0b1
 542                         >;
 543                 };
 544
 545                 pinctrl_pwm2: pwm2grp {
 546                         fsl,pins = <
 547                                 MX6QDL_PAD_GPIO_1__PWM2_OUT             0x1b0b1
 548                         >;
 549                 };
 550
 551                 pinctrl_uart1: uart1grp {
 552                         fsl,pins = <
 553                                 MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA      0x1b0b1
 554                                 MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA      0x1b0b1
 555                         >;
 556                 };
 557
 558                 pinctrl_uart1_rtscts: uart1_rtsctsgrp {
 559                         fsl,pins = <
 560                                 MX6QDL_PAD_SD3_DAT1__UART1_RTS_B        0x1b0b1
 561                                 MX6QDL_PAD_SD3_DAT0__UART1_CTS_B        0x1b0b1
 562                         >;
 563                 };
 564
 565                 pinctrl_uart2: uart2grp {
 566                         fsl,pins = <
 567                                 MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA      0x1b0b1
 568                                 MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA      0x1b0b1
 569                         >;
 570                 };
 571
 572                 pinctrl_uart2_rtscts: uart2_rtsctsgrp {
 573                         fsl,pins = <
 574                                 MX6QDL_PAD_SD4_DAT5__UART2_RTS_B        0x1b0b1
 575                                 MX6QDL_PAD_SD4_DAT6__UART2_CTS_B        0x1b0b1
 576                         >;
 577                 };
 578
 579                 pinctrl_uart3: uart3grp {
 580                         fsl,pins = <
 581                                 MX6QDL_PAD_EIM_D24__UART3_TX_DATA       0x1b0b1
 582                                 MX6QDL_PAD_EIM_D25__UART3_RX_DATA       0x1b0b1
 583                         >;
 584                 };
 585
 586                 pinctrl_uart3_rtscts: uart3_rtsctsgrp {
 587                         fsl,pins = <
 588                                 MX6QDL_PAD_SD3_DAT3__UART3_CTS_B        0x1b0b1
 589                                 MX6QDL_PAD_SD3_RST__UART3_RTS_B         0x1b0b1
 590                         >;
 591                 };
 592
 593                 pinctrl_usbh1_vbus: usbh1-vbusgrp {
 594                         fsl,pins = <
 595                                 MX6QDL_PAD_EIM_D31__GPIO3_IO31          0x1b0b0 /* USBH1_VBUSEN */
 596                         >;
 597                 };
 598
 599                 pinctrl_usbotg: usbotggrp {
 600                         fsl,pins = <
 601                                 MX6QDL_PAD_EIM_D23__GPIO3_IO23          0x17059
 602                         >;
 603                 };
 604
 605                 pinctrl_usbotg_vbus: usbotg-vbusgrp {
 606                         fsl,pins = <
 607                                 MX6QDL_PAD_GPIO_7__GPIO1_IO07           0x1b0b0 /* USBOTG_VBUSEN */
 608                         >;
 609                 };
 610
 611                 pinctrl_usdhc1: usdhc1grp {
 612                         fsl,pins = <
 613                                 MX6QDL_PAD_SD1_CMD__SD1_CMD             0x070b1
 614                                 MX6QDL_PAD_SD1_CLK__SD1_CLK             0x070b1
 615                                 MX6QDL_PAD_SD1_DAT0__SD1_DATA0          0x070b1
 616                                 MX6QDL_PAD_SD1_DAT1__SD1_DATA1          0x070b1
 617                                 MX6QDL_PAD_SD1_DAT2__SD1_DATA2          0x070b1
 618                                 MX6QDL_PAD_SD1_DAT3__SD1_DATA3          0x070b1
 619                                 MX6QDL_PAD_SD3_CMD__GPIO7_IO02          0x170b0 /* SD1 CD */
 620                         >;
 621                 };
 622
 623                 pinctrl_usdhc2: usdhc2grp {
 624                         fsl,pins = <
 625                                 MX6QDL_PAD_SD2_CMD__SD2_CMD             0x070b1
 626                                 MX6QDL_PAD_SD2_CLK__SD2_CLK             0x070b1
 627                                 MX6QDL_PAD_SD2_DAT0__SD2_DATA0          0x070b1
 628                                 MX6QDL_PAD_SD2_DAT1__SD2_DATA1          0x070b1
 629                                 MX6QDL_PAD_SD2_DAT2__SD2_DATA2          0x070b1
 630                                 MX6QDL_PAD_SD2_DAT3__SD2_DATA3          0x070b1
 631                                 MX6QDL_PAD_SD3_CLK__GPIO7_IO03          0x170b0 /* SD2 CD */
 632                         >;
 633                 };
 634
 635                 pinctrl_usdhc4: usdhc4grp {
 636                         fsl,pins = <
 637                                 MX6QDL_PAD_SD4_CMD__SD4_CMD             0x070b1
 638                                 MX6QDL_PAD_SD4_CLK__SD4_CLK             0x070b1
 639                                 MX6QDL_PAD_SD4_DAT0__SD4_DATA0          0x070b1
 640                                 MX6QDL_PAD_SD4_DAT1__SD4_DATA1          0x070b1
 641                                 MX6QDL_PAD_SD4_DAT2__SD4_DATA2          0x070b1
 642                                 MX6QDL_PAD_SD4_DAT3__SD4_DATA3          0x070b1
 643                                 MX6QDL_PAD_NANDF_ALE__SD4_RESET         0x0b0b1
 644                         >;
 645                 };
 646         };
 647 };