2 * Copyright 2016 Lothar Waßmann <LW@KARO-electronics.de>
3 * Copyright 2016-2017 Oliver Wendt <OW@KARO-electronics.de>
4 * Copyright 2016 Michael Vyskocil <MV@KARO-electronics.de>
6 * This file is dual-licensed: you can use it either under the terms
7 * of the GPL or the X11 license, at your option. Note that this dual
8 * licensing only applies to this file, and not this project as a
11 * a) This file is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License
13 * version 2 as published by the Free Software Foundation.
15 * This file is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
22 * b) Permission is hereby granted, free of charge, to any person
23 * obtaining a copy of this software and associated documentation
24 * files (the "Software"), to deal in the Software without
25 * restriction, including without limitation the rights to use,
26 * copy, modify, merge, publish, distribute, sublicense, and/or
27 * sell copies of the Software, and to permit persons to whom the
28 * Software is furnished to do so, subject to the following
31 * The above copyright notice and this permission notice shall be
32 * included in all copies or substantial portions of the Software.
34 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
35 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
36 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
37 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
38 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
39 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
40 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
41 * OTHER DEALINGS IN THE SOFTWARE.
45 * Please be reminded that in general DTSI file(s) are include files that are
46 * for more than one purpose (usually bound to a SoC) and as such shouldn't be
47 * edited. For end-user products it should be the DTS file(s) that choose which
48 * devices and pins are active and setup.
50 * The setup of DT files for Ka-Ro TX COM Modules under Yocto follow a
51 * different, non-standard, implementation, which can make it necessary.
54 #include <dt-bindings/gpio/gpio.h>
55 #include <dt-bindings/gpio/imx6qdl-tx6-gpio.h>
56 #include <dt-bindings/input/input.h>
57 #include <dt-bindings/pwm/pwm.h>
60 * Definitions for simpler referencing of TX's standard nodes
64 #define TX_EMMC &usdhc4
72 #define TX_LCD_FB &mxcfb0
74 #define TX_LDB_FB1 &mxcfb1
75 #define TX_LDB_FB2 &mxcfb2
77 #define TX_PWM1 &pwm2 /* First (1st) PWM used (TX's default) */
78 #define TX_PWM2 &pwm1 /* Second (2nd) PWM used */
80 #define TX_SD1 &usdhc1
81 #define TX_SD2 &usdhc2
82 #define TX_SPI &ecspi1
83 #define TX_SSI1 &audmux
84 #define TX_SSI_PIN &pinctrl_ssi1
86 #define TX_UART1 &uart1
87 #define TX_UART2 &uart2
88 #define TX_UART3 &uart3
90 #define TX_USBH &usbh1
91 #define TX_USBOTG &usbotg
106 reg = <0 0>; /* will be filled by U-Boot */
109 /* override imx6dl.dtsi gpu clock definition bug */
112 #address-cells = <1>;
116 compatible = "fixed-clock";
118 clock-frequency = <26000000>;
123 stdout-path = TX_UART1;
127 compatible = "simple-bus";
128 #address-cells = <1>;
131 reg_3v3_etn: regulator-3v3etn {
132 compatible = "regulator-fixed";
133 regulator-name = "3V3_ETN";
134 regulator-min-microvolt = <3300000>;
135 regulator-max-microvolt = <3300000>;
136 pinctrl-names = "default";
137 pinctrl-0 = <&pinctrl_etnphy_power>;
138 gpio = <&gpio3 20 GPIO_ACTIVE_HIGH>;
142 reg_usbh1_vbus: regulator-usbh1vbus {
143 compatible = "regulator-fixed";
144 regulator-name = "usbh1_vbus";
145 regulator-min-microvolt = <5000000>;
146 regulator-max-microvolt = <5000000>;
147 pinctrl-names = "default";
148 pinctrl-0 = <&pinctrl_usbh1_vbus>;
149 gpio = <TX_GPIO_PIN27 GPIO_ACTIVE_HIGH>;
153 reg_usbotg_vbus: regulator-usbotgvbus {
154 compatible = "regulator-fixed";
155 regulator-name = "usbotg_vbus";
156 regulator-min-microvolt = <5000000>;
157 regulator-max-microvolt = <5000000>;
158 pinctrl-names = "default";
159 pinctrl-0 = <&pinctrl_usbotg_vbus>;
160 gpio = <TX_GPIO_PIN34 GPIO_ACTIVE_HIGH>;
170 compatible = "fsl,mxc_sdc_fb";
172 interface_pix_fmt = "RGB24";
180 compatible = "fsl,mxc_sdc_fb";
182 interface_pix_fmt = "RGB666";
190 compatible = "fsl,mxc_sdc_fb";
192 interface_pix_fmt = "RGB666";
200 compatible = "fsl,imx6q-v4l2-capture";
208 compatible = "fsl,imx6q-v4l2-capture";
216 compatible = "fsl,mxc_v4l2_output";
222 pinctrl-names = "default";
223 pinctrl-0 = <&pinctrl_flexcan1>;
228 pinctrl-names = "default";
229 pinctrl-0 = <&pinctrl_flexcan2>;
234 fsl,ldb-di0-parent = <&clks IMX6QDL_CLK_PLL2_PFD0_352M>;
235 fsl,ldb-di1-parent = <&clks IMX6QDL_CLK_PLL2_PFD0_352M>;
240 dcic_mux = "dcic-lvds1";
245 pinctrl-names = "default";
246 pinctrl-0 = <&pinctrl_ecspi1>;
247 fsl,spi-num-chipselects = <2>;
249 TX_GPIO_PIN44 GPIO_ACTIVE_HIGH
250 TX_GPIO_PIN45 GPIO_ACTIVE_HIGH
255 compatible = "spidev";
257 spi-max-frequency = <54000000>;
261 compatible = "spidev";
263 spi-max-frequency = <54000000>;
268 pinctrl-names = "default";
269 pinctrl-0 = <&pinctrl_enet>;
270 clocks = <&clks IMX6QDL_CLK_ENET>,
271 <&clks IMX6QDL_CLK_ENET>,
272 <&clks IMX6QDL_CLK_ENET_REF>,
273 <&clks IMX6QDL_CLK_ENET_REF>;
274 clock-names = "ipg", "ahb", "ptp", "enet_out";
275 ref-clock = <50000000>;
277 phy-reset-gpios = <&gpio7 6 GPIO_ACTIVE_HIGH>;
278 phy-handle = <&etnphy>;
279 phy-supply = <®_3v3_etn>;
281 fsl,err006687-workaround-present;
285 #address-cells = <1>;
288 etnphy: ethernet-phy@0 {
289 compatible = "ethernet-phy-ieee802.3-c22";
291 interrupts-extended = <&gpio7 1 IRQ_TYPE_EDGE_FALLING>;
298 pinctrl-names = "default";
299 pinctrl-0 = <&pinctrl_gpmi_nand>;
301 fsl,no-blockmark-swap;
306 pinctrl-names = "default";
307 pinctrl-0 = <&pinctrl_i2c3>;
308 clock-frequency = <400000>;
313 pinctrl-names = "default";
314 pinctrl-0 = <&pinctrl_pwm1>;
319 pinctrl-names = "default";
320 pinctrl-0 = <&pinctrl_pwm2>;
325 /delete-property/ regulator-allow-bypass;
329 /delete-property/ regulator-allow-bypass;
333 /delete-property/ regulator-allow-bypass;
349 pinctrl-names = "default";
350 pinctrl-0 = <&pinctrl_uart1 &pinctrl_uart1_rtscts>;
355 pinctrl-names = "default";
356 pinctrl-0 = <&pinctrl_uart2 &pinctrl_uart2_rtscts>;
361 pinctrl-names = "default";
362 pinctrl-0 = <&pinctrl_uart3 &pinctrl_uart3_rtscts>;
367 vbus-supply = <®_usbotg_vbus>;
368 pinctrl-names = "default";
369 pinctrl-0 = <&pinctrl_usbotg>;
370 dr_mode = "peripheral";
371 disable-over-current;
376 vbus-supply = <®_usbh1_vbus>;
378 disable-over-current;
383 pinctrl-names = "default";
384 pinctrl-0 = <&pinctrl_usdhc1>;
387 cd-gpios = <&gpio7 2 GPIO_ACTIVE_LOW>;
393 pinctrl-names = "default";
394 pinctrl-0 = <&pinctrl_usdhc2>;
397 cd-gpios = <&gpio7 3 GPIO_ACTIVE_LOW>;
403 pinctrl-names = "default";
404 pinctrl-0 = <&pinctrl_usdhc4>;
413 pinctrl-names = "default";
414 pinctrl-0 = <&pinctrl_hog>;
417 pinctrl_hog: hoggrp {
419 MX6QDL_PAD_SD3_DAT2__GPIO7_IO06 0x1b0b1 /* ETN PHY RESET */
420 MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1b0b1 /* ETN PHY INT */
424 pinctrl_ssi1: audmuxgrp {
426 MX6QDL_PAD_KEY_ROW1__AUD5_RXD 0x130b0 /* SSI1_RXD */
427 MX6QDL_PAD_KEY_ROW0__AUD5_TXD 0x110b0 /* SSI1_TXD */
428 MX6QDL_PAD_KEY_COL0__AUD5_TXC 0x130b0 /* SSI1_CLK */
429 MX6QDL_PAD_KEY_COL1__AUD5_TXFS 0x130b0 /* SSI1_FS */
433 pinctrl_ecspi1: ecspi1grp {
435 MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x0b0b0
436 MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x0b0b0
437 MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x0b0b0
438 MX6QDL_PAD_GPIO_19__ECSPI1_RDY 0x0b0b0
439 MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x0b0b0 /* SPI CS0 */
440 MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x0b0b0 /* SPI CS1 */
444 pinctrl_enet: enetgrp {
446 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
447 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
448 MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0
449 MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0
450 MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0
451 MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
452 MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0
453 MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0
454 MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0
458 pinctrl_etnphy_power: etnphy-pwrgrp {
460 MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x1b0b1 /* ETN PHY POWER */
464 pinctrl_flexcan1: flexcan1grp {
466 MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x1b0b0
467 MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x1b0b0
471 pinctrl_flexcan2: flexcan2grp {
473 MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b0
474 MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b0
478 pinctrl_gpmi_nand: gpminandgrp {
480 MX6QDL_PAD_NANDF_CLE__NAND_CLE 0x0b0b1
481 MX6QDL_PAD_NANDF_ALE__NAND_ALE 0x0b0b1
482 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0x0b0b1
483 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0x0b000
484 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0x0b0b1
485 MX6QDL_PAD_SD4_CMD__NAND_RE_B 0x0b0b1
486 MX6QDL_PAD_SD4_CLK__NAND_WE_B 0x0b0b1
487 MX6QDL_PAD_NANDF_D0__NAND_DATA00 0x0b0b1
488 MX6QDL_PAD_NANDF_D1__NAND_DATA01 0x0b0b1
489 MX6QDL_PAD_NANDF_D2__NAND_DATA02 0x0b0b1
490 MX6QDL_PAD_NANDF_D3__NAND_DATA03 0x0b0b1
491 MX6QDL_PAD_NANDF_D4__NAND_DATA04 0x0b0b1
492 MX6QDL_PAD_NANDF_D5__NAND_DATA05 0x0b0b1
493 MX6QDL_PAD_NANDF_D6__NAND_DATA06 0x0b0b1
494 MX6QDL_PAD_NANDF_D7__NAND_DATA07 0x0b0b1
498 pinctrl_i2c3: i2c3grp {
500 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
501 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
505 pinctrl_ipu1: ipu1grp {
507 MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
508 MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10
509 MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10
510 MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10
511 MX6QDL_PAD_DI0_PIN4__IPU1_DI0_PIN04 0x80000000
512 MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10
513 MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10
514 MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10
515 MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10
516 MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10
517 MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10
518 MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10
519 MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10
520 MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10
521 MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10
522 MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10
523 MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10
524 MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10
525 MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10
526 MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10
527 MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10
528 MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10
529 MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10
530 MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10
531 MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10
532 MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10
533 MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10
534 MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10
535 MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10
539 pinctrl_pwm1: pwm1grp {
541 MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1
545 pinctrl_pwm2: pwm2grp {
547 MX6QDL_PAD_GPIO_1__PWM2_OUT 0x1b0b1
551 pinctrl_uart1: uart1grp {
553 MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
554 MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
558 pinctrl_uart1_rtscts: uart1_rtsctsgrp {
560 MX6QDL_PAD_SD3_DAT1__UART1_RTS_B 0x1b0b1
561 MX6QDL_PAD_SD3_DAT0__UART1_CTS_B 0x1b0b1
565 pinctrl_uart2: uart2grp {
567 MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
568 MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
572 pinctrl_uart2_rtscts: uart2_rtsctsgrp {
574 MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 0x1b0b1
575 MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0x1b0b1
579 pinctrl_uart3: uart3grp {
581 MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
582 MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
586 pinctrl_uart3_rtscts: uart3_rtsctsgrp {
588 MX6QDL_PAD_SD3_DAT3__UART3_CTS_B 0x1b0b1
589 MX6QDL_PAD_SD3_RST__UART3_RTS_B 0x1b0b1
593 pinctrl_usbh1_vbus: usbh1-vbusgrp {
595 MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x1b0b0 /* USBH1_VBUSEN */
599 pinctrl_usbotg: usbotggrp {
601 MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x17059
605 pinctrl_usbotg_vbus: usbotg-vbusgrp {
607 MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x1b0b0 /* USBOTG_VBUSEN */
611 pinctrl_usdhc1: usdhc1grp {
613 MX6QDL_PAD_SD1_CMD__SD1_CMD 0x070b1
614 MX6QDL_PAD_SD1_CLK__SD1_CLK 0x070b1
615 MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x070b1
616 MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x070b1
617 MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x070b1
618 MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x070b1
619 MX6QDL_PAD_SD3_CMD__GPIO7_IO02 0x170b0 /* SD1 CD */
623 pinctrl_usdhc2: usdhc2grp {
625 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x070b1
626 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x070b1
627 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x070b1
628 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x070b1
629 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x070b1
630 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x070b1
631 MX6QDL_PAD_SD3_CLK__GPIO7_IO03 0x170b0 /* SD2 CD */
635 pinctrl_usdhc4: usdhc4grp {
637 MX6QDL_PAD_SD4_CMD__SD4_CMD 0x070b1
638 MX6QDL_PAD_SD4_CLK__SD4_CLK 0x070b1
639 MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x070b1
640 MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x070b1
641 MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x070b1
642 MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x070b1
643 MX6QDL_PAD_NANDF_ALE__SD4_RESET 0x0b0b1