+++ /dev/null
-/*
- * Copyright 2016 Lothar Waßmann <LW@KARO-electronics.de>
- * Copyright 2016-2017 Oliver Wendt <OW@KARO-electronics.de>
- * Copyright 2016 Michael Vyskocil <MV@KARO-electronics.de>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * version 2 as published by the Free Software Foundation.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/*
- * Please be reminded that in general DTSI file(s) are include files that are
- * for more than one purpose (usually bound to a SoC) and as such shouldn't be
- * edited. For end-user products it should be the DTS file(s) that choose which
- * devices and pins are active and setup.
- *
- * The setup of DT files for Ka-Ro TX COM Modules under Yocto follow a
- * different, non-standard, implementation, which can make it necessary.
- */
-
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/gpio/imx6qdl-tx6-gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/pwm/pwm.h>
-
-/*
- * Definitions for simpler referencing of TX's standard nodes
- */
-
-/* On-board NVMe */
-#define TX_EMMC &usdhc4
-#define TX_NAND &gpmi
-/* bus connectors */
-#define TX_I2C &i2c3
-#define TX_CAN1 &can2
-#define TX_CAN2 &can1
-/* video & display */
-#define TX_LCD &lcd
-#define TX_LCD_FB &mxcfb0
-#define TX_LDB &ldb
-#define TX_LDB_FB1 &mxcfb1
-#define TX_LDB_FB2 &mxcfb2
-#define TX_PWM &pwm2
-#define TX_PWM1 &pwm2 /* First (1st) PWM used (TX's default) */
-#define TX_PWM2 &pwm1 /* Second (2nd) PWM used */
-/* NVM */
-#define TX_SD1 &usdhc1
-#define TX_SD2 &usdhc2
-#define TX_SPI &ecspi1
-#define TX_SSI1 &audmux
-#define TX_SSI_PIN &pinctrl_ssi1
-/* UART */
-#define TX_UART1 &uart1
-#define TX_UART2 &uart2
-#define TX_UART3 &uart3
-/* USB */
-#define TX_USBH &usbh1
-#define TX_USBOTG &usbotg
-
-/ {
- aliases {
- can0 = &can2;
- can1 = &can1;
- emmc = &usdhc4;
- ethernet0 = &fec;
- sdhc0 = &usdhc1;
- sdhc1 = &usdhc2;
- usbh = &usbh1;
- usbotg = &usbotg;
- };
-
- memory {
- reg = <0 0>; /* will be filled by U-Boot */
- };
-
- /* override imx6dl.dtsi gpu clock definition bug */
-
- clocks {
- #address-cells = <1>;
- #size-cells = <0>;
-
- mclk: clock {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <26000000>;
- };
- };
-
- chosen {
- stdout-path = TX_UART1;
- };
-
- regulators {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <0>;
-
- reg_3v3_etn: regulator-3v3etn {
- compatible = "regulator-fixed";
- regulator-name = "3V3_ETN";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_etnphy_power>;
- gpio = <&gpio3 20 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
-
- reg_usbh1_vbus: regulator-usbh1vbus {
- compatible = "regulator-fixed";
- regulator-name = "usbh1_vbus";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usbh1_vbus>;
- gpio = <TX_GPIO_PIN27 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
-
- reg_usbotg_vbus: regulator-usbotgvbus {
- compatible = "regulator-fixed";
- regulator-name = "usbotg_vbus";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usbotg_vbus>;
- gpio = <TX_GPIO_PIN34 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
- };
-
- lcd: lcd@0 {
- status = "disabled";
- };
-
- mxcfb0: fb@0 {
- compatible = "fsl,mxc_sdc_fb";
- disp_dev = "lcd";
- interface_pix_fmt = "RGB24";
- default_bpp = <16>;
- int_clk = <0>;
- late_init = <0>;
- status = "disabled";
- };
-
- mxcfb1: fb@1 {
- compatible = "fsl,mxc_sdc_fb";
- disp_dev = "ldb";
- interface_pix_fmt = "RGB666";
- default_bpp = <16>;
- int_clk = <0>;
- late_init = <0>;
- status = "disabled";
- };
-
- mxcfb2: fb@2 {
- compatible = "fsl,mxc_sdc_fb";
- disp_dev = "ldb";
- interface_pix_fmt = "RGB666";
- default_bpp = <16>;
- int_clk = <0>;
- late_init = <0>;
- status = "disabled";
- };
-
- v4l2_cap_0 {
- compatible = "fsl,imx6q-v4l2-capture";
- ipu_id = <0>;
- csi_id = <0>;
- mclk_source = <0>;
- status = "disabled";
- };
-
- v4l2_cap_1 {
- compatible = "fsl,imx6q-v4l2-capture";
- ipu_id = <0>;
- csi_id = <1>;
- mclk_source = <0>;
- status = "disabled";
- };
-
- v4l2_out {
- compatible = "fsl,mxc_v4l2_output";
- status = "disabled";
- };
-};
-
-&can1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_flexcan1>;
- status = "disabled";
-};
-
-&can2 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_flexcan2>;
- status = "disabled";
-};
-
-&clks {
- fsl,ldb-di0-parent = <&clks IMX6QDL_CLK_PLL2_PFD0_352M>;
- fsl,ldb-di1-parent = <&clks IMX6QDL_CLK_PLL2_PFD0_352M>;
-};
-
-&dcic2 {
- dcic_id = <1>;
- dcic_mux = "dcic-lvds1";
- status = "okay";
-};
-
-&ecspi1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_ecspi1>;
- fsl,spi-num-chipselects = <2>;
- cs-gpios = <
- TX_GPIO_PIN44 GPIO_ACTIVE_HIGH
- TX_GPIO_PIN45 GPIO_ACTIVE_HIGH
- >;
- status = "disabled";
-
- spidev0: spi@0 {
- compatible = "spidev";
- reg = <0>;
- spi-max-frequency = <54000000>;
- };
-
- spidev1: spi@1 {
- compatible = "spidev";
- reg = <1>;
- spi-max-frequency = <54000000>;
- };
-};
-
-&fec {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_enet>;
- clocks = <&clks IMX6QDL_CLK_ENET>,
- <&clks IMX6QDL_CLK_ENET>,
- <&clks IMX6QDL_CLK_ENET_REF>,
- <&clks IMX6QDL_CLK_ENET_REF>;
- clock-names = "ipg", "ahb", "ptp", "enet_out";
- ref-clock = <50000000>;
- phy-mode = "rmii";
- phy-reset-gpios = <&gpio7 6 GPIO_ACTIVE_HIGH>;
- phy-handle = <&etnphy>;
- phy-supply = <®_3v3_etn>;
- fsl,magic-packet;
- fsl,err006687-workaround-present;
- status = "okay";
-
- mdio {
- #address-cells = <1>;
- #size-cells = <0>;
-
- etnphy: ethernet-phy@0 {
- compatible = "ethernet-phy-ieee802.3-c22";
- reg = <0>;
- interrupts-extended = <&gpio7 1 IRQ_TYPE_EDGE_FALLING>;
- status = "okay";
- };
- };
-};
-
-&gpmi {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_gpmi_nand>;
- nand-on-flash-bbt;
- fsl,no-blockmark-swap;
- status = "disabled";
-};
-
-&i2c3 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c3>;
- clock-frequency = <400000>;
- status = "disabled";
-};
-
-&pwm1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_pwm1>;
- status = "disabled";
-};
-
-&pwm2 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_pwm2>;
- status = "disabled";
-};
-
-®_arm {
- /delete-property/ regulator-allow-bypass;
-};
-
-®_pu {
- /delete-property/ regulator-allow-bypass;
-};
-
-®_soc {
- /delete-property/ regulator-allow-bypass;
-};
-
-&snvs_poweroff {
- status = "okay";
-};
-
-&ssi1 {
- status = "okay";
-};
-
-&ssi2 {
- status = "okay";
-};
-
-&uart1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart1 &pinctrl_uart1_rtscts>;
- status = "disabled";
-};
-
-&uart2 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart2 &pinctrl_uart2_rtscts>;
- status = "disabled";
-};
-
-&uart3 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart3 &pinctrl_uart3_rtscts>;
- status = "disabled";
-};
-
-&usbotg {
- vbus-supply = <®_usbotg_vbus>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usbotg>;
- dr_mode = "peripheral";
- disable-over-current;
- status = "disabled";
-};
-
-&usbh1 {
- vbus-supply = <®_usbh1_vbus>;
- dr_mode = "host";
- disable-over-current;
- status = "disabled";
-};
-
-&usdhc1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usdhc1>;
- bus-width = <4>;
- no-1-8-v;
- cd-gpios = <&gpio7 2 GPIO_ACTIVE_LOW>;
- fsl,wp-controller;
- status = "disabled";
-};
-
-&usdhc2 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usdhc2>;
- bus-width = <4>;
- no-1-8-v;
- cd-gpios = <&gpio7 3 GPIO_ACTIVE_LOW>;
- fsl,wp-controller;
- status = "disabled";
-};
-
-&usdhc4 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usdhc4>;
- bus-width = <4>;
- non-removable;
- no-1-8-v;
- fsl,wp-controller;
- status = "disabled";
-};
-
-&iomuxc {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_hog>;
-
- tx6 {
- pinctrl_hog: hoggrp {
- fsl,pins = <
- MX6QDL_PAD_SD3_DAT2__GPIO7_IO06 0x1b0b1 /* ETN PHY RESET */
- MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1b0b1 /* ETN PHY INT */
- >;
- };
-
- pinctrl_ssi1: audmuxgrp {
- fsl,pins = <
- MX6QDL_PAD_KEY_ROW1__AUD5_RXD 0x130b0 /* SSI1_RXD */
- MX6QDL_PAD_KEY_ROW0__AUD5_TXD 0x110b0 /* SSI1_TXD */
- MX6QDL_PAD_KEY_COL0__AUD5_TXC 0x130b0 /* SSI1_CLK */
- MX6QDL_PAD_KEY_COL1__AUD5_TXFS 0x130b0 /* SSI1_FS */
- >;
- };
-
- pinctrl_ecspi1: ecspi1grp {
- fsl,pins = <
- MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x0b0b0
- MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x0b0b0
- MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x0b0b0
- MX6QDL_PAD_GPIO_19__ECSPI1_RDY 0x0b0b0
- MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x0b0b0 /* SPI CS0 */
- MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x0b0b0 /* SPI CS1 */
- >;
- };
-
- pinctrl_enet: enetgrp {
- fsl,pins = <
- MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
- MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
- MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0
- MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0
- MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0
- MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
- MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0
- MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0
- MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0
- >;
- };
-
- pinctrl_etnphy_power: etnphy-pwrgrp {
- fsl,pins = <
- MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x1b0b1 /* ETN PHY POWER */
- >;
- };
-
- pinctrl_flexcan1: flexcan1grp {
- fsl,pins = <
- MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x1b0b0
- MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x1b0b0
- >;
- };
-
- pinctrl_flexcan2: flexcan2grp {
- fsl,pins = <
- MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b0
- MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b0
- >;
- };
-
- pinctrl_gpmi_nand: gpminandgrp {
- fsl,pins = <
- MX6QDL_PAD_NANDF_CLE__NAND_CLE 0x0b0b1
- MX6QDL_PAD_NANDF_ALE__NAND_ALE 0x0b0b1
- MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0x0b0b1
- MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0x0b000
- MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0x0b0b1
- MX6QDL_PAD_SD4_CMD__NAND_RE_B 0x0b0b1
- MX6QDL_PAD_SD4_CLK__NAND_WE_B 0x0b0b1
- MX6QDL_PAD_NANDF_D0__NAND_DATA00 0x0b0b1
- MX6QDL_PAD_NANDF_D1__NAND_DATA01 0x0b0b1
- MX6QDL_PAD_NANDF_D2__NAND_DATA02 0x0b0b1
- MX6QDL_PAD_NANDF_D3__NAND_DATA03 0x0b0b1
- MX6QDL_PAD_NANDF_D4__NAND_DATA04 0x0b0b1
- MX6QDL_PAD_NANDF_D5__NAND_DATA05 0x0b0b1
- MX6QDL_PAD_NANDF_D6__NAND_DATA06 0x0b0b1
- MX6QDL_PAD_NANDF_D7__NAND_DATA07 0x0b0b1
- >;
- };
-
- pinctrl_i2c3: i2c3grp {
- fsl,pins = <
- MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
- MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
- >;
- };
-
- pinctrl_ipu1: ipu1grp {
- fsl,pins = <
- MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
- MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10
- MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10
- MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10
- MX6QDL_PAD_DI0_PIN4__IPU1_DI0_PIN04 0x80000000
- MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10
- MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10
- MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10
- MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10
- MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10
- MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10
- MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10
- MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10
- MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10
- MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10
- MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10
- MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10
- MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10
- MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10
- MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10
- MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10
- MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10
- MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10
- MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10
- MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10
- MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10
- MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10
- MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10
- MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10
- >;
- };
-
- pinctrl_pwm1: pwm1grp {
- fsl,pins = <
- MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1
- >;
- };
-
- pinctrl_pwm2: pwm2grp {
- fsl,pins = <
- MX6QDL_PAD_GPIO_1__PWM2_OUT 0x1b0b1
- >;
- };
-
- pinctrl_uart1: uart1grp {
- fsl,pins = <
- MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
- MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
- >;
- };
-
- pinctrl_uart1_rtscts: uart1_rtsctsgrp {
- fsl,pins = <
- MX6QDL_PAD_SD3_DAT1__UART1_RTS_B 0x1b0b1
- MX6QDL_PAD_SD3_DAT0__UART1_CTS_B 0x1b0b1
- >;
- };
-
- pinctrl_uart2: uart2grp {
- fsl,pins = <
- MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
- MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
- >;
- };
-
- pinctrl_uart2_rtscts: uart2_rtsctsgrp {
- fsl,pins = <
- MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 0x1b0b1
- MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0x1b0b1
- >;
- };
-
- pinctrl_uart3: uart3grp {
- fsl,pins = <
- MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
- MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
- >;
- };
-
- pinctrl_uart3_rtscts: uart3_rtsctsgrp {
- fsl,pins = <
- MX6QDL_PAD_SD3_DAT3__UART3_CTS_B 0x1b0b1
- MX6QDL_PAD_SD3_RST__UART3_RTS_B 0x1b0b1
- >;
- };
-
- pinctrl_usbh1_vbus: usbh1-vbusgrp {
- fsl,pins = <
- MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x1b0b0 /* USBH1_VBUSEN */
- >;
- };
-
- pinctrl_usbotg: usbotggrp {
- fsl,pins = <
- MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x17059
- >;
- };
-
- pinctrl_usbotg_vbus: usbotg-vbusgrp {
- fsl,pins = <
- MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x1b0b0 /* USBOTG_VBUSEN */
- >;
- };
-
- pinctrl_usdhc1: usdhc1grp {
- fsl,pins = <
- MX6QDL_PAD_SD1_CMD__SD1_CMD 0x070b1
- MX6QDL_PAD_SD1_CLK__SD1_CLK 0x070b1
- MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x070b1
- MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x070b1
- MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x070b1
- MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x070b1
- MX6QDL_PAD_SD3_CMD__GPIO7_IO02 0x170b0 /* SD1 CD */
- >;
- };
-
- pinctrl_usdhc2: usdhc2grp {
- fsl,pins = <
- MX6QDL_PAD_SD2_CMD__SD2_CMD 0x070b1
- MX6QDL_PAD_SD2_CLK__SD2_CLK 0x070b1
- MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x070b1
- MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x070b1
- MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x070b1
- MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x070b1
- MX6QDL_PAD_SD3_CLK__GPIO7_IO03 0x170b0 /* SD2 CD */
- >;
- };
-
- pinctrl_usdhc4: usdhc4grp {
- fsl,pins = <
- MX6QDL_PAD_SD4_CMD__SD4_CMD 0x070b1
- MX6QDL_PAD_SD4_CLK__SD4_CLK 0x070b1
- MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x070b1
- MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x070b1
- MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x070b1
- MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x070b1
- MX6QDL_PAD_NANDF_ALE__SD4_RESET 0x0b0b1
- >;
- };
- };
-};