2 * Copyright 2013 Greg Ungerer <gerg@uclinux.org>
3 * Copyright 2011 Freescale Semiconductor, Inc.
4 * Copyright 2011 Linaro Ltd.
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
14 #include "skeleton.dtsi"
15 #include "imx50-pinfunc.h"
16 #include <dt-bindings/clock/imx5-clock.h>
39 compatible = "arm,cortex-a8";
44 tzic: tz-interrupt-controller@0fffc000 {
45 compatible = "fsl,imx50-tzic", "fsl,imx53-tzic", "fsl,tzic";
47 #interrupt-cells = <1>;
48 reg = <0x0fffc000 0x4000>;
56 compatible = "fsl,imx-ckil", "fixed-clock";
58 clock-frequency = <32768>;
62 compatible = "fsl,imx-ckih1", "fixed-clock";
64 clock-frequency = <22579200>;
68 compatible = "fsl,imx-ckih2", "fixed-clock";
70 clock-frequency = <0>;
74 compatible = "fsl,imx-osc", "fixed-clock";
76 clock-frequency = <24000000>;
83 compatible = "simple-bus";
84 interrupt-parent = <&tzic>;
87 aips@50000000 { /* AIPS1 */
88 compatible = "fsl,aips-bus", "simple-bus";
91 reg = <0x50000000 0x10000000>;
95 compatible = "fsl,spba-bus", "simple-bus";
98 reg = <0x50000000 0x40000>;
101 esdhc1: esdhc@50004000 {
102 compatible = "fsl,imx50-esdhc";
103 reg = <0x50004000 0x4000>;
105 clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>,
106 <&clks IMX5_CLK_DUMMY>,
107 <&clks IMX5_CLK_ESDHC1_PER_GATE>;
108 clock-names = "ipg", "ahb", "per";
113 esdhc2: esdhc@50008000 {
114 compatible = "fsl,imx50-esdhc";
115 reg = <0x50008000 0x4000>;
117 clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>,
118 <&clks IMX5_CLK_DUMMY>,
119 <&clks IMX5_CLK_ESDHC2_PER_GATE>;
120 clock-names = "ipg", "ahb", "per";
125 uart3: serial@5000c000 {
126 compatible = "fsl,imx50-uart", "fsl,imx21-uart";
127 reg = <0x5000c000 0x4000>;
129 clocks = <&clks IMX5_CLK_UART3_IPG_GATE>,
130 <&clks IMX5_CLK_UART3_PER_GATE>;
131 clock-names = "ipg", "per";
135 ecspi1: ecspi@50010000 {
136 #address-cells = <1>;
138 compatible = "fsl,imx50-ecspi", "fsl,imx51-ecspi";
139 reg = <0x50010000 0x4000>;
141 clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>,
142 <&clks IMX5_CLK_ECSPI1_PER_GATE>;
143 clock-names = "ipg", "per";
148 #sound-dai-cells = <0>;
149 compatible = "fsl,imx50-ssi",
152 reg = <0x50014000 0x4000>;
154 clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>;
155 dmas = <&sdma 24 1 0>,
157 dma-names = "rx", "tx";
158 fsl,fifo-depth = <15>;
162 esdhc3: esdhc@50020000 {
163 compatible = "fsl,imx50-esdhc";
164 reg = <0x50020000 0x4000>;
166 clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>,
167 <&clks IMX5_CLK_DUMMY>,
168 <&clks IMX5_CLK_ESDHC3_PER_GATE>;
169 clock-names = "ipg", "ahb", "per";
174 esdhc4: esdhc@50024000 {
175 compatible = "fsl,imx50-esdhc";
176 reg = <0x50024000 0x4000>;
178 clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>,
179 <&clks IMX5_CLK_DUMMY>,
180 <&clks IMX5_CLK_ESDHC4_PER_GATE>;
181 clock-names = "ipg", "ahb", "per";
187 usbotg: usb@53f80000 {
188 compatible = "fsl,imx50-usb", "fsl,imx27-usb";
189 reg = <0x53f80000 0x0200>;
191 clocks = <&clks IMX5_CLK_USB_PHY1_GATE>;
195 usbh1: usb@53f80200 {
196 compatible = "fsl,imx50-usb", "fsl,imx27-usb";
197 reg = <0x53f80200 0x0200>;
199 clocks = <&clks IMX5_CLK_USB_PHY2_GATE>;
203 usbh2: usb@53f80400 {
204 compatible = "fsl,imx50-usb", "fsl,imx27-usb";
205 reg = <0x53f80400 0x0200>;
207 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
211 usbh3: usb@53f80600 {
212 compatible = "fsl,imx50-usb", "fsl,imx27-usb";
213 reg = <0x53f80600 0x0200>;
215 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
219 gpio1: gpio@53f84000 {
220 compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
221 reg = <0x53f84000 0x4000>;
222 interrupts = <50 51>;
225 interrupt-controller;
226 #interrupt-cells = <2>;
229 gpio2: gpio@53f88000 {
230 compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
231 reg = <0x53f88000 0x4000>;
232 interrupts = <52 53>;
235 interrupt-controller;
236 #interrupt-cells = <2>;
239 gpio3: gpio@53f8c000 {
240 compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
241 reg = <0x53f8c000 0x4000>;
242 interrupts = <54 55>;
245 interrupt-controller;
246 #interrupt-cells = <2>;
249 gpio4: gpio@53f90000 {
250 compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
251 reg = <0x53f90000 0x4000>;
252 interrupts = <56 57>;
255 interrupt-controller;
256 #interrupt-cells = <2>;
259 wdog1: wdog@53f98000 {
260 compatible = "fsl,imx50-wdt", "fsl,imx21-wdt";
261 reg = <0x53f98000 0x4000>;
263 clocks = <&clks IMX5_CLK_DUMMY>;
266 gpt: timer@53fa0000 {
267 compatible = "fsl,imx50-gpt", "fsl,imx31-gpt";
268 reg = <0x53fa0000 0x4000>;
270 clocks = <&clks IMX5_CLK_GPT_IPG_GATE>,
271 <&clks IMX5_CLK_GPT_HF_GATE>;
272 clock-names = "ipg", "per";
275 iomuxc: iomuxc@53fa8000 {
276 compatible = "fsl,imx50-iomuxc", "fsl,imx53-iomuxc";
277 reg = <0x53fa8000 0x4000>;
280 gpr: iomuxc-gpr@53fa8000 {
281 compatible = "fsl,imx50-iomuxc-gpr", "syscon";
282 reg = <0x53fa8000 0xc>;
287 compatible = "fsl,imx50-pwm", "fsl,imx27-pwm";
288 reg = <0x53fb4000 0x4000>;
289 clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>,
290 <&clks IMX5_CLK_PWM1_HF_GATE>;
291 clock-names = "ipg", "per";
297 compatible = "fsl,imx50-pwm", "fsl,imx27-pwm";
298 reg = <0x53fb8000 0x4000>;
299 clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>,
300 <&clks IMX5_CLK_PWM2_HF_GATE>;
301 clock-names = "ipg", "per";
305 uart1: serial@53fbc000 {
306 compatible = "fsl,imx50-uart", "fsl,imx21-uart";
307 reg = <0x53fbc000 0x4000>;
309 clocks = <&clks IMX5_CLK_UART1_IPG_GATE>,
310 <&clks IMX5_CLK_UART1_PER_GATE>;
311 clock-names = "ipg", "per";
315 uart2: serial@53fc0000 {
316 compatible = "fsl,imx50-uart", "fsl,imx21-uart";
317 reg = <0x53fc0000 0x4000>;
319 clocks = <&clks IMX5_CLK_UART2_IPG_GATE>,
320 <&clks IMX5_CLK_UART2_PER_GATE>;
321 clock-names = "ipg", "per";
326 compatible = "fsl,imx50-src", "fsl,imx51-src";
327 reg = <0x53fd0000 0x4000>;
332 compatible = "fsl,imx50-ccm";
333 reg = <0x53fd4000 0x4000>;
334 interrupts = <0 71 0x04 0 72 0x04>;
338 gpio5: gpio@53fdc000 {
339 compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
340 reg = <0x53fdc000 0x4000>;
341 interrupts = <103 104>;
344 interrupt-controller;
345 #interrupt-cells = <2>;
348 gpio6: gpio@53fe0000 {
349 compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
350 reg = <0x53fe0000 0x4000>;
351 interrupts = <105 106>;
354 interrupt-controller;
355 #interrupt-cells = <2>;
359 #address-cells = <1>;
361 compatible = "fsl,imx50-i2c", "fsl,imx21-i2c";
362 reg = <0x53fec000 0x4000>;
364 clocks = <&clks IMX5_CLK_I2C3_GATE>;
368 uart4: serial@53ff0000 {
369 compatible = "fsl,imx50-uart", "fsl,imx21-uart";
370 reg = <0x53ff0000 0x4000>;
372 clocks = <&clks IMX5_CLK_UART4_IPG_GATE>,
373 <&clks IMX5_CLK_UART4_PER_GATE>;
374 clock-names = "ipg", "per";
379 aips@60000000 { /* AIPS2 */
380 compatible = "fsl,aips-bus", "simple-bus";
381 #address-cells = <1>;
383 reg = <0x60000000 0x10000000>;
386 uart5: serial@63f90000 {
387 compatible = "fsl,imx50-uart", "fsl,imx21-uart";
388 reg = <0x63f90000 0x4000>;
390 clocks = <&clks IMX5_CLK_UART5_IPG_GATE>,
391 <&clks IMX5_CLK_UART5_PER_GATE>;
392 clock-names = "ipg", "per";
396 owire: owire@63fa4000 {
397 compatible = "fsl,imx50-owire", "fsl,imx21-owire";
398 reg = <0x63fa4000 0x4000>;
399 clocks = <&clks IMX5_CLK_OWIRE_GATE>;
403 ecspi2: ecspi@63fac000 {
404 #address-cells = <1>;
406 compatible = "fsl,imx50-ecspi", "fsl,imx51-ecspi";
407 reg = <0x63fac000 0x4000>;
409 clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>,
410 <&clks IMX5_CLK_ECSPI2_PER_GATE>;
411 clock-names = "ipg", "per";
415 sdma: sdma@63fb0000 {
416 compatible = "fsl,imx50-sdma", "fsl,imx35-sdma";
417 reg = <0x63fb0000 0x4000>;
419 clocks = <&clks IMX5_CLK_SDMA_GATE>,
420 <&clks IMX5_CLK_SDMA_GATE>;
421 clock-names = "ipg", "ahb";
422 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx50.bin";
425 cspi: cspi@63fc0000 {
426 #address-cells = <1>;
428 compatible = "fsl,imx50-cspi", "fsl,imx35-cspi";
429 reg = <0x63fc0000 0x4000>;
431 clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>,
432 <&clks IMX5_CLK_CSPI_IPG_GATE>;
433 clock-names = "ipg", "per";
438 #address-cells = <1>;
440 compatible = "fsl,imx50-i2c", "fsl,imx21-i2c";
441 reg = <0x63fc4000 0x4000>;
443 clocks = <&clks IMX5_CLK_I2C2_GATE>;
448 #address-cells = <1>;
450 compatible = "fsl,imx50-i2c", "fsl,imx21-i2c";
451 reg = <0x63fc8000 0x4000>;
453 clocks = <&clks IMX5_CLK_I2C1_GATE>;
458 #sound-dai-cells = <0>;
459 compatible = "fsl,imx50-ssi", "fsl,imx51-ssi",
461 reg = <0x63fcc000 0x4000>;
463 clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>;
464 dmas = <&sdma 28 0 0>,
466 dma-names = "rx", "tx";
467 fsl,fifo-depth = <15>;
471 audmux: audmux@63fd0000 {
472 compatible = "fsl,imx50-audmux", "fsl,imx31-audmux";
473 reg = <0x63fd0000 0x4000>;
477 fec: ethernet@63fec000 {
478 compatible = "fsl,imx53-fec", "fsl,imx25-fec";
479 reg = <0x63fec000 0x4000>;
481 clocks = <&clks IMX5_CLK_FEC_GATE>,
482 <&clks IMX5_CLK_FEC_GATE>,
483 <&clks IMX5_CLK_FEC_GATE>;
484 clock-names = "ipg", "ahb", "ptp";