2 * OMAP54xx Clock Management register bits
4 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
6 * Paul Walmsley (paul@pwsan.com)
7 * Rajendra Nayak (rnayak@ti.com)
8 * Benoit Cousson (b-cousson@ti.com)
10 * This file is automatically generated from the OMAP hardware databases.
11 * We respectfully ask that any modifications to this file be coordinated
12 * with the public linux-omap@vger.kernel.org mailing list and the
13 * authors above to ensure that the autogeneration scripts are kept
14 * up-to-date with the file contents.
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License version 2 as
18 * published by the Free Software Foundation.
21 #ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_54XX_H
22 #define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_54XX_H
24 /* Used by CM_DSP_DYNAMICDEP, CM_L3MAIN1_DYNAMICDEP, CM_MPU_DYNAMICDEP */
25 #define OMAP54XX_ABE_DYNDEP_SHIFT 3
26 #define OMAP54XX_ABE_DYNDEP_WIDTH 0x1
27 #define OMAP54XX_ABE_DYNDEP_MASK (1 << 3)
30 * Used by CM_C2C_STATICDEP, CM_DMA_STATICDEP, CM_DSP_STATICDEP,
31 * CM_IPU_STATICDEP, CM_L3INIT_STATICDEP, CM_MIPIEXT_STATICDEP, CM_MPU_STATICDEP
33 #define OMAP54XX_ABE_STATDEP_SHIFT 3
34 #define OMAP54XX_ABE_STATDEP_WIDTH 0x1
35 #define OMAP54XX_ABE_STATDEP_MASK (1 << 3)
38 * Used by CM_AUTOIDLE_DPLL_ABE, CM_AUTOIDLE_DPLL_CORE, CM_AUTOIDLE_DPLL_IVA,
39 * CM_AUTOIDLE_DPLL_MPU, CM_AUTOIDLE_DPLL_PER, CM_AUTOIDLE_DPLL_UNIPRO1,
40 * CM_AUTOIDLE_DPLL_UNIPRO2, CM_AUTOIDLE_DPLL_USB
42 #define OMAP54XX_AUTO_DPLL_MODE_SHIFT 0
43 #define OMAP54XX_AUTO_DPLL_MODE_WIDTH 0x3
44 #define OMAP54XX_AUTO_DPLL_MODE_MASK (0x7 << 0)
46 /* Used by CM_L3MAIN2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP */
47 #define OMAP54XX_C2C_DYNDEP_SHIFT 18
48 #define OMAP54XX_C2C_DYNDEP_WIDTH 0x1
49 #define OMAP54XX_C2C_DYNDEP_MASK (1 << 18)
51 /* Used by CM_MPU_STATICDEP */
52 #define OMAP54XX_C2C_STATDEP_SHIFT 18
53 #define OMAP54XX_C2C_STATDEP_WIDTH 0x1
54 #define OMAP54XX_C2C_STATDEP_MASK (1 << 18)
56 /* Used by CM_IPU_DYNAMICDEP, CM_L3MAIN2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP */
57 #define OMAP54XX_CAM_DYNDEP_SHIFT 9
58 #define OMAP54XX_CAM_DYNDEP_WIDTH 0x1
59 #define OMAP54XX_CAM_DYNDEP_MASK (1 << 9)
62 * Used by CM_DMA_STATICDEP, CM_DSP_STATICDEP, CM_IPU_STATICDEP,
65 #define OMAP54XX_CAM_STATDEP_SHIFT 9
66 #define OMAP54XX_CAM_STATDEP_WIDTH 0x1
67 #define OMAP54XX_CAM_STATDEP_MASK (1 << 9)
69 /* Used by CM_ABE_CLKSTCTRL */
70 #define OMAP54XX_CLKACTIVITY_ABE_24M_GFCLK_SHIFT 13
71 #define OMAP54XX_CLKACTIVITY_ABE_24M_GFCLK_WIDTH 0x1
72 #define OMAP54XX_CLKACTIVITY_ABE_24M_GFCLK_MASK (1 << 13)
74 /* Used by CM_ABE_CLKSTCTRL */
75 #define OMAP54XX_CLKACTIVITY_ABE_32K_CLK_SHIFT 12
76 #define OMAP54XX_CLKACTIVITY_ABE_32K_CLK_WIDTH 0x1
77 #define OMAP54XX_CLKACTIVITY_ABE_32K_CLK_MASK (1 << 12)
79 /* Used by CM_ABE_CLKSTCTRL */
80 #define OMAP54XX_CLKACTIVITY_ABE_GICLK_SHIFT 9
81 #define OMAP54XX_CLKACTIVITY_ABE_GICLK_WIDTH 0x1
82 #define OMAP54XX_CLKACTIVITY_ABE_GICLK_MASK (1 << 9)
84 /* Used by CM_WKUPAON_CLKSTCTRL */
85 #define OMAP54XX_CLKACTIVITY_ABE_LP_CLK_SHIFT 9
86 #define OMAP54XX_CLKACTIVITY_ABE_LP_CLK_WIDTH 0x1
87 #define OMAP54XX_CLKACTIVITY_ABE_LP_CLK_MASK (1 << 9)
89 /* Used by CM_ABE_CLKSTCTRL */
90 #define OMAP54XX_CLKACTIVITY_ABE_SYS_CLK_SHIFT 11
91 #define OMAP54XX_CLKACTIVITY_ABE_SYS_CLK_WIDTH 0x1
92 #define OMAP54XX_CLKACTIVITY_ABE_SYS_CLK_MASK (1 << 11)
94 /* Used by CM_ABE_CLKSTCTRL */
95 #define OMAP54XX_CLKACTIVITY_ABE_X2_CLK_SHIFT 8
96 #define OMAP54XX_CLKACTIVITY_ABE_X2_CLK_WIDTH 0x1
97 #define OMAP54XX_CLKACTIVITY_ABE_X2_CLK_MASK (1 << 8)
99 /* Used by CM_DSS_CLKSTCTRL */
100 #define OMAP54XX_CLKACTIVITY_BB2D_GFCLK_SHIFT 13
101 #define OMAP54XX_CLKACTIVITY_BB2D_GFCLK_WIDTH 0x1
102 #define OMAP54XX_CLKACTIVITY_BB2D_GFCLK_MASK (1 << 13)
104 /* Used by CM_C2C_CLKSTCTRL */
105 #define OMAP54XX_CLKACTIVITY_C2C_GFCLK_SHIFT 9
106 #define OMAP54XX_CLKACTIVITY_C2C_GFCLK_WIDTH 0x1
107 #define OMAP54XX_CLKACTIVITY_C2C_GFCLK_MASK (1 << 9)
109 /* Used by CM_C2C_CLKSTCTRL */
110 #define OMAP54XX_CLKACTIVITY_C2C_GICLK_SHIFT 10
111 #define OMAP54XX_CLKACTIVITY_C2C_GICLK_WIDTH 0x1
112 #define OMAP54XX_CLKACTIVITY_C2C_GICLK_MASK (1 << 10)
114 /* Used by CM_C2C_CLKSTCTRL */
115 #define OMAP54XX_CLKACTIVITY_C2C_L4_GICLK_SHIFT 8
116 #define OMAP54XX_CLKACTIVITY_C2C_L4_GICLK_WIDTH 0x1
117 #define OMAP54XX_CLKACTIVITY_C2C_L4_GICLK_MASK (1 << 8)
119 /* Used by CM_CAM_CLKSTCTRL */
120 #define OMAP54XX_CLKACTIVITY_CAM_BOOST_GCLK_SHIFT 11
121 #define OMAP54XX_CLKACTIVITY_CAM_BOOST_GCLK_WIDTH 0x1
122 #define OMAP54XX_CLKACTIVITY_CAM_BOOST_GCLK_MASK (1 << 11)
124 /* Used by CM_CAM_CLKSTCTRL */
125 #define OMAP54XX_CLKACTIVITY_CAM_GCLK_SHIFT 8
126 #define OMAP54XX_CLKACTIVITY_CAM_GCLK_WIDTH 0x1
127 #define OMAP54XX_CLKACTIVITY_CAM_GCLK_MASK (1 << 8)
129 /* Used by CM_CAM_CLKSTCTRL */
130 #define OMAP54XX_CLKACTIVITY_CAM_L3_GICLK_SHIFT 12
131 #define OMAP54XX_CLKACTIVITY_CAM_L3_GICLK_WIDTH 0x1
132 #define OMAP54XX_CLKACTIVITY_CAM_L3_GICLK_MASK (1 << 12)
134 /* Used by CM_COREAON_CLKSTCTRL */
135 #define OMAP54XX_CLKACTIVITY_COREAON_32K_GFCLK_SHIFT 12
136 #define OMAP54XX_CLKACTIVITY_COREAON_32K_GFCLK_WIDTH 0x1
137 #define OMAP54XX_CLKACTIVITY_COREAON_32K_GFCLK_MASK (1 << 12)
139 /* Used by CM_COREAON_CLKSTCTRL */
140 #define OMAP54XX_CLKACTIVITY_COREAON_IO_SRCOMP_GFCLK_SHIFT 14
141 #define OMAP54XX_CLKACTIVITY_COREAON_IO_SRCOMP_GFCLK_WIDTH 0x1
142 #define OMAP54XX_CLKACTIVITY_COREAON_IO_SRCOMP_GFCLK_MASK (1 << 14)
144 /* Used by CM_COREAON_CLKSTCTRL */
145 #define OMAP54XX_CLKACTIVITY_COREAON_L4_GICLK_SHIFT 8
146 #define OMAP54XX_CLKACTIVITY_COREAON_L4_GICLK_WIDTH 0x1
147 #define OMAP54XX_CLKACTIVITY_COREAON_L4_GICLK_MASK (1 << 8)
149 /* Used by CM_CAM_CLKSTCTRL */
150 #define OMAP54XX_CLKACTIVITY_CSI_PHY_GFCLK_SHIFT 9
151 #define OMAP54XX_CLKACTIVITY_CSI_PHY_GFCLK_WIDTH 0x1
152 #define OMAP54XX_CLKACTIVITY_CSI_PHY_GFCLK_MASK (1 << 9)
154 /* Used by CM_CUSTEFUSE_CLKSTCTRL */
155 #define OMAP54XX_CLKACTIVITY_CUSTEFUSE_L4_GICLK_SHIFT 8
156 #define OMAP54XX_CLKACTIVITY_CUSTEFUSE_L4_GICLK_WIDTH 0x1
157 #define OMAP54XX_CLKACTIVITY_CUSTEFUSE_L4_GICLK_MASK (1 << 8)
159 /* Used by CM_CUSTEFUSE_CLKSTCTRL */
160 #define OMAP54XX_CLKACTIVITY_CUSTEFUSE_SYS_GFCLK_SHIFT 9
161 #define OMAP54XX_CLKACTIVITY_CUSTEFUSE_SYS_GFCLK_WIDTH 0x1
162 #define OMAP54XX_CLKACTIVITY_CUSTEFUSE_SYS_GFCLK_MASK (1 << 9)
164 /* Used by CM_EMIF_CLKSTCTRL */
165 #define OMAP54XX_CLKACTIVITY_DLL_GCLK_SHIFT 9
166 #define OMAP54XX_CLKACTIVITY_DLL_GCLK_WIDTH 0x1
167 #define OMAP54XX_CLKACTIVITY_DLL_GCLK_MASK (1 << 9)
169 /* Used by CM_DMA_CLKSTCTRL */
170 #define OMAP54XX_CLKACTIVITY_DMA_L3_GICLK_SHIFT 8
171 #define OMAP54XX_CLKACTIVITY_DMA_L3_GICLK_WIDTH 0x1
172 #define OMAP54XX_CLKACTIVITY_DMA_L3_GICLK_MASK (1 << 8)
174 /* Used by CM_DSP_CLKSTCTRL */
175 #define OMAP54XX_CLKACTIVITY_DSP_GCLK_SHIFT 8
176 #define OMAP54XX_CLKACTIVITY_DSP_GCLK_WIDTH 0x1
177 #define OMAP54XX_CLKACTIVITY_DSP_GCLK_MASK (1 << 8)
179 /* Used by CM_DSS_CLKSTCTRL */
180 #define OMAP54XX_CLKACTIVITY_DSS_GFCLK_SHIFT 9
181 #define OMAP54XX_CLKACTIVITY_DSS_GFCLK_WIDTH 0x1
182 #define OMAP54XX_CLKACTIVITY_DSS_GFCLK_MASK (1 << 9)
184 /* Used by CM_DSS_CLKSTCTRL */
185 #define OMAP54XX_CLKACTIVITY_DSS_L3_GICLK_SHIFT 8
186 #define OMAP54XX_CLKACTIVITY_DSS_L3_GICLK_WIDTH 0x1
187 #define OMAP54XX_CLKACTIVITY_DSS_L3_GICLK_MASK (1 << 8)
189 /* Used by CM_DSS_CLKSTCTRL */
190 #define OMAP54XX_CLKACTIVITY_DSS_SYS_GFCLK_SHIFT 10
191 #define OMAP54XX_CLKACTIVITY_DSS_SYS_GFCLK_WIDTH 0x1
192 #define OMAP54XX_CLKACTIVITY_DSS_SYS_GFCLK_MASK (1 << 10)
194 /* Used by CM_EMIF_CLKSTCTRL */
195 #define OMAP54XX_CLKACTIVITY_EMIF_L3_GICLK_SHIFT 8
196 #define OMAP54XX_CLKACTIVITY_EMIF_L3_GICLK_WIDTH 0x1
197 #define OMAP54XX_CLKACTIVITY_EMIF_L3_GICLK_MASK (1 << 8)
199 /* Used by CM_EMIF_CLKSTCTRL */
200 #define OMAP54XX_CLKACTIVITY_EMIF_LL_GCLK_SHIFT 11
201 #define OMAP54XX_CLKACTIVITY_EMIF_LL_GCLK_WIDTH 0x1
202 #define OMAP54XX_CLKACTIVITY_EMIF_LL_GCLK_MASK (1 << 11)
204 /* Used by CM_EMIF_CLKSTCTRL */
205 #define OMAP54XX_CLKACTIVITY_EMIF_PHY_GCLK_SHIFT 10
206 #define OMAP54XX_CLKACTIVITY_EMIF_PHY_GCLK_WIDTH 0x1
207 #define OMAP54XX_CLKACTIVITY_EMIF_PHY_GCLK_MASK (1 << 10)
209 /* Used by CM_EMU_CLKSTCTRL */
210 #define OMAP54XX_CLKACTIVITY_EMU_SYS_GCLK_SHIFT 8
211 #define OMAP54XX_CLKACTIVITY_EMU_SYS_GCLK_WIDTH 0x1
212 #define OMAP54XX_CLKACTIVITY_EMU_SYS_GCLK_MASK (1 << 8)
214 /* Used by CM_CAM_CLKSTCTRL */
215 #define OMAP54XX_CLKACTIVITY_FDIF_GCLK_SHIFT 10
216 #define OMAP54XX_CLKACTIVITY_FDIF_GCLK_WIDTH 0x1
217 #define OMAP54XX_CLKACTIVITY_FDIF_GCLK_MASK (1 << 10)
219 /* Used by CM_ABE_CLKSTCTRL */
220 #define OMAP54XX_CLKACTIVITY_FUNC_24M_GFCLK_SHIFT 10
221 #define OMAP54XX_CLKACTIVITY_FUNC_24M_GFCLK_WIDTH 0x1
222 #define OMAP54XX_CLKACTIVITY_FUNC_24M_GFCLK_MASK (1 << 10)
224 /* Used by CM_GPU_CLKSTCTRL */
225 #define OMAP54XX_CLKACTIVITY_GPU_CORE_GCLK_SHIFT 9
226 #define OMAP54XX_CLKACTIVITY_GPU_CORE_GCLK_WIDTH 0x1
227 #define OMAP54XX_CLKACTIVITY_GPU_CORE_GCLK_MASK (1 << 9)
229 /* Used by CM_GPU_CLKSTCTRL */
230 #define OMAP54XX_CLKACTIVITY_GPU_HYD_GCLK_SHIFT 10
231 #define OMAP54XX_CLKACTIVITY_GPU_HYD_GCLK_WIDTH 0x1
232 #define OMAP54XX_CLKACTIVITY_GPU_HYD_GCLK_MASK (1 << 10)
234 /* Used by CM_GPU_CLKSTCTRL */
235 #define OMAP54XX_CLKACTIVITY_GPU_SYS_GCLK_SHIFT 8
236 #define OMAP54XX_CLKACTIVITY_GPU_SYS_GCLK_WIDTH 0x1
237 #define OMAP54XX_CLKACTIVITY_GPU_SYS_GCLK_MASK (1 << 8)
239 /* Used by CM_DSS_CLKSTCTRL */
240 #define OMAP54XX_CLKACTIVITY_HDMI_CEC_GFCLK_SHIFT 12
241 #define OMAP54XX_CLKACTIVITY_HDMI_CEC_GFCLK_WIDTH 0x1
242 #define OMAP54XX_CLKACTIVITY_HDMI_CEC_GFCLK_MASK (1 << 12)
244 /* Used by CM_DSS_CLKSTCTRL */
245 #define OMAP54XX_CLKACTIVITY_HDMI_PHY_GFCLK_SHIFT 11
246 #define OMAP54XX_CLKACTIVITY_HDMI_PHY_GFCLK_WIDTH 0x1
247 #define OMAP54XX_CLKACTIVITY_HDMI_PHY_GFCLK_MASK (1 << 11)
249 /* Used by CM_L3INIT_CLKSTCTRL */
250 #define OMAP54XX_CLKACTIVITY_HSIC_P1_480M_GFCLK_SHIFT 20
251 #define OMAP54XX_CLKACTIVITY_HSIC_P1_480M_GFCLK_WIDTH 0x1
252 #define OMAP54XX_CLKACTIVITY_HSIC_P1_480M_GFCLK_MASK (1 << 20)
254 /* Used by CM_L3INIT_CLKSTCTRL */
255 #define OMAP54XX_CLKACTIVITY_HSIC_P1_GFCLK_SHIFT 26
256 #define OMAP54XX_CLKACTIVITY_HSIC_P1_GFCLK_WIDTH 0x1
257 #define OMAP54XX_CLKACTIVITY_HSIC_P1_GFCLK_MASK (1 << 26)
259 /* Used by CM_L3INIT_CLKSTCTRL */
260 #define OMAP54XX_CLKACTIVITY_HSIC_P2_480M_GFCLK_SHIFT 21
261 #define OMAP54XX_CLKACTIVITY_HSIC_P2_480M_GFCLK_WIDTH 0x1
262 #define OMAP54XX_CLKACTIVITY_HSIC_P2_480M_GFCLK_MASK (1 << 21)
264 /* Used by CM_L3INIT_CLKSTCTRL */
265 #define OMAP54XX_CLKACTIVITY_HSIC_P2_GFCLK_SHIFT 27
266 #define OMAP54XX_CLKACTIVITY_HSIC_P2_GFCLK_WIDTH 0x1
267 #define OMAP54XX_CLKACTIVITY_HSIC_P2_GFCLK_MASK (1 << 27)
269 /* Used by CM_L3INIT_CLKSTCTRL */
270 #define OMAP54XX_CLKACTIVITY_HSIC_P3_480M_GFCLK_SHIFT 6
271 #define OMAP54XX_CLKACTIVITY_HSIC_P3_480M_GFCLK_WIDTH 0x1
272 #define OMAP54XX_CLKACTIVITY_HSIC_P3_480M_GFCLK_MASK (1 << 6)
274 /* Used by CM_L3INIT_CLKSTCTRL */
275 #define OMAP54XX_CLKACTIVITY_HSIC_P3_GFCLK_SHIFT 7
276 #define OMAP54XX_CLKACTIVITY_HSIC_P3_GFCLK_WIDTH 0x1
277 #define OMAP54XX_CLKACTIVITY_HSIC_P3_GFCLK_MASK (1 << 7)
279 /* Used by CM_L3INIT_CLKSTCTRL */
280 #define OMAP54XX_CLKACTIVITY_HSI_GFCLK_SHIFT 16
281 #define OMAP54XX_CLKACTIVITY_HSI_GFCLK_WIDTH 0x1
282 #define OMAP54XX_CLKACTIVITY_HSI_GFCLK_MASK (1 << 16)
284 /* Used by CM_IPU_CLKSTCTRL */
285 #define OMAP54XX_CLKACTIVITY_IPU_GCLK_SHIFT 8
286 #define OMAP54XX_CLKACTIVITY_IPU_GCLK_WIDTH 0x1
287 #define OMAP54XX_CLKACTIVITY_IPU_GCLK_MASK (1 << 8)
289 /* Used by CM_IVA_CLKSTCTRL */
290 #define OMAP54XX_CLKACTIVITY_IVA_GCLK_SHIFT 8
291 #define OMAP54XX_CLKACTIVITY_IVA_GCLK_WIDTH 0x1
292 #define OMAP54XX_CLKACTIVITY_IVA_GCLK_MASK (1 << 8)
294 /* Used by CM_L3INIT_CLKSTCTRL */
295 #define OMAP54XX_CLKACTIVITY_L3INIT_48M_GFCLK_SHIFT 12
296 #define OMAP54XX_CLKACTIVITY_L3INIT_48M_GFCLK_WIDTH 0x1
297 #define OMAP54XX_CLKACTIVITY_L3INIT_48M_GFCLK_MASK (1 << 12)
299 /* Used by CM_L3INIT_CLKSTCTRL */
300 #define OMAP54XX_CLKACTIVITY_L3INIT_60M_P1_GFCLK_SHIFT 28
301 #define OMAP54XX_CLKACTIVITY_L3INIT_60M_P1_GFCLK_WIDTH 0x1
302 #define OMAP54XX_CLKACTIVITY_L3INIT_60M_P1_GFCLK_MASK (1 << 28)
304 /* Used by CM_L3INIT_CLKSTCTRL */
305 #define OMAP54XX_CLKACTIVITY_L3INIT_60M_P2_GFCLK_SHIFT 29
306 #define OMAP54XX_CLKACTIVITY_L3INIT_60M_P2_GFCLK_WIDTH 0x1
307 #define OMAP54XX_CLKACTIVITY_L3INIT_60M_P2_GFCLK_MASK (1 << 29)
309 /* Used by CM_L3INIT_CLKSTCTRL */
310 #define OMAP54XX_CLKACTIVITY_L3INIT_L3_GICLK_SHIFT 8
311 #define OMAP54XX_CLKACTIVITY_L3INIT_L3_GICLK_WIDTH 0x1
312 #define OMAP54XX_CLKACTIVITY_L3INIT_L3_GICLK_MASK (1 << 8)
314 /* Used by CM_L3INIT_CLKSTCTRL */
315 #define OMAP54XX_CLKACTIVITY_L3INIT_L4_GICLK_SHIFT 9
316 #define OMAP54XX_CLKACTIVITY_L3INIT_L4_GICLK_WIDTH 0x1
317 #define OMAP54XX_CLKACTIVITY_L3INIT_L4_GICLK_MASK (1 << 9)
319 /* Used by CM_L3INIT_CLKSTCTRL */
320 #define OMAP54XX_CLKACTIVITY_L3INIT_USB_OTG_SS_LFPS_TX_GFCLK_SHIFT 11
321 #define OMAP54XX_CLKACTIVITY_L3INIT_USB_OTG_SS_LFPS_TX_GFCLK_WIDTH 0x1
322 #define OMAP54XX_CLKACTIVITY_L3INIT_USB_OTG_SS_LFPS_TX_GFCLK_MASK (1 << 11)
324 /* Used by CM_L3INSTR_CLKSTCTRL */
325 #define OMAP54XX_CLKACTIVITY_L3INSTR_DLL_AGING_GCLK_SHIFT 9
326 #define OMAP54XX_CLKACTIVITY_L3INSTR_DLL_AGING_GCLK_WIDTH 0x1
327 #define OMAP54XX_CLKACTIVITY_L3INSTR_DLL_AGING_GCLK_MASK (1 << 9)
329 /* Used by CM_L3INSTR_CLKSTCTRL */
330 #define OMAP54XX_CLKACTIVITY_L3INSTR_L3_GICLK_SHIFT 8
331 #define OMAP54XX_CLKACTIVITY_L3INSTR_L3_GICLK_WIDTH 0x1
332 #define OMAP54XX_CLKACTIVITY_L3INSTR_L3_GICLK_MASK (1 << 8)
334 /* Used by CM_L3INSTR_CLKSTCTRL */
335 #define OMAP54XX_CLKACTIVITY_L3INSTR_TS_GCLK_SHIFT 10
336 #define OMAP54XX_CLKACTIVITY_L3INSTR_TS_GCLK_WIDTH 0x1
337 #define OMAP54XX_CLKACTIVITY_L3INSTR_TS_GCLK_MASK (1 << 10)
339 /* Used by CM_L3MAIN1_CLKSTCTRL */
340 #define OMAP54XX_CLKACTIVITY_L3MAIN1_L3_GICLK_SHIFT 8
341 #define OMAP54XX_CLKACTIVITY_L3MAIN1_L3_GICLK_WIDTH 0x1
342 #define OMAP54XX_CLKACTIVITY_L3MAIN1_L3_GICLK_MASK (1 << 8)
344 /* Used by CM_L3MAIN2_CLKSTCTRL */
345 #define OMAP54XX_CLKACTIVITY_L3MAIN2_L3_GICLK_SHIFT 8
346 #define OMAP54XX_CLKACTIVITY_L3MAIN2_L3_GICLK_WIDTH 0x1
347 #define OMAP54XX_CLKACTIVITY_L3MAIN2_L3_GICLK_MASK (1 << 8)
349 /* Used by CM_L4CFG_CLKSTCTRL */
350 #define OMAP54XX_CLKACTIVITY_L4CFG_L4_GICLK_SHIFT 8
351 #define OMAP54XX_CLKACTIVITY_L4CFG_L4_GICLK_WIDTH 0x1
352 #define OMAP54XX_CLKACTIVITY_L4CFG_L4_GICLK_MASK (1 << 8)
354 /* Used by CM_L4PER_CLKSTCTRL */
355 #define OMAP54XX_CLKACTIVITY_L4PER_L4_GICLK_SHIFT 8
356 #define OMAP54XX_CLKACTIVITY_L4PER_L4_GICLK_WIDTH 0x1
357 #define OMAP54XX_CLKACTIVITY_L4PER_L4_GICLK_MASK (1 << 8)
359 /* Used by CM_L4SEC_CLKSTCTRL */
360 #define OMAP54XX_CLKACTIVITY_L4SEC_L3_GICLK_SHIFT 8
361 #define OMAP54XX_CLKACTIVITY_L4SEC_L3_GICLK_WIDTH 0x1
362 #define OMAP54XX_CLKACTIVITY_L4SEC_L3_GICLK_MASK (1 << 8)
364 /* Used by CM_L4SEC_CLKSTCTRL */
365 #define OMAP54XX_CLKACTIVITY_L4SEC_L4_GICLK_SHIFT 9
366 #define OMAP54XX_CLKACTIVITY_L4SEC_L4_GICLK_WIDTH 0x1
367 #define OMAP54XX_CLKACTIVITY_L4SEC_L4_GICLK_MASK (1 << 9)
369 /* Used by CM_MIPIEXT_CLKSTCTRL */
370 #define OMAP54XX_CLKACTIVITY_MIPIEXT_L3_GICLK_SHIFT 8
371 #define OMAP54XX_CLKACTIVITY_MIPIEXT_L3_GICLK_WIDTH 0x1
372 #define OMAP54XX_CLKACTIVITY_MIPIEXT_L3_GICLK_MASK (1 << 8)
374 /* Used by CM_MIPIEXT_CLKSTCTRL */
375 #define OMAP54XX_CLKACTIVITY_MIPIEXT_PHY_REF_GFCLK_SHIFT 11
376 #define OMAP54XX_CLKACTIVITY_MIPIEXT_PHY_REF_GFCLK_WIDTH 0x1
377 #define OMAP54XX_CLKACTIVITY_MIPIEXT_PHY_REF_GFCLK_MASK (1 << 11)
379 /* Used by CM_L3INIT_CLKSTCTRL */
380 #define OMAP54XX_CLKACTIVITY_MMC1_32K_GFCLK_SHIFT 2
381 #define OMAP54XX_CLKACTIVITY_MMC1_32K_GFCLK_WIDTH 0x1
382 #define OMAP54XX_CLKACTIVITY_MMC1_32K_GFCLK_MASK (1 << 2)
384 /* Used by CM_L3INIT_CLKSTCTRL */
385 #define OMAP54XX_CLKACTIVITY_MMC1_GFCLK_SHIFT 17
386 #define OMAP54XX_CLKACTIVITY_MMC1_GFCLK_WIDTH 0x1
387 #define OMAP54XX_CLKACTIVITY_MMC1_GFCLK_MASK (1 << 17)
389 /* Used by CM_L3INIT_CLKSTCTRL */
390 #define OMAP54XX_CLKACTIVITY_MMC2_GFCLK_SHIFT 18
391 #define OMAP54XX_CLKACTIVITY_MMC2_GFCLK_WIDTH 0x1
392 #define OMAP54XX_CLKACTIVITY_MMC2_GFCLK_MASK (1 << 18)
394 /* Used by CM_MPU_CLKSTCTRL */
395 #define OMAP54XX_CLKACTIVITY_MPU_GCLK_SHIFT 8
396 #define OMAP54XX_CLKACTIVITY_MPU_GCLK_WIDTH 0x1
397 #define OMAP54XX_CLKACTIVITY_MPU_GCLK_MASK (1 << 8)
399 /* Used by CM_ABE_CLKSTCTRL */
400 #define OMAP54XX_CLKACTIVITY_PAD_CLKS_SHIFT 14
401 #define OMAP54XX_CLKACTIVITY_PAD_CLKS_WIDTH 0x1
402 #define OMAP54XX_CLKACTIVITY_PAD_CLKS_MASK (1 << 14)
404 /* Used by CM_ABE_CLKSTCTRL */
405 #define OMAP54XX_CLKACTIVITY_PAD_SLIMBUS1_CLK_SHIFT 15
406 #define OMAP54XX_CLKACTIVITY_PAD_SLIMBUS1_CLK_WIDTH 0x1
407 #define OMAP54XX_CLKACTIVITY_PAD_SLIMBUS1_CLK_MASK (1 << 15)
409 /* Used by CM_L3INIT_CLKSTCTRL */
410 #define OMAP54XX_CLKACTIVITY_PAD_XCLK60MHSP1_SHIFT 3
411 #define OMAP54XX_CLKACTIVITY_PAD_XCLK60MHSP1_WIDTH 0x1
412 #define OMAP54XX_CLKACTIVITY_PAD_XCLK60MHSP1_MASK (1 << 3)
414 /* Used by CM_L3INIT_CLKSTCTRL */
415 #define OMAP54XX_CLKACTIVITY_PAD_XCLK60MHSP2_SHIFT 4
416 #define OMAP54XX_CLKACTIVITY_PAD_XCLK60MHSP2_WIDTH 0x1
417 #define OMAP54XX_CLKACTIVITY_PAD_XCLK60MHSP2_MASK (1 << 4)
419 /* Used by CM_L4PER_CLKSTCTRL */
420 #define OMAP54XX_CLKACTIVITY_PER_12M_GFCLK_SHIFT 15
421 #define OMAP54XX_CLKACTIVITY_PER_12M_GFCLK_WIDTH 0x1
422 #define OMAP54XX_CLKACTIVITY_PER_12M_GFCLK_MASK (1 << 15)
424 /* Used by CM_L4PER_CLKSTCTRL */
425 #define OMAP54XX_CLKACTIVITY_PER_32K_GFCLK_SHIFT 17
426 #define OMAP54XX_CLKACTIVITY_PER_32K_GFCLK_WIDTH 0x1
427 #define OMAP54XX_CLKACTIVITY_PER_32K_GFCLK_MASK (1 << 17)
429 /* Used by CM_L4PER_CLKSTCTRL */
430 #define OMAP54XX_CLKACTIVITY_PER_48M_GFCLK_SHIFT 18
431 #define OMAP54XX_CLKACTIVITY_PER_48M_GFCLK_WIDTH 0x1
432 #define OMAP54XX_CLKACTIVITY_PER_48M_GFCLK_MASK (1 << 18)
434 /* Used by CM_L4PER_CLKSTCTRL */
435 #define OMAP54XX_CLKACTIVITY_PER_96M_GFCLK_SHIFT 19
436 #define OMAP54XX_CLKACTIVITY_PER_96M_GFCLK_WIDTH 0x1
437 #define OMAP54XX_CLKACTIVITY_PER_96M_GFCLK_MASK (1 << 19)
439 /* Used by CM_L3INIT_CLKSTCTRL */
440 #define OMAP54XX_CLKACTIVITY_SATA_REF_GFCLK_SHIFT 19
441 #define OMAP54XX_CLKACTIVITY_SATA_REF_GFCLK_WIDTH 0x1
442 #define OMAP54XX_CLKACTIVITY_SATA_REF_GFCLK_MASK (1 << 19)
444 /* Used by CM_COREAON_CLKSTCTRL */
445 #define OMAP54XX_CLKACTIVITY_SR_CORE_SYS_GFCLK_SHIFT 11
446 #define OMAP54XX_CLKACTIVITY_SR_CORE_SYS_GFCLK_WIDTH 0x1
447 #define OMAP54XX_CLKACTIVITY_SR_CORE_SYS_GFCLK_MASK (1 << 11)
449 /* Used by CM_COREAON_CLKSTCTRL */
450 #define OMAP54XX_CLKACTIVITY_SR_MM_SYS_GFCLK_SHIFT 10
451 #define OMAP54XX_CLKACTIVITY_SR_MM_SYS_GFCLK_WIDTH 0x1
452 #define OMAP54XX_CLKACTIVITY_SR_MM_SYS_GFCLK_MASK (1 << 10)
454 /* Used by CM_COREAON_CLKSTCTRL */
455 #define OMAP54XX_CLKACTIVITY_SR_MPU_SYS_GFCLK_SHIFT 9
456 #define OMAP54XX_CLKACTIVITY_SR_MPU_SYS_GFCLK_WIDTH 0x1
457 #define OMAP54XX_CLKACTIVITY_SR_MPU_SYS_GFCLK_MASK (1 << 9)
459 /* Used by CM_WKUPAON_CLKSTCTRL */
460 #define OMAP54XX_CLKACTIVITY_SYS_CLK_SHIFT 8
461 #define OMAP54XX_CLKACTIVITY_SYS_CLK_WIDTH 0x1
462 #define OMAP54XX_CLKACTIVITY_SYS_CLK_MASK (1 << 8)
464 /* Used by CM_WKUPAON_CLKSTCTRL */
465 #define OMAP54XX_CLKACTIVITY_SYS_CLK_ALL_SHIFT 15
466 #define OMAP54XX_CLKACTIVITY_SYS_CLK_ALL_WIDTH 0x1
467 #define OMAP54XX_CLKACTIVITY_SYS_CLK_ALL_MASK (1 << 15)
469 /* Used by CM_WKUPAON_CLKSTCTRL */
470 #define OMAP54XX_CLKACTIVITY_SYS_CLK_FUNC_SHIFT 14
471 #define OMAP54XX_CLKACTIVITY_SYS_CLK_FUNC_WIDTH 0x1
472 #define OMAP54XX_CLKACTIVITY_SYS_CLK_FUNC_MASK (1 << 14)
474 /* Used by CM_L4PER_CLKSTCTRL */
475 #define OMAP54XX_CLKACTIVITY_TIMER10_GFCLK_SHIFT 9
476 #define OMAP54XX_CLKACTIVITY_TIMER10_GFCLK_WIDTH 0x1
477 #define OMAP54XX_CLKACTIVITY_TIMER10_GFCLK_MASK (1 << 9)
479 /* Used by CM_L4PER_CLKSTCTRL */
480 #define OMAP54XX_CLKACTIVITY_TIMER11_GFCLK_SHIFT 10
481 #define OMAP54XX_CLKACTIVITY_TIMER11_GFCLK_WIDTH 0x1
482 #define OMAP54XX_CLKACTIVITY_TIMER11_GFCLK_MASK (1 << 10)
484 /* Used by CM_L4PER_CLKSTCTRL */
485 #define OMAP54XX_CLKACTIVITY_TIMER2_GFCLK_SHIFT 11
486 #define OMAP54XX_CLKACTIVITY_TIMER2_GFCLK_WIDTH 0x1
487 #define OMAP54XX_CLKACTIVITY_TIMER2_GFCLK_MASK (1 << 11)
489 /* Used by CM_L4PER_CLKSTCTRL */
490 #define OMAP54XX_CLKACTIVITY_TIMER3_GFCLK_SHIFT 12
491 #define OMAP54XX_CLKACTIVITY_TIMER3_GFCLK_WIDTH 0x1
492 #define OMAP54XX_CLKACTIVITY_TIMER3_GFCLK_MASK (1 << 12)
494 /* Used by CM_L4PER_CLKSTCTRL */
495 #define OMAP54XX_CLKACTIVITY_TIMER4_GFCLK_SHIFT 13
496 #define OMAP54XX_CLKACTIVITY_TIMER4_GFCLK_WIDTH 0x1
497 #define OMAP54XX_CLKACTIVITY_TIMER4_GFCLK_MASK (1 << 13)
499 /* Used by CM_L4PER_CLKSTCTRL */
500 #define OMAP54XX_CLKACTIVITY_TIMER9_GFCLK_SHIFT 14
501 #define OMAP54XX_CLKACTIVITY_TIMER9_GFCLK_WIDTH 0x1
502 #define OMAP54XX_CLKACTIVITY_TIMER9_GFCLK_MASK (1 << 14)
504 /* Used by CM_L3INIT_CLKSTCTRL */
505 #define OMAP54XX_CLKACTIVITY_TLL_CH0_GFCLK_SHIFT 22
506 #define OMAP54XX_CLKACTIVITY_TLL_CH0_GFCLK_WIDTH 0x1
507 #define OMAP54XX_CLKACTIVITY_TLL_CH0_GFCLK_MASK (1 << 22)
509 /* Used by CM_L3INIT_CLKSTCTRL */
510 #define OMAP54XX_CLKACTIVITY_TLL_CH1_GFCLK_SHIFT 23
511 #define OMAP54XX_CLKACTIVITY_TLL_CH1_GFCLK_WIDTH 0x1
512 #define OMAP54XX_CLKACTIVITY_TLL_CH1_GFCLK_MASK (1 << 23)
514 /* Used by CM_L3INIT_CLKSTCTRL */
515 #define OMAP54XX_CLKACTIVITY_TLL_CH2_GFCLK_SHIFT 24
516 #define OMAP54XX_CLKACTIVITY_TLL_CH2_GFCLK_WIDTH 0x1
517 #define OMAP54XX_CLKACTIVITY_TLL_CH2_GFCLK_MASK (1 << 24)
519 /* Used by CM_MIPIEXT_CLKSTCTRL */
520 #define OMAP54XX_CLKACTIVITY_UNIPRO1_DPLL_CLK_SHIFT 10
521 #define OMAP54XX_CLKACTIVITY_UNIPRO1_DPLL_CLK_WIDTH 0x1
522 #define OMAP54XX_CLKACTIVITY_UNIPRO1_DPLL_CLK_MASK (1 << 10)
524 /* Used by CM_MIPIEXT_CLKSTCTRL */
525 #define OMAP54XX_CLKACTIVITY_UNIPRO1_PHY_GFCLK_SHIFT 13
526 #define OMAP54XX_CLKACTIVITY_UNIPRO1_PHY_GFCLK_WIDTH 0x1
527 #define OMAP54XX_CLKACTIVITY_UNIPRO1_PHY_GFCLK_MASK (1 << 13)
529 /* Used by CM_MIPIEXT_CLKSTCTRL */
530 #define OMAP54XX_CLKACTIVITY_UNIPRO1_TXPHY_LS_GFCLK_SHIFT 12
531 #define OMAP54XX_CLKACTIVITY_UNIPRO1_TXPHY_LS_GFCLK_WIDTH 0x1
532 #define OMAP54XX_CLKACTIVITY_UNIPRO1_TXPHY_LS_GFCLK_MASK (1 << 12)
534 /* Used by CM_L3INIT_CLKSTCTRL */
535 #define OMAP54XX_CLKACTIVITY_UNIPRO2_DPLL_CLK_SHIFT 10
536 #define OMAP54XX_CLKACTIVITY_UNIPRO2_DPLL_CLK_WIDTH 0x1
537 #define OMAP54XX_CLKACTIVITY_UNIPRO2_DPLL_CLK_MASK (1 << 10)
539 /* Used by CM_L3INIT_CLKSTCTRL */
540 #define OMAP54XX_CLKACTIVITY_UNIPRO2_PHY_GFCLK_SHIFT 13
541 #define OMAP54XX_CLKACTIVITY_UNIPRO2_PHY_GFCLK_WIDTH 0x1
542 #define OMAP54XX_CLKACTIVITY_UNIPRO2_PHY_GFCLK_MASK (1 << 13)
544 /* Used by CM_L3INIT_CLKSTCTRL */
545 #define OMAP54XX_CLKACTIVITY_UNIPRO2_PHY_REF_GFCLK_SHIFT 5
546 #define OMAP54XX_CLKACTIVITY_UNIPRO2_PHY_REF_GFCLK_WIDTH 0x1
547 #define OMAP54XX_CLKACTIVITY_UNIPRO2_PHY_REF_GFCLK_MASK (1 << 5)
549 /* Used by CM_L3INIT_CLKSTCTRL */
550 #define OMAP54XX_CLKACTIVITY_USB_DPLL_CLK_SHIFT 14
551 #define OMAP54XX_CLKACTIVITY_USB_DPLL_CLK_WIDTH 0x1
552 #define OMAP54XX_CLKACTIVITY_USB_DPLL_CLK_MASK (1 << 14)
554 /* Used by CM_L3INIT_CLKSTCTRL */
555 #define OMAP54XX_CLKACTIVITY_USB_DPLL_HS_CLK_SHIFT 15
556 #define OMAP54XX_CLKACTIVITY_USB_DPLL_HS_CLK_WIDTH 0x1
557 #define OMAP54XX_CLKACTIVITY_USB_DPLL_HS_CLK_MASK (1 << 15)
559 /* Used by CM_L3INIT_CLKSTCTRL */
560 #define OMAP54XX_CLKACTIVITY_USB_OTG_SS_REF_CLK_SHIFT 31
561 #define OMAP54XX_CLKACTIVITY_USB_OTG_SS_REF_CLK_WIDTH 0x1
562 #define OMAP54XX_CLKACTIVITY_USB_OTG_SS_REF_CLK_MASK (1 << 31)
564 /* Used by CM_L3INIT_CLKSTCTRL */
565 #define OMAP54XX_CLKACTIVITY_UTMI_P3_GFCLK_SHIFT 30
566 #define OMAP54XX_CLKACTIVITY_UTMI_P3_GFCLK_WIDTH 0x1
567 #define OMAP54XX_CLKACTIVITY_UTMI_P3_GFCLK_MASK (1 << 30)
569 /* Used by CM_L3INIT_CLKSTCTRL */
570 #define OMAP54XX_CLKACTIVITY_UTMI_ROOT_GFCLK_SHIFT 25
571 #define OMAP54XX_CLKACTIVITY_UTMI_ROOT_GFCLK_WIDTH 0x1
572 #define OMAP54XX_CLKACTIVITY_UTMI_ROOT_GFCLK_MASK (1 << 25)
574 /* Used by CM_WKUPAON_CLKSTCTRL */
575 #define OMAP54XX_CLKACTIVITY_WKUPAON_32K_GFCLK_SHIFT 11
576 #define OMAP54XX_CLKACTIVITY_WKUPAON_32K_GFCLK_WIDTH 0x1
577 #define OMAP54XX_CLKACTIVITY_WKUPAON_32K_GFCLK_MASK (1 << 11)
579 /* Used by CM_WKUPAON_CLKSTCTRL */
580 #define OMAP54XX_CLKACTIVITY_WKUPAON_GICLK_SHIFT 12
581 #define OMAP54XX_CLKACTIVITY_WKUPAON_GICLK_WIDTH 0x1
582 #define OMAP54XX_CLKACTIVITY_WKUPAON_GICLK_MASK (1 << 12)
584 /* Used by CM_WKUPAON_CLKSTCTRL */
585 #define OMAP54XX_CLKACTIVITY_WKUPAON_IO_SRCOMP_GFCLK_SHIFT 13
586 #define OMAP54XX_CLKACTIVITY_WKUPAON_IO_SRCOMP_GFCLK_WIDTH 0x1
587 #define OMAP54XX_CLKACTIVITY_WKUPAON_IO_SRCOMP_GFCLK_MASK (1 << 13)
589 /* Used by CM_COREAON_IO_SRCOMP_CLKCTRL, CM_WKUPAON_IO_SRCOMP_CLKCTRL */
590 #define OMAP54XX_CLKEN_SRCOMP_FCLK_SHIFT 8
591 #define OMAP54XX_CLKEN_SRCOMP_FCLK_WIDTH 0x1
592 #define OMAP54XX_CLKEN_SRCOMP_FCLK_MASK (1 << 8)
595 * Used by CM_ABE_TIMER5_CLKCTRL, CM_ABE_TIMER6_CLKCTRL, CM_ABE_TIMER7_CLKCTRL,
596 * CM_ABE_TIMER8_CLKCTRL, CM_L3INIT_HSI_CLKCTRL, CM_L4PER_TIMER10_CLKCTRL,
597 * CM_L4PER_TIMER11_CLKCTRL, CM_L4PER_TIMER2_CLKCTRL, CM_L4PER_TIMER3_CLKCTRL,
598 * CM_L4PER_TIMER4_CLKCTRL, CM_L4PER_TIMER9_CLKCTRL, CM_WKUPAON_TIMER1_CLKCTRL
600 #define OMAP54XX_CLKSEL_SHIFT 24
601 #define OMAP54XX_CLKSEL_WIDTH 0x1
602 #define OMAP54XX_CLKSEL_MASK (1 << 24)
605 * Renamed from CLKSEL Used by CM_CLKSEL_ABE_DSS_SYS, CM_CLKSEL_ABE_PLL_REF,
606 * CM_CLKSEL_USB_60MHZ, CM_CLKSEL_WKUPAON
608 #define OMAP54XX_CLKSEL_0_0_SHIFT 0
609 #define OMAP54XX_CLKSEL_0_0_WIDTH 0x1
610 #define OMAP54XX_CLKSEL_0_0_MASK (1 << 0)
612 /* Renamed from CLKSEL Used by CM_BYPCLK_DPLL_IVA, CM_BYPCLK_DPLL_MPU */
613 #define OMAP54XX_CLKSEL_0_1_SHIFT 0
614 #define OMAP54XX_CLKSEL_0_1_WIDTH 0x2
615 #define OMAP54XX_CLKSEL_0_1_MASK (0x3 << 0)
617 /* Renamed from CLKSEL Used by CM_L3INSTR_CTRL_MODULE_BANDGAP_CLKCTRL */
618 #define OMAP54XX_CLKSEL_24_25_SHIFT 24
619 #define OMAP54XX_CLKSEL_24_25_WIDTH 0x2
620 #define OMAP54XX_CLKSEL_24_25_MASK (0x3 << 24)
622 /* Used by CM_MPU_MPU_CLKCTRL */
623 #define OMAP54XX_CLKSEL_ABE_DIV_MODE_SHIFT 26
624 #define OMAP54XX_CLKSEL_ABE_DIV_MODE_WIDTH 0x1
625 #define OMAP54XX_CLKSEL_ABE_DIV_MODE_MASK (1 << 26)
627 /* Used by CM_ABE_AESS_CLKCTRL */
628 #define OMAP54XX_CLKSEL_AESS_FCLK_SHIFT 24
629 #define OMAP54XX_CLKSEL_AESS_FCLK_WIDTH 0x1
630 #define OMAP54XX_CLKSEL_AESS_FCLK_MASK (1 << 24)
632 /* Used by CM_L3INIT_MMC1_CLKCTRL, CM_L3INIT_MMC2_CLKCTRL */
633 #define OMAP54XX_CLKSEL_DIV_SHIFT 25
634 #define OMAP54XX_CLKSEL_DIV_WIDTH 0x1
635 #define OMAP54XX_CLKSEL_DIV_MASK (1 << 25)
637 /* Used by CM_MPU_MPU_CLKCTRL */
638 #define OMAP54XX_CLKSEL_EMIF_DIV_MODE_SHIFT 24
639 #define OMAP54XX_CLKSEL_EMIF_DIV_MODE_WIDTH 0x2
640 #define OMAP54XX_CLKSEL_EMIF_DIV_MODE_MASK (0x3 << 24)
642 /* Used by CM_CAM_FDIF_CLKCTRL */
643 #define OMAP54XX_CLKSEL_FCLK_SHIFT 24
644 #define OMAP54XX_CLKSEL_FCLK_WIDTH 0x1
645 #define OMAP54XX_CLKSEL_FCLK_MASK (1 << 24)
647 /* Used by CM_GPU_GPU_CLKCTRL */
648 #define OMAP54XX_CLKSEL_GPU_CORE_GCLK_SHIFT 24
649 #define OMAP54XX_CLKSEL_GPU_CORE_GCLK_WIDTH 0x1
650 #define OMAP54XX_CLKSEL_GPU_CORE_GCLK_MASK (1 << 24)
652 /* Used by CM_GPU_GPU_CLKCTRL */
653 #define OMAP54XX_CLKSEL_GPU_HYD_GCLK_SHIFT 25
654 #define OMAP54XX_CLKSEL_GPU_HYD_GCLK_WIDTH 0x1
655 #define OMAP54XX_CLKSEL_GPU_HYD_GCLK_MASK (1 << 25)
657 /* Used by CM_GPU_GPU_CLKCTRL */
658 #define OMAP54XX_CLKSEL_GPU_SYS_CLK_SHIFT 26
659 #define OMAP54XX_CLKSEL_GPU_SYS_CLK_WIDTH 0x1
660 #define OMAP54XX_CLKSEL_GPU_SYS_CLK_MASK (1 << 26)
663 * Used by CM_ABE_DMIC_CLKCTRL, CM_ABE_MCASP_CLKCTRL, CM_ABE_MCBSP1_CLKCTRL,
664 * CM_ABE_MCBSP2_CLKCTRL, CM_ABE_MCBSP3_CLKCTRL
666 #define OMAP54XX_CLKSEL_INTERNAL_SOURCE_SHIFT 26
667 #define OMAP54XX_CLKSEL_INTERNAL_SOURCE_WIDTH 0x2
668 #define OMAP54XX_CLKSEL_INTERNAL_SOURCE_MASK (0x3 << 26)
670 /* Used by CM_CLKSEL_CORE */
671 #define OMAP54XX_CLKSEL_L3_SHIFT 4
672 #define OMAP54XX_CLKSEL_L3_WIDTH 0x1
673 #define OMAP54XX_CLKSEL_L3_MASK (1 << 4)
675 /* Renamed from CLKSEL_L3 Used by CM_SHADOW_FREQ_CONFIG2 */
676 #define OMAP54XX_CLKSEL_L3_1_1_SHIFT 1
677 #define OMAP54XX_CLKSEL_L3_1_1_WIDTH 0x1
678 #define OMAP54XX_CLKSEL_L3_1_1_MASK (1 << 1)
680 /* Used by CM_CLKSEL_CORE */
681 #define OMAP54XX_CLKSEL_L4_SHIFT 8
682 #define OMAP54XX_CLKSEL_L4_WIDTH 0x1
683 #define OMAP54XX_CLKSEL_L4_MASK (1 << 8)
685 /* Used by CM_EMIF_EMIF1_CLKCTRL */
686 #define OMAP54XX_CLKSEL_LL_SHIFT 24
687 #define OMAP54XX_CLKSEL_LL_WIDTH 0x1
688 #define OMAP54XX_CLKSEL_LL_MASK (1 << 24)
690 /* Used by CM_CLKSEL_ABE */
691 #define OMAP54XX_CLKSEL_OPP_SHIFT 0
692 #define OMAP54XX_CLKSEL_OPP_WIDTH 0x2
693 #define OMAP54XX_CLKSEL_OPP_MASK (0x3 << 0)
695 /* Renamed from CLKSEL_OPP Used by CM_L3INIT_UNIPRO2_CLKCTRL */
696 #define OMAP54XX_CLKSEL_OPP_24_24_SHIFT 24
697 #define OMAP54XX_CLKSEL_OPP_24_24_WIDTH 0x1
698 #define OMAP54XX_CLKSEL_OPP_24_24_MASK (1 << 24)
701 * Used by CM_ABE_DMIC_CLKCTRL, CM_ABE_MCASP_CLKCTRL, CM_ABE_MCBSP1_CLKCTRL,
702 * CM_ABE_MCBSP2_CLKCTRL, CM_ABE_MCBSP3_CLKCTRL
704 #define OMAP54XX_CLKSEL_SOURCE_SHIFT 24
705 #define OMAP54XX_CLKSEL_SOURCE_WIDTH 0x2
706 #define OMAP54XX_CLKSEL_SOURCE_MASK (0x3 << 24)
709 * Renamed from CLKSEL_SOURCE Used by CM_L3INIT_MMC1_CLKCTRL,
710 * CM_L3INIT_MMC2_CLKCTRL
712 #define OMAP54XX_CLKSEL_SOURCE_L3INIT_MMC1_SHIFT 24
713 #define OMAP54XX_CLKSEL_SOURCE_L3INIT_MMC1_WIDTH 0x1
714 #define OMAP54XX_CLKSEL_SOURCE_L3INIT_MMC1_MASK (1 << 24)
716 /* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */
717 #define OMAP54XX_CLKSEL_UTMI_P1_SHIFT 24
718 #define OMAP54XX_CLKSEL_UTMI_P1_WIDTH 0x1
719 #define OMAP54XX_CLKSEL_UTMI_P1_MASK (1 << 24)
721 /* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */
722 #define OMAP54XX_CLKSEL_UTMI_P2_SHIFT 25
723 #define OMAP54XX_CLKSEL_UTMI_P2_WIDTH 0x1
724 #define OMAP54XX_CLKSEL_UTMI_P2_MASK (1 << 25)
727 * Used by CM_DIV_H11_DPLL_CORE, CM_DIV_H11_DPLL_IVA, CM_DIV_H11_DPLL_PER,
728 * CM_DIV_H12_DPLL_CORE, CM_DIV_H12_DPLL_IVA, CM_DIV_H12_DPLL_PER,
729 * CM_DIV_H13_DPLL_CORE, CM_DIV_H13_DPLL_PER, CM_DIV_H14_DPLL_CORE,
730 * CM_DIV_H14_DPLL_PER, CM_DIV_H21_DPLL_CORE, CM_DIV_H22_DPLL_CORE,
731 * CM_DIV_H23_DPLL_CORE, CM_DIV_H24_DPLL_CORE, CM_DIV_M2_DPLL_ABE,
732 * CM_DIV_M2_DPLL_CORE, CM_DIV_M2_DPLL_MPU, CM_DIV_M2_DPLL_PER,
733 * CM_DIV_M2_DPLL_UNIPRO1, CM_DIV_M2_DPLL_UNIPRO2, CM_DIV_M2_DPLL_USB,
734 * CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE, CM_DIV_M3_DPLL_PER
736 #define OMAP54XX_CLKST_SHIFT 9
737 #define OMAP54XX_CLKST_WIDTH 0x1
738 #define OMAP54XX_CLKST_MASK (1 << 9)
741 * Used by CM_ABE_CLKSTCTRL, CM_C2C_CLKSTCTRL, CM_CAM_CLKSTCTRL,
742 * CM_COREAON_CLKSTCTRL, CM_CUSTEFUSE_CLKSTCTRL, CM_DMA_CLKSTCTRL,
743 * CM_DSP_CLKSTCTRL, CM_DSS_CLKSTCTRL, CM_EMIF_CLKSTCTRL, CM_EMU_CLKSTCTRL,
744 * CM_GPU_CLKSTCTRL, CM_IPU_CLKSTCTRL, CM_IVA_CLKSTCTRL, CM_L3INIT_CLKSTCTRL,
745 * CM_L3INSTR_CLKSTCTRL, CM_L3MAIN1_CLKSTCTRL, CM_L3MAIN2_CLKSTCTRL,
746 * CM_L4CFG_CLKSTCTRL, CM_L4PER_CLKSTCTRL, CM_L4SEC_CLKSTCTRL,
747 * CM_MIPIEXT_CLKSTCTRL, CM_MPU_CLKSTCTRL, CM_WKUPAON_CLKSTCTRL
749 #define OMAP54XX_CLKTRCTRL_SHIFT 0
750 #define OMAP54XX_CLKTRCTRL_WIDTH 0x2
751 #define OMAP54XX_CLKTRCTRL_MASK (0x3 << 0)
753 /* Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_PER */
754 #define OMAP54XX_CLKX2ST_SHIFT 11
755 #define OMAP54XX_CLKX2ST_WIDTH 0x1
756 #define OMAP54XX_CLKX2ST_MASK (1 << 11)
758 /* Used by CM_L4CFG_DYNAMICDEP */
759 #define OMAP54XX_COREAON_DYNDEP_SHIFT 16
760 #define OMAP54XX_COREAON_DYNDEP_WIDTH 0x1
761 #define OMAP54XX_COREAON_DYNDEP_MASK (1 << 16)
763 /* Used by CM_DSP_STATICDEP, CM_IPU_STATICDEP, CM_MPU_STATICDEP */
764 #define OMAP54XX_COREAON_STATDEP_SHIFT 16
765 #define OMAP54XX_COREAON_STATDEP_WIDTH 0x1
766 #define OMAP54XX_COREAON_STATDEP_MASK (1 << 16)
768 /* Used by CM_L4CFG_DYNAMICDEP */
769 #define OMAP54XX_CUSTEFUSE_DYNDEP_SHIFT 17
770 #define OMAP54XX_CUSTEFUSE_DYNDEP_WIDTH 0x1
771 #define OMAP54XX_CUSTEFUSE_DYNDEP_MASK (1 << 17)
773 /* Used by CM_DSP_STATICDEP, CM_IPU_STATICDEP, CM_MPU_STATICDEP */
774 #define OMAP54XX_CUSTEFUSE_STATDEP_SHIFT 17
775 #define OMAP54XX_CUSTEFUSE_STATDEP_WIDTH 0x1
776 #define OMAP54XX_CUSTEFUSE_STATDEP_MASK (1 << 17)
778 /* Used by REVISION_CM_CORE, REVISION_CM_CORE_AON */
779 #define OMAP54XX_CUSTOM_SHIFT 6
780 #define OMAP54XX_CUSTOM_WIDTH 0x2
781 #define OMAP54XX_CUSTOM_MASK (0x3 << 6)
784 * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_IVA,
785 * CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER, CM_CLKSEL_DPLL_UNIPRO1,
786 * CM_CLKSEL_DPLL_UNIPRO2, CM_CLKSEL_DPLL_USB
788 #define OMAP54XX_DCC_EN_SHIFT 22
789 #define OMAP54XX_DCC_EN_WIDTH 0x1
790 #define OMAP54XX_DCC_EN_MASK (1 << 22)
793 * Used by CM_CORE_AON_DEBUG_CM_CORE_AON_FD_TRANS,
794 * CM_CORE_AON_DEBUG_DSS_FD_TRANS, CM_CORE_AON_DEBUG_EMIF_FD_TRANS,
795 * CM_CORE_AON_DEBUG_L4SEC_FD_TRANS
797 #define OMAP54XX_CM_DEBUG_OUT_SHIFT 0
798 #define OMAP54XX_CM_DEBUG_OUT_WIDTH 0xd
799 #define OMAP54XX_CM_DEBUG_OUT_MASK (0x1fff << 0)
802 * Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_ABE_FD_TRANS,
803 * CM_CORE_AON_DEBUG_L3INIT_FD_TRANS, CM_CORE_AON_DEBUG_L4PER_FD_TRANS
805 #define OMAP54XX_DEBUG_OUT_0_31_SHIFT 0
806 #define OMAP54XX_DEBUG_OUT_0_31_WIDTH 0x20
807 #define OMAP54XX_DEBUG_OUT_0_31_MASK (0xffffffff << 0)
810 * Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_C2C_FD_TRANS,
811 * CM_CORE_AON_DEBUG_COREAON_FD_TRANS, CM_CORE_AON_DEBUG_L4CFG_FD_TRANS
813 #define OMAP54XX_DEBUG_OUT_0_8_SHIFT 0
814 #define OMAP54XX_DEBUG_OUT_0_8_WIDTH 0x9
815 #define OMAP54XX_DEBUG_OUT_0_8_MASK (0x1ff << 0)
818 * Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_CUSTEFUSE_FD_TRANS,
819 * CM_CORE_AON_DEBUG_DMA_FD_TRANS, CM_CORE_AON_DEBUG_L3MAIN1_FD_TRANS
821 #define OMAP54XX_DEBUG_OUT_0_4_SHIFT 0
822 #define OMAP54XX_DEBUG_OUT_0_4_WIDTH 0x5
823 #define OMAP54XX_DEBUG_OUT_0_4_MASK (0x1f << 0)
826 * Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_DSP_FD_TRANS,
827 * CM_CORE_AON_DEBUG_IPU_FD_TRANS, CM_CORE_AON_DEBUG_MPU_FD_TRANS
829 #define OMAP54XX_DEBUG_OUT_0_5_SHIFT 0
830 #define OMAP54XX_DEBUG_OUT_0_5_WIDTH 0x6
831 #define OMAP54XX_DEBUG_OUT_0_5_MASK (0x3f << 0)
834 * Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_CAM_FD_TRANS,
835 * CM_CORE_AON_DEBUG_MIPIEXT_FD_TRANS
837 #define OMAP54XX_DEBUG_OUT_0_10_SHIFT 0
838 #define OMAP54XX_DEBUG_OUT_0_10_WIDTH 0xb
839 #define OMAP54XX_DEBUG_OUT_0_10_MASK (0x7ff << 0)
842 * Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_IVA_FD_TRANS,
843 * CM_CORE_AON_DEBUG_L3MAIN2_FD_TRANS
845 #define OMAP54XX_DEBUG_OUT_0_6_SHIFT 0
846 #define OMAP54XX_DEBUG_OUT_0_6_WIDTH 0x7
847 #define OMAP54XX_DEBUG_OUT_0_6_MASK (0x7f << 0)
849 /* Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_ABE_FD_TRANS2 */
850 #define OMAP54XX_DEBUG_OUT_0_19_SHIFT 0
851 #define OMAP54XX_DEBUG_OUT_0_19_WIDTH 0x14
852 #define OMAP54XX_DEBUG_OUT_0_19_MASK (0xfffff << 0)
854 /* Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_GPU_FD_TRANS */
855 #define OMAP54XX_DEBUG_OUT_0_9_SHIFT 0
856 #define OMAP54XX_DEBUG_OUT_0_9_WIDTH 0xa
857 #define OMAP54XX_DEBUG_OUT_0_9_MASK (0x3ff << 0)
859 /* Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_L3INIT_FD_TRANS2 */
860 #define OMAP54XX_DEBUG_OUT_0_26_SHIFT 0
861 #define OMAP54XX_DEBUG_OUT_0_26_WIDTH 0x1b
862 #define OMAP54XX_DEBUG_OUT_0_26_MASK (0x7ffffff << 0)
864 /* Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_L3INSTR_FD_TRANS */
865 #define OMAP54XX_DEBUG_OUT_0_13_SHIFT 0
866 #define OMAP54XX_DEBUG_OUT_0_13_WIDTH 0xe
867 #define OMAP54XX_DEBUG_OUT_0_13_MASK (0x3fff << 0)
869 /* Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_L4PER_FD_TRANS2 */
870 #define OMAP54XX_DEBUG_OUT_0_21_SHIFT 0
871 #define OMAP54XX_DEBUG_OUT_0_21_WIDTH 0x16
872 #define OMAP54XX_DEBUG_OUT_0_21_MASK (0x3fffff << 0)
875 * Used by CM_SSC_DELTAMSTEP_DPLL_ABE, CM_SSC_DELTAMSTEP_DPLL_CORE,
876 * CM_SSC_DELTAMSTEP_DPLL_IVA, CM_SSC_DELTAMSTEP_DPLL_MPU,
877 * CM_SSC_DELTAMSTEP_DPLL_PER
879 #define OMAP54XX_DELTAMSTEP_SHIFT 0
880 #define OMAP54XX_DELTAMSTEP_WIDTH 0x14
881 #define OMAP54XX_DELTAMSTEP_MASK (0xfffff << 0)
884 * Renamed from DELTAMSTEP Used by CM_SSC_DELTAMSTEP_DPLL_UNIPRO1,
885 * CM_SSC_DELTAMSTEP_DPLL_UNIPRO2, CM_SSC_DELTAMSTEP_DPLL_USB
887 #define OMAP54XX_DELTAMSTEP_0_20_SHIFT 0
888 #define OMAP54XX_DELTAMSTEP_0_20_WIDTH 0x15
889 #define OMAP54XX_DELTAMSTEP_0_20_MASK (0x1fffff << 0)
892 * Used by CM_DIV_H11_DPLL_CORE, CM_DIV_H11_DPLL_IVA, CM_DIV_H11_DPLL_PER,
893 * CM_DIV_H12_DPLL_CORE, CM_DIV_H12_DPLL_IVA, CM_DIV_H12_DPLL_PER,
894 * CM_DIV_H13_DPLL_CORE, CM_DIV_H13_DPLL_PER, CM_DIV_H14_DPLL_CORE,
895 * CM_DIV_H14_DPLL_PER, CM_DIV_H21_DPLL_CORE, CM_DIV_H22_DPLL_CORE,
896 * CM_DIV_H23_DPLL_CORE, CM_DIV_H24_DPLL_CORE
898 #define OMAP54XX_DIVHS_SHIFT 0
899 #define OMAP54XX_DIVHS_WIDTH 0x6
900 #define OMAP54XX_DIVHS_MASK (0x3f << 0)
903 * Renamed from DIVHS Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE,
904 * CM_DIV_M2_DPLL_MPU, CM_DIV_M2_DPLL_PER, CM_DIV_M3_DPLL_ABE,
905 * CM_DIV_M3_DPLL_CORE, CM_DIV_M3_DPLL_PER
907 #define OMAP54XX_DIVHS_0_4_SHIFT 0
908 #define OMAP54XX_DIVHS_0_4_WIDTH 0x5
909 #define OMAP54XX_DIVHS_0_4_MASK (0x1f << 0)
912 * Renamed from DIVHS Used by CM_DIV_M2_DPLL_UNIPRO1, CM_DIV_M2_DPLL_UNIPRO2,
915 #define OMAP54XX_DIVHS_0_6_SHIFT 0
916 #define OMAP54XX_DIVHS_0_6_WIDTH 0x7
917 #define OMAP54XX_DIVHS_0_6_MASK (0x7f << 0)
919 /* Used by CM_DLL_CTRL */
920 #define OMAP54XX_DLL_OVERRIDE_SHIFT 0
921 #define OMAP54XX_DLL_OVERRIDE_WIDTH 0x1
922 #define OMAP54XX_DLL_OVERRIDE_MASK (1 << 0)
924 /* Renamed from DLL_OVERRIDE Used by CM_SHADOW_FREQ_CONFIG1 */
925 #define OMAP54XX_DLL_OVERRIDE_2_2_SHIFT 2
926 #define OMAP54XX_DLL_OVERRIDE_2_2_WIDTH 0x1
927 #define OMAP54XX_DLL_OVERRIDE_2_2_MASK (1 << 2)
929 /* Used by CM_SHADOW_FREQ_CONFIG1 */
930 #define OMAP54XX_DLL_RESET_SHIFT 3
931 #define OMAP54XX_DLL_RESET_WIDTH 0x1
932 #define OMAP54XX_DLL_RESET_MASK (1 << 3)
935 * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_IVA,
936 * CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER, CM_CLKSEL_DPLL_UNIPRO1,
937 * CM_CLKSEL_DPLL_UNIPRO2, CM_CLKSEL_DPLL_USB
939 #define OMAP54XX_DPLL_BYP_CLKSEL_SHIFT 23
940 #define OMAP54XX_DPLL_BYP_CLKSEL_WIDTH 0x1
941 #define OMAP54XX_DPLL_BYP_CLKSEL_MASK (1 << 23)
943 /* Used by CM_CLKSEL_DPLL_CORE */
944 #define OMAP54XX_DPLL_CLKOUTHIF_CLKSEL_SHIFT 20
945 #define OMAP54XX_DPLL_CLKOUTHIF_CLKSEL_WIDTH 0x1
946 #define OMAP54XX_DPLL_CLKOUTHIF_CLKSEL_MASK (1 << 20)
948 /* Used by CM_SHADOW_FREQ_CONFIG1 */
949 #define OMAP54XX_DPLL_CORE_DPLL_EN_SHIFT 8
950 #define OMAP54XX_DPLL_CORE_DPLL_EN_WIDTH 0x3
951 #define OMAP54XX_DPLL_CORE_DPLL_EN_MASK (0x7 << 8)
953 /* Used by CM_SHADOW_FREQ_CONFIG2 */
954 #define OMAP54XX_DPLL_CORE_H12_DIV_SHIFT 2
955 #define OMAP54XX_DPLL_CORE_H12_DIV_WIDTH 0x6
956 #define OMAP54XX_DPLL_CORE_H12_DIV_MASK (0x3f << 2)
958 /* Used by CM_SHADOW_FREQ_CONFIG1 */
959 #define OMAP54XX_DPLL_CORE_M2_DIV_SHIFT 11
960 #define OMAP54XX_DPLL_CORE_M2_DIV_WIDTH 0x5
961 #define OMAP54XX_DPLL_CORE_M2_DIV_MASK (0x1f << 11)
964 * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_IVA,
965 * CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER
967 #define OMAP54XX_DPLL_DIV_SHIFT 0
968 #define OMAP54XX_DPLL_DIV_WIDTH 0x7
969 #define OMAP54XX_DPLL_DIV_MASK (0x7f << 0)
972 * Renamed from DPLL_DIV Used by CM_CLKSEL_DPLL_UNIPRO1,
973 * CM_CLKSEL_DPLL_UNIPRO2, CM_CLKSEL_DPLL_USB
975 #define OMAP54XX_DPLL_DIV_0_7_SHIFT 0
976 #define OMAP54XX_DPLL_DIV_0_7_WIDTH 0x8
977 #define OMAP54XX_DPLL_DIV_0_7_MASK (0xff << 0)
980 * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_IVA,
981 * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER
983 #define OMAP54XX_DPLL_DRIFTGUARD_EN_SHIFT 8
984 #define OMAP54XX_DPLL_DRIFTGUARD_EN_WIDTH 0x1
985 #define OMAP54XX_DPLL_DRIFTGUARD_EN_MASK (1 << 8)
988 * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_IVA,
989 * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO1,
990 * CM_CLKMODE_DPLL_UNIPRO2, CM_CLKMODE_DPLL_USB
992 #define OMAP54XX_DPLL_EN_SHIFT 0
993 #define OMAP54XX_DPLL_EN_WIDTH 0x3
994 #define OMAP54XX_DPLL_EN_MASK (0x7 << 0)
997 * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_IVA,
998 * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER
1000 #define OMAP54XX_DPLL_LPMODE_EN_SHIFT 10
1001 #define OMAP54XX_DPLL_LPMODE_EN_WIDTH 0x1
1002 #define OMAP54XX_DPLL_LPMODE_EN_MASK (1 << 10)
1005 * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_IVA,
1006 * CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER
1008 #define OMAP54XX_DPLL_MULT_SHIFT 8
1009 #define OMAP54XX_DPLL_MULT_WIDTH 0xb
1010 #define OMAP54XX_DPLL_MULT_MASK (0x7ff << 8)
1013 * Renamed from DPLL_MULT Used by CM_CLKSEL_DPLL_UNIPRO1,
1014 * CM_CLKSEL_DPLL_UNIPRO2, CM_CLKSEL_DPLL_USB
1016 #define OMAP54XX_DPLL_MULT_UNIPRO1_SHIFT 8
1017 #define OMAP54XX_DPLL_MULT_UNIPRO1_WIDTH 0xc
1018 #define OMAP54XX_DPLL_MULT_UNIPRO1_MASK (0xfff << 8)
1021 * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_IVA,
1022 * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER
1024 #define OMAP54XX_DPLL_REGM4XEN_SHIFT 11
1025 #define OMAP54XX_DPLL_REGM4XEN_WIDTH 0x1
1026 #define OMAP54XX_DPLL_REGM4XEN_MASK (1 << 11)
1028 /* Used by CM_CLKSEL_DPLL_UNIPRO1, CM_CLKSEL_DPLL_UNIPRO2, CM_CLKSEL_DPLL_USB */
1029 #define OMAP54XX_DPLL_SD_DIV_SHIFT 24
1030 #define OMAP54XX_DPLL_SD_DIV_WIDTH 0x8
1031 #define OMAP54XX_DPLL_SD_DIV_MASK (0xff << 24)
1033 /* Used by CM_CLKSEL_DPLL_UNIPRO1, CM_CLKSEL_DPLL_UNIPRO2, CM_CLKSEL_DPLL_USB */
1034 #define OMAP54XX_DPLL_SELFREQDCO_SHIFT 21
1035 #define OMAP54XX_DPLL_SELFREQDCO_WIDTH 0x1
1036 #define OMAP54XX_DPLL_SELFREQDCO_MASK (1 << 21)
1039 * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_IVA,
1040 * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO1,
1041 * CM_CLKMODE_DPLL_UNIPRO2, CM_CLKMODE_DPLL_USB
1043 #define OMAP54XX_DPLL_SSC_ACK_SHIFT 13
1044 #define OMAP54XX_DPLL_SSC_ACK_WIDTH 0x1
1045 #define OMAP54XX_DPLL_SSC_ACK_MASK (1 << 13)
1048 * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_IVA,
1049 * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO1,
1050 * CM_CLKMODE_DPLL_UNIPRO2, CM_CLKMODE_DPLL_USB
1052 #define OMAP54XX_DPLL_SSC_DOWNSPREAD_SHIFT 14
1053 #define OMAP54XX_DPLL_SSC_DOWNSPREAD_WIDTH 0x1
1054 #define OMAP54XX_DPLL_SSC_DOWNSPREAD_MASK (1 << 14)
1057 * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_IVA,
1058 * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO1,
1059 * CM_CLKMODE_DPLL_UNIPRO2, CM_CLKMODE_DPLL_USB
1061 #define OMAP54XX_DPLL_SSC_EN_SHIFT 12
1062 #define OMAP54XX_DPLL_SSC_EN_WIDTH 0x1
1063 #define OMAP54XX_DPLL_SSC_EN_MASK (1 << 12)
1065 /* Used by CM_L4CFG_DYNAMICDEP */
1066 #define OMAP54XX_DSP_DYNDEP_SHIFT 1
1067 #define OMAP54XX_DSP_DYNDEP_WIDTH 0x1
1068 #define OMAP54XX_DSP_DYNDEP_MASK (1 << 1)
1070 /* Used by CM_IPU_STATICDEP, CM_MPU_STATICDEP */
1071 #define OMAP54XX_DSP_STATDEP_SHIFT 1
1072 #define OMAP54XX_DSP_STATDEP_WIDTH 0x1
1073 #define OMAP54XX_DSP_STATDEP_MASK (1 << 1)
1075 /* Used by CM_L3MAIN2_DYNAMICDEP, CM_L4PER_DYNAMICDEP */
1076 #define OMAP54XX_DSS_DYNDEP_SHIFT 8
1077 #define OMAP54XX_DSS_DYNDEP_WIDTH 0x1
1078 #define OMAP54XX_DSS_DYNDEP_MASK (1 << 8)
1080 /* Used by CM_DMA_STATICDEP, CM_IPU_STATICDEP, CM_MPU_STATICDEP */
1081 #define OMAP54XX_DSS_STATDEP_SHIFT 8
1082 #define OMAP54XX_DSS_STATDEP_WIDTH 0x1
1083 #define OMAP54XX_DSS_STATDEP_MASK (1 << 8)
1086 * Used by CM_C2C_DYNAMICDEP, CM_L3MAIN1_DYNAMICDEP, CM_L4CFG_DYNAMICDEP,
1087 * CM_MIPIEXT_DYNAMICDEP, CM_MPU_DYNAMICDEP
1089 #define OMAP54XX_EMIF_DYNDEP_SHIFT 4
1090 #define OMAP54XX_EMIF_DYNDEP_WIDTH 0x1
1091 #define OMAP54XX_EMIF_DYNDEP_MASK (1 << 4)
1094 * Used by CM_C2C_STATICDEP, CM_CAM_STATICDEP, CM_DMA_STATICDEP,
1095 * CM_DSP_STATICDEP, CM_DSS_STATICDEP, CM_GPU_STATICDEP, CM_IPU_STATICDEP,
1096 * CM_IVA_STATICDEP, CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP,
1097 * CM_MIPIEXT_STATICDEP, CM_MPU_STATICDEP
1099 #define OMAP54XX_EMIF_STATDEP_SHIFT 4
1100 #define OMAP54XX_EMIF_STATDEP_WIDTH 0x1
1101 #define OMAP54XX_EMIF_STATDEP_MASK (1 << 4)
1103 /* Used by CM_SHADOW_FREQ_CONFIG1 */
1104 #define OMAP54XX_FREQ_UPDATE_SHIFT 0
1105 #define OMAP54XX_FREQ_UPDATE_WIDTH 0x1
1106 #define OMAP54XX_FREQ_UPDATE_MASK (1 << 0)
1108 /* Used by REVISION_CM_CORE, REVISION_CM_CORE_AON */
1109 #define OMAP54XX_FUNC_SHIFT 16
1110 #define OMAP54XX_FUNC_WIDTH 0xc
1111 #define OMAP54XX_FUNC_MASK (0xfff << 16)
1113 /* Used by CM_SHADOW_FREQ_CONFIG2 */
1114 #define OMAP54XX_GPMC_FREQ_UPDATE_SHIFT 0
1115 #define OMAP54XX_GPMC_FREQ_UPDATE_WIDTH 0x1
1116 #define OMAP54XX_GPMC_FREQ_UPDATE_MASK (1 << 0)
1118 /* Used by CM_L3MAIN2_DYNAMICDEP */
1119 #define OMAP54XX_GPU_DYNDEP_SHIFT 10
1120 #define OMAP54XX_GPU_DYNDEP_WIDTH 0x1
1121 #define OMAP54XX_GPU_DYNDEP_MASK (1 << 10)
1123 /* Used by CM_IPU_STATICDEP, CM_MPU_STATICDEP */
1124 #define OMAP54XX_GPU_STATDEP_SHIFT 10
1125 #define OMAP54XX_GPU_STATDEP_WIDTH 0x1
1126 #define OMAP54XX_GPU_STATDEP_MASK (1 << 10)
1129 * Used by CM_ABE_AESS_CLKCTRL, CM_ABE_DMIC_CLKCTRL, CM_ABE_L4_ABE_CLKCTRL,
1130 * CM_ABE_MCASP_CLKCTRL, CM_ABE_MCBSP1_CLKCTRL, CM_ABE_MCBSP2_CLKCTRL,
1131 * CM_ABE_MCBSP3_CLKCTRL, CM_ABE_MCPDM_CLKCTRL, CM_ABE_SLIMBUS1_CLKCTRL,
1132 * CM_ABE_TIMER5_CLKCTRL, CM_ABE_TIMER6_CLKCTRL, CM_ABE_TIMER7_CLKCTRL,
1133 * CM_ABE_TIMER8_CLKCTRL, CM_ABE_WD_TIMER3_CLKCTRL, CM_C2C_C2C_CLKCTRL,
1134 * CM_C2C_C2C_OCP_FW_CLKCTRL, CM_C2C_MODEM_ICR_CLKCTRL, CM_CAM_CAL_CLKCTRL,
1135 * CM_CAM_FDIF_CLKCTRL, CM_CAM_ISS_CLKCTRL, CM_CM_CORE_AON_PROFILING_CLKCTRL,
1136 * CM_CM_CORE_PROFILING_CLKCTRL, CM_COREAON_SMARTREFLEX_CORE_CLKCTRL,
1137 * CM_COREAON_SMARTREFLEX_MM_CLKCTRL, CM_COREAON_SMARTREFLEX_MPU_CLKCTRL,
1138 * CM_CUSTEFUSE_EFUSE_CTRL_CUST_CLKCTRL, CM_DMA_DMA_SYSTEM_CLKCTRL,
1139 * CM_DSP_DSP_CLKCTRL, CM_DSS_BB2D_CLKCTRL, CM_DSS_DSS_CLKCTRL,
1140 * CM_EMIF_DMM_CLKCTRL, CM_EMIF_EMIF1_CLKCTRL, CM_EMIF_EMIF2_CLKCTRL,
1141 * CM_EMIF_EMIF_OCP_FW_CLKCTRL, CM_EMU_DEBUGSS_CLKCTRL,
1142 * CM_EMU_MPU_EMU_DBG_CLKCTRL, CM_GPU_GPU_CLKCTRL, CM_IPU_IPU_CLKCTRL,
1143 * CM_IVA_IVA_CLKCTRL, CM_IVA_SL2_CLKCTRL, CM_L3INIT_HSI_CLKCTRL,
1144 * CM_L3INIT_IEEE1500_2_OCP_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL,
1145 * CM_L3INIT_MMC2_CLKCTRL, CM_L3INIT_MPHY_UNIPRO2_CLKCTRL,
1146 * CM_L3INIT_OCP2SCP1_CLKCTRL, CM_L3INIT_OCP2SCP3_CLKCTRL,
1147 * CM_L3INIT_SATA_CLKCTRL, CM_L3INIT_UNIPRO2_CLKCTRL,
1148 * CM_L3INIT_USB_HOST_HS_CLKCTRL, CM_L3INIT_USB_OTG_SS_CLKCTRL,
1149 * CM_L3INIT_USB_TLL_HS_CLKCTRL, CM_L3INSTR_CTRL_MODULE_BANDGAP_CLKCTRL,
1150 * CM_L3INSTR_DLL_AGING_CLKCTRL, CM_L3INSTR_L3_INSTR_CLKCTRL,
1151 * CM_L3INSTR_L3_MAIN_3_CLKCTRL, CM_L3INSTR_OCP_WP_NOC_CLKCTRL,
1152 * CM_L3MAIN1_L3_MAIN_1_CLKCTRL, CM_L3MAIN2_GPMC_CLKCTRL,
1153 * CM_L3MAIN2_L3_MAIN_2_CLKCTRL, CM_L3MAIN2_OCMC_RAM_CLKCTRL,
1154 * CM_L4CFG_L4_CFG_CLKCTRL, CM_L4CFG_MAILBOX_CLKCTRL,
1155 * CM_L4CFG_OCP2SCP2_CLKCTRL, CM_L4CFG_SAR_ROM_CLKCTRL,
1156 * CM_L4CFG_SPINLOCK_CLKCTRL, CM_L4PER_ELM_CLKCTRL, CM_L4PER_GPIO2_CLKCTRL,
1157 * CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL,
1158 * CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_GPIO7_CLKCTRL, CM_L4PER_GPIO8_CLKCTRL,
1159 * CM_L4PER_HDQ1W_CLKCTRL, CM_L4PER_I2C1_CLKCTRL, CM_L4PER_I2C2_CLKCTRL,
1160 * CM_L4PER_I2C3_CLKCTRL, CM_L4PER_I2C4_CLKCTRL, CM_L4PER_I2C5_CLKCTRL,
1161 * CM_L4PER_L4_PER_CLKCTRL, CM_L4PER_MCSPI1_CLKCTRL, CM_L4PER_MCSPI2_CLKCTRL,
1162 * CM_L4PER_MCSPI3_CLKCTRL, CM_L4PER_MCSPI4_CLKCTRL, CM_L4PER_MMC3_CLKCTRL,
1163 * CM_L4PER_MMC4_CLKCTRL, CM_L4PER_MMC5_CLKCTRL, CM_L4PER_TIMER10_CLKCTRL,
1164 * CM_L4PER_TIMER11_CLKCTRL, CM_L4PER_TIMER2_CLKCTRL, CM_L4PER_TIMER3_CLKCTRL,
1165 * CM_L4PER_TIMER4_CLKCTRL, CM_L4PER_TIMER9_CLKCTRL, CM_L4PER_UART1_CLKCTRL,
1166 * CM_L4PER_UART2_CLKCTRL, CM_L4PER_UART3_CLKCTRL, CM_L4PER_UART4_CLKCTRL,
1167 * CM_L4PER_UART5_CLKCTRL, CM_L4PER_UART6_CLKCTRL, CM_L4SEC_AES1_CLKCTRL,
1168 * CM_L4SEC_AES2_CLKCTRL, CM_L4SEC_DES3DES_CLKCTRL,
1169 * CM_L4SEC_DMA_CRYPTO_CLKCTRL, CM_L4SEC_FPKA_CLKCTRL, CM_L4SEC_RNG_CLKCTRL,
1170 * CM_L4SEC_SHA2MD5_CLKCTRL, CM_MIPIEXT_LLI_CLKCTRL,
1171 * CM_MIPIEXT_LLI_OCP_FW_CLKCTRL, CM_MIPIEXT_MPHY_CLKCTRL, CM_MPU_MPU_CLKCTRL,
1172 * CM_MPU_MPU_MPU_DBG_CLKCTRL, CM_WKUPAON_COUNTER_32K_CLKCTRL,
1173 * CM_WKUPAON_GPIO1_CLKCTRL, CM_WKUPAON_KBD_CLKCTRL,
1174 * CM_WKUPAON_L4_WKUP_CLKCTRL, CM_WKUPAON_SAR_RAM_CLKCTRL,
1175 * CM_WKUPAON_TIMER12_CLKCTRL, CM_WKUPAON_TIMER1_CLKCTRL,
1176 * CM_WKUPAON_WD_TIMER1_CLKCTRL, CM_WKUPAON_WD_TIMER2_CLKCTRL
1178 #define OMAP54XX_IDLEST_SHIFT 16
1179 #define OMAP54XX_IDLEST_WIDTH 0x2
1180 #define OMAP54XX_IDLEST_MASK (0x3 << 16)
1182 /* Used by CM_L3MAIN2_DYNAMICDEP */
1183 #define OMAP54XX_IPU_DYNDEP_SHIFT 0
1184 #define OMAP54XX_IPU_DYNDEP_WIDTH 0x1
1185 #define OMAP54XX_IPU_DYNDEP_MASK (1 << 0)
1187 /* Used by CM_DMA_STATICDEP, CM_MPU_STATICDEP */
1188 #define OMAP54XX_IPU_STATDEP_SHIFT 0
1189 #define OMAP54XX_IPU_STATDEP_WIDTH 0x1
1190 #define OMAP54XX_IPU_STATDEP_MASK (1 << 0)
1192 /* Used by CM_DSP_DYNAMICDEP, CM_L3MAIN2_DYNAMICDEP */
1193 #define OMAP54XX_IVA_DYNDEP_SHIFT 2
1194 #define OMAP54XX_IVA_DYNDEP_WIDTH 0x1
1195 #define OMAP54XX_IVA_DYNDEP_MASK (1 << 2)
1198 * Used by CM_C2C_STATICDEP, CM_CAM_STATICDEP, CM_DMA_STATICDEP,
1199 * CM_DSP_STATICDEP, CM_DSS_STATICDEP, CM_GPU_STATICDEP, CM_IPU_STATICDEP,
1200 * CM_L3INIT_STATICDEP, CM_MIPIEXT_STATICDEP, CM_MPU_STATICDEP
1202 #define OMAP54XX_IVA_STATDEP_SHIFT 2
1203 #define OMAP54XX_IVA_STATDEP_WIDTH 0x1
1204 #define OMAP54XX_IVA_STATDEP_MASK (1 << 2)
1206 /* Used by CM_L4CFG_DYNAMICDEP, CM_L4PER_DYNAMICDEP */
1207 #define OMAP54XX_L3INIT_DYNDEP_SHIFT 7
1208 #define OMAP54XX_L3INIT_DYNDEP_WIDTH 0x1
1209 #define OMAP54XX_L3INIT_DYNDEP_MASK (1 << 7)
1212 * Used by CM_C2C_STATICDEP, CM_DMA_STATICDEP, CM_DSP_STATICDEP,
1213 * CM_IPU_STATICDEP, CM_MIPIEXT_STATICDEP, CM_MPU_STATICDEP
1215 #define OMAP54XX_L3INIT_STATDEP_SHIFT 7
1216 #define OMAP54XX_L3INIT_STATDEP_WIDTH 0x1
1217 #define OMAP54XX_L3INIT_STATDEP_MASK (1 << 7)
1220 * Used by CM_DSP_DYNAMICDEP, CM_DSS_DYNAMICDEP, CM_L3INIT_DYNAMICDEP,
1221 * CM_L3MAIN2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, CM_MPU_DYNAMICDEP
1223 #define OMAP54XX_L3MAIN1_DYNDEP_SHIFT 5
1224 #define OMAP54XX_L3MAIN1_DYNDEP_WIDTH 0x1
1225 #define OMAP54XX_L3MAIN1_DYNDEP_MASK (1 << 5)
1228 * Used by CM_C2C_STATICDEP, CM_CAM_STATICDEP, CM_DMA_STATICDEP,
1229 * CM_DSP_STATICDEP, CM_DSS_STATICDEP, CM_GPU_STATICDEP, CM_IPU_STATICDEP,
1230 * CM_IVA_STATICDEP, CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP,
1231 * CM_MIPIEXT_STATICDEP, CM_MPU_STATICDEP
1233 #define OMAP54XX_L3MAIN1_STATDEP_SHIFT 5
1234 #define OMAP54XX_L3MAIN1_STATDEP_WIDTH 0x1
1235 #define OMAP54XX_L3MAIN1_STATDEP_MASK (1 << 5)
1238 * Used by CM_C2C_DYNAMICDEP, CM_CAM_DYNAMICDEP, CM_DMA_DYNAMICDEP,
1239 * CM_DSS_DYNAMICDEP, CM_EMU_DYNAMICDEP, CM_GPU_DYNAMICDEP, CM_IPU_DYNAMICDEP,
1240 * CM_IVA_DYNAMICDEP, CM_L3INIT_DYNAMICDEP, CM_L3MAIN1_DYNAMICDEP,
1241 * CM_L4CFG_DYNAMICDEP, CM_L4SEC_DYNAMICDEP, CM_MIPIEXT_DYNAMICDEP
1243 #define OMAP54XX_L3MAIN2_DYNDEP_SHIFT 6
1244 #define OMAP54XX_L3MAIN2_DYNDEP_WIDTH 0x1
1245 #define OMAP54XX_L3MAIN2_DYNDEP_MASK (1 << 6)
1248 * Used by CM_C2C_STATICDEP, CM_CAM_STATICDEP, CM_DMA_STATICDEP,
1249 * CM_DSP_STATICDEP, CM_DSS_STATICDEP, CM_GPU_STATICDEP, CM_IPU_STATICDEP,
1250 * CM_IVA_STATICDEP, CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP,
1251 * CM_MIPIEXT_STATICDEP, CM_MPU_STATICDEP
1253 #define OMAP54XX_L3MAIN2_STATDEP_SHIFT 6
1254 #define OMAP54XX_L3MAIN2_STATDEP_WIDTH 0x1
1255 #define OMAP54XX_L3MAIN2_STATDEP_MASK (1 << 6)
1257 /* Used by CM_L3MAIN1_DYNAMICDEP */
1258 #define OMAP54XX_L4CFG_DYNDEP_SHIFT 12
1259 #define OMAP54XX_L4CFG_DYNDEP_WIDTH 0x1
1260 #define OMAP54XX_L4CFG_DYNDEP_MASK (1 << 12)
1263 * Used by CM_C2C_STATICDEP, CM_DMA_STATICDEP, CM_DSP_STATICDEP,
1264 * CM_IPU_STATICDEP, CM_L3INIT_STATICDEP, CM_MIPIEXT_STATICDEP, CM_MPU_STATICDEP
1266 #define OMAP54XX_L4CFG_STATDEP_SHIFT 12
1267 #define OMAP54XX_L4CFG_STATDEP_WIDTH 0x1
1268 #define OMAP54XX_L4CFG_STATDEP_MASK (1 << 12)
1270 /* Used by CM_L3MAIN2_DYNAMICDEP */
1271 #define OMAP54XX_L4PER_DYNDEP_SHIFT 13
1272 #define OMAP54XX_L4PER_DYNDEP_WIDTH 0x1
1273 #define OMAP54XX_L4PER_DYNDEP_MASK (1 << 13)
1276 * Used by CM_C2C_STATICDEP, CM_DMA_STATICDEP, CM_DSP_STATICDEP,
1277 * CM_IPU_STATICDEP, CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP,
1278 * CM_MIPIEXT_STATICDEP, CM_MPU_STATICDEP
1280 #define OMAP54XX_L4PER_STATDEP_SHIFT 13
1281 #define OMAP54XX_L4PER_STATDEP_WIDTH 0x1
1282 #define OMAP54XX_L4PER_STATDEP_MASK (1 << 13)
1284 /* Used by CM_L3MAIN2_DYNAMICDEP, CM_L4PER_DYNAMICDEP */
1285 #define OMAP54XX_L4SEC_DYNDEP_SHIFT 14
1286 #define OMAP54XX_L4SEC_DYNDEP_WIDTH 0x1
1287 #define OMAP54XX_L4SEC_DYNDEP_MASK (1 << 14)
1290 * Used by CM_DMA_STATICDEP, CM_IPU_STATICDEP, CM_L3INIT_STATICDEP,
1293 #define OMAP54XX_L4SEC_STATDEP_SHIFT 14
1294 #define OMAP54XX_L4SEC_STATDEP_WIDTH 0x1
1295 #define OMAP54XX_L4SEC_STATDEP_MASK (1 << 14)
1297 /* Used by CM_L3MAIN2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP */
1298 #define OMAP54XX_MIPIEXT_DYNDEP_SHIFT 21
1299 #define OMAP54XX_MIPIEXT_DYNDEP_WIDTH 0x1
1300 #define OMAP54XX_MIPIEXT_DYNDEP_MASK (1 << 21)
1302 /* Used by CM_MPU_STATICDEP */
1303 #define OMAP54XX_MIPIEXT_STATDEP_SHIFT 21
1304 #define OMAP54XX_MIPIEXT_STATDEP_WIDTH 0x1
1305 #define OMAP54XX_MIPIEXT_STATDEP_MASK (1 << 21)
1308 * Used by CM_SSC_MODFREQDIV_DPLL_ABE, CM_SSC_MODFREQDIV_DPLL_CORE,
1309 * CM_SSC_MODFREQDIV_DPLL_IVA, CM_SSC_MODFREQDIV_DPLL_MPU,
1310 * CM_SSC_MODFREQDIV_DPLL_PER, CM_SSC_MODFREQDIV_DPLL_UNIPRO1,
1311 * CM_SSC_MODFREQDIV_DPLL_UNIPRO2, CM_SSC_MODFREQDIV_DPLL_USB
1313 #define OMAP54XX_MODFREQDIV_EXPONENT_SHIFT 8
1314 #define OMAP54XX_MODFREQDIV_EXPONENT_WIDTH 0x3
1315 #define OMAP54XX_MODFREQDIV_EXPONENT_MASK (0x7 << 8)
1318 * Used by CM_SSC_MODFREQDIV_DPLL_ABE, CM_SSC_MODFREQDIV_DPLL_CORE,
1319 * CM_SSC_MODFREQDIV_DPLL_IVA, CM_SSC_MODFREQDIV_DPLL_MPU,
1320 * CM_SSC_MODFREQDIV_DPLL_PER, CM_SSC_MODFREQDIV_DPLL_UNIPRO1,
1321 * CM_SSC_MODFREQDIV_DPLL_UNIPRO2, CM_SSC_MODFREQDIV_DPLL_USB
1323 #define OMAP54XX_MODFREQDIV_MANTISSA_SHIFT 0
1324 #define OMAP54XX_MODFREQDIV_MANTISSA_WIDTH 0x7
1325 #define OMAP54XX_MODFREQDIV_MANTISSA_MASK (0x7f << 0)
1328 * Used by CM_ABE_AESS_CLKCTRL, CM_ABE_DMIC_CLKCTRL, CM_ABE_L4_ABE_CLKCTRL,
1329 * CM_ABE_MCASP_CLKCTRL, CM_ABE_MCBSP1_CLKCTRL, CM_ABE_MCBSP2_CLKCTRL,
1330 * CM_ABE_MCBSP3_CLKCTRL, CM_ABE_MCPDM_CLKCTRL, CM_ABE_SLIMBUS1_CLKCTRL,
1331 * CM_ABE_TIMER5_CLKCTRL, CM_ABE_TIMER6_CLKCTRL, CM_ABE_TIMER7_CLKCTRL,
1332 * CM_ABE_TIMER8_CLKCTRL, CM_ABE_WD_TIMER3_CLKCTRL, CM_C2C_C2C_CLKCTRL,
1333 * CM_C2C_C2C_OCP_FW_CLKCTRL, CM_C2C_MODEM_ICR_CLKCTRL, CM_CAM_CAL_CLKCTRL,
1334 * CM_CAM_FDIF_CLKCTRL, CM_CAM_ISS_CLKCTRL, CM_CM_CORE_AON_PROFILING_CLKCTRL,
1335 * CM_CM_CORE_PROFILING_CLKCTRL, CM_COREAON_SMARTREFLEX_CORE_CLKCTRL,
1336 * CM_COREAON_SMARTREFLEX_MM_CLKCTRL, CM_COREAON_SMARTREFLEX_MPU_CLKCTRL,
1337 * CM_CUSTEFUSE_EFUSE_CTRL_CUST_CLKCTRL, CM_DMA_DMA_SYSTEM_CLKCTRL,
1338 * CM_DSP_DSP_CLKCTRL, CM_DSS_BB2D_CLKCTRL, CM_DSS_DSS_CLKCTRL,
1339 * CM_EMIF_DMM_CLKCTRL, CM_EMIF_EMIF1_CLKCTRL, CM_EMIF_EMIF2_CLKCTRL,
1340 * CM_EMIF_EMIF_OCP_FW_CLKCTRL, CM_EMU_DEBUGSS_CLKCTRL,
1341 * CM_EMU_MPU_EMU_DBG_CLKCTRL, CM_GPU_GPU_CLKCTRL, CM_IPU_IPU_CLKCTRL,
1342 * CM_IVA_IVA_CLKCTRL, CM_IVA_SL2_CLKCTRL, CM_L3INIT_HSI_CLKCTRL,
1343 * CM_L3INIT_IEEE1500_2_OCP_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL,
1344 * CM_L3INIT_MMC2_CLKCTRL, CM_L3INIT_MPHY_UNIPRO2_CLKCTRL,
1345 * CM_L3INIT_OCP2SCP1_CLKCTRL, CM_L3INIT_OCP2SCP3_CLKCTRL,
1346 * CM_L3INIT_SATA_CLKCTRL, CM_L3INIT_UNIPRO2_CLKCTRL,
1347 * CM_L3INIT_USB_HOST_HS_CLKCTRL, CM_L3INIT_USB_OTG_SS_CLKCTRL,
1348 * CM_L3INIT_USB_TLL_HS_CLKCTRL, CM_L3INSTR_CTRL_MODULE_BANDGAP_CLKCTRL,
1349 * CM_L3INSTR_DLL_AGING_CLKCTRL, CM_L3INSTR_L3_INSTR_CLKCTRL,
1350 * CM_L3INSTR_L3_MAIN_3_CLKCTRL, CM_L3INSTR_OCP_WP_NOC_CLKCTRL,
1351 * CM_L3MAIN1_L3_MAIN_1_CLKCTRL, CM_L3MAIN2_GPMC_CLKCTRL,
1352 * CM_L3MAIN2_L3_MAIN_2_CLKCTRL, CM_L3MAIN2_OCMC_RAM_CLKCTRL,
1353 * CM_L4CFG_L4_CFG_CLKCTRL, CM_L4CFG_MAILBOX_CLKCTRL,
1354 * CM_L4CFG_OCP2SCP2_CLKCTRL, CM_L4CFG_SAR_ROM_CLKCTRL,
1355 * CM_L4CFG_SPINLOCK_CLKCTRL, CM_L4PER_ELM_CLKCTRL, CM_L4PER_GPIO2_CLKCTRL,
1356 * CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL,
1357 * CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_GPIO7_CLKCTRL, CM_L4PER_GPIO8_CLKCTRL,
1358 * CM_L4PER_HDQ1W_CLKCTRL, CM_L4PER_I2C1_CLKCTRL, CM_L4PER_I2C2_CLKCTRL,
1359 * CM_L4PER_I2C3_CLKCTRL, CM_L4PER_I2C4_CLKCTRL, CM_L4PER_I2C5_CLKCTRL,
1360 * CM_L4PER_L4_PER_CLKCTRL, CM_L4PER_MCSPI1_CLKCTRL, CM_L4PER_MCSPI2_CLKCTRL,
1361 * CM_L4PER_MCSPI3_CLKCTRL, CM_L4PER_MCSPI4_CLKCTRL, CM_L4PER_MMC3_CLKCTRL,
1362 * CM_L4PER_MMC4_CLKCTRL, CM_L4PER_MMC5_CLKCTRL, CM_L4PER_TIMER10_CLKCTRL,
1363 * CM_L4PER_TIMER11_CLKCTRL, CM_L4PER_TIMER2_CLKCTRL, CM_L4PER_TIMER3_CLKCTRL,
1364 * CM_L4PER_TIMER4_CLKCTRL, CM_L4PER_TIMER9_CLKCTRL, CM_L4PER_UART1_CLKCTRL,
1365 * CM_L4PER_UART2_CLKCTRL, CM_L4PER_UART3_CLKCTRL, CM_L4PER_UART4_CLKCTRL,
1366 * CM_L4PER_UART5_CLKCTRL, CM_L4PER_UART6_CLKCTRL, CM_L4SEC_AES1_CLKCTRL,
1367 * CM_L4SEC_AES2_CLKCTRL, CM_L4SEC_DES3DES_CLKCTRL,
1368 * CM_L4SEC_DMA_CRYPTO_CLKCTRL, CM_L4SEC_FPKA_CLKCTRL, CM_L4SEC_RNG_CLKCTRL,
1369 * CM_L4SEC_SHA2MD5_CLKCTRL, CM_MIPIEXT_LLI_CLKCTRL,
1370 * CM_MIPIEXT_LLI_OCP_FW_CLKCTRL, CM_MIPIEXT_MPHY_CLKCTRL, CM_MPU_MPU_CLKCTRL,
1371 * CM_MPU_MPU_MPU_DBG_CLKCTRL, CM_WKUPAON_COUNTER_32K_CLKCTRL,
1372 * CM_WKUPAON_GPIO1_CLKCTRL, CM_WKUPAON_KBD_CLKCTRL,
1373 * CM_WKUPAON_L4_WKUP_CLKCTRL, CM_WKUPAON_SAR_RAM_CLKCTRL,
1374 * CM_WKUPAON_TIMER12_CLKCTRL, CM_WKUPAON_TIMER1_CLKCTRL,
1375 * CM_WKUPAON_WD_TIMER1_CLKCTRL, CM_WKUPAON_WD_TIMER2_CLKCTRL
1377 #define OMAP54XX_MODULEMODE_SHIFT 0
1378 #define OMAP54XX_MODULEMODE_WIDTH 0x2
1379 #define OMAP54XX_MODULEMODE_MASK (0x3 << 0)
1381 /* Used by CM_L4CFG_DYNAMICDEP */
1382 #define OMAP54XX_MPU_DYNDEP_SHIFT 19
1383 #define OMAP54XX_MPU_DYNDEP_WIDTH 0x1
1384 #define OMAP54XX_MPU_DYNDEP_MASK (1 << 19)
1386 /* Used by CM_DSS_DSS_CLKCTRL */
1387 #define OMAP54XX_OPTFCLKEN_32KHZ_CLK_SHIFT 11
1388 #define OMAP54XX_OPTFCLKEN_32KHZ_CLK_WIDTH 0x1
1389 #define OMAP54XX_OPTFCLKEN_32KHZ_CLK_MASK (1 << 11)
1391 /* Renamed from OPTFCLKEN_32KHZ_CLK Used by CM_L3INIT_MMC1_CLKCTRL */
1392 #define OMAP54XX_OPTFCLKEN_32KHZ_CLK_8_8_SHIFT 8
1393 #define OMAP54XX_OPTFCLKEN_32KHZ_CLK_8_8_WIDTH 0x1
1394 #define OMAP54XX_OPTFCLKEN_32KHZ_CLK_8_8_MASK (1 << 8)
1396 /* Used by CM_DSS_DSS_CLKCTRL */
1397 #define OMAP54XX_OPTFCLKEN_48MHZ_CLK_SHIFT 9
1398 #define OMAP54XX_OPTFCLKEN_48MHZ_CLK_WIDTH 0x1
1399 #define OMAP54XX_OPTFCLKEN_48MHZ_CLK_MASK (1 << 9)
1401 /* Used by CM_COREAON_USB_PHY_CORE_CLKCTRL */
1402 #define OMAP54XX_OPTFCLKEN_CLK32K_SHIFT 8
1403 #define OMAP54XX_OPTFCLKEN_CLK32K_WIDTH 0x1
1404 #define OMAP54XX_OPTFCLKEN_CLK32K_MASK (1 << 8)
1406 /* Used by CM_CAM_ISS_CLKCTRL */
1407 #define OMAP54XX_OPTFCLKEN_CTRLCLK_SHIFT 8
1408 #define OMAP54XX_OPTFCLKEN_CTRLCLK_WIDTH 0x1
1409 #define OMAP54XX_OPTFCLKEN_CTRLCLK_MASK (1 << 8)
1412 * Used by CM_L4PER_GPIO2_CLKCTRL, CM_L4PER_GPIO3_CLKCTRL,
1413 * CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL, CM_L4PER_GPIO6_CLKCTRL,
1414 * CM_L4PER_GPIO7_CLKCTRL, CM_L4PER_GPIO8_CLKCTRL, CM_WKUPAON_GPIO1_CLKCTRL
1416 #define OMAP54XX_OPTFCLKEN_DBCLK_SHIFT 8
1417 #define OMAP54XX_OPTFCLKEN_DBCLK_WIDTH 0x1
1418 #define OMAP54XX_OPTFCLKEN_DBCLK_MASK (1 << 8)
1420 /* Used by CM_EMIF_EMIF_DLL_CLKCTRL */
1421 #define OMAP54XX_OPTFCLKEN_DLL_CLK_SHIFT 8
1422 #define OMAP54XX_OPTFCLKEN_DLL_CLK_WIDTH 0x1
1423 #define OMAP54XX_OPTFCLKEN_DLL_CLK_MASK (1 << 8)
1425 /* Used by CM_DSS_DSS_CLKCTRL */
1426 #define OMAP54XX_OPTFCLKEN_DSSCLK_SHIFT 8
1427 #define OMAP54XX_OPTFCLKEN_DSSCLK_WIDTH 0x1
1428 #define OMAP54XX_OPTFCLKEN_DSSCLK_MASK (1 << 8)
1430 /* Used by CM_ABE_SLIMBUS1_CLKCTRL */
1431 #define OMAP54XX_OPTFCLKEN_FCLK0_SHIFT 8
1432 #define OMAP54XX_OPTFCLKEN_FCLK0_WIDTH 0x1
1433 #define OMAP54XX_OPTFCLKEN_FCLK0_MASK (1 << 8)
1435 /* Used by CM_ABE_SLIMBUS1_CLKCTRL */
1436 #define OMAP54XX_OPTFCLKEN_FCLK1_SHIFT 9
1437 #define OMAP54XX_OPTFCLKEN_FCLK1_WIDTH 0x1
1438 #define OMAP54XX_OPTFCLKEN_FCLK1_MASK (1 << 9)
1440 /* Used by CM_ABE_SLIMBUS1_CLKCTRL */
1441 #define OMAP54XX_OPTFCLKEN_FCLK2_SHIFT 10
1442 #define OMAP54XX_OPTFCLKEN_FCLK2_WIDTH 0x1
1443 #define OMAP54XX_OPTFCLKEN_FCLK2_MASK (1 << 10)
1445 /* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */
1446 #define OMAP54XX_OPTFCLKEN_FUNC48M_CLK_SHIFT 15
1447 #define OMAP54XX_OPTFCLKEN_FUNC48M_CLK_WIDTH 0x1
1448 #define OMAP54XX_OPTFCLKEN_FUNC48M_CLK_MASK (1 << 15)
1450 /* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */
1451 #define OMAP54XX_OPTFCLKEN_HSIC480M_P1_CLK_SHIFT 13
1452 #define OMAP54XX_OPTFCLKEN_HSIC480M_P1_CLK_WIDTH 0x1
1453 #define OMAP54XX_OPTFCLKEN_HSIC480M_P1_CLK_MASK (1 << 13)
1455 /* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */
1456 #define OMAP54XX_OPTFCLKEN_HSIC480M_P2_CLK_SHIFT 14
1457 #define OMAP54XX_OPTFCLKEN_HSIC480M_P2_CLK_WIDTH 0x1
1458 #define OMAP54XX_OPTFCLKEN_HSIC480M_P2_CLK_MASK (1 << 14)
1460 /* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */
1461 #define OMAP54XX_OPTFCLKEN_HSIC480M_P3_CLK_SHIFT 7
1462 #define OMAP54XX_OPTFCLKEN_HSIC480M_P3_CLK_WIDTH 0x1
1463 #define OMAP54XX_OPTFCLKEN_HSIC480M_P3_CLK_MASK (1 << 7)
1465 /* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */
1466 #define OMAP54XX_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT 11
1467 #define OMAP54XX_OPTFCLKEN_HSIC60M_P1_CLK_WIDTH 0x1
1468 #define OMAP54XX_OPTFCLKEN_HSIC60M_P1_CLK_MASK (1 << 11)
1470 /* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */
1471 #define OMAP54XX_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT 12
1472 #define OMAP54XX_OPTFCLKEN_HSIC60M_P2_CLK_WIDTH 0x1
1473 #define OMAP54XX_OPTFCLKEN_HSIC60M_P2_CLK_MASK (1 << 12)
1475 /* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */
1476 #define OMAP54XX_OPTFCLKEN_HSIC60M_P3_CLK_SHIFT 6
1477 #define OMAP54XX_OPTFCLKEN_HSIC60M_P3_CLK_WIDTH 0x1
1478 #define OMAP54XX_OPTFCLKEN_HSIC60M_P3_CLK_MASK (1 << 6)
1480 /* Used by CM_L3INIT_USB_OTG_SS_CLKCTRL */
1481 #define OMAP54XX_OPTFCLKEN_REFCLK960M_SHIFT 8
1482 #define OMAP54XX_OPTFCLKEN_REFCLK960M_WIDTH 0x1
1483 #define OMAP54XX_OPTFCLKEN_REFCLK960M_MASK (1 << 8)
1485 /* Used by CM_L3INIT_SATA_CLKCTRL */
1486 #define OMAP54XX_OPTFCLKEN_REF_CLK_SHIFT 8
1487 #define OMAP54XX_OPTFCLKEN_REF_CLK_WIDTH 0x1
1488 #define OMAP54XX_OPTFCLKEN_REF_CLK_MASK (1 << 8)
1490 /* Used by CM_WKUPAON_SCRM_CLKCTRL */
1491 #define OMAP54XX_OPTFCLKEN_SCRM_CORE_SHIFT 8
1492 #define OMAP54XX_OPTFCLKEN_SCRM_CORE_WIDTH 0x1
1493 #define OMAP54XX_OPTFCLKEN_SCRM_CORE_MASK (1 << 8)
1495 /* Used by CM_WKUPAON_SCRM_CLKCTRL */
1496 #define OMAP54XX_OPTFCLKEN_SCRM_PER_SHIFT 9
1497 #define OMAP54XX_OPTFCLKEN_SCRM_PER_WIDTH 0x1
1498 #define OMAP54XX_OPTFCLKEN_SCRM_PER_MASK (1 << 9)
1500 /* Used by CM_ABE_SLIMBUS1_CLKCTRL */
1501 #define OMAP54XX_OPTFCLKEN_SLIMBUS_CLK_SHIFT 11
1502 #define OMAP54XX_OPTFCLKEN_SLIMBUS_CLK_WIDTH 0x1
1503 #define OMAP54XX_OPTFCLKEN_SLIMBUS_CLK_MASK (1 << 11)
1505 /* Used by CM_DSS_DSS_CLKCTRL */
1506 #define OMAP54XX_OPTFCLKEN_SYS_CLK_SHIFT 10
1507 #define OMAP54XX_OPTFCLKEN_SYS_CLK_WIDTH 0x1
1508 #define OMAP54XX_OPTFCLKEN_SYS_CLK_MASK (1 << 10)
1510 /* Used by CM_MIPIEXT_LLI_CLKCTRL */
1511 #define OMAP54XX_OPTFCLKEN_TXPHY_CLK_SHIFT 8
1512 #define OMAP54XX_OPTFCLKEN_TXPHY_CLK_WIDTH 0x1
1513 #define OMAP54XX_OPTFCLKEN_TXPHY_CLK_MASK (1 << 8)
1515 /* Used by CM_MIPIEXT_LLI_CLKCTRL */
1516 #define OMAP54XX_OPTFCLKEN_TXPHY_LS_CLK_SHIFT 9
1517 #define OMAP54XX_OPTFCLKEN_TXPHY_LS_CLK_WIDTH 0x1
1518 #define OMAP54XX_OPTFCLKEN_TXPHY_LS_CLK_MASK (1 << 9)
1520 /* Used by CM_L3INIT_USB_TLL_HS_CLKCTRL */
1521 #define OMAP54XX_OPTFCLKEN_USB_CH0_CLK_SHIFT 8
1522 #define OMAP54XX_OPTFCLKEN_USB_CH0_CLK_WIDTH 0x1
1523 #define OMAP54XX_OPTFCLKEN_USB_CH0_CLK_MASK (1 << 8)
1525 /* Used by CM_L3INIT_USB_TLL_HS_CLKCTRL */
1526 #define OMAP54XX_OPTFCLKEN_USB_CH1_CLK_SHIFT 9
1527 #define OMAP54XX_OPTFCLKEN_USB_CH1_CLK_WIDTH 0x1
1528 #define OMAP54XX_OPTFCLKEN_USB_CH1_CLK_MASK (1 << 9)
1530 /* Used by CM_L3INIT_USB_TLL_HS_CLKCTRL */
1531 #define OMAP54XX_OPTFCLKEN_USB_CH2_CLK_SHIFT 10
1532 #define OMAP54XX_OPTFCLKEN_USB_CH2_CLK_WIDTH 0x1
1533 #define OMAP54XX_OPTFCLKEN_USB_CH2_CLK_MASK (1 << 10)
1535 /* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */
1536 #define OMAP54XX_OPTFCLKEN_UTMI_P1_CLK_SHIFT 8
1537 #define OMAP54XX_OPTFCLKEN_UTMI_P1_CLK_WIDTH 0x1
1538 #define OMAP54XX_OPTFCLKEN_UTMI_P1_CLK_MASK (1 << 8)
1540 /* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */
1541 #define OMAP54XX_OPTFCLKEN_UTMI_P2_CLK_SHIFT 9
1542 #define OMAP54XX_OPTFCLKEN_UTMI_P2_CLK_WIDTH 0x1
1543 #define OMAP54XX_OPTFCLKEN_UTMI_P2_CLK_MASK (1 << 9)
1545 /* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */
1546 #define OMAP54XX_OPTFCLKEN_UTMI_P3_CLK_SHIFT 10
1547 #define OMAP54XX_OPTFCLKEN_UTMI_P3_CLK_WIDTH 0x1
1548 #define OMAP54XX_OPTFCLKEN_UTMI_P3_CLK_MASK (1 << 10)
1550 /* Used by CM_CORE_AON_DEBUG_OUT, CM_CORE_DEBUG_OUT */
1551 #define OMAP54XX_OUTPUT_SHIFT 0
1552 #define OMAP54XX_OUTPUT_WIDTH 0x20
1553 #define OMAP54XX_OUTPUT_MASK (0xffffffff << 0)
1555 /* Used by CM_CLKSEL_ABE */
1556 #define OMAP54XX_PAD_CLKS_GATE_SHIFT 8
1557 #define OMAP54XX_PAD_CLKS_GATE_WIDTH 0x1
1558 #define OMAP54XX_PAD_CLKS_GATE_MASK (1 << 8)
1560 /* Used by CM_RESTORE_ST */
1561 #define OMAP54XX_PHASE1_COMPLETED_SHIFT 0
1562 #define OMAP54XX_PHASE1_COMPLETED_WIDTH 0x1
1563 #define OMAP54XX_PHASE1_COMPLETED_MASK (1 << 0)
1565 /* Used by CM_RESTORE_ST */
1566 #define OMAP54XX_PHASE2A_COMPLETED_SHIFT 1
1567 #define OMAP54XX_PHASE2A_COMPLETED_WIDTH 0x1
1568 #define OMAP54XX_PHASE2A_COMPLETED_MASK (1 << 1)
1570 /* Used by CM_RESTORE_ST */
1571 #define OMAP54XX_PHASE2B_COMPLETED_SHIFT 2
1572 #define OMAP54XX_PHASE2B_COMPLETED_WIDTH 0x1
1573 #define OMAP54XX_PHASE2B_COMPLETED_MASK (1 << 2)
1575 /* Used by CM_DYN_DEP_PRESCAL */
1576 #define OMAP54XX_PRESCAL_SHIFT 0
1577 #define OMAP54XX_PRESCAL_WIDTH 0x6
1578 #define OMAP54XX_PRESCAL_MASK (0x3f << 0)
1580 /* Used by REVISION_CM_CORE, REVISION_CM_CORE_AON */
1581 #define OMAP54XX_R_RTL_SHIFT 11
1582 #define OMAP54XX_R_RTL_WIDTH 0x5
1583 #define OMAP54XX_R_RTL_MASK (0x1f << 11)
1585 /* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL, CM_L3INIT_USB_TLL_HS_CLKCTRL */
1586 #define OMAP54XX_SAR_MODE_SHIFT 4
1587 #define OMAP54XX_SAR_MODE_WIDTH 0x1
1588 #define OMAP54XX_SAR_MODE_MASK (1 << 4)
1590 /* Used by REVISION_CM_CORE, REVISION_CM_CORE_AON */
1591 #define OMAP54XX_SCHEME_SHIFT 30
1592 #define OMAP54XX_SCHEME_WIDTH 0x2
1593 #define OMAP54XX_SCHEME_MASK (0x3 << 30)
1595 /* Used by CM_L4CFG_DYNAMICDEP */
1596 #define OMAP54XX_SDMA_DYNDEP_SHIFT 11
1597 #define OMAP54XX_SDMA_DYNDEP_WIDTH 0x1
1598 #define OMAP54XX_SDMA_DYNDEP_MASK (1 << 11)
1600 /* Used by CM_IPU_STATICDEP, CM_MPU_STATICDEP */
1601 #define OMAP54XX_SDMA_STATDEP_SHIFT 11
1602 #define OMAP54XX_SDMA_STATDEP_WIDTH 0x1
1603 #define OMAP54XX_SDMA_STATDEP_MASK (1 << 11)
1605 /* Used by CM_CORE_AON_DEBUG_CFG */
1606 #define OMAP54XX_SEL0_SHIFT 0
1607 #define OMAP54XX_SEL0_WIDTH 0x7
1608 #define OMAP54XX_SEL0_MASK (0x7f << 0)
1610 /* Renamed from SEL0 Used by CM_CORE_DEBUG_CFG */
1611 #define OMAP54XX_SEL0_0_7_SHIFT 0
1612 #define OMAP54XX_SEL0_0_7_WIDTH 0x8
1613 #define OMAP54XX_SEL0_0_7_MASK (0xff << 0)
1615 /* Used by CM_CORE_AON_DEBUG_CFG */
1616 #define OMAP54XX_SEL1_SHIFT 8
1617 #define OMAP54XX_SEL1_WIDTH 0x7
1618 #define OMAP54XX_SEL1_MASK (0x7f << 8)
1620 /* Renamed from SEL1 Used by CM_CORE_DEBUG_CFG */
1621 #define OMAP54XX_SEL1_CORE_DEBUG_CFG_SHIFT 8
1622 #define OMAP54XX_SEL1_CORE_DEBUG_CFG_WIDTH 0x8
1623 #define OMAP54XX_SEL1_CORE_DEBUG_CFG_MASK (0xff << 8)
1625 /* Used by CM_CORE_AON_DEBUG_CFG */
1626 #define OMAP54XX_SEL2_SHIFT 16
1627 #define OMAP54XX_SEL2_WIDTH 0x7
1628 #define OMAP54XX_SEL2_MASK (0x7f << 16)
1630 /* Renamed from SEL2 Used by CM_CORE_DEBUG_CFG */
1631 #define OMAP54XX_SEL2_CORE_DEBUG_CFG_SHIFT 16
1632 #define OMAP54XX_SEL2_CORE_DEBUG_CFG_WIDTH 0x8
1633 #define OMAP54XX_SEL2_CORE_DEBUG_CFG_MASK (0xff << 16)
1635 /* Used by CM_CORE_AON_DEBUG_CFG */
1636 #define OMAP54XX_SEL3_SHIFT 24
1637 #define OMAP54XX_SEL3_WIDTH 0x7
1638 #define OMAP54XX_SEL3_MASK (0x7f << 24)
1640 /* Renamed from SEL3 Used by CM_CORE_DEBUG_CFG */
1641 #define OMAP54XX_SEL3_CORE_DEBUG_CFG_SHIFT 24
1642 #define OMAP54XX_SEL3_CORE_DEBUG_CFG_WIDTH 0x8
1643 #define OMAP54XX_SEL3_CORE_DEBUG_CFG_MASK (0xff << 24)
1645 /* Used by CM_CLKSEL_ABE */
1646 #define OMAP54XX_SLIMBUS1_CLK_GATE_SHIFT 10
1647 #define OMAP54XX_SLIMBUS1_CLK_GATE_WIDTH 0x1
1648 #define OMAP54XX_SLIMBUS1_CLK_GATE_MASK (1 << 10)
1651 * Used by CM_ABE_AESS_CLKCTRL, CM_C2C_C2C_CLKCTRL, CM_CAM_FDIF_CLKCTRL,
1652 * CM_CAM_ISS_CLKCTRL, CM_DMA_DMA_SYSTEM_CLKCTRL, CM_DSP_DSP_CLKCTRL,
1653 * CM_DSS_BB2D_CLKCTRL, CM_DSS_DSS_CLKCTRL, CM_EMU_DEBUGSS_CLKCTRL,
1654 * CM_GPU_GPU_CLKCTRL, CM_IPU_IPU_CLKCTRL, CM_IVA_IVA_CLKCTRL,
1655 * CM_L3INIT_HSI_CLKCTRL, CM_L3INIT_IEEE1500_2_OCP_CLKCTRL,
1656 * CM_L3INIT_MMC1_CLKCTRL, CM_L3INIT_MMC2_CLKCTRL, CM_L3INIT_SATA_CLKCTRL,
1657 * CM_L3INIT_UNIPRO2_CLKCTRL, CM_L3INIT_USB_HOST_HS_CLKCTRL,
1658 * CM_L3INIT_USB_OTG_SS_CLKCTRL, CM_L4SEC_DMA_CRYPTO_CLKCTRL,
1659 * CM_MIPIEXT_LLI_CLKCTRL, CM_MPU_MPU_CLKCTRL
1661 #define OMAP54XX_STBYST_SHIFT 18
1662 #define OMAP54XX_STBYST_WIDTH 0x1
1663 #define OMAP54XX_STBYST_MASK (1 << 18)
1666 * Used by CM_IDLEST_DPLL_ABE, CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_IVA,
1667 * CM_IDLEST_DPLL_MPU, CM_IDLEST_DPLL_PER, CM_IDLEST_DPLL_UNIPRO1,
1668 * CM_IDLEST_DPLL_UNIPRO2, CM_IDLEST_DPLL_USB
1670 #define OMAP54XX_ST_DPLL_CLK_SHIFT 0
1671 #define OMAP54XX_ST_DPLL_CLK_WIDTH 0x1
1672 #define OMAP54XX_ST_DPLL_CLK_MASK (1 << 0)
1675 * Used by CM_CLKDCOLDO_DPLL_UNIPRO1, CM_CLKDCOLDO_DPLL_UNIPRO2,
1676 * CM_CLKDCOLDO_DPLL_USB
1678 #define OMAP54XX_ST_DPLL_CLKDCOLDO_SHIFT 9
1679 #define OMAP54XX_ST_DPLL_CLKDCOLDO_WIDTH 0x1
1680 #define OMAP54XX_ST_DPLL_CLKDCOLDO_MASK (1 << 9)
1683 * Used by CM_IDLEST_DPLL_ABE, CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_IVA,
1684 * CM_IDLEST_DPLL_MPU, CM_IDLEST_DPLL_PER, CM_IDLEST_DPLL_UNIPRO1,
1685 * CM_IDLEST_DPLL_UNIPRO2, CM_IDLEST_DPLL_USB
1687 #define OMAP54XX_ST_DPLL_INIT_SHIFT 4
1688 #define OMAP54XX_ST_DPLL_INIT_WIDTH 0x1
1689 #define OMAP54XX_ST_DPLL_INIT_MASK (1 << 4)
1692 * Used by CM_IDLEST_DPLL_ABE, CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_IVA,
1693 * CM_IDLEST_DPLL_MPU, CM_IDLEST_DPLL_PER, CM_IDLEST_DPLL_UNIPRO1,
1694 * CM_IDLEST_DPLL_UNIPRO2, CM_IDLEST_DPLL_USB
1696 #define OMAP54XX_ST_DPLL_MODE_SHIFT 1
1697 #define OMAP54XX_ST_DPLL_MODE_WIDTH 0x3
1698 #define OMAP54XX_ST_DPLL_MODE_MASK (0x7 << 1)
1700 /* Used by CM_CLKSEL_SYS */
1701 #define OMAP54XX_SYS_CLKSEL_SHIFT 0
1702 #define OMAP54XX_SYS_CLKSEL_WIDTH 0x3
1703 #define OMAP54XX_SYS_CLKSEL_MASK (0x7 << 0)
1706 * Used by CM_C2C_DYNAMICDEP, CM_DSP_DYNAMICDEP, CM_EMU_DYNAMICDEP,
1707 * CM_IPU_DYNAMICDEP, CM_L3MAIN1_DYNAMICDEP, CM_L3MAIN2_DYNAMICDEP,
1708 * CM_L4CFG_DYNAMICDEP, CM_L4PER_DYNAMICDEP, CM_MIPIEXT_DYNAMICDEP,
1711 #define OMAP54XX_WINDOWSIZE_SHIFT 24
1712 #define OMAP54XX_WINDOWSIZE_WIDTH 0x4
1713 #define OMAP54XX_WINDOWSIZE_MASK (0xf << 24)
1715 /* Used by CM_L3MAIN1_DYNAMICDEP */
1716 #define OMAP54XX_WKUPAON_DYNDEP_SHIFT 15
1717 #define OMAP54XX_WKUPAON_DYNDEP_WIDTH 0x1
1718 #define OMAP54XX_WKUPAON_DYNDEP_MASK (1 << 15)
1721 * Used by CM_DMA_STATICDEP, CM_DSP_STATICDEP, CM_IPU_STATICDEP,
1722 * CM_L3INIT_STATICDEP, CM_MPU_STATICDEP
1724 #define OMAP54XX_WKUPAON_STATDEP_SHIFT 15
1725 #define OMAP54XX_WKUPAON_STATDEP_WIDTH 0x1
1726 #define OMAP54XX_WKUPAON_STATDEP_MASK (1 << 15)
1728 /* Used by REVISION_CM_CORE, REVISION_CM_CORE_AON */
1729 #define OMAP54XX_X_MAJOR_SHIFT 8
1730 #define OMAP54XX_X_MAJOR_WIDTH 0x3
1731 #define OMAP54XX_X_MAJOR_MASK (0x7 << 8)
1733 /* Used by REVISION_CM_CORE, REVISION_CM_CORE_AON */
1734 #define OMAP54XX_Y_MINOR_SHIFT 0
1735 #define OMAP54XX_Y_MINOR_WIDTH 0x6
1736 #define OMAP54XX_Y_MINOR_MASK (0x3f << 0)