2 * Contains CPU feature definitions
4 * Copyright (C) 2015 ARM Ltd.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program. If not, see <http://www.gnu.org/licenses/>.
19 #define pr_fmt(fmt) "CPU features: " fmt
21 #include <linux/bsearch.h>
22 #include <linux/sort.h>
23 #include <linux/types.h>
25 #include <asm/cpufeature.h>
26 #include <asm/cpu_ops.h>
27 #include <asm/mmu_context.h>
28 #include <asm/processor.h>
29 #include <asm/sysreg.h>
31 unsigned long elf_hwcap __read_mostly;
32 EXPORT_SYMBOL_GPL(elf_hwcap);
35 #define COMPAT_ELF_HWCAP_DEFAULT \
36 (COMPAT_HWCAP_HALF|COMPAT_HWCAP_THUMB|\
37 COMPAT_HWCAP_FAST_MULT|COMPAT_HWCAP_EDSP|\
38 COMPAT_HWCAP_TLS|COMPAT_HWCAP_VFP|\
39 COMPAT_HWCAP_VFPv3|COMPAT_HWCAP_VFPv4|\
40 COMPAT_HWCAP_NEON|COMPAT_HWCAP_IDIV|\
42 unsigned int compat_elf_hwcap __read_mostly = COMPAT_ELF_HWCAP_DEFAULT;
43 unsigned int compat_elf_hwcap2 __read_mostly;
46 DECLARE_BITMAP(cpu_hwcaps, ARM64_NCAPS);
48 #define __ARM64_FTR_BITS(SIGNED, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
55 .safe_val = SAFE_VAL, \
58 /* Define a feature with unsigned values */
59 #define ARM64_FTR_BITS(STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
60 __ARM64_FTR_BITS(FTR_UNSIGNED, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL)
62 /* Define a feature with a signed value */
63 #define S_ARM64_FTR_BITS(STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
64 __ARM64_FTR_BITS(FTR_SIGNED, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL)
66 #define ARM64_FTR_END \
71 /* meta feature for alternatives */
72 static bool __maybe_unused
73 cpufeature_pan_not_uao(const struct arm64_cpu_capabilities *entry);
75 static struct arm64_ftr_bits ftr_id_aa64isar0[] = {
76 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 32, 32, 0),
77 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64ISAR0_RDM_SHIFT, 4, 0),
78 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 24, 4, 0),
79 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_ATOMICS_SHIFT, 4, 0),
80 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_CRC32_SHIFT, 4, 0),
81 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA2_SHIFT, 4, 0),
82 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA1_SHIFT, 4, 0),
83 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_AES_SHIFT, 4, 0),
84 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 4, 0), /* RAZ */
88 static struct arm64_ftr_bits ftr_id_aa64pfr0[] = {
89 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 32, 32, 0),
90 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 28, 4, 0),
91 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64PFR0_GIC_SHIFT, 4, 0),
92 S_ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_ASIMD_SHIFT, 4, ID_AA64PFR0_ASIMD_NI),
93 S_ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_FP_SHIFT, 4, ID_AA64PFR0_FP_NI),
94 /* Linux doesn't care about the EL3 */
95 ARM64_FTR_BITS(FTR_NONSTRICT, FTR_EXACT, ID_AA64PFR0_EL3_SHIFT, 4, 0),
96 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64PFR0_EL2_SHIFT, 4, 0),
97 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64PFR0_EL1_SHIFT, 4, ID_AA64PFR0_EL1_64BIT_ONLY),
98 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64PFR0_EL0_SHIFT, 4, ID_AA64PFR0_EL0_64BIT_ONLY),
102 static struct arm64_ftr_bits ftr_id_aa64mmfr0[] = {
103 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 32, 32, 0),
104 S_ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN4_SHIFT, 4, ID_AA64MMFR0_TGRAN4_NI),
105 S_ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN64_SHIFT, 4, ID_AA64MMFR0_TGRAN64_NI),
106 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN16_SHIFT, 4, ID_AA64MMFR0_TGRAN16_NI),
107 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_BIGENDEL0_SHIFT, 4, 0),
108 /* Linux shouldn't care about secure memory */
109 ARM64_FTR_BITS(FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_SNSMEM_SHIFT, 4, 0),
110 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_BIGENDEL_SHIFT, 4, 0),
111 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_ASID_SHIFT, 4, 0),
113 * Differing PARange is fine as long as all peripherals and memory are mapped
114 * within the minimum PARange of all CPUs
116 ARM64_FTR_BITS(FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_PARANGE_SHIFT, 4, 0),
120 static struct arm64_ftr_bits ftr_id_aa64mmfr1[] = {
121 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 32, 32, 0),
122 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_PAN_SHIFT, 4, 0),
123 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR1_LOR_SHIFT, 4, 0),
124 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR1_HPD_SHIFT, 4, 0),
125 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR1_VHE_SHIFT, 4, 0),
126 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR1_VMIDBITS_SHIFT, 4, 0),
127 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR1_HADBS_SHIFT, 4, 0),
131 static struct arm64_ftr_bits ftr_id_aa64mmfr2[] = {
132 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR2_UAO_SHIFT, 4, 0),
136 static struct arm64_ftr_bits ftr_ctr[] = {
137 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 31, 1, 1), /* RAO */
138 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 28, 3, 0),
139 ARM64_FTR_BITS(FTR_STRICT, FTR_HIGHER_SAFE, 24, 4, 0), /* CWG */
140 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0), /* ERG */
141 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 1), /* DminLine */
143 * Linux can handle differing I-cache policies. Userspace JITs will
144 * make use of *minLine
146 ARM64_FTR_BITS(FTR_NONSTRICT, FTR_EXACT, 14, 2, 0), /* L1Ip */
147 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 4, 10, 0), /* RAZ */
148 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), /* IminLine */
152 static struct arm64_ftr_bits ftr_id_mmfr0[] = {
153 S_ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 28, 4, 0xf), /* InnerShr */
154 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 24, 4, 0), /* FCSE */
155 ARM64_FTR_BITS(FTR_NONSTRICT, FTR_LOWER_SAFE, 20, 4, 0), /* AuxReg */
156 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 16, 4, 0), /* TCM */
157 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 12, 4, 0), /* ShareLvl */
158 S_ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 8, 4, 0xf), /* OuterShr */
159 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 4, 4, 0), /* PMSA */
160 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 4, 0), /* VMSA */
164 static struct arm64_ftr_bits ftr_id_aa64dfr0[] = {
165 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 32, 32, 0),
166 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_CTX_CMPS_SHIFT, 4, 0),
167 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_WRPS_SHIFT, 4, 0),
168 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_BRPS_SHIFT, 4, 0),
169 S_ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64DFR0_PMUVER_SHIFT, 4, 0),
170 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64DFR0_TRACEVER_SHIFT, 4, 0),
171 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64DFR0_DEBUGVER_SHIFT, 4, 0x6),
175 static struct arm64_ftr_bits ftr_mvfr2[] = {
176 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 8, 24, 0), /* RAZ */
177 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 4, 4, 0), /* FPMisc */
178 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 4, 0), /* SIMDMisc */
182 static struct arm64_ftr_bits ftr_dczid[] = {
183 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 5, 27, 0), /* RAZ */
184 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 4, 1, 1), /* DZP */
185 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), /* BS */
190 static struct arm64_ftr_bits ftr_id_isar5[] = {
191 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_ISAR5_RDM_SHIFT, 4, 0),
192 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 20, 4, 0), /* RAZ */
193 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_ISAR5_CRC32_SHIFT, 4, 0),
194 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_ISAR5_SHA2_SHIFT, 4, 0),
195 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_ISAR5_SHA1_SHIFT, 4, 0),
196 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_ISAR5_AES_SHIFT, 4, 0),
197 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_ISAR5_SEVL_SHIFT, 4, 0),
201 static struct arm64_ftr_bits ftr_id_mmfr4[] = {
202 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 8, 24, 0), /* RAZ */
203 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 4, 4, 0), /* ac2 */
204 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 4, 0), /* RAZ */
208 static struct arm64_ftr_bits ftr_id_pfr0[] = {
209 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 16, 16, 0), /* RAZ */
210 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 12, 4, 0), /* State3 */
211 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 8, 4, 0), /* State2 */
212 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 4, 4, 0), /* State1 */
213 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 4, 0), /* State0 */
217 static struct arm64_ftr_bits ftr_id_dfr0[] = {
218 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0),
219 S_ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0xf), /* PerfMon */
220 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0),
221 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0),
222 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0),
223 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0),
224 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),
225 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),
230 * Common ftr bits for a 32bit register with all hidden, strict
231 * attributes, with 4bit feature fields and a default safe value of
232 * 0. Covers the following 32bit registers:
233 * id_isar[0-4], id_mmfr[1-3], id_pfr1, mvfr[0-1]
235 static struct arm64_ftr_bits ftr_generic_32bits[] = {
236 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0),
237 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0),
238 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0),
239 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0),
240 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0),
241 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0),
242 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),
243 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),
247 static struct arm64_ftr_bits ftr_generic[] = {
248 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 64, 0),
252 static struct arm64_ftr_bits ftr_generic32[] = {
253 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 32, 0),
257 static struct arm64_ftr_bits ftr_aa64raz[] = {
258 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 64, 0),
262 #define ARM64_FTR_REG(id, table) \
266 .ftr_bits = &((table)[0]), \
269 static struct arm64_ftr_reg arm64_ftr_regs[] = {
271 /* Op1 = 0, CRn = 0, CRm = 1 */
272 ARM64_FTR_REG(SYS_ID_PFR0_EL1, ftr_id_pfr0),
273 ARM64_FTR_REG(SYS_ID_PFR1_EL1, ftr_generic_32bits),
274 ARM64_FTR_REG(SYS_ID_DFR0_EL1, ftr_id_dfr0),
275 ARM64_FTR_REG(SYS_ID_MMFR0_EL1, ftr_id_mmfr0),
276 ARM64_FTR_REG(SYS_ID_MMFR1_EL1, ftr_generic_32bits),
277 ARM64_FTR_REG(SYS_ID_MMFR2_EL1, ftr_generic_32bits),
278 ARM64_FTR_REG(SYS_ID_MMFR3_EL1, ftr_generic_32bits),
280 /* Op1 = 0, CRn = 0, CRm = 2 */
281 ARM64_FTR_REG(SYS_ID_ISAR0_EL1, ftr_generic_32bits),
282 ARM64_FTR_REG(SYS_ID_ISAR1_EL1, ftr_generic_32bits),
283 ARM64_FTR_REG(SYS_ID_ISAR2_EL1, ftr_generic_32bits),
284 ARM64_FTR_REG(SYS_ID_ISAR3_EL1, ftr_generic_32bits),
285 ARM64_FTR_REG(SYS_ID_ISAR4_EL1, ftr_generic_32bits),
286 ARM64_FTR_REG(SYS_ID_ISAR5_EL1, ftr_id_isar5),
287 ARM64_FTR_REG(SYS_ID_MMFR4_EL1, ftr_id_mmfr4),
289 /* Op1 = 0, CRn = 0, CRm = 3 */
290 ARM64_FTR_REG(SYS_MVFR0_EL1, ftr_generic_32bits),
291 ARM64_FTR_REG(SYS_MVFR1_EL1, ftr_generic_32bits),
292 ARM64_FTR_REG(SYS_MVFR2_EL1, ftr_mvfr2),
294 /* Op1 = 0, CRn = 0, CRm = 4 */
295 ARM64_FTR_REG(SYS_ID_AA64PFR0_EL1, ftr_id_aa64pfr0),
296 ARM64_FTR_REG(SYS_ID_AA64PFR1_EL1, ftr_aa64raz),
298 /* Op1 = 0, CRn = 0, CRm = 5 */
299 ARM64_FTR_REG(SYS_ID_AA64DFR0_EL1, ftr_id_aa64dfr0),
300 ARM64_FTR_REG(SYS_ID_AA64DFR1_EL1, ftr_generic),
302 /* Op1 = 0, CRn = 0, CRm = 6 */
303 ARM64_FTR_REG(SYS_ID_AA64ISAR0_EL1, ftr_id_aa64isar0),
304 ARM64_FTR_REG(SYS_ID_AA64ISAR1_EL1, ftr_aa64raz),
306 /* Op1 = 0, CRn = 0, CRm = 7 */
307 ARM64_FTR_REG(SYS_ID_AA64MMFR0_EL1, ftr_id_aa64mmfr0),
308 ARM64_FTR_REG(SYS_ID_AA64MMFR1_EL1, ftr_id_aa64mmfr1),
309 ARM64_FTR_REG(SYS_ID_AA64MMFR2_EL1, ftr_id_aa64mmfr2),
311 /* Op1 = 3, CRn = 0, CRm = 0 */
312 ARM64_FTR_REG(SYS_CTR_EL0, ftr_ctr),
313 ARM64_FTR_REG(SYS_DCZID_EL0, ftr_dczid),
315 /* Op1 = 3, CRn = 14, CRm = 0 */
316 ARM64_FTR_REG(SYS_CNTFRQ_EL0, ftr_generic32),
319 static int search_cmp_ftr_reg(const void *id, const void *regp)
321 return (int)(unsigned long)id - (int)((const struct arm64_ftr_reg *)regp)->sys_id;
325 * get_arm64_ftr_reg - Lookup a feature register entry using its
326 * sys_reg() encoding. With the array arm64_ftr_regs sorted in the
327 * ascending order of sys_id , we use binary search to find a matching
330 * returns - Upon success, matching ftr_reg entry for id.
331 * - NULL on failure. It is upto the caller to decide
332 * the impact of a failure.
334 static struct arm64_ftr_reg *get_arm64_ftr_reg(u32 sys_id)
336 return bsearch((const void *)(unsigned long)sys_id,
338 ARRAY_SIZE(arm64_ftr_regs),
339 sizeof(arm64_ftr_regs[0]),
343 static u64 arm64_ftr_set_value(struct arm64_ftr_bits *ftrp, s64 reg, s64 ftr_val)
345 u64 mask = arm64_ftr_mask(ftrp);
348 reg |= (ftr_val << ftrp->shift) & mask;
352 static s64 arm64_ftr_safe_value(struct arm64_ftr_bits *ftrp, s64 new, s64 cur)
356 switch (ftrp->type) {
358 ret = ftrp->safe_val;
361 ret = new < cur ? new : cur;
363 case FTR_HIGHER_SAFE:
364 ret = new > cur ? new : cur;
373 static int __init sort_cmp_ftr_regs(const void *a, const void *b)
375 return ((const struct arm64_ftr_reg *)a)->sys_id -
376 ((const struct arm64_ftr_reg *)b)->sys_id;
379 static void __init swap_ftr_regs(void *a, void *b, int size)
381 struct arm64_ftr_reg tmp = *(struct arm64_ftr_reg *)a;
382 *(struct arm64_ftr_reg *)a = *(struct arm64_ftr_reg *)b;
383 *(struct arm64_ftr_reg *)b = tmp;
386 static void __init sort_ftr_regs(void)
388 /* Keep the array sorted so that we can do the binary search */
390 ARRAY_SIZE(arm64_ftr_regs),
391 sizeof(arm64_ftr_regs[0]),
397 * Initialise the CPU feature register from Boot CPU values.
398 * Also initiliases the strict_mask for the register.
400 static void __init init_cpu_ftr_reg(u32 sys_reg, u64 new)
403 u64 strict_mask = ~0x0ULL;
404 struct arm64_ftr_bits *ftrp;
405 struct arm64_ftr_reg *reg = get_arm64_ftr_reg(sys_reg);
409 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) {
410 s64 ftr_new = arm64_ftr_value(ftrp, new);
412 val = arm64_ftr_set_value(ftrp, val, ftr_new);
414 strict_mask &= ~arm64_ftr_mask(ftrp);
417 reg->strict_mask = strict_mask;
420 void __init init_cpu_features(struct cpuinfo_arm64 *info)
422 /* Before we start using the tables, make sure it is sorted */
425 init_cpu_ftr_reg(SYS_CTR_EL0, info->reg_ctr);
426 init_cpu_ftr_reg(SYS_DCZID_EL0, info->reg_dczid);
427 init_cpu_ftr_reg(SYS_CNTFRQ_EL0, info->reg_cntfrq);
428 init_cpu_ftr_reg(SYS_ID_AA64DFR0_EL1, info->reg_id_aa64dfr0);
429 init_cpu_ftr_reg(SYS_ID_AA64DFR1_EL1, info->reg_id_aa64dfr1);
430 init_cpu_ftr_reg(SYS_ID_AA64ISAR0_EL1, info->reg_id_aa64isar0);
431 init_cpu_ftr_reg(SYS_ID_AA64ISAR1_EL1, info->reg_id_aa64isar1);
432 init_cpu_ftr_reg(SYS_ID_AA64MMFR0_EL1, info->reg_id_aa64mmfr0);
433 init_cpu_ftr_reg(SYS_ID_AA64MMFR1_EL1, info->reg_id_aa64mmfr1);
434 init_cpu_ftr_reg(SYS_ID_AA64MMFR2_EL1, info->reg_id_aa64mmfr2);
435 init_cpu_ftr_reg(SYS_ID_AA64PFR0_EL1, info->reg_id_aa64pfr0);
436 init_cpu_ftr_reg(SYS_ID_AA64PFR1_EL1, info->reg_id_aa64pfr1);
437 init_cpu_ftr_reg(SYS_ID_DFR0_EL1, info->reg_id_dfr0);
438 init_cpu_ftr_reg(SYS_ID_ISAR0_EL1, info->reg_id_isar0);
439 init_cpu_ftr_reg(SYS_ID_ISAR1_EL1, info->reg_id_isar1);
440 init_cpu_ftr_reg(SYS_ID_ISAR2_EL1, info->reg_id_isar2);
441 init_cpu_ftr_reg(SYS_ID_ISAR3_EL1, info->reg_id_isar3);
442 init_cpu_ftr_reg(SYS_ID_ISAR4_EL1, info->reg_id_isar4);
443 init_cpu_ftr_reg(SYS_ID_ISAR5_EL1, info->reg_id_isar5);
444 init_cpu_ftr_reg(SYS_ID_MMFR0_EL1, info->reg_id_mmfr0);
445 init_cpu_ftr_reg(SYS_ID_MMFR1_EL1, info->reg_id_mmfr1);
446 init_cpu_ftr_reg(SYS_ID_MMFR2_EL1, info->reg_id_mmfr2);
447 init_cpu_ftr_reg(SYS_ID_MMFR3_EL1, info->reg_id_mmfr3);
448 init_cpu_ftr_reg(SYS_ID_PFR0_EL1, info->reg_id_pfr0);
449 init_cpu_ftr_reg(SYS_ID_PFR1_EL1, info->reg_id_pfr1);
450 init_cpu_ftr_reg(SYS_MVFR0_EL1, info->reg_mvfr0);
451 init_cpu_ftr_reg(SYS_MVFR1_EL1, info->reg_mvfr1);
452 init_cpu_ftr_reg(SYS_MVFR2_EL1, info->reg_mvfr2);
455 static void update_cpu_ftr_reg(struct arm64_ftr_reg *reg, u64 new)
457 struct arm64_ftr_bits *ftrp;
459 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) {
460 s64 ftr_cur = arm64_ftr_value(ftrp, reg->sys_val);
461 s64 ftr_new = arm64_ftr_value(ftrp, new);
463 if (ftr_cur == ftr_new)
465 /* Find a safe value */
466 ftr_new = arm64_ftr_safe_value(ftrp, ftr_new, ftr_cur);
467 reg->sys_val = arm64_ftr_set_value(ftrp, reg->sys_val, ftr_new);
472 static int check_update_ftr_reg(u32 sys_id, int cpu, u64 val, u64 boot)
474 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id);
477 update_cpu_ftr_reg(regp, val);
478 if ((boot & regp->strict_mask) == (val & regp->strict_mask))
480 pr_warn("SANITY CHECK: Unexpected variation in %s. Boot CPU: %#016llx, CPU%d: %#016llx\n",
481 regp->name, boot, cpu, val);
486 * Update system wide CPU feature registers with the values from a
487 * non-boot CPU. Also performs SANITY checks to make sure that there
488 * aren't any insane variations from that of the boot CPU.
490 void update_cpu_features(int cpu,
491 struct cpuinfo_arm64 *info,
492 struct cpuinfo_arm64 *boot)
497 * The kernel can handle differing I-cache policies, but otherwise
498 * caches should look identical. Userspace JITs will make use of
501 taint |= check_update_ftr_reg(SYS_CTR_EL0, cpu,
502 info->reg_ctr, boot->reg_ctr);
505 * Userspace may perform DC ZVA instructions. Mismatched block sizes
506 * could result in too much or too little memory being zeroed if a
507 * process is preempted and migrated between CPUs.
509 taint |= check_update_ftr_reg(SYS_DCZID_EL0, cpu,
510 info->reg_dczid, boot->reg_dczid);
512 /* If different, timekeeping will be broken (especially with KVM) */
513 taint |= check_update_ftr_reg(SYS_CNTFRQ_EL0, cpu,
514 info->reg_cntfrq, boot->reg_cntfrq);
517 * The kernel uses self-hosted debug features and expects CPUs to
518 * support identical debug features. We presently need CTX_CMPs, WRPs,
519 * and BRPs to be identical.
520 * ID_AA64DFR1 is currently RES0.
522 taint |= check_update_ftr_reg(SYS_ID_AA64DFR0_EL1, cpu,
523 info->reg_id_aa64dfr0, boot->reg_id_aa64dfr0);
524 taint |= check_update_ftr_reg(SYS_ID_AA64DFR1_EL1, cpu,
525 info->reg_id_aa64dfr1, boot->reg_id_aa64dfr1);
527 * Even in big.LITTLE, processors should be identical instruction-set
530 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR0_EL1, cpu,
531 info->reg_id_aa64isar0, boot->reg_id_aa64isar0);
532 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR1_EL1, cpu,
533 info->reg_id_aa64isar1, boot->reg_id_aa64isar1);
536 * Differing PARange support is fine as long as all peripherals and
537 * memory are mapped within the minimum PARange of all CPUs.
538 * Linux should not care about secure memory.
540 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR0_EL1, cpu,
541 info->reg_id_aa64mmfr0, boot->reg_id_aa64mmfr0);
542 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR1_EL1, cpu,
543 info->reg_id_aa64mmfr1, boot->reg_id_aa64mmfr1);
544 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR2_EL1, cpu,
545 info->reg_id_aa64mmfr2, boot->reg_id_aa64mmfr2);
548 * EL3 is not our concern.
549 * ID_AA64PFR1 is currently RES0.
551 taint |= check_update_ftr_reg(SYS_ID_AA64PFR0_EL1, cpu,
552 info->reg_id_aa64pfr0, boot->reg_id_aa64pfr0);
553 taint |= check_update_ftr_reg(SYS_ID_AA64PFR1_EL1, cpu,
554 info->reg_id_aa64pfr1, boot->reg_id_aa64pfr1);
557 * If we have AArch32, we care about 32-bit features for compat. These
558 * registers should be RES0 otherwise.
560 taint |= check_update_ftr_reg(SYS_ID_DFR0_EL1, cpu,
561 info->reg_id_dfr0, boot->reg_id_dfr0);
562 taint |= check_update_ftr_reg(SYS_ID_ISAR0_EL1, cpu,
563 info->reg_id_isar0, boot->reg_id_isar0);
564 taint |= check_update_ftr_reg(SYS_ID_ISAR1_EL1, cpu,
565 info->reg_id_isar1, boot->reg_id_isar1);
566 taint |= check_update_ftr_reg(SYS_ID_ISAR2_EL1, cpu,
567 info->reg_id_isar2, boot->reg_id_isar2);
568 taint |= check_update_ftr_reg(SYS_ID_ISAR3_EL1, cpu,
569 info->reg_id_isar3, boot->reg_id_isar3);
570 taint |= check_update_ftr_reg(SYS_ID_ISAR4_EL1, cpu,
571 info->reg_id_isar4, boot->reg_id_isar4);
572 taint |= check_update_ftr_reg(SYS_ID_ISAR5_EL1, cpu,
573 info->reg_id_isar5, boot->reg_id_isar5);
576 * Regardless of the value of the AuxReg field, the AIFSR, ADFSR, and
577 * ACTLR formats could differ across CPUs and therefore would have to
578 * be trapped for virtualization anyway.
580 taint |= check_update_ftr_reg(SYS_ID_MMFR0_EL1, cpu,
581 info->reg_id_mmfr0, boot->reg_id_mmfr0);
582 taint |= check_update_ftr_reg(SYS_ID_MMFR1_EL1, cpu,
583 info->reg_id_mmfr1, boot->reg_id_mmfr1);
584 taint |= check_update_ftr_reg(SYS_ID_MMFR2_EL1, cpu,
585 info->reg_id_mmfr2, boot->reg_id_mmfr2);
586 taint |= check_update_ftr_reg(SYS_ID_MMFR3_EL1, cpu,
587 info->reg_id_mmfr3, boot->reg_id_mmfr3);
588 taint |= check_update_ftr_reg(SYS_ID_PFR0_EL1, cpu,
589 info->reg_id_pfr0, boot->reg_id_pfr0);
590 taint |= check_update_ftr_reg(SYS_ID_PFR1_EL1, cpu,
591 info->reg_id_pfr1, boot->reg_id_pfr1);
592 taint |= check_update_ftr_reg(SYS_MVFR0_EL1, cpu,
593 info->reg_mvfr0, boot->reg_mvfr0);
594 taint |= check_update_ftr_reg(SYS_MVFR1_EL1, cpu,
595 info->reg_mvfr1, boot->reg_mvfr1);
596 taint |= check_update_ftr_reg(SYS_MVFR2_EL1, cpu,
597 info->reg_mvfr2, boot->reg_mvfr2);
600 * Mismatched CPU features are a recipe for disaster. Don't even
601 * pretend to support them.
603 WARN_TAINT_ONCE(taint, TAINT_CPU_OUT_OF_SPEC,
604 "Unsupported CPU feature variation.\n");
607 u64 read_system_reg(u32 id)
609 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(id);
611 /* We shouldn't get a request for an unsupported register */
613 return regp->sys_val;
616 #include <linux/irqchip/arm-gic-v3.h>
619 feature_matches(u64 reg, const struct arm64_cpu_capabilities *entry)
621 int val = cpuid_feature_extract_field(reg, entry->field_pos);
623 return val >= entry->min_field_value;
627 has_cpuid_feature(const struct arm64_cpu_capabilities *entry)
631 val = read_system_reg(entry->sys_reg);
632 return feature_matches(val, entry);
635 static bool has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities *entry)
639 if (!has_cpuid_feature(entry))
642 has_sre = gic_enable_sre();
644 pr_warn_once("%s present but disabled by higher exception level\n",
650 static bool has_no_hw_prefetch(const struct arm64_cpu_capabilities *entry)
652 u32 midr = read_cpuid_id();
655 /* Cavium ThunderX pass 1.x and 2.x */
657 rv_max = (1 << MIDR_VARIANT_SHIFT) | MIDR_REVISION_MASK;
659 return MIDR_IS_CPU_MODEL_RANGE(midr, MIDR_THUNDERX, rv_min, rv_max);
662 static const struct arm64_cpu_capabilities arm64_features[] = {
664 .desc = "GIC system register CPU interface",
665 .capability = ARM64_HAS_SYSREG_GIC_CPUIF,
666 .matches = has_useable_gicv3_cpuif,
667 .sys_reg = SYS_ID_AA64PFR0_EL1,
668 .field_pos = ID_AA64PFR0_GIC_SHIFT,
669 .sign = FTR_UNSIGNED,
670 .min_field_value = 1,
672 #ifdef CONFIG_ARM64_PAN
674 .desc = "Privileged Access Never",
675 .capability = ARM64_HAS_PAN,
676 .matches = has_cpuid_feature,
677 .sys_reg = SYS_ID_AA64MMFR1_EL1,
678 .field_pos = ID_AA64MMFR1_PAN_SHIFT,
679 .sign = FTR_UNSIGNED,
680 .min_field_value = 1,
681 .enable = cpu_enable_pan,
683 #endif /* CONFIG_ARM64_PAN */
684 #if defined(CONFIG_AS_LSE) && defined(CONFIG_ARM64_LSE_ATOMICS)
686 .desc = "LSE atomic instructions",
687 .capability = ARM64_HAS_LSE_ATOMICS,
688 .matches = has_cpuid_feature,
689 .sys_reg = SYS_ID_AA64ISAR0_EL1,
690 .field_pos = ID_AA64ISAR0_ATOMICS_SHIFT,
691 .sign = FTR_UNSIGNED,
692 .min_field_value = 2,
694 #endif /* CONFIG_AS_LSE && CONFIG_ARM64_LSE_ATOMICS */
696 .desc = "Software prefetching using PRFM",
697 .capability = ARM64_HAS_NO_HW_PREFETCH,
698 .matches = has_no_hw_prefetch,
700 #ifdef CONFIG_ARM64_UAO
702 .desc = "User Access Override",
703 .capability = ARM64_HAS_UAO,
704 .matches = has_cpuid_feature,
705 .sys_reg = SYS_ID_AA64MMFR2_EL1,
706 .field_pos = ID_AA64MMFR2_UAO_SHIFT,
707 .min_field_value = 1,
708 .enable = cpu_enable_uao,
710 #endif /* CONFIG_ARM64_UAO */
711 #ifdef CONFIG_ARM64_PAN
713 .capability = ARM64_ALT_PAN_NOT_UAO,
714 .matches = cpufeature_pan_not_uao,
716 #endif /* CONFIG_ARM64_PAN */
720 #define HWCAP_CAP(reg, field, s, min_value, type, cap) \
723 .matches = has_cpuid_feature, \
725 .field_pos = field, \
727 .min_field_value = min_value, \
728 .hwcap_type = type, \
732 static const struct arm64_cpu_capabilities arm64_hwcaps[] = {
733 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, HWCAP_PMULL),
734 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_AES),
735 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA1_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_SHA1),
736 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA2_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_SHA2),
737 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_CRC32_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_CRC32),
738 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_ATOMICS_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, HWCAP_ATOMICS),
739 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, HWCAP_FP),
740 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, HWCAP_ASIMD),
742 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_PMULL),
743 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_AES),
744 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA1_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA1),
745 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA2_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA2),
746 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_CRC32_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_CRC32),
751 static void __init cap_set_hwcap(const struct arm64_cpu_capabilities *cap)
753 switch (cap->hwcap_type) {
755 elf_hwcap |= cap->hwcap;
758 case CAP_COMPAT_HWCAP:
759 compat_elf_hwcap |= (u32)cap->hwcap;
761 case CAP_COMPAT_HWCAP2:
762 compat_elf_hwcap2 |= (u32)cap->hwcap;
771 /* Check if we have a particular HWCAP enabled */
772 static bool __maybe_unused cpus_have_hwcap(const struct arm64_cpu_capabilities *cap)
776 switch (cap->hwcap_type) {
778 rc = (elf_hwcap & cap->hwcap) != 0;
781 case CAP_COMPAT_HWCAP:
782 rc = (compat_elf_hwcap & (u32)cap->hwcap) != 0;
784 case CAP_COMPAT_HWCAP2:
785 rc = (compat_elf_hwcap2 & (u32)cap->hwcap) != 0;
796 static void __init setup_cpu_hwcaps(void)
799 const struct arm64_cpu_capabilities *hwcaps = arm64_hwcaps;
801 for (i = 0; hwcaps[i].matches; i++)
802 if (hwcaps[i].matches(&hwcaps[i]))
803 cap_set_hwcap(&hwcaps[i]);
806 void update_cpu_capabilities(const struct arm64_cpu_capabilities *caps,
811 for (i = 0; caps[i].matches; i++) {
812 if (!caps[i].matches(&caps[i]))
815 if (!cpus_have_cap(caps[i].capability) && caps[i].desc)
816 pr_info("%s %s\n", info, caps[i].desc);
817 cpus_set_cap(caps[i].capability);
822 * Run through the enabled capabilities and enable() it on all active
826 enable_cpu_capabilities(const struct arm64_cpu_capabilities *caps)
830 for (i = 0; caps[i].matches; i++)
831 if (caps[i].enable && cpus_have_cap(caps[i].capability))
832 on_each_cpu(caps[i].enable, NULL, true);
836 * Flag to indicate if we have computed the system wide
837 * capabilities based on the boot time active CPUs. This
838 * will be used to determine if a new booting CPU should
839 * go through the verification process to make sure that it
840 * supports the system capabilities, without using a hotplug
843 static bool sys_caps_initialised;
845 static inline void set_sys_caps_initialised(void)
847 sys_caps_initialised = true;
851 * __raw_read_system_reg() - Used by a STARTING cpu before cpuinfo is populated.
853 static u64 __raw_read_system_reg(u32 sys_id)
856 case SYS_ID_PFR0_EL1: return read_cpuid(SYS_ID_PFR0_EL1);
857 case SYS_ID_PFR1_EL1: return read_cpuid(SYS_ID_PFR1_EL1);
858 case SYS_ID_DFR0_EL1: return read_cpuid(SYS_ID_DFR0_EL1);
859 case SYS_ID_MMFR0_EL1: return read_cpuid(SYS_ID_MMFR0_EL1);
860 case SYS_ID_MMFR1_EL1: return read_cpuid(SYS_ID_MMFR1_EL1);
861 case SYS_ID_MMFR2_EL1: return read_cpuid(SYS_ID_MMFR2_EL1);
862 case SYS_ID_MMFR3_EL1: return read_cpuid(SYS_ID_MMFR3_EL1);
863 case SYS_ID_ISAR0_EL1: return read_cpuid(SYS_ID_ISAR0_EL1);
864 case SYS_ID_ISAR1_EL1: return read_cpuid(SYS_ID_ISAR1_EL1);
865 case SYS_ID_ISAR2_EL1: return read_cpuid(SYS_ID_ISAR2_EL1);
866 case SYS_ID_ISAR3_EL1: return read_cpuid(SYS_ID_ISAR3_EL1);
867 case SYS_ID_ISAR4_EL1: return read_cpuid(SYS_ID_ISAR4_EL1);
868 case SYS_ID_ISAR5_EL1: return read_cpuid(SYS_ID_ISAR4_EL1);
869 case SYS_MVFR0_EL1: return read_cpuid(SYS_MVFR0_EL1);
870 case SYS_MVFR1_EL1: return read_cpuid(SYS_MVFR1_EL1);
871 case SYS_MVFR2_EL1: return read_cpuid(SYS_MVFR2_EL1);
873 case SYS_ID_AA64PFR0_EL1: return read_cpuid(SYS_ID_AA64PFR0_EL1);
874 case SYS_ID_AA64PFR1_EL1: return read_cpuid(SYS_ID_AA64PFR0_EL1);
875 case SYS_ID_AA64DFR0_EL1: return read_cpuid(SYS_ID_AA64DFR0_EL1);
876 case SYS_ID_AA64DFR1_EL1: return read_cpuid(SYS_ID_AA64DFR0_EL1);
877 case SYS_ID_AA64MMFR0_EL1: return read_cpuid(SYS_ID_AA64MMFR0_EL1);
878 case SYS_ID_AA64MMFR1_EL1: return read_cpuid(SYS_ID_AA64MMFR1_EL1);
879 case SYS_ID_AA64MMFR2_EL1: return read_cpuid(SYS_ID_AA64MMFR2_EL1);
880 case SYS_ID_AA64ISAR0_EL1: return read_cpuid(SYS_ID_AA64ISAR0_EL1);
881 case SYS_ID_AA64ISAR1_EL1: return read_cpuid(SYS_ID_AA64ISAR1_EL1);
883 case SYS_CNTFRQ_EL0: return read_cpuid(SYS_CNTFRQ_EL0);
884 case SYS_CTR_EL0: return read_cpuid(SYS_CTR_EL0);
885 case SYS_DCZID_EL0: return read_cpuid(SYS_DCZID_EL0);
893 * Check for CPU features that are used in early boot
894 * based on the Boot CPU value.
896 static void check_early_cpu_features(void)
898 verify_cpu_asid_bits();
902 * Run through the enabled system capabilities and enable() it on this CPU.
903 * The capabilities were decided based on the available CPUs at the boot time.
904 * Any new CPU should match the system wide status of the capability. If the
905 * new CPU doesn't have a capability which the system now has enabled, we
906 * cannot do anything to fix it up and could cause unexpected failures. So
909 void verify_local_cpu_capabilities(void)
912 const struct arm64_cpu_capabilities *caps;
914 check_early_cpu_features();
917 * If we haven't computed the system capabilities, there is nothing
920 if (!sys_caps_initialised)
923 caps = arm64_features;
924 for (i = 0; caps[i].matches; i++) {
925 if (!cpus_have_cap(caps[i].capability) || !caps[i].sys_reg)
928 * If the new CPU misses an advertised feature, we cannot proceed
929 * further, park the cpu.
931 if (!feature_matches(__raw_read_system_reg(caps[i].sys_reg), &caps[i])) {
932 pr_crit("CPU%d: missing feature: %s\n",
933 smp_processor_id(), caps[i].desc);
937 caps[i].enable(NULL);
940 for (i = 0, caps = arm64_hwcaps; caps[i].matches; i++) {
941 if (!cpus_have_hwcap(&caps[i]))
943 if (!feature_matches(__raw_read_system_reg(caps[i].sys_reg), &caps[i])) {
944 pr_crit("CPU%d: missing HWCAP: %s\n",
945 smp_processor_id(), caps[i].desc);
951 static void __init setup_feature_capabilities(void)
953 update_cpu_capabilities(arm64_features, "detected feature:");
954 enable_cpu_capabilities(arm64_features);
957 void __init setup_cpu_features(void)
962 /* Set the CPU feature capabilies */
963 setup_feature_capabilities();
966 /* Advertise that we have computed the system capabilities */
967 set_sys_caps_initialised();
970 * Check for sane CTR_EL0.CWG value.
972 cwg = cache_type_cwg();
973 cls = cache_line_size();
975 pr_warn("No Cache Writeback Granule information, assuming cache line size %d\n",
977 if (L1_CACHE_BYTES < cls)
978 pr_warn("L1_CACHE_BYTES smaller than the Cache Writeback Granule (%d < %d)\n",
979 L1_CACHE_BYTES, cls);
982 static bool __maybe_unused
983 cpufeature_pan_not_uao(const struct arm64_cpu_capabilities *entry)
985 return (cpus_have_cap(ARM64_HAS_PAN) && !cpus_have_cap(ARM64_HAS_UAO));