3 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
4 * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP
5 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
6 * Low-level exception handlers and MMU support
7 * rewritten by Paul Mackerras.
8 * Copyright (C) 1996 Paul Mackerras.
9 * MPC8xx modifications by Dan Malek
10 * Copyright (C) 1997 Dan Malek (dmalek@jlc.net).
12 * This file contains low-level support and setup for PowerPC 8xx
13 * embedded processors, including trap and interrupt dispatch.
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License
17 * as published by the Free Software Foundation; either version
18 * 2 of the License, or (at your option) any later version.
22 #include <linux/init.h>
23 #include <asm/processor.h>
26 #include <asm/cache.h>
27 #include <asm/pgtable.h>
28 #include <asm/cputable.h>
29 #include <asm/thread_info.h>
30 #include <asm/ppc_asm.h>
31 #include <asm/asm-offsets.h>
32 #include <asm/ptrace.h>
34 /* Macro to make the code more readable. */
35 #ifdef CONFIG_8xx_CPU6
36 #define SPRN_MI_TWC_ADDR 0x2b80
37 #define SPRN_MI_RPN_ADDR 0x2d80
38 #define SPRN_MD_TWC_ADDR 0x3b80
39 #define SPRN_MD_RPN_ADDR 0x3d80
41 #define MTSPR_CPU6(spr, reg, treg) \
42 li treg, spr##_ADDR; \
47 #define MTSPR_CPU6(spr, reg, treg) \
51 /* Macro to test if an address is a kernel address */
52 #if CONFIG_TASK_SIZE <= 0x80000000 && CONFIG_PAGE_OFFSET >= 0x80000000
53 #define IS_KERNEL(tmp, addr) \
54 andis. tmp, addr, 0x8000 /* Address >= 0x80000000 */
55 #define BRANCH_UNLESS_KERNEL(label) beq label
57 #define IS_KERNEL(tmp, addr) \
58 rlwinm tmp, addr, 16, 16, 31; \
59 cmpli cr0, tmp, PAGE_OFFSET >> 16
60 #define BRANCH_UNLESS_KERNEL(label) blt label
65 * Value for the bits that have fixed value in RPN entries.
66 * Also used for tagging DAR for DTLBerror.
68 #ifdef CONFIG_PPC_16K_PAGES
69 #define RPN_PATTERN (0x00f0 | MD_SPS16K)
71 #define RPN_PATTERN 0x00f0
79 * This port was done on an MBX board with an 860. Right now I only
80 * support an ELF compressed (zImage) boot from EPPC-Bug because the
81 * code there loads up some registers before calling us:
82 * r3: ptr to board info data
83 * r4: initrd_start or if no initrd then 0
84 * r5: initrd_end - unused if r4 is 0
85 * r6: Start of command line string
86 * r7: End of command line string
88 * I decided to use conditional compilation instead of checking PVR and
89 * adding more processor specific branches around code I don't need.
90 * Since this is an embedded processor, I also appreciate any memory
93 * The MPC8xx does not have any BATs, but it supports large page sizes.
94 * We first initialize the MMU to support 8M byte pages, then load one
95 * entry into each of the instruction and data TLBs to map the first
96 * 8M 1:1. I also mapped an additional I/O space 1:1 so we can get to
97 * the "internal" processor registers before MMU_init is called.
103 mr r31,r3 /* save device tree ptr */
105 /* We have to turn on the MMU right away so we get cache modes
110 /* We now have the lower 8 Meg mapped into TLB entries, and the caches
116 ori r0,r0,MSR_DR|MSR_IR
119 ori r0,r0,start_here@l
122 rfi /* enables MMU */
125 * Exception entry code. This code runs with address translation
126 * turned off, i.e. using physical addresses.
127 * We assume sprg3 has the physical address of the current
128 * task's thread_struct.
130 #define EXCEPTION_PROLOG \
131 EXCEPTION_PROLOG_0; \
133 EXCEPTION_PROLOG_1; \
136 #define EXCEPTION_PROLOG_0 \
137 mtspr SPRN_SPRG_SCRATCH0,r10; \
138 mtspr SPRN_SPRG_SCRATCH1,r11
140 #define EXCEPTION_PROLOG_1 \
141 mfspr r11,SPRN_SRR1; /* check whether user or kernel */ \
142 andi. r11,r11,MSR_PR; \
143 tophys(r11,r1); /* use tophys(r1) if kernel */ \
145 mfspr r11,SPRN_SPRG_THREAD; \
146 lwz r11,THREAD_INFO-THREAD(r11); \
147 addi r11,r11,THREAD_SIZE; \
149 1: subi r11,r11,INT_FRAME_SIZE /* alloc exc. frame */
152 #define EXCEPTION_PROLOG_2 \
154 stw r10,_CCR(r11); /* save registers */ \
155 stw r12,GPR12(r11); \
157 mfspr r10,SPRN_SPRG_SCRATCH0; \
158 stw r10,GPR10(r11); \
159 mfspr r12,SPRN_SPRG_SCRATCH1; \
160 stw r12,GPR11(r11); \
162 stw r10,_LINK(r11); \
163 mfspr r12,SPRN_SRR0; \
164 mfspr r9,SPRN_SRR1; \
167 tovirt(r1,r11); /* set new kernel sp */ \
168 li r10,MSR_KERNEL & ~(MSR_IR|MSR_DR); /* can take exceptions */ \
169 MTMSRD(r10); /* (except for mach check in rtas) */ \
171 SAVE_4GPRS(3, r11); \
175 * Exception exit code.
177 #define EXCEPTION_EPILOG_0 \
178 mfspr r10,SPRN_SPRG_SCRATCH0; \
179 mfspr r11,SPRN_SPRG_SCRATCH1
182 * Note: code which follows this uses cr0.eq (set if from kernel),
183 * r11, r12 (SRR0), and r9 (SRR1).
185 * Note2: once we have set r1 we are in a position to take exceptions
186 * again, and we could thus set MSR:RI at that point.
192 #define EXCEPTION(n, label, hdlr, xfer) \
196 addi r3,r1,STACK_FRAME_OVERHEAD; \
199 #define EXC_XFER_TEMPLATE(n, hdlr, trap, copyee, tfer, ret) \
201 stw r10,_TRAP(r11); \
209 #define COPY_EE(d, s) rlwimi d,s,0,16,16
212 #define EXC_XFER_STD(n, hdlr) \
213 EXC_XFER_TEMPLATE(n, hdlr, n, NOCOPY, transfer_to_handler_full, \
214 ret_from_except_full)
216 #define EXC_XFER_LITE(n, hdlr) \
217 EXC_XFER_TEMPLATE(n, hdlr, n+1, NOCOPY, transfer_to_handler, \
220 #define EXC_XFER_EE(n, hdlr) \
221 EXC_XFER_TEMPLATE(n, hdlr, n, COPY_EE, transfer_to_handler_full, \
222 ret_from_except_full)
224 #define EXC_XFER_EE_LITE(n, hdlr) \
225 EXC_XFER_TEMPLATE(n, hdlr, n+1, COPY_EE, transfer_to_handler, \
229 EXCEPTION(0x100, Reset, unknown_exception, EXC_XFER_STD)
238 mtspr SPRN_DAR,r5 /* Tag DAR, to be used in DTLB Error */
241 addi r3,r1,STACK_FRAME_OVERHEAD
242 EXC_XFER_STD(0x200, machine_check_exception)
244 /* Data access exception.
245 * This is "never generated" by the MPC8xx.
250 /* Instruction access exception.
251 * This is "never generated" by the MPC8xx.
256 /* External interrupt */
257 EXCEPTION(0x500, HardwareInterrupt, do_IRQ, EXC_XFER_LITE)
259 /* Alignment exception */
266 mtspr SPRN_DAR,r5 /* Tag DAR, to be used in DTLB Error */
269 addi r3,r1,STACK_FRAME_OVERHEAD
270 EXC_XFER_EE(0x600, alignment_exception)
272 /* Program check exception */
273 EXCEPTION(0x700, ProgramCheck, program_check_exception, EXC_XFER_STD)
275 /* No FPU on MPC8xx. This exception is not supposed to happen.
277 EXCEPTION(0x800, FPUnavailable, unknown_exception, EXC_XFER_STD)
280 EXCEPTION(0x900, Decrementer, timer_interrupt, EXC_XFER_LITE)
282 EXCEPTION(0xa00, Trap_0a, unknown_exception, EXC_XFER_EE)
283 EXCEPTION(0xb00, Trap_0b, unknown_exception, EXC_XFER_EE)
289 EXC_XFER_EE_LITE(0xc00, DoSyscall)
291 /* Single step - not used on 601 */
292 EXCEPTION(0xd00, SingleStep, single_step_exception, EXC_XFER_STD)
293 EXCEPTION(0xe00, Trap_0e, unknown_exception, EXC_XFER_EE)
294 EXCEPTION(0xf00, Trap_0f, unknown_exception, EXC_XFER_EE)
296 /* On the MPC8xx, this is a software emulation interrupt. It occurs
297 * for all unimplemented and illegal instructions.
299 EXCEPTION(0x1000, SoftEmu, SoftwareEmulation, EXC_XFER_STD)
303 * For the MPC8xx, this is a software tablewalk to load the instruction
304 * TLB. The task switch loads the M_TW register with the pointer to the first
306 * If we discover there is no second level table (value is zero) or if there
307 * is an invalid pte, we load that into the TLB, which causes another fault
308 * into the TLB Error interrupt where we can handle such problems.
309 * We have to use the MD_xxx registers for the tablewalk because the
310 * equivalent MI_xxx registers only perform the attribute functions.
313 #ifdef CONFIG_8xx_CPU15
314 #define INVALIDATE_ADJACENT_PAGES_CPU15(tmp, addr) \
315 addi tmp, addr, PAGE_SIZE; \
317 addi tmp, addr, -PAGE_SIZE; \
320 #define INVALIDATE_ADJACENT_PAGES_CPU15(tmp, addr)
324 #ifdef CONFIG_8xx_CPU6
325 mtspr SPRN_SPRG_SCRATCH2, r3
329 /* If we are faulting a kernel address, we have to use the
330 * kernel page tables.
332 #if defined(CONFIG_MODULES) || defined (CONFIG_DEBUG_PAGEALLOC)
333 /* Only modules will cause ITLB Misses as we always
334 * pin the first 8MB of kernel memory */
335 mfspr r11, SPRN_SRR0 /* Get effective address of fault */
336 INVALIDATE_ADJACENT_PAGES_CPU15(r10, r11)
339 mfspr r11, SPRN_M_TW /* Get level 1 table */
340 BRANCH_UNLESS_KERNEL(3f)
341 lis r11, (swapper_pg_dir-PAGE_OFFSET)@ha
344 mfspr r10, SPRN_SRR0 /* Get effective address of fault */
346 mfspr r10, SPRN_SRR0 /* Get effective address of fault */
347 INVALIDATE_ADJACENT_PAGES_CPU15(r11, r10)
348 mfspr r11, SPRN_M_TW /* Get level 1 table base address */
350 /* Insert level 1 index */
351 rlwimi r11, r10, 32 - ((PAGE_SHIFT - 2) << 1), (PAGE_SHIFT - 2) << 1, 29
352 lwz r11, (swapper_pg_dir-PAGE_OFFSET)@l(r11) /* Get the level 1 entry */
354 /* Extract level 2 index */
355 rlwinm r10, r10, 32 - (PAGE_SHIFT - 2), 32 - PAGE_SHIFT, 29
356 rlwimi r10, r11, 0, 0, 32 - PAGE_SHIFT - 1 /* Add level 2 base */
357 lwz r10, 0(r10) /* Get the pte */
359 /* Insert the APG into the TWC from the Linux PTE. */
360 rlwimi r11, r10, 0, 25, 26
361 /* Load the MI_TWC with the attributes for this "segment." */
362 MTSPR_CPU6(SPRN_MI_TWC, r11, r3) /* Set segment attributes */
365 rlwinm r11, r10, 32-5, _PAGE_PRESENT
367 rlwimi r10, r11, 0, _PAGE_PRESENT
370 /* The Linux PTE won't go exactly into the MMU TLB.
371 * Software indicator bits 20-23 and 28 must be clear.
372 * Software indicator bits 24, 25, 26, and 27 must be
373 * set. All other Linux PTE bits control the behavior
376 rlwimi r10, r11, 0, 0x0ff8 /* Set 24-27, clear 20-23,28 */
377 MTSPR_CPU6(SPRN_MI_RPN, r10, r3) /* Update TLB entry */
379 /* Restore registers */
380 #ifdef CONFIG_8xx_CPU6
381 mfspr r3, SPRN_SPRG_SCRATCH2
388 mtspr SPRN_SPRG_SCRATCH2, r3
392 /* If we are faulting a kernel address, we have to use the
393 * kernel page tables.
395 mfspr r10, SPRN_MD_EPN
397 mfspr r11, SPRN_M_TW /* Get level 1 table */
398 BRANCH_UNLESS_KERNEL(3f)
399 lis r11, (swapper_pg_dir-PAGE_OFFSET)@ha
403 /* Insert level 1 index */
404 rlwimi r11, r10, 32 - ((PAGE_SHIFT - 2) << 1), (PAGE_SHIFT - 2) << 1, 29
405 lwz r11, (swapper_pg_dir-PAGE_OFFSET)@l(r11) /* Get the level 1 entry */
407 /* We have a pte table, so load fetch the pte from the table.
409 /* Extract level 2 index */
410 rlwinm r10, r10, 32 - (PAGE_SHIFT - 2), 32 - PAGE_SHIFT, 29
411 rlwimi r10, r11, 0, 0, 32 - PAGE_SHIFT - 1 /* Add level 2 base */
412 lwz r10, 0(r10) /* Get the pte */
414 /* Insert the Guarded flag and APG into the TWC from the Linux PTE.
415 * It is bit 26-27 of both the Linux PTE and the TWC (at least
416 * I got that right :-). It will be better when we can put
417 * this into the Linux pgd/pmd and load it in the operation
420 rlwimi r11, r10, 0, 26, 27
421 /* Insert the WriteThru flag into the TWC from the Linux PTE.
422 * It is bit 25 in the Linux PTE and bit 30 in the TWC
424 rlwimi r11, r10, 32-5, 30, 30
425 MTSPR_CPU6(SPRN_MD_TWC, r11, r3)
427 /* Both _PAGE_ACCESSED and _PAGE_PRESENT has to be set.
428 * We also need to know if the insn is a load/store, so:
429 * Clear _PAGE_PRESENT and load that which will
430 * trap into DTLB Error with store bit set accordinly.
432 /* PRESENT=0x1, ACCESSED=0x20
433 * r11 = ((r10 & PRESENT) & ((r10 & ACCESSED) >> 5));
434 * r10 = (r10 & ~PRESENT) | r11;
437 rlwinm r11, r10, 32-5, _PAGE_PRESENT
439 rlwimi r10, r11, 0, _PAGE_PRESENT
441 /* The Linux PTE won't go exactly into the MMU TLB.
442 * Software indicator bits 22 and 28 must be clear.
443 * Software indicator bits 24, 25, 26, and 27 must be
444 * set. All other Linux PTE bits control the behavior
448 rlwimi r10, r11, 0, 24, 28 /* Set 24-27, clear 28 */
449 rlwimi r10, r11, 0, 20, 20 /* clear 20 */
450 MTSPR_CPU6(SPRN_MD_RPN, r10, r3) /* Update TLB entry */
452 /* Restore registers */
453 mfspr r3, SPRN_SPRG_SCRATCH2
454 mtspr SPRN_DAR, r11 /* Tag DAR */
458 /* This is an instruction TLB error on the MPC8xx. This could be due
459 * to many reasons, such as executing guarded memory or illegal instruction
460 * addresses. There is nothing to do but handle a big time error fault.
470 /* 0x400 is InstructionAccess exception, needed by bad_page_fault() */
471 1: EXC_XFER_LITE(0x400, handle_page_fault)
473 /* This is the data TLB error on the MPC8xx. This could be due to
474 * many reasons, including a dirty update to a pte. We bail out to
475 * a higher level function that can handle it.
483 cmpwi cr0, r11, RPN_PATTERN
484 beq- FixupDAR /* must be a buggy dcbX, icbi insn. */
485 DARFixed:/* Return from dcbx instruction bug workaround */
494 1: li r10,RPN_PATTERN
495 mtspr SPRN_DAR,r10 /* Tag DAR, to be used in DTLB Error */
496 /* 0x300 is DataAccess exception, needed by bad_page_fault() */
497 EXC_XFER_LITE(0x300, handle_page_fault)
499 EXCEPTION(0x1500, Trap_15, unknown_exception, EXC_XFER_EE)
500 EXCEPTION(0x1600, Trap_16, unknown_exception, EXC_XFER_EE)
501 EXCEPTION(0x1700, Trap_17, unknown_exception, EXC_XFER_EE)
502 EXCEPTION(0x1800, Trap_18, unknown_exception, EXC_XFER_EE)
503 EXCEPTION(0x1900, Trap_19, unknown_exception, EXC_XFER_EE)
504 EXCEPTION(0x1a00, Trap_1a, unknown_exception, EXC_XFER_EE)
505 EXCEPTION(0x1b00, Trap_1b, unknown_exception, EXC_XFER_EE)
507 /* On the MPC8xx, these next four traps are used for development
508 * support of breakpoints and such. Someday I will get around to
511 EXCEPTION(0x1c00, Trap_1c, unknown_exception, EXC_XFER_EE)
512 EXCEPTION(0x1d00, Trap_1d, unknown_exception, EXC_XFER_EE)
513 EXCEPTION(0x1e00, Trap_1e, unknown_exception, EXC_XFER_EE)
514 EXCEPTION(0x1f00, Trap_1f, unknown_exception, EXC_XFER_EE)
518 /* This is the procedure to calculate the data EA for buggy dcbx,dcbi instructions
519 * by decoding the registers used by the dcbx instruction and adding them.
520 * DAR is set to the calculated address.
522 /* define if you don't want to use self modifying code */
523 #define NO_SELF_MODIFYING_CODE
524 FixupDAR:/* Entry point for dcbx workaround. */
525 mtspr SPRN_SPRG_SCRATCH2, r10
526 /* fetch instruction from memory. */
529 mfspr r11, SPRN_M_TW /* Get level 1 table */
530 BRANCH_UNLESS_KERNEL(3f)
531 lis r11, (swapper_pg_dir-PAGE_OFFSET)@ha
532 /* Insert level 1 index */
533 3: rlwimi r11, r10, 32 - ((PAGE_SHIFT - 2) << 1), (PAGE_SHIFT - 2) << 1, 29
534 lwz r11, (swapper_pg_dir-PAGE_OFFSET)@l(r11) /* Get the level 1 entry */
535 rlwinm r11, r11,0,0,19 /* Extract page descriptor page address */
536 /* Insert level 2 index */
537 rlwimi r11, r10, 32 - (PAGE_SHIFT - 2), 32 - PAGE_SHIFT, 29
538 lwz r11, 0(r11) /* Get the pte */
539 /* concat physical page address(r11) and page offset(r10) */
540 rlwimi r11, r10, 0, 32 - PAGE_SHIFT, 31
542 /* Check if it really is a dcbx instruction. */
543 /* dcbt and dcbtst does not generate DTLB Misses/Errors,
544 * no need to include them here */
545 xoris r10, r11, 0x7c00 /* check if major OP code is 31 */
546 rlwinm r10, r10, 0, 21, 5
547 cmpwi cr0, r10, 2028 /* Is dcbz? */
549 cmpwi cr0, r10, 940 /* Is dcbi? */
551 cmpwi cr0, r10, 108 /* Is dcbst? */
552 beq+ 144f /* Fix up store bit! */
553 cmpwi cr0, r10, 172 /* Is dcbf? */
555 cmpwi cr0, r10, 1964 /* Is icbi? */
557 141: mfspr r10,SPRN_SPRG_SCRATCH2
558 b DARFixed /* Nope, go back to normal TLB processing */
560 144: mfspr r10, SPRN_DSISR
561 rlwinm r10, r10,0,7,5 /* Clear store bit for buggy dcbst insn */
562 mtspr SPRN_DSISR, r10
563 142: /* continue, it was a dcbx, dcbi instruction. */
564 #ifndef NO_SELF_MODIFYING_CODE
565 andis. r10,r11,0x1f /* test if reg RA is r0 */
566 li r10,modified_instr@l
567 dcbtst r0,r10 /* touch for store */
568 rlwinm r11,r11,0,0,20 /* Zero lower 10 bits */
569 oris r11,r11,640 /* Transform instr. to a "add r10,RA,RB" */
571 stw r11,0(r10) /* store add/and instruction */
572 dcbf 0,r10 /* flush new instr. to memory. */
573 icbi 0,r10 /* invalidate instr. cache line */
574 mfspr r11, SPRN_SPRG_SCRATCH1 /* restore r11 */
575 mfspr r10, SPRN_SPRG_SCRATCH0 /* restore r10 */
576 isync /* Wait until new instr is loaded from memory */
578 .space 4 /* this is where the add instr. is stored */
580 subf r10,r0,r10 /* r10=r10-r0, only if reg RA is r0 */
581 143: mtdar r10 /* store faulting EA in DAR */
582 mfspr r10,SPRN_SPRG_SCRATCH2
583 b DARFixed /* Go back to normal TLB handling */
586 mtdar r10 /* save ctr reg in DAR */
587 rlwinm r10, r11, 24, 24, 28 /* offset into jump table for reg RB */
588 addi r10, r10, 150f@l /* add start of table */
589 mtctr r10 /* load ctr with jump address */
590 xor r10, r10, r10 /* sum starts at zero */
591 bctr /* jump into table */
593 add r10, r10, r0 ;b 151f
594 add r10, r10, r1 ;b 151f
595 add r10, r10, r2 ;b 151f
596 add r10, r10, r3 ;b 151f
597 add r10, r10, r4 ;b 151f
598 add r10, r10, r5 ;b 151f
599 add r10, r10, r6 ;b 151f
600 add r10, r10, r7 ;b 151f
601 add r10, r10, r8 ;b 151f
602 add r10, r10, r9 ;b 151f
603 mtctr r11 ;b 154f /* r10 needs special handling */
604 mtctr r11 ;b 153f /* r11 needs special handling */
605 add r10, r10, r12 ;b 151f
606 add r10, r10, r13 ;b 151f
607 add r10, r10, r14 ;b 151f
608 add r10, r10, r15 ;b 151f
609 add r10, r10, r16 ;b 151f
610 add r10, r10, r17 ;b 151f
611 add r10, r10, r18 ;b 151f
612 add r10, r10, r19 ;b 151f
613 add r10, r10, r20 ;b 151f
614 add r10, r10, r21 ;b 151f
615 add r10, r10, r22 ;b 151f
616 add r10, r10, r23 ;b 151f
617 add r10, r10, r24 ;b 151f
618 add r10, r10, r25 ;b 151f
619 add r10, r10, r26 ;b 151f
620 add r10, r10, r27 ;b 151f
621 add r10, r10, r28 ;b 151f
622 add r10, r10, r29 ;b 151f
623 add r10, r10, r30 ;b 151f
626 rlwinm. r11,r11,19,24,28 /* offset into jump table for reg RA */
627 beq 152f /* if reg RA is zero, don't add it */
628 addi r11, r11, 150b@l /* add start of table */
629 mtctr r11 /* load ctr with jump address */
630 rlwinm r11,r11,0,16,10 /* make sure we don't execute this more than once */
631 bctr /* jump into table */
634 mtctr r11 /* restore ctr reg from DAR */
635 mtdar r10 /* save fault EA to DAR */
636 mfspr r10,SPRN_SPRG_SCRATCH2
637 b DARFixed /* Go back to normal TLB handling */
639 /* special handling for r10,r11 since these are modified already */
640 153: mfspr r11, SPRN_SPRG_SCRATCH1 /* load r11 from SPRN_SPRG_SCRATCH1 */
641 add r10, r10, r11 /* add it */
642 mfctr r11 /* restore r11 */
644 154: mfspr r11, SPRN_SPRG_SCRATCH0 /* load r10 from SPRN_SPRG_SCRATCH0 */
645 add r10, r10, r11 /* add it */
646 mfctr r11 /* restore r11 */
651 * This is where the main kernel code starts.
656 ori r2,r2,init_task@l
658 /* ptr to phys current thread */
660 addi r4,r4,THREAD /* init task's THREAD */
661 mtspr SPRN_SPRG_THREAD,r4
664 lis r1,init_thread_union@ha
665 addi r1,r1,init_thread_union@l
667 stwu r0,THREAD_SIZE-STACK_FRAME_OVERHEAD(r1)
669 bl early_init /* We have to do this with MMU on */
672 * Decide what sort of machine this is and initialize the MMU.
680 * Go back to running unmapped so we can load up new values
681 * and change to using our exception vectors.
682 * On the 8xx, all we have to do is invalidate the TLB to clear
683 * the old 8M byte TLB mappings and load the page table base register.
685 /* The right way to do this would be to track it down through
686 * init's THREAD like the context switch code does, but this is
687 * easier......until someone changes init's static structures.
689 lis r6, swapper_pg_dir@ha
691 #ifdef CONFIG_8xx_CPU6
692 lis r4, cpu6_errata_word@h
693 ori r4, r4, cpu6_errata_word@l
702 li r3,MSR_KERNEL & ~(MSR_IR|MSR_DR)
706 /* Load up the kernel context */
708 SYNC /* Force all PTE updates to finish */
709 tlbia /* Clear all TLB entries */
710 sync /* wait for tlbia/tlbie to finish */
711 TLBSYNC /* ... on all CPUs */
713 /* set up the PTE pointers for the Abatron bdiGDB.
716 lis r5, abatron_pteptrs@h
717 ori r5, r5, abatron_pteptrs@l
718 stw r5, 0xf0(r0) /* Must match your Abatron config file */
722 /* Now turn on the MMU for real! */
724 lis r3,start_kernel@h
725 ori r3,r3,start_kernel@l
728 rfi /* enable MMU and jump to start_kernel */
730 /* Set up the initial MMU state so we can do the first level of
731 * kernel initialization. This maps the first 8 MBytes of memory 1:1
732 * virtual to physical. Also, set the cache mode since that is defined
733 * by TLB entries and perform any additional mapping (like of the IMMR).
734 * If configured to pin some TLBs, we pin the first 8 Mbytes of kernel,
735 * 24 Mbytes of data, and the 8M IMMR space. Anything not covered by
736 * these mappings is mapped by page tables.
739 tlbia /* Invalidate all TLB entries */
740 /* Always pin the first 8 MB ITLB to prevent ITLB
741 misses while mucking around with SRR0/SRR1 in asm
746 mtspr SPRN_MI_CTR, r8 /* Set instruction MMU control */
748 #ifdef CONFIG_PIN_TLB
749 lis r10, (MD_RSV4I | MD_RESETVAL)@h
753 lis r10, MD_RESETVAL@h
755 #ifndef CONFIG_8xx_COPYBACK
756 oris r10, r10, MD_WTDEF@h
758 mtspr SPRN_MD_CTR, r10 /* Set data TLB control */
760 /* Now map the lower 8 Meg into the TLBs. For this quick hack,
761 * we can load the instruction and data TLB registers with the
764 lis r8, KERNELBASE@h /* Create vaddr for TLB */
765 ori r8, r8, MI_EVALID /* Mark it valid */
766 mtspr SPRN_MI_EPN, r8
767 mtspr SPRN_MD_EPN, r8
768 li r8, MI_PS8MEG | (2 << 5) /* Set 8M byte page, APG 2 */
769 ori r8, r8, MI_SVALID /* Make it valid */
770 mtspr SPRN_MI_TWC, r8
771 li r8, MI_PS8MEG /* Set 8M byte page, APG 0 */
772 ori r8, r8, MI_SVALID /* Make it valid */
773 mtspr SPRN_MD_TWC, r8
774 li r8, MI_BOOTINIT /* Create RPN for address 0 */
775 mtspr SPRN_MI_RPN, r8 /* Store TLB entry */
776 mtspr SPRN_MD_RPN, r8
777 lis r8, MI_APG_INIT@h /* Set protection modes */
778 ori r8, r8, MI_APG_INIT@l
780 lis r8, MD_APG_INIT@h
781 ori r8, r8, MD_APG_INIT@l
784 /* Map another 8 MByte at the IMMR to get the processor
785 * internal registers (among other things).
787 #ifdef CONFIG_PIN_TLB
788 addi r10, r10, 0x0100
789 mtspr SPRN_MD_CTR, r10
791 mfspr r9, 638 /* Get current IMMR */
792 andis. r9, r9, 0xff80 /* Get 8Mbyte boundary */
794 mr r8, r9 /* Create vaddr for TLB */
795 ori r8, r8, MD_EVALID /* Mark it valid */
796 mtspr SPRN_MD_EPN, r8
797 li r8, MD_PS8MEG /* Set 8M byte page */
798 ori r8, r8, MD_SVALID /* Make it valid */
799 mtspr SPRN_MD_TWC, r8
800 mr r8, r9 /* Create paddr for TLB */
801 ori r8, r8, MI_BOOTINIT|0x2 /* Inhibit cache -- Cort */
802 mtspr SPRN_MD_RPN, r8
804 #ifdef CONFIG_PIN_TLB
805 /* Map two more 8M kernel data pages.
807 addi r10, r10, 0x0100
808 mtspr SPRN_MD_CTR, r10
810 lis r8, KERNELBASE@h /* Create vaddr for TLB */
811 addis r8, r8, 0x0080 /* Add 8M */
812 ori r8, r8, MI_EVALID /* Mark it valid */
813 mtspr SPRN_MD_EPN, r8
814 li r9, MI_PS8MEG /* Set 8M byte page */
815 ori r9, r9, MI_SVALID /* Make it valid */
816 mtspr SPRN_MD_TWC, r9
817 li r11, MI_BOOTINIT /* Create RPN for address 0 */
818 addis r11, r11, 0x0080 /* Add 8M */
819 mtspr SPRN_MD_RPN, r11
821 addi r10, r10, 0x0100
822 mtspr SPRN_MD_CTR, r10
824 addis r8, r8, 0x0080 /* Add 8M */
825 mtspr SPRN_MD_EPN, r8
826 mtspr SPRN_MD_TWC, r9
827 addis r11, r11, 0x0080 /* Add 8M */
828 mtspr SPRN_MD_RPN, r11
831 /* Since the cache is enabled according to the information we
832 * just loaded into the TLB, invalidate and enable the caches here.
833 * We should probably check/set other modes....later.
836 mtspr SPRN_IC_CST, r8
837 mtspr SPRN_DC_CST, r8
839 mtspr SPRN_IC_CST, r8
840 #ifdef CONFIG_8xx_COPYBACK
841 mtspr SPRN_DC_CST, r8
843 /* For a debug option, I left this here to easily enable
844 * the write through cache mode
847 mtspr SPRN_DC_CST, r8
849 mtspr SPRN_DC_CST, r8
855 * Set up to use a given MMU context.
856 * r3 is context number, r4 is PGD pointer.
858 * We place the physical address of the new task page directory loaded
859 * into the MMU base register, and set the ASID compare register with
864 #ifdef CONFIG_BDI_SWITCH
865 /* Context switch the PTE pointer for the Abatron BDI2000.
866 * The PGDIR is passed as second argument.
873 /* Register M_TW will contain base address of level 1 table minus the
874 * lower part of the kernel PGDIR base address, so that all accesses to
875 * level 1 table are done relative to lower part of kernel PGDIR base
878 li r5, (swapper_pg_dir-PAGE_OFFSET)@l
881 #ifdef CONFIG_8xx_CPU6
882 lis r6, cpu6_errata_word@h
883 ori r6, r6, cpu6_errata_word@l
888 mtspr SPRN_M_TW, r4 /* Update pointeur to level 1 table */
889 #ifdef CONFIG_8xx_CPU6
894 mtspr SPRN_M_CASID, r3 /* Update context */
898 #ifdef CONFIG_8xx_CPU6
899 /* It's here because it is unique to the 8xx.
900 * It is important we get called with interrupts disabled. I used to
901 * do that, but it appears that all code that calls this already had
902 * interrupt disabled.
906 lis r7, cpu6_errata_word@h
907 ori r7, r7, cpu6_errata_word@l
911 mtspr 22, r3 /* Update Decrementer */
917 * We put a few things here that have to be page-aligned.
918 * This stuff goes at the beginning of the data segment,
919 * which is page-aligned.
924 .globl empty_zero_page
929 .globl swapper_pg_dir
931 .space PGD_TABLE_SIZE
933 /* Room for two PTE table poiners, usually the kernel and current user
934 * pointer to their respective root page table (pgdir).
939 #ifdef CONFIG_8xx_CPU6
940 .globl cpu6_errata_word