2 * Local APIC handling, local APIC timers
4 * (c) 1999, 2000 Ingo Molnar <mingo@redhat.com>
7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
8 * thanks to Eric Gilmore
10 * for testing these extensively.
11 * Maciej W. Rozycki : Various updates and fixes.
12 * Mikael Pettersson : Power Management for UP-APIC.
14 * Mikael Pettersson : PM converted to driver model.
17 #include <linux/init.h>
20 #include <linux/delay.h>
21 #include <linux/bootmem.h>
22 #include <linux/interrupt.h>
23 #include <linux/mc146818rtc.h>
24 #include <linux/kernel_stat.h>
25 #include <linux/sysdev.h>
26 #include <linux/ioport.h>
27 #include <linux/clockchips.h>
28 #include <linux/acpi_pmtmr.h>
29 #include <linux/module.h>
31 #include <asm/atomic.h>
34 #include <asm/mpspec.h>
36 #include <asm/pgalloc.h>
39 #include <asm/proto.h>
40 #include <asm/timex.h>
44 #include <mach_apic.h>
46 int disable_apic_timer __cpuinitdata;
47 static int apic_calibrate_pmtmr __initdata;
50 /* Local APIC timer works in C2 */
51 int local_apic_timer_c2_ok;
52 EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok);
55 * Debug level, exported for io_apic.c
59 static struct resource lapic_resource = {
61 .flags = IORESOURCE_MEM | IORESOURCE_BUSY,
64 static unsigned int calibration_result;
66 static int lapic_next_event(unsigned long delta,
67 struct clock_event_device *evt);
68 static void lapic_timer_setup(enum clock_event_mode mode,
69 struct clock_event_device *evt);
70 static void lapic_timer_broadcast(cpumask_t mask);
71 static void apic_pm_activate(void);
73 static struct clock_event_device lapic_clockevent = {
75 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT
76 | CLOCK_EVT_FEAT_C3STOP | CLOCK_EVT_FEAT_DUMMY,
78 .set_mode = lapic_timer_setup,
79 .set_next_event = lapic_next_event,
80 .broadcast = lapic_timer_broadcast,
84 static DEFINE_PER_CPU(struct clock_event_device, lapic_events);
86 static unsigned long apic_phys;
88 unsigned long mp_lapic_addr;
90 unsigned int __cpuinitdata maxcpus = NR_CPUS;
92 * Get the LAPIC version
94 static inline int lapic_get_version(void)
96 return GET_APIC_VERSION(apic_read(APIC_LVR));
100 * Check, if the APIC is integrated or a seperate chip
102 static inline int lapic_is_integrated(void)
108 * Check, whether this is a modern or a first generation APIC
110 static int modern_apic(void)
112 /* AMD systems use old APIC versions, so check the CPU */
113 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD &&
114 boot_cpu_data.x86 >= 0xf)
116 return lapic_get_version() >= 0x14;
119 void apic_wait_icr_idle(void)
121 while (apic_read(APIC_ICR) & APIC_ICR_BUSY)
125 u32 safe_apic_wait_icr_idle(void)
132 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
136 } while (timeout++ < 1000);
142 * enable_NMI_through_LVT0 - enable NMI through local vector table 0
144 void __cpuinit enable_NMI_through_LVT0(void)
148 /* unmask and set to NMI */
150 apic_write(APIC_LVT0, v);
154 * lapic_get_maxlvt - get the maximum number of local vector table entries
156 int lapic_get_maxlvt(void)
158 unsigned int v, maxlvt;
160 v = apic_read(APIC_LVR);
161 maxlvt = GET_APIC_MAXLVT(v);
166 * This function sets up the local APIC timer, with a timeout of
167 * 'clocks' APIC bus clock. During calibration we actually call
168 * this function twice on the boot CPU, once with a bogus timeout
169 * value, second time for real. The other (noncalibrating) CPUs
170 * call this function only once, with the real, calibrated value.
172 * We do reads before writes even if unnecessary, to get around the
173 * P5 APIC double write bug.
176 static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen)
178 unsigned int lvtt_value, tmp_value;
180 lvtt_value = LOCAL_TIMER_VECTOR;
182 lvtt_value |= APIC_LVT_TIMER_PERIODIC;
184 lvtt_value |= APIC_LVT_MASKED;
186 apic_write(APIC_LVTT, lvtt_value);
191 tmp_value = apic_read(APIC_TDCR);
192 apic_write(APIC_TDCR, (tmp_value
193 & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE))
197 apic_write(APIC_TMICT, clocks);
201 * Setup extended LVT, AMD specific (K8, family 10h)
203 * Vector mappings are hard coded. On K8 only offset 0 (APIC500) and
204 * MCE interrupts are supported. Thus MCE offset must be set to 0.
207 #define APIC_EILVT_LVTOFF_MCE 0
208 #define APIC_EILVT_LVTOFF_IBS 1
210 static void setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask)
212 unsigned long reg = (lvt_off << 4) + APIC_EILVT0;
213 unsigned int v = (mask << 16) | (msg_type << 8) | vector;
218 u8 setup_APIC_eilvt_mce(u8 vector, u8 msg_type, u8 mask)
220 setup_APIC_eilvt(APIC_EILVT_LVTOFF_MCE, vector, msg_type, mask);
221 return APIC_EILVT_LVTOFF_MCE;
224 u8 setup_APIC_eilvt_ibs(u8 vector, u8 msg_type, u8 mask)
226 setup_APIC_eilvt(APIC_EILVT_LVTOFF_IBS, vector, msg_type, mask);
227 return APIC_EILVT_LVTOFF_IBS;
231 * Program the next event, relative to now
233 static int lapic_next_event(unsigned long delta,
234 struct clock_event_device *evt)
236 apic_write(APIC_TMICT, delta);
241 * Setup the lapic timer in periodic or oneshot mode
243 static void lapic_timer_setup(enum clock_event_mode mode,
244 struct clock_event_device *evt)
249 /* Lapic used as dummy for broadcast ? */
250 if (evt->features & CLOCK_EVT_FEAT_DUMMY)
253 local_irq_save(flags);
256 case CLOCK_EVT_MODE_PERIODIC:
257 case CLOCK_EVT_MODE_ONESHOT:
258 __setup_APIC_LVTT(calibration_result,
259 mode != CLOCK_EVT_MODE_PERIODIC, 1);
261 case CLOCK_EVT_MODE_UNUSED:
262 case CLOCK_EVT_MODE_SHUTDOWN:
263 v = apic_read(APIC_LVTT);
264 v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
265 apic_write(APIC_LVTT, v);
267 case CLOCK_EVT_MODE_RESUME:
268 /* Nothing to do here */
272 local_irq_restore(flags);
276 * Local APIC timer broadcast function
278 static void lapic_timer_broadcast(cpumask_t mask)
281 send_IPI_mask(mask, LOCAL_TIMER_VECTOR);
286 * Setup the local APIC timer for this CPU. Copy the initilized values
287 * of the boot CPU and register the clock event in the framework.
289 static void setup_APIC_timer(void)
291 struct clock_event_device *levt = &__get_cpu_var(lapic_events);
293 memcpy(levt, &lapic_clockevent, sizeof(*levt));
294 levt->cpumask = cpumask_of_cpu(smp_processor_id());
296 clockevents_register_device(levt);
300 * In this function we calibrate APIC bus clocks to the external
301 * timer. Unfortunately we cannot use jiffies and the timer irq
302 * to calibrate, since some later bootup code depends on getting
303 * the first irq? Ugh.
305 * We want to do the calibration only once since we
306 * want to have local timer irqs syncron. CPUs connected
307 * by the same APIC bus have the very same bus frequency.
308 * And we want to have irqs off anyways, no accidental
312 #define TICK_COUNT 100000000
314 static void __init calibrate_APIC_clock(void)
316 unsigned apic, apic_start;
317 unsigned long tsc, tsc_start;
323 * Put whatever arbitrary (but long enough) timeout
324 * value into the APIC clock, we just want to get the
325 * counter running for calibration.
327 * No interrupt enable !
329 __setup_APIC_LVTT(250000000, 0, 0);
331 apic_start = apic_read(APIC_TMCCT);
332 #ifdef CONFIG_X86_PM_TIMER
333 if (apic_calibrate_pmtmr && pmtmr_ioport) {
334 pmtimer_wait(5000); /* 5ms wait */
335 apic = apic_read(APIC_TMCCT);
336 result = (apic_start - apic) * 1000L / 5;
343 apic = apic_read(APIC_TMCCT);
345 } while ((tsc - tsc_start) < TICK_COUNT &&
346 (apic_start - apic) < TICK_COUNT);
348 result = (apic_start - apic) * 1000L * tsc_khz /
354 printk(KERN_DEBUG "APIC timer calibration result %d\n", result);
356 printk(KERN_INFO "Detected %d.%03d MHz APIC timer.\n",
357 result / 1000 / 1000, result / 1000 % 1000);
359 /* Calculate the scaled math multiplication factor */
360 lapic_clockevent.mult = div_sc(result, NSEC_PER_SEC,
361 lapic_clockevent.shift);
362 lapic_clockevent.max_delta_ns =
363 clockevent_delta2ns(0x7FFFFF, &lapic_clockevent);
364 lapic_clockevent.min_delta_ns =
365 clockevent_delta2ns(0xF, &lapic_clockevent);
367 calibration_result = result / HZ;
371 * Setup the boot APIC
373 * Calibrate and verify the result.
375 void __init setup_boot_APIC_clock(void)
378 * The local apic timer can be disabled via the kernel commandline.
379 * Register the lapic timer as a dummy clock event source on SMP
380 * systems, so the broadcast mechanism is used. On UP systems simply
383 if (disable_apic_timer) {
384 printk(KERN_INFO "Disabling APIC timer\n");
385 /* No broadcast on UP ! */
386 if (num_possible_cpus() > 1) {
387 lapic_clockevent.mult = 1;
393 printk(KERN_INFO "Using local APIC timer interrupts.\n");
394 calibrate_APIC_clock();
397 * Do a sanity check on the APIC calibration result
399 if (calibration_result < (1000000 / HZ)) {
401 "APIC frequency too slow, disabling apic timer\n");
402 /* No broadcast on UP ! */
403 if (num_possible_cpus() > 1)
409 * If nmi_watchdog is set to IO_APIC, we need the
410 * PIT/HPET going. Otherwise register lapic as a dummy
413 if (nmi_watchdog != NMI_IO_APIC)
414 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY;
416 printk(KERN_WARNING "APIC timer registered as dummy,"
417 " due to nmi_watchdog=1!\n");
423 * AMD C1E enabled CPUs have a real nasty problem: Some BIOSes set the
424 * C1E flag only in the secondary CPU, so when we detect the wreckage
425 * we already have enabled the boot CPU local apic timer. Check, if
426 * disable_apic_timer is set and the DUMMY flag is cleared. If yes,
427 * set the DUMMY flag again and force the broadcast mode in the
430 static void __cpuinit check_boot_apic_timer_broadcast(void)
432 if (!disable_apic_timer ||
433 (lapic_clockevent.features & CLOCK_EVT_FEAT_DUMMY))
436 printk(KERN_INFO "AMD C1E detected late. Force timer broadcast.\n");
437 lapic_clockevent.features |= CLOCK_EVT_FEAT_DUMMY;
440 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_FORCE,
441 &boot_cpu_physical_apicid);
445 void __cpuinit setup_secondary_APIC_clock(void)
447 check_boot_apic_timer_broadcast();
452 * The guts of the apic timer interrupt
454 static void local_apic_timer_interrupt(void)
456 int cpu = smp_processor_id();
457 struct clock_event_device *evt = &per_cpu(lapic_events, cpu);
460 * Normally we should not be here till LAPIC has been initialized but
461 * in some cases like kdump, its possible that there is a pending LAPIC
462 * timer interrupt from previous kernel's context and is delivered in
463 * new kernel the moment interrupts are enabled.
465 * Interrupts are enabled early and LAPIC is setup much later, hence
466 * its possible that when we get here evt->event_handler is NULL.
467 * Check for event_handler being NULL and discard the interrupt as
470 if (!evt->event_handler) {
472 "Spurious LAPIC timer interrupt on cpu %d\n", cpu);
474 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, evt);
479 * the NMI deadlock-detector uses this.
481 add_pda(apic_timer_irqs, 1);
483 evt->event_handler(evt);
487 * Local APIC timer interrupt. This is the most natural way for doing
488 * local interrupts, but local timer interrupts can be emulated by
489 * broadcast interrupts too. [in case the hw doesn't support APIC timers]
491 * [ if a single-CPU system runs an SMP kernel then we call the local
492 * interrupt as well. Thus we cannot inline the local irq ... ]
494 void smp_apic_timer_interrupt(struct pt_regs *regs)
496 struct pt_regs *old_regs = set_irq_regs(regs);
499 * NOTE! We'd better ACK the irq immediately,
500 * because timer handling can be slow.
504 * update_process_times() expects us to have done irq_enter().
505 * Besides, if we don't timer interrupts ignore the global
506 * interrupt lock, which is the WrongThing (tm) to do.
510 local_apic_timer_interrupt();
512 set_irq_regs(old_regs);
515 int setup_profiling_timer(unsigned int multiplier)
522 * Local APIC start and shutdown
526 * clear_local_APIC - shutdown the local APIC
528 * This is called, when a CPU is disabled and before rebooting, so the state of
529 * the local APIC has no dangling leftovers. Also used to cleanout any BIOS
530 * leftovers during boot.
532 void clear_local_APIC(void)
537 /* APIC hasn't been mapped yet */
541 maxlvt = lapic_get_maxlvt();
543 * Masking an LVT entry can trigger a local APIC error
544 * if the vector is zero. Mask LVTERR first to prevent this.
547 v = ERROR_APIC_VECTOR; /* any non-zero vector will do */
548 apic_write(APIC_LVTERR, v | APIC_LVT_MASKED);
551 * Careful: we have to set masks only first to deassert
552 * any level-triggered sources.
554 v = apic_read(APIC_LVTT);
555 apic_write(APIC_LVTT, v | APIC_LVT_MASKED);
556 v = apic_read(APIC_LVT0);
557 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
558 v = apic_read(APIC_LVT1);
559 apic_write(APIC_LVT1, v | APIC_LVT_MASKED);
561 v = apic_read(APIC_LVTPC);
562 apic_write(APIC_LVTPC, v | APIC_LVT_MASKED);
566 * Clean APIC state for other OSs:
568 apic_write(APIC_LVTT, APIC_LVT_MASKED);
569 apic_write(APIC_LVT0, APIC_LVT_MASKED);
570 apic_write(APIC_LVT1, APIC_LVT_MASKED);
572 apic_write(APIC_LVTERR, APIC_LVT_MASKED);
574 apic_write(APIC_LVTPC, APIC_LVT_MASKED);
575 apic_write(APIC_ESR, 0);
580 * disable_local_APIC - clear and disable the local APIC
582 void disable_local_APIC(void)
589 * Disable APIC (implies clearing of registers
592 value = apic_read(APIC_SPIV);
593 value &= ~APIC_SPIV_APIC_ENABLED;
594 apic_write(APIC_SPIV, value);
597 void lapic_shutdown(void)
604 local_irq_save(flags);
606 disable_local_APIC();
608 local_irq_restore(flags);
612 * This is to verify that we're looking at a real local APIC.
613 * Check these against your board if the CPUs aren't getting
614 * started for no apparent reason.
616 int __init verify_local_APIC(void)
618 unsigned int reg0, reg1;
621 * The version register is read-only in a real APIC.
623 reg0 = apic_read(APIC_LVR);
624 apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg0);
625 apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK);
626 reg1 = apic_read(APIC_LVR);
627 apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg1);
630 * The two version reads above should print the same
631 * numbers. If the second one is different, then we
632 * poke at a non-APIC.
638 * Check if the version looks reasonably.
640 reg1 = GET_APIC_VERSION(reg0);
641 if (reg1 == 0x00 || reg1 == 0xff)
643 reg1 = lapic_get_maxlvt();
644 if (reg1 < 0x02 || reg1 == 0xff)
648 * The ID register is read/write in a real APIC.
650 reg0 = read_apic_id();
651 apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg0);
652 apic_write(APIC_ID, reg0 ^ APIC_ID_MASK);
653 reg1 = read_apic_id();
654 apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg1);
655 apic_write(APIC_ID, reg0);
656 if (reg1 != (reg0 ^ APIC_ID_MASK))
660 * The next two are just to see if we have sane values.
661 * They're only really relevant if we're in Virtual Wire
662 * compatibility mode, but most boxes are anymore.
664 reg0 = apic_read(APIC_LVT0);
665 apic_printk(APIC_DEBUG, "Getting LVT0: %x\n", reg0);
666 reg1 = apic_read(APIC_LVT1);
667 apic_printk(APIC_DEBUG, "Getting LVT1: %x\n", reg1);
673 * sync_Arb_IDs - synchronize APIC bus arbitration IDs
675 void __init sync_Arb_IDs(void)
677 /* Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 */
684 apic_wait_icr_idle();
686 apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n");
687 apic_write(APIC_ICR, APIC_DEST_ALLINC | APIC_INT_LEVELTRIG
692 * An initial setup of the virtual wire mode.
694 void __init init_bsp_APIC(void)
699 * Don't do the setup now if we have a SMP BIOS as the
700 * through-I/O-APIC virtual wire mode might be active.
702 if (smp_found_config || !cpu_has_apic)
705 value = apic_read(APIC_LVR);
708 * Do not trust the local APIC being empty at bootup.
715 value = apic_read(APIC_SPIV);
716 value &= ~APIC_VECTOR_MASK;
717 value |= APIC_SPIV_APIC_ENABLED;
718 value |= APIC_SPIV_FOCUS_DISABLED;
719 value |= SPURIOUS_APIC_VECTOR;
720 apic_write(APIC_SPIV, value);
723 * Set up the virtual wire mode.
725 apic_write(APIC_LVT0, APIC_DM_EXTINT);
727 apic_write(APIC_LVT1, value);
731 * setup_local_APIC - setup the local APIC
733 void __cpuinit setup_local_APIC(void)
739 value = apic_read(APIC_LVR);
741 BUILD_BUG_ON((SPURIOUS_APIC_VECTOR & 0x0f) != 0x0f);
744 * Double-check whether this APIC is really registered.
745 * This is meaningless in clustered apic mode, so we skip it.
747 if (!apic_id_registered())
751 * Intel recommends to set DFR, LDR and TPR before enabling
752 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
753 * document number 292116). So here it goes...
758 * Set Task Priority to 'accept all'. We never change this
761 value = apic_read(APIC_TASKPRI);
762 value &= ~APIC_TPRI_MASK;
763 apic_write(APIC_TASKPRI, value);
766 * After a crash, we no longer service the interrupts and a pending
767 * interrupt from previous kernel might still have ISR bit set.
769 * Most probably by now CPU has serviced that pending interrupt and
770 * it might not have done the ack_APIC_irq() because it thought,
771 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
772 * does not clear the ISR bit and cpu thinks it has already serivced
773 * the interrupt. Hence a vector might get locked. It was noticed
774 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
776 for (i = APIC_ISR_NR - 1; i >= 0; i--) {
777 value = apic_read(APIC_ISR + i*0x10);
778 for (j = 31; j >= 0; j--) {
785 * Now that we are all set up, enable the APIC
787 value = apic_read(APIC_SPIV);
788 value &= ~APIC_VECTOR_MASK;
792 value |= APIC_SPIV_APIC_ENABLED;
794 /* We always use processor focus */
797 * Set spurious IRQ vector
799 value |= SPURIOUS_APIC_VECTOR;
800 apic_write(APIC_SPIV, value);
805 * set up through-local-APIC on the BP's LINT0. This is not
806 * strictly necessary in pure symmetric-IO mode, but sometimes
807 * we delegate interrupts to the 8259A.
810 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
812 value = apic_read(APIC_LVT0) & APIC_LVT_MASKED;
813 if (!smp_processor_id() && !value) {
814 value = APIC_DM_EXTINT;
815 apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n",
818 value = APIC_DM_EXTINT | APIC_LVT_MASKED;
819 apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n",
822 apic_write(APIC_LVT0, value);
825 * only the BP should see the LINT1 NMI signal, obviously.
827 if (!smp_processor_id())
830 value = APIC_DM_NMI | APIC_LVT_MASKED;
831 apic_write(APIC_LVT1, value);
835 static void __cpuinit lapic_setup_esr(void)
837 unsigned maxlvt = lapic_get_maxlvt();
839 apic_write(APIC_LVTERR, ERROR_APIC_VECTOR);
841 * spec says clear errors after enabling vector.
844 apic_write(APIC_ESR, 0);
847 void __cpuinit end_local_APIC_setup(void)
850 nmi_watchdog_default();
851 setup_apic_nmi_watchdog(NULL);
856 * Detect and enable local APICs on non-SMP boards.
857 * Original code written by Keir Fraser.
858 * On AMD64 we trust the BIOS - if it says no APIC it is likely
859 * not correctly set up (usually the APIC timer won't work etc.)
861 static int __init detect_init_APIC(void)
864 printk(KERN_INFO "No local APIC present\n");
868 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
869 boot_cpu_physical_apicid = 0;
873 void __init early_init_lapic_mapping(void)
875 unsigned long apic_phys;
878 * If no local APIC can be found then go out
879 * : it means there is no mpatable and MADT
881 if (!smp_found_config)
884 apic_phys = mp_lapic_addr;
886 set_fixmap_nocache(FIX_APIC_BASE, apic_phys);
887 apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n",
888 APIC_BASE, apic_phys);
891 * Fetch the APIC ID of the BSP in case we have a
892 * default configuration (or the MP table is broken).
894 boot_cpu_physical_apicid = GET_APIC_ID(read_apic_id());
898 * init_apic_mappings - initialize APIC mappings
900 void __init init_apic_mappings(void)
903 * If no local APIC can be found then set up a fake all
904 * zeroes page to simulate the local APIC and another
905 * one for the IO-APIC.
907 if (!smp_found_config && detect_init_APIC()) {
908 apic_phys = (unsigned long) alloc_bootmem_pages(PAGE_SIZE);
909 apic_phys = __pa(apic_phys);
911 apic_phys = mp_lapic_addr;
913 set_fixmap_nocache(FIX_APIC_BASE, apic_phys);
914 apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n",
915 APIC_BASE, apic_phys);
918 * Fetch the APIC ID of the BSP in case we have a
919 * default configuration (or the MP table is broken).
921 boot_cpu_physical_apicid = GET_APIC_ID(read_apic_id());
925 * This initializes the IO-APIC and APIC hardware if this is
928 int __init APIC_init_uniprocessor(void)
931 printk(KERN_INFO "Apic disabled\n");
936 printk(KERN_INFO "Apic disabled by BIOS\n");
942 phys_cpu_present_map = physid_mask_of_physid(boot_cpu_physical_apicid);
943 apic_write(APIC_ID, SET_APIC_ID(boot_cpu_physical_apicid));
948 * Now enable IO-APICs, actually call clear_IO_APIC
949 * We need clear_IO_APIC before enabling vector on BP
951 if (!skip_ioapic_setup && nr_ioapics)
954 end_local_APIC_setup();
956 if (smp_found_config && !skip_ioapic_setup && nr_ioapics)
960 setup_boot_APIC_clock();
961 check_nmi_watchdog();
966 * Local APIC interrupts
970 * This interrupt should _never_ happen with our APIC/SMP architecture
972 asmlinkage void smp_spurious_interrupt(void)
978 * Check if this really is a spurious interrupt and ACK it
979 * if it is a vectored one. Just in case...
980 * Spurious interrupts should not be ACKed.
982 v = apic_read(APIC_ISR + ((SPURIOUS_APIC_VECTOR & ~0x1f) >> 1));
983 if (v & (1 << (SPURIOUS_APIC_VECTOR & 0x1f)))
986 add_pda(irq_spurious_count, 1);
991 * This interrupt should never happen with our APIC/SMP architecture
993 asmlinkage void smp_error_interrupt(void)
999 /* First tickle the hardware, only then report what went on. -- REW */
1000 v = apic_read(APIC_ESR);
1001 apic_write(APIC_ESR, 0);
1002 v1 = apic_read(APIC_ESR);
1004 atomic_inc(&irq_err_count);
1006 /* Here is what the APIC error bits mean:
1009 2: Send accept error
1010 3: Receive accept error
1012 5: Send illegal vector
1013 6: Received illegal vector
1014 7: Illegal register address
1016 printk(KERN_DEBUG "APIC error on CPU%d: %02x(%02x)\n",
1017 smp_processor_id(), v , v1);
1021 void disconnect_bsp_APIC(int virt_wire_setup)
1023 /* Go back to Virtual Wire compatibility mode */
1024 unsigned long value;
1026 /* For the spurious interrupt use vector F, and enable it */
1027 value = apic_read(APIC_SPIV);
1028 value &= ~APIC_VECTOR_MASK;
1029 value |= APIC_SPIV_APIC_ENABLED;
1031 apic_write(APIC_SPIV, value);
1033 if (!virt_wire_setup) {
1035 * For LVT0 make it edge triggered, active high,
1036 * external and enabled
1038 value = apic_read(APIC_LVT0);
1039 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
1040 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
1041 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
1042 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
1043 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT);
1044 apic_write(APIC_LVT0, value);
1047 apic_write(APIC_LVT0, APIC_LVT_MASKED);
1050 /* For LVT1 make it edge triggered, active high, nmi and enabled */
1051 value = apic_read(APIC_LVT1);
1052 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
1053 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
1054 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
1055 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
1056 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI);
1057 apic_write(APIC_LVT1, value);
1060 void __cpuinit generic_processor_info(int apicid, int version)
1065 if (num_processors >= NR_CPUS) {
1066 printk(KERN_WARNING "WARNING: NR_CPUS limit of %i reached."
1067 " Processor ignored.\n", NR_CPUS);
1071 if (num_processors >= maxcpus) {
1072 printk(KERN_WARNING "WARNING: maxcpus limit of %i reached."
1073 " Processor ignored.\n", maxcpus);
1078 cpus_complement(tmp_map, cpu_present_map);
1079 cpu = first_cpu(tmp_map);
1081 physid_set(apicid, phys_cpu_present_map);
1082 if (apicid == boot_cpu_physical_apicid) {
1084 * x86_bios_cpu_apicid is required to have processors listed
1085 * in same order as logical cpu numbers. Hence the first
1086 * entry is BSP, and so on.
1090 /* are we being called early in kernel startup? */
1091 if (early_per_cpu_ptr(x86_cpu_to_apicid)) {
1092 u16 *cpu_to_apicid = early_per_cpu_ptr(x86_cpu_to_apicid);
1093 u16 *bios_cpu_apicid = early_per_cpu_ptr(x86_bios_cpu_apicid);
1095 cpu_to_apicid[cpu] = apicid;
1096 bios_cpu_apicid[cpu] = apicid;
1098 per_cpu(x86_cpu_to_apicid, cpu) = apicid;
1099 per_cpu(x86_bios_cpu_apicid, cpu) = apicid;
1102 cpu_set(cpu, cpu_possible_map);
1103 cpu_set(cpu, cpu_present_map);
1112 /* 'active' is true if the local APIC was enabled by us and
1113 not the BIOS; this signifies that we are also responsible
1114 for disabling it before entering apm/acpi suspend */
1116 /* r/w apic fields */
1117 unsigned int apic_id;
1118 unsigned int apic_taskpri;
1119 unsigned int apic_ldr;
1120 unsigned int apic_dfr;
1121 unsigned int apic_spiv;
1122 unsigned int apic_lvtt;
1123 unsigned int apic_lvtpc;
1124 unsigned int apic_lvt0;
1125 unsigned int apic_lvt1;
1126 unsigned int apic_lvterr;
1127 unsigned int apic_tmict;
1128 unsigned int apic_tdcr;
1129 unsigned int apic_thmr;
1132 static int lapic_suspend(struct sys_device *dev, pm_message_t state)
1134 unsigned long flags;
1137 if (!apic_pm_state.active)
1140 maxlvt = lapic_get_maxlvt();
1142 apic_pm_state.apic_id = read_apic_id();
1143 apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI);
1144 apic_pm_state.apic_ldr = apic_read(APIC_LDR);
1145 apic_pm_state.apic_dfr = apic_read(APIC_DFR);
1146 apic_pm_state.apic_spiv = apic_read(APIC_SPIV);
1147 apic_pm_state.apic_lvtt = apic_read(APIC_LVTT);
1149 apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC);
1150 apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0);
1151 apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1);
1152 apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR);
1153 apic_pm_state.apic_tmict = apic_read(APIC_TMICT);
1154 apic_pm_state.apic_tdcr = apic_read(APIC_TDCR);
1155 #ifdef CONFIG_X86_MCE_INTEL
1157 apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR);
1159 local_irq_save(flags);
1160 disable_local_APIC();
1161 local_irq_restore(flags);
1165 static int lapic_resume(struct sys_device *dev)
1168 unsigned long flags;
1171 if (!apic_pm_state.active)
1174 maxlvt = lapic_get_maxlvt();
1176 local_irq_save(flags);
1177 rdmsr(MSR_IA32_APICBASE, l, h);
1178 l &= ~MSR_IA32_APICBASE_BASE;
1179 l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr;
1180 wrmsr(MSR_IA32_APICBASE, l, h);
1181 apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED);
1182 apic_write(APIC_ID, apic_pm_state.apic_id);
1183 apic_write(APIC_DFR, apic_pm_state.apic_dfr);
1184 apic_write(APIC_LDR, apic_pm_state.apic_ldr);
1185 apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri);
1186 apic_write(APIC_SPIV, apic_pm_state.apic_spiv);
1187 apic_write(APIC_LVT0, apic_pm_state.apic_lvt0);
1188 apic_write(APIC_LVT1, apic_pm_state.apic_lvt1);
1189 #ifdef CONFIG_X86_MCE_INTEL
1191 apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr);
1194 apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc);
1195 apic_write(APIC_LVTT, apic_pm_state.apic_lvtt);
1196 apic_write(APIC_TDCR, apic_pm_state.apic_tdcr);
1197 apic_write(APIC_TMICT, apic_pm_state.apic_tmict);
1198 apic_write(APIC_ESR, 0);
1199 apic_read(APIC_ESR);
1200 apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr);
1201 apic_write(APIC_ESR, 0);
1202 apic_read(APIC_ESR);
1203 local_irq_restore(flags);
1207 static struct sysdev_class lapic_sysclass = {
1209 .resume = lapic_resume,
1210 .suspend = lapic_suspend,
1213 static struct sys_device device_lapic = {
1215 .cls = &lapic_sysclass,
1218 static void __cpuinit apic_pm_activate(void)
1220 apic_pm_state.active = 1;
1223 static int __init init_lapic_sysfs(void)
1229 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */
1231 error = sysdev_class_register(&lapic_sysclass);
1233 error = sysdev_register(&device_lapic);
1236 device_initcall(init_lapic_sysfs);
1238 #else /* CONFIG_PM */
1240 static void apic_pm_activate(void) { }
1242 #endif /* CONFIG_PM */
1245 * apic_is_clustered_box() -- Check if we can expect good TSC
1247 * Thus far, the major user of this is IBM's Summit2 series:
1249 * Clustered boxes may have unsynced TSC problems if they are
1250 * multi-chassis. Use available data to take a good guess.
1251 * If in doubt, go HPET.
1253 __cpuinit int apic_is_clustered_box(void)
1255 int i, clusters, zeros;
1257 u16 *bios_cpu_apicid;
1258 DECLARE_BITMAP(clustermap, NUM_APIC_CLUSTERS);
1261 * there is not this kind of box with AMD CPU yet.
1262 * Some AMD box with quadcore cpu and 8 sockets apicid
1263 * will be [4, 0x23] or [8, 0x27] could be thought to
1264 * vsmp box still need checking...
1266 if ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) && !is_vsmp_box())
1269 bios_cpu_apicid = early_per_cpu_ptr(x86_bios_cpu_apicid);
1270 bitmap_zero(clustermap, NUM_APIC_CLUSTERS);
1272 for (i = 0; i < NR_CPUS; i++) {
1273 /* are we being called early in kernel startup? */
1274 if (bios_cpu_apicid) {
1275 id = bios_cpu_apicid[i];
1277 else if (i < nr_cpu_ids) {
1279 id = per_cpu(x86_bios_cpu_apicid, i);
1286 if (id != BAD_APICID)
1287 __set_bit(APIC_CLUSTERID(id), clustermap);
1290 /* Problem: Partially populated chassis may not have CPUs in some of
1291 * the APIC clusters they have been allocated. Only present CPUs have
1292 * x86_bios_cpu_apicid entries, thus causing zeroes in the bitmap.
1293 * Since clusters are allocated sequentially, count zeros only if
1294 * they are bounded by ones.
1298 for (i = 0; i < NUM_APIC_CLUSTERS; i++) {
1299 if (test_bit(i, clustermap)) {
1300 clusters += 1 + zeros;
1306 /* ScaleMP vSMPowered boxes have one cluster per board and TSCs are
1307 * not guaranteed to be synced between boards
1309 if (is_vsmp_box() && clusters > 1)
1313 * If clusters > 2, then should be multi-chassis.
1314 * May have to revisit this when multi-core + hyperthreaded CPUs come
1315 * out, but AFAIK this will work even for them.
1317 return (clusters > 2);
1321 * APIC command line parameters
1323 static int __init apic_set_verbosity(char *str)
1326 skip_ioapic_setup = 0;
1330 if (strcmp("debug", str) == 0)
1331 apic_verbosity = APIC_DEBUG;
1332 else if (strcmp("verbose", str) == 0)
1333 apic_verbosity = APIC_VERBOSE;
1335 printk(KERN_WARNING "APIC Verbosity level %s not recognised"
1336 " use apic=verbose or apic=debug\n", str);
1342 early_param("apic", apic_set_verbosity);
1344 static __init int setup_disableapic(char *str)
1347 clear_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC);
1350 early_param("disableapic", setup_disableapic);
1352 /* same as disableapic, for compatibility */
1353 static __init int setup_nolapic(char *str)
1355 return setup_disableapic(str);
1357 early_param("nolapic", setup_nolapic);
1359 static int __init parse_lapic_timer_c2_ok(char *arg)
1361 local_apic_timer_c2_ok = 1;
1364 early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok);
1366 static __init int setup_noapictimer(char *str)
1368 if (str[0] != ' ' && str[0] != 0)
1370 disable_apic_timer = 1;
1373 __setup("noapictimer", setup_noapictimer);
1375 static __init int setup_apicpmtimer(char *s)
1377 apic_calibrate_pmtmr = 1;
1381 __setup("apicpmtimer", setup_apicpmtimer);
1383 static int __init lapic_insert_resource(void)
1388 /* Put local APIC into the resource map. */
1389 lapic_resource.start = apic_phys;
1390 lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1;
1391 insert_resource(&iomem_resource, &lapic_resource);
1397 * need call insert after e820_reserve_resources()
1398 * that is using request_resource
1400 late_initcall(lapic_insert_resource);