1 #include <linux/dma-mapping.h>
2 #include <linux/dma-debug.h>
3 #include <linux/dmar.h>
4 #include <linux/bootmem.h>
11 #include <asm/calgary.h>
12 #include <asm/amd_iommu.h>
14 static int forbid_dac __read_mostly;
16 struct dma_map_ops *dma_ops;
17 EXPORT_SYMBOL(dma_ops);
19 static int iommu_sac_force __read_mostly;
21 #ifdef CONFIG_IOMMU_DEBUG
22 int panic_on_overflow __read_mostly = 1;
23 int force_iommu __read_mostly = 1;
25 int panic_on_overflow __read_mostly = 0;
26 int force_iommu __read_mostly = 0;
29 int iommu_merge __read_mostly = 0;
31 int no_iommu __read_mostly;
32 /* Set this to 1 if there is a HW IOMMU in the system */
33 int iommu_detected __read_mostly = 0;
36 * This variable becomes 1 if iommu=pt is passed on the kernel command line.
37 * If this variable is 1, IOMMU implementations do no DMA ranslation for
38 * devices and allow every device to access to whole physical memory. This is
39 * useful if a user want to use an IOMMU only for KVM device assignment to
40 * guests and not for driver dma translation.
42 int iommu_pass_through __read_mostly;
44 dma_addr_t bad_dma_address __read_mostly = 0;
45 EXPORT_SYMBOL(bad_dma_address);
47 /* Dummy device used for NULL arguments (normally ISA). Better would
48 be probably a smaller DMA mask, but this is bug-to-bug compatible
50 struct device x86_dma_fallback_dev = {
51 .init_name = "fallback device",
52 .coherent_dma_mask = DMA_BIT_MASK(32),
53 .dma_mask = &x86_dma_fallback_dev.coherent_dma_mask,
55 EXPORT_SYMBOL(x86_dma_fallback_dev);
57 /* Number of entries preallocated for DMA-API debugging */
58 #define PREALLOC_DMA_DEBUG_ENTRIES 32768
60 int dma_set_mask(struct device *dev, u64 mask)
62 if (!dev->dma_mask || !dma_supported(dev, mask))
65 *dev->dma_mask = mask;
69 EXPORT_SYMBOL(dma_set_mask);
72 static __initdata void *dma32_bootmem_ptr;
73 static unsigned long dma32_bootmem_size __initdata = (128ULL<<20);
75 static int __init parse_dma32_size_opt(char *p)
79 dma32_bootmem_size = memparse(p, &p);
82 early_param("dma32_size", parse_dma32_size_opt);
84 void __init dma32_reserve_bootmem(void)
86 unsigned long size, align;
87 if (max_pfn <= MAX_DMA32_PFN)
91 * check aperture_64.c allocate_aperture() for reason about
95 size = roundup(dma32_bootmem_size, align);
96 dma32_bootmem_ptr = __alloc_bootmem_nopanic(size, align,
98 if (dma32_bootmem_ptr)
99 dma32_bootmem_size = size;
101 dma32_bootmem_size = 0;
103 static void __init dma32_free_bootmem(void)
106 if (max_pfn <= MAX_DMA32_PFN)
109 if (!dma32_bootmem_ptr)
112 free_bootmem(__pa(dma32_bootmem_ptr), dma32_bootmem_size);
114 dma32_bootmem_ptr = NULL;
115 dma32_bootmem_size = 0;
119 void __init pci_iommu_alloc(void)
122 /* free the range so iommu could get some range less than 4G */
123 dma32_free_bootmem();
127 * The order of these functions is important for
128 * fall-back/fail-over reasons
130 gart_iommu_hole_init();
134 detect_intel_iommu();
141 void *dma_generic_alloc_coherent(struct device *dev, size_t size,
142 dma_addr_t *dma_addr, gfp_t flag)
144 unsigned long dma_mask;
148 dma_mask = dma_alloc_coherent_mask(dev, flag);
152 page = alloc_pages_node(dev_to_node(dev), flag, get_order(size));
156 addr = page_to_phys(page);
157 if (addr + size > dma_mask) {
158 __free_pages(page, get_order(size));
160 if (dma_mask < DMA_BIT_MASK(32) && !(flag & GFP_DMA)) {
161 flag = (flag & ~GFP_DMA32) | GFP_DMA;
169 return page_address(page);
173 * See <Documentation/x86_64/boot-options.txt> for the iommu kernel parameter
176 static __init int iommu_setup(char *p)
184 if (!strncmp(p, "off", 3))
186 /* gart_parse_options has more force support */
187 if (!strncmp(p, "force", 5))
189 if (!strncmp(p, "noforce", 7)) {
194 if (!strncmp(p, "biomerge", 8)) {
198 if (!strncmp(p, "panic", 5))
199 panic_on_overflow = 1;
200 if (!strncmp(p, "nopanic", 7))
201 panic_on_overflow = 0;
202 if (!strncmp(p, "merge", 5)) {
206 if (!strncmp(p, "nomerge", 7))
208 if (!strncmp(p, "forcesac", 8))
210 if (!strncmp(p, "allowdac", 8))
212 if (!strncmp(p, "nodac", 5))
214 if (!strncmp(p, "usedac", 6)) {
218 #ifdef CONFIG_SWIOTLB
219 if (!strncmp(p, "soft", 4))
222 if (!strncmp(p, "pt", 2)) {
223 iommu_pass_through = 1;
227 gart_parse_options(p);
229 #ifdef CONFIG_CALGARY_IOMMU
230 if (!strncmp(p, "calgary", 7))
232 #endif /* CONFIG_CALGARY_IOMMU */
234 p += strcspn(p, ",");
240 early_param("iommu", iommu_setup);
242 int dma_supported(struct device *dev, u64 mask)
244 struct dma_map_ops *ops = get_dma_ops(dev);
247 if (mask > 0xffffffff && forbid_dac > 0) {
248 dev_info(dev, "PCI: Disallowing DAC for device\n");
253 if (ops->dma_supported)
254 return ops->dma_supported(dev, mask);
256 /* Copied from i386. Doesn't make much sense, because it will
257 only work for pci_alloc_coherent.
258 The caller just has to use GFP_DMA in this case. */
259 if (mask < DMA_BIT_MASK(24))
262 /* Tell the device to use SAC when IOMMU force is on. This
263 allows the driver to use cheaper accesses in some cases.
265 Problem with this is that if we overflow the IOMMU area and
266 return DAC as fallback address the device may not handle it
269 As a special case some controllers have a 39bit address
270 mode that is as efficient as 32bit (aic79xx). Don't force
271 SAC for these. Assume all masks <= 40 bits are of this
272 type. Normally this doesn't make any difference, but gives
273 more gentle handling of IOMMU overflow. */
274 if (iommu_sac_force && (mask >= DMA_BIT_MASK(40))) {
275 dev_info(dev, "Force SAC with mask %Lx\n", mask);
281 EXPORT_SYMBOL(dma_supported);
283 static int __init pci_iommu_init(void)
285 dma_debug_init(PREALLOC_DMA_DEBUG_ENTRIES);
288 dma_debug_add_bus(&pci_bus_type);
291 calgary_iommu_init();
303 void pci_iommu_shutdown(void)
305 gart_iommu_shutdown();
307 amd_iommu_shutdown();
309 /* Must execute after PCI subsystem */
310 fs_initcall(pci_iommu_init);
313 /* Many VIA bridges seem to corrupt data for DAC. Disable it here */
315 static __devinit void via_no_dac(struct pci_dev *dev)
317 if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI && forbid_dac == 0) {
318 dev_info(&dev->dev, "disabling DAC on VIA PCI bridge\n");
322 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_ANY_ID, via_no_dac);