2 * Power and Sleep Controller (PSC) functions.
4 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
5 * Copyright (C) 2008 Lyrtech <www.lyrtech.com>
6 * Copyright (C) 2004 Texas Instruments.
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
27 #include <asm/arch/hardware.h>
29 #define PINMUX0_EMACEN (1 << 31)
30 #define PINMUX0_AECS5 (1 << 11)
31 #define PINMUX0_AECS4 (1 << 10)
33 #define PINMUX1_I2C (1 << 7)
34 #define PINMUX1_UART1 (1 << 1)
35 #define PINMUX1_UART0 (1 << 0)
38 * The DM6446 includes two separate power domains: "Always On" and "DSP". The
39 * "Always On" power domain is always on when the chip is on. The "Always On"
40 * domain is powered by the VDD pins of the DM6446. The majority of the
41 * DM6446's modules lie within the "Always On" power domain. A separate
42 * domain called the "DSP" domain houses the C64x+ and VICP. The "DSP" domain
43 * is not always on. The "DSP" power domain is powered by the CVDDDSP pins of
47 /* Works on Always On power domain only (no PD argument) */
48 void lpsc_on(unsigned int id)
50 dv_reg_p mdstat, mdctl;
52 if (id >= DAVINCI_LPSC_GEM)
53 return; /* Don't work on DSP Power Domain */
55 mdstat = REG_P(PSC_MDSTAT_BASE + (id * 4));
56 mdctl = REG_P(PSC_MDCTL_BASE + (id * 4));
58 while (REG(PSC_PTSTAT) & 0x01);
60 if ((*mdstat & 0x1f) == 0x03)
61 return; /* Already on and enabled */
65 /* Special treatment for some modules as for sprue14 p.7.4.2 */
67 case DAVINCI_LPSC_VPSSSLV:
68 case DAVINCI_LPSC_EMAC:
69 case DAVINCI_LPSC_EMAC_WRAPPER:
70 case DAVINCI_LPSC_MDIO:
71 case DAVINCI_LPSC_USB:
72 case DAVINCI_LPSC_ATA:
73 case DAVINCI_LPSC_VLYNQ:
74 case DAVINCI_LPSC_UHPI:
75 case DAVINCI_LPSC_DDR_EMIF:
76 case DAVINCI_LPSC_AEMIF:
77 case DAVINCI_LPSC_MMC_SD:
78 case DAVINCI_LPSC_MEMSTICK:
79 case DAVINCI_LPSC_McBSP:
80 case DAVINCI_LPSC_GPIO:
85 REG(PSC_PTCMD) = 0x01;
87 while (REG(PSC_PTSTAT) & 0x03);
88 while ((*mdstat & 0x1f) != 0x03); /* Probably an overkill... */
91 /* If DSPLINK is used, we don't want U-Boot to power on the DSP. */
92 #if !defined(CONFIG_SYS_USE_DSPLINK)
97 if (REG(PSC_PDSTAT1) & 0x1f)
98 return; /* Already on */
100 REG(PSC_GBLCTL) |= 0x01;
101 REG(PSC_PDCTL1) |= 0x01;
102 REG(PSC_PDCTL1) &= ~0x100;
103 REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_GEM * 4)) |= 0x03;
104 REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_GEM * 4)) &= 0xfffffeff;
105 REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_IMCOP * 4)) |= 0x03;
106 REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_IMCOP * 4)) &= 0xfffffeff;
107 REG(PSC_PTCMD) = 0x02;
109 for (i = 0; i < 100; i++) {
110 if (REG(PSC_EPCPR) & 0x02)
114 REG(PSC_CHP_SHRTSW) = 0x01;
115 REG(PSC_PDCTL1) |= 0x100;
116 REG(PSC_EPCCR) = 0x02;
118 for (i = 0; i < 100; i++) {
119 if (!(REG(PSC_PTSTAT) & 0x02))
123 REG(PSC_GBLCTL) &= ~0x1f;
125 #endif /* CONFIG_SYS_USE_DSPLINK */
127 void davinci_enable_uart0(void)
129 lpsc_on(DAVINCI_LPSC_UART0);
131 /* Bringup UART0 out of reset */
132 REG(UART0_PWREMU_MGMT) = 0x0000e003;
134 /* Enable UART0 MUX lines */
135 REG(PINMUX1) |= PINMUX1_UART0;
138 #ifdef CONFIG_DRIVER_TI_EMAC
139 void davinci_enable_emac(void)
141 lpsc_on(DAVINCI_LPSC_EMAC);
142 lpsc_on(DAVINCI_LPSC_EMAC_WRAPPER);
143 lpsc_on(DAVINCI_LPSC_MDIO);
145 /* Enable GIO3.3V cells used for EMAC */
146 REG(VDD3P3V_PWDN) = 0;
149 REG(PINMUX0) |= PINMUX0_EMACEN;
153 void davinci_enable_i2c(void)
155 lpsc_on(DAVINCI_LPSC_I2C);
157 /* Enable I2C pin Mux */
158 REG(PINMUX1) |= PINMUX1_I2C;
161 void davinci_errata_workarounds(void)
164 * Workaround for TMS320DM6446 errata 1.3.22:
165 * PSC: PTSTAT Register Does Not Clear After Warm/Maximum Reset
166 * Revision(s) Affected: 1.3 and earlier
168 REG(PSC_SILVER_BULLET) = 0;
171 * Set the PR_OLD_COUNT bits in the Bus Burst Priority Register (PBBPR)
172 * as suggested in TMS320DM6446 errata 2.1.2:
174 * On DM6446 Silicon Revision 2.1 and earlier, under certain conditions
175 * low priority modules can occupy the bus and prevent high priority
176 * modules like the VPSS from getting the required DDR2 throughput.
177 * A hex value of 0x20 should provide a good ARM (cache enabled)
178 * performance and still allow good utilization by the VPSS or other