2 * Copyright 2007 Wind River Systemes, Inc. <www.windriver.com>
3 * Copyright 2007 Embedded Specialties, Inc.
5 * Copyright 2004 Freescale Semiconductor.
6 * Copyright 2002,2003, Motorola Inc.
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 #include <ppc_asm.tmpl>
29 #include <asm/cache.h>
36 * TLB0 and TLB1 Entries
38 * Out of reset, TLB1's Entry 0 maps the highest 4K for CCSRBAR.
39 * However, CCSRBAR is then relocated to CFG_CCSRBAR right after
40 * these TLB entries are established.
42 * The TLB entries for DDR are dynamically setup in spd_sdram()
43 * and use TLB1 Entries 8 through 15 as needed according to the
46 * MAS0: tlbsel, esel, nv
47 * MAS1: valid, iprot, tid, ts, tsize
48 * MAS2: epn, x0, x1, w, i, m, g, e
49 * MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr
61 .section .bootpg, "ax"
68 * Number of TLB0 and TLB1 entries in the following table
72 #if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)
74 * TLB0 4K Non-cacheable, guarded
75 * 0xff700000 4K Initial CCSRBAR mapping
77 * This ends up at a TLB0 Index==0 entry, and must not collide
78 * with other TLB0 Entries.
80 .long FSL_BOOKE_MAS0(0, 0, 0)
81 .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
82 .long FSL_BOOKE_MAS2(CFG_CCSRBAR_DEFAULT, (MAS2_I|MAS2_G))
83 .long FSL_BOOKE_MAS3(CFG_CCSRBAR_DEFAULT, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
85 #error("Update the number of table entries in tlb1_entry")
89 * TLB0 16K Cacheable, non-guarded
90 * 0xe4010000 16K Temporary Global data for initialization
92 * Use four 4K TLB0 entries. These entries must be cacheable
93 * as they provide the bootstrap memory before the memory
94 * controler and real memory have been configured.
96 * These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c,
97 * and must not collide with other TLB0 entries.
99 .long FSL_BOOKE_MAS0(0, 0, 0)
100 .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
101 .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR, 0)
102 .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
104 .long FSL_BOOKE_MAS0(0, 0, 0)
105 .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
106 .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 4 * 1024, 0)
107 .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 4 * 1024, 0,
108 (MAS3_SX|MAS3_SW|MAS3_SR))
110 .long FSL_BOOKE_MAS0(0, 0, 0)
111 .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
112 .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 8 * 1024, 0)
113 .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 8 * 1024, 0,
114 (MAS3_SX|MAS3_SW|MAS3_SR))
116 .long FSL_BOOKE_MAS0(0, 0, 0)
117 .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
118 .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 12 * 1024, 0)
119 .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 12 * 1024, 0,
120 (MAS3_SX|MAS3_SW|MAS3_SR))
123 * TLB 0: 16M Non-cacheable, guarded
124 * 0xff800000 16M TLB for 8MB FLASH
125 * Out of reset this entry is only 4K.
127 .long FSL_BOOKE_MAS0(1, 0, 0)
128 .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)
129 .long FSL_BOOKE_MAS2(CFG_FLASH_BASE, (MAS2_I|MAS2_G))
130 .long FSL_BOOKE_MAS3(CFG_FLASH_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
133 * TLB 1: 256M Non-cacheable, guarded
134 * 0x80000000 256M PCI1 MEM First half
136 .long FSL_BOOKE_MAS0(1, 1, 0)
137 .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
138 .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_PHYS, (MAS2_I|MAS2_G))
139 .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_PHYS, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
142 * TLB 2: 256M Non-cacheable, guarded
143 * 0x90000000 256M PCI1 MEM Second half
145 .long FSL_BOOKE_MAS0(1, 2, 0)
146 .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
147 .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_PHYS + 0x10000000, (MAS2_I|MAS2_G))
148 .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_PHYS + 0x10000000, 0,
149 (MAS3_SX|MAS3_SW|MAS3_SR))
152 * TLB 3: 256M Cacheable, non-guarded
155 #if !defined(CONFIG_SPD_EEPROM)
156 .long FSL_BOOKE_MAS0(1, 3, 0)
157 .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
158 .long FSL_BOOKE_MAS2(CFG_DDR_SDRAM_BASE, 0)
159 .long FSL_BOOKE_MAS3(CFG_DDR_SDRAM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
163 * TLB 4: 64M Non-cacheable, guarded
164 * 0xe0000000 1M CCSRBAR
165 * 0xe2000000 16M PCI1 IO
167 .long FSL_BOOKE_MAS0(1, 4, 0)
168 .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
169 .long FSL_BOOKE_MAS2(CFG_CCSRBAR, (MAS2_I|MAS2_G))
170 .long FSL_BOOKE_MAS3(CFG_CCSRBAR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
173 * TLB 5: 64M Cacheable, non-guarded
174 * 0xf0000000 64M LBC SDRAM
176 .long FSL_BOOKE_MAS0(1, 5, 0)
177 .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
178 .long FSL_BOOKE_MAS2(CFG_LBC_SDRAM_BASE, 0)
179 .long FSL_BOOKE_MAS3(CFG_LBC_SDRAM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
182 * TLB 6: 16M Cacheable, non-guarded
183 * 0xf8000000 1M 7-segment LED display
184 * 0xf8100000 1M User switches
185 * 0xf8300000 1M Board revision
186 * 0xf8b00000 1M EEPROM
188 .long FSL_BOOKE_MAS0(1, 6, 0)
189 .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)
190 .long FSL_BOOKE_MAS2(CFG_EPLD_BASE, 0)
191 .long FSL_BOOKE_MAS3(CFG_EPLD_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))