2 * linux/drivers/mmc/host/mmci.c - ARM PrimeCell MMCI PL180/1 driver
4 * Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved.
5 * Copyright (C) 2010 ST-Ericsson SA
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/init.h>
14 #include <linux/ioport.h>
15 #include <linux/device.h>
16 #include <linux/interrupt.h>
17 #include <linux/kernel.h>
18 #include <linux/delay.h>
19 #include <linux/err.h>
20 #include <linux/highmem.h>
21 #include <linux/log2.h>
22 #include <linux/mmc/host.h>
23 #include <linux/mmc/card.h>
24 #include <linux/amba/bus.h>
25 #include <linux/clk.h>
26 #include <linux/scatterlist.h>
27 #include <linux/gpio.h>
28 #include <linux/regulator/consumer.h>
29 #include <linux/dmaengine.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/amba/mmci.h>
33 #include <asm/div64.h>
35 #include <asm/sizes.h>
39 #define DRIVER_NAME "mmci-pl18x"
41 static unsigned int fmax = 515633;
44 * struct variant_data - MMCI variant-specific quirks
45 * @clkreg: default value for MCICLOCK register
46 * @clkreg_enable: enable value for MMCICLOCK register
47 * @datalength_bits: number of bits in the MMCIDATALENGTH register
48 * @fifosize: number of bytes that can be written when MMCI_TXFIFOEMPTY
49 * is asserted (likewise for RX)
50 * @fifohalfsize: number of bytes that can be written when MCI_TXFIFOHALFEMPTY
51 * is asserted (likewise for RX)
52 * @sdio: variant supports SDIO
53 * @st_clkdiv: true if using a ST-specific clock divider algorithm
57 unsigned int clkreg_enable;
58 unsigned int datalength_bits;
59 unsigned int fifosize;
60 unsigned int fifohalfsize;
65 static struct variant_data variant_arm = {
67 .fifohalfsize = 8 * 4,
68 .datalength_bits = 16,
71 static struct variant_data variant_u300 = {
73 .fifohalfsize = 8 * 4,
74 .clkreg_enable = 1 << 13, /* HWFCEN */
75 .datalength_bits = 16,
79 static struct variant_data variant_ux500 = {
81 .fifohalfsize = 8 * 4,
82 .clkreg = MCI_CLK_ENABLE,
83 .clkreg_enable = 1 << 14, /* HWFCEN */
84 .datalength_bits = 24,
90 * This must be called with host->lock held
92 static void mmci_set_clkreg(struct mmci_host *host, unsigned int desired)
94 struct variant_data *variant = host->variant;
95 u32 clk = variant->clkreg;
98 if (desired >= host->mclk) {
100 host->cclk = host->mclk;
101 } else if (variant->st_clkdiv) {
103 * DB8500 TRM says f = mclk / (clkdiv + 2)
104 * => clkdiv = (mclk / f) - 2
105 * Round the divider up so we don't exceed the max
108 clk = DIV_ROUND_UP(host->mclk, desired) - 2;
111 host->cclk = host->mclk / (clk + 2);
114 * PL180 TRM says f = mclk / (2 * (clkdiv + 1))
115 * => clkdiv = mclk / (2 * f) - 1
117 clk = host->mclk / (2 * desired) - 1;
120 host->cclk = host->mclk / (2 * (clk + 1));
123 clk |= variant->clkreg_enable;
124 clk |= MCI_CLK_ENABLE;
125 /* This hasn't proven to be worthwhile */
126 /* clk |= MCI_CLK_PWRSAVE; */
129 if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_4)
131 if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_8)
132 clk |= MCI_ST_8BIT_BUS;
134 writel(clk, host->base + MMCICLOCK);
138 mmci_request_end(struct mmci_host *host, struct mmc_request *mrq)
140 writel(0, host->base + MMCICOMMAND);
148 * Need to drop the host lock here; mmc_request_done may call
149 * back into the driver...
151 spin_unlock(&host->lock);
152 mmc_request_done(host->mmc, mrq);
153 spin_lock(&host->lock);
156 static void mmci_set_mask1(struct mmci_host *host, unsigned int mask)
158 void __iomem *base = host->base;
160 if (host->singleirq) {
161 unsigned int mask0 = readl(base + MMCIMASK0);
163 mask0 &= ~MCI_IRQ1MASK;
166 writel(mask0, base + MMCIMASK0);
169 writel(mask, base + MMCIMASK1);
172 static void mmci_stop_data(struct mmci_host *host)
174 writel(0, host->base + MMCIDATACTRL);
175 mmci_set_mask1(host, 0);
179 static void mmci_init_sg(struct mmci_host *host, struct mmc_data *data)
181 unsigned int flags = SG_MITER_ATOMIC;
183 if (data->flags & MMC_DATA_READ)
184 flags |= SG_MITER_TO_SG;
186 flags |= SG_MITER_FROM_SG;
188 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
192 * All the DMA operation mode stuff goes inside this ifdef.
193 * This assumes that you have a generic DMA device interface,
194 * no custom DMA interfaces are supported.
196 #ifdef CONFIG_DMA_ENGINE
197 static void __devinit mmci_dma_setup(struct mmci_host *host)
199 struct mmci_platform_data *plat = host->plat;
200 const char *rxname, *txname;
203 if (!plat || !plat->dma_filter) {
204 dev_info(mmc_dev(host->mmc), "no DMA platform data\n");
208 /* Try to acquire a generic DMA engine slave channel */
210 dma_cap_set(DMA_SLAVE, mask);
213 * If only an RX channel is specified, the driver will
214 * attempt to use it bidirectionally, however if it is
215 * is specified but cannot be located, DMA will be disabled.
217 if (plat->dma_rx_param) {
218 host->dma_rx_channel = dma_request_channel(mask,
221 /* E.g if no DMA hardware is present */
222 if (!host->dma_rx_channel)
223 dev_err(mmc_dev(host->mmc), "no RX DMA channel\n");
226 if (plat->dma_tx_param) {
227 host->dma_tx_channel = dma_request_channel(mask,
230 if (!host->dma_tx_channel)
231 dev_warn(mmc_dev(host->mmc), "no TX DMA channel\n");
233 host->dma_tx_channel = host->dma_rx_channel;
236 if (host->dma_rx_channel)
237 rxname = dma_chan_name(host->dma_rx_channel);
241 if (host->dma_tx_channel)
242 txname = dma_chan_name(host->dma_tx_channel);
246 dev_info(mmc_dev(host->mmc), "DMA channels RX %s, TX %s\n",
250 * Limit the maximum segment size in any SG entry according to
251 * the parameters of the DMA engine device.
253 if (host->dma_tx_channel) {
254 struct device *dev = host->dma_tx_channel->device->dev;
255 unsigned int max_seg_size = dma_get_max_seg_size(dev);
257 if (max_seg_size < host->mmc->max_seg_size)
258 host->mmc->max_seg_size = max_seg_size;
260 if (host->dma_rx_channel) {
261 struct device *dev = host->dma_rx_channel->device->dev;
262 unsigned int max_seg_size = dma_get_max_seg_size(dev);
264 if (max_seg_size < host->mmc->max_seg_size)
265 host->mmc->max_seg_size = max_seg_size;
270 * This is used in __devinit or __devexit so inline it
271 * so it can be discarded.
273 static inline void mmci_dma_release(struct mmci_host *host)
275 struct mmci_platform_data *plat = host->plat;
277 if (host->dma_rx_channel)
278 dma_release_channel(host->dma_rx_channel);
279 if (host->dma_tx_channel && plat->dma_tx_param)
280 dma_release_channel(host->dma_tx_channel);
281 host->dma_rx_channel = host->dma_tx_channel = NULL;
284 static void mmci_dma_unmap(struct mmci_host *host, struct mmc_data *data)
286 struct dma_chan *chan = host->dma_current;
287 enum dma_data_direction dir;
291 /* Wait up to 1ms for the DMA to complete */
293 status = readl(host->base + MMCISTATUS);
294 if (!(status & MCI_RXDATAAVLBLMASK) || i >= 100)
300 * Check to see whether we still have some data left in the FIFO -
301 * this catches DMA controllers which are unable to monitor the
302 * DMALBREQ and DMALSREQ signals while allowing us to DMA to non-
303 * contiguous buffers. On TX, we'll get a FIFO underrun error.
305 if (status & MCI_RXDATAAVLBLMASK) {
306 dmaengine_terminate_all(chan);
311 if (data->flags & MMC_DATA_WRITE) {
314 dir = DMA_FROM_DEVICE;
317 dma_unmap_sg(chan->device->dev, data->sg, data->sg_len, dir);
320 * Use of DMA with scatter-gather is impossible.
321 * Give up with DMA and switch back to PIO mode.
323 if (status & MCI_RXDATAAVLBLMASK) {
324 dev_err(mmc_dev(host->mmc), "buggy DMA detected. Taking evasive action.\n");
325 mmci_dma_release(host);
329 static void mmci_dma_data_error(struct mmci_host *host)
331 dev_err(mmc_dev(host->mmc), "error during DMA transfer!\n");
332 dmaengine_terminate_all(host->dma_current);
335 static int mmci_dma_start_data(struct mmci_host *host, unsigned int datactrl)
337 struct variant_data *variant = host->variant;
338 struct dma_slave_config conf = {
339 .src_addr = host->phybase + MMCIFIFO,
340 .dst_addr = host->phybase + MMCIFIFO,
341 .src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
342 .dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
343 .src_maxburst = variant->fifohalfsize >> 2, /* # of words */
344 .dst_maxburst = variant->fifohalfsize >> 2, /* # of words */
346 struct mmc_data *data = host->data;
347 struct dma_chan *chan;
348 struct dma_device *device;
349 struct dma_async_tx_descriptor *desc;
352 host->dma_current = NULL;
354 if (data->flags & MMC_DATA_READ) {
355 conf.direction = DMA_FROM_DEVICE;
356 chan = host->dma_rx_channel;
358 conf.direction = DMA_TO_DEVICE;
359 chan = host->dma_tx_channel;
362 /* If there's no DMA channel, fall back to PIO */
366 /* If less than or equal to the fifo size, don't bother with DMA */
367 if (host->size <= variant->fifosize)
370 device = chan->device;
371 nr_sg = dma_map_sg(device->dev, data->sg, data->sg_len, conf.direction);
375 dmaengine_slave_config(chan, &conf);
376 desc = device->device_prep_slave_sg(chan, data->sg, nr_sg,
377 conf.direction, DMA_CTRL_ACK);
381 /* Okay, go for it. */
382 host->dma_current = chan;
384 dev_vdbg(mmc_dev(host->mmc),
385 "Submit MMCI DMA job, sglen %d blksz %04x blks %04x flags %08x\n",
386 data->sg_len, data->blksz, data->blocks, data->flags);
387 dmaengine_submit(desc);
388 dma_async_issue_pending(chan);
390 datactrl |= MCI_DPSM_DMAENABLE;
392 /* Trigger the DMA transfer */
393 writel(datactrl, host->base + MMCIDATACTRL);
396 * Let the MMCI say when the data is ended and it's time
397 * to fire next DMA request. When that happens, MMCI will
398 * call mmci_data_end()
400 writel(readl(host->base + MMCIMASK0) | MCI_DATAENDMASK,
401 host->base + MMCIMASK0);
405 dmaengine_terminate_all(chan);
406 dma_unmap_sg(device->dev, data->sg, data->sg_len, conf.direction);
410 /* Blank functions if the DMA engine is not available */
411 static inline void mmci_dma_setup(struct mmci_host *host)
415 static inline void mmci_dma_release(struct mmci_host *host)
419 static inline void mmci_dma_unmap(struct mmci_host *host, struct mmc_data *data)
423 static inline void mmci_dma_data_error(struct mmci_host *host)
427 static inline int mmci_dma_start_data(struct mmci_host *host, unsigned int datactrl)
433 static void mmci_start_data(struct mmci_host *host, struct mmc_data *data)
435 struct variant_data *variant = host->variant;
436 unsigned int datactrl, timeout, irqmask;
437 unsigned long long clks;
441 dev_dbg(mmc_dev(host->mmc), "blksz %04x blks %04x flags %08x\n",
442 data->blksz, data->blocks, data->flags);
445 host->size = data->blksz * data->blocks;
446 data->bytes_xfered = 0;
448 clks = (unsigned long long)data->timeout_ns * host->cclk;
449 do_div(clks, 1000000000UL);
451 timeout = data->timeout_clks + (unsigned int)clks;
454 writel(timeout, base + MMCIDATATIMER);
455 writel(host->size, base + MMCIDATALENGTH);
457 blksz_bits = ffs(data->blksz) - 1;
458 BUG_ON(1 << blksz_bits != data->blksz);
460 datactrl = MCI_DPSM_ENABLE | blksz_bits << 4;
462 if (data->flags & MMC_DATA_READ)
463 datactrl |= MCI_DPSM_DIRECTION;
466 * Attempt to use DMA operation mode, if this
467 * should fail, fall back to PIO mode
469 if (!mmci_dma_start_data(host, datactrl))
472 /* IRQ mode, map the SG list for CPU reading/writing */
473 mmci_init_sg(host, data);
475 if (data->flags & MMC_DATA_READ) {
476 irqmask = MCI_RXFIFOHALFFULLMASK;
479 * If we have less than the fifo 'half-full' threshold to
480 * transfer, trigger a PIO interrupt as soon as any data
483 if (host->size < variant->fifohalfsize)
484 irqmask |= MCI_RXDATAAVLBLMASK;
487 * We don't actually need to include "FIFO empty" here
488 * since its implicit in "FIFO half empty".
490 irqmask = MCI_TXFIFOHALFEMPTYMASK;
493 /* The ST Micro variants has a special bit to enable SDIO */
494 if (variant->sdio && host->mmc->card)
495 if (mmc_card_sdio(host->mmc->card))
496 datactrl |= MCI_ST_DPSM_SDIOEN;
498 writel(datactrl, base + MMCIDATACTRL);
499 writel(readl(base + MMCIMASK0) & ~MCI_DATAENDMASK, base + MMCIMASK0);
500 mmci_set_mask1(host, irqmask);
504 mmci_start_command(struct mmci_host *host, struct mmc_command *cmd, u32 c)
506 void __iomem *base = host->base;
508 dev_dbg(mmc_dev(host->mmc), "op %02x arg %08x flags %08x\n",
509 cmd->opcode, cmd->arg, cmd->flags);
511 if (readl(base + MMCICOMMAND) & MCI_CPSM_ENABLE) {
512 writel(0, base + MMCICOMMAND);
516 c |= cmd->opcode | MCI_CPSM_ENABLE;
517 if (cmd->flags & MMC_RSP_PRESENT) {
518 if (cmd->flags & MMC_RSP_136)
519 c |= MCI_CPSM_LONGRSP;
520 c |= MCI_CPSM_RESPONSE;
523 c |= MCI_CPSM_INTERRUPT;
527 writel(cmd->arg, base + MMCIARGUMENT);
528 writel(c, base + MMCICOMMAND);
532 mmci_data_irq(struct mmci_host *host, struct mmc_data *data,
535 /* First check for errors */
536 if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_TXUNDERRUN|MCI_RXOVERRUN)) {
539 /* Terminate the DMA transfer */
540 if (dma_inprogress(host))
541 mmci_dma_data_error(host);
544 * Calculate how far we are into the transfer. Note that
545 * the data counter gives the number of bytes transferred
546 * on the MMC bus, not on the host side. On reads, this
547 * can be as much as a FIFO-worth of data ahead. This
548 * matters for FIFO overruns only.
550 remain = readl(host->base + MMCIDATACNT);
551 success = data->blksz * data->blocks - remain;
553 dev_dbg(mmc_dev(host->mmc), "MCI ERROR IRQ, status 0x%08x at 0x%08x\n",
555 if (status & MCI_DATACRCFAIL) {
556 /* Last block was not successful */
558 data->error = -EILSEQ;
559 } else if (status & MCI_DATATIMEOUT) {
560 data->error = -ETIMEDOUT;
561 } else if (status & MCI_TXUNDERRUN) {
563 } else if (status & MCI_RXOVERRUN) {
564 if (success > host->variant->fifosize)
565 success -= host->variant->fifosize;
570 data->bytes_xfered = round_down(success, data->blksz);
573 if (status & MCI_DATABLOCKEND)
574 dev_err(mmc_dev(host->mmc), "stray MCI_DATABLOCKEND interrupt\n");
576 if (status & MCI_DATAEND || data->error) {
577 if (dma_inprogress(host))
578 mmci_dma_unmap(host, data);
579 mmci_stop_data(host);
582 /* The error clause is handled above, success! */
583 data->bytes_xfered = data->blksz * data->blocks;
586 mmci_request_end(host, data->mrq);
588 mmci_start_command(host, data->stop, 0);
594 mmci_cmd_irq(struct mmci_host *host, struct mmc_command *cmd,
597 void __iomem *base = host->base;
601 if (status & MCI_CMDTIMEOUT) {
602 cmd->error = -ETIMEDOUT;
603 } else if (status & MCI_CMDCRCFAIL && cmd->flags & MMC_RSP_CRC) {
604 cmd->error = -EILSEQ;
606 cmd->resp[0] = readl(base + MMCIRESPONSE0);
607 cmd->resp[1] = readl(base + MMCIRESPONSE1);
608 cmd->resp[2] = readl(base + MMCIRESPONSE2);
609 cmd->resp[3] = readl(base + MMCIRESPONSE3);
612 if (!cmd->data || cmd->error) {
614 mmci_stop_data(host);
615 mmci_request_end(host, cmd->mrq);
616 } else if (!(cmd->data->flags & MMC_DATA_READ)) {
617 mmci_start_data(host, cmd->data);
621 static int mmci_pio_read(struct mmci_host *host, char *buffer, unsigned int remain)
623 void __iomem *base = host->base;
626 int host_remain = host->size;
629 int count = host_remain - (readl(base + MMCIFIFOCNT) << 2);
637 readsl(base + MMCIFIFO, ptr, count >> 2);
641 host_remain -= count;
646 status = readl(base + MMCISTATUS);
647 } while (status & MCI_RXDATAAVLBL);
652 static int mmci_pio_write(struct mmci_host *host, char *buffer, unsigned int remain, u32 status)
654 struct variant_data *variant = host->variant;
655 void __iomem *base = host->base;
659 unsigned int count, maxcnt;
661 maxcnt = status & MCI_TXFIFOEMPTY ?
662 variant->fifosize : variant->fifohalfsize;
663 count = min(remain, maxcnt);
666 * The ST Micro variant for SDIO transfer sizes
667 * less then 8 bytes should have clock H/W flow
671 mmc_card_sdio(host->mmc->card)) {
673 writel(readl(host->base + MMCICLOCK) &
674 ~variant->clkreg_enable,
675 host->base + MMCICLOCK);
677 writel(readl(host->base + MMCICLOCK) |
678 variant->clkreg_enable,
679 host->base + MMCICLOCK);
683 * SDIO especially may want to send something that is
684 * not divisible by 4 (as opposed to card sectors
685 * etc), and the FIFO only accept full 32-bit writes.
686 * So compensate by adding +3 on the count, a single
687 * byte become a 32bit write, 7 bytes will be two
690 writesl(base + MMCIFIFO, ptr, (count + 3) >> 2);
698 status = readl(base + MMCISTATUS);
699 } while (status & MCI_TXFIFOHALFEMPTY);
705 * PIO data transfer IRQ handler.
707 static irqreturn_t mmci_pio_irq(int irq, void *dev_id)
709 struct mmci_host *host = dev_id;
710 struct sg_mapping_iter *sg_miter = &host->sg_miter;
711 struct variant_data *variant = host->variant;
712 void __iomem *base = host->base;
716 status = readl(base + MMCISTATUS);
718 dev_dbg(mmc_dev(host->mmc), "irq1 (pio) %08x\n", status);
720 local_irq_save(flags);
723 unsigned int remain, len;
727 * For write, we only need to test the half-empty flag
728 * here - if the FIFO is completely empty, then by
729 * definition it is more than half empty.
731 * For read, check for data available.
733 if (!(status & (MCI_TXFIFOHALFEMPTY|MCI_RXDATAAVLBL)))
736 if (!sg_miter_next(sg_miter))
739 buffer = sg_miter->addr;
740 remain = sg_miter->length;
743 if (status & MCI_RXACTIVE)
744 len = mmci_pio_read(host, buffer, remain);
745 if (status & MCI_TXACTIVE)
746 len = mmci_pio_write(host, buffer, remain, status);
748 sg_miter->consumed = len;
756 status = readl(base + MMCISTATUS);
759 sg_miter_stop(sg_miter);
761 local_irq_restore(flags);
764 * If we have less than the fifo 'half-full' threshold to transfer,
765 * trigger a PIO interrupt as soon as any data is available.
767 if (status & MCI_RXACTIVE && host->size < variant->fifohalfsize)
768 mmci_set_mask1(host, MCI_RXDATAAVLBLMASK);
771 * If we run out of data, disable the data IRQs; this
772 * prevents a race where the FIFO becomes empty before
773 * the chip itself has disabled the data path, and
774 * stops us racing with our data end IRQ.
776 if (host->size == 0) {
777 mmci_set_mask1(host, 0);
778 writel(readl(base + MMCIMASK0) | MCI_DATAENDMASK, base + MMCIMASK0);
785 * Handle completion of command and data transfers.
787 static irqreturn_t mmci_irq(int irq, void *dev_id)
789 struct mmci_host *host = dev_id;
793 spin_lock(&host->lock);
796 struct mmc_command *cmd;
797 struct mmc_data *data;
799 status = readl(host->base + MMCISTATUS);
801 if (host->singleirq) {
802 if (status & readl(host->base + MMCIMASK1))
803 mmci_pio_irq(irq, dev_id);
805 status &= ~MCI_IRQ1MASK;
808 status &= readl(host->base + MMCIMASK0);
809 writel(status, host->base + MMCICLEAR);
811 dev_dbg(mmc_dev(host->mmc), "irq0 (data+cmd) %08x\n", status);
814 if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_TXUNDERRUN|
815 MCI_RXOVERRUN|MCI_DATAEND|MCI_DATABLOCKEND) && data)
816 mmci_data_irq(host, data, status);
819 if (status & (MCI_CMDCRCFAIL|MCI_CMDTIMEOUT|MCI_CMDSENT|MCI_CMDRESPEND) && cmd)
820 mmci_cmd_irq(host, cmd, status);
825 spin_unlock(&host->lock);
827 return IRQ_RETVAL(ret);
830 static void mmci_request(struct mmc_host *mmc, struct mmc_request *mrq)
832 struct mmci_host *host = mmc_priv(mmc);
835 WARN_ON(host->mrq != NULL);
837 if (mrq->data && !is_power_of_2(mrq->data->blksz)) {
838 dev_err(mmc_dev(mmc), "unsupported block size (%d bytes)\n",
840 mrq->cmd->error = -EINVAL;
841 mmc_request_done(mmc, mrq);
845 spin_lock_irqsave(&host->lock, flags);
849 if (mrq->data && mrq->data->flags & MMC_DATA_READ)
850 mmci_start_data(host, mrq->data);
852 mmci_start_command(host, mrq->cmd, 0);
854 spin_unlock_irqrestore(&host->lock, flags);
857 static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
859 struct mmci_host *host = mmc_priv(mmc);
864 switch (ios->power_mode) {
867 ret = mmc_regulator_set_ocr(mmc, host->vcc, 0);
871 ret = mmc_regulator_set_ocr(mmc, host->vcc, ios->vdd);
873 dev_err(mmc_dev(mmc), "unable to set OCR\n");
875 * The .set_ios() function in the mmc_host_ops
876 * struct return void, and failing to set the
877 * power should be rare so we print an error
883 if (host->plat->vdd_handler)
884 pwr |= host->plat->vdd_handler(mmc_dev(mmc), ios->vdd,
886 /* The ST version does not have this, fall through to POWER_ON */
887 if (host->hw_designer != AMBA_VENDOR_ST) {
896 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) {
897 if (host->hw_designer != AMBA_VENDOR_ST)
901 * The ST Micro variant use the ROD bit for something
902 * else and only has OD (Open Drain).
908 spin_lock_irqsave(&host->lock, flags);
910 mmci_set_clkreg(host, ios->clock);
912 if (host->pwr != pwr) {
914 writel(pwr, host->base + MMCIPOWER);
917 spin_unlock_irqrestore(&host->lock, flags);
920 static int mmci_get_ro(struct mmc_host *mmc)
922 struct mmci_host *host = mmc_priv(mmc);
924 if (host->gpio_wp == -ENOSYS)
927 return gpio_get_value_cansleep(host->gpio_wp);
930 static int mmci_get_cd(struct mmc_host *mmc)
932 struct mmci_host *host = mmc_priv(mmc);
933 struct mmci_platform_data *plat = host->plat;
936 if (host->gpio_cd == -ENOSYS) {
938 return 1; /* Assume always present */
940 status = plat->status(mmc_dev(host->mmc));
942 status = !!gpio_get_value_cansleep(host->gpio_cd)
946 * Use positive logic throughout - status is zero for no card,
947 * non-zero for card inserted.
952 static irqreturn_t mmci_cd_irq(int irq, void *dev_id)
954 struct mmci_host *host = dev_id;
956 mmc_detect_change(host->mmc, msecs_to_jiffies(500));
961 static const struct mmc_host_ops mmci_ops = {
962 .request = mmci_request,
963 .set_ios = mmci_set_ios,
964 .get_ro = mmci_get_ro,
965 .get_cd = mmci_get_cd,
968 static int __devinit mmci_probe(struct amba_device *dev,
969 const struct amba_id *id)
971 struct mmci_platform_data *plat = dev->dev.platform_data;
972 struct variant_data *variant = id->data;
973 struct mmci_host *host;
974 struct mmc_host *mmc;
977 /* must have platform data */
983 ret = amba_request_regions(dev, DRIVER_NAME);
987 mmc = mmc_alloc_host(sizeof(struct mmci_host), &dev->dev);
993 host = mmc_priv(mmc);
996 host->gpio_wp = -ENOSYS;
997 host->gpio_cd = -ENOSYS;
998 host->gpio_cd_irq = -1;
1000 host->hw_designer = amba_manf(dev);
1001 host->hw_revision = amba_rev(dev);
1002 dev_dbg(mmc_dev(mmc), "designer ID = 0x%02x\n", host->hw_designer);
1003 dev_dbg(mmc_dev(mmc), "revision = 0x%01x\n", host->hw_revision);
1005 host->clk = clk_get(&dev->dev, NULL);
1006 if (IS_ERR(host->clk)) {
1007 ret = PTR_ERR(host->clk);
1012 ret = clk_enable(host->clk);
1017 host->variant = variant;
1018 host->mclk = clk_get_rate(host->clk);
1020 * According to the spec, mclk is max 100 MHz,
1021 * so we try to adjust the clock down to this,
1024 if (host->mclk > 100000000) {
1025 ret = clk_set_rate(host->clk, 100000000);
1028 host->mclk = clk_get_rate(host->clk);
1029 dev_dbg(mmc_dev(mmc), "eventual mclk rate: %u Hz\n",
1032 host->phybase = dev->res.start;
1033 host->base = ioremap(dev->res.start, resource_size(&dev->res));
1039 mmc->ops = &mmci_ops;
1040 mmc->f_min = (host->mclk + 511) / 512;
1042 * If the platform data supplies a maximum operating
1043 * frequency, this takes precedence. Else, we fall back
1044 * to using the module parameter, which has a (low)
1045 * default value in case it is not specified. Either
1046 * value must not exceed the clock rate into the block,
1050 mmc->f_max = min(host->mclk, plat->f_max);
1052 mmc->f_max = min(host->mclk, fmax);
1053 dev_dbg(mmc_dev(mmc), "clocking block at %u Hz\n", mmc->f_max);
1055 #ifdef CONFIG_REGULATOR
1056 /* If we're using the regulator framework, try to fetch a regulator */
1057 host->vcc = regulator_get(&dev->dev, "vmmc");
1058 if (IS_ERR(host->vcc))
1061 int mask = mmc_regulator_get_ocrmask(host->vcc);
1064 dev_err(&dev->dev, "error getting OCR mask (%d)\n",
1067 host->mmc->ocr_avail = (u32) mask;
1070 "Provided ocr_mask/setpower will not be used "
1071 "(using regulator instead)\n");
1075 /* Fall back to platform data if no regulator is found */
1076 if (host->vcc == NULL)
1077 mmc->ocr_avail = plat->ocr_mask;
1078 mmc->caps = plat->capabilities;
1083 mmc->max_segs = NR_SG;
1086 * Since only a certain number of bits are valid in the data length
1087 * register, we must ensure that we don't exceed 2^num-1 bytes in a
1090 mmc->max_req_size = (1 << variant->datalength_bits) - 1;
1093 * Set the maximum segment size. Since we aren't doing DMA
1094 * (yet) we are only limited by the data length register.
1096 mmc->max_seg_size = mmc->max_req_size;
1099 * Block size can be up to 2048 bytes, but must be a power of two.
1101 mmc->max_blk_size = 2048;
1104 * No limit on the number of blocks transferred.
1106 mmc->max_blk_count = mmc->max_req_size;
1108 spin_lock_init(&host->lock);
1110 writel(0, host->base + MMCIMASK0);
1111 writel(0, host->base + MMCIMASK1);
1112 writel(0xfff, host->base + MMCICLEAR);
1114 if (gpio_is_valid(plat->gpio_cd)) {
1115 ret = gpio_request(plat->gpio_cd, DRIVER_NAME " (cd)");
1117 ret = gpio_direction_input(plat->gpio_cd);
1119 host->gpio_cd = plat->gpio_cd;
1120 else if (ret != -ENOSYS)
1123 ret = request_any_context_irq(gpio_to_irq(plat->gpio_cd),
1125 DRIVER_NAME " (cd)", host);
1127 host->gpio_cd_irq = gpio_to_irq(plat->gpio_cd);
1129 if (gpio_is_valid(plat->gpio_wp)) {
1130 ret = gpio_request(plat->gpio_wp, DRIVER_NAME " (wp)");
1132 ret = gpio_direction_input(plat->gpio_wp);
1134 host->gpio_wp = plat->gpio_wp;
1135 else if (ret != -ENOSYS)
1139 if ((host->plat->status || host->gpio_cd != -ENOSYS)
1140 && host->gpio_cd_irq < 0)
1141 mmc->caps |= MMC_CAP_NEEDS_POLL;
1143 ret = request_irq(dev->irq[0], mmci_irq, IRQF_SHARED, DRIVER_NAME " (cmd)", host);
1147 if (dev->irq[1] == NO_IRQ)
1148 host->singleirq = true;
1150 ret = request_irq(dev->irq[1], mmci_pio_irq, IRQF_SHARED,
1151 DRIVER_NAME " (pio)", host);
1156 writel(MCI_IRQENABLE, host->base + MMCIMASK0);
1158 amba_set_drvdata(dev, mmc);
1160 dev_info(&dev->dev, "%s: PL%03x manf %x rev%u at 0x%08llx irq %d,%d (pio)\n",
1161 mmc_hostname(mmc), amba_part(dev), amba_manf(dev),
1162 amba_rev(dev), (unsigned long long)dev->res.start,
1163 dev->irq[0], dev->irq[1]);
1165 mmci_dma_setup(host);
1172 free_irq(dev->irq[0], host);
1174 if (host->gpio_wp != -ENOSYS)
1175 gpio_free(host->gpio_wp);
1177 if (host->gpio_cd_irq >= 0)
1178 free_irq(host->gpio_cd_irq, host);
1179 if (host->gpio_cd != -ENOSYS)
1180 gpio_free(host->gpio_cd);
1182 iounmap(host->base);
1184 clk_disable(host->clk);
1190 amba_release_regions(dev);
1195 static int __devexit mmci_remove(struct amba_device *dev)
1197 struct mmc_host *mmc = amba_get_drvdata(dev);
1199 amba_set_drvdata(dev, NULL);
1202 struct mmci_host *host = mmc_priv(mmc);
1204 mmc_remove_host(mmc);
1206 writel(0, host->base + MMCIMASK0);
1207 writel(0, host->base + MMCIMASK1);
1209 writel(0, host->base + MMCICOMMAND);
1210 writel(0, host->base + MMCIDATACTRL);
1212 mmci_dma_release(host);
1213 free_irq(dev->irq[0], host);
1214 if (!host->singleirq)
1215 free_irq(dev->irq[1], host);
1217 if (host->gpio_wp != -ENOSYS)
1218 gpio_free(host->gpio_wp);
1219 if (host->gpio_cd_irq >= 0)
1220 free_irq(host->gpio_cd_irq, host);
1221 if (host->gpio_cd != -ENOSYS)
1222 gpio_free(host->gpio_cd);
1224 iounmap(host->base);
1225 clk_disable(host->clk);
1229 mmc_regulator_set_ocr(mmc, host->vcc, 0);
1230 regulator_put(host->vcc);
1234 amba_release_regions(dev);
1241 static int mmci_suspend(struct amba_device *dev, pm_message_t state)
1243 struct mmc_host *mmc = amba_get_drvdata(dev);
1247 struct mmci_host *host = mmc_priv(mmc);
1249 ret = mmc_suspend_host(mmc);
1251 writel(0, host->base + MMCIMASK0);
1257 static int mmci_resume(struct amba_device *dev)
1259 struct mmc_host *mmc = amba_get_drvdata(dev);
1263 struct mmci_host *host = mmc_priv(mmc);
1265 writel(MCI_IRQENABLE, host->base + MMCIMASK0);
1267 ret = mmc_resume_host(mmc);
1273 #define mmci_suspend NULL
1274 #define mmci_resume NULL
1277 static struct amba_id mmci_ids[] = {
1281 .data = &variant_arm,
1286 .data = &variant_arm,
1288 /* ST Micro variants */
1292 .data = &variant_u300,
1297 .data = &variant_u300,
1302 .data = &variant_ux500,
1307 static struct amba_driver mmci_driver = {
1309 .name = DRIVER_NAME,
1311 .probe = mmci_probe,
1312 .remove = __devexit_p(mmci_remove),
1313 .suspend = mmci_suspend,
1314 .resume = mmci_resume,
1315 .id_table = mmci_ids,
1318 static int __init mmci_init(void)
1320 return amba_driver_register(&mmci_driver);
1323 static void __exit mmci_exit(void)
1325 amba_driver_unregister(&mmci_driver);
1328 module_init(mmci_init);
1329 module_exit(mmci_exit);
1330 module_param(fmax, uint, 0444);
1332 MODULE_DESCRIPTION("ARM PrimeCell PL180/181 Multimedia Card Interface driver");
1333 MODULE_LICENSE("GPL");