2 * Copyright (C) 2014 Freescale Semiconductor
4 * SPDX-License-Identifier: GPL-2.0+
8 #include <fsl-mc/fsl_mc.h>
9 #include <fsl-mc/fsl_mc_sys.h>
10 #include <fsl-mc/fsl_mc_private.h>
11 #include <fsl-mc/fsl_dpmng.h>
12 #include <fsl-mc/fsl_dprc.h>
13 #include <fsl-mc/fsl_dpio.h>
14 #include <fsl-mc/fsl_qbman_portal.h>
16 #define MC_RAM_BASE_ADDR_ALIGNMENT (512UL * 1024 * 1024)
17 #define MC_RAM_BASE_ADDR_ALIGNMENT_MASK (~(MC_RAM_BASE_ADDR_ALIGNMENT - 1))
18 #define MC_RAM_SIZE_ALIGNMENT (256UL * 1024 * 1024)
20 #define MC_MEM_SIZE_ENV_VAR "mcmemsize"
21 #define MC_BOOT_TIMEOUT_ENV_VAR "mcboottimeout"
23 DECLARE_GLOBAL_DATA_PTR;
24 static int mc_boot_status;
25 struct fsl_mc_io *dflt_mc_io = NULL;
26 uint16_t dflt_dprc_handle = 0;
27 struct fsl_dpbp_obj *dflt_dpbp = NULL;
28 struct fsl_dpio_obj *dflt_dpio = NULL;
29 uint16_t dflt_dpio_handle = 0;
32 void dump_ram_words(const char *title, void *addr)
35 uint32_t *words = addr;
37 printf("Dumping beginning of %s (%p):\n", title, addr);
38 for (i = 0; i < 16; i++)
39 printf("%#x ", words[i]);
44 void dump_mc_ccsr_regs(struct mc_ccsr_registers __iomem *mc_ccsr_regs)
46 printf("MC CCSR registers:\n"
56 mc_ccsr_regs->reg_gcr1,
57 mc_ccsr_regs->reg_gsr,
58 mc_ccsr_regs->reg_sicbalr,
59 mc_ccsr_regs->reg_sicbahr,
60 mc_ccsr_regs->reg_sicapr,
61 mc_ccsr_regs->reg_mcfbalr,
62 mc_ccsr_regs->reg_mcfbahr,
63 mc_ccsr_regs->reg_mcfapr,
64 mc_ccsr_regs->reg_psr);
68 #define dump_ram_words(title, addr)
69 #define dump_mc_ccsr_regs(mc_ccsr_regs)
73 #ifndef CONFIG_SYS_LS_MC_FW_IN_DDR
75 * Copying MC firmware or DPL image to DDR
77 static int mc_copy_image(const char *title,
78 u64 image_addr, u32 image_size, u64 mc_ram_addr)
80 debug("%s copied to address %p\n", title, (void *)mc_ram_addr);
81 memcpy((void *)mc_ram_addr, (void *)image_addr, image_size);
82 flush_dcache_range(mc_ram_addr, mc_ram_addr + image_size);
87 * MC firmware FIT image parser checks if the image is in FIT
88 * format, verifies integrity of the image and calculates
89 * raw image address and size values.
90 * Returns 0 on success and a negative errno on error.
93 int parse_mc_firmware_fit_image(const void **raw_image_addr,
94 size_t *raw_image_size)
101 const char *uname = "firmware";
103 /* Check if the image is in NOR flash */
104 #ifdef CONFIG_SYS_LS_MC_FW_IN_NOR
105 fit_hdr = (void *)CONFIG_SYS_LS_MC_FW_ADDR;
107 #error "No CONFIG_SYS_LS_MC_FW_IN_xxx defined"
110 /* Check if Image is in FIT format */
111 format = genimg_get_format(fit_hdr);
113 if (format != IMAGE_FORMAT_FIT) {
114 printf("fsl-mc: ERROR: Bad firmware image (not a FIT image)\n");
118 if (!fit_check_format(fit_hdr)) {
119 printf("fsl-mc: ERROR: Bad firmware image (bad FIT header)\n");
123 node_offset = fit_image_get_node(fit_hdr, uname);
125 if (node_offset < 0) {
126 printf("fsl-mc: ERROR: Bad firmware image (missing subimage)\n");
130 /* Verify MC firmware image */
131 if (!(fit_image_verify(fit_hdr, node_offset))) {
132 printf("fsl-mc: ERROR: Bad firmware image (bad CRC)\n");
136 /* Get address and size of raw image */
137 fit_image_get_data(fit_hdr, node_offset, &data, &size);
139 *raw_image_addr = data;
140 *raw_image_size = size;
147 * Calculates the values to be used to specify the address range
148 * for the MC private DRAM block, in the MCFBALR/MCFBAHR registers.
149 * It returns the highest 512MB-aligned address within the given
150 * address range, in '*aligned_base_addr', and the number of 256 MiB
151 * blocks in it, in 'num_256mb_blocks'.
153 static int calculate_mc_private_ram_params(u64 mc_private_ram_start_addr,
155 u64 *aligned_base_addr,
156 u8 *num_256mb_blocks)
161 if (mc_ram_size % MC_RAM_SIZE_ALIGNMENT != 0) {
162 printf("fsl-mc: ERROR: invalid MC private RAM size (%lu)\n",
167 num_blocks = mc_ram_size / MC_RAM_SIZE_ALIGNMENT;
168 if (num_blocks < 1 || num_blocks > 0xff) {
169 printf("fsl-mc: ERROR: invalid MC private RAM size (%lu)\n",
174 addr = (mc_private_ram_start_addr + mc_ram_size - 1) &
175 MC_RAM_BASE_ADDR_ALIGNMENT_MASK;
177 if (addr < mc_private_ram_start_addr) {
178 printf("fsl-mc: ERROR: bad start address %#llx\n",
179 mc_private_ram_start_addr);
183 *aligned_base_addr = addr;
184 *num_256mb_blocks = num_blocks;
188 static int load_mc_dpc(u64 mc_ram_addr, size_t mc_ram_size)
191 #ifndef CONFIG_SYS_LS_MC_DPC_IN_DDR
197 #ifdef CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET
198 BUILD_BUG_ON((CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET & 0x3) != 0 ||
199 CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET > 0xffffffff);
201 mc_dpc_offset = CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET;
203 #error "CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET not defined"
207 * Load the MC DPC blob in the MC private DRAM block:
209 #ifdef CONFIG_SYS_LS_MC_DPC_IN_DDR
210 printf("MC DPC is preloaded to %#llx\n", mc_ram_addr + mc_dpc_offset);
213 * Get address and size of the DPC blob stored in flash:
215 #ifdef CONFIG_SYS_LS_MC_DPC_IN_NOR
216 dpc_fdt_hdr = (void *)CONFIG_SYS_LS_MC_DPC_ADDR;
218 #error "No CONFIG_SYS_LS_MC_DPC_IN_xxx defined"
221 error = fdt_check_header(dpc_fdt_hdr);
224 * Don't return with error here, since the MC firmware can
225 * still boot without a DPC
227 printf("\nfsl-mc: WARNING: No DPC image found");
231 dpc_size = fdt_totalsize(dpc_fdt_hdr);
232 if (dpc_size > CONFIG_SYS_LS_MC_DPC_MAX_LENGTH) {
233 printf("\nfsl-mc: ERROR: Bad DPC image (too large: %d)\n",
238 mc_copy_image("MC DPC blob",
239 (u64)dpc_fdt_hdr, dpc_size, mc_ram_addr + mc_dpc_offset);
240 #endif /* not defined CONFIG_SYS_LS_MC_DPC_IN_DDR */
242 dump_ram_words("DPC", (void *)(mc_ram_addr + mc_dpc_offset));
246 static int load_mc_dpl(u64 mc_ram_addr, size_t mc_ram_size)
249 #ifndef CONFIG_SYS_LS_MC_DPL_IN_DDR
255 #ifdef CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET
256 BUILD_BUG_ON((CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET & 0x3) != 0 ||
257 CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET > 0xffffffff);
259 mc_dpl_offset = CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET;
261 #error "CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET not defined"
265 * Load the MC DPL blob in the MC private DRAM block:
267 #ifdef CONFIG_SYS_LS_MC_DPL_IN_DDR
268 printf("MC DPL is preloaded to %#llx\n", mc_ram_addr + mc_dpl_offset);
271 * Get address and size of the DPL blob stored in flash:
273 #ifdef CONFIG_SYS_LS_MC_DPL_IN_NOR
274 dpl_fdt_hdr = (void *)CONFIG_SYS_LS_MC_DPL_ADDR;
276 #error "No CONFIG_SYS_LS_MC_DPL_IN_xxx defined"
279 error = fdt_check_header(dpl_fdt_hdr);
281 printf("\nfsl-mc: ERROR: Bad DPL image (bad header)\n");
285 dpl_size = fdt_totalsize(dpl_fdt_hdr);
286 if (dpl_size > CONFIG_SYS_LS_MC_DPL_MAX_LENGTH) {
287 printf("\nfsl-mc: ERROR: Bad DPL image (too large: %d)\n",
292 mc_copy_image("MC DPL blob",
293 (u64)dpl_fdt_hdr, dpl_size, mc_ram_addr + mc_dpl_offset);
294 #endif /* not defined CONFIG_SYS_LS_MC_DPL_IN_DDR */
296 dump_ram_words("DPL", (void *)(mc_ram_addr + mc_dpl_offset));
301 * Return the MC boot timeout value in milliseconds
303 static unsigned long get_mc_boot_timeout_ms(void)
305 unsigned long timeout_ms = CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS;
307 char *timeout_ms_env_var = getenv(MC_BOOT_TIMEOUT_ENV_VAR);
309 if (timeout_ms_env_var) {
310 timeout_ms = simple_strtoul(timeout_ms_env_var, NULL, 10);
311 if (timeout_ms == 0) {
312 printf("fsl-mc: WARNING: Invalid value for \'"
313 MC_BOOT_TIMEOUT_ENV_VAR
314 "\' environment variable: %lu\n",
317 timeout_ms = CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS;
324 #ifdef CONFIG_SYS_LS_MC_AIOP_IMG_IN_NOR
325 static int load_mc_aiop_img(u64 mc_ram_addr, size_t mc_ram_size)
330 * Load the MC AIOP image in the MC private DRAM block:
333 aiop_img = (void *)CONFIG_SYS_LS_MC_AIOP_IMG_ADDR;
334 mc_copy_image("MC AIOP image",
335 (u64)aiop_img, CONFIG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH,
336 mc_ram_addr + CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET);
341 static int wait_for_mc(bool booting_mc, u32 *final_reg_gsr)
344 u32 mc_fw_boot_status;
345 unsigned long timeout_ms = get_mc_boot_timeout_ms();
346 struct mc_ccsr_registers __iomem *mc_ccsr_regs = MC_CCSR_BASE_ADDR;
349 assert(timeout_ms > 0);
351 udelay(1000); /* throttle polling */
352 reg_gsr = in_le32(&mc_ccsr_regs->reg_gsr);
353 mc_fw_boot_status = (reg_gsr & GSR_FS_MASK);
354 if (mc_fw_boot_status & 0x1)
362 if (timeout_ms == 0) {
363 printf("ERROR: timeout\n");
365 /* TODO: Get an error status from an MC CCSR register */
369 if (mc_fw_boot_status != 0x1) {
371 * TODO: Identify critical errors from the GSR register's FS
372 * field and for those errors, set error to -ENODEV or other
373 * appropriate errno, so that the status property is set to
374 * failure in the fsl,dprc device tree node.
376 printf("WARNING: Firmware returned an error (GSR: %#x)\n",
383 *final_reg_gsr = reg_gsr;
391 struct mc_ccsr_registers __iomem *mc_ccsr_regs = MC_CCSR_BASE_ADDR;
395 #ifndef CONFIG_SYS_LS_MC_FW_IN_DDR
396 const void *raw_image_addr;
397 size_t raw_image_size = 0;
399 struct mc_version mc_ver_info;
400 u64 mc_ram_aligned_base_addr;
401 u8 mc_ram_num_256mb_blocks;
402 size_t mc_ram_size = mc_get_dram_block_size();
405 * The MC private DRAM block was already carved at the end of DRAM
406 * by board_init_f() using CONFIG_SYS_MEM_TOP_HIDE:
408 if (gd->bd->bi_dram[1].start) {
410 gd->bd->bi_dram[1].start + gd->bd->bi_dram[1].size;
413 gd->bd->bi_dram[0].start + gd->bd->bi_dram[0].size;
416 error = calculate_mc_private_ram_params(mc_ram_addr,
418 &mc_ram_aligned_base_addr,
419 &mc_ram_num_256mb_blocks);
424 * Management Complex cores should be held at reset out of POR.
425 * U-boot should be the first software to touch MC. To be safe,
426 * we reset all cores again by setting GCR1 to 0. It doesn't do
427 * anything if they are held at reset. After we setup the firmware
428 * we kick off MC by deasserting the reset bit for core 0, and
429 * deasserting the reset bits for Command Portal Managers.
430 * The stop bits are not touched here. They are used to stop the
431 * cores when they are active. Setting stop bits doesn't stop the
432 * cores from fetching instructions when they are released from
435 out_le32(&mc_ccsr_regs->reg_gcr1, 0);
438 #ifdef CONFIG_SYS_LS_MC_FW_IN_DDR
439 printf("MC firmware is preloaded to %#llx\n", mc_ram_addr);
441 error = parse_mc_firmware_fit_image(&raw_image_addr, &raw_image_size);
445 * Load the MC FW at the beginning of the MC private DRAM block:
447 mc_copy_image("MC Firmware",
448 (u64)raw_image_addr, raw_image_size, mc_ram_addr);
450 dump_ram_words("firmware", (void *)mc_ram_addr);
452 error = load_mc_dpc(mc_ram_addr, mc_ram_size);
456 error = load_mc_dpl(mc_ram_addr, mc_ram_size);
460 #ifdef CONFIG_SYS_LS_MC_AIOP_IMG_IN_NOR
461 error = load_mc_aiop_img(mc_ram_addr, mc_ram_size);
466 debug("mc_ccsr_regs %p\n", mc_ccsr_regs);
467 dump_mc_ccsr_regs(mc_ccsr_regs);
470 * Tell MC what is the address range of the DRAM block assigned to it:
472 reg_mcfbalr = (u32)mc_ram_aligned_base_addr |
473 (mc_ram_num_256mb_blocks - 1);
474 out_le32(&mc_ccsr_regs->reg_mcfbalr, reg_mcfbalr);
475 out_le32(&mc_ccsr_regs->reg_mcfbahr,
476 (u32)(mc_ram_aligned_base_addr >> 32));
477 out_le32(&mc_ccsr_regs->reg_mcfapr, MCFAPR_BYPASS_ICID_MASK);
480 * Tell the MC that we want delayed DPL deployment.
482 out_le32(&mc_ccsr_regs->reg_gsr, 0xDD00);
484 printf("\nfsl-mc: Booting Management Complex ... ");
487 * Deassert reset and release MC core 0 to run
489 out_le32(&mc_ccsr_regs->reg_gcr1, GCR1_P1_DE_RST | GCR1_M_ALL_DE_RST);
490 error = wait_for_mc(true, ®_gsr);
495 * TODO: need to obtain the portal_id for the root container from the
501 * Initialize the global default MC portal
502 * And check that the MC firmware is responding portal commands:
504 dflt_mc_io = (struct fsl_mc_io *)malloc(sizeof(struct fsl_mc_io));
506 printf(" No memory: malloc() failed\n");
510 dflt_mc_io->mmio_regs = SOC_MC_PORTAL_ADDR(portal_id);
511 debug("Checking access to MC portal of root DPRC container (portal_id %d, portal physical addr %p)\n",
512 portal_id, dflt_mc_io->mmio_regs);
514 error = mc_get_version(dflt_mc_io, &mc_ver_info);
516 printf("fsl-mc: ERROR: Firmware version check failed (error: %d)\n",
521 if (MC_VER_MAJOR != mc_ver_info.major)
522 printf("fsl-mc: ERROR: Firmware major version mismatch (found: %d, expected: %d)\n",
523 mc_ver_info.major, MC_VER_MAJOR);
525 if (MC_VER_MINOR != mc_ver_info.minor)
526 printf("fsl-mc: WARNING: Firmware minor version mismatch (found: %d, expected: %d)\n",
527 mc_ver_info.minor, MC_VER_MINOR);
529 printf("fsl-mc: Management Complex booted (version: %d.%d.%d, boot status: %#x)\n",
530 mc_ver_info.major, mc_ver_info.minor, mc_ver_info.revision,
531 reg_gsr & GSR_FS_MASK);
534 * Tell the MC to deploy the DPL:
536 out_le32(&mc_ccsr_regs->reg_gsr, 0x0);
537 printf("fsl-mc: Deploying data path layout ... ");
538 error = wait_for_mc(false, ®_gsr);
544 mc_boot_status = -error;
551 int get_mc_boot_status(void)
553 return mc_boot_status;
557 * Return the actual size of the MC private DRAM block.
559 unsigned long mc_get_dram_block_size(void)
561 unsigned long dram_block_size = CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE;
563 char *dram_block_size_env_var = getenv(MC_MEM_SIZE_ENV_VAR);
565 if (dram_block_size_env_var) {
566 dram_block_size = simple_strtoul(dram_block_size_env_var, NULL,
569 if (dram_block_size < CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE) {
570 printf("fsl-mc: WARNING: Invalid value for \'"
572 "\' environment variable: %lu\n",
575 dram_block_size = CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE;
579 return dram_block_size;
582 int dpio_init(struct dprc_obj_desc obj_desc)
584 struct qbman_swp_desc p_des;
585 struct dpio_attr attr;
588 dflt_dpio = (struct fsl_dpio_obj *)malloc(sizeof(struct fsl_dpio_obj));
590 printf(" No memory: malloc() failed\n");
594 dflt_dpio->dpio_id = obj_desc.id;
596 err = dpio_open(dflt_mc_io, obj_desc.id, &dflt_dpio_handle);
598 printf("dpio_open() failed\n");
602 err = dpio_get_attributes(dflt_mc_io, dflt_dpio_handle, &attr);
604 printf("dpio_get_attributes() failed %d\n", err);
608 err = dpio_enable(dflt_mc_io, dflt_dpio_handle);
610 printf("dpio_enable() failed %d\n", err);
613 debug("ce_offset=0x%llx, ci_offset=0x%llx, portalid=%d, prios=%d\n",
614 attr.qbman_portal_ce_offset,
615 attr.qbman_portal_ci_offset,
616 attr.qbman_portal_id,
617 attr.num_priorities);
619 p_des.cena_bar = (void *)(SOC_QBMAN_PORTALS_BASE_ADDR
620 + attr.qbman_portal_ce_offset);
621 p_des.cinh_bar = (void *)(SOC_QBMAN_PORTALS_BASE_ADDR
622 + attr.qbman_portal_ci_offset);
624 dflt_dpio->sw_portal = qbman_swp_init(&p_des);
625 if (dflt_dpio->sw_portal == NULL) {
626 printf("qbman_swp_init() failed\n");
627 goto err_get_swp_init;
633 dpio_disable(dflt_mc_io, dflt_dpio_handle);
635 dpio_close(dflt_mc_io, dflt_dpio_handle);
641 int dpbp_init(struct dprc_obj_desc obj_desc)
643 dflt_dpbp = (struct fsl_dpbp_obj *)malloc(sizeof(struct fsl_dpbp_obj));
645 printf(" No memory: malloc() failed\n");
648 dflt_dpbp->dpbp_attr.id = obj_desc.id;
653 int dprc_init_container_obj(struct dprc_obj_desc obj_desc, uint16_t dprc_handle)
655 int error = 0, state = 0;
656 struct dprc_endpoint dpni_endpoint, dpmac_endpoint;
657 if (!strcmp(obj_desc.type, "dpbp")) {
659 error = dpbp_init(obj_desc);
661 printf("dpbp_init failed\n");
663 } else if (!strcmp(obj_desc.type, "dpio")) {
665 error = dpio_init(obj_desc);
667 printf("dpio_init failed\n");
669 } else if (!strcmp(obj_desc.type, "dpni")) {
670 strcpy(dpni_endpoint.type, obj_desc.type);
671 dpni_endpoint.id = obj_desc.id;
672 error = dprc_get_connection(dflt_mc_io, dprc_handle,
673 &dpni_endpoint, &dpmac_endpoint, &state);
674 if (!strcmp(dpmac_endpoint.type, "dpmac"))
675 error = ldpaa_eth_init(obj_desc);
677 printf("ldpaa_eth_init failed\n");
683 int dprc_scan_container_obj(uint16_t dprc_handle, char *obj_type, int i)
686 struct dprc_obj_desc obj_desc;
688 memset((void *)&obj_desc, 0x00, sizeof(struct dprc_obj_desc));
690 error = dprc_get_obj(dflt_mc_io, dprc_handle,
693 printf("dprc_get_obj(i=%d) failed: %d\n",
698 if (!strcmp(obj_desc.type, obj_type)) {
699 debug("Discovered object: type %s, id %d, req %s\n",
700 obj_desc.type, obj_desc.id, obj_type);
702 error = dprc_init_container_obj(obj_desc, dprc_handle);
704 printf("dprc_init_container_obj(i=%d) failed: %d\n",
713 int fsl_mc_ldpaa_init(bd_t *bis)
716 int dprc_opened = 0, container_id;
717 int num_child_objects = 0;
723 error = dprc_get_container_id(dflt_mc_io, &container_id);
725 printf("dprc_get_container_id() failed: %d\n", error);
729 debug("fsl-mc: Container id=0x%x\n", container_id);
731 error = dprc_open(dflt_mc_io, container_id, &dflt_dprc_handle);
733 printf("dprc_open() failed: %d\n", error);
738 error = dprc_get_obj_count(dflt_mc_io,
742 printf("dprc_get_obj_count() failed: %d\n", error);
745 debug("Total child in container %d = %d\n", container_id,
748 if (num_child_objects != 0) {
750 * Discover objects currently in the DPRC container in the MC:
752 for (i = 0; i < num_child_objects; i++)
753 error = dprc_scan_container_obj(dflt_dprc_handle,
756 for (i = 0; i < num_child_objects; i++)
757 error = dprc_scan_container_obj(dflt_dprc_handle,
760 for (i = 0; i < num_child_objects; i++)
761 error = dprc_scan_container_obj(dflt_dprc_handle,
766 dprc_close(dflt_mc_io, dflt_dprc_handle);
771 void fsl_mc_ldpaa_exit(bd_t *bis)
775 if (get_mc_boot_status() == 0) {
776 err = dpio_disable(dflt_mc_io, dflt_dpio_handle);
778 printf("dpio_disable() failed: %d\n", err);
781 err = dpio_reset(dflt_mc_io, dflt_dpio_handle);
783 printf("dpio_reset() failed: %d\n", err);
786 err = dpio_close(dflt_mc_io, dflt_dpio_handle);
788 printf("dpio_close() failed: %d\n", err);