2 * Common structures and definitions for FT1000 Flarion Flash OFDM PCMCIA and
5 * Originally copyright (c) 2002 Flarion Technologies
17 #define ELECTRABUZZ_ID 0 /* ASIC ID for Electrabuzz */
18 #define MAGNEMITE_ID 0x1a01 /* ASIC ID for Magnemite */
20 /* MEMORY MAP common to both ELECTRABUZZ and MAGNEMITE */
21 #define FT1000_REG_DPRAM_ADDR 0x000E /* DPADR - Dual Port Ram Indirect
24 #define FT1000_REG_SUP_CTRL 0x0020 /* HCTR - Host Control Register */
25 #define FT1000_REG_SUP_STAT 0x0022 /* HSTAT - Host Status Register */
26 #define FT1000_REG_RESET 0x0024 /* HCTR - Host Control Register */
27 #define FT1000_REG_SUP_ISR 0x0026 /* HISR - Host Interrupt Status
30 #define FT1000_REG_SUP_IMASK 0x0028 /* HIMASK - Host Interrupt Mask */
31 #define FT1000_REG_DOORBELL 0x002a /* DBELL - Door Bell Register */
32 #define FT1000_REG_ASIC_ID 0x002e /* ASICID - ASIC Identification
36 /* MEMORY MAP FOR ELECTRABUZZ ASIC */
37 #define FT1000_REG_UFIFO_STAT 0x0000 /* UFSR - Uplink FIFO status register */
38 #define FT1000_REG_UFIFO_BEG 0x0002 /* UFBR - Uplink FIFO beginning
41 #define FT1000_REG_UFIFO_MID 0x0004 /* UFMR - Uplink FIFO middle register */
42 #define FT1000_REG_UFIFO_END 0x0006 /* UFER - Uplink FIFO end register */
43 #define FT1000_REG_DFIFO_STAT 0x0008 /* DFSR - Downlink FIFO status
46 #define FT1000_REG_DFIFO 0x000A /* DFR - Downlink FIFO Register */
47 #define FT1000_REG_DPRAM_DATA 0x000C /* DPRAM - Dual Port Indirect
50 #define FT1000_REG_WATERMARK 0x0010 /* WMARK - Watermark Register */
52 /* MEMORY MAP FOR MAGNEMITE */
53 #define FT1000_REG_MAG_UFDR 0x0000 /* UFDR - Uplink FIFO Data
56 #define FT1000_REG_MAG_UFDRL 0x0000 /* UFDRL - Uplink FIFO Data
57 * Register low-word (16-bits)
59 #define FT1000_REG_MAG_UFDRH 0x0002 /* UFDRH - Uplink FIFO Data Register
62 #define FT1000_REG_MAG_UFER 0x0004 /* UFER - Uplink FIFO End Register */
63 #define FT1000_REG_MAG_UFSR 0x0006 /* UFSR - Uplink FIFO Status Register */
64 #define FT1000_REG_MAG_DFR 0x0008 /* DFR - Downlink FIFO Register
67 #define FT1000_REG_MAG_DFRL 0x0008 /* DFRL - Downlink FIFO Register
70 #define FT1000_REG_MAG_DFRH 0x000a /* DFRH - Downlink FIFO Register
73 #define FT1000_REG_MAG_DFSR 0x000c /* DFSR - Downlink FIFO Status
76 #define FT1000_REG_MAG_DPDATA 0x0010 /* DPDATA - Dual Port RAM Indirect
77 * Data Register (32-bits)
79 #define FT1000_REG_MAG_DPDATAL 0x0010 /* DPDATAL - Dual Port RAM Indirect
80 * Data Register low-word (16-bits)
82 #define FT1000_REG_MAG_DPDATAH 0x0012 /* DPDATAH - Dual Port RAM Indirect Data
83 * Register high-word (16-bits)
85 #define FT1000_REG_MAG_WATERMARK 0x002c /* WMARK - Watermark Register */
86 #define FT1000_REG_MAG_VERSION 0x0030 /* LLC Version */
88 /* Reserved Dual Port RAM offsets for Electrabuzz */
89 #define FT1000_DPRAM_TX_BASE 0x0002 /* Host to PC Card Messaging Area */
90 #define FT1000_DPRAM_RX_BASE 0x0800 /* PC Card to Host Messaging Area */
91 #define FT1000_FIFO_LEN 0x07FC /* total length for DSP FIFO tracking */
92 #define FT1000_HI_HO 0x07FE /* heartbeat with HI/HO */
93 #define FT1000_DSP_STATUS 0x0FFE /* dsp status - non-zero is a request
96 #define FT1000_DSP_LED 0x0FFA /* dsp led status for PAD device */
97 #define FT1000_DSP_CON_STATE 0x0FF8 /* DSP Connection Status Info */
98 #define FT1000_DPRAM_FEFE 0x0002 /* location for dsp ready indicator */
99 #define FT1000_DSP_TIMER0 0x1FF0 /* Timer Field from Basestation */
100 #define FT1000_DSP_TIMER1 0x1FF2 /* Timer Field from Basestation */
101 #define FT1000_DSP_TIMER2 0x1FF4 /* Timer Field from Basestation */
102 #define FT1000_DSP_TIMER3 0x1FF6 /* Timer Field from Basestation */
104 /* Reserved Dual Port RAM offsets for Magnemite */
105 #define FT1000_DPRAM_MAG_TX_BASE 0x0000 /* Host to PC Card
108 #define FT1000_DPRAM_MAG_RX_BASE 0x0200 /* PC Card to Host
112 #define FT1000_MAG_FIFO_LEN 0x1FF /* total length for DSP
115 #define FT1000_MAG_FIFO_LEN_INDX 0x1 /* low-word index */
116 #define FT1000_MAG_HI_HO 0x1FF /* heartbeat with HI/HO */
117 #define FT1000_MAG_HI_HO_INDX 0x0 /* high-word index */
118 #define FT1000_MAG_DSP_LED 0x3FE /* dsp led status for
121 #define FT1000_MAG_DSP_LED_INDX 0x0 /* dsp led status for
124 #define FT1000_MAG_DSP_CON_STATE 0x3FE /* DSP Connection Status Info */
125 #define FT1000_MAG_DSP_CON_STATE_INDX 0x1 /* DSP Connection Status Info */
126 #define FT1000_MAG_DPRAM_FEFE 0x000 /* location for dsp ready
129 #define FT1000_MAG_DPRAM_FEFE_INDX 0x0 /* location for dsp ready
132 #define FT1000_MAG_DSP_TIMER0 0x3FC /* Timer Field from
135 #define FT1000_MAG_DSP_TIMER0_INDX 0x1
136 #define FT1000_MAG_DSP_TIMER1 0x3FC /* Timer Field from
139 #define FT1000_MAG_DSP_TIMER1_INDX 0x0
140 #define FT1000_MAG_DSP_TIMER2 0x3FD /* Timer Field from
143 #define FT1000_MAG_DSP_TIMER2_INDX 0x1
144 #define FT1000_MAG_DSP_TIMER3 0x3FD /* Timer Field from
147 #define FT1000_MAG_DSP_TIMER3_INDX 0x0
148 #define FT1000_MAG_TOTAL_LEN 0x200
149 #define FT1000_MAG_TOTAL_LEN_INDX 0x1
150 #define FT1000_MAG_PH_LEN 0x200
151 #define FT1000_MAG_PH_LEN_INDX 0x0
152 #define FT1000_MAG_PORT_ID 0x201
153 #define FT1000_MAG_PORT_ID_INDX 0x0
155 #define HOST_INTF_LE 0x0 /* Host interface little endian mode */
156 #define HOST_INTF_BE 0x1 /* Host interface big endian mode */
158 /* FT1000 to Host Doorbell assignments */
159 #define FT1000_DB_DPRAM_RX 0x0001 /* this value indicates that DSP
160 * has data for host in DPRAM
162 #define FT1000_DB_DNLD_RX 0x0002 /* Downloader handshake doorbell */
163 #define FT1000_ASIC_RESET_REQ 0x0004 /* DSP requesting host to
166 #define FT1000_DSP_ASIC_RESET 0x0008 /* DSP indicating host that
167 * it will reset the ASIC
169 #define FT1000_DB_COND_RESET 0x0010 /* DSP request for a card reset. */
171 /* Host to FT1000 Doorbell assignments */
172 #define FT1000_DB_DPRAM_TX 0x0100 /* this value indicates that host
173 * has data for DSP in DPRAM.
175 #define FT1000_DB_DNLD_TX 0x0200 /* Downloader handshake doorbell */
176 #define FT1000_ASIC_RESET_DSP 0x0400 /* Responds to FT1000_ASIC_RESET_REQ */
177 #define FT1000_DB_HB 0x1000 /* Indicates that supervisor has a
178 * heartbeat message for DSP.
181 #define hi 0x6869 /* PC Card heartbeat values */
182 #define ho 0x686f /* PC Card heartbeat values */
184 /* Magnemite specific defines */
185 #define hi_mag 0x6968 /* Byte swap hi to avoid
186 * additional system call
188 #define ho_mag 0x6f68 /* Byte swap ho to avoid
189 * additional system call
192 /* Bit field definitions for Host Interrupt Status Register */
193 /* Indicate the cause of an interrupt. */
194 #define ISR_EMPTY 0x00 /* no bits set */
195 #define ISR_DOORBELL_ACK 0x01 /* Doorbell acknowledge from DSP */
196 #define ISR_DOORBELL_PEND 0x02 /* Doorbell pending from DSP */
197 #define ISR_RCV 0x04 /* Packet available in Downlink FIFO */
198 #define ISR_WATERMARK 0x08 /* Watermark requirements satisfied */
200 /* Bit field definition for Host Interrupt Mask */
201 #define ISR_MASK_NONE 0x0000 /* no bits set */
202 #define ISR_MASK_DOORBELL_ACK 0x0001 /* Doorbell acknowledge mask */
203 #define ISR_MASK_DOORBELL_PEND 0x0002 /* Doorbell pending mask */
204 #define ISR_MASK_RCV 0x0004 /* Downlink Packet available mask */
205 #define ISR_MASK_WATERMARK 0x0008 /* Watermark interrupt mask */
206 #define ISR_MASK_ALL 0xffff /* Mask all interrupts */
207 /* Default interrupt mask
208 * (Enable Doorbell pending and Packet available interrupts)
210 #define ISR_DEFAULT_MASK 0x7ff9
212 /* Bit field definition for Host Control Register */
213 #define DSP_RESET_BIT 0x0001 /* Bit field to control
216 /* (0 = out of reset 1 = reset) */
217 #define ASIC_RESET_BIT 0x0002 /* Bit field to control
220 /* (0 = out of reset 1 = reset) */
221 #define DSP_UNENCRYPTED 0x0004
222 #define DSP_ENCRYPTED 0x0008
223 #define EFUSE_MEM_DISABLE 0x0040
225 /* Application specific IDs */
228 #define DSPAIRID 0x90
229 #define DRIVERID 0x00
230 #define NETWORKID 0x20
232 /* Size of DPRAM Message */
233 #define MAX_CMD_SQSIZE 1780
235 #define ENET_MAX_SIZE 1514
236 #define ENET_HEADER_SIZE 14
241 #define MAX_DSP_SESS_REC 1024
243 #define DSP_QID_OFFSET 4
245 /* Driver message types */
246 #define MEDIA_STATE 0x0010
247 #define TIME_UPDATE 0x0020
248 #define DSP_PROVISION 0x0030
249 #define DSP_INIT_MSG 0x0050
250 #define DSP_HIBERNATE 0x0060
251 #define DSP_STORE_INFO 0x0070
252 #define DSP_GET_INFO 0x0071
253 #define GET_DRV_ERR_RPT_MSG 0x0073
254 #define RSP_DRV_ERR_RPT_MSG 0x0074
256 /* Driver Error Messages for DSP */
257 #define DSP_HB_INFO 0x7ef0
258 #define DSP_FIFO_INFO 0x7ef1
259 #define DSP_CONDRESET_INFO 0x7ef2
260 #define DSP_CMDLEN_INFO 0x7ef3
261 #define DSP_CMDPHCKSUM_INFO 0x7ef4
262 #define DSP_PKTPHCKSUM_INFO 0x7ef5
263 #define DSP_PKTLEN_INFO 0x7ef6
264 #define DSP_USER_RESET 0x7ef7
265 #define FIFO_FLUSH_MAXLIMIT 0x7ef8
266 #define FIFO_FLUSH_BADCNT 0x7ef9
267 #define FIFO_ZERO_LEN 0x7efa
269 /* Pseudo Header structure */
271 unsigned short length; /* length of msg body */
272 unsigned char source; /* hardware source id */
275 unsigned char destination; /* hardware destination id
278 unsigned char portdest; /* software destination port id */
280 /* Applicaton Broadcast = 0x10 */
281 /* Network Stack = 0x20 */
283 /* Dsp Airlink = 0x90 */
284 /* Dsp Loader = 0xa0 */
286 unsigned char portsrc; /* software source port id
287 * (refer to portdest)
289 unsigned short sh_str_id; /* not used */
290 unsigned char control; /* not used */
292 unsigned char seq_num; /* message sequence number */
294 unsigned short qos_class; /* not used */
295 unsigned short checksum; /* pseudo header checksum */
299 struct pseudo_hdr pseudo;
306 struct pseudo_hdr pseudo;
317 struct dsp_init_msg {
318 struct pseudo_hdr pseudo;
321 u8 DspVer[DSPVERSZ]; /* DSP version number */
322 u8 HwSerNum[HWSERNUMSZ]; /* Hardware Serial Number */
323 u8 Sku[SKUSZ]; /* SKU */
324 u8 eui64[EUISZ]; /* EUI64 */
325 u8 ProductMode[MODESZ]; /* Product Mode (Market/Production) */
326 u8 RfCalVer[CALVERSZ]; /* Rf Calibration version */
327 u8 RfCalDate[CALDATESZ]; /* Rf Calibration date */
331 struct list_head list;
337 struct net_device_stats stats;
343 u8 squeseqnum; /* sequence number on slow queue */
344 spinlock_t dpram_lock;
346 u8 DspVer[DSPVERSZ]; /* DSP version number */
347 u8 HwSerNum[HWSERNUMSZ]; /* Hardware Serial Number */
348 u8 Sku[SKUSZ]; /* SKU */
349 u8 eui64[EUISZ]; /* EUI64 */
350 time_t ConTm; /* Connection Time */
351 u8 ProductMode[MODESZ];
352 u8 RfCalVer[CALVERSZ];
353 u8 RfCalDate[CALDATESZ];
358 struct list_head prov_list;
360 int (*ft1000_reset)(void *);
361 u16 DSPInfoBlk[MAX_DSP_SESS_REC];
363 u16 Rec[MAX_DSP_SESS_REC];
364 u32 MagRec[MAX_DSP_SESS_REC/2];