1 #ifndef _ASM_POWERPC_PCI_BRIDGE_H
2 #define _ASM_POWERPC_PCI_BRIDGE_H
6 #include <linux/ioport.h>
10 struct pci_controller;
13 * pci_io_base returns the memory address at which you can access
14 * the I/O space for PCI bus number `bus' (or NULL on error).
16 extern void __iomem *pci_bus_io_base(unsigned int bus);
17 extern unsigned long pci_bus_io_base_phys(unsigned int bus);
18 extern unsigned long pci_bus_mem_base_phys(unsigned int bus);
20 /* Allocate a new PCI host bridge structure */
21 extern struct pci_controller* pcibios_alloc_controller(void);
23 /* Helper function for setting up resources */
24 extern void pci_init_resource(struct resource *res, resource_size_t start,
25 resource_size_t end, int flags, char *name);
27 /* Get the PCI host controller for a bus */
28 extern struct pci_controller* pci_bus_to_hose(int bus);
31 * Structure of a PCI controller (host bridge)
33 struct pci_controller {
36 int index; /* PCI domain number */
37 struct pci_controller *next;
38 struct device *parent;
44 void __iomem *io_base_virt;
45 resource_size_t io_base_phys;
47 /* Some machines (PReP) have a non 1:1 mapping of
48 * the PCI memory space in the CPU bus space
50 resource_size_t pci_mem_offset;
53 volatile unsigned int __iomem *cfg_addr;
54 volatile void __iomem *cfg_data;
57 * Used for variants of PCI indirect handling and possible quirks:
58 * SET_CFG_TYPE - used on 4xx or any PHB that does explicit type0/1
59 * EXT_REG - provides access to PCI-e extended registers
60 * SURPRESS_PRIMARY_BUS - we surpress the setting of PCI_PRIMARY_BUS
61 * on Freescale PCI-e controllers since they used the PCI_PRIMARY_BUS
62 * to determine which bus number to match on when generating type0
65 #define PPC_INDIRECT_TYPE_SET_CFG_TYPE (0x00000001)
66 #define PPC_INDIRECT_TYPE_EXT_REG (0x00000002)
67 #define PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS (0x00000004)
70 /* Currently, we limit ourselves to 1 IO range and 3 mem
71 * ranges since the common pci_bus structure can't handle more
73 struct resource io_resource;
74 struct resource mem_resources[3];
77 static inline struct pci_controller *pci_bus_to_host(struct pci_bus *bus)
82 /* These are used for config access before all the PCI probing
84 int early_read_config_byte(struct pci_controller *hose, int bus, int dev_fn,
86 int early_read_config_word(struct pci_controller *hose, int bus, int dev_fn,
88 int early_read_config_dword(struct pci_controller *hose, int bus, int dev_fn,
90 int early_write_config_byte(struct pci_controller *hose, int bus, int dev_fn,
92 int early_write_config_word(struct pci_controller *hose, int bus, int dev_fn,
94 int early_write_config_dword(struct pci_controller *hose, int bus, int dev_fn,
97 extern void setup_indirect_pci_nomap(struct pci_controller* hose,
98 void __iomem *cfg_addr, void __iomem *cfg_data);
99 extern void setup_indirect_pci(struct pci_controller* hose,
100 u32 cfg_addr, u32 cfg_data);
101 extern void setup_grackle(struct pci_controller *hose);
105 #include <linux/pci.h>
106 #include <linux/list.h>
109 * This program is free software; you can redistribute it and/or
110 * modify it under the terms of the GNU General Public License
111 * as published by the Free Software Foundation; either version
112 * 2 of the License, or (at your option) any later version.
116 * Structure of a PCI controller (host bridge)
118 struct pci_controller {
123 struct list_head list_node;
124 struct device *parent;
129 void __iomem *io_base_virt;
131 resource_size_t io_base_phys;
133 /* Some machines have a non 1:1 mapping of
134 * the PCI memory space in the CPU bus space
136 resource_size_t pci_mem_offset;
137 unsigned long pci_io_size;
140 volatile unsigned int __iomem *cfg_addr;
141 volatile void __iomem *cfg_data;
143 /* Currently, we limit ourselves to 1 IO range and 3 mem
144 * ranges since the common pci_bus structure can't handle more
146 struct resource io_resource;
147 struct resource mem_resources[3];
151 unsigned long dma_window_base_cur;
152 unsigned long dma_window_size;
158 * PCI stuff, for nodes representing PCI devices, pointed to
159 * by device_node->data.
161 struct pci_controller;
165 int busno; /* pci bus number */
166 int bussubno; /* pci subordinate bus number */
167 int devfn; /* pci device and function number */
168 int class_code; /* pci device class */
170 struct pci_controller *phb; /* for pci devices */
171 struct iommu_table *iommu_table; /* for phb's or bridges */
172 struct pci_dev *pcidev; /* back-pointer to the pci device */
173 struct device_node *node; /* back-pointer to the device_node */
175 int pci_ext_config_space; /* for pci devices */
178 int eeh_mode; /* See eeh.h for possible EEH_MODEs */
180 int eeh_pe_config_addr; /* new-style partition endpoint address */
181 int eeh_check_count; /* # times driver ignored error */
182 int eeh_freeze_count; /* # times this device froze up. */
183 int eeh_false_positives; /* # times this device reported #ff's */
184 u32 config_space[16]; /* saved PCI config space */
188 /* Get the pointer to a device_node's pci_dn */
189 #define PCI_DN(dn) ((struct pci_dn *) (dn)->data)
191 struct device_node *fetch_dev_dn(struct pci_dev *dev);
193 /* Get a device_node from a pci_dev. This code must be fast except
194 * in the case where the sysdata is incorrect and needs to be fixed
195 * up (this will only happen once).
196 * In this case the sysdata will have been inherited from a PCI host
197 * bridge or a PCI-PCI bridge further up the tree, so it will point
198 * to a valid struct pci_dn, just not the one we want.
200 static inline struct device_node *pci_device_to_OF_node(struct pci_dev *dev)
202 struct device_node *dn = dev->sysdata;
203 struct pci_dn *pdn = dn->data;
205 if (pdn && pdn->devfn == dev->devfn && pdn->busno == dev->bus->number)
206 return dn; /* fast path. sysdata is good */
207 return fetch_dev_dn(dev);
210 static inline int pci_device_from_OF_node(struct device_node *np,
215 *bus = PCI_DN(np)->busno;
216 *devfn = PCI_DN(np)->devfn;
220 static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus)
223 return pci_device_to_OF_node(bus->self);
225 return bus->sysdata; /* Must be root bus (PHB) */
228 /** Find the bus corresponding to the indicated device node */
229 struct pci_bus * pcibios_find_pci_bus(struct device_node *dn);
231 /** Remove all of the PCI devices under this bus */
232 void pcibios_remove_pci_devices(struct pci_bus *bus);
234 /** Discover new pci devices under this bus, and add them */
235 void pcibios_add_pci_devices(struct pci_bus * bus);
236 void pcibios_fixup_new_pci_devices(struct pci_bus *bus, int fix_bus);
238 extern int pcibios_remove_root_bus(struct pci_controller *phb);
240 static inline struct pci_controller *pci_bus_to_host(struct pci_bus *bus)
242 struct device_node *busdn = bus->sysdata;
244 BUG_ON(busdn == NULL);
245 return PCI_DN(busdn)->phb;
248 extern struct pci_controller *
249 pcibios_alloc_controller(struct device_node *dev);
250 extern void pcibios_free_controller(struct pci_controller *phb);
252 extern void isa_bridge_find_early(struct pci_controller *hose);
254 extern int pcibios_unmap_io_space(struct pci_bus *bus);
255 extern int pcibios_map_io_space(struct pci_bus *bus);
257 /* Return values for ppc_md.pci_probe_mode function */
258 #define PCI_PROBE_NONE -1 /* Don't look at this bus at all */
259 #define PCI_PROBE_NORMAL 0 /* Do normal PCI probing */
260 #define PCI_PROBE_DEVTREE 1 /* Instantiate from device tree */
263 #define PHB_SET_NODE(PHB, NODE) ((PHB)->node = (NODE))
265 #define PHB_SET_NODE(PHB, NODE) ((PHB)->node = -1)
268 #endif /* CONFIG_PPC64 */
270 /* Get the PCI host controller for an OF device */
271 extern struct pci_controller*
272 pci_find_hose_for_OF_device(struct device_node* node);
274 /* Fill up host controller resources from the OF node */
276 pci_process_bridge_OF_ranges(struct pci_controller *hose,
277 struct device_node *dev, int primary);
280 extern unsigned long pci_address_to_pio(phys_addr_t address);
282 static inline unsigned long pci_address_to_pio(phys_addr_t address)
284 return (unsigned long)-1;
290 #endif /* __KERNEL__ */