1 #ifndef _ASM_POWERPC_PCI_BRIDGE_H
2 #define _ASM_POWERPC_PCI_BRIDGE_H
6 #include <linux/ioport.h>
10 struct pci_controller;
12 /* Get the PCI host controller for a bus */
13 extern struct pci_controller* pci_bus_to_hose(int bus);
16 * Structure of a PCI controller (host bridge)
18 struct pci_controller {
21 struct pci_controller *next;
22 struct device *parent;
28 void __iomem *io_base_virt;
29 resource_size_t io_base_phys;
31 /* Some machines (PReP) have a non 1:1 mapping of
32 * the PCI memory space in the CPU bus space
34 resource_size_t pci_mem_offset;
37 volatile unsigned int __iomem *cfg_addr;
38 volatile void __iomem *cfg_data;
41 * Used for variants of PCI indirect handling and possible quirks:
42 * SET_CFG_TYPE - used on 4xx or any PHB that does explicit type0/1
43 * EXT_REG - provides access to PCI-e extended registers
44 * SURPRESS_PRIMARY_BUS - we surpress the setting of PCI_PRIMARY_BUS
45 * on Freescale PCI-e controllers since they used the PCI_PRIMARY_BUS
46 * to determine which bus number to match on when generating type0
49 #define PPC_INDIRECT_TYPE_SET_CFG_TYPE (0x00000001)
50 #define PPC_INDIRECT_TYPE_EXT_REG (0x00000002)
51 #define PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS (0x00000004)
54 /* Currently, we limit ourselves to 1 IO range and 3 mem
55 * ranges since the common pci_bus structure can't handle more
57 struct resource io_resource;
58 struct resource mem_resources[3];
59 int global_number; /* PCI domain number */
62 static inline struct pci_controller *pci_bus_to_host(struct pci_bus *bus)
67 /* These are used for config access before all the PCI probing
69 int early_read_config_byte(struct pci_controller *hose, int bus, int dev_fn,
71 int early_read_config_word(struct pci_controller *hose, int bus, int dev_fn,
73 int early_read_config_dword(struct pci_controller *hose, int bus, int dev_fn,
75 int early_write_config_byte(struct pci_controller *hose, int bus, int dev_fn,
77 int early_write_config_word(struct pci_controller *hose, int bus, int dev_fn,
79 int early_write_config_dword(struct pci_controller *hose, int bus, int dev_fn,
82 extern void setup_indirect_pci_nomap(struct pci_controller* hose,
83 void __iomem *cfg_addr, void __iomem *cfg_data);
84 extern void setup_indirect_pci(struct pci_controller* hose,
85 u32 cfg_addr, u32 cfg_data);
86 extern void setup_grackle(struct pci_controller *hose);
90 #include <linux/pci.h>
91 #include <linux/list.h>
94 * This program is free software; you can redistribute it and/or
95 * modify it under the terms of the GNU General Public License
96 * as published by the Free Software Foundation; either version
97 * 2 of the License, or (at your option) any later version.
101 * Structure of a PCI controller (host bridge)
103 struct pci_controller {
108 struct list_head list_node;
109 struct device *parent;
114 void __iomem *io_base_virt;
116 resource_size_t io_base_phys;
118 /* Some machines have a non 1:1 mapping of
119 * the PCI memory space in the CPU bus space
121 resource_size_t pci_mem_offset;
122 unsigned long pci_io_size;
125 volatile unsigned int __iomem *cfg_addr;
126 volatile void __iomem *cfg_data;
128 /* Currently, we limit ourselves to 1 IO range and 3 mem
129 * ranges since the common pci_bus structure can't handle more
131 struct resource io_resource;
132 struct resource mem_resources[3];
135 unsigned long dma_window_base_cur;
136 unsigned long dma_window_size;
142 * PCI stuff, for nodes representing PCI devices, pointed to
143 * by device_node->data.
145 struct pci_controller;
149 int busno; /* pci bus number */
150 int bussubno; /* pci subordinate bus number */
151 int devfn; /* pci device and function number */
152 int class_code; /* pci device class */
154 struct pci_controller *phb; /* for pci devices */
155 struct iommu_table *iommu_table; /* for phb's or bridges */
156 struct pci_dev *pcidev; /* back-pointer to the pci device */
157 struct device_node *node; /* back-pointer to the device_node */
159 int pci_ext_config_space; /* for pci devices */
162 int eeh_mode; /* See eeh.h for possible EEH_MODEs */
164 int eeh_pe_config_addr; /* new-style partition endpoint address */
165 int eeh_check_count; /* # times driver ignored error */
166 int eeh_freeze_count; /* # times this device froze up. */
167 int eeh_false_positives; /* # times this device reported #ff's */
168 u32 config_space[16]; /* saved PCI config space */
172 /* Get the pointer to a device_node's pci_dn */
173 #define PCI_DN(dn) ((struct pci_dn *) (dn)->data)
175 struct device_node *fetch_dev_dn(struct pci_dev *dev);
177 /* Get a device_node from a pci_dev. This code must be fast except
178 * in the case where the sysdata is incorrect and needs to be fixed
179 * up (this will only happen once).
180 * In this case the sysdata will have been inherited from a PCI host
181 * bridge or a PCI-PCI bridge further up the tree, so it will point
182 * to a valid struct pci_dn, just not the one we want.
184 static inline struct device_node *pci_device_to_OF_node(struct pci_dev *dev)
186 struct device_node *dn = dev->sysdata;
187 struct pci_dn *pdn = dn->data;
189 if (pdn && pdn->devfn == dev->devfn && pdn->busno == dev->bus->number)
190 return dn; /* fast path. sysdata is good */
191 return fetch_dev_dn(dev);
194 static inline int pci_device_from_OF_node(struct device_node *np,
199 *bus = PCI_DN(np)->busno;
200 *devfn = PCI_DN(np)->devfn;
204 static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus)
207 return pci_device_to_OF_node(bus->self);
209 return bus->sysdata; /* Must be root bus (PHB) */
212 /** Find the bus corresponding to the indicated device node */
213 struct pci_bus * pcibios_find_pci_bus(struct device_node *dn);
215 /** Remove all of the PCI devices under this bus */
216 void pcibios_remove_pci_devices(struct pci_bus *bus);
218 /** Discover new pci devices under this bus, and add them */
219 void pcibios_add_pci_devices(struct pci_bus * bus);
220 void pcibios_fixup_new_pci_devices(struct pci_bus *bus, int fix_bus);
222 extern int pcibios_remove_root_bus(struct pci_controller *phb);
224 static inline struct pci_controller *pci_bus_to_host(struct pci_bus *bus)
226 struct device_node *busdn = bus->sysdata;
228 BUG_ON(busdn == NULL);
229 return PCI_DN(busdn)->phb;
232 extern void pcibios_free_controller(struct pci_controller *phb);
234 extern void isa_bridge_find_early(struct pci_controller *hose);
236 extern int pcibios_unmap_io_space(struct pci_bus *bus);
237 extern int pcibios_map_io_space(struct pci_bus *bus);
239 /* Return values for ppc_md.pci_probe_mode function */
240 #define PCI_PROBE_NONE -1 /* Don't look at this bus at all */
241 #define PCI_PROBE_NORMAL 0 /* Do normal PCI probing */
242 #define PCI_PROBE_DEVTREE 1 /* Instantiate from device tree */
245 #define PHB_SET_NODE(PHB, NODE) ((PHB)->node = (NODE))
247 #define PHB_SET_NODE(PHB, NODE) ((PHB)->node = -1)
250 #endif /* CONFIG_PPC64 */
252 /* Get the PCI host controller for an OF device */
253 extern struct pci_controller*
254 pci_find_hose_for_OF_device(struct device_node* node);
256 /* Fill up host controller resources from the OF node */
258 pci_process_bridge_OF_ranges(struct pci_controller *hose,
259 struct device_node *dev, int primary);
261 /* Allocate a new PCI host bridge structure */
262 extern struct pci_controller *
263 pcibios_alloc_controller(struct device_node *dev);
265 extern unsigned long pci_address_to_pio(phys_addr_t address);
267 static inline unsigned long pci_address_to_pio(phys_addr_t address)
269 return (unsigned long)-1;
275 #endif /* __KERNEL__ */